fp1m1 = regInfo{inputs: fponly, outputs: maskonly}
m1fp1 = regInfo{inputs: maskonly, outputs: fponly}
fp2m1 = regInfo{inputs: []regMask{fp, fp}, outputs: maskonly}
+ fp1m1fp1 = regInfo{inputs: []regMask{fp, mask}, outputs: fponly}
fp2m1fp1 = regInfo{inputs: []regMask{fp, fp, mask}, outputs: fponly}
fp2m1m1 = regInfo{inputs: []regMask{fp, fp, mask}, outputs: maskonly}
pkg: "cmd/internal/obj/x86",
genfile: "../../amd64/ssa.go",
genSIMDfile: "../../amd64/simdssa.go",
- ops: append(AMD64ops, simdAMD64Ops(fp11, fp21, fp2m1, fp2m1fp1, fp2m1m1)...), // AMD64ops,
+ ops: append(AMD64ops, simdAMD64Ops(fp11, fp21, fp2m1, fp1m1fp1, fp2m1fp1, fp2m1m1)...), // AMD64ops,
blocks: AMD64blocks,
regnames: regNamesAMD64,
ParamIntRegNames: "AX BX CX DI SI R8 R9 R10 R11",
package main
-func simdAMD64Ops(fp11, fp21, fp2m1, fp2m1fp1, fp2m1m1 regInfo) []opData {
+func simdAMD64Ops(fp11, fp21, fp2m1, fp1m1fp1, fp2m1fp1, fp2m1m1 regInfo) []opData {
return []opData{
// {name: "VPADDB", argLength: 2, reg: fp21, asm: "VPADDB", commutative: true},
// etc, generated