cmd/compile: simplify slice/array range loops on loong64

loong64 supports R+R addressing ({st,ld}x.{b,h,w,d} instructions)
and has implemented the relevant lowering rules (only width is 1).

Removes 1616 instructions from the go binary on loong64.

file         before    after      Δ         %
asm          575366    575314    -52     -0.0090%
cgo          489972    489884    -88     -0.0180%
compile     2920418   2920110    -308    -0.0105%
cover        540458    540290    -168    -0.0311%
fix          865840    865668    -172    -0.0199%
link         732858    732662    -196    -0.0267%
preprofile   246022    245978    -44     -0.0179%
vet          839268    839124    -144    -0.0172%
go          1666470   1666114    -356    -0.0214%
gofmt        326526    326438    -88     -0.0270%
total       9203198   9201582    -1616   -0.0176%

Change-Id: If3518547c785764877a6cf987781d43d8b572990
Reviewed-on: https://go-review.googlesource.com/c/go/+/738240
Reviewed-by: Keith Randall <khr@golang.org>
LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com>
Reviewed-by: Keith Randall <khr@google.com>
Reviewed-by: Dmitri Shuralyov <dmitshur@google.com>

diff --git a/src/cmd/compile/internal/walk/range.go b/src/cmd/compile/internal/walk/range.go
index 139343a8ede2a3a7af67523cd35c43ee2a077a00..866dd23defead04771097dfe7ba208406fcbc955 100644 (file)
--- a/src/cmd/compile/internal/walk/range.go
+++ b/src/cmd/compile/internal/walk/range.go
@@ -23,7 +23,7 @@ func cheapComputableIndex(width int64) bool {
        // MIPS does not have R+R addressing
        // Arm64 may lack ability to generate this code in our assembler,
        // but the architecture supports it.
-       case sys.PPC64, sys.S390X:
+       case sys.Loong64, sys.PPC64, sys.S390X:
                return width == 1
        case sys.AMD64, sys.I386, sys.ARM64, sys.ARM:
                switch width {