[dev.simd] cmd/compile, simd: update generated files

This CL is generated by x/arch CL 694857.

Change-Id: I9745fa8c9b2e3f49bd2cff5ff6b5578c0c67bfa1
Reviewed-on: https://go-review.googlesource.com/c/go/+/694915
Reviewed-by: David Chase <drchase@google.com>
Auto-Submit: Austin Clements <austin@google.com>
Reviewed-by: Junyang Shao <shaojunyang@google.com>
LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com>

diff --git a/src/cmd/compile/internal/amd64/simdssa.go b/src/cmd/compile/internal/amd64/simdssa.go
index 274602c0a757cec45f98cec5ea71ccab3778d353..e6bbdc03def1e44987e4cabb43873d10406c7c55 100644 (file)
--- a/src/cmd/compile/internal/amd64/simdssa.go
+++ b/src/cmd/compile/internal/amd64/simdssa.go
@@ -236,9 +236,12 @@ func ssaGenSIMDValue(s *ssagen.State, v *ssa.Value) bool {
                ssa.OpAMD64VPMULDQ256,
                ssa.OpAMD64VPMULUDQ128,
                ssa.OpAMD64VPMULUDQ256,
+               ssa.OpAMD64VPMULHW128,
+               ssa.OpAMD64VPMULHW256,
+               ssa.OpAMD64VPMULHW512,
                ssa.OpAMD64VPMULHUW128,
                ssa.OpAMD64VPMULHUW256,
-               ssa.OpAMD64VPMULHW512,
+               ssa.OpAMD64VPMULHUW512,
                ssa.OpAMD64VPOR128,
                ssa.OpAMD64VPOR256,
                ssa.OpAMD64VPORD512,
@@ -481,8 +484,11 @@ func ssaGenSIMDValue(s *ssagen.State, v *ssa.Value) bool {
                ssa.OpAMD64VPMINUQMasked128,
                ssa.OpAMD64VPMINUQMasked256,
                ssa.OpAMD64VPMINUQMasked512,
-               ssa.OpAMD64VPMULHUWMasked128,
+               ssa.OpAMD64VPMULHWMasked128,
                ssa.OpAMD64VPMULHWMasked256,
+               ssa.OpAMD64VPMULHWMasked512,
+               ssa.OpAMD64VPMULHUWMasked128,
+               ssa.OpAMD64VPMULHUWMasked256,
                ssa.OpAMD64VPMULHUWMasked512,
                ssa.OpAMD64VMULPSMasked128,
                ssa.OpAMD64VMULPSMasked256,
@@ -1362,8 +1368,11 @@ func ssaGenSIMDValue(s *ssagen.State, v *ssa.Value) bool {
                ssa.OpAMD64VFMADDSUB213PDMasked128,
                ssa.OpAMD64VFMADDSUB213PDMasked256,
                ssa.OpAMD64VFMADDSUB213PDMasked512,
-               ssa.OpAMD64VPMULHUWMasked128,
+               ssa.OpAMD64VPMULHWMasked128,
                ssa.OpAMD64VPMULHWMasked256,
+               ssa.OpAMD64VPMULHWMasked512,
+               ssa.OpAMD64VPMULHUWMasked128,
+               ssa.OpAMD64VPMULHUWMasked256,
                ssa.OpAMD64VPMULHUWMasked512,
                ssa.OpAMD64VMULPSMasked128,
                ssa.OpAMD64VMULPSMasked256,

diff --git a/src/cmd/compile/internal/ssa/_gen/simdAMD64.rules b/src/cmd/compile/internal/ssa/_gen/simdAMD64.rules
index 8ff638808abc3f22caa47ddee9aa60f5cadca904..abfa10020dec49ad524137187f6fb4a65819ea41 100644 (file)
--- a/src/cmd/compile/internal/ssa/_gen/simdAMD64.rules
+++ b/src/cmd/compile/internal/ssa/_gen/simdAMD64.rules
@@ -936,12 +936,18 @@
 (MulEvenWidenInt32x8 ...) => (VPMULDQ256 ...)
 (MulEvenWidenUint32x4 ...) => (VPMULUDQ128 ...)
 (MulEvenWidenUint32x8 ...) => (VPMULUDQ256 ...)
-(MulHighInt16x8 ...) => (VPMULHUW128 ...)
-(MulHighInt16x16 ...) => (VPMULHUW256 ...)
+(MulHighInt16x8 ...) => (VPMULHW128 ...)
+(MulHighInt16x16 ...) => (VPMULHW256 ...)
 (MulHighInt16x32 ...) => (VPMULHW512 ...)
-(MulHighMaskedInt16x8 x y mask) => (VPMULHUWMasked128 x y (VPMOVVec16x8ToM <types.TypeMask> mask))
+(MulHighUint16x8 ...) => (VPMULHUW128 ...)
+(MulHighUint16x16 ...) => (VPMULHUW256 ...)
+(MulHighUint16x32 ...) => (VPMULHUW512 ...)
+(MulHighMaskedInt16x8 x y mask) => (VPMULHWMasked128 x y (VPMOVVec16x8ToM <types.TypeMask> mask))
 (MulHighMaskedInt16x16 x y mask) => (VPMULHWMasked256 x y (VPMOVVec16x16ToM <types.TypeMask> mask))
-(MulHighMaskedInt16x32 x y mask) => (VPMULHUWMasked512 x y (VPMOVVec16x32ToM <types.TypeMask> mask))
+(MulHighMaskedInt16x32 x y mask) => (VPMULHWMasked512 x y (VPMOVVec16x32ToM <types.TypeMask> mask))
+(MulHighMaskedUint16x8 x y mask) => (VPMULHUWMasked128 x y (VPMOVVec16x8ToM <types.TypeMask> mask))
+(MulHighMaskedUint16x16 x y mask) => (VPMULHUWMasked256 x y (VPMOVVec16x16ToM <types.TypeMask> mask))
+(MulHighMaskedUint16x32 x y mask) => (VPMULHUWMasked512 x y (VPMOVVec16x32ToM <types.TypeMask> mask))
 (MulMaskedFloat32x4 x y mask) => (VMULPSMasked128 x y (VPMOVVec32x4ToM <types.TypeMask> mask))
 (MulMaskedFloat32x8 x y mask) => (VMULPSMasked256 x y (VPMOVVec32x8ToM <types.TypeMask> mask))
 (MulMaskedFloat32x16 x y mask) => (VMULPSMasked512 x y (VPMOVVec32x16ToM <types.TypeMask> mask))

diff --git a/src/cmd/compile/internal/ssa/_gen/simdAMD64ops.go b/src/cmd/compile/internal/ssa/_gen/simdAMD64ops.go
index 164ca7a344487d5e7382c157b5f3c1c75ecb5e5d..386415ac41547bdb7e766f713648044dc6f47bf2 100644 (file)
--- a/src/cmd/compile/internal/ssa/_gen/simdAMD64ops.go
+++ b/src/cmd/compile/internal/ssa/_gen/simdAMD64ops.go
@@ -511,10 +511,16 @@ func simdAMD64Ops(v11, v21, v2k, vkv, v2kv, v2kk, v31, v3kv, vgpv, vgp, vfpv, vf
                {name: "VPMULDQ256", argLength: 2, reg: v21, asm: "VPMULDQ", commutative: true, typ: "Vec256", resultInArg0: false},
                {name: "VPMULHUW128", argLength: 2, reg: v21, asm: "VPMULHUW", commutative: true, typ: "Vec128", resultInArg0: false},
                {name: "VPMULHUW256", argLength: 2, reg: v21, asm: "VPMULHUW", commutative: true, typ: "Vec256", resultInArg0: false},
+               {name: "VPMULHUW512", argLength: 2, reg: w21, asm: "VPMULHUW", commutative: true, typ: "Vec512", resultInArg0: false},
                {name: "VPMULHUWMasked128", argLength: 3, reg: w2kw, asm: "VPMULHUW", commutative: true, typ: "Vec128", resultInArg0: false},
+               {name: "VPMULHUWMasked256", argLength: 3, reg: w2kw, asm: "VPMULHUW", commutative: true, typ: "Vec256", resultInArg0: false},
                {name: "VPMULHUWMasked512", argLength: 3, reg: w2kw, asm: "VPMULHUW", commutative: true, typ: "Vec512", resultInArg0: false},
+               {name: "VPMULHW128", argLength: 2, reg: v21, asm: "VPMULHW", commutative: true, typ: "Vec128", resultInArg0: false},
+               {name: "VPMULHW256", argLength: 2, reg: v21, asm: "VPMULHW", commutative: true, typ: "Vec256", resultInArg0: false},
                {name: "VPMULHW512", argLength: 2, reg: w21, asm: "VPMULHW", commutative: true, typ: "Vec512", resultInArg0: false},
+               {name: "VPMULHWMasked128", argLength: 3, reg: w2kw, asm: "VPMULHW", commutative: true, typ: "Vec128", resultInArg0: false},
                {name: "VPMULHWMasked256", argLength: 3, reg: w2kw, asm: "VPMULHW", commutative: true, typ: "Vec256", resultInArg0: false},
+               {name: "VPMULHWMasked512", argLength: 3, reg: w2kw, asm: "VPMULHW", commutative: true, typ: "Vec512", resultInArg0: false},
                {name: "VPMULLD128", argLength: 2, reg: v21, asm: "VPMULLD", commutative: true, typ: "Vec128", resultInArg0: false},
                {name: "VPMULLD256", argLength: 2, reg: v21, asm: "VPMULLD", commutative: true, typ: "Vec256", resultInArg0: false},
                {name: "VPMULLD512", argLength: 2, reg: w21, asm: "VPMULLD", commutative: true, typ: "Vec512", resultInArg0: false},

diff --git a/src/cmd/compile/internal/ssa/_gen/simdgenericOps.go b/src/cmd/compile/internal/ssa/_gen/simdgenericOps.go
index 416c53c44542b9ac9bdefe70f8fc684e46cc1131..2378f196453927c57b12a9f4ce5cc36c5f9749d4 100644 (file)
--- a/src/cmd/compile/internal/ssa/_gen/simdgenericOps.go
+++ b/src/cmd/compile/internal/ssa/_gen/simdgenericOps.go
@@ -859,6 +859,12 @@ func simdGenericOps() []opData {
                {name: "MulHighMaskedInt16x8", argLength: 3, commutative: true},
                {name: "MulHighMaskedInt16x16", argLength: 3, commutative: true},
                {name: "MulHighMaskedInt16x32", argLength: 3, commutative: true},
+               {name: "MulHighMaskedUint16x8", argLength: 3, commutative: true},
+               {name: "MulHighMaskedUint16x16", argLength: 3, commutative: true},
+               {name: "MulHighMaskedUint16x32", argLength: 3, commutative: true},
+               {name: "MulHighUint16x8", argLength: 2, commutative: true},
+               {name: "MulHighUint16x16", argLength: 2, commutative: true},
+               {name: "MulHighUint16x32", argLength: 2, commutative: true},
                {name: "MulInt16x8", argLength: 2, commutative: true},
                {name: "MulInt16x16", argLength: 2, commutative: true},
                {name: "MulInt16x32", argLength: 2, commutative: true},

diff --git a/src/cmd/compile/internal/ssa/opGen.go b/src/cmd/compile/internal/ssa/opGen.go
index d4e4f710a76c33ca85f888d5bf3d7891679d95af..77527c83b8c7511c69fa4959a9cfae1af641e7e2 100644 (file)
--- a/src/cmd/compile/internal/ssa/opGen.go
+++ b/src/cmd/compile/internal/ssa/opGen.go
@@ -1734,10 +1734,16 @@ const (
        OpAMD64VPMULDQ256
        OpAMD64VPMULHUW128
        OpAMD64VPMULHUW256
+       OpAMD64VPMULHUW512
        OpAMD64VPMULHUWMasked128
+       OpAMD64VPMULHUWMasked256
        OpAMD64VPMULHUWMasked512
+       OpAMD64VPMULHW128
+       OpAMD64VPMULHW256
        OpAMD64VPMULHW512
+       OpAMD64VPMULHWMasked128
        OpAMD64VPMULHWMasked256
+       OpAMD64VPMULHWMasked512
        OpAMD64VPMULLD128
        OpAMD64VPMULLD256
        OpAMD64VPMULLD512
@@ -5461,6 +5467,12 @@ const (
        OpMulHighMaskedInt16x8
        OpMulHighMaskedInt16x16
        OpMulHighMaskedInt16x32
+       OpMulHighMaskedUint16x8
+       OpMulHighMaskedUint16x16
+       OpMulHighMaskedUint16x32
+       OpMulHighUint16x8
+       OpMulHighUint16x16
+       OpMulHighUint16x32
        OpMulInt16x8
        OpMulInt16x16
        OpMulInt16x32
@@ -27230,6 +27242,21 @@ var opcodeTable = [...]opInfo{
                        },
                },
        },
+       {
+               name:        "VPMULHUW512",
+               argLen:      2,
+               commutative: true,
+               asm:         x86.AVPMULHUW,
+               reg: regInfo{
+                       inputs: []inputInfo{
+                               {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+                               {1, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+                       },
+                       outputs: []outputInfo{
+                               {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+                       },
+               },
+       },
        {
                name:        "VPMULHUWMasked128",
                argLen:      3,
@@ -27246,6 +27273,22 @@ var opcodeTable = [...]opInfo{
                        },
                },
        },
+       {
+               name:        "VPMULHUWMasked256",
+               argLen:      3,
+               commutative: true,
+               asm:         x86.AVPMULHUW,
+               reg: regInfo{
+                       inputs: []inputInfo{
+                               {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+                               {0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {1, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                       },
+                       outputs: []outputInfo{
+                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                       },
+               },
+       },
        {
                name:        "VPMULHUWMasked512",
                argLen:      3,
@@ -27262,6 +27305,36 @@ var opcodeTable = [...]opInfo{
                        },
                },
        },
+       {
+               name:        "VPMULHW128",
+               argLen:      2,
+               commutative: true,
+               asm:         x86.AVPMULHW,
+               reg: regInfo{
+                       inputs: []inputInfo{
+                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                       },
+                       outputs: []outputInfo{
+                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                       },
+               },
+       },
+       {
+               name:        "VPMULHW256",
+               argLen:      2,
+               commutative: true,
+               asm:         x86.AVPMULHW,
+               reg: regInfo{
+                       inputs: []inputInfo{
+                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                       },
+                       outputs: []outputInfo{
+                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                       },
+               },
+       },
        {
                name:        "VPMULHW512",
                argLen:      2,
@@ -27277,6 +27350,22 @@ var opcodeTable = [...]opInfo{
                        },
                },
        },
+       {
+               name:        "VPMULHWMasked128",
+               argLen:      3,
+               commutative: true,
+               asm:         x86.AVPMULHW,
+               reg: regInfo{
+                       inputs: []inputInfo{
+                               {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+                               {0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {1, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                       },
+                       outputs: []outputInfo{
+                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                       },
+               },
+       },
        {
                name:        "VPMULHWMasked256",
                argLen:      3,
@@ -27293,6 +27382,22 @@ var opcodeTable = [...]opInfo{
                        },
                },
        },
+       {
+               name:        "VPMULHWMasked512",
+               argLen:      3,
+               commutative: true,
+               asm:         x86.AVPMULHW,
+               reg: regInfo{
+                       inputs: []inputInfo{
+                               {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+                               {0, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {1, 2147418112},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                       },
+                       outputs: []outputInfo{
+                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                       },
+               },
+       },
        {
                name:        "VPMULLD128",
                argLen:      2,
@@ -67968,6 +68073,42 @@ var opcodeTable = [...]opInfo{
                commutative: true,
                generic:     true,
        },
+       {
+               name:        "MulHighMaskedUint16x8",
+               argLen:      3,
+               commutative: true,
+               generic:     true,
+       },
+       {
+               name:        "MulHighMaskedUint16x16",
+               argLen:      3,
+               commutative: true,
+               generic:     true,
+       },
+       {
+               name:        "MulHighMaskedUint16x32",
+               argLen:      3,
+               commutative: true,
+               generic:     true,
+       },
+       {
+               name:        "MulHighUint16x8",
+               argLen:      2,
+               commutative: true,
+               generic:     true,
+       },
+       {
+               name:        "MulHighUint16x16",
+               argLen:      2,
+               commutative: true,
+               generic:     true,
+       },
+       {
+               name:        "MulHighUint16x32",
+               argLen:      2,
+               commutative: true,
+               generic:     true,
+       },
        {
                name:        "MulInt16x8",
                argLen:      2,

diff --git a/src/cmd/compile/internal/ssa/rewriteAMD64.go b/src/cmd/compile/internal/ssa/rewriteAMD64.go
index 865b404d1419da03c1371bcf65968f7e49bd0da0..fbe8a448d8d14aa5608edd9e82bc296b96d57158 100644 (file)
--- a/src/cmd/compile/internal/ssa/rewriteAMD64.go
+++ b/src/cmd/compile/internal/ssa/rewriteAMD64.go
@@ -3151,13 +3151,13 @@ func rewriteValueAMD64(v *Value) bool {
                v.Op = OpAMD64VMULPD512
                return true
        case OpMulHighInt16x16:
-               v.Op = OpAMD64VPMULHUW256
+               v.Op = OpAMD64VPMULHW256
                return true
        case OpMulHighInt16x32:
                v.Op = OpAMD64VPMULHW512
                return true
        case OpMulHighInt16x8:
-               v.Op = OpAMD64VPMULHUW128
+               v.Op = OpAMD64VPMULHW128
                return true
        case OpMulHighMaskedInt16x16:
                return rewriteValueAMD64_OpMulHighMaskedInt16x16(v)
@@ -3165,6 +3165,21 @@ func rewriteValueAMD64(v *Value) bool {
                return rewriteValueAMD64_OpMulHighMaskedInt16x32(v)
        case OpMulHighMaskedInt16x8:
                return rewriteValueAMD64_OpMulHighMaskedInt16x8(v)
+       case OpMulHighMaskedUint16x16:
+               return rewriteValueAMD64_OpMulHighMaskedUint16x16(v)
+       case OpMulHighMaskedUint16x32:
+               return rewriteValueAMD64_OpMulHighMaskedUint16x32(v)
+       case OpMulHighMaskedUint16x8:
+               return rewriteValueAMD64_OpMulHighMaskedUint16x8(v)
+       case OpMulHighUint16x16:
+               v.Op = OpAMD64VPMULHUW256
+               return true
+       case OpMulHighUint16x32:
+               v.Op = OpAMD64VPMULHUW512
+               return true
+       case OpMulHighUint16x8:
+               v.Op = OpAMD64VPMULHUW128
+               return true
        case OpMulInt16x16:
                v.Op = OpAMD64VPMULLW256
                return true
@@ -44729,12 +44744,12 @@ func rewriteValueAMD64_OpMulHighMaskedInt16x32(v *Value) bool {
        v_0 := v.Args[0]
        b := v.Block
        // match: (MulHighMaskedInt16x32 x y mask)
-       // result: (VPMULHUWMasked512 x y (VPMOVVec16x32ToM <types.TypeMask> mask))
+       // result: (VPMULHWMasked512 x y (VPMOVVec16x32ToM <types.TypeMask> mask))
        for {
                x := v_0
                y := v_1
                mask := v_2
-               v.reset(OpAMD64VPMULHUWMasked512)
+               v.reset(OpAMD64VPMULHWMasked512)
                v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x32ToM, types.TypeMask)
                v0.AddArg(mask)
                v.AddArg3(x, y, v0)
@@ -44747,6 +44762,60 @@ func rewriteValueAMD64_OpMulHighMaskedInt16x8(v *Value) bool {
        v_0 := v.Args[0]
        b := v.Block
        // match: (MulHighMaskedInt16x8 x y mask)
+       // result: (VPMULHWMasked128 x y (VPMOVVec16x8ToM <types.TypeMask> mask))
+       for {
+               x := v_0
+               y := v_1
+               mask := v_2
+               v.reset(OpAMD64VPMULHWMasked128)
+               v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x8ToM, types.TypeMask)
+               v0.AddArg(mask)
+               v.AddArg3(x, y, v0)
+               return true
+       }
+}
+func rewriteValueAMD64_OpMulHighMaskedUint16x16(v *Value) bool {
+       v_2 := v.Args[2]
+       v_1 := v.Args[1]
+       v_0 := v.Args[0]
+       b := v.Block
+       // match: (MulHighMaskedUint16x16 x y mask)
+       // result: (VPMULHUWMasked256 x y (VPMOVVec16x16ToM <types.TypeMask> mask))
+       for {
+               x := v_0
+               y := v_1
+               mask := v_2
+               v.reset(OpAMD64VPMULHUWMasked256)
+               v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x16ToM, types.TypeMask)
+               v0.AddArg(mask)
+               v.AddArg3(x, y, v0)
+               return true
+       }
+}
+func rewriteValueAMD64_OpMulHighMaskedUint16x32(v *Value) bool {
+       v_2 := v.Args[2]
+       v_1 := v.Args[1]
+       v_0 := v.Args[0]
+       b := v.Block
+       // match: (MulHighMaskedUint16x32 x y mask)
+       // result: (VPMULHUWMasked512 x y (VPMOVVec16x32ToM <types.TypeMask> mask))
+       for {
+               x := v_0
+               y := v_1
+               mask := v_2
+               v.reset(OpAMD64VPMULHUWMasked512)
+               v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x32ToM, types.TypeMask)
+               v0.AddArg(mask)
+               v.AddArg3(x, y, v0)
+               return true
+       }
+}
+func rewriteValueAMD64_OpMulHighMaskedUint16x8(v *Value) bool {
+       v_2 := v.Args[2]
+       v_1 := v.Args[1]
+       v_0 := v.Args[0]
+       b := v.Block
+       // match: (MulHighMaskedUint16x8 x y mask)
        // result: (VPMULHUWMasked128 x y (VPMOVVec16x8ToM <types.TypeMask> mask))
        for {
                x := v_0

diff --git a/src/cmd/compile/internal/ssagen/simdintrinsics.go b/src/cmd/compile/internal/ssagen/simdintrinsics.go
index 4be74d913666eb5ccf3c47eb26c05efacae9a342..02d68a57ccc542d94e82cd3fc140cdbcb8dce700 100644 (file)
--- a/src/cmd/compile/internal/ssagen/simdintrinsics.go
+++ b/src/cmd/compile/internal/ssagen/simdintrinsics.go
@@ -950,9 +950,15 @@ func simdIntrinsics(addF func(pkg, fn string, b intrinsicBuilder, archFamilies .
        addF(simdPackage, "Int16x8.MulHigh", opLen2(ssa.OpMulHighInt16x8, types.TypeVec128), sys.AMD64)
        addF(simdPackage, "Int16x16.MulHigh", opLen2(ssa.OpMulHighInt16x16, types.TypeVec256), sys.AMD64)
        addF(simdPackage, "Int16x32.MulHigh", opLen2(ssa.OpMulHighInt16x32, types.TypeVec512), sys.AMD64)
+       addF(simdPackage, "Uint16x8.MulHigh", opLen2(ssa.OpMulHighUint16x8, types.TypeVec128), sys.AMD64)
+       addF(simdPackage, "Uint16x16.MulHigh", opLen2(ssa.OpMulHighUint16x16, types.TypeVec256), sys.AMD64)
+       addF(simdPackage, "Uint16x32.MulHigh", opLen2(ssa.OpMulHighUint16x32, types.TypeVec512), sys.AMD64)
        addF(simdPackage, "Int16x8.MulHighMasked", opLen3(ssa.OpMulHighMaskedInt16x8, types.TypeVec128), sys.AMD64)
        addF(simdPackage, "Int16x16.MulHighMasked", opLen3(ssa.OpMulHighMaskedInt16x16, types.TypeVec256), sys.AMD64)
        addF(simdPackage, "Int16x32.MulHighMasked", opLen3(ssa.OpMulHighMaskedInt16x32, types.TypeVec512), sys.AMD64)
+       addF(simdPackage, "Uint16x8.MulHighMasked", opLen3(ssa.OpMulHighMaskedUint16x8, types.TypeVec128), sys.AMD64)
+       addF(simdPackage, "Uint16x16.MulHighMasked", opLen3(ssa.OpMulHighMaskedUint16x16, types.TypeVec256), sys.AMD64)
+       addF(simdPackage, "Uint16x32.MulHighMasked", opLen3(ssa.OpMulHighMaskedUint16x32, types.TypeVec512), sys.AMD64)
        addF(simdPackage, "Float32x4.MulMasked", opLen3(ssa.OpMulMaskedFloat32x4, types.TypeVec128), sys.AMD64)
        addF(simdPackage, "Float32x8.MulMasked", opLen3(ssa.OpMulMaskedFloat32x8, types.TypeVec256), sys.AMD64)
        addF(simdPackage, "Float32x16.MulMasked", opLen3(ssa.OpMulMaskedFloat32x16, types.TypeVec512), sys.AMD64)

diff --git a/src/simd/ops_amd64.go b/src/simd/ops_amd64.go
index 01d939c9ed42f28a580493fc73cbc2a17da78c32..32830e8d2042221c5847887ed3f070bf59283fb7 100644 (file)
--- a/src/simd/ops_amd64.go
+++ b/src/simd/ops_amd64.go
@@ -5862,12 +5862,12 @@ func (x Uint32x8) MulEvenWiden(y Uint32x8) Uint64x4
 
 // MulHigh multiplies elements and stores the high part of the result.
 //
-// Asm: VPMULHUW, CPU Feature: AVX
+// Asm: VPMULHW, CPU Feature: AVX
 func (x Int16x8) MulHigh(y Int16x8) Int16x8
 
 // MulHigh multiplies elements and stores the high part of the result.
 //
-// Asm: VPMULHUW, CPU Feature: AVX2
+// Asm: VPMULHW, CPU Feature: AVX2
 func (x Int16x16) MulHigh(y Int16x16) Int16x16
 
 // MulHigh multiplies elements and stores the high part of the result.
@@ -5875,13 +5875,28 @@ func (x Int16x16) MulHigh(y Int16x16) Int16x16
 // Asm: VPMULHW, CPU Feature: AVX512BW
 func (x Int16x32) MulHigh(y Int16x32) Int16x32
 
+// MulHigh multiplies elements and stores the high part of the result.
+//
+// Asm: VPMULHUW, CPU Feature: AVX
+func (x Uint16x8) MulHigh(y Uint16x8) Uint16x8
+
+// MulHigh multiplies elements and stores the high part of the result.
+//
+// Asm: VPMULHUW, CPU Feature: AVX2
+func (x Uint16x16) MulHigh(y Uint16x16) Uint16x16
+
+// MulHigh multiplies elements and stores the high part of the result.
+//
+// Asm: VPMULHUW, CPU Feature: AVX512BW
+func (x Uint16x32) MulHigh(y Uint16x32) Uint16x32
+
 /* MulHighMasked */
 
 // MulHighMasked multiplies elements and stores the high part of the result.
 //
 // This operation is applied selectively under a write mask.
 //
-// Asm: VPMULHUW, CPU Feature: AVX512BW
+// Asm: VPMULHW, CPU Feature: AVX512BW
 func (x Int16x8) MulHighMasked(y Int16x8, mask Mask16x8) Int16x8
 
 // MulHighMasked multiplies elements and stores the high part of the result.
@@ -5895,9 +5910,30 @@ func (x Int16x16) MulHighMasked(y Int16x16, mask Mask16x16) Int16x16
 //
 // This operation is applied selectively under a write mask.
 //
-// Asm: VPMULHUW, CPU Feature: AVX512BW
+// Asm: VPMULHW, CPU Feature: AVX512BW
 func (x Int16x32) MulHighMasked(y Int16x32, mask Mask16x32) Int16x32
 
+// MulHighMasked multiplies elements and stores the high part of the result.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPMULHUW, CPU Feature: AVX512BW
+func (x Uint16x8) MulHighMasked(y Uint16x8, mask Mask16x8) Uint16x8
+
+// MulHighMasked multiplies elements and stores the high part of the result.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPMULHUW, CPU Feature: AVX512BW
+func (x Uint16x16) MulHighMasked(y Uint16x16, mask Mask16x16) Uint16x16
+
+// MulHighMasked multiplies elements and stores the high part of the result.
+//
+// This operation is applied selectively under a write mask.
+//
+// Asm: VPMULHUW, CPU Feature: AVX512BW
+func (x Uint16x32) MulHighMasked(y Uint16x32, mask Mask16x32) Uint16x32
+
 /* MulMasked */
 
 // MulMasked multiplies corresponding elements of two vectors.