cmd/compile: use zero register instead of specialized *zero instructions on loong64

author limeidan <limeidan@loongson.cn>

Tue, 19 Aug 2025 11:16:31 +0000 (19:16 +0800)

committer Gopher Robot <gobot@golang.org>

Thu, 21 Aug 2025 18:23:05 +0000 (11:23 -0700)
author limeidan <limeidan@loongson.cn>
Tue, 19 Aug 2025 11:16:31 +0000 (19:16 +0800)
committer Gopher Robot <gobot@golang.org>
Thu, 21 Aug 2025 18:23:05 +0000 (11:23 -0700)
diff --git a/src/cmd/compile/internal/loong64/ssa.go b/src/cmd/compile/internal/loong64/ssa.go

index d9bf721565bd9d9f7042e5e18423bbc479815fef..895eadd07261d6e7fade08d221b62e7b70d9e107 100644 (file)
--- a/src/cmd/compile/internal/loong64/ssa.go
+++ b/src/cmd/compile/internal/loong64/ssa.go
@@ -125,6 +125,7 @@ func ssaGenValue(s *ssagen.State, v *ssa.Value) {
                 p.To.Type = obj.TYPE_REG
                 p.To.Reg = y
         case ssa.OpLOONG64MOVVnop,
+               ssa.OpLOONG64ZERO,
                 ssa.OpLOONG64LoweredRound32F,
                 ssa.OpLOONG64LoweredRound64F:
                 // nothing to do
@@ -432,18 +433,6 @@ func ssaGenValue(s *ssagen.State, v *ssa.Value) {
                 p.To.Reg = v.Args[0].Reg()
                 p.To.Index = v.Args[1].Reg()
  
-       case ssa.OpLOONG64MOVBstorezeroidx,
-               ssa.OpLOONG64MOVHstorezeroidx,
-               ssa.OpLOONG64MOVWstorezeroidx,
-               ssa.OpLOONG64MOVVstorezeroidx:
-               p := s.Prog(v.Op.Asm())
-               p.From.Type = obj.TYPE_REG
-               p.From.Reg = loong64.REGZERO
-               p.To.Type = obj.TYPE_MEM
-               p.To.Name = obj.NAME_NONE
-               p.To.Reg = v.Args[0].Reg()
-               p.To.Index = v.Args[1].Reg()
-
         case ssa.OpLOONG64MOVBload,
                 ssa.OpLOONG64MOVBUload,
                 ssa.OpLOONG64MOVHload,
@@ -471,16 +460,6 @@ func ssaGenValue(s *ssagen.State, v *ssa.Value) {
                 p.To.Type = obj.TYPE_MEM
                 p.To.Reg = v.Args[0].Reg()
                 ssagen.AddAux(&p.To, v)
-       case ssa.OpLOONG64MOVBstorezero,
-               ssa.OpLOONG64MOVHstorezero,
-               ssa.OpLOONG64MOVWstorezero,
-               ssa.OpLOONG64MOVVstorezero:
-               p := s.Prog(v.Op.Asm())
-               p.From.Type = obj.TYPE_REG
-               p.From.Reg = loong64.REGZERO
-               p.To.Type = obj.TYPE_MEM
-               p.To.Reg = v.Args[0].Reg()
-               ssagen.AddAux(&p.To, v)
         case ssa.OpLOONG64MOVBreg,
                 ssa.OpLOONG64MOVBUreg,
                 ssa.OpLOONG64MOVHreg,
diff --git a/src/cmd/compile/internal/ssa/_gen/LOONG64.rules b/src/cmd/compile/internal/ssa/_gen/LOONG64.rules

index bef2b8615b30129527a037107911b93ea438d595..ba506ea24bb6f221c22803b78ce4c7b23b49bd96 100644 (file)
--- a/src/cmd/compile/internal/ssa/_gen/LOONG64.rules
+++ b/src/cmd/compile/internal/ssa/_gen/LOONG64.rules
@@ -576,10 +576,6 @@
         && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink) =>
         (MOV(B|H|W|V|F|D)store [off1+int32(off2)] {sym} ptr val mem)
  
-(MOV(B|H|W|V)storezero [off1] {sym} (ADDVconst [off2] ptr) mem) && is32Bit(int64(off1)+off2)
-       && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink) =>
-       (MOV(B|H|W|V)storezero [off1+int32(off2)] {sym} ptr mem)
-
  (MOV(B|BU|H|HU|W|WU|V|F|D)load [off1] {sym1} (MOVVaddr [off2] {sym2} ptr) mem) && canMergeSym(sym1,sym2)
         && is32Bit(int64(off1)+int64(off2)) && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink) =>
         (MOV(B|BU|H|HU|W|WU|V|F|D)load [off1+int32(off2)] {mergeSym(sym1,sym2)} ptr mem)
@@ -588,10 +584,6 @@
         && is32Bit(int64(off1)+int64(off2)) && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink) =>
         (MOV(B|H|W|V|F|D)store [off1+int32(off2)] {mergeSym(sym1,sym2)} ptr val mem)
  
-(MOV(B|H|W|V)storezero [off1] {sym1} (MOVVaddr [off2] {sym2} ptr) mem) && canMergeSym(sym1,sym2)
-       && is32Bit(int64(off1)+int64(off2)) && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink) =>
-       (MOV(B|H|W|V)storezero [off1+int32(off2)] {mergeSym(sym1,sym2)} ptr mem)
-
  // don't extend after proper load
  (MOVBreg x:(MOVBload _ _)) => (MOVVreg x)
  (MOVBUreg x:(MOVBUload _ _)) => (MOVVreg x)
@@ -654,11 +646,6 @@
  (MOVWstore [off] {sym} ptr (MOVWreg x) mem) => (MOVWstore [off] {sym} ptr x mem)
  (MOVWstore [off] {sym} ptr (MOVWUreg x) mem) => (MOVWstore [off] {sym} ptr x mem)
  
-(MOVBstore [off] {sym} ptr (MOVVconst [0]) mem) => (MOVBstorezero [off] {sym} ptr mem)
-(MOVHstore [off] {sym} ptr (MOVVconst [0]) mem) => (MOVHstorezero [off] {sym} ptr mem)
-(MOVWstore [off] {sym} ptr (MOVVconst [0]) mem) => (MOVWstorezero [off] {sym} ptr mem)
-(MOVVstore [off] {sym} ptr (MOVVconst [0]) mem) => (MOVVstorezero [off] {sym} ptr mem)
-
  // register indexed load
  (MOVVload [off] {sym} (ADDV ptr idx) mem) && off == 0 && sym == nil => (MOVVloadidx ptr idx mem)
  (MOVWUload [off] {sym} (ADDV ptr idx) mem) && off == 0 && sym == nil => (MOVWUloadidx ptr idx mem)
@@ -708,24 +695,6 @@
  (MOVDstoreidx ptr (MOVVconst [c]) val mem) && is32Bit(c) => (MOVDstore [int32(c)] ptr val mem)
  (MOVDstoreidx (MOVVconst [c]) idx val mem) && is32Bit(c) => (MOVDstore [int32(c)] idx val mem)
  
-// register indexed store zero
-(MOVVstorezero [off] {sym} (ADDV ptr idx) mem) && off == 0 && sym == nil => (MOVVstorezeroidx ptr idx mem)
-(MOVWstorezero [off] {sym} (ADDV ptr idx) mem) && off == 0 && sym == nil => (MOVWstorezeroidx ptr idx mem)
-(MOVHstorezero [off] {sym} (ADDV ptr idx) mem) && off == 0 && sym == nil => (MOVHstorezeroidx ptr idx mem)
-(MOVBstorezero [off] {sym} (ADDV ptr idx) mem) && off == 0 && sym == nil => (MOVBstorezeroidx ptr idx mem)
-(MOVVstoreidx ptr idx (MOVVconst [0]) mem) => (MOVVstorezeroidx ptr idx mem)
-(MOVWstoreidx ptr idx (MOVVconst [0]) mem) => (MOVWstorezeroidx ptr idx mem)
-(MOVHstoreidx ptr idx (MOVVconst [0]) mem) => (MOVHstorezeroidx ptr idx mem)
-(MOVBstoreidx ptr idx (MOVVconst [0]) mem) => (MOVBstorezeroidx ptr idx mem)
-(MOVVstorezeroidx ptr (MOVVconst [c]) mem) && is32Bit(c) => (MOVVstorezero [int32(c)] ptr mem)
-(MOVVstorezeroidx (MOVVconst [c]) idx mem) && is32Bit(c) => (MOVVstorezero [int32(c)] idx mem)
-(MOVWstorezeroidx ptr (MOVVconst [c]) mem) && is32Bit(c) => (MOVWstorezero [int32(c)] ptr mem)
-(MOVWstorezeroidx (MOVVconst [c]) idx mem) && is32Bit(c) => (MOVWstorezero [int32(c)] idx mem)
-(MOVHstorezeroidx ptr (MOVVconst [c]) mem) && is32Bit(c) => (MOVHstorezero [int32(c)] ptr mem)
-(MOVHstorezeroidx (MOVVconst [c]) idx mem) && is32Bit(c) => (MOVHstorezero [int32(c)] idx mem)
-(MOVBstorezeroidx ptr (MOVVconst [c]) mem) && is32Bit(c) => (MOVBstorezero [int32(c)] ptr mem)
-(MOVBstorezeroidx (MOVVconst [c]) idx mem) && is32Bit(c) => (MOVBstorezero [int32(c)] idx mem)
-
  // if a register move has only 1 use, just use the same register without emitting instruction
  // MOVVnop doesn't emit instruction, only for ensuring the type.
  (MOVVreg x) && x.Uses == 1 => (MOVVnop x)
diff --git a/src/cmd/compile/internal/ssa/_gen/LOONG64Ops.go b/src/cmd/compile/internal/ssa/_gen/LOONG64Ops.go

index 277998efbbccb3b84b224230c628a03105c1caac..ccd9721498232aa0bd05ec27854858e1bd488ba3 100644 (file)
--- a/src/cmd/compile/internal/ssa/_gen/LOONG64Ops.go
+++ b/src/cmd/compile/internal/ssa/_gen/LOONG64Ops.go
@@ -29,7 +29,7 @@ import "strings"
  // so that regmask stays within int64
  // Be careful when hand coding regmasks.
  var regNamesLOONG64 = []string{
-       "R0", // constant 0
+       "ZERO", // constant 0
         "R1",
         "SP", // aka R3
         "R4",
@@ -131,18 +131,18 @@ func init() {
                 fp         = buildReg("F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31")
                 callerSave = gp | fp | buildReg("g") // runtime.setg (and anything calling it) may clobber g
                 first16    = buildReg("R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19")
+               rz         = buildReg("ZERO")
         )
         // Common regInfo
         var (
                 gp01      = regInfo{inputs: nil, outputs: []regMask{gp}}
                 gp11      = regInfo{inputs: []regMask{gpg}, outputs: []regMask{gp}}
                 gp11sp    = regInfo{inputs: []regMask{gpspg}, outputs: []regMask{gp}}
-               gp21      = regInfo{inputs: []regMask{gpg, gpg}, outputs: []regMask{gp}}
+               gp21      = regInfo{inputs: []regMask{gpg, gpg | rz}, outputs: []regMask{gp}}
                 gpload    = regInfo{inputs: []regMask{gpspsbg}, outputs: []regMask{gp}}
                 gp2load   = regInfo{inputs: []regMask{gpspsbg, gpg}, outputs: []regMask{gp}}
                 gpstore   = regInfo{inputs: []regMask{gpspsbg, gpg}}
-               gpstore0  = regInfo{inputs: []regMask{gpspsbg}}
-               gpstore2  = regInfo{inputs: []regMask{gpspsbg, gpg, gpg}}
+               gpstore2  = regInfo{inputs: []regMask{gpspsbg, gpg, gpg | rz}}
                 gpxchg    = regInfo{inputs: []regMask{gpspsbg, gpg}, outputs: []regMask{gp}}
                 gpcas     = regInfo{inputs: []regMask{gpspsbg, gpg, gpg}, outputs: []regMask{gp}}
                 preldreg  = regInfo{inputs: []regMask{gpspg}}
@@ -305,12 +305,12 @@ func init() {
                 {name: "MOVFloadidx", argLength: 3, reg: fp2load, asm: "MOVF", typ: "Float32"},  // load 32-bit float from arg0 + arg1, arg2=mem.
                 {name: "MOVDloadidx", argLength: 3, reg: fp2load, asm: "MOVD", typ: "Float64"},  // load 64-bit float from arg0 + arg1, arg2=mem.
  
-               {name: "MOVBstore", argLength: 3, reg: gpstore, aux: "SymOff", asm: "MOVB", typ: "Mem", faultOnNilArg0: true, symEffect: "Write"}, // store 1 byte of arg1 to arg0 + auxInt + aux.  arg2=mem.
-               {name: "MOVHstore", argLength: 3, reg: gpstore, aux: "SymOff", asm: "MOVH", typ: "Mem", faultOnNilArg0: true, symEffect: "Write"}, // store 2 bytes of arg1 to arg0 + auxInt + aux.  arg2=mem.
-               {name: "MOVWstore", argLength: 3, reg: gpstore, aux: "SymOff", asm: "MOVW", typ: "Mem", faultOnNilArg0: true, symEffect: "Write"}, // store 4 bytes of arg1 to arg0 + auxInt + aux.  arg2=mem.
-               {name: "MOVVstore", argLength: 3, reg: gpstore, aux: "SymOff", asm: "MOVV", typ: "Mem", faultOnNilArg0: true, symEffect: "Write"}, // store 8 bytes of arg1 to arg0 + auxInt + aux.  arg2=mem.
-               {name: "MOVFstore", argLength: 3, reg: fpstore, aux: "SymOff", asm: "MOVF", typ: "Mem", faultOnNilArg0: true, symEffect: "Write"}, // store 4 bytes of arg1 to arg0 + auxInt + aux.  arg2=mem.
-               {name: "MOVDstore", argLength: 3, reg: fpstore, aux: "SymOff", asm: "MOVD", typ: "Mem", faultOnNilArg0: true, symEffect: "Write"}, // store 8 bytes of arg1 to arg0 + auxInt + aux.  arg2=mem.
+               {name: "MOVBstore", argLength: 3, reg: regInfo{inputs: []regMask{gpspsbg, gpg | rz}}, aux: "SymOff", asm: "MOVB", typ: "Mem", faultOnNilArg0: true, symEffect: "Write"}, // store 1 byte of arg1 to arg0 + auxInt + aux.  arg2=mem.
+               {name: "MOVHstore", argLength: 3, reg: regInfo{inputs: []regMask{gpspsbg, gpg | rz}}, aux: "SymOff", asm: "MOVH", typ: "Mem", faultOnNilArg0: true, symEffect: "Write"}, // store 2 bytes of arg1 to arg0 + auxInt + aux.  arg2=mem.
+               {name: "MOVWstore", argLength: 3, reg: regInfo{inputs: []regMask{gpspsbg, gpg | rz}}, aux: "SymOff", asm: "MOVW", typ: "Mem", faultOnNilArg0: true, symEffect: "Write"}, // store 4 bytes of arg1 to arg0 + auxInt + aux.  arg2=mem.
+               {name: "MOVVstore", argLength: 3, reg: regInfo{inputs: []regMask{gpspsbg, gpg | rz}}, aux: "SymOff", asm: "MOVV", typ: "Mem", faultOnNilArg0: true, symEffect: "Write"}, // store 8 bytes of arg1 to arg0 + auxInt + aux.  arg2=mem.
+               {name: "MOVFstore", argLength: 3, reg: fpstore, aux: "SymOff", asm: "MOVF", typ: "Mem", faultOnNilArg0: true, symEffect: "Write"},                                       // store 4 bytes of arg1 to arg0 + auxInt + aux.  arg2=mem.
+               {name: "MOVDstore", argLength: 3, reg: fpstore, aux: "SymOff", asm: "MOVD", typ: "Mem", faultOnNilArg0: true, symEffect: "Write"},                                       // store 8 bytes of arg1 to arg0 + auxInt + aux.  arg2=mem.
  
                 // register indexed store
                 {name: "MOVBstoreidx", argLength: 4, reg: gpstore2, asm: "MOVB", typ: "Mem"}, // store 1 byte of arg2 to arg0 + arg1, arg3 = mem.
@@ -320,17 +320,6 @@ func init() {
                 {name: "MOVFstoreidx", argLength: 4, reg: fpstore2, asm: "MOVF", typ: "Mem"}, // store 32-bit float of arg2 to arg0 + arg1, arg3=mem.
                 {name: "MOVDstoreidx", argLength: 4, reg: fpstore2, asm: "MOVD", typ: "Mem"}, // store 64-bit float of arg2 to arg0 + arg1, arg3=mem.
  
-               {name: "MOVBstorezero", argLength: 2, reg: gpstore0, aux: "SymOff", asm: "MOVB", typ: "Mem", faultOnNilArg0: true, symEffect: "Write"}, // store 1 byte of zero to arg0 + auxInt + aux.  arg1=mem.
-               {name: "MOVHstorezero", argLength: 2, reg: gpstore0, aux: "SymOff", asm: "MOVH", typ: "Mem", faultOnNilArg0: true, symEffect: "Write"}, // store 2 bytes of zero to arg0 + auxInt + aux.  arg1=mem.
-               {name: "MOVWstorezero", argLength: 2, reg: gpstore0, aux: "SymOff", asm: "MOVW", typ: "Mem", faultOnNilArg0: true, symEffect: "Write"}, // store 4 bytes of zero to arg0 + auxInt + aux.  arg1=mem.
-               {name: "MOVVstorezero", argLength: 2, reg: gpstore0, aux: "SymOff", asm: "MOVV", typ: "Mem", faultOnNilArg0: true, symEffect: "Write"}, // store 8 bytes of zero to arg0 + auxInt + aux.  ar12=mem.
-
-               // register indexed store zero
-               {name: "MOVBstorezeroidx", argLength: 3, reg: gpstore, asm: "MOVB", typ: "Mem"}, // store 1 byte of zero to arg0 + arg1, arg2 = mem.
-               {name: "MOVHstorezeroidx", argLength: 3, reg: gpstore, asm: "MOVH", typ: "Mem"}, // store 2 bytes of zero to arg0 + arg1, arg2 = mem.
-               {name: "MOVWstorezeroidx", argLength: 3, reg: gpstore, asm: "MOVW", typ: "Mem"}, // store 4 bytes of zero to arg0 + arg1, arg2 = mem.
-               {name: "MOVVstorezeroidx", argLength: 3, reg: gpstore, asm: "MOVV", typ: "Mem"}, // store 8 bytes of zero to arg0 + arg1, arg2 = mem.
-
                 // moves (no conversion)
                 {name: "MOVWfpgp", argLength: 1, reg: fpgp, asm: "MOVW"}, // move float32 to int32 (no conversion).
                 {name: "MOVWgpfp", argLength: 1, reg: gpfp, asm: "MOVW"}, // move int32 to float32 (no conversion).
@@ -580,6 +569,7 @@ func init() {
                 {name: "PRELDX", argLength: 2, aux: "Int64", reg: preldreg, asm: "PRELDX", hasSideEffects: true},
  
                 {name: "ADDshiftLLV", argLength: 2, aux: "Int64", reg: gp21, asm: "ALSLV"}, // arg0 + arg1<<auxInt, the value of auxInt should be in the range [1, 4].
+               {name: "ZERO", zeroWidth: true, fixedReg: true},
         }
  
         blocks := []blockData{
diff --git a/src/cmd/compile/internal/ssa/_gen/LOONG64latelower.rules b/src/cmd/compile/internal/ssa/_gen/LOONG64latelower.rules

index 44583e8e340926b9fd2c4fac87046e0368751c98..6ffce76fb4c1ed0b630412d38f9ae1c837b244d9 100644 (file)
--- a/src/cmd/compile/internal/ssa/_gen/LOONG64latelower.rules
+++ b/src/cmd/compile/internal/ssa/_gen/LOONG64latelower.rules
@@ -7,3 +7,6 @@
  
  (EQZ (XOR x y) yes no) => (BEQ x y yes no)
  (NEZ (XOR x y) yes no) => (BNE x y yes no)
+
+// use zero register
+(MOVVconst [0]) => (ZERO)
diff --git a/src/cmd/compile/internal/ssa/opGen.go b/src/cmd/compile/internal/ssa/opGen.go

index 6d9297acfd2746610782f28c0c43703432f33aff..126682b98668492602c2bd98b3f822af074c014c 100644 (file)
--- a/src/cmd/compile/internal/ssa/opGen.go
+++ b/src/cmd/compile/internal/ssa/opGen.go
@@ -1894,14 +1894,6 @@ const (
         OpLOONG64MOVVstoreidx
         OpLOONG64MOVFstoreidx
         OpLOONG64MOVDstoreidx
-       OpLOONG64MOVBstorezero
-       OpLOONG64MOVHstorezero
-       OpLOONG64MOVWstorezero
-       OpLOONG64MOVVstorezero
-       OpLOONG64MOVBstorezeroidx
-       OpLOONG64MOVHstorezeroidx
-       OpLOONG64MOVWstorezeroidx
-       OpLOONG64MOVVstorezeroidx
         OpLOONG64MOVWfpgp
         OpLOONG64MOVWgpfp
         OpLOONG64MOVVfpgp
@@ -1973,6 +1965,7 @@ const (
         OpLOONG64PRELD
         OpLOONG64PRELDX
         OpLOONG64ADDshiftLLV
+       OpLOONG64ZERO
  
         OpMIPSADD
         OpMIPSADDconst
@@ -24051,7 +24044,7 @@ var opcodeTable = [...]opInfo{
                 reg: regInfo{
                         inputs: []inputInfo{
                                 {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
-                               {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
+                               {1, 1073741817}, // ZERO R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
                         },
                         outputs: []outputInfo{
                                 {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
@@ -24079,7 +24072,7 @@ var opcodeTable = [...]opInfo{
                 reg: regInfo{
                         inputs: []inputInfo{
                                 {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
-                               {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
+                               {1, 1073741817}, // ZERO R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
                         },
                         outputs: []outputInfo{
                                 {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
@@ -24108,7 +24101,7 @@ var opcodeTable = [...]opInfo{
                 reg: regInfo{
                         inputs: []inputInfo{
                                 {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
-                               {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
+                               {1, 1073741817}, // ZERO R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
                         },
                         outputs: []outputInfo{
                                 {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
@@ -24123,7 +24116,7 @@ var opcodeTable = [...]opInfo{
                 reg: regInfo{
                         inputs: []inputInfo{
                                 {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
-                               {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
+                               {1, 1073741817}, // ZERO R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
                         },
                         outputs: []outputInfo{
                                 {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
@@ -24138,7 +24131,7 @@ var opcodeTable = [...]opInfo{
                 reg: regInfo{
                         inputs: []inputInfo{
                                 {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
-                               {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
+                               {1, 1073741817}, // ZERO R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
                         },
                         outputs: []outputInfo{
                                 {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
@@ -24152,7 +24145,7 @@ var opcodeTable = [...]opInfo{
                 reg: regInfo{
                         inputs: []inputInfo{
                                 {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
-                               {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
+                               {1, 1073741817}, // ZERO R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
                         },
                         outputs: []outputInfo{
                                 {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
@@ -24166,7 +24159,7 @@ var opcodeTable = [...]opInfo{
                 reg: regInfo{
                         inputs: []inputInfo{
                                 {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
-                               {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
+                               {1, 1073741817}, // ZERO R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
                         },
                         outputs: []outputInfo{
                                 {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
@@ -24180,7 +24173,7 @@ var opcodeTable = [...]opInfo{
                 reg: regInfo{
                         inputs: []inputInfo{
                                 {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
-                               {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
+                               {1, 1073741817}, // ZERO R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
                         },
                         outputs: []outputInfo{
                                 {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
@@ -24194,7 +24187,7 @@ var opcodeTable = [...]opInfo{
                 reg: regInfo{
                         inputs: []inputInfo{
                                 {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
-                               {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
+                               {1, 1073741817}, // ZERO R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
                         },
                         outputs: []outputInfo{
                                 {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
@@ -24325,7 +24318,7 @@ var opcodeTable = [...]opInfo{
                 reg: regInfo{
                         inputs: []inputInfo{
                                 {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
-                               {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
+                               {1, 1073741817}, // ZERO R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
                         },
                         outputs: []outputInfo{
                                 {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
@@ -24354,7 +24347,7 @@ var opcodeTable = [...]opInfo{
                 reg: regInfo{
                         inputs: []inputInfo{
                                 {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
-                               {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
+                               {1, 1073741817}, // ZERO R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
                         },
                         outputs: []outputInfo{
                                 {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
@@ -24383,7 +24376,7 @@ var opcodeTable = [...]opInfo{
                 reg: regInfo{
                         inputs: []inputInfo{
                                 {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
-                               {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
+                               {1, 1073741817}, // ZERO R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
                         },
                         outputs: []outputInfo{
                                 {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
@@ -24412,7 +24405,7 @@ var opcodeTable = [...]opInfo{
                 reg: regInfo{
                         inputs: []inputInfo{
                                 {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
-                               {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
+                               {1, 1073741817}, // ZERO R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
                         },
                         outputs: []outputInfo{
                                 {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
@@ -24440,7 +24433,7 @@ var opcodeTable = [...]opInfo{
                 reg: regInfo{
                         inputs: []inputInfo{
                                 {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
-                               {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
+                               {1, 1073741817}, // ZERO R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
                         },
                         outputs: []outputInfo{
                                 {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
@@ -24454,7 +24447,7 @@ var opcodeTable = [...]opInfo{
                 reg: regInfo{
                         inputs: []inputInfo{
                                 {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
-                               {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
+                               {1, 1073741817}, // ZERO R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
                         },
                         outputs: []outputInfo{
                                 {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
@@ -24660,7 +24653,7 @@ var opcodeTable = [...]opInfo{
                 reg: regInfo{
                         inputs: []inputInfo{
                                 {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
-                               {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
+                               {1, 1073741817}, // ZERO R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
                         },
                         outputs: []outputInfo{
                                 {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
@@ -24674,7 +24667,7 @@ var opcodeTable = [...]opInfo{
                 reg: regInfo{
                         inputs: []inputInfo{
                                 {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
-                               {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
+                               {1, 1073741817}, // ZERO R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
                         },
                         outputs: []outputInfo{
                                 {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
@@ -24702,7 +24695,7 @@ var opcodeTable = [...]opInfo{
                 reg: regInfo{
                         inputs: []inputInfo{
                                 {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
-                               {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
+                               {1, 1073741817}, // ZERO R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
                         },
                         outputs: []outputInfo{
                                 {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
@@ -24716,7 +24709,7 @@ var opcodeTable = [...]opInfo{
                 reg: regInfo{
                         inputs: []inputInfo{
                                 {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
-                               {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
+                               {1, 1073741817}, // ZERO R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
                         },
                         outputs: []outputInfo{
                                 {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
@@ -24758,7 +24751,7 @@ var opcodeTable = [...]opInfo{
                 reg: regInfo{
                         inputs: []inputInfo{
                                 {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
-                               {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
+                               {1, 1073741817}, // ZERO R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
                         },
                         outputs: []outputInfo{
                                 {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
@@ -24772,7 +24765,7 @@ var opcodeTable = [...]opInfo{
                 reg: regInfo{
                         inputs: []inputInfo{
                                 {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
-                               {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
+                               {1, 1073741817}, // ZERO R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
                         },
                         outputs: []outputInfo{
                                 {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
@@ -24814,7 +24807,7 @@ var opcodeTable = [...]opInfo{
                 reg: regInfo{
                         inputs: []inputInfo{
                                 {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
-                               {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
+                               {1, 1073741817}, // ZERO R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
                         },
                         outputs: []outputInfo{
                                 {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
@@ -24828,7 +24821,7 @@ var opcodeTable = [...]opInfo{
                 reg: regInfo{
                         inputs: []inputInfo{
                                 {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
-                               {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
+                               {1, 1073741817}, // ZERO R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
                         },
                         outputs: []outputInfo{
                                 {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
@@ -24870,7 +24863,7 @@ var opcodeTable = [...]opInfo{
                 reg: regInfo{
                         inputs: []inputInfo{
                                 {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
-                               {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
+                               {1, 1073741817}, // ZERO R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
                         },
                         outputs: []outputInfo{
                                 {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
@@ -24884,7 +24877,7 @@ var opcodeTable = [...]opInfo{
                 reg: regInfo{
                         inputs: []inputInfo{
                                 {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
-                               {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
+                               {1, 1073741817}, // ZERO R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
                         },
                         outputs: []outputInfo{
                                 {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
@@ -24926,7 +24919,7 @@ var opcodeTable = [...]opInfo{
                 reg: regInfo{
                         inputs: []inputInfo{
                                 {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
-                               {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
+                               {1, 1073741817}, // ZERO R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
                         },
                         outputs: []outputInfo{
                                 {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
@@ -24954,7 +24947,7 @@ var opcodeTable = [...]opInfo{
                 reg: regInfo{
                         inputs: []inputInfo{
                                 {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
-                               {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
+                               {1, 1073741817}, // ZERO R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
                         },
                         outputs: []outputInfo{
                                 {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
@@ -25400,7 +25393,7 @@ var opcodeTable = [...]opInfo{
                 asm:            loong64.AMOVB,
                 reg: regInfo{
                         inputs: []inputInfo{
-                               {1, 1073741816},          // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
+                               {1, 1073741817},          // ZERO R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
                                 {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
                         },
                 },
@@ -25414,7 +25407,7 @@ var opcodeTable = [...]opInfo{
                 asm:            loong64.AMOVH,
                 reg: regInfo{
                         inputs: []inputInfo{
-                               {1, 1073741816},          // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
+                               {1, 1073741817},          // ZERO R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
                                 {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
                         },
                 },
@@ -25428,7 +25421,7 @@ var opcodeTable = [...]opInfo{
                 asm:            loong64.AMOVW,
                 reg: regInfo{
                         inputs: []inputInfo{
-                               {1, 1073741816},          // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
+                               {1, 1073741817},          // ZERO R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
                                 {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
                         },
                 },
@@ -25442,7 +25435,7 @@ var opcodeTable = [...]opInfo{
                 asm:            loong64.AMOVV,
                 reg: regInfo{
                         inputs: []inputInfo{
-                               {1, 1073741816},          // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
+                               {1, 1073741817},          // ZERO R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
                                 {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
                         },
                 },
@@ -25482,7 +25475,7 @@ var opcodeTable = [...]opInfo{
                 reg: regInfo{
                         inputs: []inputInfo{
                                 {1, 1073741816},          // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
-                               {2, 1073741816},          // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
+                               {2, 1073741817},          // ZERO R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
                                 {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
                         },
                 },
@@ -25494,7 +25487,7 @@ var opcodeTable = [...]opInfo{
                 reg: regInfo{
                         inputs: []inputInfo{
                                 {1, 1073741816},          // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
-                               {2, 1073741816},          // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
+                               {2, 1073741817},          // ZERO R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
                                 {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
                         },
                 },
@@ -25506,7 +25499,7 @@ var opcodeTable = [...]opInfo{
                 reg: regInfo{
                         inputs: []inputInfo{
                                 {1, 1073741816},          // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
-                               {2, 1073741816},          // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
+                               {2, 1073741817},          // ZERO R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
                                 {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
                         },
                 },
@@ -25518,7 +25511,7 @@ var opcodeTable = [...]opInfo{
                 reg: regInfo{
                         inputs: []inputInfo{
                                 {1, 1073741816},          // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
-                               {2, 1073741816},          // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
+                               {2, 1073741817},          // ZERO R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
                                 {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
                         },
                 },
@@ -25547,102 +25540,6 @@ var opcodeTable = [...]opInfo{
                         },
                 },
         },
-       {
-               name:           "MOVBstorezero",
-               auxType:        auxSymOff,
-               argLen:         2,
-               faultOnNilArg0: true,
-               symEffect:      SymWrite,
-               asm:            loong64.AMOVB,
-               reg: regInfo{
-                       inputs: []inputInfo{
-                               {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
-                       },
-               },
-       },
-       {
-               name:           "MOVHstorezero",
-               auxType:        auxSymOff,
-               argLen:         2,
-               faultOnNilArg0: true,
-               symEffect:      SymWrite,
-               asm:            loong64.AMOVH,
-               reg: regInfo{
-                       inputs: []inputInfo{
-                               {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
-                       },
-               },
-       },
-       {
-               name:           "MOVWstorezero",
-               auxType:        auxSymOff,
-               argLen:         2,
-               faultOnNilArg0: true,
-               symEffect:      SymWrite,
-               asm:            loong64.AMOVW,
-               reg: regInfo{
-                       inputs: []inputInfo{
-                               {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
-                       },
-               },
-       },
-       {
-               name:           "MOVVstorezero",
-               auxType:        auxSymOff,
-               argLen:         2,
-               faultOnNilArg0: true,
-               symEffect:      SymWrite,
-               asm:            loong64.AMOVV,
-               reg: regInfo{
-                       inputs: []inputInfo{
-                               {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
-                       },
-               },
-       },
-       {
-               name:   "MOVBstorezeroidx",
-               argLen: 3,
-               asm:    loong64.AMOVB,
-               reg: regInfo{
-                       inputs: []inputInfo{
-                               {1, 1073741816},          // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
-                               {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
-                       },
-               },
-       },
-       {
-               name:   "MOVHstorezeroidx",
-               argLen: 3,
-               asm:    loong64.AMOVH,
-               reg: regInfo{
-                       inputs: []inputInfo{
-                               {1, 1073741816},          // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
-                               {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
-                       },
-               },
-       },
-       {
-               name:   "MOVWstorezeroidx",
-               argLen: 3,
-               asm:    loong64.AMOVW,
-               reg: regInfo{
-                       inputs: []inputInfo{
-                               {1, 1073741816},          // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
-                               {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
-                       },
-               },
-       },
-       {
-               name:   "MOVVstorezeroidx",
-               argLen: 3,
-               asm:    loong64.AMOVV,
-               reg: regInfo{
-                       inputs: []inputInfo{
-                               {1, 1073741816},          // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
-                               {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
-                       },
-               },
-       },
         {
                 name:   "MOVWfpgp",
                 argLen: 1,
@@ -26573,13 +26470,20 @@ var opcodeTable = [...]opInfo{
                 reg: regInfo{
                         inputs: []inputInfo{
                                 {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
-                               {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
+                               {1, 1073741817}, // ZERO R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
                         },
                         outputs: []outputInfo{
                                 {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
                         },
                 },
         },
+       {
+               name:      "ZERO",
+               argLen:    0,
+               zeroWidth: true,
+               fixedReg:  true,
+               reg:       regInfo{},
+       },
  
         {
                 name:        "ADD",
@@ -43067,7 +42971,7 @@ var specialRegMaskARM64 = regMask(0)
  var framepointerRegARM64 = int8(-1)
  var linkRegARM64 = int8(28)
  var registersLOONG64 = [...]Register{
-       {0, loong64.REG_R0, "R0"},
+       {0, loong64.REGZERO, "ZERO"},
         {1, loong64.REG_R1, "R1"},
         {2, loong64.REGSP, "SP"},
         {3, loong64.REG_R4, "R4"},
diff --git a/src/cmd/compile/internal/ssa/regalloc.go b/src/cmd/compile/internal/ssa/regalloc.go

index 43669fd143c4d6b3695adbd81b7c804359cf3819..39769779cec64dce4d44f6da6f4e1b283c0a9969 100644 (file)
--- a/src/cmd/compile/internal/ssa/regalloc.go
+++ b/src/cmd/compile/internal/ssa/regalloc.go
@@ -1407,7 +1407,7 @@ func (s *regAllocState) regalloc(f *Func) {
                                 case OpSB:
                                         s.assignReg(s.SBReg, v, v)
                                         s.sb = v.ID
-                               case OpARM64ZERO:
+                               case OpARM64ZERO, OpLOONG64ZERO:
                                         s.assignReg(s.ZeroIntReg, v, v)
                                 default:
                                         f.Fatalf("unknown fixed-register op %s", v)
diff --git a/src/cmd/compile/internal/ssa/rewriteLOONG64.go b/src/cmd/compile/internal/ssa/rewriteLOONG64.go

index c688409657099c52702cebffec2efd4b5140c493..e36ac4f78a75b78f7f1f2e58d7006aa1180c765e 100644 (file)
--- a/src/cmd/compile/internal/ssa/rewriteLOONG64.go
+++ b/src/cmd/compile/internal/ssa/rewriteLOONG64.go
@@ -356,10 +356,6 @@ func rewriteValueLOONG64(v *Value) bool {
                 return rewriteValueLOONG64_OpLOONG64MOVBstore(v)
         case OpLOONG64MOVBstoreidx:
                 return rewriteValueLOONG64_OpLOONG64MOVBstoreidx(v)
-       case OpLOONG64MOVBstorezero:
-               return rewriteValueLOONG64_OpLOONG64MOVBstorezero(v)
-       case OpLOONG64MOVBstorezeroidx:
-               return rewriteValueLOONG64_OpLOONG64MOVBstorezeroidx(v)
         case OpLOONG64MOVDload:
                 return rewriteValueLOONG64_OpLOONG64MOVDload(v)
         case OpLOONG64MOVDloadidx:
@@ -392,10 +388,6 @@ func rewriteValueLOONG64(v *Value) bool {
                 return rewriteValueLOONG64_OpLOONG64MOVHstore(v)
         case OpLOONG64MOVHstoreidx:
                 return rewriteValueLOONG64_OpLOONG64MOVHstoreidx(v)
-       case OpLOONG64MOVHstorezero:
-               return rewriteValueLOONG64_OpLOONG64MOVHstorezero(v)
-       case OpLOONG64MOVHstorezeroidx:
-               return rewriteValueLOONG64_OpLOONG64MOVHstorezeroidx(v)
         case OpLOONG64MOVVload:
                 return rewriteValueLOONG64_OpLOONG64MOVVload(v)
         case OpLOONG64MOVVloadidx:
@@ -408,10 +400,6 @@ func rewriteValueLOONG64(v *Value) bool {
                 return rewriteValueLOONG64_OpLOONG64MOVVstore(v)
         case OpLOONG64MOVVstoreidx:
                 return rewriteValueLOONG64_OpLOONG64MOVVstoreidx(v)
-       case OpLOONG64MOVVstorezero:
-               return rewriteValueLOONG64_OpLOONG64MOVVstorezero(v)
-       case OpLOONG64MOVVstorezeroidx:
-               return rewriteValueLOONG64_OpLOONG64MOVVstorezeroidx(v)
         case OpLOONG64MOVWUload:
                 return rewriteValueLOONG64_OpLOONG64MOVWUload(v)
         case OpLOONG64MOVWUloadidx:
@@ -428,10 +416,6 @@ func rewriteValueLOONG64(v *Value) bool {
                 return rewriteValueLOONG64_OpLOONG64MOVWstore(v)
         case OpLOONG64MOVWstoreidx:
                 return rewriteValueLOONG64_OpLOONG64MOVWstoreidx(v)
-       case OpLOONG64MOVWstorezero:
-               return rewriteValueLOONG64_OpLOONG64MOVWstorezero(v)
-       case OpLOONG64MOVWstorezeroidx:
-               return rewriteValueLOONG64_OpLOONG64MOVWstorezeroidx(v)
         case OpLOONG64MULV:
                 return rewriteValueLOONG64_OpLOONG64MULV(v)
         case OpLOONG64NEGV:
@@ -2964,22 +2948,6 @@ func rewriteValueLOONG64_OpLOONG64MOVBstore(v *Value) bool {
                 v.AddArg3(ptr, x, mem)
                 return true
         }
-       // match: (MOVBstore [off] {sym} ptr (MOVVconst [0]) mem)
-       // result: (MOVBstorezero [off] {sym} ptr mem)
-       for {
-               off := auxIntToInt32(v.AuxInt)
-               sym := auxToSym(v.Aux)
-               ptr := v_0
-               if v_1.Op != OpLOONG64MOVVconst || auxIntToInt64(v_1.AuxInt) != 0 {
-                       break
-               }
-               mem := v_2
-               v.reset(OpLOONG64MOVBstorezero)
-               v.AuxInt = int32ToAuxInt(off)
-               v.Aux = symToAux(sym)
-               v.AddArg2(ptr, mem)
-               return true
-       }
         // match: (MOVBstore [off] {sym} (ADDV ptr idx) val mem)
         // cond: off == 0 && sym == nil
         // result: (MOVBstoreidx ptr idx val mem)
@@ -3045,130 +3013,6 @@ func rewriteValueLOONG64_OpLOONG64MOVBstoreidx(v *Value) bool {
                 v.AddArg3(idx, val, mem)
                 return true
         }
-       // match: (MOVBstoreidx ptr idx (MOVVconst [0]) mem)
-       // result: (MOVBstorezeroidx ptr idx mem)
-       for {
-               ptr := v_0
-               idx := v_1
-               if v_2.Op != OpLOONG64MOVVconst || auxIntToInt64(v_2.AuxInt) != 0 {
-                       break
-               }
-               mem := v_3
-               v.reset(OpLOONG64MOVBstorezeroidx)
-               v.AddArg3(ptr, idx, mem)
-               return true
-       }
-       return false
-}
-func rewriteValueLOONG64_OpLOONG64MOVBstorezero(v *Value) bool {
-       v_1 := v.Args[1]
-       v_0 := v.Args[0]
-       b := v.Block
-       config := b.Func.Config
-       // match: (MOVBstorezero [off1] {sym} (ADDVconst [off2] ptr) mem)
-       // cond: is32Bit(int64(off1)+off2) && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink)
-       // result: (MOVBstorezero [off1+int32(off2)] {sym} ptr mem)
-       for {
-               off1 := auxIntToInt32(v.AuxInt)
-               sym := auxToSym(v.Aux)
-               if v_0.Op != OpLOONG64ADDVconst {
-                       break
-               }
-               off2 := auxIntToInt64(v_0.AuxInt)
-               ptr := v_0.Args[0]
-               mem := v_1
-               if !(is32Bit(int64(off1)+off2) && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink)) {
-                       break
-               }
-               v.reset(OpLOONG64MOVBstorezero)
-               v.AuxInt = int32ToAuxInt(off1 + int32(off2))
-               v.Aux = symToAux(sym)
-               v.AddArg2(ptr, mem)
-               return true
-       }
-       // match: (MOVBstorezero [off1] {sym1} (MOVVaddr [off2] {sym2} ptr) mem)
-       // cond: canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2)) && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink)
-       // result: (MOVBstorezero [off1+int32(off2)] {mergeSym(sym1,sym2)} ptr mem)
-       for {
-               off1 := auxIntToInt32(v.AuxInt)
-               sym1 := auxToSym(v.Aux)
-               if v_0.Op != OpLOONG64MOVVaddr {
-                       break
-               }
-               off2 := auxIntToInt32(v_0.AuxInt)
-               sym2 := auxToSym(v_0.Aux)
-               ptr := v_0.Args[0]
-               mem := v_1
-               if !(canMergeSym(sym1, sym2) && is32Bit(int64(off1)+int64(off2)) && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink)) {
-                       break
-               }
-               v.reset(OpLOONG64MOVBstorezero)
-               v.AuxInt = int32ToAuxInt(off1 + int32(off2))
-               v.Aux = symToAux(mergeSym(sym1, sym2))
-               v.AddArg2(ptr, mem)
-               return true
-       }
-       // match: (MOVBstorezero [off] {sym} (ADDV ptr idx) mem)
-       // cond: off == 0 && sym == nil
-       // result: (MOVBstorezeroidx ptr idx mem)
-       for {
-               off := auxIntToInt32(v.AuxInt)
-               sym := auxToSym(v.Aux)
-               if v_0.Op != OpLOONG64ADDV {
-                       break
-               }
-               idx := v_0.Args[1]
-               ptr := v_0.Args[0]
-               mem := v_1
-               if !(off == 0 && sym == nil) {
-                       break
-               }
-               v.reset(OpLOONG64MOVBstorezeroidx)
-               v.AddArg3(ptr, idx, mem)
-               return true
-       }
-       return false
-}
-func rewriteValueLOONG64_OpLOONG64MOVBstorezeroidx(v *Value) bool {
-       v_2 := v.Args[2]
-       v_1 := v.Args[1]
-       v_0 := v.Args[0]
-       // match: (MOVBstorezeroidx ptr (MOVVconst [c]) mem)
-       // cond: is32Bit(c)
-       // result: (MOVBstorezero [int32(c)] ptr mem)
-       for {
-               ptr := v_0
-               if v_1.Op != OpLOONG64MOVVconst {
-                       break
-               }
-               c := auxIntToInt64(v_1.AuxInt)
-               mem := v_2
-               if !(is32Bit(c)) {
-                       break
-               }
-               v.reset(OpLOONG64MOVBstorezero)
-               v.AuxInt = int32ToAuxInt(int32(c))
-               v.AddArg2(ptr, mem)
-               return true
-       }
-       // match: (MOVBstorezeroidx (MOVVconst [c]) idx mem)
-       // cond: is32Bit(c)
-       // result: (MOVBstorezero [int32(c)] idx mem)
-       for {
-               if v_0.Op != OpLOONG64MOVVconst {
-                       break
-               }
-               c := auxIntToInt64(v_0.AuxInt)
-               idx := v_1
-               mem := v_2
-               if !(is32Bit(c)) {
-                       break
-               }
-               v.reset(OpLOONG64MOVBstorezero)
-               v.AuxInt = int32ToAuxInt(int32(c))
-               v.AddArg2(idx, mem)
-               return true
-       }
         return false
  }
  func rewriteValueLOONG64_OpLOONG64MOVDload(v *Value) bool {
@@ -4295,22 +4139,6 @@ func rewriteValueLOONG64_OpLOONG64MOVHstore(v *Value) bool {
                 v.AddArg3(ptr, x, mem)
                 return true
         }
-       // match: (MOVHstore [off] {sym} ptr (MOVVconst [0]) mem)
-       // result: (MOVHstorezero [off] {sym} ptr mem)
-       for {
-               off := auxIntToInt32(v.AuxInt)
-               sym := auxToSym(v.Aux)
-               ptr := v_0
-               if v_1.Op != OpLOONG64MOVVconst || auxIntToInt64(v_1.AuxInt) != 0 {
-                       break
-               }
-               mem := v_2
-               v.reset(OpLOONG64MOVHstorezero)
-               v.AuxInt = int32ToAuxInt(off)
-               v.Aux = symToAux(sym)
-               v.AddArg2(ptr, mem)
-               return true
-       }
         // match: (MOVHstore [off] {sym} (ADDV ptr idx) val mem)
         // cond: off == 0 && sym == nil
         // result: (MOVHstoreidx ptr idx val mem)
@@ -4376,130 +4204,6 @@ func rewriteValueLOONG64_OpLOONG64MOVHstoreidx(v *Value) bool {
                 v.AddArg3(idx, val, mem)
                 return true
         }
-       // match: (MOVHstoreidx ptr idx (MOVVconst [0]) mem)
-       // result: (MOVHstorezeroidx ptr idx mem)
-       for {
-               ptr := v_0
-               idx := v_1
-               if v_2.Op != OpLOONG64MOVVconst || auxIntToInt64(v_2.AuxInt) != 0 {
-                       break
-               }
-               mem := v_3
-               v.reset(OpLOONG64MOVHstorezeroidx)
-               v.AddArg3(ptr, idx, mem)
-               return true
-       }
-       return false
-}
-func rewriteValueLOONG64_OpLOONG64MOVHstorezero(v *Value) bool {
-       v_1 := v.Args[1]
-       v_0 := v.Args[0]
-       b := v.Block
-       config := b.Func.Config
-       // match: (MOVHstorezero [off1] {sym} (ADDVconst [off2] ptr) mem)
-       // cond: is32Bit(int64(off1)+off2) && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink)
-       // result: (MOVHstorezero [off1+int32(off2)] {sym} ptr mem)
-       for {
-               off1 := auxIntToInt32(v.AuxInt)
-               sym := auxToSym(v.Aux)
-               if v_0.Op != OpLOONG64ADDVconst {
-                       break
-               }
-               off2 := auxIntToInt64(v_0.AuxInt)
-               ptr := v_0.Args[0]
-               mem := v_1
-               if !(is32Bit(int64(off1)+off2) && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink)) {
-                       break
-               }
-               v.reset(OpLOONG64MOVHstorezero)
-               v.AuxInt = int32ToAuxInt(off1 + int32(off2))
-               v.Aux = symToAux(sym)
-               v.AddArg2(ptr, mem)
-               return true
-       }
-       // match: (MOVHstorezero [off1] {sym1} (MOVVaddr [off2] {sym2} ptr) mem)
-       // cond: canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2)) && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink)
-       // result: (MOVHstorezero [off1+int32(off2)] {mergeSym(sym1,sym2)} ptr mem)
-       for {
-               off1 := auxIntToInt32(v.AuxInt)
-               sym1 := auxToSym(v.Aux)
-               if v_0.Op != OpLOONG64MOVVaddr {
-                       break
-               }
-               off2 := auxIntToInt32(v_0.AuxInt)
-               sym2 := auxToSym(v_0.Aux)
-               ptr := v_0.Args[0]
-               mem := v_1
-               if !(canMergeSym(sym1, sym2) && is32Bit(int64(off1)+int64(off2)) && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink)) {
-                       break
-               }
-               v.reset(OpLOONG64MOVHstorezero)
-               v.AuxInt = int32ToAuxInt(off1 + int32(off2))
-               v.Aux = symToAux(mergeSym(sym1, sym2))
-               v.AddArg2(ptr, mem)
-               return true
-       }
-       // match: (MOVHstorezero [off] {sym} (ADDV ptr idx) mem)
-       // cond: off == 0 && sym == nil
-       // result: (MOVHstorezeroidx ptr idx mem)
-       for {
-               off := auxIntToInt32(v.AuxInt)
-               sym := auxToSym(v.Aux)
-               if v_0.Op != OpLOONG64ADDV {
-                       break
-               }
-               idx := v_0.Args[1]
-               ptr := v_0.Args[0]
-               mem := v_1
-               if !(off == 0 && sym == nil) {
-                       break
-               }
-               v.reset(OpLOONG64MOVHstorezeroidx)
-               v.AddArg3(ptr, idx, mem)
-               return true
-       }
-       return false
-}
-func rewriteValueLOONG64_OpLOONG64MOVHstorezeroidx(v *Value) bool {
-       v_2 := v.Args[2]
-       v_1 := v.Args[1]
-       v_0 := v.Args[0]
-       // match: (MOVHstorezeroidx ptr (MOVVconst [c]) mem)
-       // cond: is32Bit(c)
-       // result: (MOVHstorezero [int32(c)] ptr mem)
-       for {
-               ptr := v_0
-               if v_1.Op != OpLOONG64MOVVconst {
-                       break
-               }
-               c := auxIntToInt64(v_1.AuxInt)
-               mem := v_2
-               if !(is32Bit(c)) {
-                       break
-               }
-               v.reset(OpLOONG64MOVHstorezero)
-               v.AuxInt = int32ToAuxInt(int32(c))
-               v.AddArg2(ptr, mem)
-               return true
-       }
-       // match: (MOVHstorezeroidx (MOVVconst [c]) idx mem)
-       // cond: is32Bit(c)
-       // result: (MOVHstorezero [int32(c)] idx mem)
-       for {
-               if v_0.Op != OpLOONG64MOVVconst {
-                       break
-               }
-               c := auxIntToInt64(v_0.AuxInt)
-               idx := v_1
-               mem := v_2
-               if !(is32Bit(c)) {
-                       break
-               }
-               v.reset(OpLOONG64MOVHstorezero)
-               v.AuxInt = int32ToAuxInt(int32(c))
-               v.AddArg2(idx, mem)
-               return true
-       }
         return false
  }
  func rewriteValueLOONG64_OpLOONG64MOVVload(v *Value) bool {
@@ -4740,22 +4444,6 @@ func rewriteValueLOONG64_OpLOONG64MOVVstore(v *Value) bool {
                 v.AddArg3(ptr, val, mem)
                 return true
         }
-       // match: (MOVVstore [off] {sym} ptr (MOVVconst [0]) mem)
-       // result: (MOVVstorezero [off] {sym} ptr mem)
-       for {
-               off := auxIntToInt32(v.AuxInt)
-               sym := auxToSym(v.Aux)
-               ptr := v_0
-               if v_1.Op != OpLOONG64MOVVconst || auxIntToInt64(v_1.AuxInt) != 0 {
-                       break
-               }
-               mem := v_2
-               v.reset(OpLOONG64MOVVstorezero)
-               v.AuxInt = int32ToAuxInt(off)
-               v.Aux = symToAux(sym)
-               v.AddArg2(ptr, mem)
-               return true
-       }
         // match: (MOVVstore [off] {sym} (ADDV ptr idx) val mem)
         // cond: off == 0 && sym == nil
         // result: (MOVVstoreidx ptr idx val mem)
@@ -4821,130 +4509,6 @@ func rewriteValueLOONG64_OpLOONG64MOVVstoreidx(v *Value) bool {
                 v.AddArg3(idx, val, mem)
                 return true
         }
-       // match: (MOVVstoreidx ptr idx (MOVVconst [0]) mem)
-       // result: (MOVVstorezeroidx ptr idx mem)
-       for {
-               ptr := v_0
-               idx := v_1
-               if v_2.Op != OpLOONG64MOVVconst || auxIntToInt64(v_2.AuxInt) != 0 {
-                       break
-               }
-               mem := v_3
-               v.reset(OpLOONG64MOVVstorezeroidx)
-               v.AddArg3(ptr, idx, mem)
-               return true
-       }
-       return false
-}
-func rewriteValueLOONG64_OpLOONG64MOVVstorezero(v *Value) bool {
-       v_1 := v.Args[1]
-       v_0 := v.Args[0]
-       b := v.Block
-       config := b.Func.Config
-       // match: (MOVVstorezero [off1] {sym} (ADDVconst [off2] ptr) mem)
-       // cond: is32Bit(int64(off1)+off2) && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink)
-       // result: (MOVVstorezero [off1+int32(off2)] {sym} ptr mem)
-       for {
-               off1 := auxIntToInt32(v.AuxInt)
-               sym := auxToSym(v.Aux)
-               if v_0.Op != OpLOONG64ADDVconst {
-                       break
-               }
-               off2 := auxIntToInt64(v_0.AuxInt)
-               ptr := v_0.Args[0]
-               mem := v_1
-               if !(is32Bit(int64(off1)+off2) && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink)) {
-                       break
-               }
-               v.reset(OpLOONG64MOVVstorezero)
-               v.AuxInt = int32ToAuxInt(off1 + int32(off2))
-               v.Aux = symToAux(sym)
-               v.AddArg2(ptr, mem)
-               return true
-       }
-       // match: (MOVVstorezero [off1] {sym1} (MOVVaddr [off2] {sym2} ptr) mem)
-       // cond: canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2)) && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink)
-       // result: (MOVVstorezero [off1+int32(off2)] {mergeSym(sym1,sym2)} ptr mem)
-       for {
-               off1 := auxIntToInt32(v.AuxInt)
-               sym1 := auxToSym(v.Aux)
-               if v_0.Op != OpLOONG64MOVVaddr {
-                       break
-               }
-               off2 := auxIntToInt32(v_0.AuxInt)
-               sym2 := auxToSym(v_0.Aux)
-               ptr := v_0.Args[0]
-               mem := v_1
-               if !(canMergeSym(sym1, sym2) && is32Bit(int64(off1)+int64(off2)) && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink)) {
-                       break
-               }
-               v.reset(OpLOONG64MOVVstorezero)
-               v.AuxInt = int32ToAuxInt(off1 + int32(off2))
-               v.Aux = symToAux(mergeSym(sym1, sym2))
-               v.AddArg2(ptr, mem)
-               return true
-       }
-       // match: (MOVVstorezero [off] {sym} (ADDV ptr idx) mem)
-       // cond: off == 0 && sym == nil
-       // result: (MOVVstorezeroidx ptr idx mem)
-       for {
-               off := auxIntToInt32(v.AuxInt)
-               sym := auxToSym(v.Aux)
-               if v_0.Op != OpLOONG64ADDV {
-                       break
-               }
-               idx := v_0.Args[1]
-               ptr := v_0.Args[0]
-               mem := v_1
-               if !(off == 0 && sym == nil) {
-                       break
-               }
-               v.reset(OpLOONG64MOVVstorezeroidx)
-               v.AddArg3(ptr, idx, mem)
-               return true
-       }
-       return false
-}
-func rewriteValueLOONG64_OpLOONG64MOVVstorezeroidx(v *Value) bool {
-       v_2 := v.Args[2]
-       v_1 := v.Args[1]
-       v_0 := v.Args[0]
-       // match: (MOVVstorezeroidx ptr (MOVVconst [c]) mem)
-       // cond: is32Bit(c)
-       // result: (MOVVstorezero [int32(c)] ptr mem)
-       for {
-               ptr := v_0
-               if v_1.Op != OpLOONG64MOVVconst {
-                       break
-               }
-               c := auxIntToInt64(v_1.AuxInt)
-               mem := v_2
-               if !(is32Bit(c)) {
-                       break
-               }
-               v.reset(OpLOONG64MOVVstorezero)
-               v.AuxInt = int32ToAuxInt(int32(c))
-               v.AddArg2(ptr, mem)
-               return true
-       }
-       // match: (MOVVstorezeroidx (MOVVconst [c]) idx mem)
-       // cond: is32Bit(c)
-       // result: (MOVVstorezero [int32(c)] idx mem)
-       for {
-               if v_0.Op != OpLOONG64MOVVconst {
-                       break
-               }
-               c := auxIntToInt64(v_0.AuxInt)
-               idx := v_1
-               mem := v_2
-               if !(is32Bit(c)) {
-                       break
-               }
-               v.reset(OpLOONG64MOVVstorezero)
-               v.AuxInt = int32ToAuxInt(int32(c))
-               v.AddArg2(idx, mem)
-               return true
-       }
         return false
  }
  func rewriteValueLOONG64_OpLOONG64MOVWUload(v *Value) bool {
@@ -5636,22 +5200,6 @@ func rewriteValueLOONG64_OpLOONG64MOVWstore(v *Value) bool {
                 v.AddArg3(ptr, x, mem)
                 return true
         }
-       // match: (MOVWstore [off] {sym} ptr (MOVVconst [0]) mem)
-       // result: (MOVWstorezero [off] {sym} ptr mem)
-       for {
-               off := auxIntToInt32(v.AuxInt)
-               sym := auxToSym(v.Aux)
-               ptr := v_0
-               if v_1.Op != OpLOONG64MOVVconst || auxIntToInt64(v_1.AuxInt) != 0 {
-                       break
-               }
-               mem := v_2
-               v.reset(OpLOONG64MOVWstorezero)
-               v.AuxInt = int32ToAuxInt(off)
-               v.Aux = symToAux(sym)
-               v.AddArg2(ptr, mem)
-               return true
-       }
         // match: (MOVWstore [off] {sym} (ADDV ptr idx) val mem)
         // cond: off == 0 && sym == nil
         // result: (MOVWstoreidx ptr idx val mem)
@@ -5717,130 +5265,6 @@ func rewriteValueLOONG64_OpLOONG64MOVWstoreidx(v *Value) bool {
                 v.AddArg3(idx, val, mem)
                 return true
         }
-       // match: (MOVWstoreidx ptr idx (MOVVconst [0]) mem)
-       // result: (MOVWstorezeroidx ptr idx mem)
-       for {
-               ptr := v_0
-               idx := v_1
-               if v_2.Op != OpLOONG64MOVVconst || auxIntToInt64(v_2.AuxInt) != 0 {
-                       break
-               }
-               mem := v_3
-               v.reset(OpLOONG64MOVWstorezeroidx)
-               v.AddArg3(ptr, idx, mem)
-               return true
-       }
-       return false
-}
-func rewriteValueLOONG64_OpLOONG64MOVWstorezero(v *Value) bool {
-       v_1 := v.Args[1]
-       v_0 := v.Args[0]
-       b := v.Block
-       config := b.Func.Config
-       // match: (MOVWstorezero [off1] {sym} (ADDVconst [off2] ptr) mem)
-       // cond: is32Bit(int64(off1)+off2) && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink)
-       // result: (MOVWstorezero [off1+int32(off2)] {sym} ptr mem)
-       for {
-               off1 := auxIntToInt32(v.AuxInt)
-               sym := auxToSym(v.Aux)
-               if v_0.Op != OpLOONG64ADDVconst {
-                       break
-               }
-               off2 := auxIntToInt64(v_0.AuxInt)
-               ptr := v_0.Args[0]
-               mem := v_1
-               if !(is32Bit(int64(off1)+off2) && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink)) {
-                       break
-               }
-               v.reset(OpLOONG64MOVWstorezero)
-               v.AuxInt = int32ToAuxInt(off1 + int32(off2))
-               v.Aux = symToAux(sym)
-               v.AddArg2(ptr, mem)
-               return true
-       }
-       // match: (MOVWstorezero [off1] {sym1} (MOVVaddr [off2] {sym2} ptr) mem)
-       // cond: canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2)) && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink)
-       // result: (MOVWstorezero [off1+int32(off2)] {mergeSym(sym1,sym2)} ptr mem)
-       for {
-               off1 := auxIntToInt32(v.AuxInt)
-               sym1 := auxToSym(v.Aux)
-               if v_0.Op != OpLOONG64MOVVaddr {
-                       break
-               }
-               off2 := auxIntToInt32(v_0.AuxInt)
-               sym2 := auxToSym(v_0.Aux)
-               ptr := v_0.Args[0]
-               mem := v_1
-               if !(canMergeSym(sym1, sym2) && is32Bit(int64(off1)+int64(off2)) && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink)) {
-                       break
-               }
-               v.reset(OpLOONG64MOVWstorezero)
-               v.AuxInt = int32ToAuxInt(off1 + int32(off2))
-               v.Aux = symToAux(mergeSym(sym1, sym2))
-               v.AddArg2(ptr, mem)
-               return true
-       }
-       // match: (MOVWstorezero [off] {sym} (ADDV ptr idx) mem)
-       // cond: off == 0 && sym == nil
-       // result: (MOVWstorezeroidx ptr idx mem)
-       for {
-               off := auxIntToInt32(v.AuxInt)
-               sym := auxToSym(v.Aux)
-               if v_0.Op != OpLOONG64ADDV {
-                       break
-               }
-               idx := v_0.Args[1]
-               ptr := v_0.Args[0]
-               mem := v_1
-               if !(off == 0 && sym == nil) {
-                       break
-               }
-               v.reset(OpLOONG64MOVWstorezeroidx)
-               v.AddArg3(ptr, idx, mem)
-               return true
-       }
-       return false
-}
-func rewriteValueLOONG64_OpLOONG64MOVWstorezeroidx(v *Value) bool {
-       v_2 := v.Args[2]
-       v_1 := v.Args[1]
-       v_0 := v.Args[0]
-       // match: (MOVWstorezeroidx ptr (MOVVconst [c]) mem)
-       // cond: is32Bit(c)
-       // result: (MOVWstorezero [int32(c)] ptr mem)
-       for {
-               ptr := v_0
-               if v_1.Op != OpLOONG64MOVVconst {
-                       break
-               }
-               c := auxIntToInt64(v_1.AuxInt)
-               mem := v_2
-               if !(is32Bit(c)) {
-                       break
-               }
-               v.reset(OpLOONG64MOVWstorezero)
-               v.AuxInt = int32ToAuxInt(int32(c))
-               v.AddArg2(ptr, mem)
-               return true
-       }
-       // match: (MOVWstorezeroidx (MOVVconst [c]) idx mem)
-       // cond: is32Bit(c)
-       // result: (MOVWstorezero [int32(c)] idx mem)
-       for {
-               if v_0.Op != OpLOONG64MOVVconst {
-                       break
-               }
-               c := auxIntToInt64(v_0.AuxInt)
-               idx := v_1
-               mem := v_2
-               if !(is32Bit(c)) {
-                       break
-               }
-               v.reset(OpLOONG64MOVWstorezero)
-               v.AuxInt = int32ToAuxInt(int32(c))
-               v.AddArg2(idx, mem)
-               return true
-       }
         return false
  }
  func rewriteValueLOONG64_OpLOONG64MULV(v *Value) bool {
diff --git a/src/cmd/compile/internal/ssa/rewriteLOONG64latelower.go b/src/cmd/compile/internal/ssa/rewriteLOONG64latelower.go

index 60ba120e48dad67a0ddaf07432e033c4475c8da9..02930e5e834bae5ffe270b87cee029f02e684325 100644 (file)
--- a/src/cmd/compile/internal/ssa/rewriteLOONG64latelower.go
+++ b/src/cmd/compile/internal/ssa/rewriteLOONG64latelower.go
@@ -4,11 +4,25 @@ package ssa
  
  func rewriteValueLOONG64latelower(v *Value) bool {
         switch v.Op {
+       case OpLOONG64MOVVconst:
+               return rewriteValueLOONG64latelower_OpLOONG64MOVVconst(v)
         case OpLOONG64SLLVconst:
                 return rewriteValueLOONG64latelower_OpLOONG64SLLVconst(v)
         }
         return false
  }
+func rewriteValueLOONG64latelower_OpLOONG64MOVVconst(v *Value) bool {
+       // match: (MOVVconst [0])
+       // result: (ZERO)
+       for {
+               if auxIntToInt64(v.AuxInt) != 0 {
+                       break
+               }
+               v.reset(OpLOONG64ZERO)
+               return true
+       }
+       return false
+}
  func rewriteValueLOONG64latelower_OpLOONG64SLLVconst(v *Value) bool {
         v_0 := v.Args[0]
         // match: (SLLVconst [1] x)
diff --git a/test/codegen/bitfield.go b/test/codegen/bitfield.go

index 6374d70650ce5502f7397a4bca967a2a1e3eff1b..51221266e1097b061ee599a0df872f04e77e332f 100644 (file)
--- a/test/codegen/bitfield.go
+++ b/test/codegen/bitfield.go
@@ -373,6 +373,6 @@ func shift(x uint32, y uint16, z uint8) uint64 {
         // loong64:-`MOVBU`,-`SRLV\t[$]8`
         c := uint64(z) >> 8
         // arm64:`MOVD\tZR`,-`ADD\tR[0-9]+>>16`,-`ADD\tR[0-9]+>>8`,
-       // loong64:`MOVV\t[$]0`,-`ADDVU`
+       // loong64:`MOVV\tR0`,-`ADDVU`
         return a + b + c
  }
diff --git a/test/codegen/multiply.go b/test/codegen/multiply.go

index dc2910dab7b6fb5e7f27189b5156df87bd7c3a88..8c408cbfbabc19820271362e1cfc0b3c7822a868 100644 (file)
--- a/test/codegen/multiply.go
+++ b/test/codegen/multiply.go
@@ -12,7 +12,7 @@ package codegen
  func m0(x int64) int64 {
         // amd64: "XORL"
         // arm64: "MOVD\tZR"
-       // loong64: "MOVV\t[$]0"
+       // loong64: "MOVV\tR0"
         return x * 0
  }
  func m2(x int64) int64 {
diff --git a/test/codegen/shift.go b/test/codegen/shift.go

index 3ab0fcfabc9e99ff17dd4c3f84da020844c36de3..1c71b0f3efd90a800fd12599cb753b4c254691a5 100644 (file)
--- a/test/codegen/shift.go
+++ b/test/codegen/shift.go
@@ -25,19 +25,19 @@ func rshConst64Ux64(v uint64) uint64 {
  }
  
  func rshConst64Ux64Overflow32(v uint32) uint64 {
-       // loong64:"MOVV\t\\$0,",-"SRL\t"
+       // loong64:"MOVV\tR0,",-"SRL\t"
         // riscv64:"MOV\t\\$0,",-"SRL"
         return uint64(v) >> 32
  }
  
  func rshConst64Ux64Overflow16(v uint16) uint64 {
-       // loong64:"MOVV\t\\$0,",-"SRLV"
+       // loong64:"MOVV\tR0,",-"SRLV"
         // riscv64:"MOV\t\\$0,",-"SRL"
         return uint64(v) >> 16
  }
  
  func rshConst64Ux64Overflow8(v uint8) uint64 {
-       // loong64:"MOVV\t\\$0,",-"SRLV"
+       // loong64:"MOVV\tR0,",-"SRLV"
         // riscv64:"MOV\t\\$0,",-"SRL"
         return uint64(v) >> 8
  }
author	limeidan <limeidan@loongson.cn>
	Tue, 19 Aug 2025 11:16:31 +0000 (19:16 +0800)
committer	Gopher Robot <gobot@golang.org>
	Thu, 21 Aug 2025 18:23:05 +0000 (11:23 -0700)
src/cmd/compile/internal/loong64/ssa.go		patch \| blob \| history
src/cmd/compile/internal/ssa/_gen/LOONG64.rules		patch \| blob \| history
src/cmd/compile/internal/ssa/_gen/LOONG64Ops.go		patch \| blob \| history
src/cmd/compile/internal/ssa/_gen/LOONG64latelower.rules		patch \| blob \| history
src/cmd/compile/internal/ssa/opGen.go		patch \| blob \| history
src/cmd/compile/internal/ssa/regalloc.go		patch \| blob \| history
src/cmd/compile/internal/ssa/rewriteLOONG64.go		patch \| blob \| history
src/cmd/compile/internal/ssa/rewriteLOONG64latelower.go		patch \| blob \| history
test/codegen/bitfield.go		patch \| blob \| history
test/codegen/multiply.go		patch \| blob \| history
test/codegen/shift.go		patch \| blob \| history