[dev.simd] cmd/compile: add fp1gp1fp1 register mask for AMD64

This is paired with a matching simdgen CL 682679

Change-Id: Id494d40b5e64b723a47c1682b71e523a77b0eb87
Reviewed-on: https://go-review.googlesource.com/c/go/+/682656
LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com>
Reviewed-by: Cherry Mui <cherryyz@google.com>

diff --git a/src/cmd/compile/internal/ssa/_gen/AMD64Ops.go b/src/cmd/compile/internal/ssa/_gen/AMD64Ops.go
index 99d0d0ec740063c7752044c00c67fafcb46ffd00..e2cbc65957c75fb52c4cc044f4564115c6a2095e 100644 (file)
--- a/src/cmd/compile/internal/ssa/_gen/AMD64Ops.go
+++ b/src/cmd/compile/internal/ssa/_gen/AMD64Ops.go
@@ -182,14 +182,15 @@ func init() {
                fpstore    = regInfo{inputs: []regMask{gpspsb, fp, 0}}
                fpstoreidx = regInfo{inputs: []regMask{gpspsb, gpsp, fp, 0}}
 
-               fp1k1    = regInfo{inputs: fponly, outputs: maskonly}
-               k1fp1    = regInfo{inputs: maskonly, outputs: fponly}
-               fp2k1    = regInfo{inputs: []regMask{fp, fp}, outputs: maskonly}
-               fp1k1fp1 = regInfo{inputs: []regMask{fp, mask}, outputs: fponly}
-               fp2k1fp1 = regInfo{inputs: []regMask{fp, fp, mask}, outputs: fponly}
-               fp2k1k1  = regInfo{inputs: []regMask{fp, fp, mask}, outputs: maskonly}
-               fp3fp1   = regInfo{inputs: []regMask{fp, fp, fp}, outputs: fponly}
-               fp3k1fp1 = regInfo{inputs: []regMask{fp, fp, fp, mask}, outputs: fponly}
+               fp1k1     = regInfo{inputs: fponly, outputs: maskonly}
+               k1fp1     = regInfo{inputs: maskonly, outputs: fponly}
+               fp2k1     = regInfo{inputs: []regMask{fp, fp}, outputs: maskonly}
+               fp1k1fp1  = regInfo{inputs: []regMask{fp, mask}, outputs: fponly}
+               fp2k1fp1  = regInfo{inputs: []regMask{fp, fp, mask}, outputs: fponly}
+               fp2k1k1   = regInfo{inputs: []regMask{fp, fp, mask}, outputs: maskonly}
+               fp3fp1    = regInfo{inputs: []regMask{fp, fp, fp}, outputs: fponly}
+               fp3k1fp1  = regInfo{inputs: []regMask{fp, fp, fp, mask}, outputs: fponly}
+               fp1gp1fp1 = regInfo{inputs: []regMask{fp, gp}, outputs: fponly}
 
                prefreg = regInfo{inputs: []regMask{gpspsbg}}
        )
@@ -1300,7 +1301,7 @@ func init() {
                pkg:                "cmd/internal/obj/x86",
                genfile:            "../../amd64/ssa.go",
                genSIMDfile:        "../../amd64/simdssa.go",
-               ops:                append(AMD64ops, simdAMD64Ops(fp11, fp21, fp2k1, fp1k1fp1, fp2k1fp1, fp2k1k1, fp3fp1, fp3k1fp1)...), // AMD64ops,
+               ops:                append(AMD64ops, simdAMD64Ops(fp11, fp21, fp2k1, fp1k1fp1, fp2k1fp1, fp2k1k1, fp3fp1, fp3k1fp1, fp1gp1fp1)...), // AMD64ops,
                blocks:             AMD64blocks,
                regnames:           regNamesAMD64,
                ParamIntRegNames:   "AX BX CX DI SI R8 R9 R10 R11",

diff --git a/src/cmd/compile/internal/ssa/_gen/simdAMD64ops.go b/src/cmd/compile/internal/ssa/_gen/simdAMD64ops.go
index c46bc40443ff67fdc7f7898d31df2a0e21c28919..259f1eff2332b96a504032f622e433dfd7763896 100644 (file)
--- a/src/cmd/compile/internal/ssa/_gen/simdAMD64ops.go
+++ b/src/cmd/compile/internal/ssa/_gen/simdAMD64ops.go
@@ -1,7 +1,7 @@
 // Code generated by x/arch/internal/simdgen using 'go run . -xedPath $XED_PATH -o godefs -goroot $GOROOT go.yaml types.yaml categories.yaml'; DO NOT EDIT.
 package main
 
-func simdAMD64Ops(fp11, fp21, fp2k1, fp1k1fp1, fp2k1fp1, fp2k1k1, fp31, fp3k1fp1 regInfo) []opData {
+func simdAMD64Ops(fp11, fp21, fp2k1, fp1k1fp1, fp2k1fp1, fp2k1k1, fp31, fp3k1fp1, fp1gp1fp1 regInfo) []opData {
        return []opData{
                {name: "VADDPS512", argLength: 2, reg: fp21, asm: "VADDPS", commutative: true, typ: "Vec512", resultInArg0: false},
                {name: "VANDPS512", argLength: 2, reg: fp21, asm: "VANDPS", commutative: true, typ: "Vec512", resultInArg0: false},