[dev.simd] cmd/compile: remove VPADDD4

It is from my sample SIMD compilation, not used in the real thing.
The actual operation is VPADDD128.

Also clean up some of my XXX comments.

Change-Id: Ic20a9dd3c8531e25d88ba045ccef70cb856790d8
Reviewed-on: https://go-review.googlesource.com/c/go/+/698475
Reviewed-by: David Chase <drchase@google.com>
Reviewed-by: Junyang Shao <shaojunyang@google.com>
LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com>

diff --git a/src/cmd/compile/internal/amd64/ssa.go b/src/cmd/compile/internal/amd64/ssa.go
index 025e57d94dc259a91aad2ba762d8b51f1e367071..ec4eaaed03cbd1f533df27e656ca02ec57cbec5c 100644 (file)
--- a/src/cmd/compile/internal/amd64/ssa.go
+++ b/src/cmd/compile/internal/amd64/ssa.go
@@ -1708,19 +1708,11 @@ func ssaGenValue(s *ssagen.State, v *ssa.Value) {
                p.To.Type = obj.TYPE_REG
                p.To.Reg = v.Reg()
 
-       // XXX SIMD
-       // XXX may change depending on how we handle aliased registers
+       // SIMD ops
        case ssa.OpAMD64VZEROUPPER, ssa.OpAMD64VZEROALL:
                s.Prog(v.Op.Asm())
        case ssa.OpAMD64Zero128, ssa.OpAMD64Zero256, ssa.OpAMD64Zero512:
                // zero-width, no instruction generated
-       case ssa.OpAMD64VPADDD4:
-               p := s.Prog(v.Op.Asm())
-               p.From.Type = obj.TYPE_REG
-               p.From.Reg = simdReg(v.Args[0])
-               p.AddRestSourceReg(simdReg(v.Args[1]))
-               p.To.Type = obj.TYPE_REG
-               p.To.Reg = simdReg(v)
        case ssa.OpAMD64VMOVDQUload128, ssa.OpAMD64VMOVDQUload256, ssa.OpAMD64VMOVDQUload512, ssa.OpAMD64KMOVQload:
                p := s.Prog(v.Op.Asm())
                p.From.Type = obj.TYPE_MEM

diff --git a/src/cmd/compile/internal/ssa/_gen/AMD64.rules b/src/cmd/compile/internal/ssa/_gen/AMD64.rules
index adab859e7bcc1ae4823815016682e7128ae1ad48..913ddbf5596b94244cbb7858130178f23f002fd7 100644 (file)
--- a/src/cmd/compile/internal/ssa/_gen/AMD64.rules
+++ b/src/cmd/compile/internal/ssa/_gen/AMD64.rules
@@ -1639,7 +1639,7 @@
 // If we don't use the flags any more, just use the standard op.
 (Select0 a:(ADD(Q|L)constflags [c] x)) && a.Uses == 1 => (ADD(Q|L)const [c] x)
 
-// XXX SIMD
+// SIMD lowering rules
 
 // Mask loads
 (LoadMask8x16 <t> ptr mem) => (VPMOVMToVec8x16 <types.TypeVec128> (KMOVQload <t> ptr mem))

diff --git a/src/cmd/compile/internal/ssa/_gen/AMD64Ops.go b/src/cmd/compile/internal/ssa/_gen/AMD64Ops.go
index a25d91436d979c837f6fa1cb0ed4b6b2bddfcbc0..12be7cae4185d9d5b32a90db149256fb7bf9902c 100644 (file)
--- a/src/cmd/compile/internal/ssa/_gen/AMD64Ops.go
+++ b/src/cmd/compile/internal/ssa/_gen/AMD64Ops.go
@@ -1315,9 +1315,7 @@ func init() {
                // output[i] = (input[i] >> 7) & 1
                {name: "PMOVMSKB", argLength: 1, reg: fpgp, asm: "PMOVMSKB"},
 
-               // XXX SIMD
-               {name: "VPADDD4", argLength: 2, reg: fp21, asm: "VPADDD", commutative: true}, // arg0 + arg1
-
+               // SIMD ops
                {name: "VMOVDQUload128", argLength: 2, reg: fpload, asm: "VMOVDQU", aux: "SymOff", faultOnNilArg0: true, symEffect: "Read"},    // load from arg0+auxint+aux, arg1 = mem
                {name: "VMOVDQUstore128", argLength: 3, reg: fpstore, asm: "VMOVDQU", aux: "SymOff", faultOnNilArg0: true, symEffect: "Write"}, // store, *(arg0+auxint+aux) = arg1, arg2 = mem
 

diff --git a/src/cmd/compile/internal/ssa/opGen.go b/src/cmd/compile/internal/ssa/opGen.go
index 9314603ff205baf7b39308167f4f8c884a87f7d8..76b0f84f3576affa44cfaabe69bff9f59dbd4233 100644 (file)
--- a/src/cmd/compile/internal/ssa/opGen.go
+++ b/src/cmd/compile/internal/ssa/opGen.go
@@ -1165,7 +1165,6 @@ const (
        OpAMD64PSIGNB
        OpAMD64PCMPEQB
        OpAMD64PMOVMSKB
-       OpAMD64VPADDD4
        OpAMD64VMOVDQUload128
        OpAMD64VMOVDQUstore128
        OpAMD64VMOVDQUload256
@@ -18179,21 +18178,6 @@ var opcodeTable = [...]opInfo{
                        },
                },
        },
-       {
-               name:        "VPADDD4",
-               argLen:      2,
-               commutative: true,
-               asm:         x86.AVPADDD,
-               reg: regInfo{
-                       inputs: []inputInfo{
-                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
-                               {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
-                       },
-                       outputs: []outputInfo{
-                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
-                       },
-               },
-       },
        {
                name:           "VMOVDQUload128",
                auxType:        auxSymOff,