[dev.simd] all: merge master (924fe98) into dev.simd

Conflicts:

- src/cmd/compile/internal/amd64/ssa.go
- src/cmd/compile/internal/ssa/expand_calls.go
- src/cmd/compile/internal/ssagen/ssa.go
- src/internal/buildcfg/exp.go
- src/internal/cpu/cpu.go
- src/internal/cpu/cpu_x86.go
- src/runtime/mkpreempt.go
- src/runtime/preempt_amd64.go
- src/runtime/preempt_amd64.s

Merge List:

+ 2025-08-14 924fe98902 cmd/internal/obj/riscv: add encoding for compressed riscv64 instructions
+ 2025-08-13 320df537cc cmd/compile: emit classify instructions for infinity tests on riscv64
+ 2025-08-13 ca66f907dd cmd/compile: use generated loops instead of DUFFCOPY on amd64
+ 2025-08-13 4b1800e476 encoding/json/v2: cleanup error constructors
+ 2025-08-13 af8870708b encoding/json/v2: fix incorrect marshaling of NaN in float64 any
+ 2025-08-13 0a75e5a07b encoding/json/v2: fix wrong type with cyclic marshal error in map[string]any
+ 2025-08-13 de9b6f9875 cmd/pprof: update vendored github.com/google/pprof
+ 2025-08-13 674c5f0edd os/exec: fix incorrect expansion of ".." in LookPath on plan9
+ 2025-08-13 9bbea0f21a cmd/compile: during regalloc, fixedreg values are always available
+ 2025-08-13 08eef97500 runtime/trace: fix documentation typo
+ 2025-08-13 2fe5d51d04 internal/trace: fix wrong scope for Event.Range or EvGCSweepActive
+ 2025-08-13 9fcb87c352 cmd/compile: teach prove about len's & cap's max based on the element size
+ 2025-08-13 9763ece873 cmd/compile: absorb NEGV into branch on loong64
+ 2025-08-13 f10a82b76f all: update vendored dependencies [generated]
+ 2025-08-13 3bea95b277 cmd/link/internal/ld: remove OpenBSD buildid workaround
+ 2025-08-12 90b7d7aaa2 cmd/compile/internal: optimize multiplication use new operation 'ADDshiftLLV' on loong64
+ 2025-08-12 1b263fc604 runtime/race: restore previous version of LLVM TSAN on macOS
+ 2025-08-12 b266318cf7 cmd/compile/internal/ssa: use BEQ/BNE to optimize the combination of XOR and EQ/NE on loong64
+ 2025-08-12 adbf59525c internal/runtime/gc/scan: avoid -1 index when cache sizes unavailable
+ 2025-08-12 4e182db5fc Revert "cmd/compile: use generated loops instead of DUFFCOPY on amd64"
+ 2025-08-12 d2b3c1a504 internal/trace: clarify which StateTransition events have stacks
+ 2025-08-12 f63e12d0e0 internal/trace: fix Sync.ClockSnapshot comment
+ 2025-08-12 8e317da77d internal/trace: remove unused StateTransition.id field
+ 2025-08-12 f67d8ff34a internal/trace/tracev2: adjust comment for consistency
+ 2025-08-12 fe4d445c36 internal/trace/tracev2: fix EvSTWBegin comment to include stack ID
+ 2025-08-12 750789fab7 internal/trace/internal/testgen: fix missing stacks nframes arg
+ 2025-08-12 889ab74169 internal/runtime/gc/scan: import scan kernel from gclab [green tea]
+ 2025-08-12 182336bf05 net/http: fix data race in client
+ 2025-08-12 f04421ea9a cmd/compile: soften test for 74788
+ 2025-08-12 28aa529c99 cmd/compile: use generated loops instead of DUFFZERO on arm64
+ 2025-08-12 ec9e1176c3 cmd/compile: use generated loops instead of DUFFCOPY on amd64
+ 2025-08-12 d0a64f7969 Revert "cmd/compile/internal/ssa: Use transitive properties for len/cap"
+ 2025-08-12 00a7bdcb55 all: delete aliastypeparams GOEXPERIMENT
+ 2025-08-11 74421a305b Revert "cmd/compile: allow multi-field structs to be stored directly in interfaces"
+ 2025-08-11 c31359138c Revert "cmd/compile: allow StructSelect [x] of interface data fields for x>0"
+ 2025-08-11 7248995b60 Revert "cmd/compile: allow more args in StructMake folding rule"
+ 2025-08-11 caf9fc3ccd Revert "reflect: handle zero-sized fields of directly-stored structures correctly"
+ 2025-08-11 ce3f3e2ae7 cmd/link/internal/ld, internal/syscall/unix: use posix_fallocate on netbsd
+ 2025-08-11 3dbef65bf3 database/sql: allow drivers to override Scan behavior
+ 2025-08-11 2b804abf07 net: context aware Dialer.Dial functions
+ 2025-08-11 6abfe7b0de cmd/dist: require Go 1.24.6 as minimum bootstrap toolchain
+ 2025-08-11 691af6ca28 encoding/json: fix Indent trailing whitespace regression in goexperiment.jsonv2
+ 2025-08-11 925149da20 net/http: add example for CrossOriginProtection
+ 2025-08-11 cf4af0b2f3 encoding/json/v2: fix UnmarshalDecode regression with EOF
+ 2025-08-11 b096ddb9ea internal/runtime/maps: loop invariant code motion with h2(hash) by hand
+ 2025-08-11 a2431776eb net, os, file/filepath, syscall: use slices.Equal in tests
+ 2025-08-11 a7f05b38f7 cmd/compile: convert branch with zero to more optimal branch zero on loong64
+ 2025-08-11 1718828c81 internal/sync: warn about incorrect unsafe usage in HashTrieMap
+ 2025-08-11 084c0f8494 cmd/compile: allow InlMark operations to be speculatively executed
+ 2025-08-10 a62f72f7a7 cmd/compile/internal/ssa: optimise more branches with SGTconst/SGTUconst on loong64
+ 2025-08-08 fbac94a799 internal/sync: rename Store parameter from old to new
+ 2025-08-08 317be4cfeb cmd/compile/internal/staticinit: remove deadcode
+ 2025-08-08 bce5601cbb cmd/go: fix fips doc link
+ 2025-08-08 777d76c4f2 text/template: use sync.OnceValue for builtinFuncs
+ 2025-08-08 0201524c52 math: remove redundant infinity tests
+ 2025-08-08 dcc77f9e3c cmd/go: fix get -tool when multiple packages are provided
+ 2025-08-08 c7b85e9ddc all: update blog link
+ 2025-08-08 a8dd771e13 crypto/tls: check if quic conn can send session ticket
+ 2025-08-08 bdb2d50fdf net: fix WriteMsgUDPAddrPort addr handling on IPv4 sockets
+ 2025-08-08 768c51e368 internal/runtime/maps: remove unused var bitsetDeleted
+ 2025-08-08 b3388569a1 reflect: handle zero-sized fields of directly-stored structures correctly
+ 2025-08-08 d83b16fcb8 internal/bytealg: vector implementation of compare for riscv64
+ 2025-08-07 dd3abf6bc5 internal/bytealg: optimize Index/IndexString on loong64
+ 2025-08-07 73ff6d1480 cmd/internal/obj/loong64: change the immediate range of ALSL{W/WU/V}
+ 2025-08-07 f3606b0825 cmd/compile/internal/ssa: fix typo in LOONG64Ops.go comment
+ 2025-08-07 ee7bb8969a cmd/internal/obj/loong64: add support for FSEL instruction
+ 2025-08-07 1f7ffca171 time: skip TestLongAdjustTimers on plan9 (too slow)
+ 2025-08-06 8282b72d62 runtime/race: update darwin race syso
+ 2025-08-06 dc54d7b607 all: remove support for windows/arm
+ 2025-08-06 e0a1ea431c cmd/compile: make panicBounds stack frame smaller on ppc64
+ 2025-08-06 2747f925dd debug/macho: support reading imported symbols without LC_DYSYMTAB
+ 2025-08-06 025d36917c cmd/internal/testdir: pass -buildid to link command
+ 2025-08-06 f53dcb6280 cmd/internal/testdir: unify link command
+ 2025-08-06 a3895fe9f1 database/sql: avoid closing Rows while scan is in progress
+ 2025-08-06 608e9fac90 go/types, types2: flip on position tracing
+ 2025-08-06 72e8237cc1 cmd/compile: allow more args in StructMake folding rule
+ 2025-08-06 3406a617d9 internal/bytealg: vector implementation of indexbyte for riscv64
+ 2025-08-06 75ea2d05c0 internal/bytealg: vector implementation of equal for riscv64
+ 2025-08-05 17a8be7117 crypto/sha512: use const table for key loading on loong64
+ 2025-08-05 dda9d780e2 crypto/sha256: use const table for key loading on loong64
+ 2025-08-05 5defe8ebb3 internal/chacha8rand: replace WORD with instruction VMOVQ
+ 2025-08-05 4c7362e41c cmd/internal/obj/loong64: add new instructions ALSL{W/WU/V} for loong64
+ 2025-08-05 a552737418 cmd/compile: fold negation into multiplication on loong64
+ 2025-08-05 e1fd4faf91 runtime: fix godoc comment for inVDSOPage
+ 2025-08-05 bcd25c79aa cmd/compile: allow StructSelect [x] of interface data fields for x>0
+ 2025-08-05 b0945a54b5 cmd/dist, internal/platform: mark freebsd/riscv64 broken
+ 2025-08-05 55d961b202 runtime: save AVX2 and AVX-512 state on asynchronous preemption
+ 2025-08-05 af0c4fe2ca runtime: save scalar registers off stack in amd64 async preemption
+ 2025-08-05 e73afaae69 internal/cpu: add AVX-512-CD and DQ, and derived "basic AVX-512"
+ 2025-08-05 cef381ba60 runtime: eliminate global state in mkpreempt.go
+ 2025-08-05 c0025d5e0b go/parser: correct comment in expectedErrors
+ 2025-08-05 4ee0df8c46 cmd: remove dead code
+ 2025-08-05 a2c45f0eb1 runtime: test VDSO symbol hash values
+ 2025-08-05 cd55f86b8d cmd/compile: allow multi-field structs to be stored directly in interfaces
+ 2025-08-05 21ab0128b6 cmd/compile: remove support for old-style bounds check calls
+ 2025-08-05 802d056c78 cmd/compile: move ppc64 over to new bounds check strategy
+ 2025-08-05 a3295df873 cmd/compile/internal/ssa: Use transitive properties for len/cap
+ 2025-08-05 bd082857a5 doc: fix typo in go memory model doc
+ 2025-08-05 2b622b05a9 cmd/compile: remove isUintXPowerOfTwo functions
+ 2025-08-05 72147ffa75 cmd/compile: simplify isUintXPowerOfTwo implementation
+ 2025-08-05 26da1199eb cmd/compile: make isUint{32,64}PowerOfTwo implementations clearer
+ 2025-08-05 5ab9f23977 cmd/compile, runtime: add checkptr instrumentation for unsafe.Add
+ 2025-08-05 fcc036f03b cmd/compile: optimise float <-> int register moves on riscv64

Change-Id: Ie94f29d9b0cc14a52a536866f5abaef27b5c52d7

diff --cc src/cmd/compile/internal/amd64/ssa.go
index 8d4e602beda46d543fcde0f8709dba6679f9fc93,8c8c7d90274dcb67755f1e4bdf391e663114e797..25eca691b57dc092079e50b564e30881e995ba6c
--- 1/src/cmd/compile/internal/amd64/ssa.go
--- 2/src/cmd/compile/internal/amd64/ssa.go
+++ b/src/cmd/compile/internal/amd64/ssa.go
@@@ -2149,62 -1761,20 +2200,80 @@@ func zero16(s *ssagen.State, reg int16
        p.To.Offset = off
  }
  
+ // move 16 bytes from src+off to dst+off using temporary register tmp.
+ func move16(s *ssagen.State, src, dst, tmp int16, off int64) {
+       //   MOVUPS  off(srcReg), tmpReg
+       //   MOVUPS  tmpReg, off(dstReg)
+       p := s.Prog(x86.AMOVUPS)
+       p.From.Type = obj.TYPE_MEM
+       p.From.Reg = src
+       p.From.Offset = off
+       p.To.Type = obj.TYPE_REG
+       p.To.Reg = tmp
+       p = s.Prog(x86.AMOVUPS)
+       p.From.Type = obj.TYPE_REG
+       p.From.Reg = tmp
+       p.To.Type = obj.TYPE_MEM
+       p.To.Reg = dst
+       p.To.Offset = off
+ }
++
 +// XXX maybe make this part of v.Reg?
 +// On the other hand, it is architecture-specific.
 +func simdReg(v *ssa.Value) int16 {
 +      t := v.Type
 +      if !t.IsSIMD() {
 +              base.Fatalf("simdReg: not a simd type; v=%s, b=b%d, f=%s", v.LongString(), v.Block.ID, v.Block.Func.Name)
 +      }
 +      switch t.Size() {
 +      case 16:
 +              return v.Reg()
 +      case 32:
 +              return v.Reg() + (x86.REG_Y0 - x86.REG_X0)
 +      case 64:
 +              return v.Reg() + (x86.REG_Z0 - x86.REG_X0)
 +      }
 +      panic("unreachable")
 +}
 +
 +// XXX k mask
 +func maskReg(v *ssa.Value) int16 {
 +      t := v.Type
 +      if !t.IsSIMD() {
 +              base.Fatalf("maskReg: not a simd type; v=%s, b=b%d, f=%s", v.LongString(), v.Block.ID, v.Block.Func.Name)
 +      }
 +      switch t.Size() {
 +      case 8:
 +              return v.Reg()
 +      }
 +      panic("unreachable")
 +}
 +
 +// XXX k mask + vec
 +func simdOrMaskReg(v *ssa.Value) int16 {
 +      t := v.Type
 +      if t.Size() <= 8 {
 +              return maskReg(v)
 +      }
 +      return simdReg(v)
 +}
 +
 +// XXX this is used for shift operations only.
 +// regalloc will issue OpCopy with incorrect type, but the assigned
 +// register should be correct, and this function is merely checking
 +// the sanity of this part.
 +func simdCheckRegOnly(v *ssa.Value, regStart, regEnd int16) int16 {
 +      if v.Reg() > regEnd || v.Reg() < regStart {
 +              panic("simdCheckRegOnly: not the desired register")
 +      }
 +      return v.Reg()
 +}
 +
 +func simdMov(width int64) obj.As {
 +      if width >= 64 {
 +              return x86.AVMOVDQU64
 +      } else if width >= 16 {
 +              return x86.AVMOVDQU
 +      }
 +      return x86.AKMOVQ
 +}

diff --cc src/cmd/compile/internal/inline/inl.go
Simple merge

diff --cc src/cmd/compile/internal/ssa/_gen/AMD64.rules
Simple merge

diff --cc src/cmd/compile/internal/ssa/_gen/AMD64Ops.go
Simple merge

diff --cc src/cmd/compile/internal/ssa/config.go
Simple merge

diff --cc src/cmd/compile/internal/ssa/expand_calls.go
Simple merge

diff --cc src/cmd/compile/internal/ssa/opGen.go
index 7bcbf1b6157e19513b7bafaadb906ac060e333a4,215f0ae43aab14032eb1833ab7ce130c6c911fcf..60ef38535247335daa78c6f84f4b3ef5d024eb38
--- 1/src/cmd/compile/internal/ssa/opGen.go
--- 2/src/cmd/compile/internal/ssa/opGen.go
+++ b/src/cmd/compile/internal/ssa/opGen.go
@@@ -43662,28 -39565,31 +43687,27 @@@ var opcodeTable = [...]opInfo
                },
        },
        {
-               name:        "DUFFZERO",
-               auxType:     auxInt64,
-               argLen:      2,
-               unsafePoint: true,
 -              name:   "I64Eq",
 -              argLen: 2,
 -              asm:    wasm.AI64Eq,
++              name:           "LoweredZero",
++              auxType:        auxInt64,
++              argLen:         2,
++              faultOnNilArg0: true,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 524288}, // R20
 -                              {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
 -                              {1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
 -                      },
 -                      outputs: []outputInfo{
 -                              {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
++                              {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
                        },
-                       clobbers: 269156352, // R16 R17 R20 R30
                },
        },
        {
-               name:           "LoweredZero",
-               argLen:         3,
-               clobberFlags:   true,
 -              name:   "I64Ne",
 -              argLen: 2,
 -              asm:    wasm.AI64Ne,
++              name:           "LoweredZeroLoop",
++              auxType:        auxInt64,
++              argLen:         2,
++              needIntTemp:    true,
 +              faultOnNilArg0: true,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 65536},     // R16
-                               {1, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 -                              {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
 -                              {1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
 -                      },
 -                      outputs: []outputInfo{
 -                              {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
++                              {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
                        },
-                       clobbers: 65536, // R16
++                      clobbersArg0: true,
                },
        },
        {
@@@ -44834,26417 -40626,33 +44858,26489 @@@
                        },
                },
        },
 -
 -      {
 -              name:        "Add8",
 -              argLen:      2,
 -              commutative: true,
 -              generic:     true,
 -      },
        {
 -              name:        "Add16",
 +              name:        "MULF",
                argLen:      2,
                commutative: true,
 -              generic:     true,
 -      },
 -      {
 -              name:        "Add32",
 +              asm:         loong64.AMULF,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                              {1, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +              },
 +      },
 +      {
 +              name:        "MULD",
                argLen:      2,
                commutative: true,
 -              generic:     true,
 +              asm:         loong64.AMULD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                              {1, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +              },
 +      },
 +      {
 +              name:   "DIVF",
 +              argLen: 2,
 +              asm:    loong64.ADIVF,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                              {1, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +              },
 +      },
 +      {
 +              name:   "DIVD",
 +              argLen: 2,
 +              asm:    loong64.ADIVD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                              {1, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +              },
 +      },
 +      {
 +              name:        "AND",
 +              argLen:      2,
 +              commutative: true,
 +              asm:         loong64.AAND,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
 +                              {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
 +                      },
 +              },
 +      },
 +      {
 +              name:    "ANDconst",
 +              auxType: auxInt64,
 +              argLen:  1,
 +              asm:     loong64.AAND,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
 +                      },
 +              },
 +      },
 +      {
 +              name:        "OR",
 +              argLen:      2,
 +              commutative: true,
 +              asm:         loong64.AOR,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
 +                              {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
 +                      },
 +              },
 +      },
 +      {
 +              name:    "ORconst",
 +              auxType: auxInt64,
 +              argLen:  1,
 +              asm:     loong64.AOR,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
 +                      },
 +              },
 +      },
 +      {
 +              name:        "XOR",
 +              argLen:      2,
 +              commutative: true,
 +              asm:         loong64.AXOR,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
 +                              {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
 +                      },
 +              },
 +      },
 +      {
 +              name:    "XORconst",
 +              auxType: auxInt64,
 +              argLen:  1,
 +              asm:     loong64.AXOR,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
 +                      },
 +              },
 +      },
 +      {
 +              name:        "NOR",
 +              argLen:      2,
 +              commutative: true,
 +              asm:         loong64.ANOR,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
 +                              {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
 +                      },
 +              },
 +      },
 +      {
 +              name:    "NORconst",
 +              auxType: auxInt64,
 +              argLen:  1,
 +              asm:     loong64.ANOR,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
 +                      },
 +              },
 +      },
 +      {
 +              name:   "ANDN",
 +              argLen: 2,
 +              asm:    loong64.AANDN,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
 +                              {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
 +                      },
 +              },
 +      },
 +      {
 +              name:   "ORN",
 +              argLen: 2,
 +              asm:    loong64.AORN,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
 +                              {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
 +                      },
 +              },
 +      },
 +      {
 +              name:        "FMADDF",
 +              argLen:      3,
 +              commutative: true,
 +              asm:         loong64.AFMADDF,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                              {1, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                              {2, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +              },
 +      },
 +      {
 +              name:        "FMADDD",
 +              argLen:      3,
 +              commutative: true,
 +              asm:         loong64.AFMADDD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                              {1, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                              {2, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +              },
 +      },
 +      {
 +              name:        "FMSUBF",
 +              argLen:      3,
 +              commutative: true,
 +              asm:         loong64.AFMSUBF,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                              {1, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                              {2, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +              },
 +      },
 +      {
 +              name:        "FMSUBD",
 +              argLen:      3,
 +              commutative: true,
 +              asm:         loong64.AFMSUBD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                              {1, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                              {2, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +              },
 +      },
 +      {
 +              name:        "FNMADDF",
 +              argLen:      3,
 +              commutative: true,
 +              asm:         loong64.AFNMADDF,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                              {1, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                              {2, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +              },
 +      },
 +      {
 +              name:        "FNMADDD",
 +              argLen:      3,
 +              commutative: true,
 +              asm:         loong64.AFNMADDD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                              {1, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                              {2, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +              },
 +      },
 +      {
 +              name:        "FNMSUBF",
 +              argLen:      3,
 +              commutative: true,
 +              asm:         loong64.AFNMSUBF,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                              {1, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                              {2, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +              },
 +      },
 +      {
 +              name:        "FNMSUBD",
 +              argLen:      3,
 +              commutative: true,
 +              asm:         loong64.AFNMSUBD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                              {1, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                              {2, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +              },
 +      },
 +      {
 +              name:            "FMINF",
 +              argLen:          2,
 +              commutative:     true,
 +              resultNotInArgs: true,
 +              asm:             loong64.AFMINF,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                              {1, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +              },
 +      },
 +      {
 +              name:            "FMIND",
 +              argLen:          2,
 +              commutative:     true,
 +              resultNotInArgs: true,
 +              asm:             loong64.AFMIND,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                              {1, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +              },
 +      },
 +      {
 +              name:            "FMAXF",
 +              argLen:          2,
 +              commutative:     true,
 +              resultNotInArgs: true,
 +              asm:             loong64.AFMAXF,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                              {1, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +              },
 +      },
 +      {
 +              name:            "FMAXD",
 +              argLen:          2,
 +              commutative:     true,
 +              resultNotInArgs: true,
 +              asm:             loong64.AFMAXD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                              {1, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +              },
 +      },
 +      {
 +              name:   "MASKEQZ",
 +              argLen: 2,
 +              asm:    loong64.AMASKEQZ,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
 +                              {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
 +                      },
 +              },
 +      },
 +      {
 +              name:   "MASKNEZ",
 +              argLen: 2,
 +              asm:    loong64.AMASKNEZ,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
 +                              {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
 +                      },
 +              },
 +      },
 +      {
 +              name:   "FCOPYSGD",
 +              argLen: 2,
 +              asm:    loong64.AFCOPYSGD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                              {1, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +              },
 +      },
 +      {
 +              name:   "SLL",
 +              argLen: 2,
 +              asm:    loong64.ASLL,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
 +                              {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
 +                      },
 +              },
 +      },
 +      {
 +              name:   "SLLV",
 +              argLen: 2,
 +              asm:    loong64.ASLLV,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
 +                              {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
 +                      },
 +              },
 +      },
 +      {
 +              name:    "SLLconst",
 +              auxType: auxInt64,
 +              argLen:  1,
 +              asm:     loong64.ASLL,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
 +                      },
 +              },
 +      },
 +      {
 +              name:    "SLLVconst",
 +              auxType: auxInt64,
 +              argLen:  1,
 +              asm:     loong64.ASLLV,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
 +                      },
 +              },
 +      },
 +      {
 +              name:   "SRL",
 +              argLen: 2,
 +              asm:    loong64.ASRL,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
 +                              {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
 +                      },
 +              },
 +      },
 +      {
 +              name:   "SRLV",
 +              argLen: 2,
 +              asm:    loong64.ASRLV,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
 +                              {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
 +                      },
 +              },
 +      },
 +      {
 +              name:    "SRLconst",
 +              auxType: auxInt64,
 +              argLen:  1,
 +              asm:     loong64.ASRL,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
 +                      },
 +              },
 +      },
 +      {
 +              name:    "SRLVconst",
 +              auxType: auxInt64,
 +              argLen:  1,
 +              asm:     loong64.ASRLV,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
 +                      },
 +              },
 +      },
 +      {
 +              name:   "SRA",
 +              argLen: 2,
 +              asm:    loong64.ASRA,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
 +                              {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
 +                      },
 +              },
 +      },
 +      {
 +              name:   "SRAV",
 +              argLen: 2,
 +              asm:    loong64.ASRAV,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
 +                              {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
 +                      },
 +              },
 +      },
 +      {
 +              name:    "SRAconst",
 +              auxType: auxInt64,
 +              argLen:  1,
 +              asm:     loong64.ASRA,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
 +                      },
 +              },
 +      },
 +      {
 +              name:    "SRAVconst",
 +              auxType: auxInt64,
 +              argLen:  1,
 +              asm:     loong64.ASRAV,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
 +                      },
 +              },
 +      },
 +      {
 +              name:   "ROTR",
 +              argLen: 2,
 +              asm:    loong64.AROTR,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
 +                              {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
 +                      },
 +              },
 +      },
 +      {
 +              name:   "ROTRV",
 +              argLen: 2,
 +              asm:    loong64.AROTRV,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
 +                              {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
 +                      },
 +              },
 +      },
 +      {
 +              name:    "ROTRconst",
 +              auxType: auxInt64,
 +              argLen:  1,
 +              asm:     loong64.AROTR,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
 +                      },
 +              },
 +      },
 +      {
 +              name:    "ROTRVconst",
 +              auxType: auxInt64,
 +              argLen:  1,
 +              asm:     loong64.AROTRV,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
 +                      },
 +              },
 +      },
 +      {
 +              name:   "SGT",
 +              argLen: 2,
 +              asm:    loong64.ASGT,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
 +                              {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
 +                      },
 +              },
 +      },
 +      {
 +              name:    "SGTconst",
 +              auxType: auxInt64,
 +              argLen:  1,
 +              asm:     loong64.ASGT,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
 +                      },
 +              },
 +      },
 +      {
 +              name:   "SGTU",
 +              argLen: 2,
 +              asm:    loong64.ASGTU,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
 +                              {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
 +                      },
 +              },
 +      },
 +      {
 +              name:    "SGTUconst",
 +              auxType: auxInt64,
 +              argLen:  1,
 +              asm:     loong64.ASGTU,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
 +                      },
 +              },
 +      },
 +      {
 +              name:   "CMPEQF",
 +              argLen: 2,
 +              asm:    loong64.ACMPEQF,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                              {1, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +              },
 +      },
 +      {
 +              name:   "CMPEQD",
 +              argLen: 2,
 +              asm:    loong64.ACMPEQD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                              {1, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +              },
 +      },
 +      {
 +              name:   "CMPGEF",
 +              argLen: 2,
 +              asm:    loong64.ACMPGEF,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                              {1, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +              },
 +      },
 +      {
 +              name:   "CMPGED",
 +              argLen: 2,
 +              asm:    loong64.ACMPGED,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                              {1, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +              },
 +      },
 +      {
 +              name:   "CMPGTF",
 +              argLen: 2,
 +              asm:    loong64.ACMPGTF,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                              {1, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +              },
 +      },
 +      {
 +              name:   "CMPGTD",
 +              argLen: 2,
 +              asm:    loong64.ACMPGTD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                              {1, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +              },
 +      },
 +      {
 +              name:    "BSTRPICKW",
 +              auxType: auxInt64,
 +              argLen:  1,
 +              asm:     loong64.ABSTRPICKW,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
 +                      },
 +              },
 +      },
 +      {
 +              name:    "BSTRPICKV",
 +              auxType: auxInt64,
 +              argLen:  1,
 +              asm:     loong64.ABSTRPICKV,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
 +                      },
 +              },
 +      },
 +      {
 +              name:              "MOVVconst",
 +              auxType:           auxInt64,
 +              argLen:            0,
 +              rematerializeable: true,
 +              asm:               loong64.AMOVV,
 +              reg: regInfo{
 +                      outputs: []outputInfo{
 +                              {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
 +                      },
 +              },
 +      },
 +      {
 +              name:              "MOVFconst",
 +              auxType:           auxFloat64,
 +              argLen:            0,
 +              rematerializeable: true,
 +              asm:               loong64.AMOVF,
 +              reg: regInfo{
 +                      outputs: []outputInfo{
 +                              {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +              },
 +      },
 +      {
 +              name:              "MOVDconst",
 +              auxType:           auxFloat64,
 +              argLen:            0,
 +              rematerializeable: true,
 +              asm:               loong64.AMOVD,
 +              reg: regInfo{
 +                      outputs: []outputInfo{
 +                              {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +              },
 +      },
 +      {
 +              name:              "MOVVaddr",
 +              auxType:           auxSymOff,
 +              argLen:            1,
 +              rematerializeable: true,
 +              symEffect:         SymAddr,
 +              asm:               loong64.AMOVV,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 4611686018427387908}, // SP SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
 +                      },
 +              },
 +      },
 +      {
 +              name:           "MOVBload",
 +              auxType:        auxSymOff,
 +              argLen:         2,
 +              faultOnNilArg0: true,
 +              symEffect:      SymRead,
 +              asm:            loong64.AMOVB,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
 +                      },
 +              },
 +      },
 +      {
 +              name:           "MOVBUload",
 +              auxType:        auxSymOff,
 +              argLen:         2,
 +              faultOnNilArg0: true,
 +              symEffect:      SymRead,
 +              asm:            loong64.AMOVBU,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
 +                      },
 +              },
 +      },
 +      {
 +              name:           "MOVHload",
 +              auxType:        auxSymOff,
 +              argLen:         2,
 +              faultOnNilArg0: true,
 +              symEffect:      SymRead,
 +              asm:            loong64.AMOVH,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
 +                      },
 +              },
 +      },
 +      {
 +              name:           "MOVHUload",
 +              auxType:        auxSymOff,
 +              argLen:         2,
 +              faultOnNilArg0: true,
 +              symEffect:      SymRead,
 +              asm:            loong64.AMOVHU,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
 +                      },
 +              },
 +      },
 +      {
 +              name:           "MOVWload",
 +              auxType:        auxSymOff,
 +              argLen:         2,
 +              faultOnNilArg0: true,
 +              symEffect:      SymRead,
 +              asm:            loong64.AMOVW,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
 +                      },
 +              },
 +      },
 +      {
 +              name:           "MOVWUload",
 +              auxType:        auxSymOff,
 +              argLen:         2,
 +              faultOnNilArg0: true,
 +              symEffect:      SymRead,
 +              asm:            loong64.AMOVWU,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
 +                      },
 +              },
 +      },
 +      {
 +              name:           "MOVVload",
 +              auxType:        auxSymOff,
 +              argLen:         2,
 +              faultOnNilArg0: true,
 +              symEffect:      SymRead,
 +              asm:            loong64.AMOVV,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
 +                      },
 +              },
 +      },
 +      {
 +              name:           "MOVFload",
 +              auxType:        auxSymOff,
 +              argLen:         2,
 +              faultOnNilArg0: true,
 +              symEffect:      SymRead,
 +              asm:            loong64.AMOVF,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +              },
 +      },
 +      {
 +              name:           "MOVDload",
 +              auxType:        auxSymOff,
 +              argLen:         2,
 +              faultOnNilArg0: true,
 +              symEffect:      SymRead,
 +              asm:            loong64.AMOVD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +              },
 +      },
 +      {
 +              name:   "MOVVloadidx",
 +              argLen: 3,
 +              asm:    loong64.AMOVV,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 1073741816},          // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
 +                              {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
 +                      },
 +              },
 +      },
 +      {
 +              name:   "MOVWloadidx",
 +              argLen: 3,
 +              asm:    loong64.AMOVW,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 1073741816},          // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
 +                              {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
 +                      },
 +              },
 +      },
 +      {
 +              name:   "MOVWUloadidx",
 +              argLen: 3,
 +              asm:    loong64.AMOVWU,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 1073741816},          // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
 +                              {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
 +                      },
 +              },
 +      },
 +      {
 +              name:   "MOVHloadidx",
 +              argLen: 3,
 +              asm:    loong64.AMOVH,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 1073741816},          // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
 +                              {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
 +                      },
 +              },
 +      },
 +      {
 +              name:   "MOVHUloadidx",
 +              argLen: 3,
 +              asm:    loong64.AMOVHU,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 1073741816},          // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
 +                              {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
 +                      },
 +              },
 +      },
 +      {
 +              name:   "MOVBloadidx",
 +              argLen: 3,
 +              asm:    loong64.AMOVB,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 1073741816},          // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
 +                              {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
 +                      },
 +              },
 +      },
 +      {
 +              name:   "MOVBUloadidx",
 +              argLen: 3,
 +              asm:    loong64.AMOVBU,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 1073741816},          // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
 +                              {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
 +                      },
 +              },
 +      },
 +      {
 +              name:   "MOVFloadidx",
 +              argLen: 3,
 +              asm:    loong64.AMOVF,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 1073741816},          // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
 +                              {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +              },
 +      },
 +      {
 +              name:   "MOVDloadidx",
 +              argLen: 3,
 +              asm:    loong64.AMOVD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 1073741816},          // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
 +                              {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +              },
 +      },
 +      {
 +              name:           "MOVBstore",
 +              auxType:        auxSymOff,
 +              argLen:         3,
 +              faultOnNilArg0: true,
 +              symEffect:      SymWrite,
 +              asm:            loong64.AMOVB,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 1073741816},          // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
 +                              {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
 +                      },
 +              },
 +      },
 +      {
 +              name:           "MOVHstore",
 +              auxType:        auxSymOff,
 +              argLen:         3,
 +              faultOnNilArg0: true,
 +              symEffect:      SymWrite,
 +              asm:            loong64.AMOVH,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 1073741816},          // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
 +                              {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
 +                      },
 +              },
 +      },
 +      {
 +              name:           "MOVWstore",
 +              auxType:        auxSymOff,
 +              argLen:         3,
 +              faultOnNilArg0: true,
 +              symEffect:      SymWrite,
 +              asm:            loong64.AMOVW,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 1073741816},          // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
 +                              {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
 +                      },
 +              },
 +      },
 +      {
 +              name:           "MOVVstore",
 +              auxType:        auxSymOff,
 +              argLen:         3,
 +              faultOnNilArg0: true,
 +              symEffect:      SymWrite,
 +              asm:            loong64.AMOVV,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 1073741816},          // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
 +                              {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
 +                      },
 +              },
 +      },
 +      {
 +              name:           "MOVFstore",
 +              auxType:        auxSymOff,
 +              argLen:         3,
 +              faultOnNilArg0: true,
 +              symEffect:      SymWrite,
 +              asm:            loong64.AMOVF,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
 +                              {1, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +              },
 +      },
 +      {
 +              name:           "MOVDstore",
 +              auxType:        auxSymOff,
 +              argLen:         3,
 +              faultOnNilArg0: true,
 +              symEffect:      SymWrite,
 +              asm:            loong64.AMOVD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
 +                              {1, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +              },
 +      },
 +      {
 +              name:   "MOVBstoreidx",
 +              argLen: 4,
 +              asm:    loong64.AMOVB,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 1073741816},          // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
 +                              {2, 1073741816},          // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
 +                              {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
 +                      },
 +              },
 +      },
 +      {
 +              name:   "MOVHstoreidx",
 +              argLen: 4,
 +              asm:    loong64.AMOVH,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 1073741816},          // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
 +                              {2, 1073741816},          // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
 +                              {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
 +                      },
 +              },
 +      },
 +      {
 +              name:   "MOVWstoreidx",
 +              argLen: 4,
 +              asm:    loong64.AMOVW,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 1073741816},          // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
 +                              {2, 1073741816},          // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
 +                              {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
 +                      },
 +              },
 +      },
 +      {
 +              name:   "MOVVstoreidx",
 +              argLen: 4,
 +              asm:    loong64.AMOVV,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 1073741816},          // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
 +                              {2, 1073741816},          // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
 +                              {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
 +                      },
 +              },
 +      },
 +      {
 +              name:   "MOVFstoreidx",
 +              argLen: 4,
 +              asm:    loong64.AMOVF,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 1073741816},          // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
 +                              {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
 +                              {2, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +              },
 +      },
 +      {
 +              name:   "MOVDstoreidx",
 +              argLen: 4,
 +              asm:    loong64.AMOVD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 1073741816},          // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
 +                              {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
 +                              {2, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +              },
 +      },
 +      {
 +              name:           "MOVBstorezero",
 +              auxType:        auxSymOff,
 +              argLen:         2,
 +              faultOnNilArg0: true,
 +              symEffect:      SymWrite,
 +              asm:            loong64.AMOVB,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
 +                      },
 +              },
 +      },
 +      {
 +              name:           "MOVHstorezero",
 +              auxType:        auxSymOff,
 +              argLen:         2,
 +              faultOnNilArg0: true,
 +              symEffect:      SymWrite,
 +              asm:            loong64.AMOVH,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
 +                      },
 +              },
 +      },
 +      {
 +              name:           "MOVWstorezero",
 +              auxType:        auxSymOff,
 +              argLen:         2,
 +              faultOnNilArg0: true,
 +              symEffect:      SymWrite,
 +              asm:            loong64.AMOVW,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
 +                      },
 +              },
 +      },
 +      {
 +              name:           "MOVVstorezero",
 +              auxType:        auxSymOff,
 +              argLen:         2,
 +              faultOnNilArg0: true,
 +              symEffect:      SymWrite,
 +              asm:            loong64.AMOVV,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
 +                      },
 +              },
 +      },
 +      {
 +              name:   "MOVBstorezeroidx",
 +              argLen: 3,
 +              asm:    loong64.AMOVB,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 1073741816},          // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
 +                              {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
 +                      },
 +              },
 +      },
 +      {
 +              name:   "MOVHstorezeroidx",
 +              argLen: 3,
 +              asm:    loong64.AMOVH,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 1073741816},          // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
 +                              {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
 +                      },
 +              },
 +      },
 +      {
 +              name:   "MOVWstorezeroidx",
 +              argLen: 3,
 +              asm:    loong64.AMOVW,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 1073741816},          // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
 +                              {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
 +                      },
 +              },
 +      },
 +      {
 +              name:   "MOVVstorezeroidx",
 +              argLen: 3,
 +              asm:    loong64.AMOVV,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 1073741816},          // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
 +                              {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
 +                      },
 +              },
 +      },
 +      {
 +              name:   "MOVWfpgp",
 +              argLen: 1,
 +              asm:    loong64.AMOVW,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
 +                      },
 +              },
 +      },
 +      {
 +              name:   "MOVWgpfp",
 +              argLen: 1,
 +              asm:    loong64.AMOVW,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +              },
 +      },
 +      {
 +              name:   "MOVVfpgp",
 +              argLen: 1,
 +              asm:    loong64.AMOVV,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
 +                      },
 +              },
 +      },
 +      {
 +              name:   "MOVVgpfp",
 +              argLen: 1,
 +              asm:    loong64.AMOVV,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +              },
 +      },
 +      {
 +              name:   "MOVBreg",
 +              argLen: 1,
 +              asm:    loong64.AMOVB,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
 +                      },
 +              },
 +      },
 +      {
 +              name:   "MOVBUreg",
 +              argLen: 1,
 +              asm:    loong64.AMOVBU,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
 +                      },
 +              },
 +      },
 +      {
 +              name:   "MOVHreg",
 +              argLen: 1,
 +              asm:    loong64.AMOVH,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
 +                      },
 +              },
 +      },
 +      {
 +              name:   "MOVHUreg",
 +              argLen: 1,
 +              asm:    loong64.AMOVHU,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
 +                      },
 +              },
 +      },
 +      {
 +              name:   "MOVWreg",
 +              argLen: 1,
 +              asm:    loong64.AMOVW,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
 +                      },
 +              },
 +      },
 +      {
 +              name:   "MOVWUreg",
 +              argLen: 1,
 +              asm:    loong64.AMOVWU,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
 +                      },
 +              },
 +      },
 +      {
 +              name:   "MOVVreg",
 +              argLen: 1,
 +              asm:    loong64.AMOVV,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "MOVVnop",
 +              argLen:       1,
 +              resultInArg0: true,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
 +                      },
 +              },
 +      },
 +      {
 +              name:   "MOVWF",
 +              argLen: 1,
 +              asm:    loong64.AMOVWF,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +              },
 +      },
 +      {
 +              name:   "MOVWD",
 +              argLen: 1,
 +              asm:    loong64.AMOVWD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +              },
 +      },
 +      {
 +              name:   "MOVVF",
 +              argLen: 1,
 +              asm:    loong64.AMOVVF,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +              },
 +      },
 +      {
 +              name:   "MOVVD",
 +              argLen: 1,
 +              asm:    loong64.AMOVVD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +              },
 +      },
 +      {
 +              name:   "TRUNCFW",
 +              argLen: 1,
 +              asm:    loong64.ATRUNCFW,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +              },
 +      },
 +      {
 +              name:   "TRUNCDW",
 +              argLen: 1,
 +              asm:    loong64.ATRUNCDW,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +              },
 +      },
 +      {
 +              name:   "TRUNCFV",
 +              argLen: 1,
 +              asm:    loong64.ATRUNCFV,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +              },
 +      },
 +      {
 +              name:   "TRUNCDV",
 +              argLen: 1,
 +              asm:    loong64.ATRUNCDV,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +              },
 +      },
 +      {
 +              name:   "MOVFD",
 +              argLen: 1,
 +              asm:    loong64.AMOVFD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +              },
 +      },
 +      {
 +              name:   "MOVDF",
 +              argLen: 1,
 +              asm:    loong64.AMOVDF,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "LoweredRound32F",
 +              argLen:       1,
 +              resultInArg0: true,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "LoweredRound64F",
 +              argLen:       1,
 +              resultInArg0: true,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "CALLstatic",
 +              auxType:      auxCallOff,
 +              argLen:       -1,
 +              clobberFlags: true,
 +              call:         true,
 +              reg: regInfo{
 +                      clobbers: 4611686018427387896, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +              },
 +      },
 +      {
 +              name:         "CALLtail",
 +              auxType:      auxCallOff,
 +              argLen:       -1,
 +              clobberFlags: true,
 +              call:         true,
 +              tailCall:     true,
 +              reg: regInfo{
 +                      clobbers: 4611686018427387896, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +              },
 +      },
 +      {
 +              name:         "CALLclosure",
 +              auxType:      auxCallOff,
 +              argLen:       -1,
 +              clobberFlags: true,
 +              call:         true,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 268435456},  // R29
 +                              {0, 1071644668}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
 +                      },
 +                      clobbers: 4611686018427387896, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +              },
 +      },
 +      {
 +              name:         "CALLinter",
 +              auxType:      auxCallOff,
 +              argLen:       -1,
 +              clobberFlags: true,
 +              call:         true,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
 +                      },
 +                      clobbers: 4611686018427387896, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +              },
 +      },
 +      {
 +              name:           "DUFFZERO",
 +              auxType:        auxInt64,
 +              argLen:         2,
 +              faultOnNilArg0: true,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 524288}, // R20
 +                      },
 +                      clobbers: 524290, // R1 R20
 +              },
 +      },
 +      {
 +              name:           "DUFFCOPY",
 +              auxType:        auxInt64,
 +              argLen:         3,
 +              faultOnNilArg0: true,
 +              faultOnNilArg1: true,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1048576}, // R21
 +                              {1, 524288},  // R20
 +                      },
 +                      clobbers: 1572866, // R1 R20 R21
 +              },
 +      },
 +      {
 +              name:           "LoweredZero",
 +              auxType:        auxInt64,
 +              argLen:         3,
 +              faultOnNilArg0: true,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 524288},     // R20
 +                              {1, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
 +                      },
 +                      clobbers: 524288, // R20
 +              },
 +      },
 +      {
 +              name:           "LoweredMove",
 +              auxType:        auxInt64,
 +              argLen:         4,
 +              faultOnNilArg0: true,
 +              faultOnNilArg1: true,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1048576},    // R21
 +                              {1, 524288},     // R20
 +                              {2, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
 +                      },
 +                      clobbers: 1572864, // R20 R21
 +              },
 +      },
 +      {
 +              name:           "LoweredAtomicLoad8",
 +              argLen:         2,
 +              faultOnNilArg0: true,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
 +                      },
 +              },
 +      },
 +      {
 +              name:           "LoweredAtomicLoad32",
 +              argLen:         2,
 +              faultOnNilArg0: true,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
 +                      },
 +              },
 +      },
 +      {
 +              name:           "LoweredAtomicLoad64",
 +              argLen:         2,
 +              faultOnNilArg0: true,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
 +                      },
 +              },
 +      },
 +      {
 +              name:           "LoweredAtomicStore8",
 +              argLen:         3,
 +              faultOnNilArg0: true,
 +              hasSideEffects: true,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 1073741816},          // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
 +                              {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
 +                      },
 +              },
 +      },
 +      {
 +              name:           "LoweredAtomicStore32",
 +              argLen:         3,
 +              faultOnNilArg0: true,
 +              hasSideEffects: true,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 1073741816},          // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
 +                              {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
 +                      },
 +              },
 +      },
 +      {
 +              name:           "LoweredAtomicStore64",
 +              argLen:         3,
 +              faultOnNilArg0: true,
 +              hasSideEffects: true,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 1073741816},          // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
 +                              {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
 +                      },
 +              },
 +      },
 +      {
 +              name:           "LoweredAtomicStore8Variant",
 +              argLen:         3,
 +              faultOnNilArg0: true,
 +              hasSideEffects: true,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 1073741816},          // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
 +                              {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
 +                      },
 +              },
 +      },
 +      {
 +              name:           "LoweredAtomicStore32Variant",
 +              argLen:         3,
 +              faultOnNilArg0: true,
 +              hasSideEffects: true,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 1073741816},          // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
 +                              {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
 +                      },
 +              },
 +      },
 +      {
 +              name:           "LoweredAtomicStore64Variant",
 +              argLen:         3,
 +              faultOnNilArg0: true,
 +              hasSideEffects: true,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 1073741816},          // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
 +                              {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
 +                      },
 +              },
 +      },
 +      {
 +              name:            "LoweredAtomicExchange32",
 +              argLen:          3,
 +              resultNotInArgs: true,
 +              faultOnNilArg0:  true,
 +              hasSideEffects:  true,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 1073741816},          // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
 +                              {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
 +                      },
 +              },
 +      },
 +      {
 +              name:            "LoweredAtomicExchange64",
 +              argLen:          3,
 +              resultNotInArgs: true,
 +              faultOnNilArg0:  true,
 +              hasSideEffects:  true,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 1073741816},          // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
 +                              {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
 +                      },
 +              },
 +      },
 +      {
 +              name:            "LoweredAtomicExchange8Variant",
 +              argLen:          3,
 +              resultNotInArgs: true,
 +              faultOnNilArg0:  true,
 +              hasSideEffects:  true,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 1073741816},          // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
 +                              {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
 +                      },
 +              },
 +      },
 +      {
 +              name:            "LoweredAtomicAdd32",
 +              argLen:          3,
 +              resultNotInArgs: true,
 +              faultOnNilArg0:  true,
 +              hasSideEffects:  true,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 1073741816},          // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
 +                              {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
 +                      },
 +              },
 +      },
 +      {
 +              name:            "LoweredAtomicAdd64",
 +              argLen:          3,
 +              resultNotInArgs: true,
 +              faultOnNilArg0:  true,
 +              hasSideEffects:  true,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 1073741816},          // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
 +                              {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
 +                      },
 +              },
 +      },
 +      {
 +              name:            "LoweredAtomicCas32",
 +              argLen:          4,
 +              resultNotInArgs: true,
 +              faultOnNilArg0:  true,
 +              hasSideEffects:  true,
 +              unsafePoint:     true,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 1073741816},          // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
 +                              {2, 1073741816},          // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
 +                              {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
 +                      },
 +              },
 +      },
 +      {
 +              name:            "LoweredAtomicCas64",
 +              argLen:          4,
 +              resultNotInArgs: true,
 +              faultOnNilArg0:  true,
 +              hasSideEffects:  true,
 +              unsafePoint:     true,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 1073741816},          // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
 +                              {2, 1073741816},          // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
 +                              {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
 +                      },
 +              },
 +      },
 +      {
 +              name:            "LoweredAtomicCas64Variant",
 +              argLen:          4,
 +              resultNotInArgs: true,
 +              faultOnNilArg0:  true,
 +              hasSideEffects:  true,
 +              unsafePoint:     true,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 1073741816},          // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
 +                              {2, 1073741816},          // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
 +                              {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
 +                      },
 +              },
 +      },
 +      {
 +              name:            "LoweredAtomicCas32Variant",
 +              argLen:          4,
 +              resultNotInArgs: true,
 +              faultOnNilArg0:  true,
 +              hasSideEffects:  true,
 +              unsafePoint:     true,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 1073741816},          // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
 +                              {2, 1073741816},          // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
 +                              {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
 +                      },
 +              },
 +      },
 +      {
 +              name:            "LoweredAtomicAnd32",
 +              argLen:          3,
 +              resultNotInArgs: true,
 +              faultOnNilArg0:  true,
 +              hasSideEffects:  true,
 +              asm:             loong64.AAMANDDBW,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 1073741816},          // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
 +                              {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
 +                      },
 +              },
 +      },
 +      {
 +              name:            "LoweredAtomicOr32",
 +              argLen:          3,
 +              resultNotInArgs: true,
 +              faultOnNilArg0:  true,
 +              hasSideEffects:  true,
 +              asm:             loong64.AAMORDBW,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 1073741816},          // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
 +                              {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
 +                      },
 +              },
 +      },
 +      {
 +              name:            "LoweredAtomicAnd32value",
 +              argLen:          3,
 +              resultNotInArgs: true,
 +              faultOnNilArg0:  true,
 +              hasSideEffects:  true,
 +              asm:             loong64.AAMANDDBW,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 1073741816},          // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
 +                              {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
 +                      },
 +              },
 +      },
 +      {
 +              name:            "LoweredAtomicAnd64value",
 +              argLen:          3,
 +              resultNotInArgs: true,
 +              faultOnNilArg0:  true,
 +              hasSideEffects:  true,
 +              asm:             loong64.AAMANDDBV,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 1073741816},          // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
 +                              {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
 +                      },
 +              },
 +      },
 +      {
 +              name:            "LoweredAtomicOr32value",
 +              argLen:          3,
 +              resultNotInArgs: true,
 +              faultOnNilArg0:  true,
 +              hasSideEffects:  true,
 +              asm:             loong64.AAMORDBW,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 1073741816},          // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
 +                              {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
 +                      },
 +              },
 +      },
 +      {
 +              name:            "LoweredAtomicOr64value",
 +              argLen:          3,
 +              resultNotInArgs: true,
 +              faultOnNilArg0:  true,
 +              hasSideEffects:  true,
 +              asm:             loong64.AAMORDBV,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 1073741816},          // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
 +                              {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
 +                      },
 +              },
 +      },
 +      {
 +              name:           "LoweredNilCheck",
 +              argLen:         2,
 +              nilCheck:       true,
 +              faultOnNilArg0: true,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
 +                      },
 +              },
 +      },
 +      {
 +              name:   "FPFlagTrue",
 +              argLen: 1,
 +              reg: regInfo{
 +                      outputs: []outputInfo{
 +                              {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
 +                      },
 +              },
 +      },
 +      {
 +              name:   "FPFlagFalse",
 +              argLen: 1,
 +              reg: regInfo{
 +                      outputs: []outputInfo{
 +                              {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
 +                      },
 +              },
 +      },
 +      {
 +              name:      "LoweredGetClosurePtr",
 +              argLen:    0,
 +              zeroWidth: true,
 +              reg: regInfo{
 +                      outputs: []outputInfo{
 +                              {0, 268435456}, // R29
 +                      },
 +              },
 +      },
 +      {
 +              name:              "LoweredGetCallerSP",
 +              argLen:            1,
 +              rematerializeable: true,
 +              reg: regInfo{
 +                      outputs: []outputInfo{
 +                              {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
 +                      },
 +              },
 +      },
 +      {
 +              name:              "LoweredGetCallerPC",
 +              argLen:            0,
 +              rematerializeable: true,
 +              reg: regInfo{
 +                      outputs: []outputInfo{
 +                              {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "LoweredWB",
 +              auxType:      auxInt64,
 +              argLen:       1,
 +              clobberFlags: true,
 +              reg: regInfo{
 +                      clobbers: 4611686017353646082, // R1 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      outputs: []outputInfo{
 +                              {0, 268435456}, // R29
 +                      },
 +              },
 +      },
 +      {
 +              name:           "LoweredPubBarrier",
 +              argLen:         1,
 +              hasSideEffects: true,
 +              asm:            loong64.ADBAR,
 +              reg:            regInfo{},
 +      },
 +      {
 +              name:    "LoweredPanicBoundsRR",
 +              auxType: auxInt64,
 +              argLen:  3,
 +              call:    true,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 524280}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19
 +                              {1, 524280}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19
 +                      },
 +              },
 +      },
 +      {
 +              name:    "LoweredPanicBoundsRC",
 +              auxType: auxPanicBoundsC,
 +              argLen:  2,
 +              call:    true,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 524280}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19
 +                      },
 +              },
 +      },
 +      {
 +              name:    "LoweredPanicBoundsCR",
 +              auxType: auxPanicBoundsC,
 +              argLen:  2,
 +              call:    true,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 524280}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19
 +                      },
 +              },
 +      },
 +      {
 +              name:    "LoweredPanicBoundsCC",
 +              auxType: auxPanicBoundsCC,
 +              argLen:  1,
 +              call:    true,
 +              reg:     regInfo{},
 +      },
 +      {
 +              name:           "PRELD",
 +              auxType:        auxInt64,
 +              argLen:         2,
 +              hasSideEffects: true,
 +              asm:            loong64.APRELD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1073741820}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
 +                      },
 +              },
 +      },
 +      {
 +              name:           "PRELDX",
 +              auxType:        auxInt64,
 +              argLen:         2,
 +              hasSideEffects: true,
 +              asm:            loong64.APRELDX,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1073741820}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
 +                      },
 +              },
 +      },
++      {
++              name:    "ADDshiftLLV",
++              auxType: auxInt64,
++              argLen:  2,
++              asm:     loong64.AALSLV,
++              reg: regInfo{
++                      inputs: []inputInfo{
++                              {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
++                              {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
++                      },
++                      outputs: []outputInfo{
++                              {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
++                      },
++              },
++      },
 +
 +      {
 +              name:        "ADD",
 +              argLen:      2,
 +              commutative: true,
 +              asm:         mips.AADDU,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
 +                              {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
 +                      },
 +              },
 +      },
 +      {
 +              name:    "ADDconst",
 +              auxType: auxInt32,
 +              argLen:  1,
 +              asm:     mips.AADDU,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 536870910}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
 +                      },
 +              },
 +      },
 +      {
 +              name:   "SUB",
 +              argLen: 2,
 +              asm:    mips.ASUBU,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
 +                              {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
 +                      },
 +              },
 +      },
 +      {
 +              name:    "SUBconst",
 +              auxType: auxInt32,
 +              argLen:  1,
 +              asm:     mips.ASUBU,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
 +                      },
 +              },
 +      },
 +      {
 +              name:        "MUL",
 +              argLen:      2,
 +              commutative: true,
 +              asm:         mips.AMUL,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
 +                              {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
 +                      },
 +                      clobbers: 105553116266496, // HI LO
 +                      outputs: []outputInfo{
 +                              {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
 +                      },
 +              },
 +      },
 +      {
 +              name:        "MULT",
 +              argLen:      2,
 +              commutative: true,
 +              asm:         mips.AMUL,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
 +                              {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 35184372088832}, // HI
 +                              {1, 70368744177664}, // LO
 +                      },
 +              },
 +      },
 +      {
 +              name:        "MULTU",
 +              argLen:      2,
 +              commutative: true,
 +              asm:         mips.AMULU,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
 +                              {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 35184372088832}, // HI
 +                              {1, 70368744177664}, // LO
 +                      },
 +              },
 +      },
 +      {
 +              name:   "DIV",
 +              argLen: 2,
 +              asm:    mips.ADIV,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
 +                              {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 35184372088832}, // HI
 +                              {1, 70368744177664}, // LO
 +                      },
 +              },
 +      },
 +      {
 +              name:   "DIVU",
 +              argLen: 2,
 +              asm:    mips.ADIVU,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
 +                              {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 35184372088832}, // HI
 +                              {1, 70368744177664}, // LO
 +                      },
 +              },
 +      },
 +      {
 +              name:        "ADDF",
 +              argLen:      2,
 +              commutative: true,
 +              asm:         mips.AADDF,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
 +                              {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
 +                      },
 +              },
 +      },
 +      {
 +              name:        "ADDD",
 +              argLen:      2,
 +              commutative: true,
 +              asm:         mips.AADDD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
 +                              {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
 +                      },
 +              },
 +      },
 +      {
 +              name:   "SUBF",
 +              argLen: 2,
 +              asm:    mips.ASUBF,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
 +                              {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
 +                      },
 +              },
 +      },
 +      {
 +              name:   "SUBD",
 +              argLen: 2,
 +              asm:    mips.ASUBD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
 +                              {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
 +                      },
 +              },
 +      },
 +      {
 +              name:        "MULF",
 +              argLen:      2,
 +              commutative: true,
 +              asm:         mips.AMULF,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
 +                              {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
 +                      },
 +              },
 +      },
 +      {
 +              name:        "MULD",
 +              argLen:      2,
 +              commutative: true,
 +              asm:         mips.AMULD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
 +                              {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
 +                      },
 +              },
 +      },
 +      {
 +              name:   "DIVF",
 +              argLen: 2,
 +              asm:    mips.ADIVF,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
 +                              {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
 +                      },
 +              },
 +      },
 +      {
 +              name:   "DIVD",
 +              argLen: 2,
 +              asm:    mips.ADIVD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
 +                              {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
 +                      },
 +              },
 +      },
 +      {
 +              name:        "AND",
 +              argLen:      2,
 +              commutative: true,
 +              asm:         mips.AAND,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
 +                              {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
 +                      },
 +              },
 +      },
 +      {
 +              name:    "ANDconst",
 +              auxType: auxInt32,
 +              argLen:  1,
 +              asm:     mips.AAND,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
 +                      },
 +              },
 +      },
 +      {
 +              name:        "OR",
 +              argLen:      2,
 +              commutative: true,
 +              asm:         mips.AOR,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
 +                              {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
 +                      },
 +              },
 +      },
 +      {
 +              name:    "ORconst",
 +              auxType: auxInt32,
 +              argLen:  1,
 +              asm:     mips.AOR,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
 +                      },
 +              },
 +      },
 +      {
 +              name:        "XOR",
 +              argLen:      2,
 +              commutative: true,
 +              asm:         mips.AXOR,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
 +                              {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
 +                      },
 +              },
 +      },
 +      {
 +              name:    "XORconst",
 +              auxType: auxInt32,
 +              argLen:  1,
 +              asm:     mips.AXOR,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
 +                      },
 +              },
 +      },
 +      {
 +              name:        "NOR",
 +              argLen:      2,
 +              commutative: true,
 +              asm:         mips.ANOR,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
 +                              {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
 +                      },
 +              },
 +      },
 +      {
 +              name:    "NORconst",
 +              auxType: auxInt32,
 +              argLen:  1,
 +              asm:     mips.ANOR,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
 +                      },
 +              },
 +      },
 +      {
 +              name:   "NEG",
 +              argLen: 1,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
 +                      },
 +              },
 +      },
 +      {
 +              name:   "NEGF",
 +              argLen: 1,
 +              asm:    mips.ANEGF,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
 +                      },
 +              },
 +      },
 +      {
 +              name:   "NEGD",
 +              argLen: 1,
 +              asm:    mips.ANEGD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
 +                      },
 +              },
 +      },
 +      {
 +              name:   "ABSD",
 +              argLen: 1,
 +              asm:    mips.AABSD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
 +                      },
 +              },
 +      },
 +      {
 +              name:   "SQRTD",
 +              argLen: 1,
 +              asm:    mips.ASQRTD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
 +                      },
 +              },
 +      },
 +      {
 +              name:   "SQRTF",
 +              argLen: 1,
 +              asm:    mips.ASQRTF,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
 +                      },
 +              },
 +      },
 +      {
 +              name:   "SLL",
 +              argLen: 2,
 +              asm:    mips.ASLL,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
 +                              {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
 +                      },
 +              },
 +      },
 +      {
 +              name:    "SLLconst",
 +              auxType: auxInt32,
 +              argLen:  1,
 +              asm:     mips.ASLL,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
 +                      },
 +              },
 +      },
 +      {
 +              name:   "SRL",
 +              argLen: 2,
 +              asm:    mips.ASRL,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
 +                              {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
 +                      },
 +              },
 +      },
 +      {
 +              name:    "SRLconst",
 +              auxType: auxInt32,
 +              argLen:  1,
 +              asm:     mips.ASRL,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
 +                      },
 +              },
 +      },
 +      {
 +              name:   "SRA",
 +              argLen: 2,
 +              asm:    mips.ASRA,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
 +                              {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
 +                      },
 +              },
 +      },
 +      {
 +              name:    "SRAconst",
 +              auxType: auxInt32,
 +              argLen:  1,
 +              asm:     mips.ASRA,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
 +                      },
 +              },
 +      },
 +      {
 +              name:   "CLZ",
 +              argLen: 1,
 +              asm:    mips.ACLZ,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
 +                      },
 +              },
 +      },
 +      {
 +              name:   "SGT",
 +              argLen: 2,
 +              asm:    mips.ASGT,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
 +                              {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
 +                      },
 +              },
 +      },
 +      {
 +              name:    "SGTconst",
 +              auxType: auxInt32,
 +              argLen:  1,
 +              asm:     mips.ASGT,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
 +                      },
 +              },
 +      },
 +      {
 +              name:   "SGTzero",
 +              argLen: 1,
 +              asm:    mips.ASGT,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
 +                      },
 +              },
 +      },
 +      {
 +              name:   "SGTU",
 +              argLen: 2,
 +              asm:    mips.ASGTU,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
 +                              {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
 +                      },
 +              },
 +      },
 +      {
 +              name:    "SGTUconst",
 +              auxType: auxInt32,
 +              argLen:  1,
 +              asm:     mips.ASGTU,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
 +                      },
 +              },
 +      },
 +      {
 +              name:   "SGTUzero",
 +              argLen: 1,
 +              asm:    mips.ASGTU,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
 +                      },
 +              },
 +      },
 +      {
 +              name:   "CMPEQF",
 +              argLen: 2,
 +              asm:    mips.ACMPEQF,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
 +                              {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
 +                      },
 +              },
 +      },
 +      {
 +              name:   "CMPEQD",
 +              argLen: 2,
 +              asm:    mips.ACMPEQD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
 +                              {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
 +                      },
 +              },
 +      },
 +      {
 +              name:   "CMPGEF",
 +              argLen: 2,
 +              asm:    mips.ACMPGEF,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
 +                              {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
 +                      },
 +              },
 +      },
 +      {
 +              name:   "CMPGED",
 +              argLen: 2,
 +              asm:    mips.ACMPGED,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
 +                              {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
 +                      },
 +              },
 +      },
 +      {
 +              name:   "CMPGTF",
 +              argLen: 2,
 +              asm:    mips.ACMPGTF,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
 +                              {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
 +                      },
 +              },
 +      },
 +      {
 +              name:   "CMPGTD",
 +              argLen: 2,
 +              asm:    mips.ACMPGTD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
 +                              {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
 +                      },
 +              },
 +      },
 +      {
 +              name:              "MOVWconst",
 +              auxType:           auxInt32,
 +              argLen:            0,
 +              rematerializeable: true,
 +              asm:               mips.AMOVW,
 +              reg: regInfo{
 +                      outputs: []outputInfo{
 +                              {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
 +                      },
 +              },
 +      },
 +      {
 +              name:              "MOVFconst",
 +              auxType:           auxFloat32,
 +              argLen:            0,
 +              rematerializeable: true,
 +              asm:               mips.AMOVF,
 +              reg: regInfo{
 +                      outputs: []outputInfo{
 +                              {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
 +                      },
 +              },
 +      },
 +      {
 +              name:              "MOVDconst",
 +              auxType:           auxFloat64,
 +              argLen:            0,
 +              rematerializeable: true,
 +              asm:               mips.AMOVD,
 +              reg: regInfo{
 +                      outputs: []outputInfo{
 +                              {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
 +                      },
 +              },
 +      },
 +      {
 +              name:              "MOVWaddr",
 +              auxType:           auxSymOff,
 +              argLen:            1,
 +              rematerializeable: true,
 +              symEffect:         SymAddr,
 +              asm:               mips.AMOVW,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 140737555464192}, // SP SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
 +                      },
 +              },
 +      },
 +      {
 +              name:           "MOVBload",
 +              auxType:        auxSymOff,
 +              argLen:         2,
 +              faultOnNilArg0: true,
 +              symEffect:      SymRead,
 +              asm:            mips.AMOVB,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
 +                      },
 +              },
 +      },
 +      {
 +              name:           "MOVBUload",
 +              auxType:        auxSymOff,
 +              argLen:         2,
 +              faultOnNilArg0: true,
 +              symEffect:      SymRead,
 +              asm:            mips.AMOVBU,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
 +                      },
 +              },
 +      },
 +      {
 +              name:           "MOVHload",
 +              auxType:        auxSymOff,
 +              argLen:         2,
 +              faultOnNilArg0: true,
 +              symEffect:      SymRead,
 +              asm:            mips.AMOVH,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
 +                      },
 +              },
 +      },
 +      {
 +              name:           "MOVHUload",
 +              auxType:        auxSymOff,
 +              argLen:         2,
 +              faultOnNilArg0: true,
 +              symEffect:      SymRead,
 +              asm:            mips.AMOVHU,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
 +                      },
 +              },
 +      },
 +      {
 +              name:           "MOVWload",
 +              auxType:        auxSymOff,
 +              argLen:         2,
 +              faultOnNilArg0: true,
 +              symEffect:      SymRead,
 +              asm:            mips.AMOVW,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
 +                      },
 +              },
 +      },
 +      {
 +              name:           "MOVFload",
 +              auxType:        auxSymOff,
 +              argLen:         2,
 +              faultOnNilArg0: true,
 +              symEffect:      SymRead,
 +              asm:            mips.AMOVF,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
 +                      },
 +              },
 +      },
 +      {
 +              name:           "MOVDload",
 +              auxType:        auxSymOff,
 +              argLen:         2,
 +              faultOnNilArg0: true,
 +              symEffect:      SymRead,
 +              asm:            mips.AMOVD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
 +                      },
 +              },
 +      },
 +      {
 +              name:           "MOVBstore",
 +              auxType:        auxSymOff,
 +              argLen:         3,
 +              faultOnNilArg0: true,
 +              symEffect:      SymWrite,
 +              asm:            mips.AMOVB,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 469762046},       // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
 +                              {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB
 +                      },
 +              },
 +      },
 +      {
 +              name:           "MOVHstore",
 +              auxType:        auxSymOff,
 +              argLen:         3,
 +              faultOnNilArg0: true,
 +              symEffect:      SymWrite,
 +              asm:            mips.AMOVH,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 469762046},       // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
 +                              {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB
 +                      },
 +              },
 +      },
 +      {
 +              name:           "MOVWstore",
 +              auxType:        auxSymOff,
 +              argLen:         3,
 +              faultOnNilArg0: true,
 +              symEffect:      SymWrite,
 +              asm:            mips.AMOVW,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 469762046},       // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
 +                              {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB
 +                      },
 +              },
 +      },
 +      {
 +              name:           "MOVFstore",
 +              auxType:        auxSymOff,
 +              argLen:         3,
 +              faultOnNilArg0: true,
 +              symEffect:      SymWrite,
 +              asm:            mips.AMOVF,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 35183835217920},  // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
 +                              {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB
 +                      },
 +              },
 +      },
 +      {
 +              name:           "MOVDstore",
 +              auxType:        auxSymOff,
 +              argLen:         3,
 +              faultOnNilArg0: true,
 +              symEffect:      SymWrite,
 +              asm:            mips.AMOVD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 35183835217920},  // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
 +                              {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB
 +                      },
 +              },
 +      },
 +      {
 +              name:           "MOVBstorezero",
 +              auxType:        auxSymOff,
 +              argLen:         2,
 +              faultOnNilArg0: true,
 +              symEffect:      SymWrite,
 +              asm:            mips.AMOVB,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB
 +                      },
 +              },
 +      },
 +      {
 +              name:           "MOVHstorezero",
 +              auxType:        auxSymOff,
 +              argLen:         2,
 +              faultOnNilArg0: true,
 +              symEffect:      SymWrite,
 +              asm:            mips.AMOVH,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB
 +                      },
 +              },
 +      },
 +      {
 +              name:           "MOVWstorezero",
 +              auxType:        auxSymOff,
 +              argLen:         2,
 +              faultOnNilArg0: true,
 +              symEffect:      SymWrite,
 +              asm:            mips.AMOVW,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB
 +                      },
 +              },
 +      },
 +      {
 +              name:   "MOVWfpgp",
 +              argLen: 1,
 +              asm:    mips.AMOVW,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
 +                      },
 +              },
 +      },
 +      {
 +              name:   "MOVWgpfp",
 +              argLen: 1,
 +              asm:    mips.AMOVW,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
 +                      },
 +              },
 +      },
 +      {
 +              name:   "MOVBreg",
 +              argLen: 1,
 +              asm:    mips.AMOVB,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
 +                      },
 +              },
 +      },
 +      {
 +              name:   "MOVBUreg",
 +              argLen: 1,
 +              asm:    mips.AMOVBU,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
 +                      },
 +              },
 +      },
 +      {
 +              name:   "MOVHreg",
 +              argLen: 1,
 +              asm:    mips.AMOVH,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
 +                      },
 +              },
 +      },
 +      {
 +              name:   "MOVHUreg",
 +              argLen: 1,
 +              asm:    mips.AMOVHU,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
 +                      },
 +              },
 +      },
 +      {
 +              name:   "MOVWreg",
 +              argLen: 1,
 +              asm:    mips.AMOVW,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "MOVWnop",
 +              argLen:       1,
 +              resultInArg0: true,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "CMOVZ",
 +              argLen:       3,
 +              resultInArg0: true,
 +              asm:          mips.ACMOVZ,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
 +                              {1, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
 +                              {2, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "CMOVZzero",
 +              argLen:       2,
 +              resultInArg0: true,
 +              asm:          mips.ACMOVZ,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
 +                              {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
 +                      },
 +              },
 +      },
 +      {
 +              name:   "MOVWF",
 +              argLen: 1,
 +              asm:    mips.AMOVWF,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
 +                      },
 +              },
 +      },
 +      {
 +              name:   "MOVWD",
 +              argLen: 1,
 +              asm:    mips.AMOVWD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
 +                      },
 +              },
 +      },
 +      {
 +              name:   "TRUNCFW",
 +              argLen: 1,
 +              asm:    mips.ATRUNCFW,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
 +                      },
 +              },
 +      },
 +      {
 +              name:   "TRUNCDW",
 +              argLen: 1,
 +              asm:    mips.ATRUNCDW,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
 +                      },
 +              },
 +      },
 +      {
 +              name:   "MOVFD",
 +              argLen: 1,
 +              asm:    mips.AMOVFD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
 +                      },
 +              },
 +      },
 +      {
 +              name:   "MOVDF",
 +              argLen: 1,
 +              asm:    mips.AMOVDF,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
 +                      },
 +              },
 +      },
 +      {
 +              name:         "CALLstatic",
 +              auxType:      auxCallOff,
 +              argLen:       1,
 +              clobberFlags: true,
 +              call:         true,
 +              reg: regInfo{
 +                      clobbers: 140737421246462, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 HI LO
 +              },
 +      },
 +      {
 +              name:         "CALLtail",
 +              auxType:      auxCallOff,
 +              argLen:       1,
 +              clobberFlags: true,
 +              call:         true,
 +              tailCall:     true,
 +              reg: regInfo{
 +                      clobbers: 140737421246462, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 HI LO
 +              },
 +      },
 +      {
 +              name:         "CALLclosure",
 +              auxType:      auxCallOff,
 +              argLen:       3,
 +              clobberFlags: true,
 +              call:         true,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 4194304},   // R22
 +                              {0, 402653182}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP R31
 +                      },
 +                      clobbers: 140737421246462, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 HI LO
 +              },
 +      },
 +      {
 +              name:         "CALLinter",
 +              auxType:      auxCallOff,
 +              argLen:       2,
 +              clobberFlags: true,
 +              call:         true,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
 +                      },
 +                      clobbers: 140737421246462, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 HI LO
 +              },
 +      },
 +      {
 +              name:           "LoweredAtomicLoad8",
 +              argLen:         2,
 +              faultOnNilArg0: true,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
 +                      },
 +              },
 +      },
 +      {
 +              name:           "LoweredAtomicLoad32",
 +              argLen:         2,
 +              faultOnNilArg0: true,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
 +                      },
 +              },
 +      },
 +      {
 +              name:           "LoweredAtomicStore8",
 +              argLen:         3,
 +              faultOnNilArg0: true,
 +              hasSideEffects: true,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 469762046},       // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
 +                              {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB
 +                      },
 +              },
 +      },
 +      {
 +              name:           "LoweredAtomicStore32",
 +              argLen:         3,
 +              faultOnNilArg0: true,
 +              hasSideEffects: true,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 469762046},       // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
 +                              {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB
 +                      },
 +              },
 +      },
 +      {
 +              name:           "LoweredAtomicStorezero",
 +              argLen:         2,
 +              faultOnNilArg0: true,
 +              hasSideEffects: true,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB
 +                      },
 +              },
 +      },
 +      {
 +              name:            "LoweredAtomicExchange",
 +              argLen:          3,
 +              resultNotInArgs: true,
 +              faultOnNilArg0:  true,
 +              hasSideEffects:  true,
 +              unsafePoint:     true,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 469762046},       // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
 +                              {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
 +                      },
 +              },
 +      },
 +      {
 +              name:            "LoweredAtomicAdd",
 +              argLen:          3,
 +              resultNotInArgs: true,
 +              faultOnNilArg0:  true,
 +              hasSideEffects:  true,
 +              unsafePoint:     true,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 469762046},       // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
 +                              {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
 +                      },
 +              },
 +      },
 +      {
 +              name:            "LoweredAtomicAddconst",
 +              auxType:         auxInt32,
 +              argLen:          2,
 +              resultNotInArgs: true,
 +              faultOnNilArg0:  true,
 +              hasSideEffects:  true,
 +              unsafePoint:     true,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
 +                      },
 +              },
 +      },
 +      {
 +              name:            "LoweredAtomicCas",
 +              argLen:          4,
 +              resultNotInArgs: true,
 +              faultOnNilArg0:  true,
 +              hasSideEffects:  true,
 +              unsafePoint:     true,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 469762046},       // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
 +                              {2, 469762046},       // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
 +                              {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
 +                      },
 +              },
 +      },
 +      {
 +              name:           "LoweredAtomicAnd",
 +              argLen:         3,
 +              faultOnNilArg0: true,
 +              hasSideEffects: true,
 +              unsafePoint:    true,
 +              asm:            mips.AAND,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 469762046},       // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
 +                              {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB
 +                      },
 +              },
 +      },
 +      {
 +              name:           "LoweredAtomicOr",
 +              argLen:         3,
 +              faultOnNilArg0: true,
 +              hasSideEffects: true,
 +              unsafePoint:    true,
 +              asm:            mips.AOR,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 469762046},       // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
 +                              {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB
 +                      },
 +              },
 +      },
 +      {
 +              name:           "LoweredZero",
 +              auxType:        auxInt32,
 +              argLen:         3,
 +              faultOnNilArg0: true,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 2},         // R1
 +                              {1, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
 +                      },
 +                      clobbers: 2, // R1
 +              },
 +      },
 +      {
 +              name:           "LoweredMove",
 +              auxType:        auxInt32,
 +              argLen:         4,
 +              faultOnNilArg0: true,
 +              faultOnNilArg1: true,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 4},         // R2
 +                              {1, 2},         // R1
 +                              {2, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
 +                      },
 +                      clobbers: 6, // R1 R2
 +              },
 +      },
 +      {
 +              name:           "LoweredNilCheck",
 +              argLen:         2,
 +              nilCheck:       true,
 +              faultOnNilArg0: true,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
 +                      },
 +              },
 +      },
 +      {
 +              name:   "FPFlagTrue",
 +              argLen: 1,
 +              reg: regInfo{
 +                      outputs: []outputInfo{
 +                              {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
 +                      },
 +              },
 +      },
 +      {
 +              name:   "FPFlagFalse",
 +              argLen: 1,
 +              reg: regInfo{
 +                      outputs: []outputInfo{
 +                              {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
 +                      },
 +              },
 +      },
 +      {
 +              name:      "LoweredGetClosurePtr",
 +              argLen:    0,
 +              zeroWidth: true,
 +              reg: regInfo{
 +                      outputs: []outputInfo{
 +                              {0, 4194304}, // R22
 +                      },
 +              },
 +      },
 +      {
 +              name:              "LoweredGetCallerSP",
 +              argLen:            1,
 +              rematerializeable: true,
 +              reg: regInfo{
 +                      outputs: []outputInfo{
 +                              {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
 +                      },
 +              },
 +      },
 +      {
 +              name:              "LoweredGetCallerPC",
 +              argLen:            0,
 +              rematerializeable: true,
 +              reg: regInfo{
 +                      outputs: []outputInfo{
 +                              {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "LoweredWB",
 +              auxType:      auxInt64,
 +              argLen:       1,
 +              clobberFlags: true,
 +              reg: regInfo{
 +                      clobbers: 140737219919872, // R31 F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 HI LO
 +                      outputs: []outputInfo{
 +                              {0, 16777216}, // R25
 +                      },
 +              },
 +      },
 +      {
 +              name:           "LoweredPubBarrier",
 +              argLen:         1,
 +              hasSideEffects: true,
 +              asm:            mips.ASYNC,
 +              reg:            regInfo{},
 +      },
 +      {
 +              name:    "LoweredPanicBoundsRR",
 +              auxType: auxInt64,
 +              argLen:  3,
 +              call:    true,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 131070}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16
 +                              {1, 131070}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16
 +                      },
 +              },
 +      },
 +      {
 +              name:    "LoweredPanicBoundsRC",
 +              auxType: auxPanicBoundsC,
 +              argLen:  2,
 +              call:    true,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 131070}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16
 +                      },
 +              },
 +      },
 +      {
 +              name:    "LoweredPanicBoundsCR",
 +              auxType: auxPanicBoundsC,
 +              argLen:  2,
 +              call:    true,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 131070}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16
 +                      },
 +              },
 +      },
 +      {
 +              name:    "LoweredPanicBoundsCC",
 +              auxType: auxPanicBoundsCC,
 +              argLen:  1,
 +              call:    true,
 +              reg:     regInfo{},
 +      },
 +      {
 +              name:    "LoweredPanicExtendRR",
 +              auxType: auxInt64,
 +              argLen:  4,
 +              call:    true,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 30},     // R1 R2 R3 R4
 +                              {1, 30},     // R1 R2 R3 R4
 +                              {2, 131070}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16
 +                      },
 +              },
 +      },
 +      {
 +              name:    "LoweredPanicExtendRC",
 +              auxType: auxPanicBoundsC,
 +              argLen:  3,
 +              call:    true,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 30}, // R1 R2 R3 R4
 +                              {1, 30}, // R1 R2 R3 R4
 +                      },
 +              },
 +      },
 +
 +      {
 +              name:        "ADDV",
 +              argLen:      2,
 +              commutative: true,
 +              asm:         mips.AADDVU,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
 +                              {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
 +                      },
 +              },
 +      },
 +      {
 +              name:    "ADDVconst",
 +              auxType: auxInt64,
 +              argLen:  1,
 +              asm:     mips.AADDVU,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 268435454}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
 +                      },
 +              },
 +      },
 +      {
 +              name:   "SUBV",
 +              argLen: 2,
 +              asm:    mips.ASUBVU,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
 +                              {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
 +                      },
 +              },
 +      },
 +      {
 +              name:    "SUBVconst",
 +              auxType: auxInt64,
 +              argLen:  1,
 +              asm:     mips.ASUBVU,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
 +                      },
 +              },
 +      },
 +      {
 +              name:        "MULV",
 +              argLen:      2,
 +              commutative: true,
 +              asm:         mips.AMULV,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
 +                              {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1152921504606846976}, // HI
 +                              {1, 2305843009213693952}, // LO
 +                      },
 +              },
 +      },
 +      {
 +              name:        "MULVU",
 +              argLen:      2,
 +              commutative: true,
 +              asm:         mips.AMULVU,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
 +                              {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1152921504606846976}, // HI
 +                              {1, 2305843009213693952}, // LO
 +                      },
 +              },
 +      },
 +      {
 +              name:   "DIVV",
 +              argLen: 2,
 +              asm:    mips.ADIVV,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
 +                              {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1152921504606846976}, // HI
 +                              {1, 2305843009213693952}, // LO
 +                      },
 +              },
 +      },
 +      {
 +              name:   "DIVVU",
 +              argLen: 2,
 +              asm:    mips.ADIVVU,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
 +                              {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1152921504606846976}, // HI
 +                              {1, 2305843009213693952}, // LO
 +                      },
 +              },
 +      },
 +      {
 +              name:        "ADDF",
 +              argLen:      2,
 +              commutative: true,
 +              asm:         mips.AADDF,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                              {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +              },
 +      },
 +      {
 +              name:        "ADDD",
 +              argLen:      2,
 +              commutative: true,
 +              asm:         mips.AADDD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                              {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +              },
 +      },
 +      {
 +              name:   "SUBF",
 +              argLen: 2,
 +              asm:    mips.ASUBF,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                              {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +              },
 +      },
 +      {
 +              name:   "SUBD",
 +              argLen: 2,
 +              asm:    mips.ASUBD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                              {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +              },
 +      },
 +      {
 +              name:        "MULF",
 +              argLen:      2,
 +              commutative: true,
 +              asm:         mips.AMULF,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                              {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +              },
 +      },
 +      {
 +              name:        "MULD",
 +              argLen:      2,
 +              commutative: true,
 +              asm:         mips.AMULD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                              {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +              },
 +      },
 +      {
 +              name:   "DIVF",
 +              argLen: 2,
 +              asm:    mips.ADIVF,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                              {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +              },
 +      },
 +      {
 +              name:   "DIVD",
 +              argLen: 2,
 +              asm:    mips.ADIVD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                              {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +              },
 +      },
 +      {
 +              name:        "AND",
 +              argLen:      2,
 +              commutative: true,
 +              asm:         mips.AAND,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
 +                              {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
 +                      },
 +              },
 +      },
 +      {
 +              name:    "ANDconst",
 +              auxType: auxInt64,
 +              argLen:  1,
 +              asm:     mips.AAND,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
 +                      },
 +              },
 +      },
 +      {
 +              name:        "OR",
 +              argLen:      2,
 +              commutative: true,
 +              asm:         mips.AOR,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
 +                              {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
 +                      },
 +              },
 +      },
 +      {
 +              name:    "ORconst",
 +              auxType: auxInt64,
 +              argLen:  1,
 +              asm:     mips.AOR,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
 +                      },
 +              },
 +      },
 +      {
 +              name:        "XOR",
 +              argLen:      2,
 +              commutative: true,
 +              asm:         mips.AXOR,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
 +                              {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
 +                      },
 +              },
 +      },
 +      {
 +              name:    "XORconst",
 +              auxType: auxInt64,
 +              argLen:  1,
 +              asm:     mips.AXOR,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
 +                      },
 +              },
 +      },
 +      {
 +              name:        "NOR",
 +              argLen:      2,
 +              commutative: true,
 +              asm:         mips.ANOR,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
 +                              {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
 +                      },
 +              },
 +      },
 +      {
 +              name:    "NORconst",
 +              auxType: auxInt64,
 +              argLen:  1,
 +              asm:     mips.ANOR,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
 +                      },
 +              },
 +      },
 +      {
 +              name:   "NEGV",
 +              argLen: 1,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
 +                      },
 +              },
 +      },
 +      {
 +              name:   "NEGF",
 +              argLen: 1,
 +              asm:    mips.ANEGF,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +              },
 +      },
 +      {
 +              name:   "NEGD",
 +              argLen: 1,
 +              asm:    mips.ANEGD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +              },
 +      },
 +      {
 +              name:   "ABSD",
 +              argLen: 1,
 +              asm:    mips.AABSD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +              },
 +      },
 +      {
 +              name:   "SQRTD",
 +              argLen: 1,
 +              asm:    mips.ASQRTD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +              },
 +      },
 +      {
 +              name:   "SQRTF",
 +              argLen: 1,
 +              asm:    mips.ASQRTF,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +              },
 +      },
 +      {
 +              name:   "SLLV",
 +              argLen: 2,
 +              asm:    mips.ASLLV,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
 +                              {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
 +                      },
 +              },
 +      },
 +      {
 +              name:    "SLLVconst",
 +              auxType: auxInt64,
 +              argLen:  1,
 +              asm:     mips.ASLLV,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
 +                      },
 +              },
 +      },
 +      {
 +              name:   "SRLV",
 +              argLen: 2,
 +              asm:    mips.ASRLV,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
 +                              {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
 +                      },
 +              },
 +      },
 +      {
 +              name:    "SRLVconst",
 +              auxType: auxInt64,
 +              argLen:  1,
 +              asm:     mips.ASRLV,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
 +                      },
 +              },
 +      },
 +      {
 +              name:   "SRAV",
 +              argLen: 2,
 +              asm:    mips.ASRAV,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
 +                              {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
 +                      },
 +              },
 +      },
 +      {
 +              name:    "SRAVconst",
 +              auxType: auxInt64,
 +              argLen:  1,
 +              asm:     mips.ASRAV,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
 +                      },
 +              },
 +      },
 +      {
 +              name:   "SGT",
 +              argLen: 2,
 +              asm:    mips.ASGT,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
 +                              {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
 +                      },
 +              },
 +      },
 +      {
 +              name:    "SGTconst",
 +              auxType: auxInt64,
 +              argLen:  1,
 +              asm:     mips.ASGT,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
 +                      },
 +              },
 +      },
 +      {
 +              name:   "SGTU",
 +              argLen: 2,
 +              asm:    mips.ASGTU,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
 +                              {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
 +                      },
 +              },
 +      },
 +      {
 +              name:    "SGTUconst",
 +              auxType: auxInt64,
 +              argLen:  1,
 +              asm:     mips.ASGTU,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
 +                      },
 +              },
 +      },
 +      {
 +              name:   "CMPEQF",
 +              argLen: 2,
 +              asm:    mips.ACMPEQF,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                              {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +              },
 +      },
 +      {
 +              name:   "CMPEQD",
 +              argLen: 2,
 +              asm:    mips.ACMPEQD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                              {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +              },
 +      },
 +      {
 +              name:   "CMPGEF",
 +              argLen: 2,
 +              asm:    mips.ACMPGEF,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                              {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +              },
 +      },
 +      {
 +              name:   "CMPGED",
 +              argLen: 2,
 +              asm:    mips.ACMPGED,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                              {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +              },
 +      },
 +      {
 +              name:   "CMPGTF",
 +              argLen: 2,
 +              asm:    mips.ACMPGTF,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                              {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +              },
 +      },
 +      {
 +              name:   "CMPGTD",
 +              argLen: 2,
 +              asm:    mips.ACMPGTD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                              {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +              },
 +      },
 +      {
 +              name:              "MOVVconst",
 +              auxType:           auxInt64,
 +              argLen:            0,
 +              rematerializeable: true,
 +              asm:               mips.AMOVV,
 +              reg: regInfo{
 +                      outputs: []outputInfo{
 +                              {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
 +                      },
 +              },
 +      },
 +      {
 +              name:              "MOVFconst",
 +              auxType:           auxFloat64,
 +              argLen:            0,
 +              rematerializeable: true,
 +              asm:               mips.AMOVF,
 +              reg: regInfo{
 +                      outputs: []outputInfo{
 +                              {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +              },
 +      },
 +      {
 +              name:              "MOVDconst",
 +              auxType:           auxFloat64,
 +              argLen:            0,
 +              rematerializeable: true,
 +              asm:               mips.AMOVD,
 +              reg: regInfo{
 +                      outputs: []outputInfo{
 +                              {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +              },
 +      },
 +      {
 +              name:              "MOVVaddr",
 +              auxType:           auxSymOff,
 +              argLen:            1,
 +              rematerializeable: true,
 +              symEffect:         SymAddr,
 +              asm:               mips.AMOVV,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 4611686018460942336}, // SP SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
 +                      },
 +              },
 +      },
 +      {
 +              name:           "MOVBload",
 +              auxType:        auxSymOff,
 +              argLen:         2,
 +              faultOnNilArg0: true,
 +              symEffect:      SymRead,
 +              asm:            mips.AMOVB,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
 +                      },
 +              },
 +      },
 +      {
 +              name:           "MOVBUload",
 +              auxType:        auxSymOff,
 +              argLen:         2,
 +              faultOnNilArg0: true,
 +              symEffect:      SymRead,
 +              asm:            mips.AMOVBU,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
 +                      },
 +              },
 +      },
 +      {
 +              name:           "MOVHload",
 +              auxType:        auxSymOff,
 +              argLen:         2,
 +              faultOnNilArg0: true,
 +              symEffect:      SymRead,
 +              asm:            mips.AMOVH,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
 +                      },
 +              },
 +      },
 +      {
 +              name:           "MOVHUload",
 +              auxType:        auxSymOff,
 +              argLen:         2,
 +              faultOnNilArg0: true,
 +              symEffect:      SymRead,
 +              asm:            mips.AMOVHU,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
 +                      },
 +              },
 +      },
 +      {
 +              name:           "MOVWload",
 +              auxType:        auxSymOff,
 +              argLen:         2,
 +              faultOnNilArg0: true,
 +              symEffect:      SymRead,
 +              asm:            mips.AMOVW,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
 +                      },
 +              },
 +      },
 +      {
 +              name:           "MOVWUload",
 +              auxType:        auxSymOff,
 +              argLen:         2,
 +              faultOnNilArg0: true,
 +              symEffect:      SymRead,
 +              asm:            mips.AMOVWU,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
 +                      },
 +              },
 +      },
 +      {
 +              name:           "MOVVload",
 +              auxType:        auxSymOff,
 +              argLen:         2,
 +              faultOnNilArg0: true,
 +              symEffect:      SymRead,
 +              asm:            mips.AMOVV,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
 +                      },
 +              },
 +      },
 +      {
 +              name:           "MOVFload",
 +              auxType:        auxSymOff,
 +              argLen:         2,
 +              faultOnNilArg0: true,
 +              symEffect:      SymRead,
 +              asm:            mips.AMOVF,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +              },
 +      },
 +      {
 +              name:           "MOVDload",
 +              auxType:        auxSymOff,
 +              argLen:         2,
 +              faultOnNilArg0: true,
 +              symEffect:      SymRead,
 +              asm:            mips.AMOVD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +              },
 +      },
 +      {
 +              name:           "MOVBstore",
 +              auxType:        auxSymOff,
 +              argLen:         3,
 +              faultOnNilArg0: true,
 +              symEffect:      SymWrite,
 +              asm:            mips.AMOVB,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 234881022},           // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
 +                              {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB
 +                      },
 +              },
 +      },
 +      {
 +              name:           "MOVHstore",
 +              auxType:        auxSymOff,
 +              argLen:         3,
 +              faultOnNilArg0: true,
 +              symEffect:      SymWrite,
 +              asm:            mips.AMOVH,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 234881022},           // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
 +                              {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB
 +                      },
 +              },
 +      },
 +      {
 +              name:           "MOVWstore",
 +              auxType:        auxSymOff,
 +              argLen:         3,
 +              faultOnNilArg0: true,
 +              symEffect:      SymWrite,
 +              asm:            mips.AMOVW,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 234881022},           // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
 +                              {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB
 +                      },
 +              },
 +      },
 +      {
 +              name:           "MOVVstore",
 +              auxType:        auxSymOff,
 +              argLen:         3,
 +              faultOnNilArg0: true,
 +              symEffect:      SymWrite,
 +              asm:            mips.AMOVV,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 234881022},           // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
 +                              {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB
 +                      },
 +              },
 +      },
 +      {
 +              name:           "MOVFstore",
 +              auxType:        auxSymOff,
 +              argLen:         3,
 +              faultOnNilArg0: true,
 +              symEffect:      SymWrite,
 +              asm:            mips.AMOVF,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB
 +                              {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +              },
 +      },
 +      {
 +              name:           "MOVDstore",
 +              auxType:        auxSymOff,
 +              argLen:         3,
 +              faultOnNilArg0: true,
 +              symEffect:      SymWrite,
 +              asm:            mips.AMOVD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB
 +                              {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +              },
 +      },
 +      {
 +              name:           "MOVBstorezero",
 +              auxType:        auxSymOff,
 +              argLen:         2,
 +              faultOnNilArg0: true,
 +              symEffect:      SymWrite,
 +              asm:            mips.AMOVB,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB
 +                      },
 +              },
 +      },
 +      {
 +              name:           "MOVHstorezero",
 +              auxType:        auxSymOff,
 +              argLen:         2,
 +              faultOnNilArg0: true,
 +              symEffect:      SymWrite,
 +              asm:            mips.AMOVH,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB
 +                      },
 +              },
 +      },
 +      {
 +              name:           "MOVWstorezero",
 +              auxType:        auxSymOff,
 +              argLen:         2,
 +              faultOnNilArg0: true,
 +              symEffect:      SymWrite,
 +              asm:            mips.AMOVW,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB
 +                      },
 +              },
 +      },
 +      {
 +              name:           "MOVVstorezero",
 +              auxType:        auxSymOff,
 +              argLen:         2,
 +              faultOnNilArg0: true,
 +              symEffect:      SymWrite,
 +              asm:            mips.AMOVV,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB
 +                      },
 +              },
 +      },
 +      {
 +              name:   "MOVWfpgp",
 +              argLen: 1,
 +              asm:    mips.AMOVW,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
 +                      },
 +              },
 +      },
 +      {
 +              name:   "MOVWgpfp",
 +              argLen: 1,
 +              asm:    mips.AMOVW,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +              },
 +      },
 +      {
 +              name:   "MOVVfpgp",
 +              argLen: 1,
 +              asm:    mips.AMOVV,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
 +                      },
 +              },
 +      },
 +      {
 +              name:   "MOVVgpfp",
 +              argLen: 1,
 +              asm:    mips.AMOVV,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +              },
 +      },
 +      {
 +              name:   "MOVBreg",
 +              argLen: 1,
 +              asm:    mips.AMOVB,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
 +                      },
 +              },
 +      },
 +      {
 +              name:   "MOVBUreg",
 +              argLen: 1,
 +              asm:    mips.AMOVBU,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
 +                      },
 +              },
 +      },
 +      {
 +              name:   "MOVHreg",
 +              argLen: 1,
 +              asm:    mips.AMOVH,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
 +                      },
 +              },
 +      },
 +      {
 +              name:   "MOVHUreg",
 +              argLen: 1,
 +              asm:    mips.AMOVHU,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
 +                      },
 +              },
 +      },
 +      {
 +              name:   "MOVWreg",
 +              argLen: 1,
 +              asm:    mips.AMOVW,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
 +                      },
 +              },
 +      },
 +      {
 +              name:   "MOVWUreg",
 +              argLen: 1,
 +              asm:    mips.AMOVWU,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
 +                      },
 +              },
 +      },
 +      {
 +              name:   "MOVVreg",
 +              argLen: 1,
 +              asm:    mips.AMOVV,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "MOVVnop",
 +              argLen:       1,
 +              resultInArg0: true,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
 +                      },
 +              },
 +      },
 +      {
 +              name:   "MOVWF",
 +              argLen: 1,
 +              asm:    mips.AMOVWF,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +              },
 +      },
 +      {
 +              name:   "MOVWD",
 +              argLen: 1,
 +              asm:    mips.AMOVWD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +              },
 +      },
 +      {
 +              name:   "MOVVF",
 +              argLen: 1,
 +              asm:    mips.AMOVVF,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +              },
 +      },
 +      {
 +              name:   "MOVVD",
 +              argLen: 1,
 +              asm:    mips.AMOVVD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +              },
 +      },
 +      {
 +              name:   "TRUNCFW",
 +              argLen: 1,
 +              asm:    mips.ATRUNCFW,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +              },
 +      },
 +      {
 +              name:   "TRUNCDW",
 +              argLen: 1,
 +              asm:    mips.ATRUNCDW,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +              },
 +      },
 +      {
 +              name:   "TRUNCFV",
 +              argLen: 1,
 +              asm:    mips.ATRUNCFV,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +              },
 +      },
 +      {
 +              name:   "TRUNCDV",
 +              argLen: 1,
 +              asm:    mips.ATRUNCDV,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +              },
 +      },
 +      {
 +              name:   "MOVFD",
 +              argLen: 1,
 +              asm:    mips.AMOVFD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +              },
 +      },
 +      {
 +              name:   "MOVDF",
 +              argLen: 1,
 +              asm:    mips.AMOVDF,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "CALLstatic",
 +              auxType:      auxCallOff,
 +              argLen:       1,
 +              clobberFlags: true,
 +              call:         true,
 +              reg: regInfo{
 +                      clobbers: 4611686018393833470, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 HI LO
 +              },
 +      },
 +      {
 +              name:         "CALLtail",
 +              auxType:      auxCallOff,
 +              argLen:       1,
 +              clobberFlags: true,
 +              call:         true,
 +              tailCall:     true,
 +              reg: regInfo{
 +                      clobbers: 4611686018393833470, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 HI LO
 +              },
 +      },
 +      {
 +              name:         "CALLclosure",
 +              auxType:      auxCallOff,
 +              argLen:       3,
 +              clobberFlags: true,
 +              call:         true,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 4194304},   // R22
 +                              {0, 201326590}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP R31
 +                      },
 +                      clobbers: 4611686018393833470, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 HI LO
 +              },
 +      },
 +      {
 +              name:         "CALLinter",
 +              auxType:      auxCallOff,
 +              argLen:       2,
 +              clobberFlags: true,
 +              call:         true,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
 +                      },
 +                      clobbers: 4611686018393833470, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 HI LO
 +              },
 +      },
 +      {
 +              name:           "DUFFZERO",
 +              auxType:        auxInt64,
 +              argLen:         2,
 +              faultOnNilArg0: true,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
 +                      },
 +                      clobbers: 134217730, // R1 R31
 +              },
 +      },
 +      {
 +              name:           "DUFFCOPY",
 +              auxType:        auxInt64,
 +              argLen:         3,
 +              faultOnNilArg0: true,
 +              faultOnNilArg1: true,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 4}, // R2
 +                              {1, 2}, // R1
 +                      },
 +                      clobbers: 134217734, // R1 R2 R31
 +              },
 +      },
 +      {
 +              name:           "LoweredZero",
 +              auxType:        auxInt64,
 +              argLen:         3,
 +              clobberFlags:   true,
 +              faultOnNilArg0: true,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 2},         // R1
 +                              {1, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
 +                      },
 +                      clobbers: 2, // R1
 +              },
 +      },
 +      {
 +              name:           "LoweredMove",
 +              auxType:        auxInt64,
 +              argLen:         4,
 +              clobberFlags:   true,
 +              faultOnNilArg0: true,
 +              faultOnNilArg1: true,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 4},         // R2
 +                              {1, 2},         // R1
 +                              {2, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
 +                      },
 +                      clobbers: 6, // R1 R2
 +              },
 +      },
 +      {
 +              name:           "LoweredAtomicAnd32",
 +              argLen:         3,
 +              faultOnNilArg0: true,
 +              hasSideEffects: true,
 +              unsafePoint:    true,
 +              asm:            mips.AAND,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 234881022},           // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
 +                              {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB
 +                      },
 +              },
 +      },
 +      {
 +              name:           "LoweredAtomicOr32",
 +              argLen:         3,
 +              faultOnNilArg0: true,
 +              hasSideEffects: true,
 +              unsafePoint:    true,
 +              asm:            mips.AOR,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 234881022},           // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
 +                              {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB
 +                      },
 +              },
 +      },
 +      {
 +              name:           "LoweredAtomicLoad8",
 +              argLen:         2,
 +              faultOnNilArg0: true,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
 +                      },
 +              },
 +      },
 +      {
 +              name:           "LoweredAtomicLoad32",
 +              argLen:         2,
 +              faultOnNilArg0: true,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
 +                      },
 +              },
 +      },
 +      {
 +              name:           "LoweredAtomicLoad64",
 +              argLen:         2,
 +              faultOnNilArg0: true,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
 +                      },
 +              },
 +      },
 +      {
 +              name:           "LoweredAtomicStore8",
 +              argLen:         3,
 +              faultOnNilArg0: true,
 +              hasSideEffects: true,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 234881022},           // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
 +                              {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB
 +                      },
 +              },
 +      },
 +      {
 +              name:           "LoweredAtomicStore32",
 +              argLen:         3,
 +              faultOnNilArg0: true,
 +              hasSideEffects: true,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 234881022},           // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
 +                              {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB
 +                      },
 +              },
 +      },
 +      {
 +              name:           "LoweredAtomicStore64",
 +              argLen:         3,
 +              faultOnNilArg0: true,
 +              hasSideEffects: true,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 234881022},           // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
 +                              {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB
 +                      },
 +              },
 +      },
 +      {
 +              name:           "LoweredAtomicStorezero32",
 +              argLen:         2,
 +              faultOnNilArg0: true,
 +              hasSideEffects: true,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB
 +                      },
 +              },
 +      },
 +      {
 +              name:           "LoweredAtomicStorezero64",
 +              argLen:         2,
 +              faultOnNilArg0: true,
 +              hasSideEffects: true,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB
 +                      },
 +              },
 +      },
 +      {
 +              name:            "LoweredAtomicExchange32",
 +              argLen:          3,
 +              resultNotInArgs: true,
 +              faultOnNilArg0:  true,
 +              hasSideEffects:  true,
 +              unsafePoint:     true,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 234881022},           // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
 +                              {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
 +                      },
 +              },
 +      },
 +      {
 +              name:            "LoweredAtomicExchange64",
 +              argLen:          3,
 +              resultNotInArgs: true,
 +              faultOnNilArg0:  true,
 +              hasSideEffects:  true,
 +              unsafePoint:     true,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 234881022},           // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
 +                              {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
 +                      },
 +              },
 +      },
 +      {
 +              name:            "LoweredAtomicAdd32",
 +              argLen:          3,
 +              resultNotInArgs: true,
 +              faultOnNilArg0:  true,
 +              hasSideEffects:  true,
 +              unsafePoint:     true,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 234881022},           // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
 +                              {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
 +                      },
 +              },
 +      },
 +      {
 +              name:            "LoweredAtomicAdd64",
 +              argLen:          3,
 +              resultNotInArgs: true,
 +              faultOnNilArg0:  true,
 +              hasSideEffects:  true,
 +              unsafePoint:     true,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 234881022},           // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
 +                              {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
 +                      },
 +              },
 +      },
 +      {
 +              name:            "LoweredAtomicAddconst32",
 +              auxType:         auxInt32,
 +              argLen:          2,
 +              resultNotInArgs: true,
 +              faultOnNilArg0:  true,
 +              hasSideEffects:  true,
 +              unsafePoint:     true,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
 +                      },
 +              },
 +      },
 +      {
 +              name:            "LoweredAtomicAddconst64",
 +              auxType:         auxInt64,
 +              argLen:          2,
 +              resultNotInArgs: true,
 +              faultOnNilArg0:  true,
 +              hasSideEffects:  true,
 +              unsafePoint:     true,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
 +                      },
 +              },
 +      },
 +      {
 +              name:            "LoweredAtomicCas32",
 +              argLen:          4,
 +              resultNotInArgs: true,
 +              faultOnNilArg0:  true,
 +              hasSideEffects:  true,
 +              unsafePoint:     true,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 234881022},           // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
 +                              {2, 234881022},           // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
 +                              {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
 +                      },
 +              },
 +      },
 +      {
 +              name:            "LoweredAtomicCas64",
 +              argLen:          4,
 +              resultNotInArgs: true,
 +              faultOnNilArg0:  true,
 +              hasSideEffects:  true,
 +              unsafePoint:     true,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 234881022},           // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
 +                              {2, 234881022},           // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
 +                              {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
 +                      },
 +              },
 +      },
 +      {
 +              name:           "LoweredNilCheck",
 +              argLen:         2,
 +              nilCheck:       true,
 +              faultOnNilArg0: true,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
 +                      },
 +              },
 +      },
 +      {
 +              name:   "FPFlagTrue",
 +              argLen: 1,
 +              reg: regInfo{
 +                      outputs: []outputInfo{
 +                              {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
 +                      },
 +              },
 +      },
 +      {
 +              name:   "FPFlagFalse",
 +              argLen: 1,
 +              reg: regInfo{
 +                      outputs: []outputInfo{
 +                              {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
 +                      },
 +              },
 +      },
 +      {
 +              name:      "LoweredGetClosurePtr",
 +              argLen:    0,
 +              zeroWidth: true,
 +              reg: regInfo{
 +                      outputs: []outputInfo{
 +                              {0, 4194304}, // R22
 +                      },
 +              },
 +      },
 +      {
 +              name:              "LoweredGetCallerSP",
 +              argLen:            1,
 +              rematerializeable: true,
 +              reg: regInfo{
 +                      outputs: []outputInfo{
 +                              {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
 +                      },
 +              },
 +      },
 +      {
 +              name:              "LoweredGetCallerPC",
 +              argLen:            0,
 +              rematerializeable: true,
 +              reg: regInfo{
 +                      outputs: []outputInfo{
 +                              {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "LoweredWB",
 +              auxType:      auxInt64,
 +              argLen:       1,
 +              clobberFlags: true,
 +              reg: regInfo{
 +                      clobbers: 4611686018293170176, // R31 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 HI LO
 +                      outputs: []outputInfo{
 +                              {0, 16777216}, // R25
 +                      },
 +              },
 +      },
 +      {
 +              name:           "LoweredPubBarrier",
 +              argLen:         1,
 +              hasSideEffects: true,
 +              asm:            mips.ASYNC,
 +              reg:            regInfo{},
 +      },
 +      {
 +              name:    "LoweredPanicBoundsRR",
 +              auxType: auxInt64,
 +              argLen:  3,
 +              call:    true,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 131070}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16
 +                              {1, 131070}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16
 +                      },
 +              },
 +      },
 +      {
 +              name:    "LoweredPanicBoundsRC",
 +              auxType: auxPanicBoundsC,
 +              argLen:  2,
 +              call:    true,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 131070}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16
 +                      },
 +              },
 +      },
 +      {
 +              name:    "LoweredPanicBoundsCR",
 +              auxType: auxPanicBoundsC,
 +              argLen:  2,
 +              call:    true,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 131070}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16
 +                      },
 +              },
 +      },
 +      {
 +              name:    "LoweredPanicBoundsCC",
 +              auxType: auxPanicBoundsCC,
 +              argLen:  1,
 +              call:    true,
 +              reg:     regInfo{},
 +      },
 +
 +      {
 +              name:        "ADD",
 +              argLen:      2,
 +              commutative: true,
 +              asm:         ppc64.AADD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                              {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +              },
 +      },
 +      {
 +              name:        "ADDCC",
 +              argLen:      2,
 +              commutative: true,
 +              asm:         ppc64.AADDCC,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                              {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +              },
 +      },
 +      {
 +              name:    "ADDconst",
 +              auxType: auxInt64,
 +              argLen:  1,
 +              asm:     ppc64.AADD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +              },
 +      },
 +      {
 +              name:    "ADDCCconst",
 +              auxType: auxInt64,
 +              argLen:  1,
 +              asm:     ppc64.AADDCCC,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +                      clobbers: 9223372036854775808, // XER
 +                      outputs: []outputInfo{
 +                              {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +              },
 +      },
 +      {
 +              name:        "FADD",
 +              argLen:      2,
 +              commutative: true,
 +              asm:         ppc64.AFADD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
 +                              {1, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
 +                      },
 +              },
 +      },
 +      {
 +              name:        "FADDS",
 +              argLen:      2,
 +              commutative: true,
 +              asm:         ppc64.AFADDS,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
 +                              {1, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
 +                      },
 +              },
 +      },
 +      {
 +              name:   "SUB",
 +              argLen: 2,
 +              asm:    ppc64.ASUB,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                              {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +              },
 +      },
 +      {
 +              name:   "SUBCC",
 +              argLen: 2,
 +              asm:    ppc64.ASUBCC,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                              {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +              },
 +      },
 +      {
 +              name:    "SUBFCconst",
 +              auxType: auxInt64,
 +              argLen:  1,
 +              asm:     ppc64.ASUBC,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +                      clobbers: 9223372036854775808, // XER
 +                      outputs: []outputInfo{
 +                              {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +              },
 +      },
 +      {
 +              name:   "FSUB",
 +              argLen: 2,
 +              asm:    ppc64.AFSUB,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
 +                              {1, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
 +                      },
 +              },
 +      },
 +      {
 +              name:   "FSUBS",
 +              argLen: 2,
 +              asm:    ppc64.AFSUBS,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
 +                              {1, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
 +                      },
 +              },
 +      },
 +      {
 +              name:   "XSMINJDP",
 +              argLen: 2,
 +              asm:    ppc64.AXSMINJDP,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
 +                              {1, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
 +                      },
 +              },
 +      },
 +      {
 +              name:   "XSMAXJDP",
 +              argLen: 2,
 +              asm:    ppc64.AXSMAXJDP,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
 +                              {1, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
 +                      },
 +              },
 +      },
 +      {
 +              name:        "MULLD",
 +              argLen:      2,
 +              commutative: true,
 +              asm:         ppc64.AMULLD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                              {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +              },
 +      },
 +      {
 +              name:        "MULLW",
 +              argLen:      2,
 +              commutative: true,
 +              asm:         ppc64.AMULLW,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                              {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +              },
 +      },
 +      {
 +              name:    "MULLDconst",
 +              auxType: auxInt32,
 +              argLen:  1,
 +              asm:     ppc64.AMULLD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +              },
 +      },
 +      {
 +              name:    "MULLWconst",
 +              auxType: auxInt32,
 +              argLen:  1,
 +              asm:     ppc64.AMULLW,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +              },
 +      },
 +      {
 +              name:   "MADDLD",
 +              argLen: 3,
 +              asm:    ppc64.AMADDLD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                              {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                              {2, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +              },
 +      },
 +      {
 +              name:        "MULHD",
 +              argLen:      2,
 +              commutative: true,
 +              asm:         ppc64.AMULHD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                              {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +              },
 +      },
 +      {
 +              name:        "MULHW",
 +              argLen:      2,
 +              commutative: true,
 +              asm:         ppc64.AMULHW,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                              {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +              },
 +      },
 +      {
 +              name:        "MULHDU",
 +              argLen:      2,
 +              commutative: true,
 +              asm:         ppc64.AMULHDU,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                              {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +              },
 +      },
 +      {
 +              name:        "MULHDUCC",
 +              argLen:      2,
 +              commutative: true,
 +              asm:         ppc64.AMULHDUCC,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                              {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +              },
 +      },
 +      {
 +              name:        "MULHWU",
 +              argLen:      2,
 +              commutative: true,
 +              asm:         ppc64.AMULHWU,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                              {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +              },
 +      },
 +      {
 +              name:        "FMUL",
 +              argLen:      2,
 +              commutative: true,
 +              asm:         ppc64.AFMUL,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
 +                              {1, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
 +                      },
 +              },
 +      },
 +      {
 +              name:        "FMULS",
 +              argLen:      2,
 +              commutative: true,
 +              asm:         ppc64.AFMULS,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
 +                              {1, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
 +                      },
 +              },
 +      },
 +      {
 +              name:   "FMADD",
 +              argLen: 3,
 +              asm:    ppc64.AFMADD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
 +                              {1, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
 +                              {2, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
 +                      },
 +              },
 +      },
 +      {
 +              name:   "FMADDS",
 +              argLen: 3,
 +              asm:    ppc64.AFMADDS,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
 +                              {1, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
 +                              {2, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
 +                      },
 +              },
 +      },
 +      {
 +              name:   "FMSUB",
 +              argLen: 3,
 +              asm:    ppc64.AFMSUB,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
 +                              {1, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
 +                              {2, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
 +                      },
 +              },
 +      },
 +      {
 +              name:   "FMSUBS",
 +              argLen: 3,
 +              asm:    ppc64.AFMSUBS,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
 +                              {1, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
 +                              {2, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
 +                      },
 +              },
 +      },
 +      {
 +              name:   "SRAD",
 +              argLen: 2,
 +              asm:    ppc64.ASRAD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                              {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +                      clobbers: 9223372036854775808, // XER
 +                      outputs: []outputInfo{
 +                              {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +              },
 +      },
 +      {
 +              name:   "SRAW",
 +              argLen: 2,
 +              asm:    ppc64.ASRAW,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                              {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +                      clobbers: 9223372036854775808, // XER
 +                      outputs: []outputInfo{
 +                              {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +              },
 +      },
 +      {
 +              name:   "SRD",
 +              argLen: 2,
 +              asm:    ppc64.ASRD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                              {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +              },
 +      },
 +      {
 +              name:   "SRW",
 +              argLen: 2,
 +              asm:    ppc64.ASRW,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                              {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +              },
 +      },
 +      {
 +              name:   "SLD",
 +              argLen: 2,
 +              asm:    ppc64.ASLD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                              {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +              },
 +      },
 +      {
 +              name:   "SLW",
 +              argLen: 2,
 +              asm:    ppc64.ASLW,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                              {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +              },
 +      },
 +      {
 +              name:   "ROTL",
 +              argLen: 2,
 +              asm:    ppc64.AROTL,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                              {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +              },
 +      },
 +      {
 +              name:   "ROTLW",
 +              argLen: 2,
 +              asm:    ppc64.AROTLW,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                              {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +              },
 +      },
 +      {
 +              name:    "CLRLSLWI",
 +              auxType: auxInt32,
 +              argLen:  1,
 +              asm:     ppc64.ACLRLSLWI,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +              },
 +      },
 +      {
 +              name:    "CLRLSLDI",
 +              auxType: auxInt32,
 +              argLen:  1,
 +              asm:     ppc64.ACLRLSLDI,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +              },
 +      },
 +      {
 +              name:        "ADDC",
 +              argLen:      2,
 +              commutative: true,
 +              asm:         ppc64.AADDC,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                              {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +                      clobbers: 9223372036854775808, // XER
 +                      outputs: []outputInfo{
 +                              {1, 9223372036854775808}, // XER
 +                              {0, 1073733624},          // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +              },
 +      },
 +      {
 +              name:   "SUBC",
 +              argLen: 2,
 +              asm:    ppc64.ASUBC,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                              {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +                      clobbers: 9223372036854775808, // XER
 +                      outputs: []outputInfo{
 +                              {1, 9223372036854775808}, // XER
 +                              {0, 1073733624},          // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +              },
 +      },
 +      {
 +              name:    "ADDCconst",
 +              auxType: auxInt64,
 +              argLen:  1,
 +              asm:     ppc64.AADDC,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +                      outputs: []outputInfo{
 +                              {1, 9223372036854775808}, // XER
 +                              {0, 1073733624},          // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +              },
 +      },
 +      {
 +              name:    "SUBCconst",
 +              auxType: auxInt64,
 +              argLen:  1,
 +              asm:     ppc64.ASUBC,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +                      outputs: []outputInfo{
 +                              {1, 9223372036854775808}, // XER
 +                              {0, 1073733624},          // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +              },
 +      },
 +      {
 +              name:        "ADDE",
 +              argLen:      3,
 +              commutative: true,
 +              asm:         ppc64.AADDE,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {2, 9223372036854775808}, // XER
 +                              {0, 1073733630},          // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                              {1, 1073733630},          // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +                      clobbers: 9223372036854775808, // XER
 +                      outputs: []outputInfo{
 +                              {1, 9223372036854775808}, // XER
 +                              {0, 1073733624},          // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +              },
 +      },
 +      {
 +              name:   "ADDZE",
 +              argLen: 2,
 +              asm:    ppc64.AADDZE,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 9223372036854775808}, // XER
 +                              {0, 1073733630},          // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +                      clobbers: 9223372036854775808, // XER
 +                      outputs: []outputInfo{
 +                              {1, 9223372036854775808}, // XER
 +                              {0, 1073733624},          // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +              },
 +      },
 +      {
 +              name:   "SUBE",
 +              argLen: 3,
 +              asm:    ppc64.ASUBE,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {2, 9223372036854775808}, // XER
 +                              {0, 1073733630},          // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                              {1, 1073733630},          // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +                      clobbers: 9223372036854775808, // XER
 +                      outputs: []outputInfo{
 +                              {1, 9223372036854775808}, // XER
 +                              {0, 1073733624},          // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +              },
 +      },
 +      {
 +              name:   "ADDZEzero",
 +              argLen: 1,
 +              asm:    ppc64.AADDZE,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 9223372036854775808}, // XER
 +                      },
 +                      clobbers: 9223372036854775808, // XER
 +                      outputs: []outputInfo{
 +                              {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +              },
 +      },
 +      {
 +              name:   "SUBZEzero",
 +              argLen: 1,
 +              asm:    ppc64.ASUBZE,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 9223372036854775808}, // XER
 +                      },
 +                      clobbers: 9223372036854775808, // XER
 +                      outputs: []outputInfo{
 +                              {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +              },
 +      },
 +      {
 +              name:    "SRADconst",
 +              auxType: auxInt64,
 +              argLen:  1,
 +              asm:     ppc64.ASRAD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +                      clobbers: 9223372036854775808, // XER
 +                      outputs: []outputInfo{
 +                              {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +              },
 +      },
 +      {
 +              name:    "SRAWconst",
 +              auxType: auxInt64,
 +              argLen:  1,
 +              asm:     ppc64.ASRAW,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +                      clobbers: 9223372036854775808, // XER
 +                      outputs: []outputInfo{
 +                              {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +              },
 +      },
 +      {
 +              name:    "SRDconst",
 +              auxType: auxInt64,
 +              argLen:  1,
 +              asm:     ppc64.ASRD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +              },
 +      },
 +      {
 +              name:    "SRWconst",
 +              auxType: auxInt64,
 +              argLen:  1,
 +              asm:     ppc64.ASRW,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +              },
 +      },
 +      {
 +              name:    "SLDconst",
 +              auxType: auxInt64,
 +              argLen:  1,
 +              asm:     ppc64.ASLD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +              },
 +      },
 +      {
 +              name:    "SLWconst",
 +              auxType: auxInt64,
 +              argLen:  1,
 +              asm:     ppc64.ASLW,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +              },
 +      },
 +      {
 +              name:    "ROTLconst",
 +              auxType: auxInt64,
 +              argLen:  1,
 +              asm:     ppc64.AROTL,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +              },
 +      },
 +      {
 +              name:    "ROTLWconst",
 +              auxType: auxInt64,
 +              argLen:  1,
 +              asm:     ppc64.AROTLW,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +              },
 +      },
 +      {
 +              name:    "EXTSWSLconst",
 +              auxType: auxInt64,
 +              argLen:  1,
 +              asm:     ppc64.AEXTSWSLI,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +              },
 +      },
 +      {
 +              name:    "RLWINM",
 +              auxType: auxInt64,
 +              argLen:  1,
 +              asm:     ppc64.ARLWNM,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +              },
 +      },
 +      {
 +              name:    "RLWNM",
 +              auxType: auxInt64,
 +              argLen:  2,
 +              asm:     ppc64.ARLWNM,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                              {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +              },
 +      },
 +      {
 +              name:         "RLWMI",
 +              auxType:      auxInt64,
 +              argLen:       2,
 +              resultInArg0: true,
 +              asm:          ppc64.ARLWMI,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                              {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +              },
 +      },
 +      {
 +              name:    "RLDICL",
 +              auxType: auxInt64,
 +              argLen:  1,
 +              asm:     ppc64.ARLDICL,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +              },
 +      },
 +      {
 +              name:    "RLDICLCC",
 +              auxType: auxInt64,
 +              argLen:  1,
 +              asm:     ppc64.ARLDICLCC,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +              },
 +      },
 +      {
 +              name:    "RLDICR",
 +              auxType: auxInt64,
 +              argLen:  1,
 +              asm:     ppc64.ARLDICR,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +              },
 +      },
 +      {
 +              name:   "CNTLZD",
 +              argLen: 1,
 +              asm:    ppc64.ACNTLZD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +              },
 +      },
 +      {
 +              name:   "CNTLZDCC",
 +              argLen: 1,
 +              asm:    ppc64.ACNTLZDCC,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +              },
 +      },
 +      {
 +              name:   "CNTLZW",
 +              argLen: 1,
 +              asm:    ppc64.ACNTLZW,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +              },
 +      },
 +      {
 +              name:   "CNTTZD",
 +              argLen: 1,
 +              asm:    ppc64.ACNTTZD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +              },
 +      },
 +      {
 +              name:   "CNTTZW",
 +              argLen: 1,
 +              asm:    ppc64.ACNTTZW,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +              },
 +      },
 +      {
 +              name:   "POPCNTD",
 +              argLen: 1,
 +              asm:    ppc64.APOPCNTD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +              },
 +      },
 +      {
 +              name:   "POPCNTW",
 +              argLen: 1,
 +              asm:    ppc64.APOPCNTW,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +              },
 +      },
 +      {
 +              name:   "POPCNTB",
 +              argLen: 1,
 +              asm:    ppc64.APOPCNTB,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +              },
 +      },
 +      {
 +              name:   "FDIV",
 +              argLen: 2,
 +              asm:    ppc64.AFDIV,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
 +                              {1, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
 +                      },
 +              },
 +      },
 +      {
 +              name:   "FDIVS",
 +              argLen: 2,
 +              asm:    ppc64.AFDIVS,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
 +                              {1, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
 +                      },
 +              },
 +      },
 +      {
 +              name:   "DIVD",
 +              argLen: 2,
 +              asm:    ppc64.ADIVD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                              {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +              },
 +      },
 +      {
 +              name:   "DIVW",
 +              argLen: 2,
 +              asm:    ppc64.ADIVW,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                              {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +              },
 +      },
 +      {
 +              name:   "DIVDU",
 +              argLen: 2,
 +              asm:    ppc64.ADIVDU,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                              {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +              },
 +      },
 +      {
 +              name:   "DIVWU",
 +              argLen: 2,
 +              asm:    ppc64.ADIVWU,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                              {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +              },
 +      },
 +      {
 +              name:   "MODUD",
 +              argLen: 2,
 +              asm:    ppc64.AMODUD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                              {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +              },
 +      },
 +      {
 +              name:   "MODSD",
 +              argLen: 2,
 +              asm:    ppc64.AMODSD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                              {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +              },
 +      },
 +      {
 +              name:   "MODUW",
 +              argLen: 2,
 +              asm:    ppc64.AMODUW,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                              {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +              },
 +      },
 +      {
 +              name:   "MODSW",
 +              argLen: 2,
 +              asm:    ppc64.AMODSW,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                              {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +              },
 +      },
 +      {
 +              name:   "FCTIDZ",
 +              argLen: 1,
 +              asm:    ppc64.AFCTIDZ,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
 +                      },
 +              },
 +      },
 +      {
 +              name:   "FCTIWZ",
 +              argLen: 1,
 +              asm:    ppc64.AFCTIWZ,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
 +                      },
 +              },
 +      },
 +      {
 +              name:   "FCFID",
 +              argLen: 1,
 +              asm:    ppc64.AFCFID,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
 +                      },
 +              },
 +      },
 +      {
 +              name:   "FCFIDS",
 +              argLen: 1,
 +              asm:    ppc64.AFCFIDS,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
 +                      },
 +              },
 +      },
 +      {
 +              name:   "FRSP",
 +              argLen: 1,
 +              asm:    ppc64.AFRSP,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
 +                      },
 +              },
 +      },
 +      {
 +              name:   "MFVSRD",
 +              argLen: 1,
 +              asm:    ppc64.AMFVSRD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +              },
 +      },
 +      {
 +              name:   "MTVSRD",
 +              argLen: 1,
 +              asm:    ppc64.AMTVSRD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
 +                      },
 +              },
 +      },
 +      {
 +              name:        "AND",
 +              argLen:      2,
 +              commutative: true,
 +              asm:         ppc64.AAND,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                              {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +              },
 +      },
 +      {
 +              name:   "ANDN",
 +              argLen: 2,
 +              asm:    ppc64.AANDN,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                              {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +              },
 +      },
 +      {
 +              name:   "ANDNCC",
 +              argLen: 2,
 +              asm:    ppc64.AANDNCC,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                              {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +              },
 +      },
 +      {
 +              name:        "ANDCC",
 +              argLen:      2,
 +              commutative: true,
 +              asm:         ppc64.AANDCC,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                              {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +              },
 +      },
 +      {
 +              name:        "OR",
 +              argLen:      2,
 +              commutative: true,
 +              asm:         ppc64.AOR,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                              {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +              },
 +      },
 +      {
 +              name:   "ORN",
 +              argLen: 2,
 +              asm:    ppc64.AORN,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                              {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +              },
 +      },
 +      {
 +              name:        "ORCC",
 +              argLen:      2,
 +              commutative: true,
 +              asm:         ppc64.AORCC,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                              {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +              },
 +      },
 +      {
 +              name:        "NOR",
 +              argLen:      2,
 +              commutative: true,
 +              asm:         ppc64.ANOR,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                              {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +              },
 +      },
 +      {
 +              name:        "NORCC",
 +              argLen:      2,
 +              commutative: true,
 +              asm:         ppc64.ANORCC,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                              {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +              },
 +      },
 +      {
 +              name:        "XOR",
 +              argLen:      2,
 +              commutative: true,
 +              asm:         ppc64.AXOR,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                              {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +              },
 +      },
 +      {
 +              name:        "XORCC",
 +              argLen:      2,
 +              commutative: true,
 +              asm:         ppc64.AXORCC,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                              {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +              },
 +      },
 +      {
 +              name:        "EQV",
 +              argLen:      2,
 +              commutative: true,
 +              asm:         ppc64.AEQV,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                              {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +              },
 +      },
 +      {
 +              name:   "NEG",
 +              argLen: 1,
 +              asm:    ppc64.ANEG,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +              },
 +      },
 +      {
 +              name:   "NEGCC",
 +              argLen: 1,
 +              asm:    ppc64.ANEGCC,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +              },
 +      },
 +      {
 +              name:   "BRD",
 +              argLen: 1,
 +              asm:    ppc64.ABRD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +              },
 +      },
 +      {
 +              name:   "BRW",
 +              argLen: 1,
 +              asm:    ppc64.ABRW,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +              },
 +      },
 +      {
 +              name:   "BRH",
 +              argLen: 1,
 +              asm:    ppc64.ABRH,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +              },
 +      },
 +      {
 +              name:   "FNEG",
 +              argLen: 1,
 +              asm:    ppc64.AFNEG,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
 +                      },
 +              },
 +      },
 +      {
 +              name:   "FSQRT",
 +              argLen: 1,
 +              asm:    ppc64.AFSQRT,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
 +                      },
 +              },
 +      },
 +      {
 +              name:   "FSQRTS",
 +              argLen: 1,
 +              asm:    ppc64.AFSQRTS,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
 +                      },
 +              },
 +      },
 +      {
 +              name:   "FFLOOR",
 +              argLen: 1,
 +              asm:    ppc64.AFRIM,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
 +                      },
 +              },
 +      },
 +      {
 +              name:   "FCEIL",
 +              argLen: 1,
 +              asm:    ppc64.AFRIP,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
 +                      },
 +              },
 +      },
 +      {
 +              name:   "FTRUNC",
 +              argLen: 1,
 +              asm:    ppc64.AFRIZ,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
 +                      },
 +              },
 +      },
 +      {
 +              name:   "FROUND",
 +              argLen: 1,
 +              asm:    ppc64.AFRIN,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
 +                      },
 +              },
 +      },
 +      {
 +              name:   "FABS",
 +              argLen: 1,
 +              asm:    ppc64.AFABS,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
 +                      },
 +              },
 +      },
 +      {
 +              name:   "FNABS",
 +              argLen: 1,
 +              asm:    ppc64.AFNABS,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
 +                      },
 +              },
 +      },
 +      {
 +              name:   "FCPSGN",
 +              argLen: 2,
 +              asm:    ppc64.AFCPSGN,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
 +                              {1, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
 +                      },
 +              },
 +      },
 +      {
 +              name:    "ORconst",
 +              auxType: auxInt64,
 +              argLen:  1,
 +              asm:     ppc64.AOR,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +              },
 +      },
 +      {
 +              name:    "XORconst",
 +              auxType: auxInt64,
 +              argLen:  1,
 +              asm:     ppc64.AXOR,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +              },
 +      },
 +      {
 +              name:    "ANDCCconst",
 +              auxType: auxInt64,
 +              argLen:  1,
 +              asm:     ppc64.AANDCC,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +              },
 +      },
 +      {
 +              name:         "ANDconst",
 +              auxType:      auxInt64,
 +              argLen:       1,
 +              clobberFlags: true,
 +              asm:          ppc64.AANDCC,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +              },
 +      },
 +      {
 +              name:   "MOVBreg",
 +              argLen: 1,
 +              asm:    ppc64.AMOVB,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +              },
 +      },
 +      {
 +              name:   "MOVBZreg",
 +              argLen: 1,
 +              asm:    ppc64.AMOVBZ,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +              },
 +      },
 +      {
 +              name:   "MOVHreg",
 +              argLen: 1,
 +              asm:    ppc64.AMOVH,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +              },
 +      },
 +      {
 +              name:   "MOVHZreg",
 +              argLen: 1,
 +              asm:    ppc64.AMOVHZ,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +              },
 +      },
 +      {
 +              name:   "MOVWreg",
 +              argLen: 1,
 +              asm:    ppc64.AMOVW,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +              },
 +      },
 +      {
 +              name:   "MOVWZreg",
 +              argLen: 1,
 +              asm:    ppc64.AMOVWZ,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +              },
 +      },
 +      {
 +              name:           "MOVBZload",
 +              auxType:        auxSymOff,
 +              argLen:         2,
 +              faultOnNilArg0: true,
 +              symEffect:      SymRead,
 +              asm:            ppc64.AMOVBZ,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +              },
 +      },
 +      {
 +              name:           "MOVHload",
 +              auxType:        auxSymOff,
 +              argLen:         2,
 +              faultOnNilArg0: true,
 +              symEffect:      SymRead,
 +              asm:            ppc64.AMOVH,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +              },
 +      },
 +      {
 +              name:           "MOVHZload",
 +              auxType:        auxSymOff,
 +              argLen:         2,
 +              faultOnNilArg0: true,
 +              symEffect:      SymRead,
 +              asm:            ppc64.AMOVHZ,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +              },
 +      },
 +      {
 +              name:           "MOVWload",
 +              auxType:        auxSymOff,
 +              argLen:         2,
 +              faultOnNilArg0: true,
 +              symEffect:      SymRead,
 +              asm:            ppc64.AMOVW,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +              },
 +      },
 +      {
 +              name:           "MOVWZload",
 +              auxType:        auxSymOff,
 +              argLen:         2,
 +              faultOnNilArg0: true,
 +              symEffect:      SymRead,
 +              asm:            ppc64.AMOVWZ,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +              },
 +      },
 +      {
 +              name:           "MOVDload",
 +              auxType:        auxSymOff,
 +              argLen:         2,
 +              faultOnNilArg0: true,
 +              symEffect:      SymRead,
 +              asm:            ppc64.AMOVD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +              },
 +      },
 +      {
 +              name:           "MOVDBRload",
 +              argLen:         2,
 +              faultOnNilArg0: true,
 +              asm:            ppc64.AMOVDBR,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +              },
 +      },
 +      {
 +              name:           "MOVWBRload",
 +              argLen:         2,
 +              faultOnNilArg0: true,
 +              asm:            ppc64.AMOVWBR,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +              },
 +      },
 +      {
 +              name:           "MOVHBRload",
 +              argLen:         2,
 +              faultOnNilArg0: true,
 +              asm:            ppc64.AMOVHBR,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +              },
 +      },
 +      {
 +              name:   "MOVBZloadidx",
 +              argLen: 3,
 +              asm:    ppc64.AMOVBZ,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                              {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +              },
 +      },
 +      {
 +              name:   "MOVHloadidx",
 +              argLen: 3,
 +              asm:    ppc64.AMOVH,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                              {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +              },
 +      },
 +      {
 +              name:   "MOVHZloadidx",
 +              argLen: 3,
 +              asm:    ppc64.AMOVHZ,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                              {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +              },
 +      },
 +      {
 +              name:   "MOVWloadidx",
 +              argLen: 3,
 +              asm:    ppc64.AMOVW,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                              {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +              },
 +      },
 +      {
 +              name:   "MOVWZloadidx",
 +              argLen: 3,
 +              asm:    ppc64.AMOVWZ,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                              {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +              },
 +      },
 +      {
 +              name:   "MOVDloadidx",
 +              argLen: 3,
 +              asm:    ppc64.AMOVD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                              {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +              },
 +      },
 +      {
 +              name:   "MOVHBRloadidx",
 +              argLen: 3,
 +              asm:    ppc64.AMOVHBR,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                              {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +              },
 +      },
 +      {
 +              name:   "MOVWBRloadidx",
 +              argLen: 3,
 +              asm:    ppc64.AMOVWBR,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                              {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +              },
 +      },
 +      {
 +              name:   "MOVDBRloadidx",
 +              argLen: 3,
 +              asm:    ppc64.AMOVDBR,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                              {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +              },
 +      },
 +      {
 +              name:   "FMOVDloadidx",
 +              argLen: 3,
 +              asm:    ppc64.AFMOVD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                              {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
 +                      },
 +              },
 +      },
 +      {
 +              name:   "FMOVSloadidx",
 +              argLen: 3,
 +              asm:    ppc64.AFMOVS,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                              {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
 +                      },
 +              },
 +      },
 +      {
 +              name:           "DCBT",
 +              auxType:        auxInt64,
 +              argLen:         2,
 +              hasSideEffects: true,
 +              asm:            ppc64.ADCBT,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +              },
 +      },
 +      {
 +              name:           "MOVDBRstore",
 +              argLen:         3,
 +              faultOnNilArg0: true,
 +              asm:            ppc64.AMOVDBR,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                              {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +              },
 +      },
 +      {
 +              name:           "MOVWBRstore",
 +              argLen:         3,
 +              faultOnNilArg0: true,
 +              asm:            ppc64.AMOVWBR,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                              {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +              },
 +      },
 +      {
 +              name:           "MOVHBRstore",
 +              argLen:         3,
 +              faultOnNilArg0: true,
 +              asm:            ppc64.AMOVHBR,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                              {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +              },
 +      },
 +      {
 +              name:           "FMOVDload",
 +              auxType:        auxSymOff,
 +              argLen:         2,
 +              faultOnNilArg0: true,
 +              symEffect:      SymRead,
 +              asm:            ppc64.AFMOVD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
 +                      },
 +              },
 +      },
 +      {
 +              name:           "FMOVSload",
 +              auxType:        auxSymOff,
 +              argLen:         2,
 +              faultOnNilArg0: true,
 +              symEffect:      SymRead,
 +              asm:            ppc64.AFMOVS,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
 +                      },
 +              },
 +      },
 +      {
 +              name:           "MOVBstore",
 +              auxType:        auxSymOff,
 +              argLen:         3,
 +              faultOnNilArg0: true,
 +              symEffect:      SymWrite,
 +              asm:            ppc64.AMOVB,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                              {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +              },
 +      },
 +      {
 +              name:           "MOVHstore",
 +              auxType:        auxSymOff,
 +              argLen:         3,
 +              faultOnNilArg0: true,
 +              symEffect:      SymWrite,
 +              asm:            ppc64.AMOVH,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                              {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +              },
 +      },
 +      {
 +              name:           "MOVWstore",
 +              auxType:        auxSymOff,
 +              argLen:         3,
 +              faultOnNilArg0: true,
 +              symEffect:      SymWrite,
 +              asm:            ppc64.AMOVW,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                              {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +              },
 +      },
 +      {
 +              name:           "MOVDstore",
 +              auxType:        auxSymOff,
 +              argLen:         3,
 +              faultOnNilArg0: true,
 +              symEffect:      SymWrite,
 +              asm:            ppc64.AMOVD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                              {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +              },
 +      },
 +      {
 +              name:           "FMOVDstore",
 +              auxType:        auxSymOff,
 +              argLen:         3,
 +              faultOnNilArg0: true,
 +              symEffect:      SymWrite,
 +              asm:            ppc64.AFMOVD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1073733630},          // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                              {1, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
 +                      },
 +              },
 +      },
 +      {
 +              name:           "FMOVSstore",
 +              auxType:        auxSymOff,
 +              argLen:         3,
 +              faultOnNilArg0: true,
 +              symEffect:      SymWrite,
 +              asm:            ppc64.AFMOVS,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1073733630},          // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                              {1, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
 +                      },
 +              },
 +      },
 +      {
 +              name:   "MOVBstoreidx",
 +              argLen: 4,
 +              asm:    ppc64.AMOVB,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                              {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                              {2, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +              },
 +      },
 +      {
 +              name:   "MOVHstoreidx",
 +              argLen: 4,
 +              asm:    ppc64.AMOVH,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                              {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                              {2, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +              },
 +      },
 +      {
 +              name:   "MOVWstoreidx",
 +              argLen: 4,
 +              asm:    ppc64.AMOVW,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                              {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                              {2, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +              },
 +      },
 +      {
 +              name:   "MOVDstoreidx",
 +              argLen: 4,
 +              asm:    ppc64.AMOVD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                              {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                              {2, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +              },
 +      },
 +      {
 +              name:   "FMOVDstoreidx",
 +              argLen: 4,
 +              asm:    ppc64.AFMOVD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1073733630},          // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                              {1, 1073733630},          // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                              {2, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
 +                      },
 +              },
 +      },
 +      {
 +              name:   "FMOVSstoreidx",
 +              argLen: 4,
 +              asm:    ppc64.AFMOVS,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1073733630},          // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                              {1, 1073733630},          // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                              {2, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
 +                      },
 +              },
 +      },
 +      {
 +              name:   "MOVHBRstoreidx",
 +              argLen: 4,
 +              asm:    ppc64.AMOVHBR,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                              {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                              {2, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +              },
 +      },
 +      {
 +              name:   "MOVWBRstoreidx",
 +              argLen: 4,
 +              asm:    ppc64.AMOVWBR,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                              {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                              {2, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +              },
 +      },
 +      {
 +              name:   "MOVDBRstoreidx",
 +              argLen: 4,
 +              asm:    ppc64.AMOVDBR,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                              {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                              {2, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +              },
 +      },
 +      {
 +              name:           "MOVBstorezero",
 +              auxType:        auxSymOff,
 +              argLen:         2,
 +              faultOnNilArg0: true,
 +              symEffect:      SymWrite,
 +              asm:            ppc64.AMOVB,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +              },
 +      },
 +      {
 +              name:           "MOVHstorezero",
 +              auxType:        auxSymOff,
 +              argLen:         2,
 +              faultOnNilArg0: true,
 +              symEffect:      SymWrite,
 +              asm:            ppc64.AMOVH,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +              },
 +      },
 +      {
 +              name:           "MOVWstorezero",
 +              auxType:        auxSymOff,
 +              argLen:         2,
 +              faultOnNilArg0: true,
 +              symEffect:      SymWrite,
 +              asm:            ppc64.AMOVW,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +              },
 +      },
 +      {
 +              name:           "MOVDstorezero",
 +              auxType:        auxSymOff,
 +              argLen:         2,
 +              faultOnNilArg0: true,
 +              symEffect:      SymWrite,
 +              asm:            ppc64.AMOVD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +              },
 +      },
 +      {
 +              name:              "MOVDaddr",
 +              auxType:           auxSymOff,
 +              argLen:            1,
 +              rematerializeable: true,
 +              symEffect:         SymAddr,
 +              asm:               ppc64.AMOVD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +              },
 +      },
 +      {
 +              name:              "MOVDconst",
 +              auxType:           auxInt64,
 +              argLen:            0,
 +              rematerializeable: true,
 +              asm:               ppc64.AMOVD,
 +              reg: regInfo{
 +                      outputs: []outputInfo{
 +                              {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +              },
 +      },
 +      {
 +              name:              "FMOVDconst",
 +              auxType:           auxFloat64,
 +              argLen:            0,
 +              rematerializeable: true,
 +              asm:               ppc64.AFMOVD,
 +              reg: regInfo{
 +                      outputs: []outputInfo{
 +                              {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
 +                      },
 +              },
 +      },
 +      {
 +              name:              "FMOVSconst",
 +              auxType:           auxFloat32,
 +              argLen:            0,
 +              rematerializeable: true,
 +              asm:               ppc64.AFMOVS,
 +              reg: regInfo{
 +                      outputs: []outputInfo{
 +                              {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
 +                      },
 +              },
 +      },
 +      {
 +              name:   "FCMPU",
 +              argLen: 2,
 +              asm:    ppc64.AFCMPU,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
 +                              {1, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
 +                      },
 +              },
 +      },
 +      {
 +              name:   "CMP",
 +              argLen: 2,
 +              asm:    ppc64.ACMP,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                              {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +              },
 +      },
 +      {
 +              name:   "CMPU",
 +              argLen: 2,
 +              asm:    ppc64.ACMPU,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                              {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +              },
 +      },
 +      {
 +              name:   "CMPW",
 +              argLen: 2,
 +              asm:    ppc64.ACMPW,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                              {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +              },
 +      },
 +      {
 +              name:   "CMPWU",
 +              argLen: 2,
 +              asm:    ppc64.ACMPWU,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                              {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +              },
 +      },
 +      {
 +              name:    "CMPconst",
 +              auxType: auxInt64,
 +              argLen:  1,
 +              asm:     ppc64.ACMP,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +              },
 +      },
 +      {
 +              name:    "CMPUconst",
 +              auxType: auxInt64,
 +              argLen:  1,
 +              asm:     ppc64.ACMPU,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +              },
 +      },
 +      {
 +              name:    "CMPWconst",
 +              auxType: auxInt32,
 +              argLen:  1,
 +              asm:     ppc64.ACMPW,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +              },
 +      },
 +      {
 +              name:    "CMPWUconst",
 +              auxType: auxInt32,
 +              argLen:  1,
 +              asm:     ppc64.ACMPWU,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +              },
 +      },
 +      {
 +              name:    "ISEL",
 +              auxType: auxInt32,
 +              argLen:  3,
 +              asm:     ppc64.AISEL,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                              {1, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +              },
 +      },
 +      {
 +              name:    "ISELZ",
 +              auxType: auxInt32,
 +              argLen:  2,
 +              asm:     ppc64.AISEL,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +              },
 +      },
 +      {
 +              name:    "SETBC",
 +              auxType: auxInt32,
 +              argLen:  1,
 +              asm:     ppc64.ASETBC,
 +              reg: regInfo{
 +                      outputs: []outputInfo{
 +                              {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +              },
 +      },
 +      {
 +              name:    "SETBCR",
 +              auxType: auxInt32,
 +              argLen:  1,
 +              asm:     ppc64.ASETBCR,
 +              reg: regInfo{
 +                      outputs: []outputInfo{
 +                              {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +              },
 +      },
 +      {
 +              name:   "Equal",
 +              argLen: 1,
 +              reg: regInfo{
 +                      outputs: []outputInfo{
 +                              {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +              },
 +      },
 +      {
 +              name:   "NotEqual",
 +              argLen: 1,
 +              reg: regInfo{
 +                      outputs: []outputInfo{
 +                              {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +              },
 +      },
 +      {
 +              name:   "LessThan",
 +              argLen: 1,
 +              reg: regInfo{
 +                      outputs: []outputInfo{
 +                              {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +              },
 +      },
 +      {
 +              name:   "FLessThan",
 +              argLen: 1,
 +              reg: regInfo{
 +                      outputs: []outputInfo{
 +                              {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +              },
 +      },
 +      {
 +              name:   "LessEqual",
 +              argLen: 1,
 +              reg: regInfo{
 +                      outputs: []outputInfo{
 +                              {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +              },
 +      },
 +      {
 +              name:   "FLessEqual",
 +              argLen: 1,
 +              reg: regInfo{
 +                      outputs: []outputInfo{
 +                              {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +              },
 +      },
 +      {
 +              name:   "GreaterThan",
 +              argLen: 1,
 +              reg: regInfo{
 +                      outputs: []outputInfo{
 +                              {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +              },
 +      },
 +      {
 +              name:   "FGreaterThan",
 +              argLen: 1,
 +              reg: regInfo{
 +                      outputs: []outputInfo{
 +                              {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +              },
 +      },
 +      {
 +              name:   "GreaterEqual",
 +              argLen: 1,
 +              reg: regInfo{
 +                      outputs: []outputInfo{
 +                              {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +              },
 +      },
 +      {
 +              name:   "FGreaterEqual",
 +              argLen: 1,
 +              reg: regInfo{
 +                      outputs: []outputInfo{
 +                              {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +              },
 +      },
 +      {
 +              name:      "LoweredGetClosurePtr",
 +              argLen:    0,
 +              zeroWidth: true,
 +              reg: regInfo{
 +                      outputs: []outputInfo{
 +                              {0, 2048}, // R11
 +                      },
 +              },
 +      },
 +      {
 +              name:              "LoweredGetCallerSP",
 +              argLen:            1,
 +              rematerializeable: true,
 +              reg: regInfo{
 +                      outputs: []outputInfo{
 +                              {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +              },
 +      },
 +      {
 +              name:              "LoweredGetCallerPC",
 +              argLen:            0,
 +              rematerializeable: true,
 +              reg: regInfo{
 +                      outputs: []outputInfo{
 +                              {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +              },
 +      },
 +      {
 +              name:           "LoweredNilCheck",
 +              argLen:         2,
 +              clobberFlags:   true,
 +              nilCheck:       true,
 +              faultOnNilArg0: true,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +                      clobbers: 2147483648, // R31
 +              },
 +      },
 +      {
 +              name:         "LoweredRound32F",
 +              argLen:       1,
 +              resultInArg0: true,
 +              zeroWidth:    true,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
 +                      },
 +              },
 +      },
 +      {
 +              name:         "LoweredRound64F",
 +              argLen:       1,
 +              resultInArg0: true,
 +              zeroWidth:    true,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
 +                      },
 +              },
 +      },
 +      {
 +              name:         "CALLstatic",
 +              auxType:      auxCallOff,
 +              argLen:       -1,
 +              clobberFlags: true,
 +              call:         true,
 +              reg: regInfo{
 +                      clobbers: 18446744071562059768, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 g F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 XER
 +              },
 +      },
 +      {
 +              name:         "CALLtail",
 +              auxType:      auxCallOff,
 +              argLen:       -1,
 +              clobberFlags: true,
 +              call:         true,
 +              tailCall:     true,
 +              reg: regInfo{
 +                      clobbers: 18446744071562059768, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 g F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 XER
 +              },
 +      },
 +      {
 +              name:         "CALLclosure",
 +              auxType:      auxCallOff,
 +              argLen:       -1,
 +              clobberFlags: true,
 +              call:         true,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 4096}, // R12
 +                              {1, 2048}, // R11
 +                      },
 +                      clobbers: 18446744071562059768, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 g F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 XER
 +              },
 +      },
 +      {
 +              name:         "CALLinter",
 +              auxType:      auxCallOff,
 +              argLen:       -1,
 +              clobberFlags: true,
 +              call:         true,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 4096}, // R12
 +                      },
 +                      clobbers: 18446744071562059768, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 g F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 XER
 +              },
 +      },
 +      {
 +              name:           "LoweredZero",
 +              auxType:        auxInt64,
 +              argLen:         2,
 +              clobberFlags:   true,
 +              faultOnNilArg0: true,
 +              unsafePoint:    true,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1048576}, // R20
 +                      },
 +                      clobbers: 1048576, // R20
 +              },
 +      },
 +      {
 +              name:           "LoweredZeroShort",
 +              auxType:        auxInt64,
 +              argLen:         2,
 +              faultOnNilArg0: true,
 +              unsafePoint:    true,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +              },
 +      },
 +      {
 +              name:           "LoweredQuadZeroShort",
 +              auxType:        auxInt64,
 +              argLen:         2,
 +              faultOnNilArg0: true,
 +              unsafePoint:    true,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +              },
 +      },
 +      {
 +              name:           "LoweredQuadZero",
 +              auxType:        auxInt64,
 +              argLen:         2,
 +              clobberFlags:   true,
 +              faultOnNilArg0: true,
 +              unsafePoint:    true,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1048576}, // R20
 +                      },
 +                      clobbers: 1048576, // R20
 +              },
 +      },
 +      {
 +              name:           "LoweredMove",
 +              auxType:        auxInt64,
 +              argLen:         3,
 +              clobberFlags:   true,
 +              faultOnNilArg0: true,
 +              faultOnNilArg1: true,
 +              unsafePoint:    true,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1048576}, // R20
 +                              {1, 2097152}, // R21
 +                      },
 +                      clobbers: 3145728, // R20 R21
 +              },
 +      },
 +      {
 +              name:           "LoweredMoveShort",
 +              auxType:        auxInt64,
 +              argLen:         3,
 +              faultOnNilArg0: true,
 +              faultOnNilArg1: true,
 +              unsafePoint:    true,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                              {1, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +              },
 +      },
 +      {
 +              name:           "LoweredQuadMove",
 +              auxType:        auxInt64,
 +              argLen:         3,
 +              clobberFlags:   true,
 +              faultOnNilArg0: true,
 +              faultOnNilArg1: true,
 +              unsafePoint:    true,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1048576}, // R20
 +                              {1, 2097152}, // R21
 +                      },
 +                      clobbers: 3145728, // R20 R21
 +              },
 +      },
 +      {
 +              name:           "LoweredQuadMoveShort",
 +              auxType:        auxInt64,
 +              argLen:         3,
 +              faultOnNilArg0: true,
 +              faultOnNilArg1: true,
 +              unsafePoint:    true,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                              {1, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +              },
 +      },
 +      {
 +              name:           "LoweredAtomicStore8",
 +              auxType:        auxInt64,
 +              argLen:         3,
 +              faultOnNilArg0: true,
 +              hasSideEffects: true,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                              {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +              },
 +      },
 +      {
 +              name:           "LoweredAtomicStore32",
 +              auxType:        auxInt64,
 +              argLen:         3,
 +              faultOnNilArg0: true,
 +              hasSideEffects: true,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                              {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +              },
 +      },
 +      {
 +              name:           "LoweredAtomicStore64",
 +              auxType:        auxInt64,
 +              argLen:         3,
 +              faultOnNilArg0: true,
 +              hasSideEffects: true,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                              {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +              },
 +      },
 +      {
 +              name:           "LoweredAtomicLoad8",
 +              auxType:        auxInt64,
 +              argLen:         2,
 +              clobberFlags:   true,
 +              faultOnNilArg0: true,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +              },
 +      },
 +      {
 +              name:           "LoweredAtomicLoad32",
 +              auxType:        auxInt64,
 +              argLen:         2,
 +              clobberFlags:   true,
 +              faultOnNilArg0: true,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +              },
 +      },
 +      {
 +              name:           "LoweredAtomicLoad64",
 +              auxType:        auxInt64,
 +              argLen:         2,
 +              clobberFlags:   true,
 +              faultOnNilArg0: true,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +              },
 +      },
 +      {
 +              name:           "LoweredAtomicLoadPtr",
 +              auxType:        auxInt64,
 +              argLen:         2,
 +              clobberFlags:   true,
 +              faultOnNilArg0: true,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +              },
 +      },
 +      {
 +              name:            "LoweredAtomicAdd32",
 +              argLen:          3,
 +              resultNotInArgs: true,
 +              clobberFlags:    true,
 +              faultOnNilArg0:  true,
 +              hasSideEffects:  true,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                              {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +              },
 +      },
 +      {
 +              name:            "LoweredAtomicAdd64",
 +              argLen:          3,
 +              resultNotInArgs: true,
 +              clobberFlags:    true,
 +              faultOnNilArg0:  true,
 +              hasSideEffects:  true,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                              {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +              },
 +      },
 +      {
 +              name:            "LoweredAtomicExchange8",
 +              argLen:          3,
 +              resultNotInArgs: true,
 +              clobberFlags:    true,
 +              faultOnNilArg0:  true,
 +              hasSideEffects:  true,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                              {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +              },
 +      },
 +      {
 +              name:            "LoweredAtomicExchange32",
 +              argLen:          3,
 +              resultNotInArgs: true,
 +              clobberFlags:    true,
 +              faultOnNilArg0:  true,
 +              hasSideEffects:  true,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                              {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +              },
 +      },
 +      {
 +              name:            "LoweredAtomicExchange64",
 +              argLen:          3,
 +              resultNotInArgs: true,
 +              clobberFlags:    true,
 +              faultOnNilArg0:  true,
 +              hasSideEffects:  true,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                              {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +              },
 +      },
 +      {
 +              name:            "LoweredAtomicCas64",
 +              auxType:         auxInt64,
 +              argLen:          4,
 +              resultNotInArgs: true,
 +              clobberFlags:    true,
 +              faultOnNilArg0:  true,
 +              hasSideEffects:  true,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                              {2, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                              {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +              },
 +      },
 +      {
 +              name:            "LoweredAtomicCas32",
 +              auxType:         auxInt64,
 +              argLen:          4,
 +              resultNotInArgs: true,
 +              clobberFlags:    true,
 +              faultOnNilArg0:  true,
 +              hasSideEffects:  true,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                              {2, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                              {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +              },
 +      },
 +      {
 +              name:           "LoweredAtomicAnd8",
 +              argLen:         3,
 +              faultOnNilArg0: true,
 +              hasSideEffects: true,
 +              asm:            ppc64.AAND,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                              {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +              },
 +      },
 +      {
 +              name:           "LoweredAtomicAnd32",
 +              argLen:         3,
 +              faultOnNilArg0: true,
 +              hasSideEffects: true,
 +              asm:            ppc64.AAND,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                              {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +              },
 +      },
 +      {
 +              name:           "LoweredAtomicOr8",
 +              argLen:         3,
 +              faultOnNilArg0: true,
 +              hasSideEffects: true,
 +              asm:            ppc64.AOR,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                              {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +              },
 +      },
 +      {
 +              name:           "LoweredAtomicOr32",
 +              argLen:         3,
 +              faultOnNilArg0: true,
 +              hasSideEffects: true,
 +              asm:            ppc64.AOR,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                              {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +              },
 +      },
 +      {
 +              name:         "LoweredWB",
 +              auxType:      auxInt64,
 +              argLen:       1,
 +              clobberFlags: true,
 +              reg: regInfo{
 +                      clobbers: 18446744072632408064, // R11 R12 R18 R19 R22 R23 R24 R25 R26 R27 R28 R29 R31 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 XER
 +                      outputs: []outputInfo{
 +                              {0, 536870912}, // R29
 +                      },
 +              },
 +      },
 +      {
 +              name:           "LoweredPubBarrier",
 +              argLen:         1,
 +              hasSideEffects: true,
 +              asm:            ppc64.ALWSYNC,
 +              reg:            regInfo{},
 +      },
 +      {
-               name:    "LoweredPanicBoundsA",
++              name:    "LoweredPanicBoundsRR",
 +              auxType: auxInt64,
 +              argLen:  3,
 +              call:    true,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
-                               {0, 32}, // R5
-                               {1, 64}, // R6
++                              {0, 1016}, // R3 R4 R5 R6 R7 R8 R9
++                              {1, 1016}, // R3 R4 R5 R6 R7 R8 R9
 +                      },
 +              },
 +      },
 +      {
-               name:    "LoweredPanicBoundsB",
-               auxType: auxInt64,
-               argLen:  3,
++              name:    "LoweredPanicBoundsRC",
++              auxType: auxPanicBoundsC,
++              argLen:  2,
 +              call:    true,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
-                               {0, 16}, // R4
-                               {1, 32}, // R5
++                              {0, 1016}, // R3 R4 R5 R6 R7 R8 R9
 +                      },
 +              },
 +      },
 +      {
-               name:    "LoweredPanicBoundsC",
-               auxType: auxInt64,
-               argLen:  3,
++              name:    "LoweredPanicBoundsCR",
++              auxType: auxPanicBoundsC,
++              argLen:  2,
 +              call:    true,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
-                               {0, 8},  // R3
-                               {1, 16}, // R4
++                              {0, 1016}, // R3 R4 R5 R6 R7 R8 R9
 +                      },
 +              },
 +      },
++      {
++              name:    "LoweredPanicBoundsCC",
++              auxType: auxPanicBoundsCC,
++              argLen:  1,
++              call:    true,
++              reg:     regInfo{},
++      },
 +      {
 +              name:   "InvertFlags",
 +              argLen: 1,
 +              reg:    regInfo{},
 +      },
 +      {
 +              name:   "FlagEQ",
 +              argLen: 0,
 +              reg:    regInfo{},
 +      },
 +      {
 +              name:   "FlagLT",
 +              argLen: 0,
 +              reg:    regInfo{},
 +      },
 +      {
 +              name:   "FlagGT",
 +              argLen: 0,
 +              reg:    regInfo{},
 +      },
 +
 +      {
 +              name:        "ADD",
 +              argLen:      2,
 +              commutative: true,
 +              asm:         riscv.AADD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                              {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                      },
 +              },
 +      },
 +      {
 +              name:    "ADDI",
 +              auxType: auxInt64,
 +              argLen:  1,
 +              asm:     riscv.AADDI,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                      },
 +              },
 +      },
 +      {
 +              name:    "ADDIW",
 +              auxType: auxInt64,
 +              argLen:  1,
 +              asm:     riscv.AADDIW,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                      },
 +              },
 +      },
 +      {
 +              name:   "NEG",
 +              argLen: 1,
 +              asm:    riscv.ANEG,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                      },
 +              },
 +      },
 +      {
 +              name:   "NEGW",
 +              argLen: 1,
 +              asm:    riscv.ANEGW,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                      },
 +              },
 +      },
 +      {
 +              name:   "SUB",
 +              argLen: 2,
 +              asm:    riscv.ASUB,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                              {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                      },
 +              },
 +      },
 +      {
 +              name:   "SUBW",
 +              argLen: 2,
 +              asm:    riscv.ASUBW,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                              {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                      },
 +              },
 +      },
 +      {
 +              name:        "MUL",
 +              argLen:      2,
 +              commutative: true,
 +              asm:         riscv.AMUL,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                              {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                      },
 +              },
 +      },
 +      {
 +              name:        "MULW",
 +              argLen:      2,
 +              commutative: true,
 +              asm:         riscv.AMULW,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                              {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                      },
 +              },
 +      },
 +      {
 +              name:        "MULH",
 +              argLen:      2,
 +              commutative: true,
 +              asm:         riscv.AMULH,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                              {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                      },
 +              },
 +      },
 +      {
 +              name:        "MULHU",
 +              argLen:      2,
 +              commutative: true,
 +              asm:         riscv.AMULHU,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                              {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                      },
 +              },
 +      },
 +      {
 +              name:            "LoweredMuluhilo",
 +              argLen:          2,
 +              resultNotInArgs: true,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                              {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                              {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                      },
 +              },
 +      },
 +      {
 +              name:            "LoweredMuluover",
 +              argLen:          2,
 +              resultNotInArgs: true,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                              {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                              {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                      },
 +              },
 +      },
 +      {
 +              name:   "DIV",
 +              argLen: 2,
 +              asm:    riscv.ADIV,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                              {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                      },
 +              },
 +      },
 +      {
 +              name:   "DIVU",
 +              argLen: 2,
 +              asm:    riscv.ADIVU,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                              {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                      },
 +              },
 +      },
 +      {
 +              name:   "DIVW",
 +              argLen: 2,
 +              asm:    riscv.ADIVW,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                              {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                      },
 +              },
 +      },
 +      {
 +              name:   "DIVUW",
 +              argLen: 2,
 +              asm:    riscv.ADIVUW,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                              {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                      },
 +              },
 +      },
 +      {
 +              name:   "REM",
 +              argLen: 2,
 +              asm:    riscv.AREM,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                              {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                      },
 +              },
 +      },
 +      {
 +              name:   "REMU",
 +              argLen: 2,
 +              asm:    riscv.AREMU,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                              {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                      },
 +              },
 +      },
 +      {
 +              name:   "REMW",
 +              argLen: 2,
 +              asm:    riscv.AREMW,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                              {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                      },
 +              },
 +      },
 +      {
 +              name:   "REMUW",
 +              argLen: 2,
 +              asm:    riscv.AREMUW,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                              {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                      },
 +              },
 +      },
 +      {
 +              name:              "MOVaddr",
 +              auxType:           auxSymOff,
 +              argLen:            1,
 +              rematerializeable: true,
 +              symEffect:         SymAddr,
 +              asm:               riscv.AMOV,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                      },
 +              },
 +      },
 +      {
 +              name:              "MOVDconst",
 +              auxType:           auxInt64,
 +              argLen:            0,
 +              rematerializeable: true,
 +              asm:               riscv.AMOV,
 +              reg: regInfo{
 +                      outputs: []outputInfo{
 +                              {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                      },
 +              },
 +      },
 +      {
 +              name:           "MOVBload",
 +              auxType:        auxSymOff,
 +              argLen:         2,
 +              faultOnNilArg0: true,
 +              symEffect:      SymRead,
 +              asm:            riscv.AMOVB,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                      },
 +              },
 +      },
 +      {
 +              name:           "MOVHload",
 +              auxType:        auxSymOff,
 +              argLen:         2,
 +              faultOnNilArg0: true,
 +              symEffect:      SymRead,
 +              asm:            riscv.AMOVH,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                      },
 +              },
 +      },
 +      {
 +              name:           "MOVWload",
 +              auxType:        auxSymOff,
 +              argLen:         2,
 +              faultOnNilArg0: true,
 +              symEffect:      SymRead,
 +              asm:            riscv.AMOVW,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                      },
 +              },
 +      },
 +      {
 +              name:           "MOVDload",
 +              auxType:        auxSymOff,
 +              argLen:         2,
 +              faultOnNilArg0: true,
 +              symEffect:      SymRead,
 +              asm:            riscv.AMOV,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                      },
 +              },
 +      },
 +      {
 +              name:           "MOVBUload",
 +              auxType:        auxSymOff,
 +              argLen:         2,
 +              faultOnNilArg0: true,
 +              symEffect:      SymRead,
 +              asm:            riscv.AMOVBU,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                      },
 +              },
 +      },
 +      {
 +              name:           "MOVHUload",
 +              auxType:        auxSymOff,
 +              argLen:         2,
 +              faultOnNilArg0: true,
 +              symEffect:      SymRead,
 +              asm:            riscv.AMOVHU,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                      },
 +              },
 +      },
 +      {
 +              name:           "MOVWUload",
 +              auxType:        auxSymOff,
 +              argLen:         2,
 +              faultOnNilArg0: true,
 +              symEffect:      SymRead,
 +              asm:            riscv.AMOVWU,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                      },
 +              },
 +      },
 +      {
 +              name:           "MOVBstore",
 +              auxType:        auxSymOff,
 +              argLen:         3,
 +              faultOnNilArg0: true,
 +              symEffect:      SymWrite,
 +              asm:            riscv.AMOVB,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 1006632946},          // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                              {0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB
 +                      },
 +              },
 +      },
 +      {
 +              name:           "MOVHstore",
 +              auxType:        auxSymOff,
 +              argLen:         3,
 +              faultOnNilArg0: true,
 +              symEffect:      SymWrite,
 +              asm:            riscv.AMOVH,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 1006632946},          // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                              {0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB
 +                      },
 +              },
 +      },
 +      {
 +              name:           "MOVWstore",
 +              auxType:        auxSymOff,
 +              argLen:         3,
 +              faultOnNilArg0: true,
 +              symEffect:      SymWrite,
 +              asm:            riscv.AMOVW,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 1006632946},          // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                              {0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB
 +                      },
 +              },
 +      },
 +      {
 +              name:           "MOVDstore",
 +              auxType:        auxSymOff,
 +              argLen:         3,
 +              faultOnNilArg0: true,
 +              symEffect:      SymWrite,
 +              asm:            riscv.AMOV,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 1006632946},          // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                              {0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB
 +                      },
 +              },
 +      },
 +      {
 +              name:           "MOVBstorezero",
 +              auxType:        auxSymOff,
 +              argLen:         2,
 +              faultOnNilArg0: true,
 +              symEffect:      SymWrite,
 +              asm:            riscv.AMOVB,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB
 +                      },
 +              },
 +      },
 +      {
 +              name:           "MOVHstorezero",
 +              auxType:        auxSymOff,
 +              argLen:         2,
 +              faultOnNilArg0: true,
 +              symEffect:      SymWrite,
 +              asm:            riscv.AMOVH,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB
 +                      },
 +              },
 +      },
 +      {
 +              name:           "MOVWstorezero",
 +              auxType:        auxSymOff,
 +              argLen:         2,
 +              faultOnNilArg0: true,
 +              symEffect:      SymWrite,
 +              asm:            riscv.AMOVW,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB
 +                      },
 +              },
 +      },
 +      {
 +              name:           "MOVDstorezero",
 +              auxType:        auxSymOff,
 +              argLen:         2,
 +              faultOnNilArg0: true,
 +              symEffect:      SymWrite,
 +              asm:            riscv.AMOV,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB
 +                      },
 +              },
 +      },
 +      {
 +              name:   "MOVBreg",
 +              argLen: 1,
 +              asm:    riscv.AMOVB,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                      },
 +              },
 +      },
 +      {
 +              name:   "MOVHreg",
 +              argLen: 1,
 +              asm:    riscv.AMOVH,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                      },
 +              },
 +      },
 +      {
 +              name:   "MOVWreg",
 +              argLen: 1,
 +              asm:    riscv.AMOVW,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                      },
 +              },
 +      },
 +      {
 +              name:   "MOVDreg",
 +              argLen: 1,
 +              asm:    riscv.AMOV,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                      },
 +              },
 +      },
 +      {
 +              name:   "MOVBUreg",
 +              argLen: 1,
 +              asm:    riscv.AMOVBU,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                      },
 +              },
 +      },
 +      {
 +              name:   "MOVHUreg",
 +              argLen: 1,
 +              asm:    riscv.AMOVHU,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                      },
 +              },
 +      },
 +      {
 +              name:   "MOVWUreg",
 +              argLen: 1,
 +              asm:    riscv.AMOVWU,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                      },
 +              },
 +      },
 +      {
 +              name:         "MOVDnop",
 +              argLen:       1,
 +              resultInArg0: true,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                      },
 +              },
 +      },
 +      {
 +              name:   "SLL",
 +              argLen: 2,
 +              asm:    riscv.ASLL,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                              {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                      },
 +              },
 +      },
 +      {
 +              name:   "SLLW",
 +              argLen: 2,
 +              asm:    riscv.ASLLW,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                              {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                      },
 +              },
 +      },
 +      {
 +              name:   "SRA",
 +              argLen: 2,
 +              asm:    riscv.ASRA,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                              {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                      },
 +              },
 +      },
 +      {
 +              name:   "SRAW",
 +              argLen: 2,
 +              asm:    riscv.ASRAW,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                              {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                      },
 +              },
 +      },
 +      {
 +              name:   "SRL",
 +              argLen: 2,
 +              asm:    riscv.ASRL,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                              {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                      },
 +              },
 +      },
 +      {
 +              name:   "SRLW",
 +              argLen: 2,
 +              asm:    riscv.ASRLW,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                              {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                      },
 +              },
 +      },
 +      {
 +              name:    "SLLI",
 +              auxType: auxInt64,
 +              argLen:  1,
 +              asm:     riscv.ASLLI,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                      },
 +              },
 +      },
 +      {
 +              name:    "SLLIW",
 +              auxType: auxInt64,
 +              argLen:  1,
 +              asm:     riscv.ASLLIW,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                      },
 +              },
 +      },
 +      {
 +              name:    "SRAI",
 +              auxType: auxInt64,
 +              argLen:  1,
 +              asm:     riscv.ASRAI,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                      },
 +              },
 +      },
 +      {
 +              name:    "SRAIW",
 +              auxType: auxInt64,
 +              argLen:  1,
 +              asm:     riscv.ASRAIW,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                      },
 +              },
 +      },
 +      {
 +              name:    "SRLI",
 +              auxType: auxInt64,
 +              argLen:  1,
 +              asm:     riscv.ASRLI,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                      },
 +              },
 +      },
 +      {
 +              name:    "SRLIW",
 +              auxType: auxInt64,
 +              argLen:  1,
 +              asm:     riscv.ASRLIW,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                      },
 +              },
 +      },
 +      {
 +              name:   "SH1ADD",
 +              argLen: 2,
 +              asm:    riscv.ASH1ADD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                              {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                      },
 +              },
 +      },
 +      {
 +              name:   "SH2ADD",
 +              argLen: 2,
 +              asm:    riscv.ASH2ADD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                              {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                      },
 +              },
 +      },
 +      {
 +              name:   "SH3ADD",
 +              argLen: 2,
 +              asm:    riscv.ASH3ADD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                              {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                      },
 +              },
 +      },
 +      {
 +              name:        "AND",
 +              argLen:      2,
 +              commutative: true,
 +              asm:         riscv.AAND,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                              {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                      },
 +              },
 +      },
 +      {
 +              name:   "ANDN",
 +              argLen: 2,
 +              asm:    riscv.AANDN,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                              {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                      },
 +              },
 +      },
 +      {
 +              name:    "ANDI",
 +              auxType: auxInt64,
 +              argLen:  1,
 +              asm:     riscv.AANDI,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                      },
 +              },
 +      },
 +      {
 +              name:   "CLZ",
 +              argLen: 1,
 +              asm:    riscv.ACLZ,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                      },
 +              },
 +      },
 +      {
 +              name:   "CLZW",
 +              argLen: 1,
 +              asm:    riscv.ACLZW,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                      },
 +              },
 +      },
 +      {
 +              name:   "CPOP",
 +              argLen: 1,
 +              asm:    riscv.ACPOP,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                      },
 +              },
 +      },
 +      {
 +              name:   "CPOPW",
 +              argLen: 1,
 +              asm:    riscv.ACPOPW,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                      },
 +              },
 +      },
 +      {
 +              name:   "CTZ",
 +              argLen: 1,
 +              asm:    riscv.ACTZ,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                      },
 +              },
 +      },
 +      {
 +              name:   "CTZW",
 +              argLen: 1,
 +              asm:    riscv.ACTZW,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                      },
 +              },
 +      },
 +      {
 +              name:   "NOT",
 +              argLen: 1,
 +              asm:    riscv.ANOT,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                      },
 +              },
 +      },
 +      {
 +              name:        "OR",
 +              argLen:      2,
 +              commutative: true,
 +              asm:         riscv.AOR,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                              {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                      },
 +              },
 +      },
 +      {
 +              name:   "ORN",
 +              argLen: 2,
 +              asm:    riscv.AORN,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                              {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                      },
 +              },
 +      },
 +      {
 +              name:    "ORI",
 +              auxType: auxInt64,
 +              argLen:  1,
 +              asm:     riscv.AORI,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                      },
 +              },
 +      },
 +      {
 +              name:   "REV8",
 +              argLen: 1,
 +              asm:    riscv.AREV8,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                      },
 +              },
 +      },
 +      {
 +              name:   "ROL",
 +              argLen: 2,
 +              asm:    riscv.AROL,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                              {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                      },
 +              },
 +      },
 +      {
 +              name:   "ROLW",
 +              argLen: 2,
 +              asm:    riscv.AROLW,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                              {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                      },
 +              },
 +      },
 +      {
 +              name:   "ROR",
 +              argLen: 2,
 +              asm:    riscv.AROR,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                              {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                      },
 +              },
 +      },
 +      {
 +              name:    "RORI",
 +              auxType: auxInt64,
 +              argLen:  1,
 +              asm:     riscv.ARORI,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                      },
 +              },
 +      },
 +      {
 +              name:    "RORIW",
 +              auxType: auxInt64,
 +              argLen:  1,
 +              asm:     riscv.ARORIW,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                      },
 +              },
 +      },
 +      {
 +              name:   "RORW",
 +              argLen: 2,
 +              asm:    riscv.ARORW,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                              {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                      },
 +              },
 +      },
 +      {
 +              name:        "XNOR",
 +              argLen:      2,
 +              commutative: true,
 +              asm:         riscv.AXNOR,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                              {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                      },
 +              },
 +      },
 +      {
 +              name:        "XOR",
 +              argLen:      2,
 +              commutative: true,
 +              asm:         riscv.AXOR,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                              {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                      },
 +              },
 +      },
 +      {
 +              name:    "XORI",
 +              auxType: auxInt64,
 +              argLen:  1,
 +              asm:     riscv.AXORI,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                      },
 +              },
 +      },
 +      {
 +              name:        "MIN",
 +              argLen:      2,
 +              commutative: true,
 +              asm:         riscv.AMIN,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                              {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                      },
 +              },
 +      },
 +      {
 +              name:        "MAX",
 +              argLen:      2,
 +              commutative: true,
 +              asm:         riscv.AMAX,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                              {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                      },
 +              },
 +      },
 +      {
 +              name:        "MINU",
 +              argLen:      2,
 +              commutative: true,
 +              asm:         riscv.AMINU,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                              {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                      },
 +              },
 +      },
 +      {
 +              name:        "MAXU",
 +              argLen:      2,
 +              commutative: true,
 +              asm:         riscv.AMAXU,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                              {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                      },
 +              },
 +      },
 +      {
 +              name:   "SEQZ",
 +              argLen: 1,
 +              asm:    riscv.ASEQZ,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                      },
 +              },
 +      },
 +      {
 +              name:   "SNEZ",
 +              argLen: 1,
 +              asm:    riscv.ASNEZ,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                      },
 +              },
 +      },
 +      {
 +              name:   "SLT",
 +              argLen: 2,
 +              asm:    riscv.ASLT,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                              {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                      },
 +              },
 +      },
 +      {
 +              name:    "SLTI",
 +              auxType: auxInt64,
 +              argLen:  1,
 +              asm:     riscv.ASLTI,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                      },
 +              },
 +      },
 +      {
 +              name:   "SLTU",
 +              argLen: 2,
 +              asm:    riscv.ASLTU,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                              {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                      },
 +              },
 +      },
 +      {
 +              name:    "SLTIU",
 +              auxType: auxInt64,
 +              argLen:  1,
 +              asm:     riscv.ASLTIU,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                      },
 +              },
 +      },
 +      {
 +              name:         "LoweredRound32F",
 +              argLen:       1,
 +              resultInArg0: true,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "LoweredRound64F",
 +              argLen:       1,
 +              resultInArg0: true,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +              },
 +      },
 +      {
 +              name:    "CALLstatic",
 +              auxType: auxCallOff,
 +              argLen:  -1,
 +              call:    true,
 +              reg: regInfo{
 +                      clobbers: 9223372035781033968, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +              },
 +      },
 +      {
 +              name:     "CALLtail",
 +              auxType:  auxCallOff,
 +              argLen:   -1,
 +              call:     true,
 +              tailCall: true,
 +              reg: regInfo{
 +                      clobbers: 9223372035781033968, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +              },
 +      },
 +      {
 +              name:    "CALLclosure",
 +              auxType: auxCallOff,
 +              argLen:  -1,
 +              call:    true,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 33554432},   // X26
 +                              {0, 1006632946}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                      },
 +                      clobbers: 9223372035781033968, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +              },
 +      },
 +      {
 +              name:    "CALLinter",
 +              auxType: auxCallOff,
 +              argLen:  -1,
 +              call:    true,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                      },
 +                      clobbers: 9223372035781033968, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +              },
 +      },
 +      {
 +              name:           "DUFFZERO",
 +              auxType:        auxInt64,
 +              argLen:         2,
 +              faultOnNilArg0: true,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 16777216}, // X25
 +                      },
 +                      clobbers: 16777216, // X25
 +              },
 +      },
 +      {
 +              name:           "DUFFCOPY",
 +              auxType:        auxInt64,
 +              argLen:         3,
 +              faultOnNilArg0: true,
 +              faultOnNilArg1: true,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 16777216}, // X25
 +                              {1, 8388608},  // X24
 +                      },
 +                      clobbers: 25165824, // X24 X25
 +              },
 +      },
 +      {
 +              name:           "LoweredZero",
 +              auxType:        auxInt64,
 +              argLen:         3,
 +              faultOnNilArg0: true,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 16},         // X5
 +                              {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                      },
 +                      clobbers: 16, // X5
 +              },
 +      },
 +      {
 +              name:           "LoweredMove",
 +              auxType:        auxInt64,
 +              argLen:         4,
 +              faultOnNilArg0: true,
 +              faultOnNilArg1: true,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 16},         // X5
 +                              {1, 32},         // X6
 +                              {2, 1006632880}, // X5 X6 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                      },
 +                      clobbers: 112, // X5 X6 X7
 +              },
 +      },
 +      {
 +              name:           "LoweredAtomicLoad8",
 +              argLen:         2,
 +              faultOnNilArg0: true,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                      },
 +              },
 +      },
 +      {
 +              name:           "LoweredAtomicLoad32",
 +              argLen:         2,
 +              faultOnNilArg0: true,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                      },
 +              },
 +      },
 +      {
 +              name:           "LoweredAtomicLoad64",
 +              argLen:         2,
 +              faultOnNilArg0: true,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                      },
 +              },
 +      },
 +      {
 +              name:           "LoweredAtomicStore8",
 +              argLen:         3,
 +              faultOnNilArg0: true,
 +              hasSideEffects: true,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 1006632946},          // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                              {0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB
 +                      },
 +              },
 +      },
 +      {
 +              name:           "LoweredAtomicStore32",
 +              argLen:         3,
 +              faultOnNilArg0: true,
 +              hasSideEffects: true,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 1006632946},          // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                              {0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB
 +                      },
 +              },
 +      },
 +      {
 +              name:           "LoweredAtomicStore64",
 +              argLen:         3,
 +              faultOnNilArg0: true,
 +              hasSideEffects: true,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 1006632946},          // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                              {0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB
 +                      },
 +              },
 +      },
 +      {
 +              name:            "LoweredAtomicExchange32",
 +              argLen:          3,
 +              resultNotInArgs: true,
 +              faultOnNilArg0:  true,
 +              hasSideEffects:  true,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 1073741808},          // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30
 +                              {0, 9223372037928517618}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30 SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                      },
 +              },
 +      },
 +      {
 +              name:            "LoweredAtomicExchange64",
 +              argLen:          3,
 +              resultNotInArgs: true,
 +              faultOnNilArg0:  true,
 +              hasSideEffects:  true,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 1073741808},          // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30
 +                              {0, 9223372037928517618}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30 SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                      },
 +              },
 +      },
 +      {
 +              name:            "LoweredAtomicAdd32",
 +              argLen:          3,
 +              resultNotInArgs: true,
 +              faultOnNilArg0:  true,
 +              hasSideEffects:  true,
 +              unsafePoint:     true,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 1073741808},          // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30
 +                              {0, 9223372037928517618}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30 SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                      },
 +              },
 +      },
 +      {
 +              name:            "LoweredAtomicAdd64",
 +              argLen:          3,
 +              resultNotInArgs: true,
 +              faultOnNilArg0:  true,
 +              hasSideEffects:  true,
 +              unsafePoint:     true,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 1073741808},          // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30
 +                              {0, 9223372037928517618}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30 SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                      },
 +              },
 +      },
 +      {
 +              name:            "LoweredAtomicCas32",
 +              argLen:          4,
 +              resultNotInArgs: true,
 +              faultOnNilArg0:  true,
 +              hasSideEffects:  true,
 +              unsafePoint:     true,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 1073741808},          // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30
 +                              {2, 1073741808},          // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30
 +                              {0, 9223372037928517618}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30 SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                      },
 +              },
 +      },
 +      {
 +              name:            "LoweredAtomicCas64",
 +              argLen:          4,
 +              resultNotInArgs: true,
 +              faultOnNilArg0:  true,
 +              hasSideEffects:  true,
 +              unsafePoint:     true,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 1073741808},          // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30
 +                              {2, 1073741808},          // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30
 +                              {0, 9223372037928517618}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30 SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                      },
 +              },
 +      },
 +      {
 +              name:           "LoweredAtomicAnd32",
 +              argLen:         3,
 +              faultOnNilArg0: true,
 +              hasSideEffects: true,
 +              asm:            riscv.AAMOANDW,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 1073741808},          // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30
 +                              {0, 9223372037928517618}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30 SB
 +                      },
 +              },
 +      },
 +      {
 +              name:           "LoweredAtomicOr32",
 +              argLen:         3,
 +              faultOnNilArg0: true,
 +              hasSideEffects: true,
 +              asm:            riscv.AAMOORW,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 1073741808},          // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30
 +                              {0, 9223372037928517618}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30 SB
 +                      },
 +              },
 +      },
 +      {
 +              name:           "LoweredNilCheck",
 +              argLen:         2,
 +              nilCheck:       true,
 +              faultOnNilArg0: true,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1006632946}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                      },
 +              },
 +      },
 +      {
 +              name:   "LoweredGetClosurePtr",
 +              argLen: 0,
 +              reg: regInfo{
 +                      outputs: []outputInfo{
 +                              {0, 33554432}, // X26
 +                      },
 +              },
 +      },
 +      {
 +              name:              "LoweredGetCallerSP",
 +              argLen:            1,
 +              rematerializeable: true,
 +              reg: regInfo{
 +                      outputs: []outputInfo{
 +                              {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                      },
 +              },
 +      },
 +      {
 +              name:              "LoweredGetCallerPC",
 +              argLen:            0,
 +              rematerializeable: true,
 +              reg: regInfo{
 +                      outputs: []outputInfo{
 +                              {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                      },
 +              },
 +      },
 +      {
 +              name:         "LoweredWB",
 +              auxType:      auxInt64,
 +              argLen:       1,
 +              clobberFlags: true,
 +              reg: regInfo{
 +                      clobbers: 9223372034707292160, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      outputs: []outputInfo{
 +                              {0, 8388608}, // X24
 +                      },
 +              },
 +      },
 +      {
 +              name:           "LoweredPubBarrier",
 +              argLen:         1,
 +              hasSideEffects: true,
 +              asm:            riscv.AFENCE,
 +              reg:            regInfo{},
 +      },
 +      {
 +              name:    "LoweredPanicBoundsRR",
 +              auxType: auxInt64,
 +              argLen:  3,
 +              call:    true,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1048560}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20
 +                              {1, 1048560}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20
 +                      },
 +              },
 +      },
 +      {
 +              name:    "LoweredPanicBoundsRC",
 +              auxType: auxPanicBoundsC,
 +              argLen:  2,
 +              call:    true,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1048560}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20
 +                      },
 +              },
 +      },
 +      {
 +              name:    "LoweredPanicBoundsCR",
 +              auxType: auxPanicBoundsC,
 +              argLen:  2,
 +              call:    true,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1048560}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20
 +                      },
 +              },
 +      },
 +      {
 +              name:    "LoweredPanicBoundsCC",
 +              auxType: auxPanicBoundsCC,
 +              argLen:  1,
 +              call:    true,
 +              reg:     regInfo{},
 +      },
 +      {
 +              name:        "FADDS",
 +              argLen:      2,
 +              commutative: true,
 +              asm:         riscv.AFADDS,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                              {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +              },
 +      },
 +      {
 +              name:   "FSUBS",
 +              argLen: 2,
 +              asm:    riscv.AFSUBS,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                              {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +              },
 +      },
 +      {
 +              name:        "FMULS",
 +              argLen:      2,
 +              commutative: true,
 +              asm:         riscv.AFMULS,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                              {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +              },
 +      },
 +      {
 +              name:   "FDIVS",
 +              argLen: 2,
 +              asm:    riscv.AFDIVS,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                              {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +              },
 +      },
 +      {
 +              name:        "FMADDS",
 +              argLen:      3,
 +              commutative: true,
 +              asm:         riscv.AFMADDS,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                              {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                              {2, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +              },
 +      },
 +      {
 +              name:        "FMSUBS",
 +              argLen:      3,
 +              commutative: true,
 +              asm:         riscv.AFMSUBS,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                              {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                              {2, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +              },
 +      },
 +      {
 +              name:        "FNMADDS",
 +              argLen:      3,
 +              commutative: true,
 +              asm:         riscv.AFNMADDS,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                              {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                              {2, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +              },
 +      },
 +      {
 +              name:        "FNMSUBS",
 +              argLen:      3,
 +              commutative: true,
 +              asm:         riscv.AFNMSUBS,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                              {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                              {2, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +              },
 +      },
 +      {
 +              name:   "FSQRTS",
 +              argLen: 1,
 +              asm:    riscv.AFSQRTS,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +              },
 +      },
 +      {
 +              name:   "FNEGS",
 +              argLen: 1,
 +              asm:    riscv.AFNEGS,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +              },
 +      },
 +      {
 +              name:   "FMVSX",
 +              argLen: 1,
 +              asm:    riscv.AFMVSX,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +              },
 +      },
++      {
++              name:   "FMVXS",
++              argLen: 1,
++              asm:    riscv.AFMVXS,
++              reg: regInfo{
++                      inputs: []inputInfo{
++                              {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
++                      },
++                      outputs: []outputInfo{
++                              {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
++                      },
++              },
++      },
 +      {
 +              name:   "FCVTSW",
 +              argLen: 1,
 +              asm:    riscv.AFCVTSW,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +              },
 +      },
 +      {
 +              name:   "FCVTSL",
 +              argLen: 1,
 +              asm:    riscv.AFCVTSL,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +              },
 +      },
 +      {
 +              name:   "FCVTWS",
 +              argLen: 1,
 +              asm:    riscv.AFCVTWS,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                      },
 +              },
 +      },
 +      {
 +              name:   "FCVTLS",
 +              argLen: 1,
 +              asm:    riscv.AFCVTLS,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                      },
 +              },
 +      },
 +      {
 +              name:           "FMOVWload",
 +              auxType:        auxSymOff,
 +              argLen:         2,
 +              faultOnNilArg0: true,
 +              symEffect:      SymRead,
 +              asm:            riscv.AMOVF,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +              },
 +      },
 +      {
 +              name:           "FMOVWstore",
 +              auxType:        auxSymOff,
 +              argLen:         3,
 +              faultOnNilArg0: true,
 +              symEffect:      SymWrite,
 +              asm:            riscv.AMOVF,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB
 +                              {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +              },
 +      },
 +      {
 +              name:        "FEQS",
 +              argLen:      2,
 +              commutative: true,
 +              asm:         riscv.AFEQS,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                              {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                      },
 +              },
 +      },
 +      {
 +              name:        "FNES",
 +              argLen:      2,
 +              commutative: true,
 +              asm:         riscv.AFNES,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                              {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                      },
 +              },
 +      },
 +      {
 +              name:   "FLTS",
 +              argLen: 2,
 +              asm:    riscv.AFLTS,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                              {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                      },
 +              },
 +      },
 +      {
 +              name:   "FLES",
 +              argLen: 2,
 +              asm:    riscv.AFLES,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                              {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                      },
 +              },
 +      },
 +      {
 +              name:            "LoweredFMAXS",
 +              argLen:          2,
 +              commutative:     true,
 +              resultNotInArgs: true,
 +              asm:             riscv.AFMAXS,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                              {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +              },
 +      },
 +      {
 +              name:            "LoweredFMINS",
 +              argLen:          2,
 +              commutative:     true,
 +              resultNotInArgs: true,
 +              asm:             riscv.AFMINS,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                              {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +              },
 +      },
 +      {
 +              name:        "FADDD",
 +              argLen:      2,
 +              commutative: true,
 +              asm:         riscv.AFADDD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                              {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +              },
 +      },
 +      {
 +              name:   "FSUBD",
 +              argLen: 2,
 +              asm:    riscv.AFSUBD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                              {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +              },
 +      },
 +      {
 +              name:        "FMULD",
 +              argLen:      2,
 +              commutative: true,
 +              asm:         riscv.AFMULD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                              {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +              },
 +      },
 +      {
 +              name:   "FDIVD",
 +              argLen: 2,
 +              asm:    riscv.AFDIVD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                              {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +              },
 +      },
 +      {
 +              name:        "FMADDD",
 +              argLen:      3,
 +              commutative: true,
 +              asm:         riscv.AFMADDD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                              {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                              {2, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +              },
 +      },
 +      {
 +              name:        "FMSUBD",
 +              argLen:      3,
 +              commutative: true,
 +              asm:         riscv.AFMSUBD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                              {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                              {2, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +              },
 +      },
 +      {
 +              name:        "FNMADDD",
 +              argLen:      3,
 +              commutative: true,
 +              asm:         riscv.AFNMADDD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                              {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                              {2, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +              },
 +      },
 +      {
 +              name:        "FNMSUBD",
 +              argLen:      3,
 +              commutative: true,
 +              asm:         riscv.AFNMSUBD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                              {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                              {2, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +              },
 +      },
 +      {
 +              name:   "FSQRTD",
 +              argLen: 1,
 +              asm:    riscv.AFSQRTD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +              },
 +      },
 +      {
 +              name:   "FNEGD",
 +              argLen: 1,
 +              asm:    riscv.AFNEGD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +              },
 +      },
 +      {
 +              name:   "FABSD",
 +              argLen: 1,
 +              asm:    riscv.AFABSD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +              },
 +      },
 +      {
 +              name:   "FSGNJD",
 +              argLen: 2,
 +              asm:    riscv.AFSGNJD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                              {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +              },
 +      },
 +      {
 +              name:   "FMVDX",
 +              argLen: 1,
 +              asm:    riscv.AFMVDX,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +              },
 +      },
++      {
++              name:   "FMVXD",
++              argLen: 1,
++              asm:    riscv.AFMVXD,
++              reg: regInfo{
++                      inputs: []inputInfo{
++                              {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
++                      },
++                      outputs: []outputInfo{
++                              {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
++                      },
++              },
++      },
 +      {
 +              name:   "FCVTDW",
 +              argLen: 1,
 +              asm:    riscv.AFCVTDW,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +              },
 +      },
 +      {
 +              name:   "FCVTDL",
 +              argLen: 1,
 +              asm:    riscv.AFCVTDL,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +              },
 +      },
 +      {
 +              name:   "FCVTWD",
 +              argLen: 1,
 +              asm:    riscv.AFCVTWD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                      },
 +              },
 +      },
 +      {
 +              name:   "FCVTLD",
 +              argLen: 1,
 +              asm:    riscv.AFCVTLD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                      },
 +              },
 +      },
 +      {
 +              name:   "FCVTDS",
 +              argLen: 1,
 +              asm:    riscv.AFCVTDS,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +              },
 +      },
 +      {
 +              name:   "FCVTSD",
 +              argLen: 1,
 +              asm:    riscv.AFCVTSD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +              },
 +      },
 +      {
 +              name:           "FMOVDload",
 +              auxType:        auxSymOff,
 +              argLen:         2,
 +              faultOnNilArg0: true,
 +              symEffect:      SymRead,
 +              asm:            riscv.AMOVD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +              },
 +      },
 +      {
 +              name:           "FMOVDstore",
 +              auxType:        auxSymOff,
 +              argLen:         3,
 +              faultOnNilArg0: true,
 +              symEffect:      SymWrite,
 +              asm:            riscv.AMOVD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB
 +                              {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +              },
 +      },
 +      {
 +              name:        "FEQD",
 +              argLen:      2,
 +              commutative: true,
 +              asm:         riscv.AFEQD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                              {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                      },
 +              },
 +      },
 +      {
 +              name:        "FNED",
 +              argLen:      2,
 +              commutative: true,
 +              asm:         riscv.AFNED,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                              {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                      },
 +              },
 +      },
 +      {
 +              name:   "FLTD",
 +              argLen: 2,
 +              asm:    riscv.AFLTD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                              {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                      },
 +              },
 +      },
 +      {
 +              name:   "FLED",
 +              argLen: 2,
 +              asm:    riscv.AFLED,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                              {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                      },
 +              },
 +      },
 +      {
 +              name:            "LoweredFMIND",
 +              argLen:          2,
 +              commutative:     true,
 +              resultNotInArgs: true,
 +              asm:             riscv.AFMIND,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                              {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +              },
 +      },
 +      {
 +              name:            "LoweredFMAXD",
 +              argLen:          2,
 +              commutative:     true,
 +              resultNotInArgs: true,
 +              asm:             riscv.AFMAXD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                              {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +              },
 +      },
++      {
++              name:   "FCLASSS",
++              argLen: 1,
++              asm:    riscv.AFCLASSS,
++              reg: regInfo{
++                      inputs: []inputInfo{
++                              {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
++                      },
++                      outputs: []outputInfo{
++                              {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
++                      },
++              },
++      },
++      {
++              name:   "FCLASSD",
++              argLen: 1,
++              asm:    riscv.AFCLASSD,
++              reg: regInfo{
++                      inputs: []inputInfo{
++                              {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
++                      },
++                      outputs: []outputInfo{
++                              {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
++                      },
++              },
++      },
 +
 +      {
 +              name:         "FADDS",
 +              argLen:       2,
 +              commutative:  true,
 +              resultInArg0: true,
 +              asm:          s390x.AFADDS,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 +                              {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 +                      },
 +              },
 +      },
 +      {
 +              name:         "FADD",
 +              argLen:       2,
 +              commutative:  true,
 +              resultInArg0: true,
 +              asm:          s390x.AFADD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 +                              {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 +                      },
 +              },
 +      },
 +      {
 +              name:         "FSUBS",
 +              argLen:       2,
 +              resultInArg0: true,
 +              asm:          s390x.AFSUBS,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 +                              {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 +                      },
 +              },
 +      },
 +      {
 +              name:         "FSUB",
 +              argLen:       2,
 +              resultInArg0: true,
 +              asm:          s390x.AFSUB,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 +                              {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 +                      },
 +              },
 +      },
 +      {
 +              name:         "FMULS",
 +              argLen:       2,
 +              commutative:  true,
 +              resultInArg0: true,
 +              asm:          s390x.AFMULS,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 +                              {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 +                      },
 +              },
 +      },
 +      {
 +              name:         "FMUL",
 +              argLen:       2,
 +              commutative:  true,
 +              resultInArg0: true,
 +              asm:          s390x.AFMUL,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 +                              {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 +                      },
 +              },
 +      },
 +      {
 +              name:         "FDIVS",
 +              argLen:       2,
 +              resultInArg0: true,
 +              asm:          s390x.AFDIVS,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 +                              {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 +                      },
 +              },
 +      },
 +      {
 +              name:         "FDIV",
 +              argLen:       2,
 +              resultInArg0: true,
 +              asm:          s390x.AFDIV,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 +                              {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 +                      },
 +              },
 +      },
 +      {
 +              name:         "FNEGS",
 +              argLen:       1,
 +              clobberFlags: true,
 +              asm:          s390x.AFNEGS,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 +                      },
 +              },
 +      },
 +      {
 +              name:         "FNEG",
 +              argLen:       1,
 +              clobberFlags: true,
 +              asm:          s390x.AFNEG,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 +                      },
 +              },
 +      },
 +      {
 +              name:         "FMADDS",
 +              argLen:       3,
 +              resultInArg0: true,
 +              asm:          s390x.AFMADDS,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 +                              {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 +                              {2, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 +                      },
 +              },
 +      },
 +      {
 +              name:         "FMADD",
 +              argLen:       3,
 +              resultInArg0: true,
 +              asm:          s390x.AFMADD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 +                              {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 +                              {2, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 +                      },
 +              },
 +      },
 +      {
 +              name:         "FMSUBS",
 +              argLen:       3,
 +              resultInArg0: true,
 +              asm:          s390x.AFMSUBS,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 +                              {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 +                              {2, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 +                      },
 +              },
 +      },
 +      {
 +              name:         "FMSUB",
 +              argLen:       3,
 +              resultInArg0: true,
 +              asm:          s390x.AFMSUB,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 +                              {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 +                              {2, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 +                      },
 +              },
 +      },
 +      {
 +              name:   "LPDFR",
 +              argLen: 1,
 +              asm:    s390x.ALPDFR,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 +                      },
 +              },
 +      },
 +      {
 +              name:   "LNDFR",
 +              argLen: 1,
 +              asm:    s390x.ALNDFR,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 +                      },
 +              },
 +      },
 +      {
 +              name:   "CPSDR",
 +              argLen: 2,
 +              asm:    s390x.ACPSDR,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 +                              {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 +                      },
 +              },
 +      },
 +      {
 +              name:   "WFMAXDB",
 +              argLen: 2,
 +              asm:    s390x.AWFMAXDB,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 +                              {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 +                      },
 +              },
 +      },
 +      {
 +              name:   "WFMAXSB",
 +              argLen: 2,
 +              asm:    s390x.AWFMAXSB,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 +                              {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 +                      },
 +              },
 +      },
 +      {
 +              name:   "WFMINDB",
 +              argLen: 2,
 +              asm:    s390x.AWFMINDB,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 +                              {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 +                      },
 +              },
 +      },
 +      {
 +              name:   "WFMINSB",
 +              argLen: 2,
 +              asm:    s390x.AWFMINSB,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 +                              {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 +                      },
 +              },
 +      },
 +      {
 +              name:    "FIDBR",
 +              auxType: auxInt8,
 +              argLen:  1,
 +              asm:     s390x.AFIDBR,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 +                      },
 +              },
 +      },
 +      {
 +              name:           "FMOVSload",
 +              auxType:        auxSymOff,
 +              argLen:         2,
 +              faultOnNilArg0: true,
 +              symEffect:      SymRead,
 +              asm:            s390x.AFMOVS,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 +                      },
 +              },
 +      },
 +      {
 +              name:           "FMOVDload",
 +              auxType:        auxSymOff,
 +              argLen:         2,
 +              faultOnNilArg0: true,
 +              symEffect:      SymRead,
 +              asm:            s390x.AFMOVD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 +                      },
 +              },
 +      },
 +      {
 +              name:              "FMOVSconst",
 +              auxType:           auxFloat32,
 +              argLen:            0,
 +              rematerializeable: true,
 +              asm:               s390x.AFMOVS,
 +              reg: regInfo{
 +                      outputs: []outputInfo{
 +                              {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 +                      },
 +              },
 +      },
 +      {
 +              name:              "FMOVDconst",
 +              auxType:           auxFloat64,
 +              argLen:            0,
 +              rematerializeable: true,
 +              asm:               s390x.AFMOVD,
 +              reg: regInfo{
 +                      outputs: []outputInfo{
 +                              {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 +                      },
 +              },
 +      },
 +      {
 +              name:      "FMOVSloadidx",
 +              auxType:   auxSymOff,
 +              argLen:    3,
 +              symEffect: SymRead,
 +              asm:       s390x.AFMOVS,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
 +                              {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 +                      },
 +              },
 +      },
 +      {
 +              name:      "FMOVDloadidx",
 +              auxType:   auxSymOff,
 +              argLen:    3,
 +              symEffect: SymRead,
 +              asm:       s390x.AFMOVD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
 +                              {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 +                      },
 +              },
 +      },
 +      {
 +              name:           "FMOVSstore",
 +              auxType:        auxSymOff,
 +              argLen:         3,
 +              faultOnNilArg0: true,
 +              symEffect:      SymWrite,
 +              asm:            s390x.AFMOVS,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB
 +                              {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 +                      },
 +              },
 +      },
 +      {
 +              name:           "FMOVDstore",
 +              auxType:        auxSymOff,
 +              argLen:         3,
 +              faultOnNilArg0: true,
 +              symEffect:      SymWrite,
 +              asm:            s390x.AFMOVD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB
 +                              {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 +                      },
 +              },
 +      },
 +      {
 +              name:      "FMOVSstoreidx",
 +              auxType:   auxSymOff,
 +              argLen:    4,
 +              symEffect: SymWrite,
 +              asm:       s390x.AFMOVS,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 56318},      // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
 +                              {1, 56318},      // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
 +                              {2, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 +                      },
 +              },
 +      },
 +      {
 +              name:      "FMOVDstoreidx",
 +              auxType:   auxSymOff,
 +              argLen:    4,
 +              symEffect: SymWrite,
 +              asm:       s390x.AFMOVD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 56318},      // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
 +                              {1, 56318},      // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
 +                              {2, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 +                      },
 +              },
 +      },
 +      {
 +              name:         "ADD",
 +              argLen:       2,
 +              commutative:  true,
 +              clobberFlags: true,
 +              asm:          s390x.AADD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                              {0, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:         "ADDW",
 +              argLen:       2,
 +              commutative:  true,
 +              clobberFlags: true,
 +              asm:          s390x.AADDW,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                              {0, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:         "ADDconst",
 +              auxType:      auxInt32,
 +              argLen:       1,
 +              clobberFlags: true,
 +              asm:          s390x.AADD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:         "ADDWconst",
 +              auxType:      auxInt32,
 +              argLen:       1,
 +              clobberFlags: true,
 +              asm:          s390x.AADDW,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:           "ADDload",
 +              auxType:        auxSymOff,
 +              argLen:         3,
 +              resultInArg0:   true,
 +              clobberFlags:   true,
 +              faultOnNilArg1: true,
 +              symEffect:      SymRead,
 +              asm:            s390x.AADD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                              {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:           "ADDWload",
 +              auxType:        auxSymOff,
 +              argLen:         3,
 +              resultInArg0:   true,
 +              clobberFlags:   true,
 +              faultOnNilArg1: true,
 +              symEffect:      SymRead,
 +              asm:            s390x.AADDW,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                              {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:         "SUB",
 +              argLen:       2,
 +              clobberFlags: true,
 +              asm:          s390x.ASUB,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                              {1, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:         "SUBW",
 +              argLen:       2,
 +              clobberFlags: true,
 +              asm:          s390x.ASUBW,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                              {1, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:         "SUBconst",
 +              auxType:      auxInt32,
 +              argLen:       1,
 +              resultInArg0: true,
 +              clobberFlags: true,
 +              asm:          s390x.ASUB,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:         "SUBWconst",
 +              auxType:      auxInt32,
 +              argLen:       1,
 +              resultInArg0: true,
 +              clobberFlags: true,
 +              asm:          s390x.ASUBW,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:           "SUBload",
 +              auxType:        auxSymOff,
 +              argLen:         3,
 +              resultInArg0:   true,
 +              clobberFlags:   true,
 +              faultOnNilArg1: true,
 +              symEffect:      SymRead,
 +              asm:            s390x.ASUB,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                              {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:           "SUBWload",
 +              auxType:        auxSymOff,
 +              argLen:         3,
 +              resultInArg0:   true,
 +              clobberFlags:   true,
 +              faultOnNilArg1: true,
 +              symEffect:      SymRead,
 +              asm:            s390x.ASUBW,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                              {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:         "MULLD",
 +              argLen:       2,
 +              commutative:  true,
 +              resultInArg0: true,
 +              clobberFlags: true,
 +              asm:          s390x.AMULLD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                              {1, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:         "MULLW",
 +              argLen:       2,
 +              commutative:  true,
 +              resultInArg0: true,
 +              clobberFlags: true,
 +              asm:          s390x.AMULLW,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                              {1, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:         "MULLDconst",
 +              auxType:      auxInt32,
 +              argLen:       1,
 +              resultInArg0: true,
 +              clobberFlags: true,
 +              asm:          s390x.AMULLD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:         "MULLWconst",
 +              auxType:      auxInt32,
 +              argLen:       1,
 +              resultInArg0: true,
 +              clobberFlags: true,
 +              asm:          s390x.AMULLW,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:           "MULLDload",
 +              auxType:        auxSymOff,
 +              argLen:         3,
 +              resultInArg0:   true,
 +              clobberFlags:   true,
 +              faultOnNilArg1: true,
 +              symEffect:      SymRead,
 +              asm:            s390x.AMULLD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                              {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:           "MULLWload",
 +              auxType:        auxSymOff,
 +              argLen:         3,
 +              resultInArg0:   true,
 +              clobberFlags:   true,
 +              faultOnNilArg1: true,
 +              symEffect:      SymRead,
 +              asm:            s390x.AMULLW,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                              {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:         "MULHD",
 +              argLen:       2,
 +              commutative:  true,
 +              resultInArg0: true,
 +              clobberFlags: true,
 +              asm:          s390x.AMULHD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                              {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                      },
 +                      clobbers: 2048, // R11
 +                      outputs: []outputInfo{
 +                              {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:         "MULHDU",
 +              argLen:       2,
 +              commutative:  true,
 +              resultInArg0: true,
 +              clobberFlags: true,
 +              asm:          s390x.AMULHDU,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                              {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                      },
 +                      clobbers: 2048, // R11
 +                      outputs: []outputInfo{
 +                              {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:         "DIVD",
 +              argLen:       2,
 +              resultInArg0: true,
 +              clobberFlags: true,
 +              asm:          s390x.ADIVD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                              {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                      },
 +                      clobbers: 2048, // R11
 +                      outputs: []outputInfo{
 +                              {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:         "DIVW",
 +              argLen:       2,
 +              resultInArg0: true,
 +              clobberFlags: true,
 +              asm:          s390x.ADIVW,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                              {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                      },
 +                      clobbers: 2048, // R11
 +                      outputs: []outputInfo{
 +                              {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:         "DIVDU",
 +              argLen:       2,
 +              resultInArg0: true,
 +              clobberFlags: true,
 +              asm:          s390x.ADIVDU,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                              {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                      },
 +                      clobbers: 2048, // R11
 +                      outputs: []outputInfo{
 +                              {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:         "DIVWU",
 +              argLen:       2,
 +              resultInArg0: true,
 +              clobberFlags: true,
 +              asm:          s390x.ADIVWU,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                              {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                      },
 +                      clobbers: 2048, // R11
 +                      outputs: []outputInfo{
 +                              {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:         "MODD",
 +              argLen:       2,
 +              resultInArg0: true,
 +              clobberFlags: true,
 +              asm:          s390x.AMODD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                              {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                      },
 +                      clobbers: 2048, // R11
 +                      outputs: []outputInfo{
 +                              {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:         "MODW",
 +              argLen:       2,
 +              resultInArg0: true,
 +              clobberFlags: true,
 +              asm:          s390x.AMODW,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                              {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                      },
 +                      clobbers: 2048, // R11
 +                      outputs: []outputInfo{
 +                              {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:         "MODDU",
 +              argLen:       2,
 +              resultInArg0: true,
 +              clobberFlags: true,
 +              asm:          s390x.AMODDU,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                              {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                      },
 +                      clobbers: 2048, // R11
 +                      outputs: []outputInfo{
 +                              {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:         "MODWU",
 +              argLen:       2,
 +              resultInArg0: true,
 +              clobberFlags: true,
 +              asm:          s390x.AMODWU,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                              {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                      },
 +                      clobbers: 2048, // R11
 +                      outputs: []outputInfo{
 +                              {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:         "AND",
 +              argLen:       2,
 +              commutative:  true,
 +              clobberFlags: true,
 +              asm:          s390x.AAND,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                              {1, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:         "ANDW",
 +              argLen:       2,
 +              commutative:  true,
 +              clobberFlags: true,
 +              asm:          s390x.AANDW,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                              {1, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:         "ANDconst",
 +              auxType:      auxInt64,
 +              argLen:       1,
 +              resultInArg0: true,
 +              clobberFlags: true,
 +              asm:          s390x.AAND,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:         "ANDWconst",
 +              auxType:      auxInt32,
 +              argLen:       1,
 +              resultInArg0: true,
 +              clobberFlags: true,
 +              asm:          s390x.AANDW,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:           "ANDload",
 +              auxType:        auxSymOff,
 +              argLen:         3,
 +              resultInArg0:   true,
 +              clobberFlags:   true,
 +              faultOnNilArg1: true,
 +              symEffect:      SymRead,
 +              asm:            s390x.AAND,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                              {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:           "ANDWload",
 +              auxType:        auxSymOff,
 +              argLen:         3,
 +              resultInArg0:   true,
 +              clobberFlags:   true,
 +              faultOnNilArg1: true,
 +              symEffect:      SymRead,
 +              asm:            s390x.AANDW,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                              {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:         "OR",
 +              argLen:       2,
 +              commutative:  true,
 +              clobberFlags: true,
 +              asm:          s390x.AOR,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                              {1, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:         "ORW",
 +              argLen:       2,
 +              commutative:  true,
 +              clobberFlags: true,
 +              asm:          s390x.AORW,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                              {1, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:         "ORconst",
 +              auxType:      auxInt64,
 +              argLen:       1,
 +              resultInArg0: true,
 +              clobberFlags: true,
 +              asm:          s390x.AOR,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:         "ORWconst",
 +              auxType:      auxInt32,
 +              argLen:       1,
 +              resultInArg0: true,
 +              clobberFlags: true,
 +              asm:          s390x.AORW,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:           "ORload",
 +              auxType:        auxSymOff,
 +              argLen:         3,
 +              resultInArg0:   true,
 +              clobberFlags:   true,
 +              faultOnNilArg1: true,
 +              symEffect:      SymRead,
 +              asm:            s390x.AOR,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                              {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:           "ORWload",
 +              auxType:        auxSymOff,
 +              argLen:         3,
 +              resultInArg0:   true,
 +              clobberFlags:   true,
 +              faultOnNilArg1: true,
 +              symEffect:      SymRead,
 +              asm:            s390x.AORW,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                              {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:         "XOR",
 +              argLen:       2,
 +              commutative:  true,
 +              clobberFlags: true,
 +              asm:          s390x.AXOR,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                              {1, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:         "XORW",
 +              argLen:       2,
 +              commutative:  true,
 +              clobberFlags: true,
 +              asm:          s390x.AXORW,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                              {1, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:         "XORconst",
 +              auxType:      auxInt64,
 +              argLen:       1,
 +              resultInArg0: true,
 +              clobberFlags: true,
 +              asm:          s390x.AXOR,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:         "XORWconst",
 +              auxType:      auxInt32,
 +              argLen:       1,
 +              resultInArg0: true,
 +              clobberFlags: true,
 +              asm:          s390x.AXORW,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:           "XORload",
 +              auxType:        auxSymOff,
 +              argLen:         3,
 +              resultInArg0:   true,
 +              clobberFlags:   true,
 +              faultOnNilArg1: true,
 +              symEffect:      SymRead,
 +              asm:            s390x.AXOR,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                              {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:           "XORWload",
 +              auxType:        auxSymOff,
 +              argLen:         3,
 +              resultInArg0:   true,
 +              clobberFlags:   true,
 +              faultOnNilArg1: true,
 +              symEffect:      SymRead,
 +              asm:            s390x.AXORW,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                              {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:        "ADDC",
 +              argLen:      2,
 +              commutative: true,
 +              asm:         s390x.AADDC,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                              {1, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:    "ADDCconst",
 +              auxType: auxInt16,
 +              argLen:  1,
 +              asm:     s390x.AADDC,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:         "ADDE",
 +              argLen:       3,
 +              commutative:  true,
 +              resultInArg0: true,
 +              asm:          s390x.AADDE,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                              {1, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:   "SUBC",
 +              argLen: 2,
 +              asm:    s390x.ASUBC,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                              {1, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:         "SUBE",
 +              argLen:       3,
 +              resultInArg0: true,
 +              asm:          s390x.ASUBE,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                              {1, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:   "CMP",
 +              argLen: 2,
 +              asm:    s390x.ACMP,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
 +                              {1, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
 +                      },
 +              },
 +      },
 +      {
 +              name:   "CMPW",
 +              argLen: 2,
 +              asm:    s390x.ACMPW,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
 +                              {1, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
 +                      },
 +              },
 +      },
 +      {
 +              name:   "CMPU",
 +              argLen: 2,
 +              asm:    s390x.ACMPU,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
 +                              {1, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
 +                      },
 +              },
 +      },
 +      {
 +              name:   "CMPWU",
 +              argLen: 2,
 +              asm:    s390x.ACMPWU,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
 +                              {1, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
 +                      },
 +              },
 +      },
 +      {
 +              name:    "CMPconst",
 +              auxType: auxInt32,
 +              argLen:  1,
 +              asm:     s390x.ACMP,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
 +                      },
 +              },
 +      },
 +      {
 +              name:    "CMPWconst",
 +              auxType: auxInt32,
 +              argLen:  1,
 +              asm:     s390x.ACMPW,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
 +                      },
 +              },
 +      },
 +      {
 +              name:    "CMPUconst",
 +              auxType: auxInt32,
 +              argLen:  1,
 +              asm:     s390x.ACMPU,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
 +                      },
 +              },
 +      },
 +      {
 +              name:    "CMPWUconst",
 +              auxType: auxInt32,
 +              argLen:  1,
 +              asm:     s390x.ACMPWU,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
 +                      },
 +              },
 +      },
 +      {
 +              name:   "FCMPS",
 +              argLen: 2,
 +              asm:    s390x.ACEBR,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 +                              {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 +                      },
 +              },
 +      },
 +      {
 +              name:   "FCMP",
 +              argLen: 2,
 +              asm:    s390x.AFCMPU,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 +                              {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 +                      },
 +              },
 +      },
 +      {
 +              name:   "LTDBR",
 +              argLen: 1,
 +              asm:    s390x.ALTDBR,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 +                      },
 +              },
 +      },
 +      {
 +              name:   "LTEBR",
 +              argLen: 1,
 +              asm:    s390x.ALTEBR,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 +                      },
 +              },
 +      },
 +      {
 +              name:   "SLD",
 +              argLen: 2,
 +              asm:    s390x.ASLD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 23550}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                              {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:   "SLW",
 +              argLen: 2,
 +              asm:    s390x.ASLW,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 23550}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                              {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:    "SLDconst",
 +              auxType: auxUInt8,
 +              argLen:  1,
 +              asm:     s390x.ASLD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:    "SLWconst",
 +              auxType: auxUInt8,
 +              argLen:  1,
 +              asm:     s390x.ASLW,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:   "SRD",
 +              argLen: 2,
 +              asm:    s390x.ASRD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 23550}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                              {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:   "SRW",
 +              argLen: 2,
 +              asm:    s390x.ASRW,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 23550}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                              {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:    "SRDconst",
 +              auxType: auxUInt8,
 +              argLen:  1,
 +              asm:     s390x.ASRD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:    "SRWconst",
 +              auxType: auxUInt8,
 +              argLen:  1,
 +              asm:     s390x.ASRW,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:         "SRAD",
 +              argLen:       2,
 +              clobberFlags: true,
 +              asm:          s390x.ASRAD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 23550}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                              {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:         "SRAW",
 +              argLen:       2,
 +              clobberFlags: true,
 +              asm:          s390x.ASRAW,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 23550}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                              {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:         "SRADconst",
 +              auxType:      auxUInt8,
 +              argLen:       1,
 +              clobberFlags: true,
 +              asm:          s390x.ASRAD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:         "SRAWconst",
 +              auxType:      auxUInt8,
 +              argLen:       1,
 +              clobberFlags: true,
 +              asm:          s390x.ASRAW,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:   "RLLG",
 +              argLen: 2,
 +              asm:    s390x.ARLLG,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 23550}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                              {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:   "RLL",
 +              argLen: 2,
 +              asm:    s390x.ARLL,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 23550}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                              {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:    "RLLconst",
 +              auxType: auxUInt8,
 +              argLen:  1,
 +              asm:     s390x.ARLL,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:         "RXSBG",
 +              auxType:      auxS390XRotateParams,
 +              argLen:       2,
 +              resultInArg0: true,
 +              clobberFlags: true,
 +              asm:          s390x.ARXSBG,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                              {1, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:         "RISBGZ",
 +              auxType:      auxS390XRotateParams,
 +              argLen:       1,
 +              clobberFlags: true,
 +              asm:          s390x.ARISBGZ,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:         "NEG",
 +              argLen:       1,
 +              clobberFlags: true,
 +              asm:          s390x.ANEG,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:         "NEGW",
 +              argLen:       1,
 +              clobberFlags: true,
 +              asm:          s390x.ANEGW,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:         "NOT",
 +              argLen:       1,
 +              resultInArg0: true,
 +              clobberFlags: true,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:         "NOTW",
 +              argLen:       1,
 +              resultInArg0: true,
 +              clobberFlags: true,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:   "FSQRT",
 +              argLen: 1,
 +              asm:    s390x.AFSQRT,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 +                      },
 +              },
 +      },
 +      {
 +              name:   "FSQRTS",
 +              argLen: 1,
 +              asm:    s390x.AFSQRTS,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 +                      },
 +              },
 +      },
 +      {
 +              name:         "LOCGR",
 +              auxType:      auxS390XCCMask,
 +              argLen:       3,
 +              resultInArg0: true,
 +              asm:          s390x.ALOCGR,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                              {1, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:   "MOVBreg",
 +              argLen: 1,
 +              asm:    s390x.AMOVB,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:   "MOVBZreg",
 +              argLen: 1,
 +              asm:    s390x.AMOVBZ,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:   "MOVHreg",
 +              argLen: 1,
 +              asm:    s390x.AMOVH,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:   "MOVHZreg",
 +              argLen: 1,
 +              asm:    s390x.AMOVHZ,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:   "MOVWreg",
 +              argLen: 1,
 +              asm:    s390x.AMOVW,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:   "MOVWZreg",
 +              argLen: 1,
 +              asm:    s390x.AMOVWZ,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:              "MOVDconst",
 +              auxType:           auxInt64,
 +              argLen:            0,
 +              rematerializeable: true,
 +              asm:               s390x.AMOVD,
 +              reg: regInfo{
 +                      outputs: []outputInfo{
 +                              {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:   "LDGR",
 +              argLen: 1,
 +              asm:    s390x.ALDGR,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 +                      },
 +              },
 +      },
 +      {
 +              name:   "LGDR",
 +              argLen: 1,
 +              asm:    s390x.ALGDR,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:         "CFDBRA",
 +              argLen:       1,
 +              clobberFlags: true,
 +              asm:          s390x.ACFDBRA,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:         "CGDBRA",
 +              argLen:       1,
 +              clobberFlags: true,
 +              asm:          s390x.ACGDBRA,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:         "CFEBRA",
 +              argLen:       1,
 +              clobberFlags: true,
 +              asm:          s390x.ACFEBRA,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:         "CGEBRA",
 +              argLen:       1,
 +              clobberFlags: true,
 +              asm:          s390x.ACGEBRA,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:         "CEFBRA",
 +              argLen:       1,
 +              clobberFlags: true,
 +              asm:          s390x.ACEFBRA,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 +                      },
 +              },
 +      },
 +      {
 +              name:         "CDFBRA",
 +              argLen:       1,
 +              clobberFlags: true,
 +              asm:          s390x.ACDFBRA,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 +                      },
 +              },
 +      },
 +      {
 +              name:         "CEGBRA",
 +              argLen:       1,
 +              clobberFlags: true,
 +              asm:          s390x.ACEGBRA,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 +                      },
 +              },
 +      },
 +      {
 +              name:         "CDGBRA",
 +              argLen:       1,
 +              clobberFlags: true,
 +              asm:          s390x.ACDGBRA,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 +                      },
 +              },
 +      },
 +      {
 +              name:         "CLFEBR",
 +              argLen:       1,
 +              clobberFlags: true,
 +              asm:          s390x.ACLFEBR,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:         "CLFDBR",
 +              argLen:       1,
 +              clobberFlags: true,
 +              asm:          s390x.ACLFDBR,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:         "CLGEBR",
 +              argLen:       1,
 +              clobberFlags: true,
 +              asm:          s390x.ACLGEBR,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:         "CLGDBR",
 +              argLen:       1,
 +              clobberFlags: true,
 +              asm:          s390x.ACLGDBR,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:         "CELFBR",
 +              argLen:       1,
 +              clobberFlags: true,
 +              asm:          s390x.ACELFBR,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 +                      },
 +              },
 +      },
 +      {
 +              name:         "CDLFBR",
 +              argLen:       1,
 +              clobberFlags: true,
 +              asm:          s390x.ACDLFBR,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 +                      },
 +              },
 +      },
 +      {
 +              name:         "CELGBR",
 +              argLen:       1,
 +              clobberFlags: true,
 +              asm:          s390x.ACELGBR,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 +                      },
 +              },
 +      },
 +      {
 +              name:         "CDLGBR",
 +              argLen:       1,
 +              clobberFlags: true,
 +              asm:          s390x.ACDLGBR,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 +                      },
 +              },
 +      },
 +      {
 +              name:   "LEDBR",
 +              argLen: 1,
 +              asm:    s390x.ALEDBR,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 +                      },
 +              },
 +      },
 +      {
 +              name:   "LDEBR",
 +              argLen: 1,
 +              asm:    s390x.ALDEBR,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 +                      },
 +              },
 +      },
 +      {
 +              name:              "MOVDaddr",
 +              auxType:           auxSymOff,
 +              argLen:            1,
 +              rematerializeable: true,
 +              symEffect:         SymAddr,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 4295000064}, // SP SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:      "MOVDaddridx",
 +              auxType:   auxSymOff,
 +              argLen:    2,
 +              symEffect: SymAddr,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 4295000064}, // SP SB
 +                              {1, 56318},      // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:           "MOVBZload",
 +              auxType:        auxSymOff,
 +              argLen:         2,
 +              faultOnNilArg0: true,
 +              symEffect:      SymRead,
 +              asm:            s390x.AMOVBZ,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:           "MOVBload",
 +              auxType:        auxSymOff,
 +              argLen:         2,
 +              faultOnNilArg0: true,
 +              symEffect:      SymRead,
 +              asm:            s390x.AMOVB,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:           "MOVHZload",
 +              auxType:        auxSymOff,
 +              argLen:         2,
 +              faultOnNilArg0: true,
 +              symEffect:      SymRead,
 +              asm:            s390x.AMOVHZ,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:           "MOVHload",
 +              auxType:        auxSymOff,
 +              argLen:         2,
 +              faultOnNilArg0: true,
 +              symEffect:      SymRead,
 +              asm:            s390x.AMOVH,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:           "MOVWZload",
 +              auxType:        auxSymOff,
 +              argLen:         2,
 +              faultOnNilArg0: true,
 +              symEffect:      SymRead,
 +              asm:            s390x.AMOVWZ,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:           "MOVWload",
 +              auxType:        auxSymOff,
 +              argLen:         2,
 +              faultOnNilArg0: true,
 +              symEffect:      SymRead,
 +              asm:            s390x.AMOVW,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:           "MOVDload",
 +              auxType:        auxSymOff,
 +              argLen:         2,
 +              faultOnNilArg0: true,
 +              symEffect:      SymRead,
 +              asm:            s390x.AMOVD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:   "MOVWBR",
 +              argLen: 1,
 +              asm:    s390x.AMOVWBR,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:   "MOVDBR",
 +              argLen: 1,
 +              asm:    s390x.AMOVDBR,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:           "MOVHBRload",
 +              auxType:        auxSymOff,
 +              argLen:         2,
 +              faultOnNilArg0: true,
 +              symEffect:      SymRead,
 +              asm:            s390x.AMOVHBR,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:           "MOVWBRload",
 +              auxType:        auxSymOff,
 +              argLen:         2,
 +              faultOnNilArg0: true,
 +              symEffect:      SymRead,
 +              asm:            s390x.AMOVWBR,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:           "MOVDBRload",
 +              auxType:        auxSymOff,
 +              argLen:         2,
 +              faultOnNilArg0: true,
 +              symEffect:      SymRead,
 +              asm:            s390x.AMOVDBR,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:           "MOVBstore",
 +              auxType:        auxSymOff,
 +              argLen:         3,
 +              faultOnNilArg0: true,
 +              symEffect:      SymWrite,
 +              asm:            s390x.AMOVB,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB
 +                              {1, 56319},      // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
 +                      },
 +              },
 +      },
 +      {
 +              name:           "MOVHstore",
 +              auxType:        auxSymOff,
 +              argLen:         3,
 +              faultOnNilArg0: true,
 +              symEffect:      SymWrite,
 +              asm:            s390x.AMOVH,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB
 +                              {1, 56319},      // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
 +                      },
 +              },
 +      },
 +      {
 +              name:           "MOVWstore",
 +              auxType:        auxSymOff,
 +              argLen:         3,
 +              faultOnNilArg0: true,
 +              symEffect:      SymWrite,
 +              asm:            s390x.AMOVW,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB
 +                              {1, 56319},      // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
 +                      },
 +              },
 +      },
 +      {
 +              name:           "MOVDstore",
 +              auxType:        auxSymOff,
 +              argLen:         3,
 +              faultOnNilArg0: true,
 +              symEffect:      SymWrite,
 +              asm:            s390x.AMOVD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB
 +                              {1, 56319},      // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
 +                      },
 +              },
 +      },
 +      {
 +              name:           "MOVHBRstore",
 +              auxType:        auxSymOff,
 +              argLen:         3,
 +              faultOnNilArg0: true,
 +              symEffect:      SymWrite,
 +              asm:            s390x.AMOVHBR,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
 +                              {1, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
 +                      },
 +              },
 +      },
 +      {
 +              name:           "MOVWBRstore",
 +              auxType:        auxSymOff,
 +              argLen:         3,
 +              faultOnNilArg0: true,
 +              symEffect:      SymWrite,
 +              asm:            s390x.AMOVWBR,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
 +                              {1, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
 +                      },
 +              },
 +      },
 +      {
 +              name:           "MOVDBRstore",
 +              auxType:        auxSymOff,
 +              argLen:         3,
 +              faultOnNilArg0: true,
 +              symEffect:      SymWrite,
 +              asm:            s390x.AMOVDBR,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
 +                              {1, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
 +                      },
 +              },
 +      },
 +      {
 +              name:           "MVC",
 +              auxType:        auxSymValAndOff,
 +              argLen:         3,
 +              clobberFlags:   true,
 +              faultOnNilArg0: true,
 +              faultOnNilArg1: true,
 +              symEffect:      SymNone,
 +              asm:            s390x.AMVC,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
 +                              {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
 +                      },
 +              },
 +      },
 +      {
 +              name:        "MOVBZloadidx",
 +              auxType:     auxSymOff,
 +              argLen:      3,
 +              commutative: true,
 +              symEffect:   SymRead,
 +              asm:         s390x.AMOVBZ,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 56318},      // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
 +                              {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:        "MOVBloadidx",
 +              auxType:     auxSymOff,
 +              argLen:      3,
 +              commutative: true,
 +              symEffect:   SymRead,
 +              asm:         s390x.AMOVB,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 56318},      // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
 +                              {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:        "MOVHZloadidx",
 +              auxType:     auxSymOff,
 +              argLen:      3,
 +              commutative: true,
 +              symEffect:   SymRead,
 +              asm:         s390x.AMOVHZ,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 56318},      // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
 +                              {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:        "MOVHloadidx",
 +              auxType:     auxSymOff,
 +              argLen:      3,
 +              commutative: true,
 +              symEffect:   SymRead,
 +              asm:         s390x.AMOVH,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 56318},      // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
 +                              {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:        "MOVWZloadidx",
 +              auxType:     auxSymOff,
 +              argLen:      3,
 +              commutative: true,
 +              symEffect:   SymRead,
 +              asm:         s390x.AMOVWZ,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 56318},      // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
 +                              {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:        "MOVWloadidx",
 +              auxType:     auxSymOff,
 +              argLen:      3,
 +              commutative: true,
 +              symEffect:   SymRead,
 +              asm:         s390x.AMOVW,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 56318},      // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
 +                              {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:        "MOVDloadidx",
 +              auxType:     auxSymOff,
 +              argLen:      3,
 +              commutative: true,
 +              symEffect:   SymRead,
 +              asm:         s390x.AMOVD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 56318},      // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
 +                              {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:        "MOVHBRloadidx",
 +              auxType:     auxSymOff,
 +              argLen:      3,
 +              commutative: true,
 +              symEffect:   SymRead,
 +              asm:         s390x.AMOVHBR,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 56318},      // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
 +                              {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:        "MOVWBRloadidx",
 +              auxType:     auxSymOff,
 +              argLen:      3,
 +              commutative: true,
 +              symEffect:   SymRead,
 +              asm:         s390x.AMOVWBR,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 56318},      // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
 +                              {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:        "MOVDBRloadidx",
 +              auxType:     auxSymOff,
 +              argLen:      3,
 +              commutative: true,
 +              symEffect:   SymRead,
 +              asm:         s390x.AMOVDBR,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 56318},      // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
 +                              {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:        "MOVBstoreidx",
 +              auxType:     auxSymOff,
 +              argLen:      4,
 +              commutative: true,
 +              symEffect:   SymWrite,
 +              asm:         s390x.AMOVB,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
 +                              {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
 +                              {2, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
 +                      },
 +              },
 +      },
 +      {
 +              name:        "MOVHstoreidx",
 +              auxType:     auxSymOff,
 +              argLen:      4,
 +              commutative: true,
 +              symEffect:   SymWrite,
 +              asm:         s390x.AMOVH,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
 +                              {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
 +                              {2, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
 +                      },
 +              },
 +      },
 +      {
 +              name:        "MOVWstoreidx",
 +              auxType:     auxSymOff,
 +              argLen:      4,
 +              commutative: true,
 +              symEffect:   SymWrite,
 +              asm:         s390x.AMOVW,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
 +                              {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
 +                              {2, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
 +                      },
 +              },
 +      },
 +      {
 +              name:        "MOVDstoreidx",
 +              auxType:     auxSymOff,
 +              argLen:      4,
 +              commutative: true,
 +              symEffect:   SymWrite,
 +              asm:         s390x.AMOVD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
 +                              {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
 +                              {2, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
 +                      },
 +              },
 +      },
 +      {
 +              name:        "MOVHBRstoreidx",
 +              auxType:     auxSymOff,
 +              argLen:      4,
 +              commutative: true,
 +              symEffect:   SymWrite,
 +              asm:         s390x.AMOVHBR,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
 +                              {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
 +                              {2, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
 +                      },
 +              },
 +      },
 +      {
 +              name:        "MOVWBRstoreidx",
 +              auxType:     auxSymOff,
 +              argLen:      4,
 +              commutative: true,
 +              symEffect:   SymWrite,
 +              asm:         s390x.AMOVWBR,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
 +                              {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
 +                              {2, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
 +                      },
 +              },
 +      },
 +      {
 +              name:        "MOVDBRstoreidx",
 +              auxType:     auxSymOff,
 +              argLen:      4,
 +              commutative: true,
 +              symEffect:   SymWrite,
 +              asm:         s390x.AMOVDBR,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
 +                              {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
 +                              {2, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
 +                      },
 +              },
 +      },
 +      {
 +              name:           "MOVBstoreconst",
 +              auxType:        auxSymValAndOff,
 +              argLen:         2,
 +              faultOnNilArg0: true,
 +              symEffect:      SymWrite,
 +              asm:            s390x.AMOVB,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB
 +                      },
 +              },
 +      },
 +      {
 +              name:           "MOVHstoreconst",
 +              auxType:        auxSymValAndOff,
 +              argLen:         2,
 +              faultOnNilArg0: true,
 +              symEffect:      SymWrite,
 +              asm:            s390x.AMOVH,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB
 +                      },
 +              },
 +      },
 +      {
 +              name:           "MOVWstoreconst",
 +              auxType:        auxSymValAndOff,
 +              argLen:         2,
 +              faultOnNilArg0: true,
 +              symEffect:      SymWrite,
 +              asm:            s390x.AMOVW,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB
 +                      },
 +              },
 +      },
 +      {
 +              name:           "MOVDstoreconst",
 +              auxType:        auxSymValAndOff,
 +              argLen:         2,
 +              faultOnNilArg0: true,
 +              symEffect:      SymWrite,
 +              asm:            s390x.AMOVD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB
 +                      },
 +              },
 +      },
 +      {
 +              name:           "CLEAR",
 +              auxType:        auxSymValAndOff,
 +              argLen:         2,
 +              clobberFlags:   true,
 +              faultOnNilArg0: true,
 +              symEffect:      SymWrite,
 +              asm:            s390x.ACLEAR,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 23550}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:         "CALLstatic",
 +              auxType:      auxCallOff,
 +              argLen:       1,
 +              clobberFlags: true,
 +              call:         true,
 +              reg: regInfo{
 +                      clobbers: 4294933503, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 g R14 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 +              },
 +      },
 +      {
 +              name:         "CALLtail",
 +              auxType:      auxCallOff,
 +              argLen:       1,
 +              clobberFlags: true,
 +              call:         true,
 +              tailCall:     true,
 +              reg: regInfo{
 +                      clobbers: 4294933503, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 g R14 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 +              },
 +      },
 +      {
 +              name:         "CALLclosure",
 +              auxType:      auxCallOff,
 +              argLen:       3,
 +              clobberFlags: true,
 +              call:         true,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 4096},  // R12
 +                              {0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
 +                      },
 +                      clobbers: 4294933503, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 g R14 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 +              },
 +      },
 +      {
 +              name:         "CALLinter",
 +              auxType:      auxCallOff,
 +              argLen:       2,
 +              clobberFlags: true,
 +              call:         true,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 23550}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                      },
 +                      clobbers: 4294933503, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 g R14 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 +              },
 +      },
 +      {
 +              name:   "InvertFlags",
 +              argLen: 1,
 +              reg:    regInfo{},
 +      },
 +      {
 +              name:   "LoweredGetG",
 +              argLen: 1,
 +              reg: regInfo{
 +                      outputs: []outputInfo{
 +                              {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:      "LoweredGetClosurePtr",
 +              argLen:    0,
 +              zeroWidth: true,
 +              reg: regInfo{
 +                      outputs: []outputInfo{
 +                              {0, 4096}, // R12
 +                      },
 +              },
 +      },
 +      {
 +              name:              "LoweredGetCallerSP",
 +              argLen:            1,
 +              rematerializeable: true,
 +              reg: regInfo{
 +                      outputs: []outputInfo{
 +                              {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:              "LoweredGetCallerPC",
 +              argLen:            0,
 +              rematerializeable: true,
 +              reg: regInfo{
 +                      outputs: []outputInfo{
 +                              {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:           "LoweredNilCheck",
 +              argLen:         2,
 +              clobberFlags:   true,
 +              nilCheck:       true,
 +              faultOnNilArg0: true,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
 +                      },
 +              },
 +      },
 +      {
 +              name:         "LoweredRound32F",
 +              argLen:       1,
 +              resultInArg0: true,
 +              zeroWidth:    true,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 +                      },
 +              },
 +      },
 +      {
 +              name:         "LoweredRound64F",
 +              argLen:       1,
 +              resultInArg0: true,
 +              zeroWidth:    true,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 +                      },
 +              },
 +      },
 +      {
 +              name:         "LoweredWB",
 +              auxType:      auxInt64,
 +              argLen:       1,
 +              clobberFlags: true,
 +              reg: regInfo{
 +                      clobbers: 4294918146, // R1 R14 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 +                      outputs: []outputInfo{
 +                              {0, 512}, // R9
 +                      },
 +              },
 +      },
 +      {
 +              name:    "LoweredPanicBoundsRR",
 +              auxType: auxInt64,
 +              argLen:  3,
 +              call:    true,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 7167}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12
 +                              {1, 7167}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12
 +                      },
 +              },
 +      },
 +      {
 +              name:    "LoweredPanicBoundsRC",
 +              auxType: auxPanicBoundsC,
 +              argLen:  2,
 +              call:    true,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 7167}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12
 +                      },
 +              },
 +      },
 +      {
 +              name:    "LoweredPanicBoundsCR",
 +              auxType: auxPanicBoundsC,
 +              argLen:  2,
 +              call:    true,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 7167}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12
 +                      },
 +              },
 +      },
 +      {
 +              name:    "LoweredPanicBoundsCC",
 +              auxType: auxPanicBoundsCC,
 +              argLen:  1,
 +              call:    true,
 +              reg:     regInfo{},
 +      },
 +      {
 +              name:   "FlagEQ",
 +              argLen: 0,
 +              reg:    regInfo{},
 +      },
 +      {
 +              name:   "FlagLT",
 +              argLen: 0,
 +              reg:    regInfo{},
 +      },
 +      {
 +              name:   "FlagGT",
 +              argLen: 0,
 +              reg:    regInfo{},
 +      },
 +      {
 +              name:   "FlagOV",
 +              argLen: 0,
 +              reg:    regInfo{},
 +      },
 +      {
 +              name:   "SYNC",
 +              argLen: 1,
 +              asm:    s390x.ASYNC,
 +              reg:    regInfo{},
 +      },
 +      {
 +              name:           "MOVBZatomicload",
 +              auxType:        auxSymOff,
 +              argLen:         2,
 +              faultOnNilArg0: true,
 +              symEffect:      SymRead,
 +              asm:            s390x.AMOVBZ,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:           "MOVWZatomicload",
 +              auxType:        auxSymOff,
 +              argLen:         2,
 +              faultOnNilArg0: true,
 +              symEffect:      SymRead,
 +              asm:            s390x.AMOVWZ,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:           "MOVDatomicload",
 +              auxType:        auxSymOff,
 +              argLen:         2,
 +              faultOnNilArg0: true,
 +              symEffect:      SymRead,
 +              asm:            s390x.AMOVD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:           "MOVBatomicstore",
 +              auxType:        auxSymOff,
 +              argLen:         3,
 +              clobberFlags:   true,
 +              faultOnNilArg0: true,
 +              hasSideEffects: true,
 +              symEffect:      SymWrite,
 +              asm:            s390x.AMOVB,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB
 +                              {1, 56319},      // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
 +                      },
 +              },
 +      },
 +      {
 +              name:           "MOVWatomicstore",
 +              auxType:        auxSymOff,
 +              argLen:         3,
 +              clobberFlags:   true,
 +              faultOnNilArg0: true,
 +              hasSideEffects: true,
 +              symEffect:      SymWrite,
 +              asm:            s390x.AMOVW,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB
 +                              {1, 56319},      // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
 +                      },
 +              },
 +      },
 +      {
 +              name:           "MOVDatomicstore",
 +              auxType:        auxSymOff,
 +              argLen:         3,
 +              clobberFlags:   true,
 +              faultOnNilArg0: true,
 +              hasSideEffects: true,
 +              symEffect:      SymWrite,
 +              asm:            s390x.AMOVD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB
 +                              {1, 56319},      // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
 +                      },
 +              },
 +      },
 +      {
 +              name:           "LAA",
 +              auxType:        auxSymOff,
 +              argLen:         3,
 +              clobberFlags:   true,
 +              faultOnNilArg0: true,
 +              hasSideEffects: true,
 +              symEffect:      SymRdWr,
 +              asm:            s390x.ALAA,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB
 +                              {1, 56319},      // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:           "LAAG",
 +              auxType:        auxSymOff,
 +              argLen:         3,
 +              clobberFlags:   true,
 +              faultOnNilArg0: true,
 +              hasSideEffects: true,
 +              symEffect:      SymRdWr,
 +              asm:            s390x.ALAAG,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB
 +                              {1, 56319},      // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:   "AddTupleFirst32",
 +              argLen: 2,
 +              reg:    regInfo{},
 +      },
 +      {
 +              name:   "AddTupleFirst64",
 +              argLen: 2,
 +              reg:    regInfo{},
 +      },
 +      {
 +              name:           "LAN",
 +              argLen:         3,
 +              clobberFlags:   true,
 +              hasSideEffects: true,
 +              asm:            s390x.ALAN,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB
 +                              {1, 56319},      // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
 +                      },
 +              },
 +      },
 +      {
 +              name:           "LANfloor",
 +              argLen:         3,
 +              clobberFlags:   true,
 +              hasSideEffects: true,
 +              asm:            s390x.ALAN,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 2},     // R1
 +                              {1, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
 +                      },
 +                      clobbers: 2, // R1
 +              },
 +      },
 +      {
 +              name:           "LAO",
 +              argLen:         3,
 +              clobberFlags:   true,
 +              hasSideEffects: true,
 +              asm:            s390x.ALAO,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB
 +                              {1, 56319},      // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
 +                      },
 +              },
 +      },
 +      {
 +              name:           "LAOfloor",
 +              argLen:         3,
 +              clobberFlags:   true,
 +              hasSideEffects: true,
 +              asm:            s390x.ALAO,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 2},     // R1
 +                              {1, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
 +                      },
 +                      clobbers: 2, // R1
 +              },
 +      },
 +      {
 +              name:           "LoweredAtomicCas32",
 +              auxType:        auxSymOff,
 +              argLen:         4,
 +              clobberFlags:   true,
 +              faultOnNilArg0: true,
 +              hasSideEffects: true,
 +              symEffect:      SymRdWr,
 +              asm:            s390x.ACS,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 1},     // R0
 +                              {0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
 +                              {2, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
 +                      },
 +                      clobbers: 1, // R0
 +                      outputs: []outputInfo{
 +                              {1, 0},
 +                              {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:           "LoweredAtomicCas64",
 +              auxType:        auxSymOff,
 +              argLen:         4,
 +              clobberFlags:   true,
 +              faultOnNilArg0: true,
 +              hasSideEffects: true,
 +              symEffect:      SymRdWr,
 +              asm:            s390x.ACSG,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 1},     // R0
 +                              {0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
 +                              {2, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
 +                      },
 +                      clobbers: 1, // R0
 +                      outputs: []outputInfo{
 +                              {1, 0},
 +                              {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:           "LoweredAtomicExchange32",
 +              auxType:        auxSymOff,
 +              argLen:         3,
 +              clobberFlags:   true,
 +              faultOnNilArg0: true,
 +              hasSideEffects: true,
 +              symEffect:      SymRdWr,
 +              asm:            s390x.ACS,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
 +                              {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
 +                      },
 +                      outputs: []outputInfo{
 +                              {1, 0},
 +                              {0, 1}, // R0
 +                      },
 +              },
 +      },
 +      {
 +              name:           "LoweredAtomicExchange64",
 +              auxType:        auxSymOff,
 +              argLen:         3,
 +              clobberFlags:   true,
 +              faultOnNilArg0: true,
 +              hasSideEffects: true,
 +              symEffect:      SymRdWr,
 +              asm:            s390x.ACSG,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
 +                              {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
 +                      },
 +                      outputs: []outputInfo{
 +                              {1, 0},
 +                              {0, 1}, // R0
 +                      },
 +              },
 +      },
 +      {
 +              name:         "FLOGR",
 +              argLen:       1,
 +              clobberFlags: true,
 +              asm:          s390x.AFLOGR,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                      },
 +                      clobbers: 2, // R1
 +                      outputs: []outputInfo{
 +                              {0, 1}, // R0
 +                      },
 +              },
 +      },
 +      {
 +              name:         "POPCNT",
 +              argLen:       1,
 +              clobberFlags: true,
 +              asm:          s390x.APOPCNT,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:   "MLGR",
 +              argLen: 2,
 +              asm:    s390x.AMLGR,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 8},     // R3
 +                              {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 4}, // R2
 +                              {1, 8}, // R3
 +                      },
 +              },
 +      },
 +      {
 +              name:   "SumBytes2",
 +              argLen: 1,
 +              reg:    regInfo{},
 +      },
 +      {
 +              name:   "SumBytes4",
 +              argLen: 1,
 +              reg:    regInfo{},
 +      },
 +      {
 +              name:   "SumBytes8",
 +              argLen: 1,
 +              reg:    regInfo{},
 +      },
 +      {
 +              name:           "STMG2",
 +              auxType:        auxSymOff,
 +              argLen:         4,
 +              clobberFlags:   true,
 +              faultOnNilArg0: true,
 +              symEffect:      SymWrite,
 +              asm:            s390x.ASTMG,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 2},     // R1
 +                              {2, 4},     // R2
 +                              {0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
 +                      },
 +              },
 +      },
 +      {
 +              name:           "STMG3",
 +              auxType:        auxSymOff,
 +              argLen:         5,
 +              clobberFlags:   true,
 +              faultOnNilArg0: true,
 +              symEffect:      SymWrite,
 +              asm:            s390x.ASTMG,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 2},     // R1
 +                              {2, 4},     // R2
 +                              {3, 8},     // R3
 +                              {0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
 +                      },
 +              },
 +      },
 +      {
 +              name:           "STMG4",
 +              auxType:        auxSymOff,
 +              argLen:         6,
 +              clobberFlags:   true,
 +              faultOnNilArg0: true,
 +              symEffect:      SymWrite,
 +              asm:            s390x.ASTMG,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 2},     // R1
 +                              {2, 4},     // R2
 +                              {3, 8},     // R3
 +                              {4, 16},    // R4
 +                              {0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
 +                      },
 +              },
 +      },
 +      {
 +              name:           "STM2",
 +              auxType:        auxSymOff,
 +              argLen:         4,
 +              clobberFlags:   true,
 +              faultOnNilArg0: true,
 +              symEffect:      SymWrite,
 +              asm:            s390x.ASTMY,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 2},     // R1
 +                              {2, 4},     // R2
 +                              {0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
 +                      },
 +              },
 +      },
 +      {
 +              name:           "STM3",
 +              auxType:        auxSymOff,
 +              argLen:         5,
 +              clobberFlags:   true,
 +              faultOnNilArg0: true,
 +              symEffect:      SymWrite,
 +              asm:            s390x.ASTMY,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 2},     // R1
 +                              {2, 4},     // R2
 +                              {3, 8},     // R3
 +                              {0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
 +                      },
 +              },
 +      },
 +      {
 +              name:           "STM4",
 +              auxType:        auxSymOff,
 +              argLen:         6,
 +              clobberFlags:   true,
 +              faultOnNilArg0: true,
 +              symEffect:      SymWrite,
 +              asm:            s390x.ASTMY,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 2},     // R1
 +                              {2, 4},     // R2
 +                              {3, 8},     // R3
 +                              {4, 16},    // R4
 +                              {0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
 +                      },
 +              },
 +      },
 +      {
 +              name:           "LoweredMove",
 +              auxType:        auxInt64,
 +              argLen:         4,
 +              clobberFlags:   true,
 +              faultOnNilArg0: true,
 +              faultOnNilArg1: true,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 2},     // R1
 +                              {1, 4},     // R2
 +                              {2, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
 +                      },
 +                      clobbers: 6, // R1 R2
 +              },
 +      },
 +      {
 +              name:           "LoweredZero",
 +              auxType:        auxInt64,
 +              argLen:         3,
 +              clobberFlags:   true,
 +              faultOnNilArg0: true,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 2},     // R1
 +                              {1, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
 +                      },
 +                      clobbers: 2, // R1
 +              },
 +      },
 +
 +      {
 +              name:    "LoweredStaticCall",
 +              auxType: auxCallOff,
 +              argLen:  1,
 +              call:    true,
 +              reg: regInfo{
 +                      clobbers: 844424930131967, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 g
 +              },
 +      },
 +      {
 +              name:     "LoweredTailCall",
 +              auxType:  auxCallOff,
 +              argLen:   1,
 +              call:     true,
 +              tailCall: true,
 +              reg: regInfo{
 +                      clobbers: 844424930131967, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 g
 +              },
 +      },
 +      {
 +              name:    "LoweredClosureCall",
 +              auxType: auxCallOff,
 +              argLen:  3,
 +              call:    true,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
 +                              {1, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
 +                      },
 +                      clobbers: 844424930131967, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 g
 +              },
 +      },
 +      {
 +              name:    "LoweredInterCall",
 +              auxType: auxCallOff,
 +              argLen:  2,
 +              call:    true,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
 +                      },
 +                      clobbers: 844424930131967, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 g
 +              },
 +      },
 +      {
 +              name:              "LoweredAddr",
 +              auxType:           auxSymOff,
 +              argLen:            1,
 +              rematerializeable: true,
 +              symEffect:         SymAddr,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
 +                      },
 +              },
 +      },
 +      {
 +              name:    "LoweredMove",
 +              auxType: auxInt64,
 +              argLen:  3,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
 +                              {1, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
 +                      },
 +              },
 +      },
 +      {
 +              name:    "LoweredZero",
 +              auxType: auxInt64,
 +              argLen:  2,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
 +                      },
 +              },
 +      },
 +      {
 +              name:   "LoweredGetClosurePtr",
 +              argLen: 0,
 +              reg: regInfo{
 +                      outputs: []outputInfo{
 +                              {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
 +                      },
 +              },
 +      },
 +      {
 +              name:              "LoweredGetCallerPC",
 +              argLen:            0,
 +              rematerializeable: true,
 +              reg: regInfo{
 +                      outputs: []outputInfo{
 +                              {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
 +                      },
 +              },
 +      },
 +      {
 +              name:              "LoweredGetCallerSP",
 +              argLen:            1,
 +              rematerializeable: true,
 +              reg: regInfo{
 +                      outputs: []outputInfo{
 +                              {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
 +                      },
 +              },
 +      },
 +      {
 +              name:           "LoweredNilCheck",
 +              argLen:         2,
 +              nilCheck:       true,
 +              faultOnNilArg0: true,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
 +                      },
 +              },
 +      },
 +      {
 +              name:    "LoweredWB",
 +              auxType: auxInt64,
 +              argLen:  1,
 +              reg: regInfo{
 +                      clobbers: 844424930131967, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 g
 +                      outputs: []outputInfo{
 +                              {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
 +                      },
 +              },
 +      },
 +      {
 +              name:   "LoweredConvert",
 +              argLen: 2,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
 +                      },
 +              },
 +      },
 +      {
 +              name:   "Select",
 +              argLen: 3,
 +              asm:    wasm.ASelect,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
 +                              {1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
 +                              {2, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
 +                      },
 +              },
 +      },
 +      {
 +              name:    "I64Load8U",
 +              auxType: auxInt64,
 +              argLen:  2,
 +              asm:     wasm.AI64Load8U,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1407374883618815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
 +                      },
 +              },
 +      },
 +      {
 +              name:    "I64Load8S",
 +              auxType: auxInt64,
 +              argLen:  2,
 +              asm:     wasm.AI64Load8S,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1407374883618815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
 +                      },
 +              },
 +      },
 +      {
 +              name:    "I64Load16U",
 +              auxType: auxInt64,
 +              argLen:  2,
 +              asm:     wasm.AI64Load16U,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1407374883618815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
 +                      },
 +              },
 +      },
 +      {
 +              name:    "I64Load16S",
 +              auxType: auxInt64,
 +              argLen:  2,
 +              asm:     wasm.AI64Load16S,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1407374883618815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
 +                      },
 +              },
 +      },
 +      {
 +              name:    "I64Load32U",
 +              auxType: auxInt64,
 +              argLen:  2,
 +              asm:     wasm.AI64Load32U,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1407374883618815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
 +                      },
 +              },
 +      },
 +      {
 +              name:    "I64Load32S",
 +              auxType: auxInt64,
 +              argLen:  2,
 +              asm:     wasm.AI64Load32S,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1407374883618815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
 +                      },
 +              },
 +      },
 +      {
 +              name:    "I64Load",
 +              auxType: auxInt64,
 +              argLen:  2,
 +              asm:     wasm.AI64Load,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1407374883618815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
 +                      },
 +              },
 +      },
 +      {
 +              name:    "I64Store8",
 +              auxType: auxInt64,
 +              argLen:  3,
 +              asm:     wasm.AI64Store8,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 281474976776191},  // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
 +                              {0, 1407374883618815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP SB
 +                      },
 +              },
 +      },
 +      {
 +              name:    "I64Store16",
 +              auxType: auxInt64,
 +              argLen:  3,
 +              asm:     wasm.AI64Store16,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 281474976776191},  // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
 +                              {0, 1407374883618815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP SB
 +                      },
 +              },
 +      },
 +      {
 +              name:    "I64Store32",
 +              auxType: auxInt64,
 +              argLen:  3,
 +              asm:     wasm.AI64Store32,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 281474976776191},  // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
 +                              {0, 1407374883618815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP SB
 +                      },
 +              },
 +      },
 +      {
 +              name:    "I64Store",
 +              auxType: auxInt64,
 +              argLen:  3,
 +              asm:     wasm.AI64Store,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 281474976776191},  // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
 +                              {0, 1407374883618815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP SB
 +                      },
 +              },
 +      },
 +      {
 +              name:    "F32Load",
 +              auxType: auxInt64,
 +              argLen:  2,
 +              asm:     wasm.AF32Load,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1407374883618815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 +                      },
 +              },
 +      },
 +      {
 +              name:    "F64Load",
 +              auxType: auxInt64,
 +              argLen:  2,
 +              asm:     wasm.AF64Load,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1407374883618815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +              },
 +      },
 +      {
 +              name:    "F32Store",
 +              auxType: auxInt64,
 +              argLen:  3,
 +              asm:     wasm.AF32Store,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 4294901760},       // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 +                              {0, 1407374883618815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP SB
 +                      },
 +              },
 +      },
 +      {
 +              name:    "F64Store",
 +              auxType: auxInt64,
 +              argLen:  3,
 +              asm:     wasm.AF64Store,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 281470681743360},  // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                              {0, 1407374883618815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP SB
 +                      },
 +              },
 +      },
 +      {
 +              name:              "I64Const",
 +              auxType:           auxInt64,
 +              argLen:            0,
 +              rematerializeable: true,
 +              reg: regInfo{
 +                      outputs: []outputInfo{
 +                              {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
 +                      },
 +              },
 +      },
 +      {
 +              name:              "F32Const",
 +              auxType:           auxFloat32,
 +              argLen:            0,
 +              rematerializeable: true,
 +              reg: regInfo{
 +                      outputs: []outputInfo{
 +                              {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 +                      },
 +              },
 +      },
 +      {
 +              name:              "F64Const",
 +              auxType:           auxFloat64,
 +              argLen:            0,
 +              rematerializeable: true,
 +              reg: regInfo{
 +                      outputs: []outputInfo{
 +                              {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +              },
 +      },
 +      {
 +              name:   "I64Eqz",
 +              argLen: 1,
 +              asm:    wasm.AI64Eqz,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
 +                      },
 +              },
 +      },
 +      {
 +              name:   "I64Eq",
 +              argLen: 2,
 +              asm:    wasm.AI64Eq,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
 +                              {1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
 +                      },
 +              },
 +      },
 +      {
 +              name:   "I64Ne",
 +              argLen: 2,
 +              asm:    wasm.AI64Ne,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
 +                              {1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
 +                      },
 +              },
 +      },
 +      {
 +              name:   "I64LtS",
 +              argLen: 2,
 +              asm:    wasm.AI64LtS,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
 +                              {1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
 +                      },
 +              },
 +      },
 +      {
 +              name:   "I64LtU",
 +              argLen: 2,
 +              asm:    wasm.AI64LtU,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
 +                              {1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
 +                      },
 +              },
 +      },
 +      {
 +              name:   "I64GtS",
 +              argLen: 2,
 +              asm:    wasm.AI64GtS,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
 +                              {1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
 +                      },
 +              },
 +      },
 +      {
 +              name:   "I64GtU",
 +              argLen: 2,
 +              asm:    wasm.AI64GtU,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
 +                              {1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
 +                      },
 +              },
 +      },
 +      {
 +              name:   "I64LeS",
 +              argLen: 2,
 +              asm:    wasm.AI64LeS,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
 +                              {1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
 +                      },
 +              },
 +      },
 +      {
 +              name:   "I64LeU",
 +              argLen: 2,
 +              asm:    wasm.AI64LeU,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
 +                              {1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
 +                      },
 +              },
 +      },
 +      {
 +              name:   "I64GeS",
 +              argLen: 2,
 +              asm:    wasm.AI64GeS,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
 +                              {1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
 +                      },
 +              },
 +      },
 +      {
 +              name:   "I64GeU",
 +              argLen: 2,
 +              asm:    wasm.AI64GeU,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
 +                              {1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
 +                      },
 +              },
 +      },
 +      {
 +              name:   "F32Eq",
 +              argLen: 2,
 +              asm:    wasm.AF32Eq,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 +                              {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
 +                      },
 +              },
 +      },
 +      {
 +              name:   "F32Ne",
 +              argLen: 2,
 +              asm:    wasm.AF32Ne,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 +                              {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
 +                      },
 +              },
 +      },
 +      {
 +              name:   "F32Lt",
 +              argLen: 2,
 +              asm:    wasm.AF32Lt,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 +                              {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
 +                      },
 +              },
 +      },
 +      {
 +              name:   "F32Gt",
 +              argLen: 2,
 +              asm:    wasm.AF32Gt,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 +                              {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
 +                      },
 +              },
 +      },
 +      {
 +              name:   "F32Le",
 +              argLen: 2,
 +              asm:    wasm.AF32Le,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 +                              {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
 +                      },
 +              },
 +      },
 +      {
 +              name:   "F32Ge",
 +              argLen: 2,
 +              asm:    wasm.AF32Ge,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 +                              {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
 +                      },
 +              },
 +      },
 +      {
 +              name:   "F64Eq",
 +              argLen: 2,
 +              asm:    wasm.AF64Eq,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                              {1, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
 +                      },
 +              },
 +      },
 +      {
 +              name:   "F64Ne",
 +              argLen: 2,
 +              asm:    wasm.AF64Ne,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                              {1, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
 +                      },
 +              },
 +      },
 +      {
 +              name:   "F64Lt",
 +              argLen: 2,
 +              asm:    wasm.AF64Lt,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                              {1, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
 +                      },
 +              },
 +      },
 +      {
 +              name:   "F64Gt",
 +              argLen: 2,
 +              asm:    wasm.AF64Gt,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                              {1, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
 +                      },
 +              },
 +      },
 +      {
 +              name:   "F64Le",
 +              argLen: 2,
 +              asm:    wasm.AF64Le,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                              {1, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
 +                      },
 +              },
 +      },
 +      {
 +              name:   "F64Ge",
 +              argLen: 2,
 +              asm:    wasm.AF64Ge,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                              {1, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
 +                      },
 +              },
 +      },
 +      {
 +              name:   "I64Add",
 +              argLen: 2,
 +              asm:    wasm.AI64Add,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
 +                              {1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
 +                      },
 +              },
 +      },
 +      {
 +              name:    "I64AddConst",
 +              auxType: auxInt64,
 +              argLen:  1,
 +              asm:     wasm.AI64Add,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
 +                      },
 +              },
 +      },
 +      {
 +              name:   "I64Sub",
 +              argLen: 2,
 +              asm:    wasm.AI64Sub,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
 +                              {1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
 +                      },
 +              },
 +      },
 +      {
 +              name:   "I64Mul",
 +              argLen: 2,
 +              asm:    wasm.AI64Mul,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
 +                              {1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
 +                      },
 +              },
 +      },
 +      {
 +              name:   "I64DivS",
 +              argLen: 2,
 +              asm:    wasm.AI64DivS,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
 +                              {1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
 +                      },
 +              },
 +      },
 +      {
 +              name:   "I64DivU",
 +              argLen: 2,
 +              asm:    wasm.AI64DivU,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
 +                              {1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
 +                      },
 +              },
 +      },
 +      {
 +              name:   "I64RemS",
 +              argLen: 2,
 +              asm:    wasm.AI64RemS,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
 +                              {1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
 +                      },
 +              },
 +      },
 +      {
 +              name:   "I64RemU",
 +              argLen: 2,
 +              asm:    wasm.AI64RemU,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
 +                              {1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
 +                      },
 +              },
 +      },
 +      {
 +              name:   "I64And",
 +              argLen: 2,
 +              asm:    wasm.AI64And,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
 +                              {1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
 +                      },
 +              },
 +      },
 +      {
 +              name:   "I64Or",
 +              argLen: 2,
 +              asm:    wasm.AI64Or,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
 +                              {1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
 +                      },
 +              },
 +      },
 +      {
 +              name:   "I64Xor",
 +              argLen: 2,
 +              asm:    wasm.AI64Xor,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
 +                              {1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
 +                      },
 +              },
 +      },
 +      {
 +              name:   "I64Shl",
 +              argLen: 2,
 +              asm:    wasm.AI64Shl,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
 +                              {1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
 +                      },
 +              },
 +      },
 +      {
 +              name:   "I64ShrS",
 +              argLen: 2,
 +              asm:    wasm.AI64ShrS,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
 +                              {1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
 +                      },
 +              },
 +      },
 +      {
 +              name:   "I64ShrU",
 +              argLen: 2,
 +              asm:    wasm.AI64ShrU,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
 +                              {1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
 +                      },
 +              },
 +      },
 +      {
 +              name:   "F32Neg",
 +              argLen: 1,
 +              asm:    wasm.AF32Neg,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 +                      },
 +              },
 +      },
 +      {
 +              name:   "F32Add",
 +              argLen: 2,
 +              asm:    wasm.AF32Add,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 +                              {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 +                      },
 +              },
 +      },
 +      {
 +              name:   "F32Sub",
 +              argLen: 2,
 +              asm:    wasm.AF32Sub,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 +                              {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 +                      },
 +              },
 +      },
 +      {
 +              name:   "F32Mul",
 +              argLen: 2,
 +              asm:    wasm.AF32Mul,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 +                              {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 +                      },
 +              },
 +      },
 +      {
 +              name:   "F32Div",
 +              argLen: 2,
 +              asm:    wasm.AF32Div,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 +                              {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 +                      },
 +              },
 +      },
 +      {
 +              name:   "F64Neg",
 +              argLen: 1,
 +              asm:    wasm.AF64Neg,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +              },
 +      },
 +      {
 +              name:   "F64Add",
 +              argLen: 2,
 +              asm:    wasm.AF64Add,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                              {1, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +              },
 +      },
 +      {
 +              name:   "F64Sub",
 +              argLen: 2,
 +              asm:    wasm.AF64Sub,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                              {1, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +              },
 +      },
 +      {
 +              name:   "F64Mul",
 +              argLen: 2,
 +              asm:    wasm.AF64Mul,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                              {1, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +              },
 +      },
 +      {
 +              name:   "F64Div",
 +              argLen: 2,
 +              asm:    wasm.AF64Div,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                              {1, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +              },
 +      },
 +      {
 +              name:   "I64TruncSatF64S",
 +              argLen: 1,
 +              asm:    wasm.AI64TruncSatF64S,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
 +                      },
 +              },
 +      },
 +      {
 +              name:   "I64TruncSatF64U",
 +              argLen: 1,
 +              asm:    wasm.AI64TruncSatF64U,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
 +                      },
 +              },
 +      },
 +      {
 +              name:   "I64TruncSatF32S",
 +              argLen: 1,
 +              asm:    wasm.AI64TruncSatF32S,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
 +                      },
 +              },
 +      },
 +      {
 +              name:   "I64TruncSatF32U",
 +              argLen: 1,
 +              asm:    wasm.AI64TruncSatF32U,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
 +                      },
 +              },
 +      },
 +      {
 +              name:   "F32ConvertI64S",
 +              argLen: 1,
 +              asm:    wasm.AF32ConvertI64S,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 +                      },
 +              },
 +      },
 +      {
 +              name:   "F32ConvertI64U",
 +              argLen: 1,
 +              asm:    wasm.AF32ConvertI64U,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 +                      },
 +              },
 +      },
 +      {
 +              name:   "F64ConvertI64S",
 +              argLen: 1,
 +              asm:    wasm.AF64ConvertI64S,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +              },
 +      },
 +      {
 +              name:   "F64ConvertI64U",
 +              argLen: 1,
 +              asm:    wasm.AF64ConvertI64U,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +              },
 +      },
 +      {
 +              name:   "F32DemoteF64",
 +              argLen: 1,
 +              asm:    wasm.AF32DemoteF64,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 +                      },
 +              },
 +      },
 +      {
 +              name:   "F64PromoteF32",
 +              argLen: 1,
 +              asm:    wasm.AF64PromoteF32,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +              },
 +      },
 +      {
 +              name:   "I64Extend8S",
 +              argLen: 1,
 +              asm:    wasm.AI64Extend8S,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
 +                      },
 +              },
 +      },
 +      {
 +              name:   "I64Extend16S",
 +              argLen: 1,
 +              asm:    wasm.AI64Extend16S,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
 +                      },
 +              },
 +      },
 +      {
 +              name:   "I64Extend32S",
 +              argLen: 1,
 +              asm:    wasm.AI64Extend32S,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
 +                      },
 +              },
 +      },
 +      {
 +              name:   "F32Sqrt",
 +              argLen: 1,
 +              asm:    wasm.AF32Sqrt,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 +                      },
 +              },
 +      },
 +      {
 +              name:   "F32Trunc",
 +              argLen: 1,
 +              asm:    wasm.AF32Trunc,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 +                      },
 +              },
 +      },
 +      {
 +              name:   "F32Ceil",
 +              argLen: 1,
 +              asm:    wasm.AF32Ceil,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 +                      },
 +              },
 +      },
 +      {
 +              name:   "F32Floor",
 +              argLen: 1,
 +              asm:    wasm.AF32Floor,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 +                      },
 +              },
 +      },
 +      {
 +              name:   "F32Nearest",
 +              argLen: 1,
 +              asm:    wasm.AF32Nearest,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 +                      },
 +              },
 +      },
 +      {
 +              name:   "F32Abs",
 +              argLen: 1,
 +              asm:    wasm.AF32Abs,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 +                      },
 +              },
 +      },
 +      {
 +              name:   "F32Copysign",
 +              argLen: 2,
 +              asm:    wasm.AF32Copysign,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 +                              {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 +                      },
 +              },
 +      },
 +      {
 +              name:   "F64Sqrt",
 +              argLen: 1,
 +              asm:    wasm.AF64Sqrt,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +              },
 +      },
 +      {
 +              name:   "F64Trunc",
 +              argLen: 1,
 +              asm:    wasm.AF64Trunc,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +              },
 +      },
 +      {
 +              name:   "F64Ceil",
 +              argLen: 1,
 +              asm:    wasm.AF64Ceil,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +              },
 +      },
 +      {
 +              name:   "F64Floor",
 +              argLen: 1,
 +              asm:    wasm.AF64Floor,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +              },
 +      },
 +      {
 +              name:   "F64Nearest",
 +              argLen: 1,
 +              asm:    wasm.AF64Nearest,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +              },
 +      },
 +      {
 +              name:   "F64Abs",
 +              argLen: 1,
 +              asm:    wasm.AF64Abs,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +              },
 +      },
 +      {
 +              name:   "F64Copysign",
 +              argLen: 2,
 +              asm:    wasm.AF64Copysign,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                              {1, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +              },
 +      },
 +      {
 +              name:   "I64Ctz",
 +              argLen: 1,
 +              asm:    wasm.AI64Ctz,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
 +                      },
 +              },
 +      },
 +      {
 +              name:   "I64Clz",
 +              argLen: 1,
 +              asm:    wasm.AI64Clz,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
 +                      },
 +              },
 +      },
 +      {
 +              name:   "I32Rotl",
 +              argLen: 2,
 +              asm:    wasm.AI32Rotl,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
 +                              {1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
 +                      },
 +              },
 +      },
 +      {
 +              name:   "I64Rotl",
 +              argLen: 2,
 +              asm:    wasm.AI64Rotl,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
 +                              {1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
 +                      },
 +              },
 +      },
 +      {
 +              name:   "I64Popcnt",
 +              argLen: 1,
 +              asm:    wasm.AI64Popcnt,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
 +                      },
 +              },
 +      },
 +
 +      {
 +              name:        "Add8",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "Add16",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "Add32",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "Add64",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:    "AddPtr",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:        "Add32F",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "Add64F",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:    "Sub8",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "Sub16",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "Sub32",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "Sub64",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "SubPtr",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "Sub32F",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "Sub64F",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:        "Mul8",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "Mul16",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "Mul32",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "Mul64",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "Mul32F",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "Mul64F",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:    "Div32F",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "Div64F",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:        "Hmul32",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "Hmul32u",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "Hmul64",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "Hmul64u",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "Mul32uhilo",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "Mul64uhilo",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "Mul32uover",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "Mul64uover",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:    "Avg32u",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "Avg64u",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "Div8",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "Div8u",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "Div16",
 +              auxType: auxBool,
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "Div16u",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "Div32",
 +              auxType: auxBool,
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "Div32u",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "Div64",
 +              auxType: auxBool,
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "Div64u",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "Div128u",
 +              argLen:  3,
 +              generic: true,
 +      },
 +      {
 +              name:    "Mod8",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "Mod8u",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "Mod16",
 +              auxType: auxBool,
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "Mod16u",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "Mod32",
 +              auxType: auxBool,
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "Mod32u",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "Mod64",
 +              auxType: auxBool,
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "Mod64u",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:        "And8",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "And16",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "And32",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "And64",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "Or8",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "Or16",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "Or32",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "Or64",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "Xor8",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "Xor16",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "Xor32",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "Xor64",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:    "Lsh8x8",
 +              auxType: auxBool,
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "Lsh8x16",
 +              auxType: auxBool,
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "Lsh8x32",
 +              auxType: auxBool,
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "Lsh8x64",
 +              auxType: auxBool,
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "Lsh16x8",
 +              auxType: auxBool,
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "Lsh16x16",
 +              auxType: auxBool,
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "Lsh16x32",
 +              auxType: auxBool,
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "Lsh16x64",
 +              auxType: auxBool,
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "Lsh32x8",
 +              auxType: auxBool,
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "Lsh32x16",
 +              auxType: auxBool,
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "Lsh32x32",
 +              auxType: auxBool,
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "Lsh32x64",
 +              auxType: auxBool,
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "Lsh64x8",
 +              auxType: auxBool,
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "Lsh64x16",
 +              auxType: auxBool,
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "Lsh64x32",
 +              auxType: auxBool,
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "Lsh64x64",
 +              auxType: auxBool,
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "Rsh8x8",
 +              auxType: auxBool,
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "Rsh8x16",
 +              auxType: auxBool,
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "Rsh8x32",
 +              auxType: auxBool,
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "Rsh8x64",
 +              auxType: auxBool,
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "Rsh16x8",
 +              auxType: auxBool,
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "Rsh16x16",
 +              auxType: auxBool,
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "Rsh16x32",
 +              auxType: auxBool,
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "Rsh16x64",
 +              auxType: auxBool,
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "Rsh32x8",
 +              auxType: auxBool,
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "Rsh32x16",
 +              auxType: auxBool,
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "Rsh32x32",
 +              auxType: auxBool,
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "Rsh32x64",
 +              auxType: auxBool,
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "Rsh64x8",
 +              auxType: auxBool,
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "Rsh64x16",
 +              auxType: auxBool,
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "Rsh64x32",
 +              auxType: auxBool,
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "Rsh64x64",
 +              auxType: auxBool,
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "Rsh8Ux8",
 +              auxType: auxBool,
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "Rsh8Ux16",
 +              auxType: auxBool,
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "Rsh8Ux32",
 +              auxType: auxBool,
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "Rsh8Ux64",
 +              auxType: auxBool,
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "Rsh16Ux8",
 +              auxType: auxBool,
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "Rsh16Ux16",
 +              auxType: auxBool,
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "Rsh16Ux32",
 +              auxType: auxBool,
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "Rsh16Ux64",
 +              auxType: auxBool,
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "Rsh32Ux8",
 +              auxType: auxBool,
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "Rsh32Ux16",
 +              auxType: auxBool,
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "Rsh32Ux32",
 +              auxType: auxBool,
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "Rsh32Ux64",
 +              auxType: auxBool,
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "Rsh64Ux8",
 +              auxType: auxBool,
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "Rsh64Ux16",
 +              auxType: auxBool,
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "Rsh64Ux32",
 +              auxType: auxBool,
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "Rsh64Ux64",
 +              auxType: auxBool,
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:        "Eq8",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "Eq16",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "Eq32",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "Eq64",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "EqPtr",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:    "EqInter",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "EqSlice",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:        "Eq32F",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "Eq64F",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "Neq8",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "Neq16",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "Neq32",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "Neq64",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "NeqPtr",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:    "NeqInter",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "NeqSlice",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:        "Neq32F",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "Neq64F",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:    "Less8",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "Less8U",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "Less16",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "Less16U",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "Less32",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "Less32U",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "Less64",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "Less64U",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "Less32F",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "Less64F",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "Leq8",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "Leq8U",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "Leq16",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "Leq16U",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "Leq32",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "Leq32U",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "Leq64",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "Leq64U",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "Leq32F",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "Leq64F",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "CondSelect",
 +              argLen:  3,
 +              generic: true,
 +      },
 +      {
 +              name:        "AndB",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "OrB",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "EqB",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "NeqB",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:    "Not",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "Neg8",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "Neg16",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "Neg32",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "Neg64",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "Neg32F",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "Neg64F",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "Com8",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "Com16",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "Com32",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "Com64",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "Ctz8",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "Ctz16",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "Ctz32",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "Ctz64",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "Ctz64On32",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "Ctz8NonZero",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "Ctz16NonZero",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "Ctz32NonZero",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "Ctz64NonZero",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "BitLen8",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "BitLen16",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "BitLen32",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "BitLen64",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "Bswap16",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "Bswap32",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "Bswap64",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "BitRev8",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "BitRev16",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "BitRev32",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "BitRev64",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "PopCount8",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "PopCount16",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "PopCount32",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "PopCount64",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "RotateLeft64",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "RotateLeft32",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "RotateLeft16",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "RotateLeft8",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "Sqrt",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "Sqrt32",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "Floor",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "Ceil",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "Trunc",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "Round",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "RoundToEven",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "Abs",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "Copysign",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "Min64",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "Max64",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "Min64u",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "Max64u",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "Min64F",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "Min32F",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "Max64F",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "Max32F",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "FMA",
 +              argLen:  3,
 +              generic: true,
 +      },
 +      {
 +              name:      "Phi",
 +              argLen:    -1,
 +              zeroWidth: true,
 +              generic:   true,
 +      },
 +      {
 +              name:    "Copy",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:         "Convert",
 +              argLen:       2,
 +              resultInArg0: true,
 +              zeroWidth:    true,
 +              generic:      true,
 +      },
 +      {
 +              name:    "ConstBool",
 +              auxType: auxBool,
 +              argLen:  0,
 +              generic: true,
 +      },
 +      {
 +              name:    "ConstString",
 +              auxType: auxString,
 +              argLen:  0,
 +              generic: true,
 +      },
 +      {
 +              name:    "ConstNil",
 +              argLen:  0,
 +              generic: true,
 +      },
 +      {
 +              name:    "Const8",
 +              auxType: auxInt8,
 +              argLen:  0,
 +              generic: true,
 +      },
 +      {
 +              name:    "Const16",
 +              auxType: auxInt16,
 +              argLen:  0,
 +              generic: true,
 +      },
 +      {
 +              name:    "Const32",
 +              auxType: auxInt32,
 +              argLen:  0,
 +              generic: true,
 +      },
 +      {
 +              name:    "Const64",
 +              auxType: auxInt64,
 +              argLen:  0,
 +              generic: true,
 +      },
 +      {
 +              name:    "Const32F",
 +              auxType: auxFloat32,
 +              argLen:  0,
 +              generic: true,
 +      },
 +      {
 +              name:    "Const64F",
 +              auxType: auxFloat64,
 +              argLen:  0,
 +              generic: true,
 +      },
 +      {
 +              name:    "ConstInterface",
 +              argLen:  0,
 +              generic: true,
 +      },
 +      {
 +              name:    "ConstSlice",
 +              argLen:  0,
 +              generic: true,
 +      },
 +      {
 +              name:      "InitMem",
 +              argLen:    0,
 +              zeroWidth: true,
 +              generic:   true,
 +      },
 +      {
 +              name:      "Arg",
 +              auxType:   auxSymOff,
 +              argLen:    0,
 +              zeroWidth: true,
 +              symEffect: SymRead,
 +              generic:   true,
 +      },
 +      {
 +              name:      "ArgIntReg",
 +              auxType:   auxNameOffsetInt8,
 +              argLen:    0,
 +              zeroWidth: true,
 +              generic:   true,
 +      },
 +      {
 +              name:      "ArgFloatReg",
 +              auxType:   auxNameOffsetInt8,
 +              argLen:    0,
 +              zeroWidth: true,
 +              generic:   true,
 +      },
 +      {
 +              name:      "Addr",
 +              auxType:   auxSym,
 +              argLen:    1,
 +              symEffect: SymAddr,
 +              generic:   true,
 +      },
 +      {
 +              name:      "LocalAddr",
 +              auxType:   auxSym,
 +              argLen:    2,
 +              symEffect: SymAddr,
 +              generic:   true,
 +      },
 +      {
 +              name:      "SP",
 +              argLen:    0,
 +              zeroWidth: true,
 +              fixedReg:  true,
 +              generic:   true,
 +      },
 +      {
 +              name:      "SB",
 +              argLen:    0,
 +              zeroWidth: true,
 +              fixedReg:  true,
 +              generic:   true,
 +      },
 +      {
 +              name:      "SPanchored",
 +              argLen:    2,
 +              zeroWidth: true,
 +              generic:   true,
 +      },
 +      {
 +              name:    "Load",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "Dereference",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "Store",
 +              auxType: auxTyp,
 +              argLen:  3,
 +              generic: true,
 +      },
 +      {
 +              name:    "LoadMasked8",
 +              argLen:  3,
 +              generic: true,
 +      },
 +      {
 +              name:    "LoadMasked16",
 +              argLen:  3,
 +              generic: true,
 +      },
 +      {
 +              name:    "LoadMasked32",
 +              argLen:  3,
 +              generic: true,
 +      },
 +      {
 +              name:    "LoadMasked64",
 +              argLen:  3,
 +              generic: true,
 +      },
 +      {
 +              name:    "StoreMasked8",
 +              auxType: auxTyp,
 +              argLen:  4,
 +              generic: true,
 +      },
 +      {
 +              name:    "StoreMasked16",
 +              auxType: auxTyp,
 +              argLen:  4,
 +              generic: true,
 +      },
 +      {
 +              name:    "StoreMasked32",
 +              auxType: auxTyp,
 +              argLen:  4,
 +              generic: true,
 +      },
 +      {
 +              name:    "StoreMasked64",
 +              auxType: auxTyp,
 +              argLen:  4,
 +              generic: true,
 +      },
 +      {
 +              name:    "Move",
 +              auxType: auxTypSize,
 +              argLen:  3,
 +              generic: true,
 +      },
 +      {
 +              name:    "Zero",
 +              auxType: auxTypSize,
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "StoreWB",
 +              auxType: auxTyp,
 +              argLen:  3,
 +              generic: true,
 +      },
 +      {
 +              name:    "MoveWB",
 +              auxType: auxTypSize,
 +              argLen:  3,
 +              generic: true,
 +      },
 +      {
 +              name:    "ZeroWB",
 +              auxType: auxTypSize,
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "WBend",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "WB",
 +              auxType: auxInt64,
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:      "HasCPUFeature",
 +              auxType:   auxSym,
 +              argLen:    0,
 +              symEffect: SymNone,
 +              generic:   true,
 +      },
 +      {
 +              name:    "PanicBounds",
 +              auxType: auxInt64,
 +              argLen:  3,
 +              call:    true,
 +              generic: true,
 +      },
 +      {
 +              name:    "PanicExtend",
 +              auxType: auxInt64,
 +              argLen:  4,
 +              call:    true,
 +              generic: true,
 +      },
 +      {
 +              name:    "ClosureCall",
 +              auxType: auxCallOff,
 +              argLen:  -1,
 +              call:    true,
 +              generic: true,
 +      },
 +      {
 +              name:    "StaticCall",
 +              auxType: auxCallOff,
 +              argLen:  -1,
 +              call:    true,
 +              generic: true,
 +      },
 +      {
 +              name:    "InterCall",
 +              auxType: auxCallOff,
 +              argLen:  -1,
 +              call:    true,
 +              generic: true,
 +      },
 +      {
 +              name:    "TailCall",
 +              auxType: auxCallOff,
 +              argLen:  -1,
 +              call:    true,
 +              generic: true,
 +      },
 +      {
 +              name:    "ClosureLECall",
 +              auxType: auxCallOff,
 +              argLen:  -1,
 +              call:    true,
 +              generic: true,
 +      },
 +      {
 +              name:    "StaticLECall",
 +              auxType: auxCallOff,
 +              argLen:  -1,
 +              call:    true,
 +              generic: true,
 +      },
 +      {
 +              name:    "InterLECall",
 +              auxType: auxCallOff,
 +              argLen:  -1,
 +              call:    true,
 +              generic: true,
 +      },
 +      {
 +              name:    "TailLECall",
 +              auxType: auxCallOff,
 +              argLen:  -1,
 +              call:    true,
 +              generic: true,
 +      },
 +      {
 +              name:    "SignExt8to16",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "SignExt8to32",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "SignExt8to64",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "SignExt16to32",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "SignExt16to64",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "SignExt32to64",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "ZeroExt8to16",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "ZeroExt8to32",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "ZeroExt8to64",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "ZeroExt16to32",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "ZeroExt16to64",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "ZeroExt32to64",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "Trunc16to8",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "Trunc32to8",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "Trunc32to16",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "Trunc64to8",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "Trunc64to16",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "Trunc64to32",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "Cvt32to32F",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "Cvt32to64F",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "Cvt64to32F",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "Cvt64to64F",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "Cvt32Fto32",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "Cvt32Fto64",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "Cvt64Fto32",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "Cvt64Fto64",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "Cvt32Fto64F",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "Cvt64Fto32F",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "CvtBoolToUint8",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "Round32F",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "Round64F",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "IsNonNil",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "IsInBounds",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "IsSliceInBounds",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:     "NilCheck",
 +              argLen:   2,
 +              nilCheck: true,
 +              generic:  true,
 +      },
 +      {
 +              name:      "GetG",
 +              argLen:    1,
 +              zeroWidth: true,
 +              generic:   true,
 +      },
 +      {
 +              name:    "GetClosurePtr",
 +              argLen:  0,
 +              generic: true,
 +      },
 +      {
 +              name:    "GetCallerPC",
 +              argLen:  0,
 +              generic: true,
 +      },
 +      {
 +              name:    "GetCallerSP",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "PtrIndex",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "OffPtr",
 +              auxType: auxInt64,
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "SliceMake",
 +              argLen:  3,
 +              generic: true,
 +      },
 +      {
 +              name:    "SlicePtr",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "SliceLen",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "SliceCap",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "SlicePtrUnchecked",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "ComplexMake",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "ComplexReal",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "ComplexImag",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "StringMake",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "StringPtr",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "StringLen",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "IMake",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "ITab",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "IData",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "StructMake",
 +              argLen:  -1,
 +              generic: true,
 +      },
 +      {
 +              name:    "StructSelect",
 +              auxType: auxInt64,
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "ArrayMake0",
 +              argLen:  0,
 +              generic: true,
 +      },
 +      {
 +              name:    "ArrayMake1",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "ArraySelect",
 +              auxType: auxInt64,
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "StoreReg",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "LoadReg",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:      "FwdRef",
 +              auxType:   auxSym,
 +              argLen:    0,
 +              symEffect: SymNone,
 +              generic:   true,
 +      },
 +      {
 +              name:    "Unknown",
 +              argLen:  0,
 +              generic: true,
 +      },
 +      {
 +              name:      "VarDef",
 +              auxType:   auxSym,
 +              argLen:    1,
 +              zeroWidth: true,
 +              symEffect: SymNone,
 +              generic:   true,
 +      },
 +      {
 +              name:      "VarLive",
 +              auxType:   auxSym,
 +              argLen:    1,
 +              zeroWidth: true,
 +              symEffect: SymRead,
 +              generic:   true,
 +      },
 +      {
 +              name:      "KeepAlive",
 +              argLen:    2,
 +              zeroWidth: true,
 +              generic:   true,
 +      },
 +      {
 +              name:    "InlMark",
 +              auxType: auxInt32,
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "Int64Make",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "Int64Hi",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "Int64Lo",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:        "Add32carry",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "Add32withcarry",
 +              argLen:      3,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:    "Sub32carry",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "Sub32withcarry",
 +              argLen:  3,
 +              generic: true,
 +      },
 +      {
 +              name:        "Add64carry",
 +              argLen:      3,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:    "Sub64borrow",
 +              argLen:  3,
 +              generic: true,
 +      },
 +      {
 +              name:    "Signmask",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "Zeromask",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "Slicemask",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "SpectreIndex",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "SpectreSliceIndex",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "Cvt32Uto32F",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "Cvt32Uto64F",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "Cvt32Fto32U",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "Cvt64Fto32U",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "Cvt64Uto32F",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "Cvt64Uto64F",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "Cvt32Fto64U",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "Cvt64Fto64U",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:      "Select0",
 +              argLen:    1,
 +              zeroWidth: true,
 +              generic:   true,
 +      },
 +      {
 +              name:      "Select1",
 +              argLen:    1,
 +              zeroWidth: true,
 +              generic:   true,
 +      },
 +      {
 +              name:    "MakeTuple",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "SelectN",
 +              auxType: auxInt64,
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "SelectNAddr",
 +              auxType: auxInt64,
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "MakeResult",
 +              argLen:  -1,
 +              generic: true,
 +      },
 +      {
 +              name:    "AtomicLoad8",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "AtomicLoad32",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "AtomicLoad64",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "AtomicLoadPtr",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "AtomicLoadAcq32",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "AtomicLoadAcq64",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:           "AtomicStore8",
 +              argLen:         3,
 +              hasSideEffects: true,
 +              generic:        true,
 +      },
 +      {
 +              name:           "AtomicStore32",
 +              argLen:         3,
 +              hasSideEffects: true,
 +              generic:        true,
 +      },
 +      {
 +              name:           "AtomicStore64",
 +              argLen:         3,
 +              hasSideEffects: true,
 +              generic:        true,
 +      },
 +      {
 +              name:           "AtomicStorePtrNoWB",
 +              argLen:         3,
 +              hasSideEffects: true,
 +              generic:        true,
 +      },
 +      {
 +              name:           "AtomicStoreRel32",
 +              argLen:         3,
 +              hasSideEffects: true,
 +              generic:        true,
 +      },
 +      {
 +              name:           "AtomicStoreRel64",
 +              argLen:         3,
 +              hasSideEffects: true,
 +              generic:        true,
 +      },
 +      {
 +              name:           "AtomicExchange8",
 +              argLen:         3,
 +              hasSideEffects: true,
 +              generic:        true,
 +      },
 +      {
 +              name:           "AtomicExchange32",
 +              argLen:         3,
 +              hasSideEffects: true,
 +              generic:        true,
 +      },
 +      {
 +              name:           "AtomicExchange64",
 +              argLen:         3,
 +              hasSideEffects: true,
 +              generic:        true,
 +      },
 +      {
 +              name:           "AtomicAdd32",
 +              argLen:         3,
 +              hasSideEffects: true,
 +              generic:        true,
 +      },
 +      {
 +              name:           "AtomicAdd64",
 +              argLen:         3,
 +              hasSideEffects: true,
 +              generic:        true,
 +      },
 +      {
 +              name:           "AtomicCompareAndSwap32",
 +              argLen:         4,
 +              hasSideEffects: true,
 +              generic:        true,
 +      },
 +      {
 +              name:           "AtomicCompareAndSwap64",
 +              argLen:         4,
 +              hasSideEffects: true,
 +              generic:        true,
 +      },
 +      {
 +              name:           "AtomicCompareAndSwapRel32",
 +              argLen:         4,
 +              hasSideEffects: true,
 +              generic:        true,
 +      },
 +      {
 +              name:           "AtomicAnd8",
 +              argLen:         3,
 +              hasSideEffects: true,
 +              generic:        true,
 +      },
 +      {
 +              name:           "AtomicOr8",
 +              argLen:         3,
 +              hasSideEffects: true,
 +              generic:        true,
 +      },
 +      {
 +              name:           "AtomicAnd32",
 +              argLen:         3,
 +              hasSideEffects: true,
 +              generic:        true,
 +      },
 +      {
 +              name:           "AtomicOr32",
 +              argLen:         3,
 +              hasSideEffects: true,
 +              generic:        true,
 +      },
 +      {
 +              name:           "AtomicAnd64value",
 +              argLen:         3,
 +              hasSideEffects: true,
 +              generic:        true,
 +      },
 +      {
 +              name:           "AtomicAnd32value",
 +              argLen:         3,
 +              hasSideEffects: true,
 +              generic:        true,
 +      },
 +      {
 +              name:           "AtomicAnd8value",
 +              argLen:         3,
 +              hasSideEffects: true,
 +              generic:        true,
 +      },
 +      {
 +              name:           "AtomicOr64value",
 +              argLen:         3,
 +              hasSideEffects: true,
 +              generic:        true,
 +      },
 +      {
 +              name:           "AtomicOr32value",
 +              argLen:         3,
 +              hasSideEffects: true,
 +              generic:        true,
 +      },
 +      {
 +              name:           "AtomicOr8value",
 +              argLen:         3,
 +              hasSideEffects: true,
 +              generic:        true,
 +      },
 +      {
 +              name:           "AtomicStore8Variant",
 +              argLen:         3,
 +              hasSideEffects: true,
 +              generic:        true,
 +      },
 +      {
 +              name:           "AtomicStore32Variant",
 +              argLen:         3,
 +              hasSideEffects: true,
 +              generic:        true,
 +      },
 +      {
 +              name:           "AtomicStore64Variant",
 +              argLen:         3,
 +              hasSideEffects: true,
 +              generic:        true,
 +      },
 +      {
 +              name:           "AtomicAdd32Variant",
 +              argLen:         3,
 +              hasSideEffects: true,
 +              generic:        true,
 +      },
 +      {
 +              name:           "AtomicAdd64Variant",
 +              argLen:         3,
 +              hasSideEffects: true,
 +              generic:        true,
 +      },
 +      {
 +              name:           "AtomicExchange8Variant",
 +              argLen:         3,
 +              hasSideEffects: true,
 +              generic:        true,
 +      },
 +      {
 +              name:           "AtomicExchange32Variant",
 +              argLen:         3,
 +              hasSideEffects: true,
 +              generic:        true,
 +      },
 +      {
 +              name:           "AtomicExchange64Variant",
 +              argLen:         3,
 +              hasSideEffects: true,
 +              generic:        true,
 +      },
 +      {
 +              name:           "AtomicCompareAndSwap32Variant",
 +              argLen:         4,
 +              hasSideEffects: true,
 +              generic:        true,
 +      },
 +      {
 +              name:           "AtomicCompareAndSwap64Variant",
 +              argLen:         4,
 +              hasSideEffects: true,
 +              generic:        true,
 +      },
 +      {
 +              name:           "AtomicAnd64valueVariant",
 +              argLen:         3,
 +              hasSideEffects: true,
 +              generic:        true,
 +      },
 +      {
 +              name:           "AtomicOr64valueVariant",
 +              argLen:         3,
 +              hasSideEffects: true,
 +              generic:        true,
 +      },
 +      {
 +              name:           "AtomicAnd32valueVariant",
 +              argLen:         3,
 +              hasSideEffects: true,
 +              generic:        true,
 +      },
 +      {
 +              name:           "AtomicOr32valueVariant",
 +              argLen:         3,
 +              hasSideEffects: true,
 +              generic:        true,
 +      },
 +      {
 +              name:           "AtomicAnd8valueVariant",
 +              argLen:         3,
 +              hasSideEffects: true,
 +              generic:        true,
 +      },
 +      {
 +              name:           "AtomicOr8valueVariant",
 +              argLen:         3,
 +              hasSideEffects: true,
 +              generic:        true,
 +      },
 +      {
 +              name:           "PubBarrier",
 +              argLen:         1,
 +              hasSideEffects: true,
 +              generic:        true,
 +      },
 +      {
 +              name:      "Clobber",
 +              auxType:   auxSymOff,
 +              argLen:    0,
 +              symEffect: SymNone,
 +              generic:   true,
 +      },
 +      {
 +              name:    "ClobberReg",
 +              argLen:  0,
 +              generic: true,
 +      },
 +      {
 +              name:           "PrefetchCache",
 +              argLen:         2,
 +              hasSideEffects: true,
 +              generic:        true,
 +      },
 +      {
 +              name:           "PrefetchCacheStreamed",
 +              argLen:         2,
 +              hasSideEffects: true,
 +              generic:        true,
 +      },
 +      {
 +              name:    "Add32x4",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "ZeroSIMD",
 +              argLen:  0,
 +              generic: true,
 +      },
 +      {
 +              name:    "LoadMask8x16",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "LoadMask8x32",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "LoadMask8x64",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "LoadMask16x8",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "LoadMask16x16",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "LoadMask16x32",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "LoadMask32x4",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "LoadMask32x8",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "LoadMask32x16",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "LoadMask64x2",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "LoadMask64x4",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "LoadMask64x8",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "StoreMask8x16",
 +              auxType: auxTyp,
 +              argLen:  3,
 +              generic: true,
 +      },
 +      {
 +              name:    "StoreMask8x32",
 +              auxType: auxTyp,
 +              argLen:  3,
 +              generic: true,
 +      },
 +      {
 +              name:    "StoreMask8x64",
 +              auxType: auxTyp,
 +              argLen:  3,
 +              generic: true,
 +      },
 +      {
 +              name:    "StoreMask16x8",
 +              auxType: auxTyp,
 +              argLen:  3,
 +              generic: true,
 +      },
 +      {
 +              name:    "StoreMask16x16",
 +              auxType: auxTyp,
 +              argLen:  3,
 +              generic: true,
 +      },
 +      {
 +              name:    "StoreMask16x32",
 +              auxType: auxTyp,
 +              argLen:  3,
 +              generic: true,
 +      },
 +      {
 +              name:    "StoreMask32x4",
 +              auxType: auxTyp,
 +              argLen:  3,
 +              generic: true,
 +      },
 +      {
 +              name:    "StoreMask32x8",
 +              auxType: auxTyp,
 +              argLen:  3,
 +              generic: true,
 +      },
 +      {
 +              name:    "StoreMask32x16",
 +              auxType: auxTyp,
 +              argLen:  3,
 +              generic: true,
 +      },
 +      {
 +              name:    "StoreMask64x2",
 +              auxType: auxTyp,
 +              argLen:  3,
 +              generic: true,
 +      },
 +      {
 +              name:    "StoreMask64x4",
 +              auxType: auxTyp,
 +              argLen:  3,
 +              generic: true,
 +      },
 +      {
 +              name:    "StoreMask64x8",
 +              auxType: auxTyp,
 +              argLen:  3,
 +              generic: true,
 +      },
 +      {
 +              name:    "Cvt16toMask8x16",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "Cvt32toMask8x32",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "Cvt64toMask8x64",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "Cvt8toMask16x8",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "Cvt16toMask16x16",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "Cvt32toMask16x32",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "Cvt8toMask32x4",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "Cvt8toMask32x8",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "Cvt16toMask32x16",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "Cvt8toMask64x2",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "Cvt8toMask64x4",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "Cvt8toMask64x8",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "CvtMask8x16to16",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "CvtMask8x32to32",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "CvtMask8x64to64",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "CvtMask16x8to8",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "CvtMask16x16to16",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "CvtMask16x32to32",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "CvtMask32x4to8",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "CvtMask32x8to8",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "CvtMask32x16to16",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "CvtMask64x2to8",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "CvtMask64x4to8",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "CvtMask64x8to8",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "AbsInt8x16",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "AbsInt8x32",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "AbsInt8x64",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "AbsInt16x8",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "AbsInt16x16",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "AbsInt16x32",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "AbsInt32x4",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "AbsInt32x8",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "AbsInt32x16",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "AbsInt64x2",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "AbsInt64x4",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "AbsInt64x8",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "AbsMaskedInt8x16",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "AbsMaskedInt8x32",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "AbsMaskedInt8x64",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "AbsMaskedInt16x8",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "AbsMaskedInt16x16",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "AbsMaskedInt16x32",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "AbsMaskedInt32x4",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "AbsMaskedInt32x8",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "AbsMaskedInt32x16",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "AbsMaskedInt64x2",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "AbsMaskedInt64x4",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "AbsMaskedInt64x8",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "AddDotProdPairsSaturatedInt32x4",
 +              argLen:  3,
 +              generic: true,
 +      },
 +      {
 +              name:    "AddDotProdPairsSaturatedInt32x8",
 +              argLen:  3,
 +              generic: true,
 +      },
 +      {
 +              name:    "AddDotProdPairsSaturatedInt32x16",
 +              argLen:  3,
 +              generic: true,
 +      },
 +      {
 +              name:    "AddDotProdPairsSaturatedMaskedInt32x4",
 +              argLen:  4,
 +              generic: true,
 +      },
 +      {
 +              name:    "AddDotProdPairsSaturatedMaskedInt32x8",
 +              argLen:  4,
 +              generic: true,
 +      },
 +      {
 +              name:    "AddDotProdPairsSaturatedMaskedInt32x16",
 +              argLen:  4,
 +              generic: true,
 +      },
 +      {
 +              name:    "AddDotProdQuadrupleInt32x4",
 +              argLen:  3,
 +              generic: true,
 +      },
 +      {
 +              name:    "AddDotProdQuadrupleInt32x8",
 +              argLen:  3,
 +              generic: true,
 +      },
 +      {
 +              name:    "AddDotProdQuadrupleInt32x16",
 +              argLen:  3,
 +              generic: true,
 +      },
 +      {
 +              name:    "AddDotProdQuadrupleMaskedInt32x4",
 +              argLen:  4,
 +              generic: true,
 +      },
 +      {
 +              name:    "AddDotProdQuadrupleMaskedInt32x8",
 +              argLen:  4,
 +              generic: true,
 +      },
 +      {
 +              name:    "AddDotProdQuadrupleMaskedInt32x16",
 +              argLen:  4,
 +              generic: true,
 +      },
 +      {
 +              name:    "AddDotProdQuadrupleSaturatedInt32x4",
 +              argLen:  3,
 +              generic: true,
 +      },
 +      {
 +              name:    "AddDotProdQuadrupleSaturatedInt32x8",
 +              argLen:  3,
 +              generic: true,
 +      },
 +      {
 +              name:    "AddDotProdQuadrupleSaturatedInt32x16",
 +              argLen:  3,
 +              generic: true,
 +      },
 +      {
 +              name:    "AddDotProdQuadrupleSaturatedMaskedInt32x4",
 +              argLen:  4,
 +              generic: true,
 +      },
 +      {
 +              name:    "AddDotProdQuadrupleSaturatedMaskedInt32x8",
 +              argLen:  4,
 +              generic: true,
 +      },
 +      {
 +              name:    "AddDotProdQuadrupleSaturatedMaskedInt32x16",
 +              argLen:  4,
 +              generic: true,
 +      },
 +      {
 +              name:        "AddFloat32x4",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "AddFloat32x8",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "AddFloat32x16",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "AddFloat64x2",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "AddFloat64x4",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "AddFloat64x8",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "AddInt8x16",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "AddInt8x32",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "AddInt8x64",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "AddInt16x8",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "AddInt16x16",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "AddInt16x32",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "AddInt32x4",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "AddInt32x8",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "AddInt32x16",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "AddInt64x2",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "AddInt64x4",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "AddInt64x8",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "AddMaskedFloat32x4",
 +              argLen:      3,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "AddMaskedFloat32x8",
 +              argLen:      3,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "AddMaskedFloat32x16",
 +              argLen:      3,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "AddMaskedFloat64x2",
 +              argLen:      3,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "AddMaskedFloat64x4",
 +              argLen:      3,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "AddMaskedFloat64x8",
 +              argLen:      3,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "AddMaskedInt8x16",
 +              argLen:      3,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "AddMaskedInt8x32",
 +              argLen:      3,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "AddMaskedInt8x64",
 +              argLen:      3,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "AddMaskedInt16x8",
 +              argLen:      3,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "AddMaskedInt16x16",
 +              argLen:      3,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "AddMaskedInt16x32",
 +              argLen:      3,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "AddMaskedInt32x4",
 +              argLen:      3,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "AddMaskedInt32x8",
 +              argLen:      3,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "AddMaskedInt32x16",
 +              argLen:      3,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "AddMaskedInt64x2",
 +              argLen:      3,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "AddMaskedInt64x4",
 +              argLen:      3,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "AddMaskedInt64x8",
 +              argLen:      3,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "AddMaskedUint8x16",
 +              argLen:      3,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "AddMaskedUint8x32",
 +              argLen:      3,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "AddMaskedUint8x64",
 +              argLen:      3,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "AddMaskedUint16x8",
 +              argLen:      3,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "AddMaskedUint16x16",
 +              argLen:      3,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "AddMaskedUint16x32",
 +              argLen:      3,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "AddMaskedUint32x4",
 +              argLen:      3,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "AddMaskedUint32x8",
 +              argLen:      3,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "AddMaskedUint32x16",
 +              argLen:      3,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "AddMaskedUint64x2",
 +              argLen:      3,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "AddMaskedUint64x4",
 +              argLen:      3,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "AddMaskedUint64x8",
 +              argLen:      3,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:    "AddPairsFloat32x4",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "AddPairsFloat32x8",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "AddPairsFloat64x2",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "AddPairsFloat64x4",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "AddPairsInt16x8",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "AddPairsInt16x16",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "AddPairsInt32x4",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "AddPairsInt32x8",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "AddPairsSaturatedInt16x8",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "AddPairsSaturatedInt16x16",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "AddPairsUint16x8",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "AddPairsUint16x16",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "AddPairsUint32x4",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "AddPairsUint32x8",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:        "AddSaturatedInt8x16",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "AddSaturatedInt8x32",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "AddSaturatedInt8x64",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "AddSaturatedInt16x8",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "AddSaturatedInt16x16",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "AddSaturatedInt16x32",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "AddSaturatedMaskedInt8x16",
 +              argLen:      3,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "AddSaturatedMaskedInt8x32",
 +              argLen:      3,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "AddSaturatedMaskedInt8x64",
 +              argLen:      3,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "AddSaturatedMaskedInt16x8",
 +              argLen:      3,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "AddSaturatedMaskedInt16x16",
 +              argLen:      3,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "AddSaturatedMaskedInt16x32",
 +              argLen:      3,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "AddSaturatedMaskedUint8x16",
 +              argLen:      3,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "AddSaturatedMaskedUint8x32",
 +              argLen:      3,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "AddSaturatedMaskedUint8x64",
 +              argLen:      3,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "AddSaturatedMaskedUint16x8",
 +              argLen:      3,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "AddSaturatedMaskedUint16x16",
 +              argLen:      3,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "AddSaturatedMaskedUint16x32",
 +              argLen:      3,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "AddSaturatedUint8x16",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "AddSaturatedUint8x32",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "AddSaturatedUint8x64",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "AddSaturatedUint16x8",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "AddSaturatedUint16x16",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "AddSaturatedUint16x32",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:    "AddSubFloat32x4",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "AddSubFloat32x8",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "AddSubFloat64x2",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "AddSubFloat64x4",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:        "AddUint8x16",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "AddUint8x32",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "AddUint8x64",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "AddUint16x8",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "AddUint16x16",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "AddUint16x32",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "AddUint32x4",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "AddUint32x8",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "AddUint32x16",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "AddUint64x2",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "AddUint64x4",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "AddUint64x8",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "AndInt8x16",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "AndInt8x32",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "AndInt8x64",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "AndInt16x8",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "AndInt16x16",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "AndInt16x32",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "AndInt32x4",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "AndInt32x8",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "AndInt32x16",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "AndInt64x2",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "AndInt64x4",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "AndInt64x8",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "AndMaskedInt32x4",
 +              argLen:      3,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "AndMaskedInt32x8",
 +              argLen:      3,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "AndMaskedInt32x16",
 +              argLen:      3,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "AndMaskedInt64x2",
 +              argLen:      3,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "AndMaskedInt64x4",
 +              argLen:      3,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "AndMaskedInt64x8",
 +              argLen:      3,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "AndMaskedUint32x4",
 +              argLen:      3,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "AndMaskedUint32x8",
 +              argLen:      3,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "AndMaskedUint32x16",
 +              argLen:      3,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "AndMaskedUint64x2",
 +              argLen:      3,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "AndMaskedUint64x4",
 +              argLen:      3,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "AndMaskedUint64x8",
 +              argLen:      3,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:    "AndNotInt8x16",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "AndNotInt8x32",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "AndNotInt8x64",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "AndNotInt16x8",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "AndNotInt16x16",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "AndNotInt16x32",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "AndNotInt32x4",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "AndNotInt32x8",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "AndNotInt32x16",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "AndNotInt64x2",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "AndNotInt64x4",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "AndNotInt64x8",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "AndNotMaskedInt32x4",
 +              argLen:  3,
 +              generic: true,
 +      },
 +      {
 +              name:    "AndNotMaskedInt32x8",
 +              argLen:  3,
 +              generic: true,
 +      },
 +      {
 +              name:    "AndNotMaskedInt32x16",
 +              argLen:  3,
 +              generic: true,
 +      },
 +      {
 +              name:    "AndNotMaskedInt64x2",
 +              argLen:  3,
 +              generic: true,
 +      },
 +      {
 +              name:    "AndNotMaskedInt64x4",
 +              argLen:  3,
 +              generic: true,
 +      },
 +      {
 +              name:    "AndNotMaskedInt64x8",
 +              argLen:  3,
 +              generic: true,
 +      },
 +      {
 +              name:    "AndNotMaskedUint32x4",
 +              argLen:  3,
 +              generic: true,
 +      },
 +      {
 +              name:    "AndNotMaskedUint32x8",
 +              argLen:  3,
 +              generic: true,
 +      },
 +      {
 +              name:    "AndNotMaskedUint32x16",
 +              argLen:  3,
 +              generic: true,
 +      },
 +      {
 +              name:    "AndNotMaskedUint64x2",
 +              argLen:  3,
 +              generic: true,
 +      },
 +      {
 +              name:    "AndNotMaskedUint64x4",
 +              argLen:  3,
 +              generic: true,
 +      },
 +      {
 +              name:    "AndNotMaskedUint64x8",
 +              argLen:  3,
 +              generic: true,
 +      },
 +      {
 +              name:    "AndNotUint8x16",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "AndNotUint8x32",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "AndNotUint8x64",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "AndNotUint16x8",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "AndNotUint16x16",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "AndNotUint16x32",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "AndNotUint32x4",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "AndNotUint32x8",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "AndNotUint32x16",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "AndNotUint64x2",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "AndNotUint64x4",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "AndNotUint64x8",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:        "AndUint8x16",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "AndUint8x32",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "AndUint8x64",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "AndUint16x8",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "AndUint16x16",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "AndUint16x32",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "AndUint32x4",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "AndUint32x8",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "AndUint32x16",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "AndUint64x2",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "AndUint64x4",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "AndUint64x8",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "AverageMaskedUint8x16",
 +              argLen:      3,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "AverageMaskedUint8x32",
 +              argLen:      3,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "AverageMaskedUint8x64",
 +              argLen:      3,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "AverageMaskedUint16x8",
 +              argLen:      3,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "AverageMaskedUint16x16",
 +              argLen:      3,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "AverageMaskedUint16x32",
 +              argLen:      3,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "AverageUint8x16",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "AverageUint8x32",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "AverageUint8x64",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "AverageUint16x8",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "AverageUint16x16",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "AverageUint16x32",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:    "Broadcast128Float32x4",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "Broadcast128Float64x2",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "Broadcast128Int8x16",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "Broadcast128Int16x8",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "Broadcast128Int32x4",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "Broadcast128Int64x2",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "Broadcast128MaskedFloat32x4",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "Broadcast128MaskedFloat64x2",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "Broadcast128MaskedInt8x16",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "Broadcast128MaskedInt16x8",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "Broadcast128MaskedInt32x4",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "Broadcast128MaskedInt64x2",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "Broadcast128MaskedUint8x16",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "Broadcast128MaskedUint16x8",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "Broadcast128MaskedUint32x4",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "Broadcast128MaskedUint64x2",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "Broadcast128Uint8x16",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "Broadcast128Uint16x8",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "Broadcast128Uint32x4",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "Broadcast128Uint64x2",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "Broadcast256Float32x4",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "Broadcast256Float64x2",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "Broadcast256Int8x16",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "Broadcast256Int16x8",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "Broadcast256Int32x4",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "Broadcast256Int64x2",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "Broadcast256MaskedFloat32x4",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "Broadcast256MaskedFloat64x2",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "Broadcast256MaskedInt8x16",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "Broadcast256MaskedInt16x8",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "Broadcast256MaskedInt32x4",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "Broadcast256MaskedInt64x2",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "Broadcast256MaskedUint8x16",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "Broadcast256MaskedUint16x8",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "Broadcast256MaskedUint32x4",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "Broadcast256MaskedUint64x2",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "Broadcast256Uint8x16",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "Broadcast256Uint16x8",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "Broadcast256Uint32x4",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "Broadcast256Uint64x2",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "Broadcast512Float32x4",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "Broadcast512Float64x2",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "Broadcast512Int8x16",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "Broadcast512Int16x8",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "Broadcast512Int32x4",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "Broadcast512Int64x2",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "Broadcast512MaskedFloat32x4",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "Broadcast512MaskedFloat64x2",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "Broadcast512MaskedInt8x16",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "Broadcast512MaskedInt16x8",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "Broadcast512MaskedInt32x4",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "Broadcast512MaskedInt64x2",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "Broadcast512MaskedUint8x16",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "Broadcast512MaskedUint16x8",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "Broadcast512MaskedUint32x4",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "Broadcast512MaskedUint64x2",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "Broadcast512Uint8x16",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "Broadcast512Uint16x8",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "Broadcast512Uint32x4",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "Broadcast512Uint64x2",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "CeilFloat32x4",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "CeilFloat32x8",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "CeilFloat64x2",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "CeilFloat64x4",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "CompressFloat32x4",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "CompressFloat32x8",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "CompressFloat32x16",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "CompressFloat64x2",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "CompressFloat64x4",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "CompressFloat64x8",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "CompressInt8x16",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "CompressInt8x32",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "CompressInt8x64",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "CompressInt16x8",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "CompressInt16x16",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "CompressInt16x32",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "CompressInt32x4",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "CompressInt32x8",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "CompressInt32x16",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "CompressInt64x2",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "CompressInt64x4",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "CompressInt64x8",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "CompressUint8x16",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "CompressUint8x32",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "CompressUint8x64",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "CompressUint16x8",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "CompressUint16x16",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "CompressUint16x32",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "CompressUint32x4",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "CompressUint32x8",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "CompressUint32x16",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "CompressUint64x2",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "CompressUint64x4",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "CompressUint64x8",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "ConvertToInt32Float32x4",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "ConvertToInt32Float32x8",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "ConvertToInt32Float32x16",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "ConvertToInt32MaskedFloat32x4",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "ConvertToInt32MaskedFloat32x8",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "ConvertToInt32MaskedFloat32x16",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "ConvertToUint32Float32x4",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "ConvertToUint32Float32x8",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "ConvertToUint32Float32x16",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "ConvertToUint32MaskedFloat32x4",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "ConvertToUint32MaskedFloat32x8",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "ConvertToUint32MaskedFloat32x16",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "CopySignInt8x16",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "CopySignInt8x32",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "CopySignInt16x8",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "CopySignInt16x16",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "CopySignInt32x4",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "CopySignInt32x8",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "DivFloat32x4",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "DivFloat32x8",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "DivFloat32x16",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "DivFloat64x2",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "DivFloat64x4",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "DivFloat64x8",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "DivMaskedFloat32x4",
 +              argLen:  3,
 +              generic: true,
 +      },
 +      {
 +              name:    "DivMaskedFloat32x8",
 +              argLen:  3,
 +              generic: true,
 +      },
 +      {
 +              name:    "DivMaskedFloat32x16",
 +              argLen:  3,
 +              generic: true,
 +      },
 +      {
 +              name:    "DivMaskedFloat64x2",
 +              argLen:  3,
 +              generic: true,
 +      },
 +      {
 +              name:    "DivMaskedFloat64x4",
 +              argLen:  3,
 +              generic: true,
 +      },
 +      {
 +              name:    "DivMaskedFloat64x8",
 +              argLen:  3,
 +              generic: true,
 +      },
 +      {
 +              name:    "DotProdPairsInt16x8",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "DotProdPairsInt16x16",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "DotProdPairsInt16x32",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "DotProdPairsMaskedInt16x8",
 +              argLen:  3,
 +              generic: true,
 +      },
 +      {
 +              name:    "DotProdPairsMaskedInt16x16",
 +              argLen:  3,
 +              generic: true,
 +      },
 +      {
 +              name:    "DotProdPairsMaskedInt16x32",
 +              argLen:  3,
 +              generic: true,
 +      },
 +      {
 +              name:    "DotProdPairsSaturatedMaskedUint8x16",
 +              argLen:  3,
 +              generic: true,
 +      },
 +      {
 +              name:    "DotProdPairsSaturatedMaskedUint8x32",
 +              argLen:  3,
 +              generic: true,
 +      },
 +      {
 +              name:    "DotProdPairsSaturatedMaskedUint8x64",
 +              argLen:  3,
 +              generic: true,
 +      },
 +      {
 +              name:    "DotProdPairsSaturatedUint8x16",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "DotProdPairsSaturatedUint8x32",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "DotProdPairsSaturatedUint8x64",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:        "EqualFloat32x4",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "EqualFloat32x8",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "EqualFloat32x16",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "EqualFloat64x2",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "EqualFloat64x4",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "EqualFloat64x8",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "EqualInt8x16",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "EqualInt8x32",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "EqualInt8x64",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "EqualInt16x8",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "EqualInt16x16",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "EqualInt16x32",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "EqualInt32x4",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "EqualInt32x8",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "EqualInt32x16",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "EqualInt64x2",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "EqualInt64x4",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "EqualInt64x8",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "EqualMaskedFloat32x4",
 +              argLen:      3,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "EqualMaskedFloat32x8",
 +              argLen:      3,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "EqualMaskedFloat32x16",
 +              argLen:      3,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "EqualMaskedFloat64x2",
 +              argLen:      3,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "EqualMaskedFloat64x4",
 +              argLen:      3,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "EqualMaskedFloat64x8",
 +              argLen:      3,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "EqualMaskedInt8x16",
 +              argLen:      3,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "EqualMaskedInt8x32",
 +              argLen:      3,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "EqualMaskedInt8x64",
 +              argLen:      3,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "EqualMaskedInt16x8",
 +              argLen:      3,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "EqualMaskedInt16x16",
 +              argLen:      3,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "EqualMaskedInt16x32",
 +              argLen:      3,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "EqualMaskedInt32x4",
 +              argLen:      3,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "EqualMaskedInt32x8",
 +              argLen:      3,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "EqualMaskedInt32x16",
 +              argLen:      3,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "EqualMaskedInt64x2",
 +              argLen:      3,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "EqualMaskedInt64x4",
 +              argLen:      3,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "EqualMaskedInt64x8",
 +              argLen:      3,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "EqualMaskedUint8x16",
 +              argLen:      3,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "EqualMaskedUint8x32",
 +              argLen:      3,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "EqualMaskedUint8x64",
 +              argLen:      3,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "EqualMaskedUint16x8",
 +              argLen:      3,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "EqualMaskedUint16x16",
 +              argLen:      3,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "EqualMaskedUint16x32",
 +              argLen:      3,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "EqualMaskedUint32x4",
 +              argLen:      3,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "EqualMaskedUint32x8",
 +              argLen:      3,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "EqualMaskedUint32x16",
 +              argLen:      3,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "EqualMaskedUint64x2",
 +              argLen:      3,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "EqualMaskedUint64x4",
 +              argLen:      3,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "EqualMaskedUint64x8",
 +              argLen:      3,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "EqualUint8x16",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "EqualUint8x32",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "EqualUint8x64",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "EqualUint16x8",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "EqualUint16x16",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "EqualUint16x32",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "EqualUint32x4",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "EqualUint32x8",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "EqualUint32x16",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "EqualUint64x2",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "EqualUint64x4",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "EqualUint64x8",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:    "ExpandFloat32x4",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "ExpandFloat32x8",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "ExpandFloat32x16",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "ExpandFloat64x2",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "ExpandFloat64x4",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "ExpandFloat64x8",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "ExpandInt8x16",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "ExpandInt8x32",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "ExpandInt8x64",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "ExpandInt16x8",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "ExpandInt16x16",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "ExpandInt16x32",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "ExpandInt32x4",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "ExpandInt32x8",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "ExpandInt32x16",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "ExpandInt64x2",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "ExpandInt64x4",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "ExpandInt64x8",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "ExpandUint8x16",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "ExpandUint8x32",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "ExpandUint8x64",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "ExpandUint16x8",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "ExpandUint16x16",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "ExpandUint16x32",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "ExpandUint32x4",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "ExpandUint32x8",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "ExpandUint32x16",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "ExpandUint64x2",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "ExpandUint64x4",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "ExpandUint64x8",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "FloorFloat32x4",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "FloorFloat32x8",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "FloorFloat64x2",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "FloorFloat64x4",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "GaloisFieldMulMaskedUint8x16",
 +              argLen:  3,
 +              generic: true,
 +      },
 +      {
 +              name:    "GaloisFieldMulMaskedUint8x32",
 +              argLen:  3,
 +              generic: true,
 +      },
 +      {
 +              name:    "GaloisFieldMulMaskedUint8x64",
 +              argLen:  3,
 +              generic: true,
 +      },
 +      {
 +              name:    "GaloisFieldMulUint8x16",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "GaloisFieldMulUint8x32",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "GaloisFieldMulUint8x64",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "GetHiFloat32x8",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "GetHiFloat32x16",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "GetHiFloat64x4",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "GetHiFloat64x8",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "GetHiInt8x32",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "GetHiInt8x64",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "GetHiInt16x16",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "GetHiInt16x32",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "GetHiInt32x8",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "GetHiInt32x16",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "GetHiInt64x4",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "GetHiInt64x8",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "GetHiUint8x32",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "GetHiUint8x64",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "GetHiUint16x16",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "GetHiUint16x32",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "GetHiUint32x8",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "GetHiUint32x16",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "GetHiUint64x4",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "GetHiUint64x8",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "GetLoFloat32x8",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "GetLoFloat32x16",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "GetLoFloat64x4",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "GetLoFloat64x8",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "GetLoInt8x32",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "GetLoInt8x64",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "GetLoInt16x16",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "GetLoInt16x32",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "GetLoInt32x8",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "GetLoInt32x16",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "GetLoInt64x4",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "GetLoInt64x8",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "GetLoUint8x32",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "GetLoUint8x64",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "GetLoUint16x16",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "GetLoUint16x32",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "GetLoUint32x8",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "GetLoUint32x16",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "GetLoUint64x4",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "GetLoUint64x8",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "GreaterEqualFloat32x4",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "GreaterEqualFloat32x8",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "GreaterEqualFloat32x16",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "GreaterEqualFloat64x2",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "GreaterEqualFloat64x4",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "GreaterEqualFloat64x8",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "GreaterEqualInt8x64",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "GreaterEqualInt16x32",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "GreaterEqualInt32x16",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "GreaterEqualInt64x8",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "GreaterEqualMaskedFloat32x4",
 +              argLen:  3,
 +              generic: true,
 +      },
 +      {
 +              name:    "GreaterEqualMaskedFloat32x8",
 +              argLen:  3,
 +              generic: true,
 +      },
 +      {
 +              name:    "GreaterEqualMaskedFloat32x16",
 +              argLen:  3,
 +              generic: true,
 +      },
 +      {
 +              name:    "GreaterEqualMaskedFloat64x2",
 +              argLen:  3,
 +              generic: true,
 +      },
 +      {
 +              name:    "GreaterEqualMaskedFloat64x4",
 +              argLen:  3,
 +              generic: true,
 +      },
 +      {
 +              name:    "GreaterEqualMaskedFloat64x8",
 +              argLen:  3,
 +              generic: true,
 +      },
 +      {
 +              name:    "GreaterEqualMaskedInt8x16",
 +              argLen:  3,
 +              generic: true,
 +      },
 +      {
 +              name:    "GreaterEqualMaskedInt8x32",
 +              argLen:  3,
 +              generic: true,
 +      },
 +      {
 +              name:    "GreaterEqualMaskedInt8x64",
 +              argLen:  3,
 +              generic: true,
 +      },
 +      {
 +              name:    "GreaterEqualMaskedInt16x8",
 +              argLen:  3,
 +              generic: true,
 +      },
 +      {
 +              name:    "GreaterEqualMaskedInt16x16",
 +              argLen:  3,
 +              generic: true,
 +      },
 +      {
 +              name:    "GreaterEqualMaskedInt16x32",
 +              argLen:  3,
 +              generic: true,
 +      },
 +      {
 +              name:    "GreaterEqualMaskedInt32x4",
 +              argLen:  3,
 +              generic: true,
 +      },
 +      {
 +              name:    "GreaterEqualMaskedInt32x8",
 +              argLen:  3,
 +              generic: true,
 +      },
 +      {
 +              name:    "GreaterEqualMaskedInt32x16",
 +              argLen:  3,
 +              generic: true,
 +      },
 +      {
 +              name:    "GreaterEqualMaskedInt64x2",
 +              argLen:  3,
 +              generic: true,
 +      },
 +      {
 +              name:    "GreaterEqualMaskedInt64x4",
 +              argLen:  3,
 +              generic: true,
 +      },
 +      {
 +              name:    "GreaterEqualMaskedInt64x8",
 +              argLen:  3,
 +              generic: true,
 +      },
 +      {
 +              name:    "GreaterEqualMaskedUint8x16",
 +              argLen:  3,
 +              generic: true,
 +      },
 +      {
 +              name:    "GreaterEqualMaskedUint8x32",
 +              argLen:  3,
 +              generic: true,
 +      },
 +      {
 +              name:    "GreaterEqualMaskedUint8x64",
 +              argLen:  3,
 +              generic: true,
 +      },
 +      {
 +              name:    "GreaterEqualMaskedUint16x8",
 +              argLen:  3,
 +              generic: true,
 +      },
 +      {
 +              name:    "GreaterEqualMaskedUint16x16",
 +              argLen:  3,
 +              generic: true,
 +      },
 +      {
 +              name:    "GreaterEqualMaskedUint16x32",
 +              argLen:  3,
 +              generic: true,
 +      },
 +      {
 +              name:    "GreaterEqualMaskedUint32x4",
 +              argLen:  3,
 +              generic: true,
 +      },
 +      {
 +              name:    "GreaterEqualMaskedUint32x8",
 +              argLen:  3,
 +              generic: true,
 +      },
 +      {
 +              name:    "GreaterEqualMaskedUint32x16",
 +              argLen:  3,
 +              generic: true,
 +      },
 +      {
 +              name:    "GreaterEqualMaskedUint64x2",
 +              argLen:  3,
 +              generic: true,
 +      },
 +      {
 +              name:    "GreaterEqualMaskedUint64x4",
 +              argLen:  3,
 +              generic: true,
 +      },
 +      {
 +              name:    "GreaterEqualMaskedUint64x8",
 +              argLen:  3,
 +              generic: true,
 +      },
 +      {
 +              name:    "GreaterEqualUint8x64",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "GreaterEqualUint16x32",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "GreaterEqualUint32x16",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "GreaterEqualUint64x8",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "GreaterFloat32x4",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "GreaterFloat32x8",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "GreaterFloat32x16",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "GreaterFloat64x2",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "GreaterFloat64x4",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "GreaterFloat64x8",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "GreaterInt8x16",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "GreaterInt8x32",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "GreaterInt8x64",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "GreaterInt16x8",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "GreaterInt16x16",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "GreaterInt16x32",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "GreaterInt32x4",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "GreaterInt32x8",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "GreaterInt32x16",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "GreaterInt64x2",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "GreaterInt64x4",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "GreaterInt64x8",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "GreaterMaskedFloat32x4",
 +              argLen:  3,
 +              generic: true,
 +      },
 +      {
 +              name:    "GreaterMaskedFloat32x8",
 +              argLen:  3,
 +              generic: true,
 +      },
 +      {
 +              name:    "GreaterMaskedFloat32x16",
 +              argLen:  3,
 +              generic: true,
 +      },
 +      {
 +              name:    "GreaterMaskedFloat64x2",
 +              argLen:  3,
 +              generic: true,
 +      },
 +      {
 +              name:    "GreaterMaskedFloat64x4",
 +              argLen:  3,
 +              generic: true,
 +      },
 +      {
 +              name:    "GreaterMaskedFloat64x8",
 +              argLen:  3,
 +              generic: true,
 +      },
 +      {
 +              name:    "GreaterMaskedInt8x16",
 +              argLen:  3,
 +              generic: true,
 +      },
 +      {
 +              name:    "GreaterMaskedInt8x32",
 +              argLen:  3,
 +              generic: true,
 +      },
 +      {
 +              name:    "GreaterMaskedInt8x64",
 +              argLen:  3,
 +              generic: true,
 +      },
 +      {
 +              name:    "GreaterMaskedInt16x8",
 +              argLen:  3,
 +              generic: true,
 +      },
 +      {
 +              name:    "GreaterMaskedInt16x16",
 +              argLen:  3,
 +              generic: true,
 +      },
 +      {
 +              name:    "GreaterMaskedInt16x32",
 +              argLen:  3,
 +              generic: true,
 +      },
 +      {
 +              name:    "GreaterMaskedInt32x4",
 +              argLen:  3,
 +              generic: true,
 +      },
 +      {
 +              name:    "GreaterMaskedInt32x8",
 +              argLen:  3,
 +              generic: true,
 +      },
 +      {
 +              name:    "GreaterMaskedInt32x16",
 +              argLen:  3,
 +              generic: true,
 +      },
 +      {
 +              name:    "GreaterMaskedInt64x2",
 +              argLen:  3,
 +              generic: true,
 +      },
 +      {
 +              name:    "GreaterMaskedInt64x4",
 +              argLen:  3,
 +              generic: true,
 +      },
 +      {
 +              name:    "GreaterMaskedInt64x8",
 +              argLen:  3,
 +              generic: true,
 +      },
 +      {
 +              name:    "GreaterMaskedUint8x16",
 +              argLen:  3,
 +              generic: true,
 +      },
 +      {
 +              name:    "GreaterMaskedUint8x32",
 +              argLen:  3,
 +              generic: true,
 +      },
 +      {
 +              name:    "GreaterMaskedUint8x64",
 +              argLen:  3,
 +              generic: true,
 +      },
 +      {
 +              name:    "GreaterMaskedUint16x8",
 +              argLen:  3,
 +              generic: true,
 +      },
 +      {
 +              name:    "GreaterMaskedUint16x16",
 +              argLen:  3,
 +              generic: true,
 +      },
 +      {
 +              name:    "GreaterMaskedUint16x32",
 +              argLen:  3,
 +              generic: true,
 +      },
 +      {
 +              name:    "GreaterMaskedUint32x4",
 +              argLen:  3,
 +              generic: true,
 +      },
 +      {
 +              name:    "GreaterMaskedUint32x8",
 +              argLen:  3,
 +              generic: true,
 +      },
 +      {
 +              name:    "GreaterMaskedUint32x16",
 +              argLen:  3,
 +              generic: true,
 +      },
 +      {
 +              name:    "GreaterMaskedUint64x2",
 +              argLen:  3,
 +              generic: true,
 +      },
 +      {
 +              name:    "GreaterMaskedUint64x4",
 +              argLen:  3,
 +              generic: true,
 +      },
 +      {
 +              name:    "GreaterMaskedUint64x8",
 +              argLen:  3,
 +              generic: true,
 +      },
 +      {
 +              name:    "GreaterUint8x64",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "GreaterUint16x32",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "GreaterUint32x16",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "GreaterUint64x8",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:        "IsNanFloat32x4",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "IsNanFloat32x8",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "IsNanFloat32x16",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "IsNanFloat64x2",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "IsNanFloat64x4",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "IsNanFloat64x8",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "IsNanMaskedFloat32x4",
 +              argLen:      3,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "IsNanMaskedFloat32x8",
 +              argLen:      3,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "IsNanMaskedFloat32x16",
 +              argLen:      3,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "IsNanMaskedFloat64x2",
 +              argLen:      3,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "IsNanMaskedFloat64x4",
 +              argLen:      3,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "IsNanMaskedFloat64x8",
 +              argLen:      3,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:    "LessEqualFloat32x4",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "LessEqualFloat32x8",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "LessEqualFloat32x16",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "LessEqualFloat64x2",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "LessEqualFloat64x4",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "LessEqualFloat64x8",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "LessEqualInt8x64",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "LessEqualInt16x32",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "LessEqualInt32x16",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "LessEqualInt64x8",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "LessEqualMaskedFloat32x4",
 +              argLen:  3,
 +              generic: true,
 +      },
 +      {
 +              name:    "LessEqualMaskedFloat32x8",
 +              argLen:  3,
 +              generic: true,
 +      },
 +      {
 +              name:    "LessEqualMaskedFloat32x16",
 +              argLen:  3,
 +              generic: true,
 +      },
 +      {
 +              name:    "LessEqualMaskedFloat64x2",
 +              argLen:  3,
 +              generic: true,
 +      },
 +      {
 +              name:    "LessEqualMaskedFloat64x4",
 +              argLen:  3,
 +              generic: true,
 +      },
 +      {
 +              name:    "LessEqualMaskedFloat64x8",
 +              argLen:  3,
 +              generic: true,
 +      },
 +      {
 +              name:    "LessEqualMaskedInt8x16",
 +              argLen:  3,
 +              generic: true,
 +      },
 +      {
 +              name:    "LessEqualMaskedInt8x32",
 +              argLen:  3,
 +              generic: true,
 +      },
 +      {
 +              name:    "LessEqualMaskedInt8x64",
 +              argLen:  3,
 +              generic: true,
 +      },
 +      {
 +              name:    "LessEqualMaskedInt16x8",
 +              argLen:  3,
 +              generic: true,
 +      },
 +      {
 +              name:    "LessEqualMaskedInt16x16",
 +              argLen:  3,
 +              generic: true,
 +      },
 +      {
 +              name:    "LessEqualMaskedInt16x32",
 +              argLen:  3,
 +              generic: true,
 +      },
 +      {
 +              name:    "LessEqualMaskedInt32x4",
 +              argLen:  3,
 +              generic: true,
 +      },
 +      {
 +              name:    "LessEqualMaskedInt32x8",
 +              argLen:  3,
 +              generic: true,
 +      },
 +      {
 +              name:    "LessEqualMaskedInt32x16",
 +              argLen:  3,
 +              generic: true,
 +      },
 +      {
 +              name:    "LessEqualMaskedInt64x2",
 +              argLen:  3,
 +              generic: true,
 +      },
 +      {
 +              name:    "LessEqualMaskedInt64x4",
 +              argLen:  3,
 +              generic: true,
 +      },
 +      {
 +              name:    "LessEqualMaskedInt64x8",
 +              argLen:  3,
 +              generic: true,
 +      },
 +      {
 +              name:    "LessEqualMaskedUint8x16",
 +              argLen:  3,
 +              generic: true,
 +      },
 +      {
 +              name:    "LessEqualMaskedUint8x32",
 +              argLen:  3,
 +              generic: true,
 +      },
 +      {
 +              name:    "LessEqualMaskedUint8x64",
 +              argLen:  3,
 +              generic: true,
 +      },
 +      {
 +              name:    "LessEqualMaskedUint16x8",
 +              argLen:  3,
 +              generic: true,
 +      },
 +      {
 +              name:    "LessEqualMaskedUint16x16",
 +              argLen:  3,
 +              generic: true,
 +      },
 +      {
 +              name:    "LessEqualMaskedUint16x32",
 +              argLen:  3,
 +              generic: true,
 +      },
 +      {
 +              name:    "LessEqualMaskedUint32x4",
 +              argLen:  3,
 +              generic: true,
 +      },
 +      {
 +              name:    "LessEqualMaskedUint32x8",
 +              argLen:  3,
 +              generic: true,
 +      },
 +      {
 +              name:    "LessEqualMaskedUint32x16",
 +              argLen:  3,
 +              generic: true,
 +      },
 +      {
 +              name:    "LessEqualMaskedUint64x2",
 +              argLen:  3,
 +              generic: true,
 +      },
 +      {
 +              name:    "LessEqualMaskedUint64x4",
 +              argLen:  3,
 +              generic: true,
 +      },
 +      {
 +              name:    "LessEqualMaskedUint64x8",
 +              argLen:  3,
 +              generic: true,
 +      },
 +      {
 +              name:    "LessEqualUint8x64",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "LessEqualUint16x32",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "LessEqualUint32x16",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "LessEqualUint64x8",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "LessFloat32x4",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "LessFloat32x8",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "LessFloat32x16",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "LessFloat64x2",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "LessFloat64x4",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "LessFloat64x8",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "LessInt8x64",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "LessInt16x32",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "LessInt32x16",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "LessInt64x8",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "LessMaskedFloat32x4",
 +              argLen:  3,
 +              generic: true,
 +      },
 +      {
 +              name:    "LessMaskedFloat32x8",
 +              argLen:  3,
 +              generic: true,
 +      },
 +      {
 +              name:    "LessMaskedFloat32x16",
 +              argLen:  3,
 +              generic: true,
 +      },
 +      {
 +              name:    "LessMaskedFloat64x2",
 +              argLen:  3,
 +              generic: true,
 +      },
 +      {
 +              name:    "LessMaskedFloat64x4",
 +              argLen:  3,
 +              generic: true,
 +      },
 +      {
 +              name:    "LessMaskedFloat64x8",
 +              argLen:  3,
 +              generic: true,
 +      },
 +      {
 +              name:    "LessMaskedInt8x16",
 +              argLen:  3,
 +              generic: true,
 +      },
 +      {
 +              name:    "LessMaskedInt8x32",
 +              argLen:  3,
 +              generic: true,
 +      },
 +      {
 +              name:    "LessMaskedInt8x64",
 +              argLen:  3,
 +              generic: true,
 +      },
 +      {
 +              name:    "LessMaskedInt16x8",
 +              argLen:  3,
 +              generic: true,
 +      },
 +      {
 +              name:    "LessMaskedInt16x16",
 +              argLen:  3,
 +              generic: true,
 +      },
 +      {
 +              name:    "LessMaskedInt16x32",
 +              argLen:  3,
 +              generic: true,
 +      },
 +      {
 +              name:    "LessMaskedInt32x4",
 +              argLen:  3,
 +              generic: true,
 +      },
 +      {
 +              name:    "LessMaskedInt32x8",
 +              argLen:  3,
 +              generic: true,
 +      },
 +      {
 +              name:    "LessMaskedInt32x16",
 +              argLen:  3,
 +              generic: true,
 +      },
 +      {
 +              name:    "LessMaskedInt64x2",
 +              argLen:  3,
 +              generic: true,
 +      },
 +      {
 +              name:    "LessMaskedInt64x4",
 +              argLen:  3,
 +              generic: true,
 +      },
 +      {
 +              name:    "LessMaskedInt64x8",
 +              argLen:  3,
 +              generic: true,
 +      },
 +      {
 +              name:    "LessMaskedUint8x16",
 +              argLen:  3,
 +              generic: true,
 +      },
 +      {
 +              name:    "LessMaskedUint8x32",
 +              argLen:  3,
 +              generic: true,
 +      },
 +      {
 +              name:    "LessMaskedUint8x64",
 +              argLen:  3,
 +              generic: true,
 +      },
 +      {
 +              name:    "LessMaskedUint16x8",
 +              argLen:  3,
 +              generic: true,
 +      },
 +      {
 +              name:    "LessMaskedUint16x16",
 +              argLen:  3,
 +              generic: true,
 +      },
 +      {
 +              name:    "LessMaskedUint16x32",
 +              argLen:  3,
 +              generic: true,
 +      },
 +      {
 +              name:    "LessMaskedUint32x4",
 +              argLen:  3,
 +              generic: true,
 +      },
 +      {
 +              name:    "LessMaskedUint32x8",
 +              argLen:  3,
 +              generic: true,
 +      },
 +      {
 +              name:    "LessMaskedUint32x16",
 +              argLen:  3,
 +              generic: true,
 +      },
 +      {
 +              name:    "LessMaskedUint64x2",
 +              argLen:  3,
 +              generic: true,
 +      },
 +      {
 +              name:    "LessMaskedUint64x4",
 +              argLen:  3,
 +              generic: true,
 +      },
 +      {
 +              name:    "LessMaskedUint64x8",
 +              argLen:  3,
 +              generic: true,
 +      },
 +      {
 +              name:    "LessUint8x64",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "LessUint16x32",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "LessUint32x16",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "LessUint64x8",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:        "MaxFloat32x4",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "MaxFloat32x8",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "MaxFloat32x16",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "MaxFloat64x2",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "MaxFloat64x4",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "MaxFloat64x8",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "MaxInt8x16",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "MaxInt8x32",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "MaxInt8x64",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "MaxInt16x8",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "MaxInt16x16",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "MaxInt16x32",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "MaxInt32x4",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "MaxInt32x8",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "MaxInt32x16",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "MaxInt64x2",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "MaxInt64x4",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "MaxInt64x8",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "MaxMaskedFloat32x4",
 +              argLen:      3,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "MaxMaskedFloat32x8",
 +              argLen:      3,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "MaxMaskedFloat32x16",
 +              argLen:      3,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "MaxMaskedFloat64x2",
 +              argLen:      3,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "MaxMaskedFloat64x4",
 +              argLen:      3,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "MaxMaskedFloat64x8",
 +              argLen:      3,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "MaxMaskedInt8x16",
 +              argLen:      3,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "MaxMaskedInt8x32",
 +              argLen:      3,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "MaxMaskedInt8x64",
 +              argLen:      3,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "MaxMaskedInt16x8",
 +              argLen:      3,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "MaxMaskedInt16x16",
 +              argLen:      3,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "MaxMaskedInt16x32",
 +              argLen:      3,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "MaxMaskedInt32x4",
 +              argLen:      3,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "MaxMaskedInt32x8",
 +              argLen:      3,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "MaxMaskedInt32x16",
 +              argLen:      3,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "MaxMaskedInt64x2",
 +              argLen:      3,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "MaxMaskedInt64x4",
 +              argLen:      3,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "MaxMaskedInt64x8",
 +              argLen:      3,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "MaxMaskedUint8x16",
 +              argLen:      3,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "MaxMaskedUint8x32",
 +              argLen:      3,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "MaxMaskedUint8x64",
 +              argLen:      3,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "MaxMaskedUint16x8",
 +              argLen:      3,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "MaxMaskedUint16x16",
 +              argLen:      3,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "MaxMaskedUint16x32",
 +              argLen:      3,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "MaxMaskedUint32x4",
 +              argLen:      3,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "MaxMaskedUint32x8",
 +              argLen:      3,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "MaxMaskedUint32x16",
 +              argLen:      3,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "MaxMaskedUint64x2",
 +              argLen:      3,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "MaxMaskedUint64x4",
 +              argLen:      3,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "MaxMaskedUint64x8",
 +              argLen:      3,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "MaxUint8x16",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "MaxUint8x32",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "MaxUint8x64",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "MaxUint16x8",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "MaxUint16x16",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "MaxUint16x32",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "MaxUint32x4",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "MaxUint32x8",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "MaxUint32x16",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "MaxUint64x2",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "MaxUint64x4",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "MaxUint64x8",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "MinFloat32x4",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "MinFloat32x8",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "MinFloat32x16",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "MinFloat64x2",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "MinFloat64x4",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "MinFloat64x8",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "MinInt8x16",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "MinInt8x32",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "MinInt8x64",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "MinInt16x8",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "MinInt16x16",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "MinInt16x32",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "MinInt32x4",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "MinInt32x8",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "MinInt32x16",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "MinInt64x2",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "MinInt64x4",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "MinInt64x8",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "MinMaskedFloat32x4",
 +              argLen:      3,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "MinMaskedFloat32x8",
 +              argLen:      3,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "MinMaskedFloat32x16",
 +              argLen:      3,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "MinMaskedFloat64x2",
 +              argLen:      3,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "MinMaskedFloat64x4",
 +              argLen:      3,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "MinMaskedFloat64x8",
 +              argLen:      3,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "MinMaskedInt8x16",
 +              argLen:      3,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "MinMaskedInt8x32",
 +              argLen:      3,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "MinMaskedInt8x64",
 +              argLen:      3,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "MinMaskedInt16x8",
 +              argLen:      3,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "MinMaskedInt16x16",
 +              argLen:      3,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "MinMaskedInt16x32",
 +              argLen:      3,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "MinMaskedInt32x4",
 +              argLen:      3,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "MinMaskedInt32x8",
 +              argLen:      3,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "MinMaskedInt32x16",
 +              argLen:      3,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "MinMaskedInt64x2",
 +              argLen:      3,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "MinMaskedInt64x4",
 +              argLen:      3,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "MinMaskedInt64x8",
 +              argLen:      3,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "MinMaskedUint8x16",
 +              argLen:      3,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "MinMaskedUint8x32",
 +              argLen:      3,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "MinMaskedUint8x64",
 +              argLen:      3,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "MinMaskedUint16x8",
 +              argLen:      3,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "MinMaskedUint16x16",
 +              argLen:      3,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "MinMaskedUint16x32",
 +              argLen:      3,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "MinMaskedUint32x4",
 +              argLen:      3,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "MinMaskedUint32x8",
 +              argLen:      3,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "MinMaskedUint32x16",
 +              argLen:      3,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "MinMaskedUint64x2",
 +              argLen:      3,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "MinMaskedUint64x4",
 +              argLen:      3,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "MinMaskedUint64x8",
 +              argLen:      3,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "MinUint8x16",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "MinUint8x32",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "MinUint8x64",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "MinUint16x8",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "MinUint16x16",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "MinUint16x32",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "MinUint32x4",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "MinUint32x8",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "MinUint32x16",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "MinUint64x2",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "MinUint64x4",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "MinUint64x8",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:    "MulAddFloat32x4",
 +              argLen:  3,
 +              generic: true,
 +      },
 +      {
 +              name:    "MulAddFloat32x8",
 +              argLen:  3,
 +              generic: true,
 +      },
 +      {
 +              name:    "MulAddFloat32x16",
 +              argLen:  3,
 +              generic: true,
 +      },
 +      {
 +              name:    "MulAddFloat64x2",
 +              argLen:  3,
 +              generic: true,
 +      },
 +      {
 +              name:    "MulAddFloat64x4",
 +              argLen:  3,
 +              generic: true,
 +      },
 +      {
 +              name:    "MulAddFloat64x8",
 +              argLen:  3,
 +              generic: true,
 +      },
 +      {
 +              name:    "MulAddMaskedFloat32x4",
 +              argLen:  4,
 +              generic: true,
 +      },
 +      {
 +              name:    "MulAddMaskedFloat32x8",
 +              argLen:  4,
 +              generic: true,
 +      },
 +      {
 +              name:    "MulAddMaskedFloat32x16",
 +              argLen:  4,
 +              generic: true,
 +      },
 +      {
 +              name:    "MulAddMaskedFloat64x2",
 +              argLen:  4,
 +              generic: true,
 +      },
 +      {
 +              name:    "MulAddMaskedFloat64x4",
 +              argLen:  4,
 +              generic: true,
 +      },
 +      {
 +              name:    "MulAddMaskedFloat64x8",
 +              argLen:  4,
 +              generic: true,
 +      },
 +      {
 +              name:    "MulAddSubFloat32x4",
 +              argLen:  3,
 +              generic: true,
 +      },
 +      {
 +              name:    "MulAddSubFloat32x8",
 +              argLen:  3,
 +              generic: true,
 +      },
 +      {
 +              name:    "MulAddSubFloat32x16",
 +              argLen:  3,
 +              generic: true,
 +      },
 +      {
 +              name:    "MulAddSubFloat64x2",
 +              argLen:  3,
 +              generic: true,
 +      },
 +      {
 +              name:    "MulAddSubFloat64x4",
 +              argLen:  3,
 +              generic: true,
 +      },
 +      {
 +              name:    "MulAddSubFloat64x8",
 +              argLen:  3,
 +              generic: true,
 +      },
 +      {
 +              name:    "MulAddSubMaskedFloat32x4",
 +              argLen:  4,
 +              generic: true,
 +      },
 +      {
 +              name:    "MulAddSubMaskedFloat32x8",
 +              argLen:  4,
 +              generic: true,
 +      },
 +      {
 +              name:    "MulAddSubMaskedFloat32x16",
 +              argLen:  4,
 +              generic: true,
 +      },
 +      {
 +              name:    "MulAddSubMaskedFloat64x2",
 +              argLen:  4,
 +              generic: true,
 +      },
 +      {
 +              name:    "MulAddSubMaskedFloat64x4",
 +              argLen:  4,
 +              generic: true,
 +      },
 +      {
 +              name:    "MulAddSubMaskedFloat64x8",
 +              argLen:  4,
 +              generic: true,
 +      },
 +      {
 +              name:        "MulEvenWidenInt32x4",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "MulEvenWidenInt32x8",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "MulEvenWidenUint32x4",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "MulEvenWidenUint32x8",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "MulFloat32x4",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "MulFloat32x8",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "MulFloat32x16",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "MulFloat64x2",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "MulFloat64x4",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "MulFloat64x8",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "MulHighInt16x8",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "MulHighInt16x16",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "MulHighInt16x32",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "MulHighMaskedInt16x8",
 +              argLen:      3,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "MulHighMaskedInt16x16",
 +              argLen:      3,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "MulHighMaskedInt16x32",
 +              argLen:      3,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "MulHighMaskedUint16x8",
 +              argLen:      3,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "MulHighMaskedUint16x16",
 +              argLen:      3,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "MulHighMaskedUint16x32",
 +              argLen:      3,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "MulHighUint16x8",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "MulHighUint16x16",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "MulHighUint16x32",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "MulInt16x8",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "MulInt16x16",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "MulInt16x32",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "MulInt32x4",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "MulInt32x8",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "MulInt32x16",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "MulInt64x2",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "MulInt64x4",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "MulInt64x8",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "MulMaskedFloat32x4",
 +              argLen:      3,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "MulMaskedFloat32x8",
 +              argLen:      3,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "MulMaskedFloat32x16",
 +              argLen:      3,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "MulMaskedFloat64x2",
 +              argLen:      3,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "MulMaskedFloat64x4",
 +              argLen:      3,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "MulMaskedFloat64x8",
 +              argLen:      3,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "MulMaskedInt16x8",
 +              argLen:      3,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "MulMaskedInt16x16",
 +              argLen:      3,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "MulMaskedInt16x32",
 +              argLen:      3,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "MulMaskedInt32x4",
 +              argLen:      3,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "MulMaskedInt32x8",
 +              argLen:      3,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "MulMaskedInt32x16",
 +              argLen:      3,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "MulMaskedInt64x2",
 +              argLen:      3,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "MulMaskedInt64x4",
 +              argLen:      3,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "MulMaskedInt64x8",
 +              argLen:      3,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "MulMaskedUint16x8",
 +              argLen:      3,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "MulMaskedUint16x16",
 +              argLen:      3,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "MulMaskedUint16x32",
 +              argLen:      3,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "MulMaskedUint32x4",
 +              argLen:      3,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "MulMaskedUint32x8",
 +              argLen:      3,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "MulMaskedUint32x16",
 +              argLen:      3,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "MulMaskedUint64x2",
 +              argLen:      3,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "MulMaskedUint64x4",
 +              argLen:      3,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "MulMaskedUint64x8",
 +              argLen:      3,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:    "MulSubAddFloat32x4",
 +              argLen:  3,
 +              generic: true,
 +      },
 +      {
 +              name:    "MulSubAddFloat32x8",
 +              argLen:  3,
 +              generic: true,
 +      },
 +      {
 +              name:    "MulSubAddFloat32x16",
 +              argLen:  3,
 +              generic: true,
 +      },
 +      {
 +              name:    "MulSubAddFloat64x2",
 +              argLen:  3,
 +              generic: true,
 +      },
 +      {
 +              name:    "MulSubAddFloat64x4",
 +              argLen:  3,
 +              generic: true,
 +      },
 +      {
 +              name:    "MulSubAddFloat64x8",
 +              argLen:  3,
 +              generic: true,
 +      },
 +      {
 +              name:    "MulSubAddMaskedFloat32x4",
 +              argLen:  4,
 +              generic: true,
 +      },
 +      {
 +              name:    "MulSubAddMaskedFloat32x8",
 +              argLen:  4,
 +              generic: true,
 +      },
 +      {
 +              name:    "MulSubAddMaskedFloat32x16",
 +              argLen:  4,
 +              generic: true,
 +      },
 +      {
 +              name:    "MulSubAddMaskedFloat64x2",
 +              argLen:  4,
 +              generic: true,
 +      },
 +      {
 +              name:    "MulSubAddMaskedFloat64x4",
 +              argLen:  4,
 +              generic: true,
 +      },
 +      {
 +              name:    "MulSubAddMaskedFloat64x8",
 +              argLen:  4,
 +              generic: true,
 +      },
 +      {
 +              name:        "MulUint16x8",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "MulUint16x16",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "MulUint16x32",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "MulUint32x4",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "MulUint32x8",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "MulUint32x16",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "MulUint64x2",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "MulUint64x4",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "MulUint64x8",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "NotEqualFloat32x4",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "NotEqualFloat32x8",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "NotEqualFloat32x16",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "NotEqualFloat64x2",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "NotEqualFloat64x4",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "NotEqualFloat64x8",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "NotEqualInt8x64",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "NotEqualInt16x32",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "NotEqualInt32x16",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "NotEqualInt64x8",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "NotEqualMaskedFloat32x4",
 +              argLen:      3,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "NotEqualMaskedFloat32x8",
 +              argLen:      3,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "NotEqualMaskedFloat32x16",
 +              argLen:      3,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "NotEqualMaskedFloat64x2",
 +              argLen:      3,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "NotEqualMaskedFloat64x4",
 +              argLen:      3,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "NotEqualMaskedFloat64x8",
 +              argLen:      3,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "NotEqualMaskedInt8x16",
 +              argLen:      3,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "NotEqualMaskedInt8x32",
 +              argLen:      3,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "NotEqualMaskedInt8x64",
 +              argLen:      3,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "NotEqualMaskedInt16x8",
 +              argLen:      3,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "NotEqualMaskedInt16x16",
 +              argLen:      3,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "NotEqualMaskedInt16x32",
 +              argLen:      3,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "NotEqualMaskedInt32x4",
 +              argLen:      3,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "NotEqualMaskedInt32x8",
 +              argLen:      3,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "NotEqualMaskedInt32x16",
 +              argLen:      3,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "NotEqualMaskedInt64x2",
 +              argLen:      3,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "NotEqualMaskedInt64x4",
 +              argLen:      3,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "NotEqualMaskedInt64x8",
 +              argLen:      3,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "NotEqualMaskedUint8x16",
 +              argLen:      3,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "NotEqualMaskedUint8x32",
 +              argLen:      3,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "NotEqualMaskedUint8x64",
 +              argLen:      3,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "NotEqualMaskedUint16x8",
 +              argLen:      3,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "NotEqualMaskedUint16x16",
 +              argLen:      3,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "NotEqualMaskedUint16x32",
 +              argLen:      3,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "NotEqualMaskedUint32x4",
 +              argLen:      3,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "NotEqualMaskedUint32x8",
 +              argLen:      3,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "NotEqualMaskedUint32x16",
 +              argLen:      3,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "NotEqualMaskedUint64x2",
 +              argLen:      3,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "NotEqualMaskedUint64x4",
 +              argLen:      3,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "NotEqualMaskedUint64x8",
 +              argLen:      3,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "NotEqualUint8x64",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "NotEqualUint16x32",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "NotEqualUint32x16",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "NotEqualUint64x8",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:    "OnesCountInt8x16",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "OnesCountInt8x32",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "OnesCountInt8x64",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "OnesCountInt16x8",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "OnesCountInt16x16",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "OnesCountInt16x32",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "OnesCountInt32x4",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "OnesCountInt32x8",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "OnesCountInt32x16",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "OnesCountInt64x2",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "OnesCountInt64x4",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "OnesCountInt64x8",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "OnesCountMaskedInt8x16",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "OnesCountMaskedInt8x32",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "OnesCountMaskedInt8x64",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "OnesCountMaskedInt16x8",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "OnesCountMaskedInt16x16",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "OnesCountMaskedInt16x32",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "OnesCountMaskedInt32x4",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "OnesCountMaskedInt32x8",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "OnesCountMaskedInt32x16",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "OnesCountMaskedInt64x2",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "OnesCountMaskedInt64x4",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "OnesCountMaskedInt64x8",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "OnesCountMaskedUint8x16",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "OnesCountMaskedUint8x32",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "OnesCountMaskedUint8x64",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "OnesCountMaskedUint16x8",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "OnesCountMaskedUint16x16",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "OnesCountMaskedUint16x32",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "OnesCountMaskedUint32x4",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "OnesCountMaskedUint32x8",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "OnesCountMaskedUint32x16",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "OnesCountMaskedUint64x2",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "OnesCountMaskedUint64x4",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "OnesCountMaskedUint64x8",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "OnesCountUint8x16",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "OnesCountUint8x32",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "OnesCountUint8x64",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "OnesCountUint16x8",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "OnesCountUint16x16",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "OnesCountUint16x32",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "OnesCountUint32x4",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "OnesCountUint32x8",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "OnesCountUint32x16",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "OnesCountUint64x2",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "OnesCountUint64x4",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "OnesCountUint64x8",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:        "OrInt8x16",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "OrInt8x32",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "OrInt8x64",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "OrInt16x8",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "OrInt16x16",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "OrInt16x32",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "OrInt32x4",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "OrInt32x8",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "OrInt32x16",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "OrInt64x2",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "OrInt64x4",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "OrInt64x8",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "OrMaskedInt32x4",
 +              argLen:      3,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "OrMaskedInt32x8",
 +              argLen:      3,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "OrMaskedInt32x16",
 +              argLen:      3,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "OrMaskedInt64x2",
 +              argLen:      3,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "OrMaskedInt64x4",
 +              argLen:      3,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "OrMaskedInt64x8",
 +              argLen:      3,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "OrMaskedUint32x4",
 +              argLen:      3,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "OrMaskedUint32x8",
 +              argLen:      3,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "OrMaskedUint32x16",
 +              argLen:      3,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "OrMaskedUint64x2",
 +              argLen:      3,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "OrMaskedUint64x4",
 +              argLen:      3,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "OrMaskedUint64x8",
 +              argLen:      3,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "OrUint8x16",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "OrUint8x32",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "OrUint8x64",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "OrUint16x8",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "OrUint16x16",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "OrUint16x32",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "OrUint32x4",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "OrUint32x8",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "OrUint32x16",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "OrUint64x2",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "OrUint64x4",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "OrUint64x8",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:    "Permute2Float32x4",
 +              argLen:  3,
 +              generic: true,
 +      },
 +      {
 +              name:    "Permute2Float32x8",
 +              argLen:  3,
 +              generic: true,
 +      },
 +      {
 +              name:    "Permute2Float32x16",
 +              argLen:  3,
 +              generic: true,
 +      },
 +      {
 +              name:    "Permute2Float64x2",
 +              argLen:  3,
 +              generic: true,
 +      },
 +      {
 +              name:    "Permute2Float64x4",
 +              argLen:  3,
 +              generic: true,
 +      },
 +      {
 +              name:    "Permute2Float64x8",
 +              argLen:  3,
 +              generic: true,
 +      },
 +      {
 +              name:    "Permute2Int8x16",
 +              argLen:  3,
 +              generic: true,
 +      },
 +      {
 +              name:    "Permute2Int8x32",
 +              argLen:  3,
 +              generic: true,
 +      },
 +      {
 +              name:    "Permute2Int8x64",
 +              argLen:  3,
 +              generic: true,
 +      },
 +      {
 +              name:    "Permute2Int16x8",
 +              argLen:  3,
 +              generic: true,
 +      },
 +      {
 +              name:    "Permute2Int16x16",
 +              argLen:  3,
 +              generic: true,
 +      },
 +      {
 +              name:    "Permute2Int16x32",
 +              argLen:  3,
 +              generic: true,
 +      },
 +      {
 +              name:    "Permute2Int32x4",
 +              argLen:  3,
 +              generic: true,
 +      },
 +      {
 +              name:    "Permute2Int32x8",
 +              argLen:  3,
 +              generic: true,
 +      },
 +      {
 +              name:    "Permute2Int32x16",
 +              argLen:  3,
 +              generic: true,
 +      },
 +      {
 +              name:    "Permute2Int64x2",
 +              argLen:  3,
 +              generic: true,
 +      },
 +      {
 +              name:    "Permute2Int64x4",
 +              argLen:  3,
 +              generic: true,
 +      },
 +      {
 +              name:    "Permute2Int64x8",
 +              argLen:  3,
 +              generic: true,
 +      },
 +      {
 +              name:    "Permute2MaskedFloat32x4",
 +              argLen:  4,
 +              generic: true,
 +      },
 +      {
 +              name:    "Permute2MaskedFloat32x8",
 +              argLen:  4,
 +              generic: true,
 +      },
 +      {
 +              name:    "Permute2MaskedFloat32x16",
 +              argLen:  4,
 +              generic: true,
 +      },
 +      {
 +              name:    "Permute2MaskedFloat64x2",
 +              argLen:  4,
 +              generic: true,
 +      },
 +      {
 +              name:    "Permute2MaskedFloat64x4",
 +              argLen:  4,
 +              generic: true,
 +      },
 +      {
 +              name:    "Permute2MaskedFloat64x8",
 +              argLen:  4,
 +              generic: true,
 +      },
 +      {
 +              name:    "Permute2MaskedInt8x16",
 +              argLen:  4,
 +              generic: true,
 +      },
 +      {
 +              name:    "Permute2MaskedInt8x32",
 +              argLen:  4,
 +              generic: true,
 +      },
 +      {
 +              name:    "Permute2MaskedInt8x64",
 +              argLen:  4,
 +              generic: true,
 +      },
 +      {
 +              name:    "Permute2MaskedInt16x8",
 +              argLen:  4,
 +              generic: true,
 +      },
 +      {
 +              name:    "Permute2MaskedInt16x16",
 +              argLen:  4,
 +              generic: true,
 +      },
 +      {
 +              name:    "Permute2MaskedInt16x32",
 +              argLen:  4,
 +              generic: true,
 +      },
 +      {
 +              name:    "Permute2MaskedInt32x4",
 +              argLen:  4,
 +              generic: true,
 +      },
 +      {
 +              name:    "Permute2MaskedInt32x8",
 +              argLen:  4,
 +              generic: true,
 +      },
 +      {
 +              name:    "Permute2MaskedInt32x16",
 +              argLen:  4,
 +              generic: true,
 +      },
 +      {
 +              name:    "Permute2MaskedInt64x2",
 +              argLen:  4,
 +              generic: true,
 +      },
 +      {
 +              name:    "Permute2MaskedInt64x4",
 +              argLen:  4,
 +              generic: true,
 +      },
 +      {
 +              name:    "Permute2MaskedInt64x8",
 +              argLen:  4,
 +              generic: true,
 +      },
 +      {
 +              name:    "Permute2MaskedUint8x16",
 +              argLen:  4,
 +              generic: true,
 +      },
 +      {
 +              name:    "Permute2MaskedUint8x32",
 +              argLen:  4,
 +              generic: true,
 +      },
 +      {
 +              name:    "Permute2MaskedUint8x64",
 +              argLen:  4,
 +              generic: true,
 +      },
 +      {
 +              name:    "Permute2MaskedUint16x8",
 +              argLen:  4,
 +              generic: true,
 +      },
 +      {
 +              name:    "Permute2MaskedUint16x16",
 +              argLen:  4,
 +              generic: true,
 +      },
 +      {
 +              name:    "Permute2MaskedUint16x32",
 +              argLen:  4,
 +              generic: true,
 +      },
 +      {
 +              name:    "Permute2MaskedUint32x4",
 +              argLen:  4,
 +              generic: true,
 +      },
 +      {
 +              name:    "Permute2MaskedUint32x8",
 +              argLen:  4,
 +              generic: true,
 +      },
 +      {
 +              name:    "Permute2MaskedUint32x16",
 +              argLen:  4,
 +              generic: true,
 +      },
 +      {
 +              name:    "Permute2MaskedUint64x2",
 +              argLen:  4,
 +              generic: true,
 +      },
 +      {
 +              name:    "Permute2MaskedUint64x4",
 +              argLen:  4,
 +              generic: true,
 +      },
 +      {
 +              name:    "Permute2MaskedUint64x8",
 +              argLen:  4,
 +              generic: true,
 +      },
 +      {
 +              name:    "Permute2Uint8x16",
 +              argLen:  3,
 +              generic: true,
 +      },
 +      {
 +              name:    "Permute2Uint8x32",
 +              argLen:  3,
 +              generic: true,
 +      },
 +      {
 +              name:    "Permute2Uint8x64",
 +              argLen:  3,
 +              generic: true,
 +      },
 +      {
 +              name:    "Permute2Uint16x8",
 +              argLen:  3,
 +              generic: true,
 +      },
 +      {
 +              name:    "Permute2Uint16x16",
 +              argLen:  3,
 +              generic: true,
 +      },
 +      {
 +              name:    "Permute2Uint16x32",
 +              argLen:  3,
 +              generic: true,
 +      },
 +      {
 +              name:    "Permute2Uint32x4",
 +              argLen:  3,
 +              generic: true,
 +      },
 +      {
 +              name:    "Permute2Uint32x8",
 +              argLen:  3,
 +              generic: true,
 +      },
 +      {
 +              name:    "Permute2Uint32x16",
 +              argLen:  3,
 +              generic: true,
 +      },
 +      {
 +              name:    "Permute2Uint64x2",
 +              argLen:  3,
 +              generic: true,
 +      },
 +      {
 +              name:    "Permute2Uint64x4",
 +              argLen:  3,
 +              generic: true,
 +      },
 +      {
 +              name:    "Permute2Uint64x8",
 +              argLen:  3,
 +              generic: true,
 +      },
 +      {
 +              name:    "PermuteFloat32x8",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "PermuteFloat32x16",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "PermuteFloat64x4",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "PermuteFloat64x8",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "PermuteInt8x16",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "PermuteInt8x32",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "PermuteInt8x64",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "PermuteInt16x8",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "PermuteInt16x16",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "PermuteInt16x32",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "PermuteInt32x8",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "PermuteInt32x16",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "PermuteInt64x4",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "PermuteInt64x8",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "PermuteMaskedFloat32x8",
 +              argLen:  3,
 +              generic: true,
 +      },
 +      {
 +              name:    "PermuteMaskedFloat32x16",
 +              argLen:  3,
 +              generic: true,
 +      },
 +      {
 +              name:    "PermuteMaskedFloat64x4",
 +              argLen:  3,
 +              generic: true,
 +      },
 +      {
 +              name:    "PermuteMaskedFloat64x8",
 +              argLen:  3,
 +              generic: true,
 +      },
 +      {
 +              name:    "PermuteMaskedInt8x16",
 +              argLen:  3,
 +              generic: true,
 +      },
 +      {
 +              name:    "PermuteMaskedInt8x32",
 +              argLen:  3,
 +              generic: true,
 +      },
 +      {
 +              name:    "PermuteMaskedInt8x64",
 +              argLen:  3,
 +              generic: true,
 +      },
 +      {
 +              name:    "PermuteMaskedInt16x8",
 +              argLen:  3,
 +              generic: true,
 +      },
 +      {
 +              name:    "PermuteMaskedInt16x16",
 +              argLen:  3,
 +              generic: true,
 +      },
 +      {
 +              name:    "PermuteMaskedInt16x32",
 +              argLen:  3,
 +              generic: true,
 +      },
 +      {
 +              name:    "PermuteMaskedInt32x8",
 +              argLen:  3,
 +              generic: true,
 +      },
 +      {
 +              name:    "PermuteMaskedInt32x16",
 +              argLen:  3,
 +              generic: true,
 +      },
 +      {
 +              name:    "PermuteMaskedInt64x4",
 +              argLen:  3,
 +              generic: true,
 +      },
 +      {
 +              name:    "PermuteMaskedInt64x8",
 +              argLen:  3,
 +              generic: true,
 +      },
 +      {
 +              name:    "PermuteMaskedUint8x16",
 +              argLen:  3,
 +              generic: true,
 +      },
 +      {
 +              name:    "PermuteMaskedUint8x32",
 +              argLen:  3,
 +              generic: true,
 +      },
 +      {
 +              name:    "PermuteMaskedUint8x64",
 +              argLen:  3,
 +              generic: true,
 +      },
 +      {
 +              name:    "PermuteMaskedUint16x8",
 +              argLen:  3,
 +              generic: true,
 +      },
 +      {
 +              name:    "PermuteMaskedUint16x16",
 +              argLen:  3,
 +              generic: true,
 +      },
 +      {
 +              name:    "PermuteMaskedUint16x32",
 +              argLen:  3,
 +              generic: true,
 +      },
 +      {
 +              name:    "PermuteMaskedUint32x8",
 +              argLen:  3,
 +              generic: true,
 +      },
 +      {
 +              name:    "PermuteMaskedUint32x16",
 +              argLen:  3,
 +              generic: true,
 +      },
 +      {
 +              name:    "PermuteMaskedUint64x4",
 +              argLen:  3,
 +              generic: true,
 +      },
 +      {
 +              name:    "PermuteMaskedUint64x8",
 +              argLen:  3,
 +              generic: true,
 +      },
 +      {
 +              name:    "PermuteUint8x16",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "PermuteUint8x32",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "PermuteUint8x64",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "PermuteUint16x8",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "PermuteUint16x16",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "PermuteUint16x32",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "PermuteUint32x8",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "PermuteUint32x16",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "PermuteUint64x4",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "PermuteUint64x8",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "ReciprocalFloat32x4",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "ReciprocalFloat32x8",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "ReciprocalFloat32x16",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "ReciprocalFloat64x2",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "ReciprocalFloat64x4",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "ReciprocalFloat64x8",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "ReciprocalMaskedFloat32x4",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "ReciprocalMaskedFloat32x8",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "ReciprocalMaskedFloat32x16",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "ReciprocalMaskedFloat64x2",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "ReciprocalMaskedFloat64x4",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "ReciprocalMaskedFloat64x8",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "ReciprocalSqrtFloat32x4",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "ReciprocalSqrtFloat32x8",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "ReciprocalSqrtFloat32x16",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "ReciprocalSqrtFloat64x2",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "ReciprocalSqrtFloat64x4",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "ReciprocalSqrtFloat64x8",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "ReciprocalSqrtMaskedFloat32x4",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "ReciprocalSqrtMaskedFloat32x8",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "ReciprocalSqrtMaskedFloat32x16",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "ReciprocalSqrtMaskedFloat64x2",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "ReciprocalSqrtMaskedFloat64x4",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "ReciprocalSqrtMaskedFloat64x8",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "RotateLeftInt32x4",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "RotateLeftInt32x8",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "RotateLeftInt32x16",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "RotateLeftInt64x2",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "RotateLeftInt64x4",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "RotateLeftInt64x8",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "RotateLeftMaskedInt32x4",
 +              argLen:  3,
 +              generic: true,
 +      },
 +      {
 +              name:    "RotateLeftMaskedInt32x8",
 +              argLen:  3,
 +              generic: true,
 +      },
 +      {
 +              name:    "RotateLeftMaskedInt32x16",
 +              argLen:  3,
 +              generic: true,
 +      },
 +      {
 +              name:    "RotateLeftMaskedInt64x2",
 +              argLen:  3,
 +              generic: true,
 +      },
 +      {
 +              name:    "RotateLeftMaskedInt64x4",
 +              argLen:  3,
 +              generic: true,
 +      },
 +      {
 +              name:    "RotateLeftMaskedInt64x8",
 +              argLen:  3,
 +              generic: true,
 +      },
 +      {
 +              name:    "RotateLeftMaskedUint32x4",
 +              argLen:  3,
 +              generic: true,
 +      },
 +      {
 +              name:    "RotateLeftMaskedUint32x8",
 +              argLen:  3,
 +              generic: true,
 +      },
 +      {
 +              name:    "RotateLeftMaskedUint32x16",
 +              argLen:  3,
 +              generic: true,
 +      },
 +      {
 +              name:    "RotateLeftMaskedUint64x2",
 +              argLen:  3,
 +              generic: true,
 +      },
 +      {
 +              name:    "RotateLeftMaskedUint64x4",
 +              argLen:  3,
 +              generic: true,
 +      },
 +      {
 +              name:    "RotateLeftMaskedUint64x8",
 +              argLen:  3,
 +              generic: true,
 +      },
 +      {
 +              name:    "RotateLeftUint32x4",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "RotateLeftUint32x8",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "RotateLeftUint32x16",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "RotateLeftUint64x2",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "RotateLeftUint64x4",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "RotateLeftUint64x8",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "RotateRightInt32x4",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "RotateRightInt32x8",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "RotateRightInt32x16",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "RotateRightInt64x2",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "RotateRightInt64x4",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "RotateRightInt64x8",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "RotateRightMaskedInt32x4",
 +              argLen:  3,
 +              generic: true,
 +      },
 +      {
 +              name:    "RotateRightMaskedInt32x8",
 +              argLen:  3,
 +              generic: true,
 +      },
 +      {
 +              name:    "RotateRightMaskedInt32x16",
 +              argLen:  3,
 +              generic: true,
 +      },
 +      {
 +              name:    "RotateRightMaskedInt64x2",
 +              argLen:  3,
 +              generic: true,
 +      },
 +      {
 +              name:    "RotateRightMaskedInt64x4",
 +              argLen:  3,
 +              generic: true,
 +      },
 +      {
 +              name:    "RotateRightMaskedInt64x8",
 +              argLen:  3,
 +              generic: true,
 +      },
 +      {
 +              name:    "RotateRightMaskedUint32x4",
 +              argLen:  3,
 +              generic: true,
 +      },
 +      {
 +              name:    "RotateRightMaskedUint32x8",
 +              argLen:  3,
 +              generic: true,
 +      },
 +      {
 +              name:    "RotateRightMaskedUint32x16",
 +              argLen:  3,
 +              generic: true,
 +      },
 +      {
 +              name:    "RotateRightMaskedUint64x2",
 +              argLen:  3,
 +              generic: true,
 +      },
 +      {
 +              name:    "RotateRightMaskedUint64x4",
 +              argLen:  3,
 +              generic: true,
 +      },
 +      {
 +              name:    "RotateRightMaskedUint64x8",
 +              argLen:  3,
 +              generic: true,
 +      },
 +      {
 +              name:    "RotateRightUint32x4",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "RotateRightUint32x8",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "RotateRightUint32x16",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "RotateRightUint64x2",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "RotateRightUint64x4",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "RotateRightUint64x8",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "RoundToEvenFloat32x4",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "RoundToEvenFloat32x8",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "RoundToEvenFloat64x2",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "RoundToEvenFloat64x4",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "ScaleFloat32x4",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "ScaleFloat32x8",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "ScaleFloat32x16",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "ScaleFloat64x2",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "ScaleFloat64x4",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "ScaleFloat64x8",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "ScaleMaskedFloat32x4",
 +              argLen:  3,
 +              generic: true,
 +      },
 +      {
 +              name:    "ScaleMaskedFloat32x8",
 +              argLen:  3,
 +              generic: true,
 +      },
 +      {
 +              name:    "ScaleMaskedFloat32x16",
 +              argLen:  3,
 +              generic: true,
 +      },
 +      {
 +              name:    "ScaleMaskedFloat64x2",
 +              argLen:  3,
 +              generic: true,
 +      },
 +      {
 +              name:    "ScaleMaskedFloat64x4",
 +              argLen:  3,
 +              generic: true,
 +      },
 +      {
 +              name:    "ScaleMaskedFloat64x8",
 +              argLen:  3,
 +              generic: true,
 +      },
 +      {
 +              name:    "SetHiFloat32x8",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "SetHiFloat32x16",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "SetHiFloat64x4",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "SetHiFloat64x8",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "SetHiInt8x32",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "SetHiInt8x64",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "SetHiInt16x16",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "SetHiInt16x32",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "SetHiInt32x8",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "SetHiInt32x16",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "SetHiInt64x4",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "SetHiInt64x8",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "SetHiUint8x32",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "SetHiUint8x64",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "SetHiUint16x16",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "SetHiUint16x32",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "SetHiUint32x8",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "SetHiUint32x16",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "SetHiUint64x4",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "SetHiUint64x8",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "SetLoFloat32x8",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "SetLoFloat32x16",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "SetLoFloat64x4",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "SetLoFloat64x8",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "SetLoInt8x32",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "SetLoInt8x64",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "SetLoInt16x16",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "SetLoInt16x32",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "SetLoInt32x8",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "SetLoInt32x16",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "SetLoInt64x4",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "SetLoInt64x8",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "SetLoUint8x32",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "SetLoUint8x64",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "SetLoUint16x16",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "SetLoUint16x32",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "SetLoUint32x8",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "SetLoUint32x16",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "SetLoUint64x4",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "SetLoUint64x8",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "ShiftAllLeftInt16x8",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "ShiftAllLeftInt16x16",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "ShiftAllLeftInt16x32",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "ShiftAllLeftInt32x4",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "ShiftAllLeftInt32x8",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "ShiftAllLeftInt32x16",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "ShiftAllLeftInt64x2",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "ShiftAllLeftInt64x4",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "ShiftAllLeftInt64x8",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "ShiftAllLeftMaskedInt16x8",
 +              argLen:  3,
 +              generic: true,
 +      },
 +      {
 +              name:    "ShiftAllLeftMaskedInt16x16",
 +              argLen:  3,
 +              generic: true,
 +      },
 +      {
 +              name:    "ShiftAllLeftMaskedInt16x32",
 +              argLen:  3,
 +              generic: true,
 +      },
 +      {
 +              name:    "ShiftAllLeftMaskedInt32x4",
 +              argLen:  3,
 +              generic: true,
 +      },
 +      {
 +              name:    "ShiftAllLeftMaskedInt32x8",
 +              argLen:  3,
 +              generic: true,
 +      },
 +      {
 +              name:    "ShiftAllLeftMaskedInt32x16",
 +              argLen:  3,
 +              generic: true,
 +      },
 +      {
 +              name:    "ShiftAllLeftMaskedInt64x2",
 +              argLen:  3,
 +              generic: true,
 +      },
 +      {
 +              name:    "ShiftAllLeftMaskedInt64x4",
 +              argLen:  3,
 +              generic: true,
 +      },
 +      {
 +              name:    "ShiftAllLeftMaskedInt64x8",
 +              argLen:  3,
 +              generic: true,
 +      },
 +      {
 +              name:    "ShiftAllLeftMaskedUint16x8",
 +              argLen:  3,
 +              generic: true,
 +      },
 +      {
 +              name:    "ShiftAllLeftMaskedUint16x16",
 +              argLen:  3,
 +              generic: true,
 +      },
 +      {
 +              name:    "ShiftAllLeftMaskedUint16x32",
 +              argLen:  3,
 +              generic: true,
 +      },
 +      {
 +              name:    "ShiftAllLeftMaskedUint32x4",
 +              argLen:  3,
 +              generic: true,
 +      },
 +      {
 +              name:    "ShiftAllLeftMaskedUint32x8",
 +              argLen:  3,
 +              generic: true,
 +      },
 +      {
 +              name:    "ShiftAllLeftMaskedUint32x16",
 +              argLen:  3,
 +              generic: true,
 +      },
 +      {
 +              name:    "ShiftAllLeftMaskedUint64x2",
 +              argLen:  3,
 +              generic: true,
 +      },
 +      {
 +              name:    "ShiftAllLeftMaskedUint64x4",
 +              argLen:  3,
 +              generic: true,
 +      },
 +      {
 +              name:    "ShiftAllLeftMaskedUint64x8",
 +              argLen:  3,
 +              generic: true,
 +      },
 +      {
 +              name:    "ShiftAllLeftUint16x8",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "ShiftAllLeftUint16x16",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "ShiftAllLeftUint16x32",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "ShiftAllLeftUint32x4",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "ShiftAllLeftUint32x8",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "ShiftAllLeftUint32x16",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "ShiftAllLeftUint64x2",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "ShiftAllLeftUint64x4",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "ShiftAllLeftUint64x8",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "ShiftAllRightInt16x8",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "ShiftAllRightInt16x16",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "ShiftAllRightInt16x32",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "ShiftAllRightInt32x4",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "ShiftAllRightInt32x8",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "ShiftAllRightInt32x16",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "ShiftAllRightInt64x2",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "ShiftAllRightInt64x4",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "ShiftAllRightInt64x8",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "ShiftAllRightMaskedInt16x8",
 +              argLen:  3,
 +              generic: true,
 +      },
 +      {
 +              name:    "ShiftAllRightMaskedInt16x16",
 +              argLen:  3,
 +              generic: true,
 +      },
 +      {
 +              name:    "ShiftAllRightMaskedInt16x32",
 +              argLen:  3,
 +              generic: true,
 +      },
 +      {
 +              name:    "ShiftAllRightMaskedInt32x4",
 +              argLen:  3,
 +              generic: true,
 +      },
 +      {
 +              name:    "ShiftAllRightMaskedInt32x8",
 +              argLen:  3,
 +              generic: true,
 +      },
 +      {
 +              name:    "ShiftAllRightMaskedInt32x16",
 +              argLen:  3,
 +              generic: true,
 +      },
 +      {
 +              name:    "ShiftAllRightMaskedInt64x2",
 +              argLen:  3,
 +              generic: true,
 +      },
 +      {
 +              name:    "ShiftAllRightMaskedInt64x4",
 +              argLen:  3,
 +              generic: true,
 +      },
 +      {
 +              name:    "ShiftAllRightMaskedInt64x8",
 +              argLen:  3,
 +              generic: true,
 +      },
 +      {
 +              name:    "ShiftAllRightMaskedUint16x8",
 +              argLen:  3,
 +              generic: true,
 +      },
 +      {
 +              name:    "ShiftAllRightMaskedUint16x16",
 +              argLen:  3,
 +              generic: true,
 +      },
 +      {
 +              name:    "ShiftAllRightMaskedUint16x32",
 +              argLen:  3,
 +              generic: true,
 +      },
 +      {
 +              name:    "ShiftAllRightMaskedUint32x4",
 +              argLen:  3,
 +              generic: true,
 +      },
 +      {
 +              name:    "ShiftAllRightMaskedUint32x8",
 +              argLen:  3,
 +              generic: true,
 +      },
 +      {
 +              name:    "ShiftAllRightMaskedUint32x16",
 +              argLen:  3,
 +              generic: true,
 +      },
 +      {
 +              name:    "ShiftAllRightMaskedUint64x2",
 +              argLen:  3,
 +              generic: true,
 +      },
 +      {
 +              name:    "ShiftAllRightMaskedUint64x4",
 +              argLen:  3,
 +              generic: true,
 +      },
 +      {
 +              name:    "ShiftAllRightMaskedUint64x8",
 +              argLen:  3,
 +              generic: true,
 +      },
 +      {
 +              name:    "ShiftAllRightUint16x8",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "ShiftAllRightUint16x16",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "ShiftAllRightUint16x32",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "ShiftAllRightUint32x4",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "ShiftAllRightUint32x8",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "ShiftAllRightUint32x16",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "ShiftAllRightUint64x2",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "ShiftAllRightUint64x4",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "ShiftAllRightUint64x8",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "ShiftLeftConcatInt16x8",
 +              argLen:  3,
 +              generic: true,
 +      },
 +      {
 +              name:    "ShiftLeftConcatInt16x16",
 +              argLen:  3,
 +              generic: true,
 +      },
 +      {
 +              name:    "ShiftLeftConcatInt16x32",
 +              argLen:  3,
 +              generic: true,
 +      },
 +      {
 +              name:    "ShiftLeftConcatInt32x4",
 +              argLen:  3,
 +              generic: true,
 +      },
 +      {
 +              name:    "ShiftLeftConcatInt32x8",
 +              argLen:  3,
 +              generic: true,
 +      },
 +      {
 +              name:    "ShiftLeftConcatInt32x16",
 +              argLen:  3,
 +              generic: true,
 +      },
 +      {
 +              name:    "ShiftLeftConcatInt64x2",
 +              argLen:  3,
 +              generic: true,
 +      },
 +      {
 +              name:    "ShiftLeftConcatInt64x4",
 +              argLen:  3,
 +              generic: true,
 +      },
 +      {
 +              name:    "ShiftLeftConcatInt64x8",
 +              argLen:  3,
 +              generic: true,
 +      },
 +      {
 +              name:    "ShiftLeftConcatMaskedInt16x8",
 +              argLen:  4,
 +              generic: true,
 +      },
 +      {
 +              name:    "ShiftLeftConcatMaskedInt16x16",
 +              argLen:  4,
 +              generic: true,
 +      },
 +      {
 +              name:    "ShiftLeftConcatMaskedInt16x32",
 +              argLen:  4,
 +              generic: true,
 +      },
 +      {
 +              name:    "ShiftLeftConcatMaskedInt32x4",
 +              argLen:  4,
 +              generic: true,
 +      },
 +      {
 +              name:    "ShiftLeftConcatMaskedInt32x8",
 +              argLen:  4,
 +              generic: true,
 +      },
 +      {
 +              name:    "ShiftLeftConcatMaskedInt32x16",
 +              argLen:  4,
 +              generic: true,
 +      },
 +      {
 +              name:    "ShiftLeftConcatMaskedInt64x2",
 +              argLen:  4,
 +              generic: true,
 +      },
 +      {
 +              name:    "ShiftLeftConcatMaskedInt64x4",
 +              argLen:  4,
 +              generic: true,
 +      },
 +      {
 +              name:    "ShiftLeftConcatMaskedInt64x8",
 +              argLen:  4,
 +              generic: true,
 +      },
 +      {
 +              name:    "ShiftLeftConcatMaskedUint16x8",
 +              argLen:  4,
 +              generic: true,
 +      },
 +      {
 +              name:    "ShiftLeftConcatMaskedUint16x16",
 +              argLen:  4,
 +              generic: true,
 +      },
 +      {
 +              name:    "ShiftLeftConcatMaskedUint16x32",
 +              argLen:  4,
 +              generic: true,
 +      },
 +      {
 +              name:    "ShiftLeftConcatMaskedUint32x4",
 +              argLen:  4,
 +              generic: true,
 +      },
 +      {
 +              name:    "ShiftLeftConcatMaskedUint32x8",
 +              argLen:  4,
 +              generic: true,
 +      },
 +      {
 +              name:    "ShiftLeftConcatMaskedUint32x16",
 +              argLen:  4,
 +              generic: true,
 +      },
 +      {
 +              name:    "ShiftLeftConcatMaskedUint64x2",
 +              argLen:  4,
 +              generic: true,
 +      },
 +      {
 +              name:    "ShiftLeftConcatMaskedUint64x4",
 +              argLen:  4,
 +              generic: true,
 +      },
 +      {
 +              name:    "ShiftLeftConcatMaskedUint64x8",
 +              argLen:  4,
 +              generic: true,
 +      },
 +      {
 +              name:    "ShiftLeftConcatUint16x8",
 +              argLen:  3,
 +              generic: true,
 +      },
 +      {
 +              name:    "ShiftLeftConcatUint16x16",
 +              argLen:  3,
 +              generic: true,
 +      },
 +      {
 +              name:    "ShiftLeftConcatUint16x32",
 +              argLen:  3,
 +              generic: true,
 +      },
 +      {
 +              name:    "ShiftLeftConcatUint32x4",
 +              argLen:  3,
 +              generic: true,
 +      },
 +      {
 +              name:    "ShiftLeftConcatUint32x8",
 +              argLen:  3,
 +              generic: true,
 +      },
 +      {
 +              name:    "ShiftLeftConcatUint32x16",
 +              argLen:  3,
 +              generic: true,
 +      },
 +      {
 +              name:    "ShiftLeftConcatUint64x2",
 +              argLen:  3,
 +              generic: true,
 +      },
 +      {
 +              name:    "ShiftLeftConcatUint64x4",
 +              argLen:  3,
 +              generic: true,
 +      },
 +      {
 +              name:    "ShiftLeftConcatUint64x8",
 +              argLen:  3,
 +              generic: true,
 +      },
 +      {
 +              name:    "ShiftLeftInt16x8",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "ShiftLeftInt16x16",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "ShiftLeftInt16x32",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "ShiftLeftInt32x4",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "ShiftLeftInt32x8",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "ShiftLeftInt32x16",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "ShiftLeftInt64x2",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "ShiftLeftInt64x4",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "ShiftLeftInt64x8",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "ShiftLeftMaskedInt16x8",
 +              argLen:  3,
 +              generic: true,
 +      },
 +      {
 +              name:    "ShiftLeftMaskedInt16x16",
 +              argLen:  3,
 +              generic: true,
 +      },
 +      {
 +              name:    "ShiftLeftMaskedInt16x32",
 +              argLen:  3,
 +              generic: true,
 +      },
 +      {
 +              name:    "ShiftLeftMaskedInt32x4",
 +              argLen:  3,
 +              generic: true,
 +      },
 +      {
 +              name:    "ShiftLeftMaskedInt32x8",
 +              argLen:  3,
 +              generic: true,
 +      },
 +      {
 +              name:    "ShiftLeftMaskedInt32x16",
 +              argLen:  3,
 +              generic: true,
 +      },
 +      {
 +              name:    "ShiftLeftMaskedInt64x2",
 +              argLen:  3,
 +              generic: true,
 +      },
 +      {
 +              name:    "ShiftLeftMaskedInt64x4",
 +              argLen:  3,
 +              generic: true,
        },
        {
 -              name:        "Add64",
 -              argLen:      2,
 -              commutative: true,
 -              generic:     true,
 +              name:    "ShiftLeftMaskedInt64x8",
 +              argLen:  3,
 +              generic: true,
        },
        {
 -              name:    "AddPtr",
 +              name:    "ShiftLeftMaskedUint16x8",
 +              argLen:  3,
 +              generic: true,
 +      },
 +      {
 +              name:    "ShiftLeftMaskedUint16x16",
 +              argLen:  3,
 +              generic: true,
 +      },
 +      {
 +              name:    "ShiftLeftMaskedUint16x32",
 +              argLen:  3,
 +              generic: true,
 +      },
 +      {
 +              name:    "ShiftLeftMaskedUint32x4",
 +              argLen:  3,
 +              generic: true,
 +      },
 +      {
 +              name:    "ShiftLeftMaskedUint32x8",
 +              argLen:  3,
 +              generic: true,
 +      },
 +      {
 +              name:    "ShiftLeftMaskedUint32x16",
 +              argLen:  3,
 +              generic: true,
 +      },
 +      {
 +              name:    "ShiftLeftMaskedUint64x2",
 +              argLen:  3,
 +              generic: true,
 +      },
 +      {
 +              name:    "ShiftLeftMaskedUint64x4",
 +              argLen:  3,
 +              generic: true,
 +      },
 +      {
 +              name:    "ShiftLeftMaskedUint64x8",
 +              argLen:  3,
 +              generic: true,
 +      },
 +      {
 +              name:    "ShiftLeftUint16x8",
                argLen:  2,
                generic: true,
        },

diff --cc src/cmd/compile/internal/ssa/regalloc.go
Simple merge

diff --cc src/cmd/compile/internal/ssa/rewriteAMD64.go
index 0e2e2311f0f3c13c6e4f65910c2c0daf91254892,a7ee632ae1af7241b48d24aeb5f6981f3304dc4b..6e5e212fbeb00b4bee08c713721eb394966c82b7
--- 1/src/cmd/compile/internal/ssa/rewriteAMD64.go
--- 2/src/cmd/compile/internal/ssa/rewriteAMD64.go
+++ b/src/cmd/compile/internal/ssa/rewriteAMD64.go
@@@ -28972,873 -24384,777 +28972,873 @@@ func rewriteValueAMD64_OpAMD64XORLload(
        v_0 := v.Args[0]
        b := v.Block
        typ := &b.Func.Config.Types
 -      // match: (CondSelect <t> x y (SETEQ cond))
 -      // cond: (is64BitInt(t) || isPtr(t))
 -      // result: (CMOVQEQ y x cond)
 +      // match: (XORLload [off1] {sym} val (ADDQconst [off2] base) mem)
 +      // cond: is32Bit(int64(off1)+int64(off2))
 +      // result: (XORLload [off1+off2] {sym} val base mem)
        for {
 -              t := v.Type
 -              x := v_0
 -              y := v_1
 -              if v_2.Op != OpAMD64SETEQ {
 +              off1 := auxIntToInt32(v.AuxInt)
 +              sym := auxToSym(v.Aux)
 +              val := v_0
 +              if v_1.Op != OpAMD64ADDQconst {
                        break
                }
 -              cond := v_2.Args[0]
 -              if !(is64BitInt(t) || isPtr(t)) {
 +              off2 := auxIntToInt32(v_1.AuxInt)
 +              base := v_1.Args[0]
 +              mem := v_2
 +              if !(is32Bit(int64(off1) + int64(off2))) {
                        break
                }
 -              v.reset(OpAMD64CMOVQEQ)
 -              v.AddArg3(y, x, cond)
 +              v.reset(OpAMD64XORLload)
 +              v.AuxInt = int32ToAuxInt(off1 + off2)
 +              v.Aux = symToAux(sym)
 +              v.AddArg3(val, base, mem)
                return true
        }
 -      // match: (CondSelect <t> x y (SETNE cond))
 -      // cond: (is64BitInt(t) || isPtr(t))
 -      // result: (CMOVQNE y x cond)
 +      // match: (XORLload [off1] {sym1} val (LEAQ [off2] {sym2} base) mem)
 +      // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)
 +      // result: (XORLload [off1+off2] {mergeSym(sym1,sym2)} val base mem)
        for {
 -              t := v.Type
 -              x := v_0
 -              y := v_1
 -              if v_2.Op != OpAMD64SETNE {
 +              off1 := auxIntToInt32(v.AuxInt)
 +              sym1 := auxToSym(v.Aux)
 +              val := v_0
 +              if v_1.Op != OpAMD64LEAQ {
                        break
                }
 -              cond := v_2.Args[0]
 -              if !(is64BitInt(t) || isPtr(t)) {
 +              off2 := auxIntToInt32(v_1.AuxInt)
 +              sym2 := auxToSym(v_1.Aux)
 +              base := v_1.Args[0]
 +              mem := v_2
 +              if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) {
                        break
                }
 -              v.reset(OpAMD64CMOVQNE)
 -              v.AddArg3(y, x, cond)
 +              v.reset(OpAMD64XORLload)
 +              v.AuxInt = int32ToAuxInt(off1 + off2)
 +              v.Aux = symToAux(mergeSym(sym1, sym2))
 +              v.AddArg3(val, base, mem)
                return true
        }
 -      // match: (CondSelect <t> x y (SETL cond))
 -      // cond: (is64BitInt(t) || isPtr(t))
 -      // result: (CMOVQLT y x cond)
 +      // match: (XORLload x [off] {sym} ptr (MOVSSstore [off] {sym} ptr y _))
 +      // result: (XORL x (MOVLf2i y))
        for {
 -              t := v.Type
 +              off := auxIntToInt32(v.AuxInt)
 +              sym := auxToSym(v.Aux)
                x := v_0
 -              y := v_1
 -              if v_2.Op != OpAMD64SETL {
 +              ptr := v_1
 +              if v_2.Op != OpAMD64MOVSSstore || auxIntToInt32(v_2.AuxInt) != off || auxToSym(v_2.Aux) != sym {
                        break
                }
 -              cond := v_2.Args[0]
 -              if !(is64BitInt(t) || isPtr(t)) {
 +              y := v_2.Args[1]
 +              if ptr != v_2.Args[0] {
                        break
                }
 -              v.reset(OpAMD64CMOVQLT)
 -              v.AddArg3(y, x, cond)
 +              v.reset(OpAMD64XORL)
 +              v0 := b.NewValue0(v_2.Pos, OpAMD64MOVLf2i, typ.UInt32)
 +              v0.AddArg(y)
 +              v.AddArg2(x, v0)
                return true
        }
 -      // match: (CondSelect <t> x y (SETG cond))
 -      // cond: (is64BitInt(t) || isPtr(t))
 -      // result: (CMOVQGT y x cond)
 +      return false
 +}
 +func rewriteValueAMD64_OpAMD64XORLmodify(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      // match: (XORLmodify [off1] {sym} (ADDQconst [off2] base) val mem)
 +      // cond: is32Bit(int64(off1)+int64(off2))
 +      // result: (XORLmodify [off1+off2] {sym} base val mem)
        for {
 -              t := v.Type
 -              x := v_0
 -              y := v_1
 -              if v_2.Op != OpAMD64SETG {
 +              off1 := auxIntToInt32(v.AuxInt)
 +              sym := auxToSym(v.Aux)
 +              if v_0.Op != OpAMD64ADDQconst {
                        break
                }
 -              cond := v_2.Args[0]
 -              if !(is64BitInt(t) || isPtr(t)) {
 +              off2 := auxIntToInt32(v_0.AuxInt)
 +              base := v_0.Args[0]
 +              val := v_1
 +              mem := v_2
 +              if !(is32Bit(int64(off1) + int64(off2))) {
                        break
                }
 -              v.reset(OpAMD64CMOVQGT)
 -              v.AddArg3(y, x, cond)
 +              v.reset(OpAMD64XORLmodify)
 +              v.AuxInt = int32ToAuxInt(off1 + off2)
 +              v.Aux = symToAux(sym)
 +              v.AddArg3(base, val, mem)
                return true
        }
 -      // match: (CondSelect <t> x y (SETLE cond))
 -      // cond: (is64BitInt(t) || isPtr(t))
 -      // result: (CMOVQLE y x cond)
 +      // match: (XORLmodify [off1] {sym1} (LEAQ [off2] {sym2} base) val mem)
 +      // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)
 +      // result: (XORLmodify [off1+off2] {mergeSym(sym1,sym2)} base val mem)
        for {
 -              t := v.Type
 -              x := v_0
 -              y := v_1
 -              if v_2.Op != OpAMD64SETLE {
 +              off1 := auxIntToInt32(v.AuxInt)
 +              sym1 := auxToSym(v.Aux)
 +              if v_0.Op != OpAMD64LEAQ {
                        break
                }
 -              cond := v_2.Args[0]
 -              if !(is64BitInt(t) || isPtr(t)) {
 +              off2 := auxIntToInt32(v_0.AuxInt)
 +              sym2 := auxToSym(v_0.Aux)
 +              base := v_0.Args[0]
 +              val := v_1
 +              mem := v_2
 +              if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) {
                        break
                }
 -              v.reset(OpAMD64CMOVQLE)
 -              v.AddArg3(y, x, cond)
 +              v.reset(OpAMD64XORLmodify)
 +              v.AuxInt = int32ToAuxInt(off1 + off2)
 +              v.Aux = symToAux(mergeSym(sym1, sym2))
 +              v.AddArg3(base, val, mem)
                return true
        }
 -      // match: (CondSelect <t> x y (SETGE cond))
 -      // cond: (is64BitInt(t) || isPtr(t))
 -      // result: (CMOVQGE y x cond)
 +      return false
 +}
 +func rewriteValueAMD64_OpAMD64XORQ(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      // match: (XORQ (SHLQ (MOVQconst [1]) y) x)
 +      // result: (BTCQ x y)
        for {
 -              t := v.Type
 -              x := v_0
 -              y := v_1
 -              if v_2.Op != OpAMD64SETGE {
 -                      break
 -              }
 -              cond := v_2.Args[0]
 -              if !(is64BitInt(t) || isPtr(t)) {
 -                      break
 +              for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
 +                      if v_0.Op != OpAMD64SHLQ {
 +                              continue
 +                      }
 +                      y := v_0.Args[1]
 +                      v_0_0 := v_0.Args[0]
 +                      if v_0_0.Op != OpAMD64MOVQconst || auxIntToInt64(v_0_0.AuxInt) != 1 {
 +                              continue
 +                      }
 +                      x := v_1
 +                      v.reset(OpAMD64BTCQ)
 +                      v.AddArg2(x, y)
 +                      return true
                }
 -              v.reset(OpAMD64CMOVQGE)
 -              v.AddArg3(y, x, cond)
 -              return true
 +              break
        }
 -      // match: (CondSelect <t> x y (SETA cond))
 -      // cond: (is64BitInt(t) || isPtr(t))
 -      // result: (CMOVQHI y x cond)
 +      // match: (XORQ (MOVQconst [c]) x)
-       // cond: isUint64PowerOfTwo(c) && uint64(c) >= 1<<31
-       // result: (BTCQconst [int8(log64(c))] x)
++      // cond: isUnsignedPowerOfTwo(uint64(c)) && uint64(c) >= 1<<31
++      // result: (BTCQconst [int8(log64u(uint64(c)))] x)
        for {
 -              t := v.Type
 -              x := v_0
 -              y := v_1
 -              if v_2.Op != OpAMD64SETA {
 -                      break
 -              }
 -              cond := v_2.Args[0]
 -              if !(is64BitInt(t) || isPtr(t)) {
 -                      break
 +              for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
 +                      if v_0.Op != OpAMD64MOVQconst {
 +                              continue
 +                      }
 +                      c := auxIntToInt64(v_0.AuxInt)
 +                      x := v_1
-                       if !(isUint64PowerOfTwo(c) && uint64(c) >= 1<<31) {
++                      if !(isUnsignedPowerOfTwo(uint64(c)) && uint64(c) >= 1<<31) {
 +                              continue
 +                      }
 +                      v.reset(OpAMD64BTCQconst)
-                       v.AuxInt = int8ToAuxInt(int8(log64(c)))
++                      v.AuxInt = int8ToAuxInt(int8(log64u(uint64(c))))
 +                      v.AddArg(x)
 +                      return true
                }
 -              v.reset(OpAMD64CMOVQHI)
 -              v.AddArg3(y, x, cond)
 -              return true
 +              break
        }
 -      // match: (CondSelect <t> x y (SETB cond))
 -      // cond: (is64BitInt(t) || isPtr(t))
 -      // result: (CMOVQCS y x cond)
 +      // match: (XORQ x (MOVQconst [c]))
 +      // cond: is32Bit(c)
 +      // result: (XORQconst [int32(c)] x)
        for {
 -              t := v.Type
 -              x := v_0
 -              y := v_1
 -              if v_2.Op != OpAMD64SETB {
 -                      break
 -              }
 -              cond := v_2.Args[0]
 -              if !(is64BitInt(t) || isPtr(t)) {
 -                      break
 +              for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
 +                      x := v_0
 +                      if v_1.Op != OpAMD64MOVQconst {
 +                              continue
 +                      }
 +                      c := auxIntToInt64(v_1.AuxInt)
 +                      if !(is32Bit(c)) {
 +                              continue
 +                      }
 +                      v.reset(OpAMD64XORQconst)
 +                      v.AuxInt = int32ToAuxInt(int32(c))
 +                      v.AddArg(x)
 +                      return true
                }
 -              v.reset(OpAMD64CMOVQCS)
 -              v.AddArg3(y, x, cond)
 -              return true
 +              break
        }
 -      // match: (CondSelect <t> x y (SETAE cond))
 -      // cond: (is64BitInt(t) || isPtr(t))
 -      // result: (CMOVQCC y x cond)
 +      // match: (XORQ x x)
 +      // result: (MOVQconst [0])
        for {
 -              t := v.Type
                x := v_0
 -              y := v_1
 -              if v_2.Op != OpAMD64SETAE {
 -                      break
 -              }
 -              cond := v_2.Args[0]
 -              if !(is64BitInt(t) || isPtr(t)) {
 +              if x != v_1 {
                        break
                }
 -              v.reset(OpAMD64CMOVQCC)
 -              v.AddArg3(y, x, cond)
 +              v.reset(OpAMD64MOVQconst)
 +              v.AuxInt = int64ToAuxInt(0)
                return true
        }
 -      // match: (CondSelect <t> x y (SETBE cond))
 -      // cond: (is64BitInt(t) || isPtr(t))
 -      // result: (CMOVQLS y x cond)
 +      // match: (XORQ x l:(MOVQload [off] {sym} ptr mem))
 +      // cond: canMergeLoadClobber(v, l, x) && clobber(l)
 +      // result: (XORQload x [off] {sym} ptr mem)
        for {
 -              t := v.Type
 -              x := v_0
 -              y := v_1
 -              if v_2.Op != OpAMD64SETBE {
 -                      break
 -              }
 -              cond := v_2.Args[0]
 -              if !(is64BitInt(t) || isPtr(t)) {
 -                      break
 +              for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
 +                      x := v_0
 +                      l := v_1
 +                      if l.Op != OpAMD64MOVQload {
 +                              continue
 +                      }
 +                      off := auxIntToInt32(l.AuxInt)
 +                      sym := auxToSym(l.Aux)
 +                      mem := l.Args[1]
 +                      ptr := l.Args[0]
 +                      if !(canMergeLoadClobber(v, l, x) && clobber(l)) {
 +                              continue
 +                      }
 +                      v.reset(OpAMD64XORQload)
 +                      v.AuxInt = int32ToAuxInt(off)
 +                      v.Aux = symToAux(sym)
 +                      v.AddArg3(x, ptr, mem)
 +                      return true
                }
 -              v.reset(OpAMD64CMOVQLS)
 -              v.AddArg3(y, x, cond)
 -              return true
 +              break
        }
 -      // match: (CondSelect <t> x y (SETEQF cond))
 -      // cond: (is64BitInt(t) || isPtr(t))
 -      // result: (CMOVQEQF y x cond)
 +      // match: (XORQ x (ADDQconst [-1] x))
 +      // cond: buildcfg.GOAMD64 >= 3
 +      // result: (BLSMSKQ x)
        for {
 -              t := v.Type
 -              x := v_0
 -              y := v_1
 -              if v_2.Op != OpAMD64SETEQF {
 -                      break
 +              for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
 +                      x := v_0
 +                      if v_1.Op != OpAMD64ADDQconst || auxIntToInt32(v_1.AuxInt) != -1 || x != v_1.Args[0] || !(buildcfg.GOAMD64 >= 3) {
 +                              continue
 +                      }
 +                      v.reset(OpAMD64BLSMSKQ)
 +                      v.AddArg(x)
 +                      return true
                }
 -              cond := v_2.Args[0]
 -              if !(is64BitInt(t) || isPtr(t)) {
 +              break
 +      }
 +      return false
 +}
 +func rewriteValueAMD64_OpAMD64XORQconst(v *Value) bool {
 +      v_0 := v.Args[0]
 +      // match: (XORQconst [c] (XORQconst [d] x))
 +      // result: (XORQconst [c ^ d] x)
 +      for {
 +              c := auxIntToInt32(v.AuxInt)
 +              if v_0.Op != OpAMD64XORQconst {
                        break
                }
 -              v.reset(OpAMD64CMOVQEQF)
 -              v.AddArg3(y, x, cond)
 +              d := auxIntToInt32(v_0.AuxInt)
 +              x := v_0.Args[0]
 +              v.reset(OpAMD64XORQconst)
 +              v.AuxInt = int32ToAuxInt(c ^ d)
 +              v.AddArg(x)
                return true
        }
 -      // match: (CondSelect <t> x y (SETNEF cond))
 -      // cond: (is64BitInt(t) || isPtr(t))
 -      // result: (CMOVQNEF y x cond)
 +      // match: (XORQconst [0] x)
 +      // result: x
        for {
 -              t := v.Type
 -              x := v_0
 -              y := v_1
 -              if v_2.Op != OpAMD64SETNEF {
 +              if auxIntToInt32(v.AuxInt) != 0 {
                        break
                }
 -              cond := v_2.Args[0]
 -              if !(is64BitInt(t) || isPtr(t)) {
 +              x := v_0
 +              v.copyOf(x)
 +              return true
 +      }
 +      // match: (XORQconst [c] (MOVQconst [d]))
 +      // result: (MOVQconst [int64(c)^d])
 +      for {
 +              c := auxIntToInt32(v.AuxInt)
 +              if v_0.Op != OpAMD64MOVQconst {
                        break
                }
 -              v.reset(OpAMD64CMOVQNEF)
 -              v.AddArg3(y, x, cond)
 +              d := auxIntToInt64(v_0.AuxInt)
 +              v.reset(OpAMD64MOVQconst)
 +              v.AuxInt = int64ToAuxInt(int64(c) ^ d)
                return true
        }
 -      // match: (CondSelect <t> x y (SETGF cond))
 -      // cond: (is64BitInt(t) || isPtr(t))
 -      // result: (CMOVQGTF y x cond)
 +      return false
 +}
 +func rewriteValueAMD64_OpAMD64XORQconstmodify(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      // match: (XORQconstmodify [valoff1] {sym} (ADDQconst [off2] base) mem)
 +      // cond: ValAndOff(valoff1).canAdd32(off2)
 +      // result: (XORQconstmodify [ValAndOff(valoff1).addOffset32(off2)] {sym} base mem)
        for {
 -              t := v.Type
 -              x := v_0
 -              y := v_1
 -              if v_2.Op != OpAMD64SETGF {
 +              valoff1 := auxIntToValAndOff(v.AuxInt)
 +              sym := auxToSym(v.Aux)
 +              if v_0.Op != OpAMD64ADDQconst {
                        break
                }
 -              cond := v_2.Args[0]
 -              if !(is64BitInt(t) || isPtr(t)) {
 +              off2 := auxIntToInt32(v_0.AuxInt)
 +              base := v_0.Args[0]
 +              mem := v_1
 +              if !(ValAndOff(valoff1).canAdd32(off2)) {
                        break
                }
 -              v.reset(OpAMD64CMOVQGTF)
 -              v.AddArg3(y, x, cond)
 +              v.reset(OpAMD64XORQconstmodify)
 +              v.AuxInt = valAndOffToAuxInt(ValAndOff(valoff1).addOffset32(off2))
 +              v.Aux = symToAux(sym)
 +              v.AddArg2(base, mem)
                return true
        }
 -      // match: (CondSelect <t> x y (SETGEF cond))
 -      // cond: (is64BitInt(t) || isPtr(t))
 -      // result: (CMOVQGEF y x cond)
 +      // match: (XORQconstmodify [valoff1] {sym1} (LEAQ [off2] {sym2} base) mem)
 +      // cond: ValAndOff(valoff1).canAdd32(off2) && canMergeSym(sym1, sym2)
 +      // result: (XORQconstmodify [ValAndOff(valoff1).addOffset32(off2)] {mergeSym(sym1,sym2)} base mem)
        for {
 -              t := v.Type
 -              x := v_0
 -              y := v_1
 -              if v_2.Op != OpAMD64SETGEF {
 +              valoff1 := auxIntToValAndOff(v.AuxInt)
 +              sym1 := auxToSym(v.Aux)
 +              if v_0.Op != OpAMD64LEAQ {
                        break
                }
 -              cond := v_2.Args[0]
 -              if !(is64BitInt(t) || isPtr(t)) {
 +              off2 := auxIntToInt32(v_0.AuxInt)
 +              sym2 := auxToSym(v_0.Aux)
 +              base := v_0.Args[0]
 +              mem := v_1
 +              if !(ValAndOff(valoff1).canAdd32(off2) && canMergeSym(sym1, sym2)) {
                        break
                }
 -              v.reset(OpAMD64CMOVQGEF)
 -              v.AddArg3(y, x, cond)
 +              v.reset(OpAMD64XORQconstmodify)
 +              v.AuxInt = valAndOffToAuxInt(ValAndOff(valoff1).addOffset32(off2))
 +              v.Aux = symToAux(mergeSym(sym1, sym2))
 +              v.AddArg2(base, mem)
                return true
        }
 -      // match: (CondSelect <t> x y (SETEQ cond))
 -      // cond: is32BitInt(t)
 -      // result: (CMOVLEQ y x cond)
 +      return false
 +}
 +func rewriteValueAMD64_OpAMD64XORQload(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      typ := &b.Func.Config.Types
 +      // match: (XORQload [off1] {sym} val (ADDQconst [off2] base) mem)
 +      // cond: is32Bit(int64(off1)+int64(off2))
 +      // result: (XORQload [off1+off2] {sym} val base mem)
        for {
 -              t := v.Type
 -              x := v_0
 -              y := v_1
 -              if v_2.Op != OpAMD64SETEQ {
 +              off1 := auxIntToInt32(v.AuxInt)
 +              sym := auxToSym(v.Aux)
 +              val := v_0
 +              if v_1.Op != OpAMD64ADDQconst {
                        break
                }
 -              cond := v_2.Args[0]
 -              if !(is32BitInt(t)) {
 +              off2 := auxIntToInt32(v_1.AuxInt)
 +              base := v_1.Args[0]
 +              mem := v_2
 +              if !(is32Bit(int64(off1) + int64(off2))) {
                        break
                }
 -              v.reset(OpAMD64CMOVLEQ)
 -              v.AddArg3(y, x, cond)
 +              v.reset(OpAMD64XORQload)
 +              v.AuxInt = int32ToAuxInt(off1 + off2)
 +              v.Aux = symToAux(sym)
 +              v.AddArg3(val, base, mem)
                return true
        }
 -      // match: (CondSelect <t> x y (SETNE cond))
 -      // cond: is32BitInt(t)
 -      // result: (CMOVLNE y x cond)
 +      // match: (XORQload [off1] {sym1} val (LEAQ [off2] {sym2} base) mem)
 +      // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)
 +      // result: (XORQload [off1+off2] {mergeSym(sym1,sym2)} val base mem)
        for {
 -              t := v.Type
 -              x := v_0
 -              y := v_1
 -              if v_2.Op != OpAMD64SETNE {
 +              off1 := auxIntToInt32(v.AuxInt)
 +              sym1 := auxToSym(v.Aux)
 +              val := v_0
 +              if v_1.Op != OpAMD64LEAQ {
                        break
                }
 -              cond := v_2.Args[0]
 -              if !(is32BitInt(t)) {
 +              off2 := auxIntToInt32(v_1.AuxInt)
 +              sym2 := auxToSym(v_1.Aux)
 +              base := v_1.Args[0]
 +              mem := v_2
 +              if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) {
                        break
                }
 -              v.reset(OpAMD64CMOVLNE)
 -              v.AddArg3(y, x, cond)
 +              v.reset(OpAMD64XORQload)
 +              v.AuxInt = int32ToAuxInt(off1 + off2)
 +              v.Aux = symToAux(mergeSym(sym1, sym2))
 +              v.AddArg3(val, base, mem)
                return true
        }
 -      // match: (CondSelect <t> x y (SETL cond))
 -      // cond: is32BitInt(t)
 -      // result: (CMOVLLT y x cond)
 +      // match: (XORQload x [off] {sym} ptr (MOVSDstore [off] {sym} ptr y _))
 +      // result: (XORQ x (MOVQf2i y))
        for {
 -              t := v.Type
 +              off := auxIntToInt32(v.AuxInt)
 +              sym := auxToSym(v.Aux)
                x := v_0
 -              y := v_1
 -              if v_2.Op != OpAMD64SETL {
 +              ptr := v_1
 +              if v_2.Op != OpAMD64MOVSDstore || auxIntToInt32(v_2.AuxInt) != off || auxToSym(v_2.Aux) != sym {
                        break
                }
 -              cond := v_2.Args[0]
 -              if !(is32BitInt(t)) {
 +              y := v_2.Args[1]
 +              if ptr != v_2.Args[0] {
                        break
                }
 -              v.reset(OpAMD64CMOVLLT)
 -              v.AddArg3(y, x, cond)
 +              v.reset(OpAMD64XORQ)
 +              v0 := b.NewValue0(v_2.Pos, OpAMD64MOVQf2i, typ.UInt64)
 +              v0.AddArg(y)
 +              v.AddArg2(x, v0)
                return true
        }
 -      // match: (CondSelect <t> x y (SETG cond))
 -      // cond: is32BitInt(t)
 -      // result: (CMOVLGT y x cond)
 +      return false
 +}
 +func rewriteValueAMD64_OpAMD64XORQmodify(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      // match: (XORQmodify [off1] {sym} (ADDQconst [off2] base) val mem)
 +      // cond: is32Bit(int64(off1)+int64(off2))
 +      // result: (XORQmodify [off1+off2] {sym} base val mem)
        for {
 -              t := v.Type
 -              x := v_0
 -              y := v_1
 -              if v_2.Op != OpAMD64SETG {
 +              off1 := auxIntToInt32(v.AuxInt)
 +              sym := auxToSym(v.Aux)
 +              if v_0.Op != OpAMD64ADDQconst {
                        break
                }
 -              cond := v_2.Args[0]
 -              if !(is32BitInt(t)) {
 +              off2 := auxIntToInt32(v_0.AuxInt)
 +              base := v_0.Args[0]
 +              val := v_1
 +              mem := v_2
 +              if !(is32Bit(int64(off1) + int64(off2))) {
                        break
                }
 -              v.reset(OpAMD64CMOVLGT)
 -              v.AddArg3(y, x, cond)
 +              v.reset(OpAMD64XORQmodify)
 +              v.AuxInt = int32ToAuxInt(off1 + off2)
 +              v.Aux = symToAux(sym)
 +              v.AddArg3(base, val, mem)
                return true
        }
 -      // match: (CondSelect <t> x y (SETLE cond))
 -      // cond: is32BitInt(t)
 -      // result: (CMOVLLE y x cond)
 +      // match: (XORQmodify [off1] {sym1} (LEAQ [off2] {sym2} base) val mem)
 +      // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)
 +      // result: (XORQmodify [off1+off2] {mergeSym(sym1,sym2)} base val mem)
        for {
 -              t := v.Type
 -              x := v_0
 -              y := v_1
 -              if v_2.Op != OpAMD64SETLE {
 +              off1 := auxIntToInt32(v.AuxInt)
 +              sym1 := auxToSym(v.Aux)
 +              if v_0.Op != OpAMD64LEAQ {
                        break
                }
 -              cond := v_2.Args[0]
 -              if !(is32BitInt(t)) {
 +              off2 := auxIntToInt32(v_0.AuxInt)
 +              sym2 := auxToSym(v_0.Aux)
 +              base := v_0.Args[0]
 +              val := v_1
 +              mem := v_2
 +              if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) {
                        break
                }
 -              v.reset(OpAMD64CMOVLLE)
 -              v.AddArg3(y, x, cond)
 +              v.reset(OpAMD64XORQmodify)
 +              v.AuxInt = int32ToAuxInt(off1 + off2)
 +              v.Aux = symToAux(mergeSym(sym1, sym2))
 +              v.AddArg3(base, val, mem)
                return true
        }
 -      // match: (CondSelect <t> x y (SETGE cond))
 -      // cond: is32BitInt(t)
 -      // result: (CMOVLGE y x cond)
 +      return false
 +}
 +func rewriteValueAMD64_OpAbsMaskedInt16x16(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (AbsMaskedInt16x16 x mask)
 +      // result: (VPABSWMasked256 x (VPMOVVec16x16ToM <types.TypeMask> mask))
        for {
 -              t := v.Type
                x := v_0
 -              y := v_1
 -              if v_2.Op != OpAMD64SETGE {
 -                      break
 -              }
 -              cond := v_2.Args[0]
 -              if !(is32BitInt(t)) {
 -                      break
 -              }
 -              v.reset(OpAMD64CMOVLGE)
 -              v.AddArg3(y, x, cond)
 +              mask := v_1
 +              v.reset(OpAMD64VPABSWMasked256)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x16ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg2(x, v0)
                return true
        }
 -      // match: (CondSelect <t> x y (SETA cond))
 -      // cond: is32BitInt(t)
 -      // result: (CMOVLHI y x cond)
 +}
 +func rewriteValueAMD64_OpAbsMaskedInt16x32(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (AbsMaskedInt16x32 x mask)
 +      // result: (VPABSWMasked512 x (VPMOVVec16x32ToM <types.TypeMask> mask))
        for {
 -              t := v.Type
                x := v_0
 -              y := v_1
 -              if v_2.Op != OpAMD64SETA {
 -                      break
 -              }
 -              cond := v_2.Args[0]
 -              if !(is32BitInt(t)) {
 -                      break
 -              }
 -              v.reset(OpAMD64CMOVLHI)
 -              v.AddArg3(y, x, cond)
 +              mask := v_1
 +              v.reset(OpAMD64VPABSWMasked512)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x32ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg2(x, v0)
                return true
        }
 -      // match: (CondSelect <t> x y (SETB cond))
 -      // cond: is32BitInt(t)
 -      // result: (CMOVLCS y x cond)
 +}
 +func rewriteValueAMD64_OpAbsMaskedInt16x8(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (AbsMaskedInt16x8 x mask)
 +      // result: (VPABSWMasked128 x (VPMOVVec16x8ToM <types.TypeMask> mask))
        for {
 -              t := v.Type
                x := v_0
 -              y := v_1
 -              if v_2.Op != OpAMD64SETB {
 -                      break
 -              }
 -              cond := v_2.Args[0]
 -              if !(is32BitInt(t)) {
 -                      break
 -              }
 -              v.reset(OpAMD64CMOVLCS)
 -              v.AddArg3(y, x, cond)
 +              mask := v_1
 +              v.reset(OpAMD64VPABSWMasked128)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x8ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg2(x, v0)
                return true
        }
 -      // match: (CondSelect <t> x y (SETAE cond))
 -      // cond: is32BitInt(t)
 -      // result: (CMOVLCC y x cond)
 +}
 +func rewriteValueAMD64_OpAbsMaskedInt32x16(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (AbsMaskedInt32x16 x mask)
 +      // result: (VPABSDMasked512 x (VPMOVVec32x16ToM <types.TypeMask> mask))
        for {
 -              t := v.Type
                x := v_0
 -              y := v_1
 -              if v_2.Op != OpAMD64SETAE {
 -                      break
 -              }
 -              cond := v_2.Args[0]
 -              if !(is32BitInt(t)) {
 -                      break
 -              }
 -              v.reset(OpAMD64CMOVLCC)
 -              v.AddArg3(y, x, cond)
 +              mask := v_1
 +              v.reset(OpAMD64VPABSDMasked512)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x16ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg2(x, v0)
                return true
        }
 -      // match: (CondSelect <t> x y (SETBE cond))
 -      // cond: is32BitInt(t)
 -      // result: (CMOVLLS y x cond)
 +}
 +func rewriteValueAMD64_OpAbsMaskedInt32x4(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (AbsMaskedInt32x4 x mask)
 +      // result: (VPABSDMasked128 x (VPMOVVec32x4ToM <types.TypeMask> mask))
        for {
 -              t := v.Type
                x := v_0
 -              y := v_1
 -              if v_2.Op != OpAMD64SETBE {
 -                      break
 -              }
 -              cond := v_2.Args[0]
 -              if !(is32BitInt(t)) {
 -                      break
 -              }
 -              v.reset(OpAMD64CMOVLLS)
 -              v.AddArg3(y, x, cond)
 +              mask := v_1
 +              v.reset(OpAMD64VPABSDMasked128)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x4ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg2(x, v0)
                return true
        }
 -      // match: (CondSelect <t> x y (SETEQF cond))
 -      // cond: is32BitInt(t)
 -      // result: (CMOVLEQF y x cond)
 +}
 +func rewriteValueAMD64_OpAbsMaskedInt32x8(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (AbsMaskedInt32x8 x mask)
 +      // result: (VPABSDMasked256 x (VPMOVVec32x8ToM <types.TypeMask> mask))
        for {
 -              t := v.Type
                x := v_0
 -              y := v_1
 -              if v_2.Op != OpAMD64SETEQF {
 -                      break
 -              }
 -              cond := v_2.Args[0]
 -              if !(is32BitInt(t)) {
 -                      break
 -              }
 -              v.reset(OpAMD64CMOVLEQF)
 -              v.AddArg3(y, x, cond)
 +              mask := v_1
 +              v.reset(OpAMD64VPABSDMasked256)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x8ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg2(x, v0)
                return true
        }
 -      // match: (CondSelect <t> x y (SETNEF cond))
 -      // cond: is32BitInt(t)
 -      // result: (CMOVLNEF y x cond)
 +}
 +func rewriteValueAMD64_OpAbsMaskedInt64x2(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (AbsMaskedInt64x2 x mask)
 +      // result: (VPABSQMasked128 x (VPMOVVec64x2ToM <types.TypeMask> mask))
        for {
 -              t := v.Type
                x := v_0
 -              y := v_1
 -              if v_2.Op != OpAMD64SETNEF {
 -                      break
 -              }
 -              cond := v_2.Args[0]
 -              if !(is32BitInt(t)) {
 -                      break
 -              }
 -              v.reset(OpAMD64CMOVLNEF)
 -              v.AddArg3(y, x, cond)
 +              mask := v_1
 +              v.reset(OpAMD64VPABSQMasked128)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x2ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg2(x, v0)
                return true
        }
 -      // match: (CondSelect <t> x y (SETGF cond))
 -      // cond: is32BitInt(t)
 -      // result: (CMOVLGTF y x cond)
 +}
 +func rewriteValueAMD64_OpAbsMaskedInt64x4(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (AbsMaskedInt64x4 x mask)
 +      // result: (VPABSQMasked256 x (VPMOVVec64x4ToM <types.TypeMask> mask))
        for {
 -              t := v.Type
                x := v_0
 -              y := v_1
 -              if v_2.Op != OpAMD64SETGF {
 -                      break
 -              }
 -              cond := v_2.Args[0]
 -              if !(is32BitInt(t)) {
 -                      break
 -              }
 -              v.reset(OpAMD64CMOVLGTF)
 -              v.AddArg3(y, x, cond)
 +              mask := v_1
 +              v.reset(OpAMD64VPABSQMasked256)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x4ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg2(x, v0)
                return true
        }
 -      // match: (CondSelect <t> x y (SETGEF cond))
 -      // cond: is32BitInt(t)
 -      // result: (CMOVLGEF y x cond)
 +}
 +func rewriteValueAMD64_OpAbsMaskedInt64x8(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (AbsMaskedInt64x8 x mask)
 +      // result: (VPABSQMasked512 x (VPMOVVec64x8ToM <types.TypeMask> mask))
        for {
 -              t := v.Type
                x := v_0
 -              y := v_1
 -              if v_2.Op != OpAMD64SETGEF {
 -                      break
 -              }
 -              cond := v_2.Args[0]
 -              if !(is32BitInt(t)) {
 -                      break
 -              }
 -              v.reset(OpAMD64CMOVLGEF)
 -              v.AddArg3(y, x, cond)
 +              mask := v_1
 +              v.reset(OpAMD64VPABSQMasked512)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x8ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg2(x, v0)
                return true
        }
 -      // match: (CondSelect <t> x y (SETEQ cond))
 -      // cond: is16BitInt(t)
 -      // result: (CMOVWEQ y x cond)
 +}
 +func rewriteValueAMD64_OpAbsMaskedInt8x16(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (AbsMaskedInt8x16 x mask)
 +      // result: (VPABSBMasked128 x (VPMOVVec8x16ToM <types.TypeMask> mask))
        for {
 -              t := v.Type
                x := v_0
 -              y := v_1
 -              if v_2.Op != OpAMD64SETEQ {
 -                      break
 -              }
 -              cond := v_2.Args[0]
 -              if !(is16BitInt(t)) {
 -                      break
 -              }
 -              v.reset(OpAMD64CMOVWEQ)
 -              v.AddArg3(y, x, cond)
 +              mask := v_1
 +              v.reset(OpAMD64VPABSBMasked128)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec8x16ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg2(x, v0)
                return true
        }
 -      // match: (CondSelect <t> x y (SETNE cond))
 -      // cond: is16BitInt(t)
 -      // result: (CMOVWNE y x cond)
 +}
 +func rewriteValueAMD64_OpAbsMaskedInt8x32(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (AbsMaskedInt8x32 x mask)
 +      // result: (VPABSBMasked256 x (VPMOVVec8x32ToM <types.TypeMask> mask))
        for {
 -              t := v.Type
                x := v_0
 -              y := v_1
 -              if v_2.Op != OpAMD64SETNE {
 -                      break
 -              }
 -              cond := v_2.Args[0]
 -              if !(is16BitInt(t)) {
 -                      break
 -              }
 -              v.reset(OpAMD64CMOVWNE)
 -              v.AddArg3(y, x, cond)
 +              mask := v_1
 +              v.reset(OpAMD64VPABSBMasked256)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec8x32ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg2(x, v0)
                return true
        }
 -      // match: (CondSelect <t> x y (SETL cond))
 -      // cond: is16BitInt(t)
 -      // result: (CMOVWLT y x cond)
 +}
 +func rewriteValueAMD64_OpAbsMaskedInt8x64(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (AbsMaskedInt8x64 x mask)
 +      // result: (VPABSBMasked512 x (VPMOVVec8x64ToM <types.TypeMask> mask))
        for {
 -              t := v.Type
                x := v_0
 -              y := v_1
 -              if v_2.Op != OpAMD64SETL {
 -                      break
 -              }
 -              cond := v_2.Args[0]
 -              if !(is16BitInt(t)) {
 -                      break
 -              }
 -              v.reset(OpAMD64CMOVWLT)
 -              v.AddArg3(y, x, cond)
 +              mask := v_1
 +              v.reset(OpAMD64VPABSBMasked512)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec8x64ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg2(x, v0)
                return true
        }
 -      // match: (CondSelect <t> x y (SETG cond))
 -      // cond: is16BitInt(t)
 -      // result: (CMOVWGT y x cond)
 +}
 +func rewriteValueAMD64_OpAddDotProdPairsSaturatedMaskedInt32x16(v *Value) bool {
 +      v_3 := v.Args[3]
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (AddDotProdPairsSaturatedMaskedInt32x16 x y z mask)
 +      // result: (VPDPWSSDSMasked512 x y z (VPMOVVec32x16ToM <types.TypeMask> mask))
        for {
 -              t := v.Type
                x := v_0
                y := v_1
 -              if v_2.Op != OpAMD64SETG {
 -                      break
 -              }
 -              cond := v_2.Args[0]
 -              if !(is16BitInt(t)) {
 -                      break
 -              }
 -              v.reset(OpAMD64CMOVWGT)
 -              v.AddArg3(y, x, cond)
 +              z := v_2
 +              mask := v_3
 +              v.reset(OpAMD64VPDPWSSDSMasked512)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x16ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg4(x, y, z, v0)
                return true
        }
 -      // match: (CondSelect <t> x y (SETLE cond))
 -      // cond: is16BitInt(t)
 -      // result: (CMOVWLE y x cond)
 +}
 +func rewriteValueAMD64_OpAddDotProdPairsSaturatedMaskedInt32x4(v *Value) bool {
 +      v_3 := v.Args[3]
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (AddDotProdPairsSaturatedMaskedInt32x4 x y z mask)
 +      // result: (VPDPWSSDSMasked128 x y z (VPMOVVec32x4ToM <types.TypeMask> mask))
        for {
 -              t := v.Type
                x := v_0
                y := v_1
 -              if v_2.Op != OpAMD64SETLE {
 -                      break
 -              }
 -              cond := v_2.Args[0]
 -              if !(is16BitInt(t)) {
 -                      break
 -              }
 -              v.reset(OpAMD64CMOVWLE)
 -              v.AddArg3(y, x, cond)
 +              z := v_2
 +              mask := v_3
 +              v.reset(OpAMD64VPDPWSSDSMasked128)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x4ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg4(x, y, z, v0)
                return true
        }
 -      // match: (CondSelect <t> x y (SETGE cond))
 -      // cond: is16BitInt(t)
 -      // result: (CMOVWGE y x cond)
 +}
 +func rewriteValueAMD64_OpAddDotProdPairsSaturatedMaskedInt32x8(v *Value) bool {
 +      v_3 := v.Args[3]
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (AddDotProdPairsSaturatedMaskedInt32x8 x y z mask)
 +      // result: (VPDPWSSDSMasked256 x y z (VPMOVVec32x8ToM <types.TypeMask> mask))
        for {
 -              t := v.Type
                x := v_0
                y := v_1
 -              if v_2.Op != OpAMD64SETGE {
 -                      break
 -              }
 -              cond := v_2.Args[0]
 -              if !(is16BitInt(t)) {
 -                      break
 -              }
 -              v.reset(OpAMD64CMOVWGE)
 -              v.AddArg3(y, x, cond)
 +              z := v_2
 +              mask := v_3
 +              v.reset(OpAMD64VPDPWSSDSMasked256)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x8ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg4(x, y, z, v0)
                return true
        }
 -      // match: (CondSelect <t> x y (SETA cond))
 -      // cond: is16BitInt(t)
 -      // result: (CMOVWHI y x cond)
 +}
 +func rewriteValueAMD64_OpAddDotProdQuadrupleMaskedInt32x16(v *Value) bool {
 +      v_3 := v.Args[3]
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (AddDotProdQuadrupleMaskedInt32x16 x y z mask)
 +      // result: (VPDPBUSDMasked512 x y z (VPMOVVec32x16ToM <types.TypeMask> mask))
        for {
 -              t := v.Type
                x := v_0
                y := v_1
 -              if v_2.Op != OpAMD64SETA {
 -                      break
 -              }
 -              cond := v_2.Args[0]
 -              if !(is16BitInt(t)) {
 -                      break
 -              }
 -              v.reset(OpAMD64CMOVWHI)
 -              v.AddArg3(y, x, cond)
 +              z := v_2
 +              mask := v_3
 +              v.reset(OpAMD64VPDPBUSDMasked512)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x16ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg4(x, y, z, v0)
                return true
        }
 -      // match: (CondSelect <t> x y (SETB cond))
 -      // cond: is16BitInt(t)
 -      // result: (CMOVWCS y x cond)
 +}
 +func rewriteValueAMD64_OpAddDotProdQuadrupleMaskedInt32x4(v *Value) bool {
 +      v_3 := v.Args[3]
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (AddDotProdQuadrupleMaskedInt32x4 x y z mask)
 +      // result: (VPDPBUSDMasked128 x y z (VPMOVVec32x4ToM <types.TypeMask> mask))
        for {
 -              t := v.Type
                x := v_0
                y := v_1
 -              if v_2.Op != OpAMD64SETB {
 -                      break
 -              }
 -              cond := v_2.Args[0]
 -              if !(is16BitInt(t)) {
 -                      break
 -              }
 -              v.reset(OpAMD64CMOVWCS)
 -              v.AddArg3(y, x, cond)
 +              z := v_2
 +              mask := v_3
 +              v.reset(OpAMD64VPDPBUSDMasked128)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x4ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg4(x, y, z, v0)
                return true
        }
 -      // match: (CondSelect <t> x y (SETAE cond))
 -      // cond: is16BitInt(t)
 -      // result: (CMOVWCC y x cond)
 +}
 +func rewriteValueAMD64_OpAddDotProdQuadrupleMaskedInt32x8(v *Value) bool {
 +      v_3 := v.Args[3]
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (AddDotProdQuadrupleMaskedInt32x8 x y z mask)
 +      // result: (VPDPBUSDMasked256 x y z (VPMOVVec32x8ToM <types.TypeMask> mask))
        for {
 -              t := v.Type
                x := v_0
                y := v_1
 -              if v_2.Op != OpAMD64SETAE {
 -                      break
 -              }
 -              cond := v_2.Args[0]
 -              if !(is16BitInt(t)) {
 -                      break
 -              }
 -              v.reset(OpAMD64CMOVWCC)
 -              v.AddArg3(y, x, cond)
 +              z := v_2
 +              mask := v_3
 +              v.reset(OpAMD64VPDPBUSDMasked256)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x8ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg4(x, y, z, v0)
                return true
        }
 -      // match: (CondSelect <t> x y (SETBE cond))
 -      // cond: is16BitInt(t)
 -      // result: (CMOVWLS y x cond)
 +}
 +func rewriteValueAMD64_OpAddDotProdQuadrupleSaturatedMaskedInt32x16(v *Value) bool {
 +      v_3 := v.Args[3]
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (AddDotProdQuadrupleSaturatedMaskedInt32x16 x y z mask)
 +      // result: (VPDPBUSDSMasked512 x y z (VPMOVVec32x16ToM <types.TypeMask> mask))
        for {
 -              t := v.Type
                x := v_0
                y := v_1
 -              if v_2.Op != OpAMD64SETBE {
 -                      break
 -              }
 -              cond := v_2.Args[0]
 -              if !(is16BitInt(t)) {
 -                      break
 -              }
 -              v.reset(OpAMD64CMOVWLS)
 -              v.AddArg3(y, x, cond)
 +              z := v_2
 +              mask := v_3
 +              v.reset(OpAMD64VPDPBUSDSMasked512)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x16ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg4(x, y, z, v0)
                return true
        }
 -      // match: (CondSelect <t> x y (SETEQF cond))
 -      // cond: is16BitInt(t)
 -      // result: (CMOVWEQF y x cond)
 +}
 +func rewriteValueAMD64_OpAddDotProdQuadrupleSaturatedMaskedInt32x4(v *Value) bool {
 +      v_3 := v.Args[3]
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (AddDotProdQuadrupleSaturatedMaskedInt32x4 x y z mask)
 +      // result: (VPDPBUSDSMasked128 x y z (VPMOVVec32x4ToM <types.TypeMask> mask))
        for {
 -              t := v.Type
                x := v_0
                y := v_1
 -              if v_2.Op != OpAMD64SETEQF {
 -                      break
 -              }
 -              cond := v_2.Args[0]
 -              if !(is16BitInt(t)) {
 -                      break
 -              }
 -              v.reset(OpAMD64CMOVWEQF)
 -              v.AddArg3(y, x, cond)
 +              z := v_2
 +              mask := v_3
 +              v.reset(OpAMD64VPDPBUSDSMasked128)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x4ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg4(x, y, z, v0)
                return true
        }
 -      // match: (CondSelect <t> x y (SETNEF cond))
 -      // cond: is16BitInt(t)
 -      // result: (CMOVWNEF y x cond)
 +}
 +func rewriteValueAMD64_OpAddDotProdQuadrupleSaturatedMaskedInt32x8(v *Value) bool {
 +      v_3 := v.Args[3]
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (AddDotProdQuadrupleSaturatedMaskedInt32x8 x y z mask)
 +      // result: (VPDPBUSDSMasked256 x y z (VPMOVVec32x8ToM <types.TypeMask> mask))
        for {
 -              t := v.Type
                x := v_0
                y := v_1
 -              if v_2.Op != OpAMD64SETNEF {
 -                      break
 -              }
 -              cond := v_2.Args[0]
 -              if !(is16BitInt(t)) {
 -                      break
 -              }
 -              v.reset(OpAMD64CMOVWNEF)
 -              v.AddArg3(y, x, cond)
 +              z := v_2
 +              mask := v_3
 +              v.reset(OpAMD64VPDPBUSDSMasked256)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x8ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg4(x, y, z, v0)
                return true
        }
 -      // match: (CondSelect <t> x y (SETGF cond))
 -      // cond: is16BitInt(t)
 -      // result: (CMOVWGTF y x cond)
 +}
 +func rewriteValueAMD64_OpAddMaskedFloat32x16(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (AddMaskedFloat32x16 x y mask)
 +      // result: (VADDPSMasked512 x y (VPMOVVec32x16ToM <types.TypeMask> mask))
        for {
 -              t := v.Type
                x := v_0
                y := v_1
 -              if v_2.Op != OpAMD64SETGF {
 -                      break
 -              }
 -              cond := v_2.Args[0]
 -              if !(is16BitInt(t)) {
 -                      break
 -              }
 -              v.reset(OpAMD64CMOVWGTF)
 -              v.AddArg3(y, x, cond)
 +              mask := v_2
 +              v.reset(OpAMD64VADDPSMasked512)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x16ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg3(x, y, v0)
                return true
        }
 -      // match: (CondSelect <t> x y (SETGEF cond))
 -      // cond: is16BitInt(t)
 -      // result: (CMOVWGEF y x cond)
 +}
 +func rewriteValueAMD64_OpAddMaskedFloat32x4(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (AddMaskedFloat32x4 x y mask)
 +      // result: (VADDPSMasked128 x y (VPMOVVec32x4ToM <types.TypeMask> mask))
        for {
 -              t := v.Type
                x := v_0
                y := v_1
 -              if v_2.Op != OpAMD64SETGEF {
 -                      break
 -              }
 -              cond := v_2.Args[0]
 -              if !(is16BitInt(t)) {
 -                      break
 -              }
 -              v.reset(OpAMD64CMOVWGEF)
 -              v.AddArg3(y, x, cond)
 +              mask := v_2
 +              v.reset(OpAMD64VADDPSMasked128)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x4ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg3(x, y, v0)
                return true
        }
 -      // match: (CondSelect <t> x y check)
 -      // cond: !check.Type.IsFlags() && check.Type.Size() == 1
 -      // result: (CondSelect <t> x y (MOVBQZX <typ.UInt64> check))
 +}
 +func rewriteValueAMD64_OpAddMaskedFloat32x8(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (AddMaskedFloat32x8 x y mask)
 +      // result: (VADDPSMasked256 x y (VPMOVVec32x8ToM <types.TypeMask> mask))
        for {
 -              t := v.Type
                x := v_0
                y := v_1
 -              check := v_2
 -              if !(!check.Type.IsFlags() && check.Type.Size() == 1) {
 -                      break
 -              }
 -              v.reset(OpCondSelect)
 -              v.Type = t
 -              v0 := b.NewValue0(v.Pos, OpAMD64MOVBQZX, typ.UInt64)
 -              v0.AddArg(check)
 +              mask := v_2
 +              v.reset(OpAMD64VADDPSMasked256)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x8ToM, types.TypeMask)
 +              v0.AddArg(mask)
                v.AddArg3(x, y, v0)
                return true
        }
@@@ -31836,22822 -27221,372 +31836,22743 @@@ func rewriteValueAMD64_OpBroadcast256Ma
        v_1 := v.Args[1]
        v_0 := v.Args[0]
        b := v.Block
 -      typ := &b.Func.Config.Types
 -      // match: (Move [0] _ _ mem)
 -      // result: mem
 +      // match: (Broadcast256MaskedInt16x8 x mask)
 +      // result: (VPBROADCASTWMasked256 x (VPMOVVec16x8ToM <types.TypeMask> mask))
        for {
 -              if auxIntToInt64(v.AuxInt) != 0 {
 -                      break
 -              }
 -              mem := v_2
 -              v.copyOf(mem)
 +              x := v_0
 +              mask := v_1
 +              v.reset(OpAMD64VPBROADCASTWMasked256)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x8ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg2(x, v0)
                return true
        }
 -      // match: (Move [1] dst src mem)
 -      // result: (MOVBstore dst (MOVBload src mem) mem)
 +}
 +func rewriteValueAMD64_OpBroadcast256MaskedInt32x4(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (Broadcast256MaskedInt32x4 x mask)
 +      // result: (VPBROADCASTDMasked256 x (VPMOVVec32x4ToM <types.TypeMask> mask))
        for {
 -              if auxIntToInt64(v.AuxInt) != 1 {
 -                      break
 -              }
 -              dst := v_0
 -              src := v_1
 -              mem := v_2
 -              v.reset(OpAMD64MOVBstore)
 -              v0 := b.NewValue0(v.Pos, OpAMD64MOVBload, typ.UInt8)
 -              v0.AddArg2(src, mem)
 -              v.AddArg3(dst, v0, mem)
 +              x := v_0
 +              mask := v_1
 +              v.reset(OpAMD64VPBROADCASTDMasked256)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x4ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg2(x, v0)
                return true
        }
 -      // match: (Move [2] dst src mem)
 -      // result: (MOVWstore dst (MOVWload src mem) mem)
 +}
 +func rewriteValueAMD64_OpBroadcast256MaskedInt64x2(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (Broadcast256MaskedInt64x2 x mask)
 +      // result: (VPBROADCASTQMasked256 x (VPMOVVec64x2ToM <types.TypeMask> mask))
        for {
 -              if auxIntToInt64(v.AuxInt) != 2 {
 -                      break
 -              }
 -              dst := v_0
 -              src := v_1
 -              mem := v_2
 -              v.reset(OpAMD64MOVWstore)
 -              v0 := b.NewValue0(v.Pos, OpAMD64MOVWload, typ.UInt16)
 -              v0.AddArg2(src, mem)
 -              v.AddArg3(dst, v0, mem)
 +              x := v_0
 +              mask := v_1
 +              v.reset(OpAMD64VPBROADCASTQMasked256)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x2ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg2(x, v0)
                return true
        }
 -      // match: (Move [4] dst src mem)
 -      // result: (MOVLstore dst (MOVLload src mem) mem)
 +}
 +func rewriteValueAMD64_OpBroadcast256MaskedInt8x16(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (Broadcast256MaskedInt8x16 x mask)
 +      // result: (VPBROADCASTBMasked256 x (VPMOVVec8x16ToM <types.TypeMask> mask))
        for {
 -              if auxIntToInt64(v.AuxInt) != 4 {
 -                      break
 -              }
 -              dst := v_0
 -              src := v_1
 -              mem := v_2
 -              v.reset(OpAMD64MOVLstore)
 -              v0 := b.NewValue0(v.Pos, OpAMD64MOVLload, typ.UInt32)
 -              v0.AddArg2(src, mem)
 -              v.AddArg3(dst, v0, mem)
 +              x := v_0
 +              mask := v_1
 +              v.reset(OpAMD64VPBROADCASTBMasked256)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec8x16ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg2(x, v0)
                return true
        }
 -      // match: (Move [8] dst src mem)
 -      // result: (MOVQstore dst (MOVQload src mem) mem)
 +}
 +func rewriteValueAMD64_OpBroadcast256MaskedUint16x8(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (Broadcast256MaskedUint16x8 x mask)
 +      // result: (VPBROADCASTWMasked256 x (VPMOVVec16x8ToM <types.TypeMask> mask))
        for {
 -              if auxIntToInt64(v.AuxInt) != 8 {
 -                      break
 -              }
 -              dst := v_0
 -              src := v_1
 -              mem := v_2
 -              v.reset(OpAMD64MOVQstore)
 -              v0 := b.NewValue0(v.Pos, OpAMD64MOVQload, typ.UInt64)
 -              v0.AddArg2(src, mem)
 -              v.AddArg3(dst, v0, mem)
 +              x := v_0
 +              mask := v_1
 +              v.reset(OpAMD64VPBROADCASTWMasked256)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x8ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg2(x, v0)
                return true
        }
 -      // match: (Move [16] dst src mem)
 -      // result: (MOVOstore dst (MOVOload src mem) mem)
 +}
 +func rewriteValueAMD64_OpBroadcast256MaskedUint32x4(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (Broadcast256MaskedUint32x4 x mask)
 +      // result: (VPBROADCASTDMasked256 x (VPMOVVec32x4ToM <types.TypeMask> mask))
        for {
 -              if auxIntToInt64(v.AuxInt) != 16 {
 -                      break
 -              }
 -              dst := v_0
 -              src := v_1
 -              mem := v_2
 -              v.reset(OpAMD64MOVOstore)
 -              v0 := b.NewValue0(v.Pos, OpAMD64MOVOload, types.TypeInt128)
 -              v0.AddArg2(src, mem)
 -              v.AddArg3(dst, v0, mem)
 +              x := v_0
 +              mask := v_1
 +              v.reset(OpAMD64VPBROADCASTDMasked256)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x4ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg2(x, v0)
                return true
        }
 -      // match: (Move [3] dst src mem)
 -      // result: (MOVBstore [2] dst (MOVBload [2] src mem) (MOVWstore dst (MOVWload src mem) mem))
 +}
 +func rewriteValueAMD64_OpBroadcast256MaskedUint64x2(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (Broadcast256MaskedUint64x2 x mask)
 +      // result: (VPBROADCASTQMasked256 x (VPMOVVec64x2ToM <types.TypeMask> mask))
        for {
 -              if auxIntToInt64(v.AuxInt) != 3 {
 -                      break
 -              }
 -              dst := v_0
 -              src := v_1
 -              mem := v_2
 -              v.reset(OpAMD64MOVBstore)
 -              v.AuxInt = int32ToAuxInt(2)
 -              v0 := b.NewValue0(v.Pos, OpAMD64MOVBload, typ.UInt8)
 -              v0.AuxInt = int32ToAuxInt(2)
 -              v0.AddArg2(src, mem)
 -              v1 := b.NewValue0(v.Pos, OpAMD64MOVWstore, types.TypeMem)
 -              v2 := b.NewValue0(v.Pos, OpAMD64MOVWload, typ.UInt16)
 -              v2.AddArg2(src, mem)
 -              v1.AddArg3(dst, v2, mem)
 -              v.AddArg3(dst, v0, v1)
 +              x := v_0
 +              mask := v_1
 +              v.reset(OpAMD64VPBROADCASTQMasked256)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x2ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg2(x, v0)
                return true
        }
 -      // match: (Move [5] dst src mem)
 -      // result: (MOVBstore [4] dst (MOVBload [4] src mem) (MOVLstore dst (MOVLload src mem) mem))
 +}
 +func rewriteValueAMD64_OpBroadcast256MaskedUint8x16(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (Broadcast256MaskedUint8x16 x mask)
 +      // result: (VPBROADCASTBMasked256 x (VPMOVVec8x16ToM <types.TypeMask> mask))
        for {
 -              if auxIntToInt64(v.AuxInt) != 5 {
 -                      break
 -              }
 -              dst := v_0
 -              src := v_1
 -              mem := v_2
 -              v.reset(OpAMD64MOVBstore)
 -              v.AuxInt = int32ToAuxInt(4)
 -              v0 := b.NewValue0(v.Pos, OpAMD64MOVBload, typ.UInt8)
 -              v0.AuxInt = int32ToAuxInt(4)
 -              v0.AddArg2(src, mem)
 -              v1 := b.NewValue0(v.Pos, OpAMD64MOVLstore, types.TypeMem)
 -              v2 := b.NewValue0(v.Pos, OpAMD64MOVLload, typ.UInt32)
 -              v2.AddArg2(src, mem)
 -              v1.AddArg3(dst, v2, mem)
 -              v.AddArg3(dst, v0, v1)
 +              x := v_0
 +              mask := v_1
 +              v.reset(OpAMD64VPBROADCASTBMasked256)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec8x16ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg2(x, v0)
                return true
        }
 -      // match: (Move [6] dst src mem)
 -      // result: (MOVWstore [4] dst (MOVWload [4] src mem) (MOVLstore dst (MOVLload src mem) mem))
 +}
 +func rewriteValueAMD64_OpBroadcast512MaskedFloat32x4(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (Broadcast512MaskedFloat32x4 x mask)
 +      // result: (VBROADCASTSSMasked512 x (VPMOVVec32x4ToM <types.TypeMask> mask))
        for {
 -              if auxIntToInt64(v.AuxInt) != 6 {
 -                      break
 -              }
 -              dst := v_0
 -              src := v_1
 -              mem := v_2
 -              v.reset(OpAMD64MOVWstore)
 -              v.AuxInt = int32ToAuxInt(4)
 -              v0 := b.NewValue0(v.Pos, OpAMD64MOVWload, typ.UInt16)
 -              v0.AuxInt = int32ToAuxInt(4)
 -              v0.AddArg2(src, mem)
 -              v1 := b.NewValue0(v.Pos, OpAMD64MOVLstore, types.TypeMem)
 -              v2 := b.NewValue0(v.Pos, OpAMD64MOVLload, typ.UInt32)
 -              v2.AddArg2(src, mem)
 -              v1.AddArg3(dst, v2, mem)
 -              v.AddArg3(dst, v0, v1)
 +              x := v_0
 +              mask := v_1
 +              v.reset(OpAMD64VBROADCASTSSMasked512)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x4ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg2(x, v0)
                return true
        }
 -      // match: (Move [7] dst src mem)
 -      // result: (MOVLstore [3] dst (MOVLload [3] src mem) (MOVLstore dst (MOVLload src mem) mem))
 +}
 +func rewriteValueAMD64_OpBroadcast512MaskedFloat64x2(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (Broadcast512MaskedFloat64x2 x mask)
 +      // result: (VBROADCASTSDMasked512 x (VPMOVVec64x2ToM <types.TypeMask> mask))
        for {
 -              if auxIntToInt64(v.AuxInt) != 7 {
 -                      break
 -              }
 -              dst := v_0
 -              src := v_1
 -              mem := v_2
 -              v.reset(OpAMD64MOVLstore)
 -              v.AuxInt = int32ToAuxInt(3)
 -              v0 := b.NewValue0(v.Pos, OpAMD64MOVLload, typ.UInt32)
 -              v0.AuxInt = int32ToAuxInt(3)
 -              v0.AddArg2(src, mem)
 -              v1 := b.NewValue0(v.Pos, OpAMD64MOVLstore, types.TypeMem)
 -              v2 := b.NewValue0(v.Pos, OpAMD64MOVLload, typ.UInt32)
 -              v2.AddArg2(src, mem)
 -              v1.AddArg3(dst, v2, mem)
 -              v.AddArg3(dst, v0, v1)
 +              x := v_0
 +              mask := v_1
 +              v.reset(OpAMD64VBROADCASTSDMasked512)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x2ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg2(x, v0)
                return true
        }
 -      // match: (Move [9] dst src mem)
 -      // result: (MOVBstore [8] dst (MOVBload [8] src mem) (MOVQstore dst (MOVQload src mem) mem))
 +}
 +func rewriteValueAMD64_OpBroadcast512MaskedInt16x8(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (Broadcast512MaskedInt16x8 x mask)
 +      // result: (VPBROADCASTWMasked512 x (VPMOVVec16x8ToM <types.TypeMask> mask))
        for {
 -              if auxIntToInt64(v.AuxInt) != 9 {
 -                      break
 -              }
 -              dst := v_0
 -              src := v_1
 -              mem := v_2
 -              v.reset(OpAMD64MOVBstore)
 -              v.AuxInt = int32ToAuxInt(8)
 -              v0 := b.NewValue0(v.Pos, OpAMD64MOVBload, typ.UInt8)
 -              v0.AuxInt = int32ToAuxInt(8)
 -              v0.AddArg2(src, mem)
 -              v1 := b.NewValue0(v.Pos, OpAMD64MOVQstore, types.TypeMem)
 -              v2 := b.NewValue0(v.Pos, OpAMD64MOVQload, typ.UInt64)
 -              v2.AddArg2(src, mem)
 -              v1.AddArg3(dst, v2, mem)
 -              v.AddArg3(dst, v0, v1)
 +              x := v_0
 +              mask := v_1
 +              v.reset(OpAMD64VPBROADCASTWMasked512)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x8ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg2(x, v0)
                return true
        }
 -      // match: (Move [10] dst src mem)
 -      // result: (MOVWstore [8] dst (MOVWload [8] src mem) (MOVQstore dst (MOVQload src mem) mem))
 +}
 +func rewriteValueAMD64_OpBroadcast512MaskedInt32x4(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (Broadcast512MaskedInt32x4 x mask)
 +      // result: (VPBROADCASTDMasked512 x (VPMOVVec32x4ToM <types.TypeMask> mask))
        for {
 -              if auxIntToInt64(v.AuxInt) != 10 {
 -                      break
 -              }
 -              dst := v_0
 -              src := v_1
 -              mem := v_2
 -              v.reset(OpAMD64MOVWstore)
 -              v.AuxInt = int32ToAuxInt(8)
 -              v0 := b.NewValue0(v.Pos, OpAMD64MOVWload, typ.UInt16)
 -              v0.AuxInt = int32ToAuxInt(8)
 -              v0.AddArg2(src, mem)
 -              v1 := b.NewValue0(v.Pos, OpAMD64MOVQstore, types.TypeMem)
 -              v2 := b.NewValue0(v.Pos, OpAMD64MOVQload, typ.UInt64)
 -              v2.AddArg2(src, mem)
 -              v1.AddArg3(dst, v2, mem)
 -              v.AddArg3(dst, v0, v1)
 +              x := v_0
 +              mask := v_1
 +              v.reset(OpAMD64VPBROADCASTDMasked512)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x4ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg2(x, v0)
                return true
        }
 -      // match: (Move [11] dst src mem)
 -      // result: (MOVLstore [7] dst (MOVLload [7] src mem) (MOVQstore dst (MOVQload src mem) mem))
 +}
 +func rewriteValueAMD64_OpBroadcast512MaskedInt64x2(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (Broadcast512MaskedInt64x2 x mask)
 +      // result: (VPBROADCASTQMasked512 x (VPMOVVec64x2ToM <types.TypeMask> mask))
        for {
 -              if auxIntToInt64(v.AuxInt) != 11 {
 -                      break
 -              }
 -              dst := v_0
 -              src := v_1
 -              mem := v_2
 -              v.reset(OpAMD64MOVLstore)
 -              v.AuxInt = int32ToAuxInt(7)
 -              v0 := b.NewValue0(v.Pos, OpAMD64MOVLload, typ.UInt32)
 -              v0.AuxInt = int32ToAuxInt(7)
 -              v0.AddArg2(src, mem)
 -              v1 := b.NewValue0(v.Pos, OpAMD64MOVQstore, types.TypeMem)
 -              v2 := b.NewValue0(v.Pos, OpAMD64MOVQload, typ.UInt64)
 -              v2.AddArg2(src, mem)
 -              v1.AddArg3(dst, v2, mem)
 -              v.AddArg3(dst, v0, v1)
 +              x := v_0
 +              mask := v_1
 +              v.reset(OpAMD64VPBROADCASTQMasked512)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x2ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg2(x, v0)
                return true
        }
 -      // match: (Move [12] dst src mem)
 -      // result: (MOVLstore [8] dst (MOVLload [8] src mem) (MOVQstore dst (MOVQload src mem) mem))
 +}
 +func rewriteValueAMD64_OpBroadcast512MaskedInt8x16(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (Broadcast512MaskedInt8x16 x mask)
 +      // result: (VPBROADCASTBMasked512 x (VPMOVVec8x16ToM <types.TypeMask> mask))
        for {
 -              if auxIntToInt64(v.AuxInt) != 12 {
 -                      break
 -              }
 -              dst := v_0
 -              src := v_1
 -              mem := v_2
 -              v.reset(OpAMD64MOVLstore)
 -              v.AuxInt = int32ToAuxInt(8)
 -              v0 := b.NewValue0(v.Pos, OpAMD64MOVLload, typ.UInt32)
 -              v0.AuxInt = int32ToAuxInt(8)
 -              v0.AddArg2(src, mem)
 -              v1 := b.NewValue0(v.Pos, OpAMD64MOVQstore, types.TypeMem)
 -              v2 := b.NewValue0(v.Pos, OpAMD64MOVQload, typ.UInt64)
 -              v2.AddArg2(src, mem)
 -              v1.AddArg3(dst, v2, mem)
 -              v.AddArg3(dst, v0, v1)
 +              x := v_0
 +              mask := v_1
 +              v.reset(OpAMD64VPBROADCASTBMasked512)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec8x16ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg2(x, v0)
                return true
        }
 -      // match: (Move [s] dst src mem)
 -      // cond: s >= 13 && s <= 15
 -      // result: (MOVQstore [int32(s-8)] dst (MOVQload [int32(s-8)] src mem) (MOVQstore dst (MOVQload src mem) mem))
 +}
 +func rewriteValueAMD64_OpBroadcast512MaskedUint16x8(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (Broadcast512MaskedUint16x8 x mask)
 +      // result: (VPBROADCASTWMasked512 x (VPMOVVec16x8ToM <types.TypeMask> mask))
        for {
 -              s := auxIntToInt64(v.AuxInt)
 -              dst := v_0
 -              src := v_1
 -              mem := v_2
 -              if !(s >= 13 && s <= 15) {
 -                      break
 -              }
 -              v.reset(OpAMD64MOVQstore)
 -              v.AuxInt = int32ToAuxInt(int32(s - 8))
 -              v0 := b.NewValue0(v.Pos, OpAMD64MOVQload, typ.UInt64)
 -              v0.AuxInt = int32ToAuxInt(int32(s - 8))
 -              v0.AddArg2(src, mem)
 -              v1 := b.NewValue0(v.Pos, OpAMD64MOVQstore, types.TypeMem)
 -              v2 := b.NewValue0(v.Pos, OpAMD64MOVQload, typ.UInt64)
 -              v2.AddArg2(src, mem)
 -              v1.AddArg3(dst, v2, mem)
 -              v.AddArg3(dst, v0, v1)
 +              x := v_0
 +              mask := v_1
 +              v.reset(OpAMD64VPBROADCASTWMasked512)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x8ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg2(x, v0)
                return true
        }
 -      // match: (Move [s] dst src mem)
 -      // cond: s > 16 && s < 192 && logLargeCopy(v, s)
 -      // result: (LoweredMove [s] dst src mem)
 +}
 +func rewriteValueAMD64_OpBroadcast512MaskedUint32x4(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (Broadcast512MaskedUint32x4 x mask)
 +      // result: (VPBROADCASTDMasked512 x (VPMOVVec32x4ToM <types.TypeMask> mask))
        for {
 -              s := auxIntToInt64(v.AuxInt)
 -              dst := v_0
 -              src := v_1
 -              mem := v_2
 -              if !(s > 16 && s < 192 && logLargeCopy(v, s)) {
 -                      break
 -              }
 -              v.reset(OpAMD64LoweredMove)
 -              v.AuxInt = int64ToAuxInt(s)
 -              v.AddArg3(dst, src, mem)
 +              x := v_0
 +              mask := v_1
 +              v.reset(OpAMD64VPBROADCASTDMasked512)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x4ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg2(x, v0)
                return true
        }
 -      // match: (Move [s] dst src mem)
 -      // cond: s >= 192 && s <= repMoveThreshold && logLargeCopy(v, s)
 -      // result: (LoweredMoveLoop [s] dst src mem)
 +}
 +func rewriteValueAMD64_OpBroadcast512MaskedUint64x2(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (Broadcast512MaskedUint64x2 x mask)
 +      // result: (VPBROADCASTQMasked512 x (VPMOVVec64x2ToM <types.TypeMask> mask))
        for {
 -              s := auxIntToInt64(v.AuxInt)
 -              dst := v_0
 -              src := v_1
 -              mem := v_2
 -              if !(s >= 192 && s <= repMoveThreshold && logLargeCopy(v, s)) {
 -                      break
 -              }
 -              v.reset(OpAMD64LoweredMoveLoop)
 -              v.AuxInt = int64ToAuxInt(s)
 -              v.AddArg3(dst, src, mem)
 +              x := v_0
 +              mask := v_1
 +              v.reset(OpAMD64VPBROADCASTQMasked512)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x2ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg2(x, v0)
                return true
        }
 -      // match: (Move [s] dst src mem)
 -      // cond: s > repMoveThreshold && s%8 != 0
 -      // result: (Move [s-s%8] (OffPtr <dst.Type> dst [s%8]) (OffPtr <src.Type> src [s%8]) (MOVQstore dst (MOVQload src mem) mem))
 +}
 +func rewriteValueAMD64_OpBroadcast512MaskedUint8x16(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (Broadcast512MaskedUint8x16 x mask)
 +      // result: (VPBROADCASTBMasked512 x (VPMOVVec8x16ToM <types.TypeMask> mask))
        for {
 -              s := auxIntToInt64(v.AuxInt)
 -              dst := v_0
 -              src := v_1
 +              x := v_0
 +              mask := v_1
 +              v.reset(OpAMD64VPBROADCASTBMasked512)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec8x16ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg2(x, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpBswap16(v *Value) bool {
 +      v_0 := v.Args[0]
 +      // match: (Bswap16 x)
 +      // result: (ROLWconst [8] x)
 +      for {
 +              x := v_0
 +              v.reset(OpAMD64ROLWconst)
 +              v.AuxInt = int8ToAuxInt(8)
 +              v.AddArg(x)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpCeil(v *Value) bool {
 +      v_0 := v.Args[0]
 +      // match: (Ceil x)
 +      // result: (ROUNDSD [2] x)
 +      for {
 +              x := v_0
 +              v.reset(OpAMD64ROUNDSD)
 +              v.AuxInt = int8ToAuxInt(2)
 +              v.AddArg(x)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpCeilFloat32x4(v *Value) bool {
 +      v_0 := v.Args[0]
 +      // match: (CeilFloat32x4 x)
 +      // result: (VROUNDPS128 [2] x)
 +      for {
 +              x := v_0
 +              v.reset(OpAMD64VROUNDPS128)
 +              v.AuxInt = uint8ToAuxInt(2)
 +              v.AddArg(x)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpCeilFloat32x8(v *Value) bool {
 +      v_0 := v.Args[0]
 +      // match: (CeilFloat32x8 x)
 +      // result: (VROUNDPS256 [2] x)
 +      for {
 +              x := v_0
 +              v.reset(OpAMD64VROUNDPS256)
 +              v.AuxInt = uint8ToAuxInt(2)
 +              v.AddArg(x)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpCeilFloat64x2(v *Value) bool {
 +      v_0 := v.Args[0]
 +      // match: (CeilFloat64x2 x)
 +      // result: (VROUNDPD128 [2] x)
 +      for {
 +              x := v_0
 +              v.reset(OpAMD64VROUNDPD128)
 +              v.AuxInt = uint8ToAuxInt(2)
 +              v.AddArg(x)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpCeilFloat64x4(v *Value) bool {
 +      v_0 := v.Args[0]
 +      // match: (CeilFloat64x4 x)
 +      // result: (VROUNDPD256 [2] x)
 +      for {
 +              x := v_0
 +              v.reset(OpAMD64VROUNDPD256)
 +              v.AuxInt = uint8ToAuxInt(2)
 +              v.AddArg(x)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpCeilScaledFloat32x16(v *Value) bool {
 +      v_0 := v.Args[0]
 +      // match: (CeilScaledFloat32x16 [a] x)
 +      // result: (VRNDSCALEPS512 [a+2] x)
 +      for {
 +              a := auxIntToUint8(v.AuxInt)
 +              x := v_0
 +              v.reset(OpAMD64VRNDSCALEPS512)
 +              v.AuxInt = uint8ToAuxInt(a + 2)
 +              v.AddArg(x)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpCeilScaledFloat32x4(v *Value) bool {
 +      v_0 := v.Args[0]
 +      // match: (CeilScaledFloat32x4 [a] x)
 +      // result: (VRNDSCALEPS128 [a+2] x)
 +      for {
 +              a := auxIntToUint8(v.AuxInt)
 +              x := v_0
 +              v.reset(OpAMD64VRNDSCALEPS128)
 +              v.AuxInt = uint8ToAuxInt(a + 2)
 +              v.AddArg(x)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpCeilScaledFloat32x8(v *Value) bool {
 +      v_0 := v.Args[0]
 +      // match: (CeilScaledFloat32x8 [a] x)
 +      // result: (VRNDSCALEPS256 [a+2] x)
 +      for {
 +              a := auxIntToUint8(v.AuxInt)
 +              x := v_0
 +              v.reset(OpAMD64VRNDSCALEPS256)
 +              v.AuxInt = uint8ToAuxInt(a + 2)
 +              v.AddArg(x)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpCeilScaledFloat64x2(v *Value) bool {
 +      v_0 := v.Args[0]
 +      // match: (CeilScaledFloat64x2 [a] x)
 +      // result: (VRNDSCALEPD128 [a+2] x)
 +      for {
 +              a := auxIntToUint8(v.AuxInt)
 +              x := v_0
 +              v.reset(OpAMD64VRNDSCALEPD128)
 +              v.AuxInt = uint8ToAuxInt(a + 2)
 +              v.AddArg(x)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpCeilScaledFloat64x4(v *Value) bool {
 +      v_0 := v.Args[0]
 +      // match: (CeilScaledFloat64x4 [a] x)
 +      // result: (VRNDSCALEPD256 [a+2] x)
 +      for {
 +              a := auxIntToUint8(v.AuxInt)
 +              x := v_0
 +              v.reset(OpAMD64VRNDSCALEPD256)
 +              v.AuxInt = uint8ToAuxInt(a + 2)
 +              v.AddArg(x)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpCeilScaledFloat64x8(v *Value) bool {
 +      v_0 := v.Args[0]
 +      // match: (CeilScaledFloat64x8 [a] x)
 +      // result: (VRNDSCALEPD512 [a+2] x)
 +      for {
 +              a := auxIntToUint8(v.AuxInt)
 +              x := v_0
 +              v.reset(OpAMD64VRNDSCALEPD512)
 +              v.AuxInt = uint8ToAuxInt(a + 2)
 +              v.AddArg(x)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpCeilScaledMaskedFloat32x16(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (CeilScaledMaskedFloat32x16 [a] x mask)
 +      // result: (VRNDSCALEPSMasked512 [a+2] x (VPMOVVec32x16ToM <types.TypeMask> mask))
 +      for {
 +              a := auxIntToUint8(v.AuxInt)
 +              x := v_0
 +              mask := v_1
 +              v.reset(OpAMD64VRNDSCALEPSMasked512)
 +              v.AuxInt = uint8ToAuxInt(a + 2)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x16ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg2(x, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpCeilScaledMaskedFloat32x4(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (CeilScaledMaskedFloat32x4 [a] x mask)
 +      // result: (VRNDSCALEPSMasked128 [a+2] x (VPMOVVec32x4ToM <types.TypeMask> mask))
 +      for {
 +              a := auxIntToUint8(v.AuxInt)
 +              x := v_0
 +              mask := v_1
 +              v.reset(OpAMD64VRNDSCALEPSMasked128)
 +              v.AuxInt = uint8ToAuxInt(a + 2)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x4ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg2(x, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpCeilScaledMaskedFloat32x8(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (CeilScaledMaskedFloat32x8 [a] x mask)
 +      // result: (VRNDSCALEPSMasked256 [a+2] x (VPMOVVec32x8ToM <types.TypeMask> mask))
 +      for {
 +              a := auxIntToUint8(v.AuxInt)
 +              x := v_0
 +              mask := v_1
 +              v.reset(OpAMD64VRNDSCALEPSMasked256)
 +              v.AuxInt = uint8ToAuxInt(a + 2)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x8ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg2(x, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpCeilScaledMaskedFloat64x2(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (CeilScaledMaskedFloat64x2 [a] x mask)
 +      // result: (VRNDSCALEPDMasked128 [a+2] x (VPMOVVec64x2ToM <types.TypeMask> mask))
 +      for {
 +              a := auxIntToUint8(v.AuxInt)
 +              x := v_0
 +              mask := v_1
 +              v.reset(OpAMD64VRNDSCALEPDMasked128)
 +              v.AuxInt = uint8ToAuxInt(a + 2)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x2ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg2(x, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpCeilScaledMaskedFloat64x4(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (CeilScaledMaskedFloat64x4 [a] x mask)
 +      // result: (VRNDSCALEPDMasked256 [a+2] x (VPMOVVec64x4ToM <types.TypeMask> mask))
 +      for {
 +              a := auxIntToUint8(v.AuxInt)
 +              x := v_0
 +              mask := v_1
 +              v.reset(OpAMD64VRNDSCALEPDMasked256)
 +              v.AuxInt = uint8ToAuxInt(a + 2)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x4ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg2(x, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpCeilScaledMaskedFloat64x8(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (CeilScaledMaskedFloat64x8 [a] x mask)
 +      // result: (VRNDSCALEPDMasked512 [a+2] x (VPMOVVec64x8ToM <types.TypeMask> mask))
 +      for {
 +              a := auxIntToUint8(v.AuxInt)
 +              x := v_0
 +              mask := v_1
 +              v.reset(OpAMD64VRNDSCALEPDMasked512)
 +              v.AuxInt = uint8ToAuxInt(a + 2)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x8ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg2(x, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpCeilScaledResidueFloat32x16(v *Value) bool {
 +      v_0 := v.Args[0]
 +      // match: (CeilScaledResidueFloat32x16 [a] x)
 +      // result: (VREDUCEPS512 [a+2] x)
 +      for {
 +              a := auxIntToUint8(v.AuxInt)
 +              x := v_0
 +              v.reset(OpAMD64VREDUCEPS512)
 +              v.AuxInt = uint8ToAuxInt(a + 2)
 +              v.AddArg(x)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpCeilScaledResidueFloat32x4(v *Value) bool {
 +      v_0 := v.Args[0]
 +      // match: (CeilScaledResidueFloat32x4 [a] x)
 +      // result: (VREDUCEPS128 [a+2] x)
 +      for {
 +              a := auxIntToUint8(v.AuxInt)
 +              x := v_0
 +              v.reset(OpAMD64VREDUCEPS128)
 +              v.AuxInt = uint8ToAuxInt(a + 2)
 +              v.AddArg(x)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpCeilScaledResidueFloat32x8(v *Value) bool {
 +      v_0 := v.Args[0]
 +      // match: (CeilScaledResidueFloat32x8 [a] x)
 +      // result: (VREDUCEPS256 [a+2] x)
 +      for {
 +              a := auxIntToUint8(v.AuxInt)
 +              x := v_0
 +              v.reset(OpAMD64VREDUCEPS256)
 +              v.AuxInt = uint8ToAuxInt(a + 2)
 +              v.AddArg(x)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpCeilScaledResidueFloat64x2(v *Value) bool {
 +      v_0 := v.Args[0]
 +      // match: (CeilScaledResidueFloat64x2 [a] x)
 +      // result: (VREDUCEPD128 [a+2] x)
 +      for {
 +              a := auxIntToUint8(v.AuxInt)
 +              x := v_0
 +              v.reset(OpAMD64VREDUCEPD128)
 +              v.AuxInt = uint8ToAuxInt(a + 2)
 +              v.AddArg(x)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpCeilScaledResidueFloat64x4(v *Value) bool {
 +      v_0 := v.Args[0]
 +      // match: (CeilScaledResidueFloat64x4 [a] x)
 +      // result: (VREDUCEPD256 [a+2] x)
 +      for {
 +              a := auxIntToUint8(v.AuxInt)
 +              x := v_0
 +              v.reset(OpAMD64VREDUCEPD256)
 +              v.AuxInt = uint8ToAuxInt(a + 2)
 +              v.AddArg(x)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpCeilScaledResidueFloat64x8(v *Value) bool {
 +      v_0 := v.Args[0]
 +      // match: (CeilScaledResidueFloat64x8 [a] x)
 +      // result: (VREDUCEPD512 [a+2] x)
 +      for {
 +              a := auxIntToUint8(v.AuxInt)
 +              x := v_0
 +              v.reset(OpAMD64VREDUCEPD512)
 +              v.AuxInt = uint8ToAuxInt(a + 2)
 +              v.AddArg(x)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpCeilScaledResidueMaskedFloat32x16(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (CeilScaledResidueMaskedFloat32x16 [a] x mask)
 +      // result: (VREDUCEPSMasked512 [a+2] x (VPMOVVec32x16ToM <types.TypeMask> mask))
 +      for {
 +              a := auxIntToUint8(v.AuxInt)
 +              x := v_0
 +              mask := v_1
 +              v.reset(OpAMD64VREDUCEPSMasked512)
 +              v.AuxInt = uint8ToAuxInt(a + 2)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x16ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg2(x, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpCeilScaledResidueMaskedFloat32x4(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (CeilScaledResidueMaskedFloat32x4 [a] x mask)
 +      // result: (VREDUCEPSMasked128 [a+2] x (VPMOVVec32x4ToM <types.TypeMask> mask))
 +      for {
 +              a := auxIntToUint8(v.AuxInt)
 +              x := v_0
 +              mask := v_1
 +              v.reset(OpAMD64VREDUCEPSMasked128)
 +              v.AuxInt = uint8ToAuxInt(a + 2)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x4ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg2(x, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpCeilScaledResidueMaskedFloat32x8(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (CeilScaledResidueMaskedFloat32x8 [a] x mask)
 +      // result: (VREDUCEPSMasked256 [a+2] x (VPMOVVec32x8ToM <types.TypeMask> mask))
 +      for {
 +              a := auxIntToUint8(v.AuxInt)
 +              x := v_0
 +              mask := v_1
 +              v.reset(OpAMD64VREDUCEPSMasked256)
 +              v.AuxInt = uint8ToAuxInt(a + 2)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x8ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg2(x, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpCeilScaledResidueMaskedFloat64x2(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (CeilScaledResidueMaskedFloat64x2 [a] x mask)
 +      // result: (VREDUCEPDMasked128 [a+2] x (VPMOVVec64x2ToM <types.TypeMask> mask))
 +      for {
 +              a := auxIntToUint8(v.AuxInt)
 +              x := v_0
 +              mask := v_1
 +              v.reset(OpAMD64VREDUCEPDMasked128)
 +              v.AuxInt = uint8ToAuxInt(a + 2)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x2ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg2(x, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpCeilScaledResidueMaskedFloat64x4(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (CeilScaledResidueMaskedFloat64x4 [a] x mask)
 +      // result: (VREDUCEPDMasked256 [a+2] x (VPMOVVec64x4ToM <types.TypeMask> mask))
 +      for {
 +              a := auxIntToUint8(v.AuxInt)
 +              x := v_0
 +              mask := v_1
 +              v.reset(OpAMD64VREDUCEPDMasked256)
 +              v.AuxInt = uint8ToAuxInt(a + 2)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x4ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg2(x, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpCeilScaledResidueMaskedFloat64x8(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (CeilScaledResidueMaskedFloat64x8 [a] x mask)
 +      // result: (VREDUCEPDMasked512 [a+2] x (VPMOVVec64x8ToM <types.TypeMask> mask))
 +      for {
 +              a := auxIntToUint8(v.AuxInt)
 +              x := v_0
 +              mask := v_1
 +              v.reset(OpAMD64VREDUCEPDMasked512)
 +              v.AuxInt = uint8ToAuxInt(a + 2)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x8ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg2(x, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpCompressFloat32x16(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (CompressFloat32x16 x mask)
 +      // result: (VCOMPRESSPSMasked512 x (VPMOVVec32x16ToM <types.TypeMask> mask))
 +      for {
 +              x := v_0
 +              mask := v_1
 +              v.reset(OpAMD64VCOMPRESSPSMasked512)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x16ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg2(x, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpCompressFloat32x4(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (CompressFloat32x4 x mask)
 +      // result: (VCOMPRESSPSMasked128 x (VPMOVVec32x4ToM <types.TypeMask> mask))
 +      for {
 +              x := v_0
 +              mask := v_1
 +              v.reset(OpAMD64VCOMPRESSPSMasked128)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x4ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg2(x, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpCompressFloat32x8(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (CompressFloat32x8 x mask)
 +      // result: (VCOMPRESSPSMasked256 x (VPMOVVec32x8ToM <types.TypeMask> mask))
 +      for {
 +              x := v_0
 +              mask := v_1
 +              v.reset(OpAMD64VCOMPRESSPSMasked256)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x8ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg2(x, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpCompressFloat64x2(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (CompressFloat64x2 x mask)
 +      // result: (VCOMPRESSPDMasked128 x (VPMOVVec64x2ToM <types.TypeMask> mask))
 +      for {
 +              x := v_0
 +              mask := v_1
 +              v.reset(OpAMD64VCOMPRESSPDMasked128)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x2ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg2(x, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpCompressFloat64x4(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (CompressFloat64x4 x mask)
 +      // result: (VCOMPRESSPDMasked256 x (VPMOVVec64x4ToM <types.TypeMask> mask))
 +      for {
 +              x := v_0
 +              mask := v_1
 +              v.reset(OpAMD64VCOMPRESSPDMasked256)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x4ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg2(x, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpCompressFloat64x8(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (CompressFloat64x8 x mask)
 +      // result: (VCOMPRESSPDMasked512 x (VPMOVVec64x8ToM <types.TypeMask> mask))
 +      for {
 +              x := v_0
 +              mask := v_1
 +              v.reset(OpAMD64VCOMPRESSPDMasked512)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x8ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg2(x, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpCompressInt16x16(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (CompressInt16x16 x mask)
 +      // result: (VPCOMPRESSWMasked256 x (VPMOVVec16x16ToM <types.TypeMask> mask))
 +      for {
 +              x := v_0
 +              mask := v_1
 +              v.reset(OpAMD64VPCOMPRESSWMasked256)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x16ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg2(x, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpCompressInt16x32(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (CompressInt16x32 x mask)
 +      // result: (VPCOMPRESSWMasked512 x (VPMOVVec16x32ToM <types.TypeMask> mask))
 +      for {
 +              x := v_0
 +              mask := v_1
 +              v.reset(OpAMD64VPCOMPRESSWMasked512)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x32ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg2(x, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpCompressInt16x8(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (CompressInt16x8 x mask)
 +      // result: (VPCOMPRESSWMasked128 x (VPMOVVec16x8ToM <types.TypeMask> mask))
 +      for {
 +              x := v_0
 +              mask := v_1
 +              v.reset(OpAMD64VPCOMPRESSWMasked128)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x8ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg2(x, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpCompressInt32x16(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (CompressInt32x16 x mask)
 +      // result: (VPCOMPRESSDMasked512 x (VPMOVVec32x16ToM <types.TypeMask> mask))
 +      for {
 +              x := v_0
 +              mask := v_1
 +              v.reset(OpAMD64VPCOMPRESSDMasked512)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x16ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg2(x, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpCompressInt32x4(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (CompressInt32x4 x mask)
 +      // result: (VPCOMPRESSDMasked128 x (VPMOVVec32x4ToM <types.TypeMask> mask))
 +      for {
 +              x := v_0
 +              mask := v_1
 +              v.reset(OpAMD64VPCOMPRESSDMasked128)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x4ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg2(x, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpCompressInt32x8(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (CompressInt32x8 x mask)
 +      // result: (VPCOMPRESSDMasked256 x (VPMOVVec32x8ToM <types.TypeMask> mask))
 +      for {
 +              x := v_0
 +              mask := v_1
 +              v.reset(OpAMD64VPCOMPRESSDMasked256)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x8ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg2(x, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpCompressInt64x2(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (CompressInt64x2 x mask)
 +      // result: (VPCOMPRESSQMasked128 x (VPMOVVec64x2ToM <types.TypeMask> mask))
 +      for {
 +              x := v_0
 +              mask := v_1
 +              v.reset(OpAMD64VPCOMPRESSQMasked128)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x2ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg2(x, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpCompressInt64x4(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (CompressInt64x4 x mask)
 +      // result: (VPCOMPRESSQMasked256 x (VPMOVVec64x4ToM <types.TypeMask> mask))
 +      for {
 +              x := v_0
 +              mask := v_1
 +              v.reset(OpAMD64VPCOMPRESSQMasked256)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x4ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg2(x, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpCompressInt64x8(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (CompressInt64x8 x mask)
 +      // result: (VPCOMPRESSQMasked512 x (VPMOVVec64x8ToM <types.TypeMask> mask))
 +      for {
 +              x := v_0
 +              mask := v_1
 +              v.reset(OpAMD64VPCOMPRESSQMasked512)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x8ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg2(x, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpCompressInt8x16(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (CompressInt8x16 x mask)
 +      // result: (VPCOMPRESSBMasked128 x (VPMOVVec8x16ToM <types.TypeMask> mask))
 +      for {
 +              x := v_0
 +              mask := v_1
 +              v.reset(OpAMD64VPCOMPRESSBMasked128)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec8x16ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg2(x, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpCompressInt8x32(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (CompressInt8x32 x mask)
 +      // result: (VPCOMPRESSBMasked256 x (VPMOVVec8x32ToM <types.TypeMask> mask))
 +      for {
 +              x := v_0
 +              mask := v_1
 +              v.reset(OpAMD64VPCOMPRESSBMasked256)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec8x32ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg2(x, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpCompressInt8x64(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (CompressInt8x64 x mask)
 +      // result: (VPCOMPRESSBMasked512 x (VPMOVVec8x64ToM <types.TypeMask> mask))
 +      for {
 +              x := v_0
 +              mask := v_1
 +              v.reset(OpAMD64VPCOMPRESSBMasked512)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec8x64ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg2(x, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpCompressUint16x16(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (CompressUint16x16 x mask)
 +      // result: (VPCOMPRESSWMasked256 x (VPMOVVec16x16ToM <types.TypeMask> mask))
 +      for {
 +              x := v_0
 +              mask := v_1
 +              v.reset(OpAMD64VPCOMPRESSWMasked256)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x16ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg2(x, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpCompressUint16x32(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (CompressUint16x32 x mask)
 +      // result: (VPCOMPRESSWMasked512 x (VPMOVVec16x32ToM <types.TypeMask> mask))
 +      for {
 +              x := v_0
 +              mask := v_1
 +              v.reset(OpAMD64VPCOMPRESSWMasked512)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x32ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg2(x, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpCompressUint16x8(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (CompressUint16x8 x mask)
 +      // result: (VPCOMPRESSWMasked128 x (VPMOVVec16x8ToM <types.TypeMask> mask))
 +      for {
 +              x := v_0
 +              mask := v_1
 +              v.reset(OpAMD64VPCOMPRESSWMasked128)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x8ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg2(x, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpCompressUint32x16(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (CompressUint32x16 x mask)
 +      // result: (VPCOMPRESSDMasked512 x (VPMOVVec32x16ToM <types.TypeMask> mask))
 +      for {
 +              x := v_0
 +              mask := v_1
 +              v.reset(OpAMD64VPCOMPRESSDMasked512)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x16ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg2(x, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpCompressUint32x4(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (CompressUint32x4 x mask)
 +      // result: (VPCOMPRESSDMasked128 x (VPMOVVec32x4ToM <types.TypeMask> mask))
 +      for {
 +              x := v_0
 +              mask := v_1
 +              v.reset(OpAMD64VPCOMPRESSDMasked128)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x4ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg2(x, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpCompressUint32x8(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (CompressUint32x8 x mask)
 +      // result: (VPCOMPRESSDMasked256 x (VPMOVVec32x8ToM <types.TypeMask> mask))
 +      for {
 +              x := v_0
 +              mask := v_1
 +              v.reset(OpAMD64VPCOMPRESSDMasked256)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x8ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg2(x, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpCompressUint64x2(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (CompressUint64x2 x mask)
 +      // result: (VPCOMPRESSQMasked128 x (VPMOVVec64x2ToM <types.TypeMask> mask))
 +      for {
 +              x := v_0
 +              mask := v_1
 +              v.reset(OpAMD64VPCOMPRESSQMasked128)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x2ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg2(x, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpCompressUint64x4(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (CompressUint64x4 x mask)
 +      // result: (VPCOMPRESSQMasked256 x (VPMOVVec64x4ToM <types.TypeMask> mask))
 +      for {
 +              x := v_0
 +              mask := v_1
 +              v.reset(OpAMD64VPCOMPRESSQMasked256)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x4ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg2(x, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpCompressUint64x8(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (CompressUint64x8 x mask)
 +      // result: (VPCOMPRESSQMasked512 x (VPMOVVec64x8ToM <types.TypeMask> mask))
 +      for {
 +              x := v_0
 +              mask := v_1
 +              v.reset(OpAMD64VPCOMPRESSQMasked512)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x8ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg2(x, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpCompressUint8x16(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (CompressUint8x16 x mask)
 +      // result: (VPCOMPRESSBMasked128 x (VPMOVVec8x16ToM <types.TypeMask> mask))
 +      for {
 +              x := v_0
 +              mask := v_1
 +              v.reset(OpAMD64VPCOMPRESSBMasked128)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec8x16ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg2(x, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpCompressUint8x32(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (CompressUint8x32 x mask)
 +      // result: (VPCOMPRESSBMasked256 x (VPMOVVec8x32ToM <types.TypeMask> mask))
 +      for {
 +              x := v_0
 +              mask := v_1
 +              v.reset(OpAMD64VPCOMPRESSBMasked256)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec8x32ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg2(x, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpCompressUint8x64(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (CompressUint8x64 x mask)
 +      // result: (VPCOMPRESSBMasked512 x (VPMOVVec8x64ToM <types.TypeMask> mask))
 +      for {
 +              x := v_0
 +              mask := v_1
 +              v.reset(OpAMD64VPCOMPRESSBMasked512)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec8x64ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg2(x, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpCondSelect(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      typ := &b.Func.Config.Types
 +      // match: (CondSelect <t> x y (SETEQ cond))
 +      // cond: (is64BitInt(t) || isPtr(t))
 +      // result: (CMOVQEQ y x cond)
 +      for {
 +              t := v.Type
 +              x := v_0
 +              y := v_1
 +              if v_2.Op != OpAMD64SETEQ {
 +                      break
 +              }
 +              cond := v_2.Args[0]
 +              if !(is64BitInt(t) || isPtr(t)) {
 +                      break
 +              }
 +              v.reset(OpAMD64CMOVQEQ)
 +              v.AddArg3(y, x, cond)
 +              return true
 +      }
 +      // match: (CondSelect <t> x y (SETNE cond))
 +      // cond: (is64BitInt(t) || isPtr(t))
 +      // result: (CMOVQNE y x cond)
 +      for {
 +              t := v.Type
 +              x := v_0
 +              y := v_1
 +              if v_2.Op != OpAMD64SETNE {
 +                      break
 +              }
 +              cond := v_2.Args[0]
 +              if !(is64BitInt(t) || isPtr(t)) {
 +                      break
 +              }
 +              v.reset(OpAMD64CMOVQNE)
 +              v.AddArg3(y, x, cond)
 +              return true
 +      }
 +      // match: (CondSelect <t> x y (SETL cond))
 +      // cond: (is64BitInt(t) || isPtr(t))
 +      // result: (CMOVQLT y x cond)
 +      for {
 +              t := v.Type
 +              x := v_0
 +              y := v_1
 +              if v_2.Op != OpAMD64SETL {
 +                      break
 +              }
 +              cond := v_2.Args[0]
 +              if !(is64BitInt(t) || isPtr(t)) {
 +                      break
 +              }
 +              v.reset(OpAMD64CMOVQLT)
 +              v.AddArg3(y, x, cond)
 +              return true
 +      }
 +      // match: (CondSelect <t> x y (SETG cond))
 +      // cond: (is64BitInt(t) || isPtr(t))
 +      // result: (CMOVQGT y x cond)
 +      for {
 +              t := v.Type
 +              x := v_0
 +              y := v_1
 +              if v_2.Op != OpAMD64SETG {
 +                      break
 +              }
 +              cond := v_2.Args[0]
 +              if !(is64BitInt(t) || isPtr(t)) {
 +                      break
 +              }
 +              v.reset(OpAMD64CMOVQGT)
 +              v.AddArg3(y, x, cond)
 +              return true
 +      }
 +      // match: (CondSelect <t> x y (SETLE cond))
 +      // cond: (is64BitInt(t) || isPtr(t))
 +      // result: (CMOVQLE y x cond)
 +      for {
 +              t := v.Type
 +              x := v_0
 +              y := v_1
 +              if v_2.Op != OpAMD64SETLE {
 +                      break
 +              }
 +              cond := v_2.Args[0]
 +              if !(is64BitInt(t) || isPtr(t)) {
 +                      break
 +              }
 +              v.reset(OpAMD64CMOVQLE)
 +              v.AddArg3(y, x, cond)
 +              return true
 +      }
 +      // match: (CondSelect <t> x y (SETGE cond))
 +      // cond: (is64BitInt(t) || isPtr(t))
 +      // result: (CMOVQGE y x cond)
 +      for {
 +              t := v.Type
 +              x := v_0
 +              y := v_1
 +              if v_2.Op != OpAMD64SETGE {
 +                      break
 +              }
 +              cond := v_2.Args[0]
 +              if !(is64BitInt(t) || isPtr(t)) {
 +                      break
 +              }
 +              v.reset(OpAMD64CMOVQGE)
 +              v.AddArg3(y, x, cond)
 +              return true
 +      }
 +      // match: (CondSelect <t> x y (SETA cond))
 +      // cond: (is64BitInt(t) || isPtr(t))
 +      // result: (CMOVQHI y x cond)
 +      for {
 +              t := v.Type
 +              x := v_0
 +              y := v_1
 +              if v_2.Op != OpAMD64SETA {
 +                      break
 +              }
 +              cond := v_2.Args[0]
 +              if !(is64BitInt(t) || isPtr(t)) {
 +                      break
 +              }
 +              v.reset(OpAMD64CMOVQHI)
 +              v.AddArg3(y, x, cond)
 +              return true
 +      }
 +      // match: (CondSelect <t> x y (SETB cond))
 +      // cond: (is64BitInt(t) || isPtr(t))
 +      // result: (CMOVQCS y x cond)
 +      for {
 +              t := v.Type
 +              x := v_0
 +              y := v_1
 +              if v_2.Op != OpAMD64SETB {
 +                      break
 +              }
 +              cond := v_2.Args[0]
 +              if !(is64BitInt(t) || isPtr(t)) {
 +                      break
 +              }
 +              v.reset(OpAMD64CMOVQCS)
 +              v.AddArg3(y, x, cond)
 +              return true
 +      }
 +      // match: (CondSelect <t> x y (SETAE cond))
 +      // cond: (is64BitInt(t) || isPtr(t))
 +      // result: (CMOVQCC y x cond)
 +      for {
 +              t := v.Type
 +              x := v_0
 +              y := v_1
 +              if v_2.Op != OpAMD64SETAE {
 +                      break
 +              }
 +              cond := v_2.Args[0]
 +              if !(is64BitInt(t) || isPtr(t)) {
 +                      break
 +              }
 +              v.reset(OpAMD64CMOVQCC)
 +              v.AddArg3(y, x, cond)
 +              return true
 +      }
 +      // match: (CondSelect <t> x y (SETBE cond))
 +      // cond: (is64BitInt(t) || isPtr(t))
 +      // result: (CMOVQLS y x cond)
 +      for {
 +              t := v.Type
 +              x := v_0
 +              y := v_1
 +              if v_2.Op != OpAMD64SETBE {
 +                      break
 +              }
 +              cond := v_2.Args[0]
 +              if !(is64BitInt(t) || isPtr(t)) {
 +                      break
 +              }
 +              v.reset(OpAMD64CMOVQLS)
 +              v.AddArg3(y, x, cond)
 +              return true
 +      }
 +      // match: (CondSelect <t> x y (SETEQF cond))
 +      // cond: (is64BitInt(t) || isPtr(t))
 +      // result: (CMOVQEQF y x cond)
 +      for {
 +              t := v.Type
 +              x := v_0
 +              y := v_1
 +              if v_2.Op != OpAMD64SETEQF {
 +                      break
 +              }
 +              cond := v_2.Args[0]
 +              if !(is64BitInt(t) || isPtr(t)) {
 +                      break
 +              }
 +              v.reset(OpAMD64CMOVQEQF)
 +              v.AddArg3(y, x, cond)
 +              return true
 +      }
 +      // match: (CondSelect <t> x y (SETNEF cond))
 +      // cond: (is64BitInt(t) || isPtr(t))
 +      // result: (CMOVQNEF y x cond)
 +      for {
 +              t := v.Type
 +              x := v_0
 +              y := v_1
 +              if v_2.Op != OpAMD64SETNEF {
 +                      break
 +              }
 +              cond := v_2.Args[0]
 +              if !(is64BitInt(t) || isPtr(t)) {
 +                      break
 +              }
 +              v.reset(OpAMD64CMOVQNEF)
 +              v.AddArg3(y, x, cond)
 +              return true
 +      }
 +      // match: (CondSelect <t> x y (SETGF cond))
 +      // cond: (is64BitInt(t) || isPtr(t))
 +      // result: (CMOVQGTF y x cond)
 +      for {
 +              t := v.Type
 +              x := v_0
 +              y := v_1
 +              if v_2.Op != OpAMD64SETGF {
 +                      break
 +              }
 +              cond := v_2.Args[0]
 +              if !(is64BitInt(t) || isPtr(t)) {
 +                      break
 +              }
 +              v.reset(OpAMD64CMOVQGTF)
 +              v.AddArg3(y, x, cond)
 +              return true
 +      }
 +      // match: (CondSelect <t> x y (SETGEF cond))
 +      // cond: (is64BitInt(t) || isPtr(t))
 +      // result: (CMOVQGEF y x cond)
 +      for {
 +              t := v.Type
 +              x := v_0
 +              y := v_1
 +              if v_2.Op != OpAMD64SETGEF {
 +                      break
 +              }
 +              cond := v_2.Args[0]
 +              if !(is64BitInt(t) || isPtr(t)) {
 +                      break
 +              }
 +              v.reset(OpAMD64CMOVQGEF)
 +              v.AddArg3(y, x, cond)
 +              return true
 +      }
 +      // match: (CondSelect <t> x y (SETEQ cond))
 +      // cond: is32BitInt(t)
 +      // result: (CMOVLEQ y x cond)
 +      for {
 +              t := v.Type
 +              x := v_0
 +              y := v_1
 +              if v_2.Op != OpAMD64SETEQ {
 +                      break
 +              }
 +              cond := v_2.Args[0]
 +              if !(is32BitInt(t)) {
 +                      break
 +              }
 +              v.reset(OpAMD64CMOVLEQ)
 +              v.AddArg3(y, x, cond)
 +              return true
 +      }
 +      // match: (CondSelect <t> x y (SETNE cond))
 +      // cond: is32BitInt(t)
 +      // result: (CMOVLNE y x cond)
 +      for {
 +              t := v.Type
 +              x := v_0
 +              y := v_1
 +              if v_2.Op != OpAMD64SETNE {
 +                      break
 +              }
 +              cond := v_2.Args[0]
 +              if !(is32BitInt(t)) {
 +                      break
 +              }
 +              v.reset(OpAMD64CMOVLNE)
 +              v.AddArg3(y, x, cond)
 +              return true
 +      }
 +      // match: (CondSelect <t> x y (SETL cond))
 +      // cond: is32BitInt(t)
 +      // result: (CMOVLLT y x cond)
 +      for {
 +              t := v.Type
 +              x := v_0
 +              y := v_1
 +              if v_2.Op != OpAMD64SETL {
 +                      break
 +              }
 +              cond := v_2.Args[0]
 +              if !(is32BitInt(t)) {
 +                      break
 +              }
 +              v.reset(OpAMD64CMOVLLT)
 +              v.AddArg3(y, x, cond)
 +              return true
 +      }
 +      // match: (CondSelect <t> x y (SETG cond))
 +      // cond: is32BitInt(t)
 +      // result: (CMOVLGT y x cond)
 +      for {
 +              t := v.Type
 +              x := v_0
 +              y := v_1
 +              if v_2.Op != OpAMD64SETG {
 +                      break
 +              }
 +              cond := v_2.Args[0]
 +              if !(is32BitInt(t)) {
 +                      break
 +              }
 +              v.reset(OpAMD64CMOVLGT)
 +              v.AddArg3(y, x, cond)
 +              return true
 +      }
 +      // match: (CondSelect <t> x y (SETLE cond))
 +      // cond: is32BitInt(t)
 +      // result: (CMOVLLE y x cond)
 +      for {
 +              t := v.Type
 +              x := v_0
 +              y := v_1
 +              if v_2.Op != OpAMD64SETLE {
 +                      break
 +              }
 +              cond := v_2.Args[0]
 +              if !(is32BitInt(t)) {
 +                      break
 +              }
 +              v.reset(OpAMD64CMOVLLE)
 +              v.AddArg3(y, x, cond)
 +              return true
 +      }
 +      // match: (CondSelect <t> x y (SETGE cond))
 +      // cond: is32BitInt(t)
 +      // result: (CMOVLGE y x cond)
 +      for {
 +              t := v.Type
 +              x := v_0
 +              y := v_1
 +              if v_2.Op != OpAMD64SETGE {
 +                      break
 +              }
 +              cond := v_2.Args[0]
 +              if !(is32BitInt(t)) {
 +                      break
 +              }
 +              v.reset(OpAMD64CMOVLGE)
 +              v.AddArg3(y, x, cond)
 +              return true
 +      }
 +      // match: (CondSelect <t> x y (SETA cond))
 +      // cond: is32BitInt(t)
 +      // result: (CMOVLHI y x cond)
 +      for {
 +              t := v.Type
 +              x := v_0
 +              y := v_1
 +              if v_2.Op != OpAMD64SETA {
 +                      break
 +              }
 +              cond := v_2.Args[0]
 +              if !(is32BitInt(t)) {
 +                      break
 +              }
 +              v.reset(OpAMD64CMOVLHI)
 +              v.AddArg3(y, x, cond)
 +              return true
 +      }
 +      // match: (CondSelect <t> x y (SETB cond))
 +      // cond: is32BitInt(t)
 +      // result: (CMOVLCS y x cond)
 +      for {
 +              t := v.Type
 +              x := v_0
 +              y := v_1
 +              if v_2.Op != OpAMD64SETB {
 +                      break
 +              }
 +              cond := v_2.Args[0]
 +              if !(is32BitInt(t)) {
 +                      break
 +              }
 +              v.reset(OpAMD64CMOVLCS)
 +              v.AddArg3(y, x, cond)
 +              return true
 +      }
 +      // match: (CondSelect <t> x y (SETAE cond))
 +      // cond: is32BitInt(t)
 +      // result: (CMOVLCC y x cond)
 +      for {
 +              t := v.Type
 +              x := v_0
 +              y := v_1
 +              if v_2.Op != OpAMD64SETAE {
 +                      break
 +              }
 +              cond := v_2.Args[0]
 +              if !(is32BitInt(t)) {
 +                      break
 +              }
 +              v.reset(OpAMD64CMOVLCC)
 +              v.AddArg3(y, x, cond)
 +              return true
 +      }
 +      // match: (CondSelect <t> x y (SETBE cond))
 +      // cond: is32BitInt(t)
 +      // result: (CMOVLLS y x cond)
 +      for {
 +              t := v.Type
 +              x := v_0
 +              y := v_1
 +              if v_2.Op != OpAMD64SETBE {
 +                      break
 +              }
 +              cond := v_2.Args[0]
 +              if !(is32BitInt(t)) {
 +                      break
 +              }
 +              v.reset(OpAMD64CMOVLLS)
 +              v.AddArg3(y, x, cond)
 +              return true
 +      }
 +      // match: (CondSelect <t> x y (SETEQF cond))
 +      // cond: is32BitInt(t)
 +      // result: (CMOVLEQF y x cond)
 +      for {
 +              t := v.Type
 +              x := v_0
 +              y := v_1
 +              if v_2.Op != OpAMD64SETEQF {
 +                      break
 +              }
 +              cond := v_2.Args[0]
 +              if !(is32BitInt(t)) {
 +                      break
 +              }
 +              v.reset(OpAMD64CMOVLEQF)
 +              v.AddArg3(y, x, cond)
 +              return true
 +      }
 +      // match: (CondSelect <t> x y (SETNEF cond))
 +      // cond: is32BitInt(t)
 +      // result: (CMOVLNEF y x cond)
 +      for {
 +              t := v.Type
 +              x := v_0
 +              y := v_1
 +              if v_2.Op != OpAMD64SETNEF {
 +                      break
 +              }
 +              cond := v_2.Args[0]
 +              if !(is32BitInt(t)) {
 +                      break
 +              }
 +              v.reset(OpAMD64CMOVLNEF)
 +              v.AddArg3(y, x, cond)
 +              return true
 +      }
 +      // match: (CondSelect <t> x y (SETGF cond))
 +      // cond: is32BitInt(t)
 +      // result: (CMOVLGTF y x cond)
 +      for {
 +              t := v.Type
 +              x := v_0
 +              y := v_1
 +              if v_2.Op != OpAMD64SETGF {
 +                      break
 +              }
 +              cond := v_2.Args[0]
 +              if !(is32BitInt(t)) {
 +                      break
 +              }
 +              v.reset(OpAMD64CMOVLGTF)
 +              v.AddArg3(y, x, cond)
 +              return true
 +      }
 +      // match: (CondSelect <t> x y (SETGEF cond))
 +      // cond: is32BitInt(t)
 +      // result: (CMOVLGEF y x cond)
 +      for {
 +              t := v.Type
 +              x := v_0
 +              y := v_1
 +              if v_2.Op != OpAMD64SETGEF {
 +                      break
 +              }
 +              cond := v_2.Args[0]
 +              if !(is32BitInt(t)) {
 +                      break
 +              }
 +              v.reset(OpAMD64CMOVLGEF)
 +              v.AddArg3(y, x, cond)
 +              return true
 +      }
 +      // match: (CondSelect <t> x y (SETEQ cond))
 +      // cond: is16BitInt(t)
 +      // result: (CMOVWEQ y x cond)
 +      for {
 +              t := v.Type
 +              x := v_0
 +              y := v_1
 +              if v_2.Op != OpAMD64SETEQ {
 +                      break
 +              }
 +              cond := v_2.Args[0]
 +              if !(is16BitInt(t)) {
 +                      break
 +              }
 +              v.reset(OpAMD64CMOVWEQ)
 +              v.AddArg3(y, x, cond)
 +              return true
 +      }
 +      // match: (CondSelect <t> x y (SETNE cond))
 +      // cond: is16BitInt(t)
 +      // result: (CMOVWNE y x cond)
 +      for {
 +              t := v.Type
 +              x := v_0
 +              y := v_1
 +              if v_2.Op != OpAMD64SETNE {
 +                      break
 +              }
 +              cond := v_2.Args[0]
 +              if !(is16BitInt(t)) {
 +                      break
 +              }
 +              v.reset(OpAMD64CMOVWNE)
 +              v.AddArg3(y, x, cond)
 +              return true
 +      }
 +      // match: (CondSelect <t> x y (SETL cond))
 +      // cond: is16BitInt(t)
 +      // result: (CMOVWLT y x cond)
 +      for {
 +              t := v.Type
 +              x := v_0
 +              y := v_1
 +              if v_2.Op != OpAMD64SETL {
 +                      break
 +              }
 +              cond := v_2.Args[0]
 +              if !(is16BitInt(t)) {
 +                      break
 +              }
 +              v.reset(OpAMD64CMOVWLT)
 +              v.AddArg3(y, x, cond)
 +              return true
 +      }
 +      // match: (CondSelect <t> x y (SETG cond))
 +      // cond: is16BitInt(t)
 +      // result: (CMOVWGT y x cond)
 +      for {
 +              t := v.Type
 +              x := v_0
 +              y := v_1
 +              if v_2.Op != OpAMD64SETG {
 +                      break
 +              }
 +              cond := v_2.Args[0]
 +              if !(is16BitInt(t)) {
 +                      break
 +              }
 +              v.reset(OpAMD64CMOVWGT)
 +              v.AddArg3(y, x, cond)
 +              return true
 +      }
 +      // match: (CondSelect <t> x y (SETLE cond))
 +      // cond: is16BitInt(t)
 +      // result: (CMOVWLE y x cond)
 +      for {
 +              t := v.Type
 +              x := v_0
 +              y := v_1
 +              if v_2.Op != OpAMD64SETLE {
 +                      break
 +              }
 +              cond := v_2.Args[0]
 +              if !(is16BitInt(t)) {
 +                      break
 +              }
 +              v.reset(OpAMD64CMOVWLE)
 +              v.AddArg3(y, x, cond)
 +              return true
 +      }
 +      // match: (CondSelect <t> x y (SETGE cond))
 +      // cond: is16BitInt(t)
 +      // result: (CMOVWGE y x cond)
 +      for {
 +              t := v.Type
 +              x := v_0
 +              y := v_1
 +              if v_2.Op != OpAMD64SETGE {
 +                      break
 +              }
 +              cond := v_2.Args[0]
 +              if !(is16BitInt(t)) {
 +                      break
 +              }
 +              v.reset(OpAMD64CMOVWGE)
 +              v.AddArg3(y, x, cond)
 +              return true
 +      }
 +      // match: (CondSelect <t> x y (SETA cond))
 +      // cond: is16BitInt(t)
 +      // result: (CMOVWHI y x cond)
 +      for {
 +              t := v.Type
 +              x := v_0
 +              y := v_1
 +              if v_2.Op != OpAMD64SETA {
 +                      break
 +              }
 +              cond := v_2.Args[0]
 +              if !(is16BitInt(t)) {
 +                      break
 +              }
 +              v.reset(OpAMD64CMOVWHI)
 +              v.AddArg3(y, x, cond)
 +              return true
 +      }
 +      // match: (CondSelect <t> x y (SETB cond))
 +      // cond: is16BitInt(t)
 +      // result: (CMOVWCS y x cond)
 +      for {
 +              t := v.Type
 +              x := v_0
 +              y := v_1
 +              if v_2.Op != OpAMD64SETB {
 +                      break
 +              }
 +              cond := v_2.Args[0]
 +              if !(is16BitInt(t)) {
 +                      break
 +              }
 +              v.reset(OpAMD64CMOVWCS)
 +              v.AddArg3(y, x, cond)
 +              return true
 +      }
 +      // match: (CondSelect <t> x y (SETAE cond))
 +      // cond: is16BitInt(t)
 +      // result: (CMOVWCC y x cond)
 +      for {
 +              t := v.Type
 +              x := v_0
 +              y := v_1
 +              if v_2.Op != OpAMD64SETAE {
 +                      break
 +              }
 +              cond := v_2.Args[0]
 +              if !(is16BitInt(t)) {
 +                      break
 +              }
 +              v.reset(OpAMD64CMOVWCC)
 +              v.AddArg3(y, x, cond)
 +              return true
 +      }
 +      // match: (CondSelect <t> x y (SETBE cond))
 +      // cond: is16BitInt(t)
 +      // result: (CMOVWLS y x cond)
 +      for {
 +              t := v.Type
 +              x := v_0
 +              y := v_1
 +              if v_2.Op != OpAMD64SETBE {
 +                      break
 +              }
 +              cond := v_2.Args[0]
 +              if !(is16BitInt(t)) {
 +                      break
 +              }
 +              v.reset(OpAMD64CMOVWLS)
 +              v.AddArg3(y, x, cond)
 +              return true
 +      }
 +      // match: (CondSelect <t> x y (SETEQF cond))
 +      // cond: is16BitInt(t)
 +      // result: (CMOVWEQF y x cond)
 +      for {
 +              t := v.Type
 +              x := v_0
 +              y := v_1
 +              if v_2.Op != OpAMD64SETEQF {
 +                      break
 +              }
 +              cond := v_2.Args[0]
 +              if !(is16BitInt(t)) {
 +                      break
 +              }
 +              v.reset(OpAMD64CMOVWEQF)
 +              v.AddArg3(y, x, cond)
 +              return true
 +      }
 +      // match: (CondSelect <t> x y (SETNEF cond))
 +      // cond: is16BitInt(t)
 +      // result: (CMOVWNEF y x cond)
 +      for {
 +              t := v.Type
 +              x := v_0
 +              y := v_1
 +              if v_2.Op != OpAMD64SETNEF {
 +                      break
 +              }
 +              cond := v_2.Args[0]
 +              if !(is16BitInt(t)) {
 +                      break
 +              }
 +              v.reset(OpAMD64CMOVWNEF)
 +              v.AddArg3(y, x, cond)
 +              return true
 +      }
 +      // match: (CondSelect <t> x y (SETGF cond))
 +      // cond: is16BitInt(t)
 +      // result: (CMOVWGTF y x cond)
 +      for {
 +              t := v.Type
 +              x := v_0
 +              y := v_1
 +              if v_2.Op != OpAMD64SETGF {
 +                      break
 +              }
 +              cond := v_2.Args[0]
 +              if !(is16BitInt(t)) {
 +                      break
 +              }
 +              v.reset(OpAMD64CMOVWGTF)
 +              v.AddArg3(y, x, cond)
 +              return true
 +      }
 +      // match: (CondSelect <t> x y (SETGEF cond))
 +      // cond: is16BitInt(t)
 +      // result: (CMOVWGEF y x cond)
 +      for {
 +              t := v.Type
 +              x := v_0
 +              y := v_1
 +              if v_2.Op != OpAMD64SETGEF {
 +                      break
 +              }
 +              cond := v_2.Args[0]
 +              if !(is16BitInt(t)) {
 +                      break
 +              }
 +              v.reset(OpAMD64CMOVWGEF)
 +              v.AddArg3(y, x, cond)
 +              return true
 +      }
 +      // match: (CondSelect <t> x y check)
 +      // cond: !check.Type.IsFlags() && check.Type.Size() == 1
 +      // result: (CondSelect <t> x y (MOVBQZX <typ.UInt64> check))
 +      for {
 +              t := v.Type
 +              x := v_0
 +              y := v_1
 +              check := v_2
 +              if !(!check.Type.IsFlags() && check.Type.Size() == 1) {
 +                      break
 +              }
 +              v.reset(OpCondSelect)
 +              v.Type = t
 +              v0 := b.NewValue0(v.Pos, OpAMD64MOVBQZX, typ.UInt64)
 +              v0.AddArg(check)
 +              v.AddArg3(x, y, v0)
 +              return true
 +      }
 +      // match: (CondSelect <t> x y check)
 +      // cond: !check.Type.IsFlags() && check.Type.Size() == 2
 +      // result: (CondSelect <t> x y (MOVWQZX <typ.UInt64> check))
 +      for {
 +              t := v.Type
 +              x := v_0
 +              y := v_1
 +              check := v_2
 +              if !(!check.Type.IsFlags() && check.Type.Size() == 2) {
 +                      break
 +              }
 +              v.reset(OpCondSelect)
 +              v.Type = t
 +              v0 := b.NewValue0(v.Pos, OpAMD64MOVWQZX, typ.UInt64)
 +              v0.AddArg(check)
 +              v.AddArg3(x, y, v0)
 +              return true
 +      }
 +      // match: (CondSelect <t> x y check)
 +      // cond: !check.Type.IsFlags() && check.Type.Size() == 4
 +      // result: (CondSelect <t> x y (MOVLQZX <typ.UInt64> check))
 +      for {
 +              t := v.Type
 +              x := v_0
 +              y := v_1
 +              check := v_2
 +              if !(!check.Type.IsFlags() && check.Type.Size() == 4) {
 +                      break
 +              }
 +              v.reset(OpCondSelect)
 +              v.Type = t
 +              v0 := b.NewValue0(v.Pos, OpAMD64MOVLQZX, typ.UInt64)
 +              v0.AddArg(check)
 +              v.AddArg3(x, y, v0)
 +              return true
 +      }
 +      // match: (CondSelect <t> x y check)
 +      // cond: !check.Type.IsFlags() && check.Type.Size() == 8 && (is64BitInt(t) || isPtr(t))
 +      // result: (CMOVQNE y x (CMPQconst [0] check))
 +      for {
 +              t := v.Type
 +              x := v_0
 +              y := v_1
 +              check := v_2
 +              if !(!check.Type.IsFlags() && check.Type.Size() == 8 && (is64BitInt(t) || isPtr(t))) {
 +                      break
 +              }
 +              v.reset(OpAMD64CMOVQNE)
 +              v0 := b.NewValue0(v.Pos, OpAMD64CMPQconst, types.TypeFlags)
 +              v0.AuxInt = int32ToAuxInt(0)
 +              v0.AddArg(check)
 +              v.AddArg3(y, x, v0)
 +              return true
 +      }
 +      // match: (CondSelect <t> x y check)
 +      // cond: !check.Type.IsFlags() && check.Type.Size() == 8 && is32BitInt(t)
 +      // result: (CMOVLNE y x (CMPQconst [0] check))
 +      for {
 +              t := v.Type
 +              x := v_0
 +              y := v_1
 +              check := v_2
 +              if !(!check.Type.IsFlags() && check.Type.Size() == 8 && is32BitInt(t)) {
 +                      break
 +              }
 +              v.reset(OpAMD64CMOVLNE)
 +              v0 := b.NewValue0(v.Pos, OpAMD64CMPQconst, types.TypeFlags)
 +              v0.AuxInt = int32ToAuxInt(0)
 +              v0.AddArg(check)
 +              v.AddArg3(y, x, v0)
 +              return true
 +      }
 +      // match: (CondSelect <t> x y check)
 +      // cond: !check.Type.IsFlags() && check.Type.Size() == 8 && is16BitInt(t)
 +      // result: (CMOVWNE y x (CMPQconst [0] check))
 +      for {
 +              t := v.Type
 +              x := v_0
 +              y := v_1
 +              check := v_2
 +              if !(!check.Type.IsFlags() && check.Type.Size() == 8 && is16BitInt(t)) {
 +                      break
 +              }
 +              v.reset(OpAMD64CMOVWNE)
 +              v0 := b.NewValue0(v.Pos, OpAMD64CMPQconst, types.TypeFlags)
 +              v0.AuxInt = int32ToAuxInt(0)
 +              v0.AddArg(check)
 +              v.AddArg3(y, x, v0)
 +              return true
 +      }
 +      return false
 +}
 +func rewriteValueAMD64_OpConst16(v *Value) bool {
 +      // match: (Const16 [c])
 +      // result: (MOVLconst [int32(c)])
 +      for {
 +              c := auxIntToInt16(v.AuxInt)
 +              v.reset(OpAMD64MOVLconst)
 +              v.AuxInt = int32ToAuxInt(int32(c))
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpConst8(v *Value) bool {
 +      // match: (Const8 [c])
 +      // result: (MOVLconst [int32(c)])
 +      for {
 +              c := auxIntToInt8(v.AuxInt)
 +              v.reset(OpAMD64MOVLconst)
 +              v.AuxInt = int32ToAuxInt(int32(c))
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpConstBool(v *Value) bool {
 +      // match: (ConstBool [c])
 +      // result: (MOVLconst [b2i32(c)])
 +      for {
 +              c := auxIntToBool(v.AuxInt)
 +              v.reset(OpAMD64MOVLconst)
 +              v.AuxInt = int32ToAuxInt(b2i32(c))
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpConstNil(v *Value) bool {
 +      // match: (ConstNil )
 +      // result: (MOVQconst [0])
 +      for {
 +              v.reset(OpAMD64MOVQconst)
 +              v.AuxInt = int64ToAuxInt(0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpConvertToInt32MaskedFloat32x16(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (ConvertToInt32MaskedFloat32x16 x mask)
 +      // result: (VCVTTPS2DQMasked512 x (VPMOVVec32x16ToM <types.TypeMask> mask))
 +      for {
 +              x := v_0
 +              mask := v_1
 +              v.reset(OpAMD64VCVTTPS2DQMasked512)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x16ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg2(x, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpConvertToInt32MaskedFloat32x4(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (ConvertToInt32MaskedFloat32x4 x mask)
 +      // result: (VCVTTPS2DQMasked128 x (VPMOVVec32x4ToM <types.TypeMask> mask))
 +      for {
 +              x := v_0
 +              mask := v_1
 +              v.reset(OpAMD64VCVTTPS2DQMasked128)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x4ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg2(x, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpConvertToInt32MaskedFloat32x8(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (ConvertToInt32MaskedFloat32x8 x mask)
 +      // result: (VCVTTPS2DQMasked256 x (VPMOVVec32x8ToM <types.TypeMask> mask))
 +      for {
 +              x := v_0
 +              mask := v_1
 +              v.reset(OpAMD64VCVTTPS2DQMasked256)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x8ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg2(x, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpConvertToUint32MaskedFloat32x16(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (ConvertToUint32MaskedFloat32x16 x mask)
 +      // result: (VCVTPS2UDQMasked512 x (VPMOVVec32x16ToM <types.TypeMask> mask))
 +      for {
 +              x := v_0
 +              mask := v_1
 +              v.reset(OpAMD64VCVTPS2UDQMasked512)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x16ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg2(x, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpConvertToUint32MaskedFloat32x4(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (ConvertToUint32MaskedFloat32x4 x mask)
 +      // result: (VCVTPS2UDQMasked128 x (VPMOVVec32x4ToM <types.TypeMask> mask))
 +      for {
 +              x := v_0
 +              mask := v_1
 +              v.reset(OpAMD64VCVTPS2UDQMasked128)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x4ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg2(x, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpConvertToUint32MaskedFloat32x8(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (ConvertToUint32MaskedFloat32x8 x mask)
 +      // result: (VCVTPS2UDQMasked256 x (VPMOVVec32x8ToM <types.TypeMask> mask))
 +      for {
 +              x := v_0
 +              mask := v_1
 +              v.reset(OpAMD64VCVTPS2UDQMasked256)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x8ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg2(x, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpCtz16(v *Value) bool {
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      typ := &b.Func.Config.Types
 +      // match: (Ctz16 x)
 +      // result: (BSFL (ORLconst <typ.UInt32> [1<<16] x))
 +      for {
 +              x := v_0
 +              v.reset(OpAMD64BSFL)
 +              v0 := b.NewValue0(v.Pos, OpAMD64ORLconst, typ.UInt32)
 +              v0.AuxInt = int32ToAuxInt(1 << 16)
 +              v0.AddArg(x)
 +              v.AddArg(v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpCtz16NonZero(v *Value) bool {
 +      v_0 := v.Args[0]
 +      // match: (Ctz16NonZero x)
 +      // cond: buildcfg.GOAMD64 >= 3
 +      // result: (TZCNTL x)
 +      for {
 +              x := v_0
 +              if !(buildcfg.GOAMD64 >= 3) {
 +                      break
 +              }
 +              v.reset(OpAMD64TZCNTL)
 +              v.AddArg(x)
 +              return true
 +      }
 +      // match: (Ctz16NonZero x)
 +      // cond: buildcfg.GOAMD64 < 3
 +      // result: (BSFL x)
 +      for {
 +              x := v_0
 +              if !(buildcfg.GOAMD64 < 3) {
 +                      break
 +              }
 +              v.reset(OpAMD64BSFL)
 +              v.AddArg(x)
 +              return true
 +      }
 +      return false
 +}
 +func rewriteValueAMD64_OpCtz32(v *Value) bool {
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      typ := &b.Func.Config.Types
 +      // match: (Ctz32 x)
 +      // cond: buildcfg.GOAMD64 >= 3
 +      // result: (TZCNTL x)
 +      for {
 +              x := v_0
 +              if !(buildcfg.GOAMD64 >= 3) {
 +                      break
 +              }
 +              v.reset(OpAMD64TZCNTL)
 +              v.AddArg(x)
 +              return true
 +      }
 +      // match: (Ctz32 x)
 +      // cond: buildcfg.GOAMD64 < 3
 +      // result: (Select0 (BSFQ (BTSQconst <typ.UInt64> [32] x)))
 +      for {
 +              x := v_0
 +              if !(buildcfg.GOAMD64 < 3) {
 +                      break
 +              }
 +              v.reset(OpSelect0)
 +              v0 := b.NewValue0(v.Pos, OpAMD64BSFQ, types.NewTuple(typ.UInt64, types.TypeFlags))
 +              v1 := b.NewValue0(v.Pos, OpAMD64BTSQconst, typ.UInt64)
 +              v1.AuxInt = int8ToAuxInt(32)
 +              v1.AddArg(x)
 +              v0.AddArg(v1)
 +              v.AddArg(v0)
 +              return true
 +      }
 +      return false
 +}
 +func rewriteValueAMD64_OpCtz32NonZero(v *Value) bool {
 +      v_0 := v.Args[0]
 +      // match: (Ctz32NonZero x)
 +      // cond: buildcfg.GOAMD64 >= 3
 +      // result: (TZCNTL x)
 +      for {
 +              x := v_0
 +              if !(buildcfg.GOAMD64 >= 3) {
 +                      break
 +              }
 +              v.reset(OpAMD64TZCNTL)
 +              v.AddArg(x)
 +              return true
 +      }
 +      // match: (Ctz32NonZero x)
 +      // cond: buildcfg.GOAMD64 < 3
 +      // result: (BSFL x)
 +      for {
 +              x := v_0
 +              if !(buildcfg.GOAMD64 < 3) {
 +                      break
 +              }
 +              v.reset(OpAMD64BSFL)
 +              v.AddArg(x)
 +              return true
 +      }
 +      return false
 +}
 +func rewriteValueAMD64_OpCtz64(v *Value) bool {
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      typ := &b.Func.Config.Types
 +      // match: (Ctz64 x)
 +      // cond: buildcfg.GOAMD64 >= 3
 +      // result: (TZCNTQ x)
 +      for {
 +              x := v_0
 +              if !(buildcfg.GOAMD64 >= 3) {
 +                      break
 +              }
 +              v.reset(OpAMD64TZCNTQ)
 +              v.AddArg(x)
 +              return true
 +      }
 +      // match: (Ctz64 <t> x)
 +      // cond: buildcfg.GOAMD64 < 3
 +      // result: (CMOVQEQ (Select0 <t> (BSFQ x)) (MOVQconst <t> [64]) (Select1 <types.TypeFlags> (BSFQ x)))
 +      for {
 +              t := v.Type
 +              x := v_0
 +              if !(buildcfg.GOAMD64 < 3) {
 +                      break
 +              }
 +              v.reset(OpAMD64CMOVQEQ)
 +              v0 := b.NewValue0(v.Pos, OpSelect0, t)
 +              v1 := b.NewValue0(v.Pos, OpAMD64BSFQ, types.NewTuple(typ.UInt64, types.TypeFlags))
 +              v1.AddArg(x)
 +              v0.AddArg(v1)
 +              v2 := b.NewValue0(v.Pos, OpAMD64MOVQconst, t)
 +              v2.AuxInt = int64ToAuxInt(64)
 +              v3 := b.NewValue0(v.Pos, OpSelect1, types.TypeFlags)
 +              v3.AddArg(v1)
 +              v.AddArg3(v0, v2, v3)
 +              return true
 +      }
 +      return false
 +}
 +func rewriteValueAMD64_OpCtz64NonZero(v *Value) bool {
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      typ := &b.Func.Config.Types
 +      // match: (Ctz64NonZero x)
 +      // cond: buildcfg.GOAMD64 >= 3
 +      // result: (TZCNTQ x)
 +      for {
 +              x := v_0
 +              if !(buildcfg.GOAMD64 >= 3) {
 +                      break
 +              }
 +              v.reset(OpAMD64TZCNTQ)
 +              v.AddArg(x)
 +              return true
 +      }
 +      // match: (Ctz64NonZero x)
 +      // cond: buildcfg.GOAMD64 < 3
 +      // result: (Select0 (BSFQ x))
 +      for {
 +              x := v_0
 +              if !(buildcfg.GOAMD64 < 3) {
 +                      break
 +              }
 +              v.reset(OpSelect0)
 +              v0 := b.NewValue0(v.Pos, OpAMD64BSFQ, types.NewTuple(typ.UInt64, types.TypeFlags))
 +              v0.AddArg(x)
 +              v.AddArg(v0)
 +              return true
 +      }
 +      return false
 +}
 +func rewriteValueAMD64_OpCtz8(v *Value) bool {
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      typ := &b.Func.Config.Types
 +      // match: (Ctz8 x)
 +      // result: (BSFL (ORLconst <typ.UInt32> [1<<8 ] x))
 +      for {
 +              x := v_0
 +              v.reset(OpAMD64BSFL)
 +              v0 := b.NewValue0(v.Pos, OpAMD64ORLconst, typ.UInt32)
 +              v0.AuxInt = int32ToAuxInt(1 << 8)
 +              v0.AddArg(x)
 +              v.AddArg(v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpCtz8NonZero(v *Value) bool {
 +      v_0 := v.Args[0]
 +      // match: (Ctz8NonZero x)
 +      // cond: buildcfg.GOAMD64 >= 3
 +      // result: (TZCNTL x)
 +      for {
 +              x := v_0
 +              if !(buildcfg.GOAMD64 >= 3) {
 +                      break
 +              }
 +              v.reset(OpAMD64TZCNTL)
 +              v.AddArg(x)
 +              return true
 +      }
 +      // match: (Ctz8NonZero x)
 +      // cond: buildcfg.GOAMD64 < 3
 +      // result: (BSFL x)
 +      for {
 +              x := v_0
 +              if !(buildcfg.GOAMD64 < 3) {
 +                      break
 +              }
 +              v.reset(OpAMD64BSFL)
 +              v.AddArg(x)
 +              return true
 +      }
 +      return false
 +}
 +func rewriteValueAMD64_OpCvt16toMask16x16(v *Value) bool {
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (Cvt16toMask16x16 <t> x)
 +      // result: (VPMOVMToVec16x16 <types.TypeVec256> (KMOVWk <t> x))
 +      for {
 +              t := v.Type
 +              x := v_0
 +              v.reset(OpAMD64VPMOVMToVec16x16)
 +              v.Type = types.TypeVec256
 +              v0 := b.NewValue0(v.Pos, OpAMD64KMOVWk, t)
 +              v0.AddArg(x)
 +              v.AddArg(v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpCvt16toMask32x16(v *Value) bool {
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (Cvt16toMask32x16 <t> x)
 +      // result: (VPMOVMToVec32x16 <types.TypeVec512> (KMOVWk <t> x))
 +      for {
 +              t := v.Type
 +              x := v_0
 +              v.reset(OpAMD64VPMOVMToVec32x16)
 +              v.Type = types.TypeVec512
 +              v0 := b.NewValue0(v.Pos, OpAMD64KMOVWk, t)
 +              v0.AddArg(x)
 +              v.AddArg(v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpCvt16toMask8x16(v *Value) bool {
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (Cvt16toMask8x16 <t> x)
 +      // result: (VPMOVMToVec8x16 <types.TypeVec128> (KMOVWk <t> x))
 +      for {
 +              t := v.Type
 +              x := v_0
 +              v.reset(OpAMD64VPMOVMToVec8x16)
 +              v.Type = types.TypeVec128
 +              v0 := b.NewValue0(v.Pos, OpAMD64KMOVWk, t)
 +              v0.AddArg(x)
 +              v.AddArg(v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpCvt32toMask16x32(v *Value) bool {
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (Cvt32toMask16x32 <t> x)
 +      // result: (VPMOVMToVec16x32 <types.TypeVec512> (KMOVDk <t> x))
 +      for {
 +              t := v.Type
 +              x := v_0
 +              v.reset(OpAMD64VPMOVMToVec16x32)
 +              v.Type = types.TypeVec512
 +              v0 := b.NewValue0(v.Pos, OpAMD64KMOVDk, t)
 +              v0.AddArg(x)
 +              v.AddArg(v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpCvt32toMask8x32(v *Value) bool {
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (Cvt32toMask8x32 <t> x)
 +      // result: (VPMOVMToVec8x32 <types.TypeVec256> (KMOVDk <t> x))
 +      for {
 +              t := v.Type
 +              x := v_0
 +              v.reset(OpAMD64VPMOVMToVec8x32)
 +              v.Type = types.TypeVec256
 +              v0 := b.NewValue0(v.Pos, OpAMD64KMOVDk, t)
 +              v0.AddArg(x)
 +              v.AddArg(v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpCvt64toMask8x64(v *Value) bool {
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (Cvt64toMask8x64 <t> x)
 +      // result: (VPMOVMToVec8x64 <types.TypeVec512> (KMOVQk <t> x))
 +      for {
 +              t := v.Type
 +              x := v_0
 +              v.reset(OpAMD64VPMOVMToVec8x64)
 +              v.Type = types.TypeVec512
 +              v0 := b.NewValue0(v.Pos, OpAMD64KMOVQk, t)
 +              v0.AddArg(x)
 +              v.AddArg(v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpCvt8toMask16x8(v *Value) bool {
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (Cvt8toMask16x8 <t> x)
 +      // result: (VPMOVMToVec16x8 <types.TypeVec128> (KMOVBk <t> x))
 +      for {
 +              t := v.Type
 +              x := v_0
 +              v.reset(OpAMD64VPMOVMToVec16x8)
 +              v.Type = types.TypeVec128
 +              v0 := b.NewValue0(v.Pos, OpAMD64KMOVBk, t)
 +              v0.AddArg(x)
 +              v.AddArg(v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpCvt8toMask32x4(v *Value) bool {
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (Cvt8toMask32x4 <t> x)
 +      // result: (VPMOVMToVec32x4 <types.TypeVec128> (KMOVBk <t> x))
 +      for {
 +              t := v.Type
 +              x := v_0
 +              v.reset(OpAMD64VPMOVMToVec32x4)
 +              v.Type = types.TypeVec128
 +              v0 := b.NewValue0(v.Pos, OpAMD64KMOVBk, t)
 +              v0.AddArg(x)
 +              v.AddArg(v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpCvt8toMask32x8(v *Value) bool {
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (Cvt8toMask32x8 <t> x)
 +      // result: (VPMOVMToVec32x8 <types.TypeVec256> (KMOVBk <t> x))
 +      for {
 +              t := v.Type
 +              x := v_0
 +              v.reset(OpAMD64VPMOVMToVec32x8)
 +              v.Type = types.TypeVec256
 +              v0 := b.NewValue0(v.Pos, OpAMD64KMOVBk, t)
 +              v0.AddArg(x)
 +              v.AddArg(v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpCvt8toMask64x2(v *Value) bool {
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (Cvt8toMask64x2 <t> x)
 +      // result: (VPMOVMToVec64x2 <types.TypeVec128> (KMOVBk <t> x))
 +      for {
 +              t := v.Type
 +              x := v_0
 +              v.reset(OpAMD64VPMOVMToVec64x2)
 +              v.Type = types.TypeVec128
 +              v0 := b.NewValue0(v.Pos, OpAMD64KMOVBk, t)
 +              v0.AddArg(x)
 +              v.AddArg(v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpCvt8toMask64x4(v *Value) bool {
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (Cvt8toMask64x4 <t> x)
 +      // result: (VPMOVMToVec64x4 <types.TypeVec256> (KMOVBk <t> x))
 +      for {
 +              t := v.Type
 +              x := v_0
 +              v.reset(OpAMD64VPMOVMToVec64x4)
 +              v.Type = types.TypeVec256
 +              v0 := b.NewValue0(v.Pos, OpAMD64KMOVBk, t)
 +              v0.AddArg(x)
 +              v.AddArg(v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpCvt8toMask64x8(v *Value) bool {
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (Cvt8toMask64x8 <t> x)
 +      // result: (VPMOVMToVec64x8 <types.TypeVec512> (KMOVBk <t> x))
 +      for {
 +              t := v.Type
 +              x := v_0
 +              v.reset(OpAMD64VPMOVMToVec64x8)
 +              v.Type = types.TypeVec512
 +              v0 := b.NewValue0(v.Pos, OpAMD64KMOVBk, t)
 +              v0.AddArg(x)
 +              v.AddArg(v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpCvtMask16x16to16(v *Value) bool {
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (CvtMask16x16to16 <t> x)
 +      // result: (KMOVWi <t> (VPMOVVec16x16ToM <types.TypeMask> x))
 +      for {
 +              t := v.Type
 +              x := v_0
 +              v.reset(OpAMD64KMOVWi)
 +              v.Type = t
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x16ToM, types.TypeMask)
 +              v0.AddArg(x)
 +              v.AddArg(v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpCvtMask16x32to32(v *Value) bool {
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (CvtMask16x32to32 <t> x)
 +      // result: (KMOVDi <t> (VPMOVVec16x32ToM <types.TypeMask> x))
 +      for {
 +              t := v.Type
 +              x := v_0
 +              v.reset(OpAMD64KMOVDi)
 +              v.Type = t
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x32ToM, types.TypeMask)
 +              v0.AddArg(x)
 +              v.AddArg(v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpCvtMask16x8to8(v *Value) bool {
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (CvtMask16x8to8 <t> x)
 +      // result: (KMOVBi <t> (VPMOVVec16x8ToM <types.TypeMask> x))
 +      for {
 +              t := v.Type
 +              x := v_0
 +              v.reset(OpAMD64KMOVBi)
 +              v.Type = t
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x8ToM, types.TypeMask)
 +              v0.AddArg(x)
 +              v.AddArg(v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpCvtMask32x16to16(v *Value) bool {
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (CvtMask32x16to16 <t> x)
 +      // result: (KMOVWi <t> (VPMOVVec32x16ToM <types.TypeMask> x))
 +      for {
 +              t := v.Type
 +              x := v_0
 +              v.reset(OpAMD64KMOVWi)
 +              v.Type = t
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x16ToM, types.TypeMask)
 +              v0.AddArg(x)
 +              v.AddArg(v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpCvtMask32x4to8(v *Value) bool {
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (CvtMask32x4to8 <t> x)
 +      // result: (KMOVBi <t> (VPMOVVec32x4ToM <types.TypeMask> x))
 +      for {
 +              t := v.Type
 +              x := v_0
 +              v.reset(OpAMD64KMOVBi)
 +              v.Type = t
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x4ToM, types.TypeMask)
 +              v0.AddArg(x)
 +              v.AddArg(v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpCvtMask32x8to8(v *Value) bool {
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (CvtMask32x8to8 <t> x)
 +      // result: (KMOVBi <t> (VPMOVVec32x8ToM <types.TypeMask> x))
 +      for {
 +              t := v.Type
 +              x := v_0
 +              v.reset(OpAMD64KMOVBi)
 +              v.Type = t
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x8ToM, types.TypeMask)
 +              v0.AddArg(x)
 +              v.AddArg(v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpCvtMask64x2to8(v *Value) bool {
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (CvtMask64x2to8 <t> x)
 +      // result: (KMOVBi <t> (VPMOVVec64x2ToM <types.TypeMask> x))
 +      for {
 +              t := v.Type
 +              x := v_0
 +              v.reset(OpAMD64KMOVBi)
 +              v.Type = t
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x2ToM, types.TypeMask)
 +              v0.AddArg(x)
 +              v.AddArg(v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpCvtMask64x4to8(v *Value) bool {
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (CvtMask64x4to8 <t> x)
 +      // result: (KMOVBi <t> (VPMOVVec64x4ToM <types.TypeMask> x))
 +      for {
 +              t := v.Type
 +              x := v_0
 +              v.reset(OpAMD64KMOVBi)
 +              v.Type = t
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x4ToM, types.TypeMask)
 +              v0.AddArg(x)
 +              v.AddArg(v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpCvtMask64x8to8(v *Value) bool {
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (CvtMask64x8to8 <t> x)
 +      // result: (KMOVBi <t> (VPMOVVec64x8ToM <types.TypeMask> x))
 +      for {
 +              t := v.Type
 +              x := v_0
 +              v.reset(OpAMD64KMOVBi)
 +              v.Type = t
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x8ToM, types.TypeMask)
 +              v0.AddArg(x)
 +              v.AddArg(v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpCvtMask8x16to16(v *Value) bool {
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (CvtMask8x16to16 <t> x)
 +      // result: (KMOVWi <t> (VPMOVVec8x16ToM <types.TypeMask> x))
 +      for {
 +              t := v.Type
 +              x := v_0
 +              v.reset(OpAMD64KMOVWi)
 +              v.Type = t
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec8x16ToM, types.TypeMask)
 +              v0.AddArg(x)
 +              v.AddArg(v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpCvtMask8x32to32(v *Value) bool {
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (CvtMask8x32to32 <t> x)
 +      // result: (KMOVDi <t> (VPMOVVec8x32ToM <types.TypeMask> x))
 +      for {
 +              t := v.Type
 +              x := v_0
 +              v.reset(OpAMD64KMOVDi)
 +              v.Type = t
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec8x32ToM, types.TypeMask)
 +              v0.AddArg(x)
 +              v.AddArg(v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpCvtMask8x64to64(v *Value) bool {
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (CvtMask8x64to64 <t> x)
 +      // result: (KMOVQi <t> (VPMOVVec8x64ToM <types.TypeMask> x))
 +      for {
 +              t := v.Type
 +              x := v_0
 +              v.reset(OpAMD64KMOVQi)
 +              v.Type = t
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec8x64ToM, types.TypeMask)
 +              v0.AddArg(x)
 +              v.AddArg(v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpDiv16(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      typ := &b.Func.Config.Types
 +      // match: (Div16 [a] x y)
 +      // result: (Select0 (DIVW [a] x y))
 +      for {
 +              a := auxIntToBool(v.AuxInt)
 +              x := v_0
 +              y := v_1
 +              v.reset(OpSelect0)
 +              v0 := b.NewValue0(v.Pos, OpAMD64DIVW, types.NewTuple(typ.Int16, typ.Int16))
 +              v0.AuxInt = boolToAuxInt(a)
 +              v0.AddArg2(x, y)
 +              v.AddArg(v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpDiv16u(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      typ := &b.Func.Config.Types
 +      // match: (Div16u x y)
 +      // result: (Select0 (DIVWU x y))
 +      for {
 +              x := v_0
 +              y := v_1
 +              v.reset(OpSelect0)
 +              v0 := b.NewValue0(v.Pos, OpAMD64DIVWU, types.NewTuple(typ.UInt16, typ.UInt16))
 +              v0.AddArg2(x, y)
 +              v.AddArg(v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpDiv32(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      typ := &b.Func.Config.Types
 +      // match: (Div32 [a] x y)
 +      // result: (Select0 (DIVL [a] x y))
 +      for {
 +              a := auxIntToBool(v.AuxInt)
 +              x := v_0
 +              y := v_1
 +              v.reset(OpSelect0)
 +              v0 := b.NewValue0(v.Pos, OpAMD64DIVL, types.NewTuple(typ.Int32, typ.Int32))
 +              v0.AuxInt = boolToAuxInt(a)
 +              v0.AddArg2(x, y)
 +              v.AddArg(v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpDiv32u(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      typ := &b.Func.Config.Types
 +      // match: (Div32u x y)
 +      // result: (Select0 (DIVLU x y))
 +      for {
 +              x := v_0
 +              y := v_1
 +              v.reset(OpSelect0)
 +              v0 := b.NewValue0(v.Pos, OpAMD64DIVLU, types.NewTuple(typ.UInt32, typ.UInt32))
 +              v0.AddArg2(x, y)
 +              v.AddArg(v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpDiv64(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      typ := &b.Func.Config.Types
 +      // match: (Div64 [a] x y)
 +      // result: (Select0 (DIVQ [a] x y))
 +      for {
 +              a := auxIntToBool(v.AuxInt)
 +              x := v_0
 +              y := v_1
 +              v.reset(OpSelect0)
 +              v0 := b.NewValue0(v.Pos, OpAMD64DIVQ, types.NewTuple(typ.Int64, typ.Int64))
 +              v0.AuxInt = boolToAuxInt(a)
 +              v0.AddArg2(x, y)
 +              v.AddArg(v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpDiv64u(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      typ := &b.Func.Config.Types
 +      // match: (Div64u x y)
 +      // result: (Select0 (DIVQU x y))
 +      for {
 +              x := v_0
 +              y := v_1
 +              v.reset(OpSelect0)
 +              v0 := b.NewValue0(v.Pos, OpAMD64DIVQU, types.NewTuple(typ.UInt64, typ.UInt64))
 +              v0.AddArg2(x, y)
 +              v.AddArg(v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpDiv8(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      typ := &b.Func.Config.Types
 +      // match: (Div8 x y)
 +      // result: (Select0 (DIVW (SignExt8to16 x) (SignExt8to16 y)))
 +      for {
 +              x := v_0
 +              y := v_1
 +              v.reset(OpSelect0)
 +              v0 := b.NewValue0(v.Pos, OpAMD64DIVW, types.NewTuple(typ.Int16, typ.Int16))
 +              v1 := b.NewValue0(v.Pos, OpSignExt8to16, typ.Int16)
 +              v1.AddArg(x)
 +              v2 := b.NewValue0(v.Pos, OpSignExt8to16, typ.Int16)
 +              v2.AddArg(y)
 +              v0.AddArg2(v1, v2)
 +              v.AddArg(v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpDiv8u(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      typ := &b.Func.Config.Types
 +      // match: (Div8u x y)
 +      // result: (Select0 (DIVWU (ZeroExt8to16 x) (ZeroExt8to16 y)))
 +      for {
 +              x := v_0
 +              y := v_1
 +              v.reset(OpSelect0)
 +              v0 := b.NewValue0(v.Pos, OpAMD64DIVWU, types.NewTuple(typ.UInt16, typ.UInt16))
 +              v1 := b.NewValue0(v.Pos, OpZeroExt8to16, typ.UInt16)
 +              v1.AddArg(x)
 +              v2 := b.NewValue0(v.Pos, OpZeroExt8to16, typ.UInt16)
 +              v2.AddArg(y)
 +              v0.AddArg2(v1, v2)
 +              v.AddArg(v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpDivMaskedFloat32x16(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (DivMaskedFloat32x16 x y mask)
 +      // result: (VDIVPSMasked512 x y (VPMOVVec32x16ToM <types.TypeMask> mask))
 +      for {
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VDIVPSMasked512)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x16ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg3(x, y, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpDivMaskedFloat32x4(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (DivMaskedFloat32x4 x y mask)
 +      // result: (VDIVPSMasked128 x y (VPMOVVec32x4ToM <types.TypeMask> mask))
 +      for {
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VDIVPSMasked128)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x4ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg3(x, y, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpDivMaskedFloat32x8(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (DivMaskedFloat32x8 x y mask)
 +      // result: (VDIVPSMasked256 x y (VPMOVVec32x8ToM <types.TypeMask> mask))
 +      for {
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VDIVPSMasked256)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x8ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg3(x, y, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpDivMaskedFloat64x2(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (DivMaskedFloat64x2 x y mask)
 +      // result: (VDIVPDMasked128 x y (VPMOVVec64x2ToM <types.TypeMask> mask))
 +      for {
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VDIVPDMasked128)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x2ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg3(x, y, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpDivMaskedFloat64x4(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (DivMaskedFloat64x4 x y mask)
 +      // result: (VDIVPDMasked256 x y (VPMOVVec64x4ToM <types.TypeMask> mask))
 +      for {
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VDIVPDMasked256)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x4ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg3(x, y, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpDivMaskedFloat64x8(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (DivMaskedFloat64x8 x y mask)
 +      // result: (VDIVPDMasked512 x y (VPMOVVec64x8ToM <types.TypeMask> mask))
 +      for {
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VDIVPDMasked512)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x8ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg3(x, y, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpDotProdPairsMaskedInt16x16(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (DotProdPairsMaskedInt16x16 x y mask)
 +      // result: (VPMADDWDMasked256 x y (VPMOVVec16x16ToM <types.TypeMask> mask))
 +      for {
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VPMADDWDMasked256)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x16ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg3(x, y, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpDotProdPairsMaskedInt16x32(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (DotProdPairsMaskedInt16x32 x y mask)
 +      // result: (VPMADDWDMasked512 x y (VPMOVVec16x32ToM <types.TypeMask> mask))
 +      for {
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VPMADDWDMasked512)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x32ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg3(x, y, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpDotProdPairsMaskedInt16x8(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (DotProdPairsMaskedInt16x8 x y mask)
 +      // result: (VPMADDWDMasked128 x y (VPMOVVec16x8ToM <types.TypeMask> mask))
 +      for {
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VPMADDWDMasked128)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x8ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg3(x, y, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpDotProdPairsSaturatedMaskedUint8x16(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (DotProdPairsSaturatedMaskedUint8x16 x y mask)
 +      // result: (VPMADDUBSWMasked128 x y (VPMOVVec16x8ToM <types.TypeMask> mask))
 +      for {
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VPMADDUBSWMasked128)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x8ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg3(x, y, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpDotProdPairsSaturatedMaskedUint8x32(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (DotProdPairsSaturatedMaskedUint8x32 x y mask)
 +      // result: (VPMADDUBSWMasked256 x y (VPMOVVec16x16ToM <types.TypeMask> mask))
 +      for {
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VPMADDUBSWMasked256)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x16ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg3(x, y, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpDotProdPairsSaturatedMaskedUint8x64(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (DotProdPairsSaturatedMaskedUint8x64 x y mask)
 +      // result: (VPMADDUBSWMasked512 x y (VPMOVVec16x32ToM <types.TypeMask> mask))
 +      for {
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VPMADDUBSWMasked512)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x32ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg3(x, y, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpEq16(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (Eq16 x y)
 +      // result: (SETEQ (CMPW x y))
 +      for {
 +              x := v_0
 +              y := v_1
 +              v.reset(OpAMD64SETEQ)
 +              v0 := b.NewValue0(v.Pos, OpAMD64CMPW, types.TypeFlags)
 +              v0.AddArg2(x, y)
 +              v.AddArg(v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpEq32(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (Eq32 x y)
 +      // result: (SETEQ (CMPL x y))
 +      for {
 +              x := v_0
 +              y := v_1
 +              v.reset(OpAMD64SETEQ)
 +              v0 := b.NewValue0(v.Pos, OpAMD64CMPL, types.TypeFlags)
 +              v0.AddArg2(x, y)
 +              v.AddArg(v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpEq32F(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (Eq32F x y)
 +      // result: (SETEQF (UCOMISS x y))
 +      for {
 +              x := v_0
 +              y := v_1
 +              v.reset(OpAMD64SETEQF)
 +              v0 := b.NewValue0(v.Pos, OpAMD64UCOMISS, types.TypeFlags)
 +              v0.AddArg2(x, y)
 +              v.AddArg(v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpEq64(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (Eq64 x y)
 +      // result: (SETEQ (CMPQ x y))
 +      for {
 +              x := v_0
 +              y := v_1
 +              v.reset(OpAMD64SETEQ)
 +              v0 := b.NewValue0(v.Pos, OpAMD64CMPQ, types.TypeFlags)
 +              v0.AddArg2(x, y)
 +              v.AddArg(v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpEq64F(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (Eq64F x y)
 +      // result: (SETEQF (UCOMISD x y))
 +      for {
 +              x := v_0
 +              y := v_1
 +              v.reset(OpAMD64SETEQF)
 +              v0 := b.NewValue0(v.Pos, OpAMD64UCOMISD, types.TypeFlags)
 +              v0.AddArg2(x, y)
 +              v.AddArg(v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpEq8(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (Eq8 x y)
 +      // result: (SETEQ (CMPB x y))
 +      for {
 +              x := v_0
 +              y := v_1
 +              v.reset(OpAMD64SETEQ)
 +              v0 := b.NewValue0(v.Pos, OpAMD64CMPB, types.TypeFlags)
 +              v0.AddArg2(x, y)
 +              v.AddArg(v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpEqB(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (EqB x y)
 +      // result: (SETEQ (CMPB x y))
 +      for {
 +              x := v_0
 +              y := v_1
 +              v.reset(OpAMD64SETEQ)
 +              v0 := b.NewValue0(v.Pos, OpAMD64CMPB, types.TypeFlags)
 +              v0.AddArg2(x, y)
 +              v.AddArg(v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpEqPtr(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (EqPtr x y)
 +      // result: (SETEQ (CMPQ x y))
 +      for {
 +              x := v_0
 +              y := v_1
 +              v.reset(OpAMD64SETEQ)
 +              v0 := b.NewValue0(v.Pos, OpAMD64CMPQ, types.TypeFlags)
 +              v0.AddArg2(x, y)
 +              v.AddArg(v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpEqualFloat32x16(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      typ := &b.Func.Config.Types
 +      // match: (EqualFloat32x16 x y)
 +      // result: (VPMOVMToVec32x16 (VCMPPS512 [0] x y))
 +      for {
 +              x := v_0
 +              y := v_1
 +              v.reset(OpAMD64VPMOVMToVec32x16)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VCMPPS512, typ.Mask)
 +              v0.AuxInt = uint8ToAuxInt(0)
 +              v0.AddArg2(x, y)
 +              v.AddArg(v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpEqualFloat32x4(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      // match: (EqualFloat32x4 x y)
 +      // result: (VCMPPS128 [0] x y)
 +      for {
 +              x := v_0
 +              y := v_1
 +              v.reset(OpAMD64VCMPPS128)
 +              v.AuxInt = uint8ToAuxInt(0)
 +              v.AddArg2(x, y)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpEqualFloat32x8(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      // match: (EqualFloat32x8 x y)
 +      // result: (VCMPPS256 [0] x y)
 +      for {
 +              x := v_0
 +              y := v_1
 +              v.reset(OpAMD64VCMPPS256)
 +              v.AuxInt = uint8ToAuxInt(0)
 +              v.AddArg2(x, y)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpEqualFloat64x2(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      // match: (EqualFloat64x2 x y)
 +      // result: (VCMPPD128 [0] x y)
 +      for {
 +              x := v_0
 +              y := v_1
 +              v.reset(OpAMD64VCMPPD128)
 +              v.AuxInt = uint8ToAuxInt(0)
 +              v.AddArg2(x, y)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpEqualFloat64x4(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      // match: (EqualFloat64x4 x y)
 +      // result: (VCMPPD256 [0] x y)
 +      for {
 +              x := v_0
 +              y := v_1
 +              v.reset(OpAMD64VCMPPD256)
 +              v.AuxInt = uint8ToAuxInt(0)
 +              v.AddArg2(x, y)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpEqualFloat64x8(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      typ := &b.Func.Config.Types
 +      // match: (EqualFloat64x8 x y)
 +      // result: (VPMOVMToVec64x8 (VCMPPD512 [0] x y))
 +      for {
 +              x := v_0
 +              y := v_1
 +              v.reset(OpAMD64VPMOVMToVec64x8)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VCMPPD512, typ.Mask)
 +              v0.AuxInt = uint8ToAuxInt(0)
 +              v0.AddArg2(x, y)
 +              v.AddArg(v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpEqualInt16x32(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      typ := &b.Func.Config.Types
 +      // match: (EqualInt16x32 x y)
 +      // result: (VPMOVMToVec16x32 (VPCMPEQW512 x y))
 +      for {
 +              x := v_0
 +              y := v_1
 +              v.reset(OpAMD64VPMOVMToVec16x32)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPCMPEQW512, typ.Mask)
 +              v0.AddArg2(x, y)
 +              v.AddArg(v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpEqualInt32x16(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      typ := &b.Func.Config.Types
 +      // match: (EqualInt32x16 x y)
 +      // result: (VPMOVMToVec32x16 (VPCMPEQD512 x y))
 +      for {
 +              x := v_0
 +              y := v_1
 +              v.reset(OpAMD64VPMOVMToVec32x16)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPCMPEQD512, typ.Mask)
 +              v0.AddArg2(x, y)
 +              v.AddArg(v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpEqualInt64x8(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      typ := &b.Func.Config.Types
 +      // match: (EqualInt64x8 x y)
 +      // result: (VPMOVMToVec64x8 (VPCMPEQQ512 x y))
 +      for {
 +              x := v_0
 +              y := v_1
 +              v.reset(OpAMD64VPMOVMToVec64x8)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPCMPEQQ512, typ.Mask)
 +              v0.AddArg2(x, y)
 +              v.AddArg(v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpEqualInt8x64(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      typ := &b.Func.Config.Types
 +      // match: (EqualInt8x64 x y)
 +      // result: (VPMOVMToVec8x64 (VPCMPEQB512 x y))
 +      for {
 +              x := v_0
 +              y := v_1
 +              v.reset(OpAMD64VPMOVMToVec8x64)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPCMPEQB512, typ.Mask)
 +              v0.AddArg2(x, y)
 +              v.AddArg(v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpEqualMaskedFloat32x16(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      typ := &b.Func.Config.Types
 +      // match: (EqualMaskedFloat32x16 x y mask)
 +      // result: (VPMOVMToVec32x16 (VCMPPSMasked512 [0] x y (VPMOVVec32x16ToM <types.TypeMask> mask)))
 +      for {
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VPMOVMToVec32x16)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VCMPPSMasked512, typ.Mask)
 +              v0.AuxInt = uint8ToAuxInt(0)
 +              v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x16ToM, types.TypeMask)
 +              v1.AddArg(mask)
 +              v0.AddArg3(x, y, v1)
 +              v.AddArg(v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpEqualMaskedFloat32x4(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      typ := &b.Func.Config.Types
 +      // match: (EqualMaskedFloat32x4 x y mask)
 +      // result: (VPMOVMToVec32x4 (VCMPPSMasked128 [0] x y (VPMOVVec32x4ToM <types.TypeMask> mask)))
 +      for {
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VPMOVMToVec32x4)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VCMPPSMasked128, typ.Mask)
 +              v0.AuxInt = uint8ToAuxInt(0)
 +              v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x4ToM, types.TypeMask)
 +              v1.AddArg(mask)
 +              v0.AddArg3(x, y, v1)
 +              v.AddArg(v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpEqualMaskedFloat32x8(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      typ := &b.Func.Config.Types
 +      // match: (EqualMaskedFloat32x8 x y mask)
 +      // result: (VPMOVMToVec32x8 (VCMPPSMasked256 [0] x y (VPMOVVec32x8ToM <types.TypeMask> mask)))
 +      for {
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VPMOVMToVec32x8)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VCMPPSMasked256, typ.Mask)
 +              v0.AuxInt = uint8ToAuxInt(0)
 +              v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x8ToM, types.TypeMask)
 +              v1.AddArg(mask)
 +              v0.AddArg3(x, y, v1)
 +              v.AddArg(v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpEqualMaskedFloat64x2(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      typ := &b.Func.Config.Types
 +      // match: (EqualMaskedFloat64x2 x y mask)
 +      // result: (VPMOVMToVec64x2 (VCMPPDMasked128 [0] x y (VPMOVVec64x2ToM <types.TypeMask> mask)))
 +      for {
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VPMOVMToVec64x2)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VCMPPDMasked128, typ.Mask)
 +              v0.AuxInt = uint8ToAuxInt(0)
 +              v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x2ToM, types.TypeMask)
 +              v1.AddArg(mask)
 +              v0.AddArg3(x, y, v1)
 +              v.AddArg(v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpEqualMaskedFloat64x4(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      typ := &b.Func.Config.Types
 +      // match: (EqualMaskedFloat64x4 x y mask)
 +      // result: (VPMOVMToVec64x4 (VCMPPDMasked256 [0] x y (VPMOVVec64x4ToM <types.TypeMask> mask)))
 +      for {
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VPMOVMToVec64x4)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VCMPPDMasked256, typ.Mask)
 +              v0.AuxInt = uint8ToAuxInt(0)
 +              v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x4ToM, types.TypeMask)
 +              v1.AddArg(mask)
 +              v0.AddArg3(x, y, v1)
 +              v.AddArg(v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpEqualMaskedFloat64x8(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      typ := &b.Func.Config.Types
 +      // match: (EqualMaskedFloat64x8 x y mask)
 +      // result: (VPMOVMToVec64x8 (VCMPPDMasked512 [0] x y (VPMOVVec64x8ToM <types.TypeMask> mask)))
 +      for {
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VPMOVMToVec64x8)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VCMPPDMasked512, typ.Mask)
 +              v0.AuxInt = uint8ToAuxInt(0)
 +              v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x8ToM, types.TypeMask)
 +              v1.AddArg(mask)
 +              v0.AddArg3(x, y, v1)
 +              v.AddArg(v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpEqualMaskedInt16x16(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      typ := &b.Func.Config.Types
 +      // match: (EqualMaskedInt16x16 x y mask)
 +      // result: (VPMOVMToVec16x16 (VPCMPWMasked256 [0] x y (VPMOVVec16x16ToM <types.TypeMask> mask)))
 +      for {
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VPMOVMToVec16x16)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPCMPWMasked256, typ.Mask)
 +              v0.AuxInt = uint8ToAuxInt(0)
 +              v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x16ToM, types.TypeMask)
 +              v1.AddArg(mask)
 +              v0.AddArg3(x, y, v1)
 +              v.AddArg(v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpEqualMaskedInt16x32(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      typ := &b.Func.Config.Types
 +      // match: (EqualMaskedInt16x32 x y mask)
 +      // result: (VPMOVMToVec16x32 (VPCMPWMasked512 [0] x y (VPMOVVec16x32ToM <types.TypeMask> mask)))
 +      for {
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VPMOVMToVec16x32)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPCMPWMasked512, typ.Mask)
 +              v0.AuxInt = uint8ToAuxInt(0)
 +              v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x32ToM, types.TypeMask)
 +              v1.AddArg(mask)
 +              v0.AddArg3(x, y, v1)
 +              v.AddArg(v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpEqualMaskedInt16x8(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      typ := &b.Func.Config.Types
 +      // match: (EqualMaskedInt16x8 x y mask)
 +      // result: (VPMOVMToVec16x8 (VPCMPWMasked128 [0] x y (VPMOVVec16x8ToM <types.TypeMask> mask)))
 +      for {
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VPMOVMToVec16x8)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPCMPWMasked128, typ.Mask)
 +              v0.AuxInt = uint8ToAuxInt(0)
 +              v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x8ToM, types.TypeMask)
 +              v1.AddArg(mask)
 +              v0.AddArg3(x, y, v1)
 +              v.AddArg(v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpEqualMaskedInt32x16(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      typ := &b.Func.Config.Types
 +      // match: (EqualMaskedInt32x16 x y mask)
 +      // result: (VPMOVMToVec32x16 (VPCMPDMasked512 [0] x y (VPMOVVec32x16ToM <types.TypeMask> mask)))
 +      for {
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VPMOVMToVec32x16)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPCMPDMasked512, typ.Mask)
 +              v0.AuxInt = uint8ToAuxInt(0)
 +              v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x16ToM, types.TypeMask)
 +              v1.AddArg(mask)
 +              v0.AddArg3(x, y, v1)
 +              v.AddArg(v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpEqualMaskedInt32x4(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      typ := &b.Func.Config.Types
 +      // match: (EqualMaskedInt32x4 x y mask)
 +      // result: (VPMOVMToVec32x4 (VPCMPDMasked128 [0] x y (VPMOVVec32x4ToM <types.TypeMask> mask)))
 +      for {
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VPMOVMToVec32x4)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPCMPDMasked128, typ.Mask)
 +              v0.AuxInt = uint8ToAuxInt(0)
 +              v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x4ToM, types.TypeMask)
 +              v1.AddArg(mask)
 +              v0.AddArg3(x, y, v1)
 +              v.AddArg(v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpEqualMaskedInt32x8(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      typ := &b.Func.Config.Types
 +      // match: (EqualMaskedInt32x8 x y mask)
 +      // result: (VPMOVMToVec32x8 (VPCMPDMasked256 [0] x y (VPMOVVec32x8ToM <types.TypeMask> mask)))
 +      for {
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VPMOVMToVec32x8)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPCMPDMasked256, typ.Mask)
 +              v0.AuxInt = uint8ToAuxInt(0)
 +              v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x8ToM, types.TypeMask)
 +              v1.AddArg(mask)
 +              v0.AddArg3(x, y, v1)
 +              v.AddArg(v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpEqualMaskedInt64x2(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      typ := &b.Func.Config.Types
 +      // match: (EqualMaskedInt64x2 x y mask)
 +      // result: (VPMOVMToVec64x2 (VPCMPQMasked128 [0] x y (VPMOVVec64x2ToM <types.TypeMask> mask)))
 +      for {
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VPMOVMToVec64x2)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPCMPQMasked128, typ.Mask)
 +              v0.AuxInt = uint8ToAuxInt(0)
 +              v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x2ToM, types.TypeMask)
 +              v1.AddArg(mask)
 +              v0.AddArg3(x, y, v1)
 +              v.AddArg(v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpEqualMaskedInt64x4(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      typ := &b.Func.Config.Types
 +      // match: (EqualMaskedInt64x4 x y mask)
 +      // result: (VPMOVMToVec64x4 (VPCMPQMasked256 [0] x y (VPMOVVec64x4ToM <types.TypeMask> mask)))
 +      for {
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VPMOVMToVec64x4)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPCMPQMasked256, typ.Mask)
 +              v0.AuxInt = uint8ToAuxInt(0)
 +              v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x4ToM, types.TypeMask)
 +              v1.AddArg(mask)
 +              v0.AddArg3(x, y, v1)
 +              v.AddArg(v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpEqualMaskedInt64x8(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      typ := &b.Func.Config.Types
 +      // match: (EqualMaskedInt64x8 x y mask)
 +      // result: (VPMOVMToVec64x8 (VPCMPQMasked512 [0] x y (VPMOVVec64x8ToM <types.TypeMask> mask)))
 +      for {
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VPMOVMToVec64x8)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPCMPQMasked512, typ.Mask)
 +              v0.AuxInt = uint8ToAuxInt(0)
 +              v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x8ToM, types.TypeMask)
 +              v1.AddArg(mask)
 +              v0.AddArg3(x, y, v1)
 +              v.AddArg(v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpEqualMaskedInt8x16(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      typ := &b.Func.Config.Types
 +      // match: (EqualMaskedInt8x16 x y mask)
 +      // result: (VPMOVMToVec8x16 (VPCMPBMasked128 [0] x y (VPMOVVec8x16ToM <types.TypeMask> mask)))
 +      for {
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VPMOVMToVec8x16)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPCMPBMasked128, typ.Mask)
 +              v0.AuxInt = uint8ToAuxInt(0)
 +              v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec8x16ToM, types.TypeMask)
 +              v1.AddArg(mask)
 +              v0.AddArg3(x, y, v1)
 +              v.AddArg(v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpEqualMaskedInt8x32(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      typ := &b.Func.Config.Types
 +      // match: (EqualMaskedInt8x32 x y mask)
 +      // result: (VPMOVMToVec8x32 (VPCMPBMasked256 [0] x y (VPMOVVec8x32ToM <types.TypeMask> mask)))
 +      for {
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VPMOVMToVec8x32)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPCMPBMasked256, typ.Mask)
 +              v0.AuxInt = uint8ToAuxInt(0)
 +              v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec8x32ToM, types.TypeMask)
 +              v1.AddArg(mask)
 +              v0.AddArg3(x, y, v1)
 +              v.AddArg(v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpEqualMaskedInt8x64(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      typ := &b.Func.Config.Types
 +      // match: (EqualMaskedInt8x64 x y mask)
 +      // result: (VPMOVMToVec8x64 (VPCMPBMasked512 [0] x y (VPMOVVec8x64ToM <types.TypeMask> mask)))
 +      for {
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VPMOVMToVec8x64)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPCMPBMasked512, typ.Mask)
 +              v0.AuxInt = uint8ToAuxInt(0)
 +              v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec8x64ToM, types.TypeMask)
 +              v1.AddArg(mask)
 +              v0.AddArg3(x, y, v1)
 +              v.AddArg(v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpEqualMaskedUint16x16(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      typ := &b.Func.Config.Types
 +      // match: (EqualMaskedUint16x16 x y mask)
 +      // result: (VPMOVMToVec16x16 (VPCMPUWMasked256 [0] x y (VPMOVVec16x16ToM <types.TypeMask> mask)))
 +      for {
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VPMOVMToVec16x16)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPCMPUWMasked256, typ.Mask)
 +              v0.AuxInt = uint8ToAuxInt(0)
 +              v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x16ToM, types.TypeMask)
 +              v1.AddArg(mask)
 +              v0.AddArg3(x, y, v1)
 +              v.AddArg(v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpEqualMaskedUint16x32(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      typ := &b.Func.Config.Types
 +      // match: (EqualMaskedUint16x32 x y mask)
 +      // result: (VPMOVMToVec16x32 (VPCMPUWMasked512 [0] x y (VPMOVVec16x32ToM <types.TypeMask> mask)))
 +      for {
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VPMOVMToVec16x32)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPCMPUWMasked512, typ.Mask)
 +              v0.AuxInt = uint8ToAuxInt(0)
 +              v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x32ToM, types.TypeMask)
 +              v1.AddArg(mask)
 +              v0.AddArg3(x, y, v1)
 +              v.AddArg(v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpEqualMaskedUint16x8(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      typ := &b.Func.Config.Types
 +      // match: (EqualMaskedUint16x8 x y mask)
 +      // result: (VPMOVMToVec16x8 (VPCMPUWMasked128 [0] x y (VPMOVVec16x8ToM <types.TypeMask> mask)))
 +      for {
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VPMOVMToVec16x8)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPCMPUWMasked128, typ.Mask)
 +              v0.AuxInt = uint8ToAuxInt(0)
 +              v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x8ToM, types.TypeMask)
 +              v1.AddArg(mask)
 +              v0.AddArg3(x, y, v1)
 +              v.AddArg(v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpEqualMaskedUint32x16(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      typ := &b.Func.Config.Types
 +      // match: (EqualMaskedUint32x16 x y mask)
 +      // result: (VPMOVMToVec32x16 (VPCMPUDMasked512 [0] x y (VPMOVVec32x16ToM <types.TypeMask> mask)))
 +      for {
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VPMOVMToVec32x16)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPCMPUDMasked512, typ.Mask)
 +              v0.AuxInt = uint8ToAuxInt(0)
 +              v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x16ToM, types.TypeMask)
 +              v1.AddArg(mask)
 +              v0.AddArg3(x, y, v1)
 +              v.AddArg(v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpEqualMaskedUint32x4(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      typ := &b.Func.Config.Types
 +      // match: (EqualMaskedUint32x4 x y mask)
 +      // result: (VPMOVMToVec32x4 (VPCMPUDMasked128 [0] x y (VPMOVVec32x4ToM <types.TypeMask> mask)))
 +      for {
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VPMOVMToVec32x4)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPCMPUDMasked128, typ.Mask)
 +              v0.AuxInt = uint8ToAuxInt(0)
 +              v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x4ToM, types.TypeMask)
 +              v1.AddArg(mask)
 +              v0.AddArg3(x, y, v1)
 +              v.AddArg(v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpEqualMaskedUint32x8(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      typ := &b.Func.Config.Types
 +      // match: (EqualMaskedUint32x8 x y mask)
 +      // result: (VPMOVMToVec32x8 (VPCMPUDMasked256 [0] x y (VPMOVVec32x8ToM <types.TypeMask> mask)))
 +      for {
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VPMOVMToVec32x8)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPCMPUDMasked256, typ.Mask)
 +              v0.AuxInt = uint8ToAuxInt(0)
 +              v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x8ToM, types.TypeMask)
 +              v1.AddArg(mask)
 +              v0.AddArg3(x, y, v1)
 +              v.AddArg(v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpEqualMaskedUint64x2(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      typ := &b.Func.Config.Types
 +      // match: (EqualMaskedUint64x2 x y mask)
 +      // result: (VPMOVMToVec64x2 (VPCMPUQMasked128 [0] x y (VPMOVVec64x2ToM <types.TypeMask> mask)))
 +      for {
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VPMOVMToVec64x2)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPCMPUQMasked128, typ.Mask)
 +              v0.AuxInt = uint8ToAuxInt(0)
 +              v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x2ToM, types.TypeMask)
 +              v1.AddArg(mask)
 +              v0.AddArg3(x, y, v1)
 +              v.AddArg(v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpEqualMaskedUint64x4(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      typ := &b.Func.Config.Types
 +      // match: (EqualMaskedUint64x4 x y mask)
 +      // result: (VPMOVMToVec64x4 (VPCMPUQMasked256 [0] x y (VPMOVVec64x4ToM <types.TypeMask> mask)))
 +      for {
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VPMOVMToVec64x4)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPCMPUQMasked256, typ.Mask)
 +              v0.AuxInt = uint8ToAuxInt(0)
 +              v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x4ToM, types.TypeMask)
 +              v1.AddArg(mask)
 +              v0.AddArg3(x, y, v1)
 +              v.AddArg(v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpEqualMaskedUint64x8(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      typ := &b.Func.Config.Types
 +      // match: (EqualMaskedUint64x8 x y mask)
 +      // result: (VPMOVMToVec64x8 (VPCMPUQMasked512 [0] x y (VPMOVVec64x8ToM <types.TypeMask> mask)))
 +      for {
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VPMOVMToVec64x8)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPCMPUQMasked512, typ.Mask)
 +              v0.AuxInt = uint8ToAuxInt(0)
 +              v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x8ToM, types.TypeMask)
 +              v1.AddArg(mask)
 +              v0.AddArg3(x, y, v1)
 +              v.AddArg(v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpEqualMaskedUint8x16(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      typ := &b.Func.Config.Types
 +      // match: (EqualMaskedUint8x16 x y mask)
 +      // result: (VPMOVMToVec8x16 (VPCMPUBMasked128 [0] x y (VPMOVVec8x16ToM <types.TypeMask> mask)))
 +      for {
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VPMOVMToVec8x16)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPCMPUBMasked128, typ.Mask)
 +              v0.AuxInt = uint8ToAuxInt(0)
 +              v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec8x16ToM, types.TypeMask)
 +              v1.AddArg(mask)
 +              v0.AddArg3(x, y, v1)
 +              v.AddArg(v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpEqualMaskedUint8x32(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      typ := &b.Func.Config.Types
 +      // match: (EqualMaskedUint8x32 x y mask)
 +      // result: (VPMOVMToVec8x32 (VPCMPUBMasked256 [0] x y (VPMOVVec8x32ToM <types.TypeMask> mask)))
 +      for {
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VPMOVMToVec8x32)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPCMPUBMasked256, typ.Mask)
 +              v0.AuxInt = uint8ToAuxInt(0)
 +              v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec8x32ToM, types.TypeMask)
 +              v1.AddArg(mask)
 +              v0.AddArg3(x, y, v1)
 +              v.AddArg(v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpEqualMaskedUint8x64(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      typ := &b.Func.Config.Types
 +      // match: (EqualMaskedUint8x64 x y mask)
 +      // result: (VPMOVMToVec8x64 (VPCMPUBMasked512 [0] x y (VPMOVVec8x64ToM <types.TypeMask> mask)))
 +      for {
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VPMOVMToVec8x64)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPCMPUBMasked512, typ.Mask)
 +              v0.AuxInt = uint8ToAuxInt(0)
 +              v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec8x64ToM, types.TypeMask)
 +              v1.AddArg(mask)
 +              v0.AddArg3(x, y, v1)
 +              v.AddArg(v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpEqualUint16x32(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      typ := &b.Func.Config.Types
 +      // match: (EqualUint16x32 x y)
 +      // result: (VPMOVMToVec16x32 (VPCMPEQW512 x y))
 +      for {
 +              x := v_0
 +              y := v_1
 +              v.reset(OpAMD64VPMOVMToVec16x32)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPCMPEQW512, typ.Mask)
 +              v0.AddArg2(x, y)
 +              v.AddArg(v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpEqualUint32x16(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      typ := &b.Func.Config.Types
 +      // match: (EqualUint32x16 x y)
 +      // result: (VPMOVMToVec32x16 (VPCMPEQD512 x y))
 +      for {
 +              x := v_0
 +              y := v_1
 +              v.reset(OpAMD64VPMOVMToVec32x16)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPCMPEQD512, typ.Mask)
 +              v0.AddArg2(x, y)
 +              v.AddArg(v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpEqualUint64x8(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      typ := &b.Func.Config.Types
 +      // match: (EqualUint64x8 x y)
 +      // result: (VPMOVMToVec64x8 (VPCMPEQQ512 x y))
 +      for {
 +              x := v_0
 +              y := v_1
 +              v.reset(OpAMD64VPMOVMToVec64x8)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPCMPEQQ512, typ.Mask)
 +              v0.AddArg2(x, y)
 +              v.AddArg(v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpEqualUint8x64(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      typ := &b.Func.Config.Types
 +      // match: (EqualUint8x64 x y)
 +      // result: (VPMOVMToVec8x64 (VPCMPEQB512 x y))
 +      for {
 +              x := v_0
 +              y := v_1
 +              v.reset(OpAMD64VPMOVMToVec8x64)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPCMPEQB512, typ.Mask)
 +              v0.AddArg2(x, y)
 +              v.AddArg(v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpExpandFloat32x16(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (ExpandFloat32x16 x mask)
 +      // result: (VEXPANDPSMasked512 x (VPMOVVec32x16ToM <types.TypeMask> mask))
 +      for {
 +              x := v_0
 +              mask := v_1
 +              v.reset(OpAMD64VEXPANDPSMasked512)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x16ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg2(x, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpExpandFloat32x4(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (ExpandFloat32x4 x mask)
 +      // result: (VEXPANDPSMasked128 x (VPMOVVec32x4ToM <types.TypeMask> mask))
 +      for {
 +              x := v_0
 +              mask := v_1
 +              v.reset(OpAMD64VEXPANDPSMasked128)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x4ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg2(x, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpExpandFloat32x8(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (ExpandFloat32x8 x mask)
 +      // result: (VEXPANDPSMasked256 x (VPMOVVec32x8ToM <types.TypeMask> mask))
 +      for {
 +              x := v_0
 +              mask := v_1
 +              v.reset(OpAMD64VEXPANDPSMasked256)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x8ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg2(x, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpExpandFloat64x2(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (ExpandFloat64x2 x mask)
 +      // result: (VEXPANDPDMasked128 x (VPMOVVec64x2ToM <types.TypeMask> mask))
 +      for {
 +              x := v_0
 +              mask := v_1
 +              v.reset(OpAMD64VEXPANDPDMasked128)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x2ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg2(x, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpExpandFloat64x4(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (ExpandFloat64x4 x mask)
 +      // result: (VEXPANDPDMasked256 x (VPMOVVec64x4ToM <types.TypeMask> mask))
 +      for {
 +              x := v_0
 +              mask := v_1
 +              v.reset(OpAMD64VEXPANDPDMasked256)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x4ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg2(x, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpExpandFloat64x8(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (ExpandFloat64x8 x mask)
 +      // result: (VEXPANDPDMasked512 x (VPMOVVec64x8ToM <types.TypeMask> mask))
 +      for {
 +              x := v_0
 +              mask := v_1
 +              v.reset(OpAMD64VEXPANDPDMasked512)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x8ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg2(x, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpExpandInt16x16(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (ExpandInt16x16 x mask)
 +      // result: (VPEXPANDWMasked256 x (VPMOVVec16x16ToM <types.TypeMask> mask))
 +      for {
 +              x := v_0
 +              mask := v_1
 +              v.reset(OpAMD64VPEXPANDWMasked256)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x16ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg2(x, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpExpandInt16x32(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (ExpandInt16x32 x mask)
 +      // result: (VPEXPANDWMasked512 x (VPMOVVec16x32ToM <types.TypeMask> mask))
 +      for {
 +              x := v_0
 +              mask := v_1
 +              v.reset(OpAMD64VPEXPANDWMasked512)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x32ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg2(x, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpExpandInt16x8(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (ExpandInt16x8 x mask)
 +      // result: (VPEXPANDWMasked128 x (VPMOVVec16x8ToM <types.TypeMask> mask))
 +      for {
 +              x := v_0
 +              mask := v_1
 +              v.reset(OpAMD64VPEXPANDWMasked128)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x8ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg2(x, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpExpandInt32x16(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (ExpandInt32x16 x mask)
 +      // result: (VPEXPANDDMasked512 x (VPMOVVec32x16ToM <types.TypeMask> mask))
 +      for {
 +              x := v_0
 +              mask := v_1
 +              v.reset(OpAMD64VPEXPANDDMasked512)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x16ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg2(x, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpExpandInt32x4(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (ExpandInt32x4 x mask)
 +      // result: (VPEXPANDDMasked128 x (VPMOVVec32x4ToM <types.TypeMask> mask))
 +      for {
 +              x := v_0
 +              mask := v_1
 +              v.reset(OpAMD64VPEXPANDDMasked128)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x4ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg2(x, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpExpandInt32x8(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (ExpandInt32x8 x mask)
 +      // result: (VPEXPANDDMasked256 x (VPMOVVec32x8ToM <types.TypeMask> mask))
 +      for {
 +              x := v_0
 +              mask := v_1
 +              v.reset(OpAMD64VPEXPANDDMasked256)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x8ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg2(x, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpExpandInt64x2(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (ExpandInt64x2 x mask)
 +      // result: (VPEXPANDQMasked128 x (VPMOVVec64x2ToM <types.TypeMask> mask))
 +      for {
 +              x := v_0
 +              mask := v_1
 +              v.reset(OpAMD64VPEXPANDQMasked128)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x2ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg2(x, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpExpandInt64x4(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (ExpandInt64x4 x mask)
 +      // result: (VPEXPANDQMasked256 x (VPMOVVec64x4ToM <types.TypeMask> mask))
 +      for {
 +              x := v_0
 +              mask := v_1
 +              v.reset(OpAMD64VPEXPANDQMasked256)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x4ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg2(x, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpExpandInt64x8(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (ExpandInt64x8 x mask)
 +      // result: (VPEXPANDQMasked512 x (VPMOVVec64x8ToM <types.TypeMask> mask))
 +      for {
 +              x := v_0
 +              mask := v_1
 +              v.reset(OpAMD64VPEXPANDQMasked512)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x8ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg2(x, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpExpandInt8x16(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (ExpandInt8x16 x mask)
 +      // result: (VPEXPANDBMasked128 x (VPMOVVec8x16ToM <types.TypeMask> mask))
 +      for {
 +              x := v_0
 +              mask := v_1
 +              v.reset(OpAMD64VPEXPANDBMasked128)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec8x16ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg2(x, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpExpandInt8x32(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (ExpandInt8x32 x mask)
 +      // result: (VPEXPANDBMasked256 x (VPMOVVec8x32ToM <types.TypeMask> mask))
 +      for {
 +              x := v_0
 +              mask := v_1
 +              v.reset(OpAMD64VPEXPANDBMasked256)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec8x32ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg2(x, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpExpandInt8x64(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (ExpandInt8x64 x mask)
 +      // result: (VPEXPANDBMasked512 x (VPMOVVec8x64ToM <types.TypeMask> mask))
 +      for {
 +              x := v_0
 +              mask := v_1
 +              v.reset(OpAMD64VPEXPANDBMasked512)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec8x64ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg2(x, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpExpandUint16x16(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (ExpandUint16x16 x mask)
 +      // result: (VPEXPANDWMasked256 x (VPMOVVec16x16ToM <types.TypeMask> mask))
 +      for {
 +              x := v_0
 +              mask := v_1
 +              v.reset(OpAMD64VPEXPANDWMasked256)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x16ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg2(x, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpExpandUint16x32(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (ExpandUint16x32 x mask)
 +      // result: (VPEXPANDWMasked512 x (VPMOVVec16x32ToM <types.TypeMask> mask))
 +      for {
 +              x := v_0
 +              mask := v_1
 +              v.reset(OpAMD64VPEXPANDWMasked512)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x32ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg2(x, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpExpandUint16x8(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (ExpandUint16x8 x mask)
 +      // result: (VPEXPANDWMasked128 x (VPMOVVec16x8ToM <types.TypeMask> mask))
 +      for {
 +              x := v_0
 +              mask := v_1
 +              v.reset(OpAMD64VPEXPANDWMasked128)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x8ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg2(x, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpExpandUint32x16(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (ExpandUint32x16 x mask)
 +      // result: (VPEXPANDDMasked512 x (VPMOVVec32x16ToM <types.TypeMask> mask))
 +      for {
 +              x := v_0
 +              mask := v_1
 +              v.reset(OpAMD64VPEXPANDDMasked512)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x16ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg2(x, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpExpandUint32x4(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (ExpandUint32x4 x mask)
 +      // result: (VPEXPANDDMasked128 x (VPMOVVec32x4ToM <types.TypeMask> mask))
 +      for {
 +              x := v_0
 +              mask := v_1
 +              v.reset(OpAMD64VPEXPANDDMasked128)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x4ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg2(x, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpExpandUint32x8(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (ExpandUint32x8 x mask)
 +      // result: (VPEXPANDDMasked256 x (VPMOVVec32x8ToM <types.TypeMask> mask))
 +      for {
 +              x := v_0
 +              mask := v_1
 +              v.reset(OpAMD64VPEXPANDDMasked256)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x8ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg2(x, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpExpandUint64x2(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (ExpandUint64x2 x mask)
 +      // result: (VPEXPANDQMasked128 x (VPMOVVec64x2ToM <types.TypeMask> mask))
 +      for {
 +              x := v_0
 +              mask := v_1
 +              v.reset(OpAMD64VPEXPANDQMasked128)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x2ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg2(x, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpExpandUint64x4(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (ExpandUint64x4 x mask)
 +      // result: (VPEXPANDQMasked256 x (VPMOVVec64x4ToM <types.TypeMask> mask))
 +      for {
 +              x := v_0
 +              mask := v_1
 +              v.reset(OpAMD64VPEXPANDQMasked256)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x4ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg2(x, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpExpandUint64x8(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (ExpandUint64x8 x mask)
 +      // result: (VPEXPANDQMasked512 x (VPMOVVec64x8ToM <types.TypeMask> mask))
 +      for {
 +              x := v_0
 +              mask := v_1
 +              v.reset(OpAMD64VPEXPANDQMasked512)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x8ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg2(x, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpExpandUint8x16(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (ExpandUint8x16 x mask)
 +      // result: (VPEXPANDBMasked128 x (VPMOVVec8x16ToM <types.TypeMask> mask))
 +      for {
 +              x := v_0
 +              mask := v_1
 +              v.reset(OpAMD64VPEXPANDBMasked128)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec8x16ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg2(x, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpExpandUint8x32(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (ExpandUint8x32 x mask)
 +      // result: (VPEXPANDBMasked256 x (VPMOVVec8x32ToM <types.TypeMask> mask))
 +      for {
 +              x := v_0
 +              mask := v_1
 +              v.reset(OpAMD64VPEXPANDBMasked256)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec8x32ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg2(x, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpExpandUint8x64(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (ExpandUint8x64 x mask)
 +      // result: (VPEXPANDBMasked512 x (VPMOVVec8x64ToM <types.TypeMask> mask))
 +      for {
 +              x := v_0
 +              mask := v_1
 +              v.reset(OpAMD64VPEXPANDBMasked512)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec8x64ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg2(x, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpFMA(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      // match: (FMA x y z)
 +      // result: (VFMADD231SD z x y)
 +      for {
 +              x := v_0
 +              y := v_1
 +              z := v_2
 +              v.reset(OpAMD64VFMADD231SD)
 +              v.AddArg3(z, x, y)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpFloor(v *Value) bool {
 +      v_0 := v.Args[0]
 +      // match: (Floor x)
 +      // result: (ROUNDSD [1] x)
 +      for {
 +              x := v_0
 +              v.reset(OpAMD64ROUNDSD)
 +              v.AuxInt = int8ToAuxInt(1)
 +              v.AddArg(x)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpFloorFloat32x4(v *Value) bool {
 +      v_0 := v.Args[0]
 +      // match: (FloorFloat32x4 x)
 +      // result: (VROUNDPS128 [1] x)
 +      for {
 +              x := v_0
 +              v.reset(OpAMD64VROUNDPS128)
 +              v.AuxInt = uint8ToAuxInt(1)
 +              v.AddArg(x)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpFloorFloat32x8(v *Value) bool {
 +      v_0 := v.Args[0]
 +      // match: (FloorFloat32x8 x)
 +      // result: (VROUNDPS256 [1] x)
 +      for {
 +              x := v_0
 +              v.reset(OpAMD64VROUNDPS256)
 +              v.AuxInt = uint8ToAuxInt(1)
 +              v.AddArg(x)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpFloorFloat64x2(v *Value) bool {
 +      v_0 := v.Args[0]
 +      // match: (FloorFloat64x2 x)
 +      // result: (VROUNDPD128 [1] x)
 +      for {
 +              x := v_0
 +              v.reset(OpAMD64VROUNDPD128)
 +              v.AuxInt = uint8ToAuxInt(1)
 +              v.AddArg(x)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpFloorFloat64x4(v *Value) bool {
 +      v_0 := v.Args[0]
 +      // match: (FloorFloat64x4 x)
 +      // result: (VROUNDPD256 [1] x)
 +      for {
 +              x := v_0
 +              v.reset(OpAMD64VROUNDPD256)
 +              v.AuxInt = uint8ToAuxInt(1)
 +              v.AddArg(x)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpFloorScaledFloat32x16(v *Value) bool {
 +      v_0 := v.Args[0]
 +      // match: (FloorScaledFloat32x16 [a] x)
 +      // result: (VRNDSCALEPS512 [a+1] x)
 +      for {
 +              a := auxIntToUint8(v.AuxInt)
 +              x := v_0
 +              v.reset(OpAMD64VRNDSCALEPS512)
 +              v.AuxInt = uint8ToAuxInt(a + 1)
 +              v.AddArg(x)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpFloorScaledFloat32x4(v *Value) bool {
 +      v_0 := v.Args[0]
 +      // match: (FloorScaledFloat32x4 [a] x)
 +      // result: (VRNDSCALEPS128 [a+1] x)
 +      for {
 +              a := auxIntToUint8(v.AuxInt)
 +              x := v_0
 +              v.reset(OpAMD64VRNDSCALEPS128)
 +              v.AuxInt = uint8ToAuxInt(a + 1)
 +              v.AddArg(x)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpFloorScaledFloat32x8(v *Value) bool {
 +      v_0 := v.Args[0]
 +      // match: (FloorScaledFloat32x8 [a] x)
 +      // result: (VRNDSCALEPS256 [a+1] x)
 +      for {
 +              a := auxIntToUint8(v.AuxInt)
 +              x := v_0
 +              v.reset(OpAMD64VRNDSCALEPS256)
 +              v.AuxInt = uint8ToAuxInt(a + 1)
 +              v.AddArg(x)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpFloorScaledFloat64x2(v *Value) bool {
 +      v_0 := v.Args[0]
 +      // match: (FloorScaledFloat64x2 [a] x)
 +      // result: (VRNDSCALEPD128 [a+1] x)
 +      for {
 +              a := auxIntToUint8(v.AuxInt)
 +              x := v_0
 +              v.reset(OpAMD64VRNDSCALEPD128)
 +              v.AuxInt = uint8ToAuxInt(a + 1)
 +              v.AddArg(x)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpFloorScaledFloat64x4(v *Value) bool {
 +      v_0 := v.Args[0]
 +      // match: (FloorScaledFloat64x4 [a] x)
 +      // result: (VRNDSCALEPD256 [a+1] x)
 +      for {
 +              a := auxIntToUint8(v.AuxInt)
 +              x := v_0
 +              v.reset(OpAMD64VRNDSCALEPD256)
 +              v.AuxInt = uint8ToAuxInt(a + 1)
 +              v.AddArg(x)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpFloorScaledFloat64x8(v *Value) bool {
 +      v_0 := v.Args[0]
 +      // match: (FloorScaledFloat64x8 [a] x)
 +      // result: (VRNDSCALEPD512 [a+1] x)
 +      for {
 +              a := auxIntToUint8(v.AuxInt)
 +              x := v_0
 +              v.reset(OpAMD64VRNDSCALEPD512)
 +              v.AuxInt = uint8ToAuxInt(a + 1)
 +              v.AddArg(x)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpFloorScaledMaskedFloat32x16(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (FloorScaledMaskedFloat32x16 [a] x mask)
 +      // result: (VRNDSCALEPSMasked512 [a+1] x (VPMOVVec32x16ToM <types.TypeMask> mask))
 +      for {
 +              a := auxIntToUint8(v.AuxInt)
 +              x := v_0
 +              mask := v_1
 +              v.reset(OpAMD64VRNDSCALEPSMasked512)
 +              v.AuxInt = uint8ToAuxInt(a + 1)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x16ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg2(x, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpFloorScaledMaskedFloat32x4(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (FloorScaledMaskedFloat32x4 [a] x mask)
 +      // result: (VRNDSCALEPSMasked128 [a+1] x (VPMOVVec32x4ToM <types.TypeMask> mask))
 +      for {
 +              a := auxIntToUint8(v.AuxInt)
 +              x := v_0
 +              mask := v_1
 +              v.reset(OpAMD64VRNDSCALEPSMasked128)
 +              v.AuxInt = uint8ToAuxInt(a + 1)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x4ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg2(x, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpFloorScaledMaskedFloat32x8(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (FloorScaledMaskedFloat32x8 [a] x mask)
 +      // result: (VRNDSCALEPSMasked256 [a+1] x (VPMOVVec32x8ToM <types.TypeMask> mask))
 +      for {
 +              a := auxIntToUint8(v.AuxInt)
 +              x := v_0
 +              mask := v_1
 +              v.reset(OpAMD64VRNDSCALEPSMasked256)
 +              v.AuxInt = uint8ToAuxInt(a + 1)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x8ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg2(x, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpFloorScaledMaskedFloat64x2(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (FloorScaledMaskedFloat64x2 [a] x mask)
 +      // result: (VRNDSCALEPDMasked128 [a+1] x (VPMOVVec64x2ToM <types.TypeMask> mask))
 +      for {
 +              a := auxIntToUint8(v.AuxInt)
 +              x := v_0
 +              mask := v_1
 +              v.reset(OpAMD64VRNDSCALEPDMasked128)
 +              v.AuxInt = uint8ToAuxInt(a + 1)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x2ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg2(x, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpFloorScaledMaskedFloat64x4(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (FloorScaledMaskedFloat64x4 [a] x mask)
 +      // result: (VRNDSCALEPDMasked256 [a+1] x (VPMOVVec64x4ToM <types.TypeMask> mask))
 +      for {
 +              a := auxIntToUint8(v.AuxInt)
 +              x := v_0
 +              mask := v_1
 +              v.reset(OpAMD64VRNDSCALEPDMasked256)
 +              v.AuxInt = uint8ToAuxInt(a + 1)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x4ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg2(x, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpFloorScaledMaskedFloat64x8(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (FloorScaledMaskedFloat64x8 [a] x mask)
 +      // result: (VRNDSCALEPDMasked512 [a+1] x (VPMOVVec64x8ToM <types.TypeMask> mask))
 +      for {
 +              a := auxIntToUint8(v.AuxInt)
 +              x := v_0
 +              mask := v_1
 +              v.reset(OpAMD64VRNDSCALEPDMasked512)
 +              v.AuxInt = uint8ToAuxInt(a + 1)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x8ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg2(x, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpFloorScaledResidueFloat32x16(v *Value) bool {
 +      v_0 := v.Args[0]
 +      // match: (FloorScaledResidueFloat32x16 [a] x)
 +      // result: (VREDUCEPS512 [a+1] x)
 +      for {
 +              a := auxIntToUint8(v.AuxInt)
 +              x := v_0
 +              v.reset(OpAMD64VREDUCEPS512)
 +              v.AuxInt = uint8ToAuxInt(a + 1)
 +              v.AddArg(x)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpFloorScaledResidueFloat32x4(v *Value) bool {
 +      v_0 := v.Args[0]
 +      // match: (FloorScaledResidueFloat32x4 [a] x)
 +      // result: (VREDUCEPS128 [a+1] x)
 +      for {
 +              a := auxIntToUint8(v.AuxInt)
 +              x := v_0
 +              v.reset(OpAMD64VREDUCEPS128)
 +              v.AuxInt = uint8ToAuxInt(a + 1)
 +              v.AddArg(x)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpFloorScaledResidueFloat32x8(v *Value) bool {
 +      v_0 := v.Args[0]
 +      // match: (FloorScaledResidueFloat32x8 [a] x)
 +      // result: (VREDUCEPS256 [a+1] x)
 +      for {
 +              a := auxIntToUint8(v.AuxInt)
 +              x := v_0
 +              v.reset(OpAMD64VREDUCEPS256)
 +              v.AuxInt = uint8ToAuxInt(a + 1)
 +              v.AddArg(x)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpFloorScaledResidueFloat64x2(v *Value) bool {
 +      v_0 := v.Args[0]
 +      // match: (FloorScaledResidueFloat64x2 [a] x)
 +      // result: (VREDUCEPD128 [a+1] x)
 +      for {
 +              a := auxIntToUint8(v.AuxInt)
 +              x := v_0
 +              v.reset(OpAMD64VREDUCEPD128)
 +              v.AuxInt = uint8ToAuxInt(a + 1)
 +              v.AddArg(x)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpFloorScaledResidueFloat64x4(v *Value) bool {
 +      v_0 := v.Args[0]
 +      // match: (FloorScaledResidueFloat64x4 [a] x)
 +      // result: (VREDUCEPD256 [a+1] x)
 +      for {
 +              a := auxIntToUint8(v.AuxInt)
 +              x := v_0
 +              v.reset(OpAMD64VREDUCEPD256)
 +              v.AuxInt = uint8ToAuxInt(a + 1)
 +              v.AddArg(x)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpFloorScaledResidueFloat64x8(v *Value) bool {
 +      v_0 := v.Args[0]
 +      // match: (FloorScaledResidueFloat64x8 [a] x)
 +      // result: (VREDUCEPD512 [a+1] x)
 +      for {
 +              a := auxIntToUint8(v.AuxInt)
 +              x := v_0
 +              v.reset(OpAMD64VREDUCEPD512)
 +              v.AuxInt = uint8ToAuxInt(a + 1)
 +              v.AddArg(x)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpFloorScaledResidueMaskedFloat32x16(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (FloorScaledResidueMaskedFloat32x16 [a] x mask)
 +      // result: (VREDUCEPSMasked512 [a+1] x (VPMOVVec32x16ToM <types.TypeMask> mask))
 +      for {
 +              a := auxIntToUint8(v.AuxInt)
 +              x := v_0
 +              mask := v_1
 +              v.reset(OpAMD64VREDUCEPSMasked512)
 +              v.AuxInt = uint8ToAuxInt(a + 1)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x16ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg2(x, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpFloorScaledResidueMaskedFloat32x4(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (FloorScaledResidueMaskedFloat32x4 [a] x mask)
 +      // result: (VREDUCEPSMasked128 [a+1] x (VPMOVVec32x4ToM <types.TypeMask> mask))
 +      for {
 +              a := auxIntToUint8(v.AuxInt)
 +              x := v_0
 +              mask := v_1
 +              v.reset(OpAMD64VREDUCEPSMasked128)
 +              v.AuxInt = uint8ToAuxInt(a + 1)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x4ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg2(x, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpFloorScaledResidueMaskedFloat32x8(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (FloorScaledResidueMaskedFloat32x8 [a] x mask)
 +      // result: (VREDUCEPSMasked256 [a+1] x (VPMOVVec32x8ToM <types.TypeMask> mask))
 +      for {
 +              a := auxIntToUint8(v.AuxInt)
 +              x := v_0
 +              mask := v_1
 +              v.reset(OpAMD64VREDUCEPSMasked256)
 +              v.AuxInt = uint8ToAuxInt(a + 1)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x8ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg2(x, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpFloorScaledResidueMaskedFloat64x2(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (FloorScaledResidueMaskedFloat64x2 [a] x mask)
 +      // result: (VREDUCEPDMasked128 [a+1] x (VPMOVVec64x2ToM <types.TypeMask> mask))
 +      for {
 +              a := auxIntToUint8(v.AuxInt)
 +              x := v_0
 +              mask := v_1
 +              v.reset(OpAMD64VREDUCEPDMasked128)
 +              v.AuxInt = uint8ToAuxInt(a + 1)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x2ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg2(x, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpFloorScaledResidueMaskedFloat64x4(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (FloorScaledResidueMaskedFloat64x4 [a] x mask)
 +      // result: (VREDUCEPDMasked256 [a+1] x (VPMOVVec64x4ToM <types.TypeMask> mask))
 +      for {
 +              a := auxIntToUint8(v.AuxInt)
 +              x := v_0
 +              mask := v_1
 +              v.reset(OpAMD64VREDUCEPDMasked256)
 +              v.AuxInt = uint8ToAuxInt(a + 1)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x4ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg2(x, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpFloorScaledResidueMaskedFloat64x8(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (FloorScaledResidueMaskedFloat64x8 [a] x mask)
 +      // result: (VREDUCEPDMasked512 [a+1] x (VPMOVVec64x8ToM <types.TypeMask> mask))
 +      for {
 +              a := auxIntToUint8(v.AuxInt)
 +              x := v_0
 +              mask := v_1
 +              v.reset(OpAMD64VREDUCEPDMasked512)
 +              v.AuxInt = uint8ToAuxInt(a + 1)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x8ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg2(x, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpGaloisFieldAffineTransformInverseMaskedUint8x16(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (GaloisFieldAffineTransformInverseMaskedUint8x16 [a] x y mask)
 +      // result: (VGF2P8AFFINEINVQBMasked128 [a] x y (VPMOVVec8x16ToM <types.TypeMask> mask))
 +      for {
 +              a := auxIntToUint8(v.AuxInt)
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VGF2P8AFFINEINVQBMasked128)
 +              v.AuxInt = uint8ToAuxInt(a)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec8x16ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg3(x, y, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpGaloisFieldAffineTransformInverseMaskedUint8x32(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (GaloisFieldAffineTransformInverseMaskedUint8x32 [a] x y mask)
 +      // result: (VGF2P8AFFINEINVQBMasked256 [a] x y (VPMOVVec8x32ToM <types.TypeMask> mask))
 +      for {
 +              a := auxIntToUint8(v.AuxInt)
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VGF2P8AFFINEINVQBMasked256)
 +              v.AuxInt = uint8ToAuxInt(a)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec8x32ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg3(x, y, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpGaloisFieldAffineTransformInverseMaskedUint8x64(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (GaloisFieldAffineTransformInverseMaskedUint8x64 [a] x y mask)
 +      // result: (VGF2P8AFFINEINVQBMasked512 [a] x y (VPMOVVec8x64ToM <types.TypeMask> mask))
 +      for {
 +              a := auxIntToUint8(v.AuxInt)
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VGF2P8AFFINEINVQBMasked512)
 +              v.AuxInt = uint8ToAuxInt(a)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec8x64ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg3(x, y, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpGaloisFieldAffineTransformMaskedUint8x16(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (GaloisFieldAffineTransformMaskedUint8x16 [a] x y mask)
 +      // result: (VGF2P8AFFINEQBMasked128 [a] x y (VPMOVVec8x16ToM <types.TypeMask> mask))
 +      for {
 +              a := auxIntToUint8(v.AuxInt)
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VGF2P8AFFINEQBMasked128)
 +              v.AuxInt = uint8ToAuxInt(a)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec8x16ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg3(x, y, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpGaloisFieldAffineTransformMaskedUint8x32(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (GaloisFieldAffineTransformMaskedUint8x32 [a] x y mask)
 +      // result: (VGF2P8AFFINEQBMasked256 [a] x y (VPMOVVec8x32ToM <types.TypeMask> mask))
 +      for {
 +              a := auxIntToUint8(v.AuxInt)
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VGF2P8AFFINEQBMasked256)
 +              v.AuxInt = uint8ToAuxInt(a)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec8x32ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg3(x, y, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpGaloisFieldAffineTransformMaskedUint8x64(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (GaloisFieldAffineTransformMaskedUint8x64 [a] x y mask)
 +      // result: (VGF2P8AFFINEQBMasked512 [a] x y (VPMOVVec8x64ToM <types.TypeMask> mask))
 +      for {
 +              a := auxIntToUint8(v.AuxInt)
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VGF2P8AFFINEQBMasked512)
 +              v.AuxInt = uint8ToAuxInt(a)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec8x64ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg3(x, y, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpGaloisFieldMulMaskedUint8x16(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (GaloisFieldMulMaskedUint8x16 x y mask)
 +      // result: (VGF2P8MULBMasked128 x y (VPMOVVec8x16ToM <types.TypeMask> mask))
 +      for {
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VGF2P8MULBMasked128)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec8x16ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg3(x, y, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpGaloisFieldMulMaskedUint8x32(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (GaloisFieldMulMaskedUint8x32 x y mask)
 +      // result: (VGF2P8MULBMasked256 x y (VPMOVVec8x32ToM <types.TypeMask> mask))
 +      for {
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VGF2P8MULBMasked256)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec8x32ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg3(x, y, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpGaloisFieldMulMaskedUint8x64(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (GaloisFieldMulMaskedUint8x64 x y mask)
 +      // result: (VGF2P8MULBMasked512 x y (VPMOVVec8x64ToM <types.TypeMask> mask))
 +      for {
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VGF2P8MULBMasked512)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec8x64ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg3(x, y, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpGetG(v *Value) bool {
 +      v_0 := v.Args[0]
 +      // match: (GetG mem)
 +      // cond: v.Block.Func.OwnAux.Fn.ABI() != obj.ABIInternal
 +      // result: (LoweredGetG mem)
 +      for {
 +              mem := v_0
 +              if !(v.Block.Func.OwnAux.Fn.ABI() != obj.ABIInternal) {
 +                      break
 +              }
 +              v.reset(OpAMD64LoweredGetG)
 +              v.AddArg(mem)
 +              return true
 +      }
 +      return false
 +}
 +func rewriteValueAMD64_OpGetHiFloat32x16(v *Value) bool {
 +      v_0 := v.Args[0]
 +      // match: (GetHiFloat32x16 x)
 +      // result: (VEXTRACTF64X4256 [1] x)
 +      for {
 +              x := v_0
 +              v.reset(OpAMD64VEXTRACTF64X4256)
 +              v.AuxInt = uint8ToAuxInt(1)
 +              v.AddArg(x)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpGetHiFloat32x8(v *Value) bool {
 +      v_0 := v.Args[0]
 +      // match: (GetHiFloat32x8 x)
 +      // result: (VEXTRACTF128128 [1] x)
 +      for {
 +              x := v_0
 +              v.reset(OpAMD64VEXTRACTF128128)
 +              v.AuxInt = uint8ToAuxInt(1)
 +              v.AddArg(x)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpGetHiFloat64x4(v *Value) bool {
 +      v_0 := v.Args[0]
 +      // match: (GetHiFloat64x4 x)
 +      // result: (VEXTRACTF128128 [1] x)
 +      for {
 +              x := v_0
 +              v.reset(OpAMD64VEXTRACTF128128)
 +              v.AuxInt = uint8ToAuxInt(1)
 +              v.AddArg(x)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpGetHiFloat64x8(v *Value) bool {
 +      v_0 := v.Args[0]
 +      // match: (GetHiFloat64x8 x)
 +      // result: (VEXTRACTF64X4256 [1] x)
 +      for {
 +              x := v_0
 +              v.reset(OpAMD64VEXTRACTF64X4256)
 +              v.AuxInt = uint8ToAuxInt(1)
 +              v.AddArg(x)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpGetHiInt16x16(v *Value) bool {
 +      v_0 := v.Args[0]
 +      // match: (GetHiInt16x16 x)
 +      // result: (VEXTRACTI128128 [1] x)
 +      for {
 +              x := v_0
 +              v.reset(OpAMD64VEXTRACTI128128)
 +              v.AuxInt = uint8ToAuxInt(1)
 +              v.AddArg(x)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpGetHiInt16x32(v *Value) bool {
 +      v_0 := v.Args[0]
 +      // match: (GetHiInt16x32 x)
 +      // result: (VEXTRACTI64X4256 [1] x)
 +      for {
 +              x := v_0
 +              v.reset(OpAMD64VEXTRACTI64X4256)
 +              v.AuxInt = uint8ToAuxInt(1)
 +              v.AddArg(x)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpGetHiInt32x16(v *Value) bool {
 +      v_0 := v.Args[0]
 +      // match: (GetHiInt32x16 x)
 +      // result: (VEXTRACTI64X4256 [1] x)
 +      for {
 +              x := v_0
 +              v.reset(OpAMD64VEXTRACTI64X4256)
 +              v.AuxInt = uint8ToAuxInt(1)
 +              v.AddArg(x)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpGetHiInt32x8(v *Value) bool {
 +      v_0 := v.Args[0]
 +      // match: (GetHiInt32x8 x)
 +      // result: (VEXTRACTI128128 [1] x)
 +      for {
 +              x := v_0
 +              v.reset(OpAMD64VEXTRACTI128128)
 +              v.AuxInt = uint8ToAuxInt(1)
 +              v.AddArg(x)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpGetHiInt64x4(v *Value) bool {
 +      v_0 := v.Args[0]
 +      // match: (GetHiInt64x4 x)
 +      // result: (VEXTRACTI128128 [1] x)
 +      for {
 +              x := v_0
 +              v.reset(OpAMD64VEXTRACTI128128)
 +              v.AuxInt = uint8ToAuxInt(1)
 +              v.AddArg(x)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpGetHiInt64x8(v *Value) bool {
 +      v_0 := v.Args[0]
 +      // match: (GetHiInt64x8 x)
 +      // result: (VEXTRACTI64X4256 [1] x)
 +      for {
 +              x := v_0
 +              v.reset(OpAMD64VEXTRACTI64X4256)
 +              v.AuxInt = uint8ToAuxInt(1)
 +              v.AddArg(x)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpGetHiInt8x32(v *Value) bool {
 +      v_0 := v.Args[0]
 +      // match: (GetHiInt8x32 x)
 +      // result: (VEXTRACTI128128 [1] x)
 +      for {
 +              x := v_0
 +              v.reset(OpAMD64VEXTRACTI128128)
 +              v.AuxInt = uint8ToAuxInt(1)
 +              v.AddArg(x)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpGetHiInt8x64(v *Value) bool {
 +      v_0 := v.Args[0]
 +      // match: (GetHiInt8x64 x)
 +      // result: (VEXTRACTI64X4256 [1] x)
 +      for {
 +              x := v_0
 +              v.reset(OpAMD64VEXTRACTI64X4256)
 +              v.AuxInt = uint8ToAuxInt(1)
 +              v.AddArg(x)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpGetHiUint16x16(v *Value) bool {
 +      v_0 := v.Args[0]
 +      // match: (GetHiUint16x16 x)
 +      // result: (VEXTRACTI128128 [1] x)
 +      for {
 +              x := v_0
 +              v.reset(OpAMD64VEXTRACTI128128)
 +              v.AuxInt = uint8ToAuxInt(1)
 +              v.AddArg(x)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpGetHiUint16x32(v *Value) bool {
 +      v_0 := v.Args[0]
 +      // match: (GetHiUint16x32 x)
 +      // result: (VEXTRACTI64X4256 [1] x)
 +      for {
 +              x := v_0
 +              v.reset(OpAMD64VEXTRACTI64X4256)
 +              v.AuxInt = uint8ToAuxInt(1)
 +              v.AddArg(x)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpGetHiUint32x16(v *Value) bool {
 +      v_0 := v.Args[0]
 +      // match: (GetHiUint32x16 x)
 +      // result: (VEXTRACTI64X4256 [1] x)
 +      for {
 +              x := v_0
 +              v.reset(OpAMD64VEXTRACTI64X4256)
 +              v.AuxInt = uint8ToAuxInt(1)
 +              v.AddArg(x)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpGetHiUint32x8(v *Value) bool {
 +      v_0 := v.Args[0]
 +      // match: (GetHiUint32x8 x)
 +      // result: (VEXTRACTI128128 [1] x)
 +      for {
 +              x := v_0
 +              v.reset(OpAMD64VEXTRACTI128128)
 +              v.AuxInt = uint8ToAuxInt(1)
 +              v.AddArg(x)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpGetHiUint64x4(v *Value) bool {
 +      v_0 := v.Args[0]
 +      // match: (GetHiUint64x4 x)
 +      // result: (VEXTRACTI128128 [1] x)
 +      for {
 +              x := v_0
 +              v.reset(OpAMD64VEXTRACTI128128)
 +              v.AuxInt = uint8ToAuxInt(1)
 +              v.AddArg(x)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpGetHiUint64x8(v *Value) bool {
 +      v_0 := v.Args[0]
 +      // match: (GetHiUint64x8 x)
 +      // result: (VEXTRACTI64X4256 [1] x)
 +      for {
 +              x := v_0
 +              v.reset(OpAMD64VEXTRACTI64X4256)
 +              v.AuxInt = uint8ToAuxInt(1)
 +              v.AddArg(x)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpGetHiUint8x32(v *Value) bool {
 +      v_0 := v.Args[0]
 +      // match: (GetHiUint8x32 x)
 +      // result: (VEXTRACTI128128 [1] x)
 +      for {
 +              x := v_0
 +              v.reset(OpAMD64VEXTRACTI128128)
 +              v.AuxInt = uint8ToAuxInt(1)
 +              v.AddArg(x)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpGetHiUint8x64(v *Value) bool {
 +      v_0 := v.Args[0]
 +      // match: (GetHiUint8x64 x)
 +      // result: (VEXTRACTI64X4256 [1] x)
 +      for {
 +              x := v_0
 +              v.reset(OpAMD64VEXTRACTI64X4256)
 +              v.AuxInt = uint8ToAuxInt(1)
 +              v.AddArg(x)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpGetLoFloat32x16(v *Value) bool {
 +      v_0 := v.Args[0]
 +      // match: (GetLoFloat32x16 x)
 +      // result: (VEXTRACTF64X4256 [0] x)
 +      for {
 +              x := v_0
 +              v.reset(OpAMD64VEXTRACTF64X4256)
 +              v.AuxInt = uint8ToAuxInt(0)
 +              v.AddArg(x)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpGetLoFloat32x8(v *Value) bool {
 +      v_0 := v.Args[0]
 +      // match: (GetLoFloat32x8 x)
 +      // result: (VEXTRACTF128128 [0] x)
 +      for {
 +              x := v_0
 +              v.reset(OpAMD64VEXTRACTF128128)
 +              v.AuxInt = uint8ToAuxInt(0)
 +              v.AddArg(x)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpGetLoFloat64x4(v *Value) bool {
 +      v_0 := v.Args[0]
 +      // match: (GetLoFloat64x4 x)
 +      // result: (VEXTRACTF128128 [0] x)
 +      for {
 +              x := v_0
 +              v.reset(OpAMD64VEXTRACTF128128)
 +              v.AuxInt = uint8ToAuxInt(0)
 +              v.AddArg(x)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpGetLoFloat64x8(v *Value) bool {
 +      v_0 := v.Args[0]
 +      // match: (GetLoFloat64x8 x)
 +      // result: (VEXTRACTF64X4256 [0] x)
 +      for {
 +              x := v_0
 +              v.reset(OpAMD64VEXTRACTF64X4256)
 +              v.AuxInt = uint8ToAuxInt(0)
 +              v.AddArg(x)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpGetLoInt16x16(v *Value) bool {
 +      v_0 := v.Args[0]
 +      // match: (GetLoInt16x16 x)
 +      // result: (VEXTRACTI128128 [0] x)
 +      for {
 +              x := v_0
 +              v.reset(OpAMD64VEXTRACTI128128)
 +              v.AuxInt = uint8ToAuxInt(0)
 +              v.AddArg(x)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpGetLoInt16x32(v *Value) bool {
 +      v_0 := v.Args[0]
 +      // match: (GetLoInt16x32 x)
 +      // result: (VEXTRACTI64X4256 [0] x)
 +      for {
 +              x := v_0
 +              v.reset(OpAMD64VEXTRACTI64X4256)
 +              v.AuxInt = uint8ToAuxInt(0)
 +              v.AddArg(x)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpGetLoInt32x16(v *Value) bool {
 +      v_0 := v.Args[0]
 +      // match: (GetLoInt32x16 x)
 +      // result: (VEXTRACTI64X4256 [0] x)
 +      for {
 +              x := v_0
 +              v.reset(OpAMD64VEXTRACTI64X4256)
 +              v.AuxInt = uint8ToAuxInt(0)
 +              v.AddArg(x)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpGetLoInt32x8(v *Value) bool {
 +      v_0 := v.Args[0]
 +      // match: (GetLoInt32x8 x)
 +      // result: (VEXTRACTI128128 [0] x)
 +      for {
 +              x := v_0
 +              v.reset(OpAMD64VEXTRACTI128128)
 +              v.AuxInt = uint8ToAuxInt(0)
 +              v.AddArg(x)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpGetLoInt64x4(v *Value) bool {
 +      v_0 := v.Args[0]
 +      // match: (GetLoInt64x4 x)
 +      // result: (VEXTRACTI128128 [0] x)
 +      for {
 +              x := v_0
 +              v.reset(OpAMD64VEXTRACTI128128)
 +              v.AuxInt = uint8ToAuxInt(0)
 +              v.AddArg(x)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpGetLoInt64x8(v *Value) bool {
 +      v_0 := v.Args[0]
 +      // match: (GetLoInt64x8 x)
 +      // result: (VEXTRACTI64X4256 [0] x)
 +      for {
 +              x := v_0
 +              v.reset(OpAMD64VEXTRACTI64X4256)
 +              v.AuxInt = uint8ToAuxInt(0)
 +              v.AddArg(x)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpGetLoInt8x32(v *Value) bool {
 +      v_0 := v.Args[0]
 +      // match: (GetLoInt8x32 x)
 +      // result: (VEXTRACTI128128 [0] x)
 +      for {
 +              x := v_0
 +              v.reset(OpAMD64VEXTRACTI128128)
 +              v.AuxInt = uint8ToAuxInt(0)
 +              v.AddArg(x)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpGetLoInt8x64(v *Value) bool {
 +      v_0 := v.Args[0]
 +      // match: (GetLoInt8x64 x)
 +      // result: (VEXTRACTI64X4256 [0] x)
 +      for {
 +              x := v_0
 +              v.reset(OpAMD64VEXTRACTI64X4256)
 +              v.AuxInt = uint8ToAuxInt(0)
 +              v.AddArg(x)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpGetLoUint16x16(v *Value) bool {
 +      v_0 := v.Args[0]
 +      // match: (GetLoUint16x16 x)
 +      // result: (VEXTRACTI128128 [0] x)
 +      for {
 +              x := v_0
 +              v.reset(OpAMD64VEXTRACTI128128)
 +              v.AuxInt = uint8ToAuxInt(0)
 +              v.AddArg(x)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpGetLoUint16x32(v *Value) bool {
 +      v_0 := v.Args[0]
 +      // match: (GetLoUint16x32 x)
 +      // result: (VEXTRACTI64X4256 [0] x)
 +      for {
 +              x := v_0
 +              v.reset(OpAMD64VEXTRACTI64X4256)
 +              v.AuxInt = uint8ToAuxInt(0)
 +              v.AddArg(x)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpGetLoUint32x16(v *Value) bool {
 +      v_0 := v.Args[0]
 +      // match: (GetLoUint32x16 x)
 +      // result: (VEXTRACTI64X4256 [0] x)
 +      for {
 +              x := v_0
 +              v.reset(OpAMD64VEXTRACTI64X4256)
 +              v.AuxInt = uint8ToAuxInt(0)
 +              v.AddArg(x)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpGetLoUint32x8(v *Value) bool {
 +      v_0 := v.Args[0]
 +      // match: (GetLoUint32x8 x)
 +      // result: (VEXTRACTI128128 [0] x)
 +      for {
 +              x := v_0
 +              v.reset(OpAMD64VEXTRACTI128128)
 +              v.AuxInt = uint8ToAuxInt(0)
 +              v.AddArg(x)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpGetLoUint64x4(v *Value) bool {
 +      v_0 := v.Args[0]
 +      // match: (GetLoUint64x4 x)
 +      // result: (VEXTRACTI128128 [0] x)
 +      for {
 +              x := v_0
 +              v.reset(OpAMD64VEXTRACTI128128)
 +              v.AuxInt = uint8ToAuxInt(0)
 +              v.AddArg(x)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpGetLoUint64x8(v *Value) bool {
 +      v_0 := v.Args[0]
 +      // match: (GetLoUint64x8 x)
 +      // result: (VEXTRACTI64X4256 [0] x)
 +      for {
 +              x := v_0
 +              v.reset(OpAMD64VEXTRACTI64X4256)
 +              v.AuxInt = uint8ToAuxInt(0)
 +              v.AddArg(x)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpGetLoUint8x32(v *Value) bool {
 +      v_0 := v.Args[0]
 +      // match: (GetLoUint8x32 x)
 +      // result: (VEXTRACTI128128 [0] x)
 +      for {
 +              x := v_0
 +              v.reset(OpAMD64VEXTRACTI128128)
 +              v.AuxInt = uint8ToAuxInt(0)
 +              v.AddArg(x)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpGetLoUint8x64(v *Value) bool {
 +      v_0 := v.Args[0]
 +      // match: (GetLoUint8x64 x)
 +      // result: (VEXTRACTI64X4256 [0] x)
 +      for {
 +              x := v_0
 +              v.reset(OpAMD64VEXTRACTI64X4256)
 +              v.AuxInt = uint8ToAuxInt(0)
 +              v.AddArg(x)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpGreaterEqualFloat32x16(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      typ := &b.Func.Config.Types
 +      // match: (GreaterEqualFloat32x16 x y)
 +      // result: (VPMOVMToVec32x16 (VCMPPS512 [13] x y))
 +      for {
 +              x := v_0
 +              y := v_1
 +              v.reset(OpAMD64VPMOVMToVec32x16)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VCMPPS512, typ.Mask)
 +              v0.AuxInt = uint8ToAuxInt(13)
 +              v0.AddArg2(x, y)
 +              v.AddArg(v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpGreaterEqualFloat32x4(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      // match: (GreaterEqualFloat32x4 x y)
 +      // result: (VCMPPS128 [13] x y)
 +      for {
 +              x := v_0
 +              y := v_1
 +              v.reset(OpAMD64VCMPPS128)
 +              v.AuxInt = uint8ToAuxInt(13)
 +              v.AddArg2(x, y)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpGreaterEqualFloat32x8(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      // match: (GreaterEqualFloat32x8 x y)
 +      // result: (VCMPPS256 [13] x y)
 +      for {
 +              x := v_0
 +              y := v_1
 +              v.reset(OpAMD64VCMPPS256)
 +              v.AuxInt = uint8ToAuxInt(13)
 +              v.AddArg2(x, y)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpGreaterEqualFloat64x2(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      // match: (GreaterEqualFloat64x2 x y)
 +      // result: (VCMPPD128 [13] x y)
 +      for {
 +              x := v_0
 +              y := v_1
 +              v.reset(OpAMD64VCMPPD128)
 +              v.AuxInt = uint8ToAuxInt(13)
 +              v.AddArg2(x, y)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpGreaterEqualFloat64x4(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      // match: (GreaterEqualFloat64x4 x y)
 +      // result: (VCMPPD256 [13] x y)
 +      for {
 +              x := v_0
 +              y := v_1
 +              v.reset(OpAMD64VCMPPD256)
 +              v.AuxInt = uint8ToAuxInt(13)
 +              v.AddArg2(x, y)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpGreaterEqualFloat64x8(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      typ := &b.Func.Config.Types
 +      // match: (GreaterEqualFloat64x8 x y)
 +      // result: (VPMOVMToVec64x8 (VCMPPD512 [13] x y))
 +      for {
 +              x := v_0
 +              y := v_1
 +              v.reset(OpAMD64VPMOVMToVec64x8)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VCMPPD512, typ.Mask)
 +              v0.AuxInt = uint8ToAuxInt(13)
 +              v0.AddArg2(x, y)
 +              v.AddArg(v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpGreaterEqualInt16x32(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      typ := &b.Func.Config.Types
 +      // match: (GreaterEqualInt16x32 x y)
 +      // result: (VPMOVMToVec16x32 (VPCMPW512 [13] x y))
 +      for {
 +              x := v_0
 +              y := v_1
 +              v.reset(OpAMD64VPMOVMToVec16x32)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPCMPW512, typ.Mask)
 +              v0.AuxInt = uint8ToAuxInt(13)
 +              v0.AddArg2(x, y)
 +              v.AddArg(v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpGreaterEqualInt32x16(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      typ := &b.Func.Config.Types
 +      // match: (GreaterEqualInt32x16 x y)
 +      // result: (VPMOVMToVec32x16 (VPCMPD512 [13] x y))
 +      for {
 +              x := v_0
 +              y := v_1
 +              v.reset(OpAMD64VPMOVMToVec32x16)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPCMPD512, typ.Mask)
 +              v0.AuxInt = uint8ToAuxInt(13)
 +              v0.AddArg2(x, y)
 +              v.AddArg(v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpGreaterEqualInt64x8(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      typ := &b.Func.Config.Types
 +      // match: (GreaterEqualInt64x8 x y)
 +      // result: (VPMOVMToVec64x8 (VPCMPQ512 [13] x y))
 +      for {
 +              x := v_0
 +              y := v_1
 +              v.reset(OpAMD64VPMOVMToVec64x8)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPCMPQ512, typ.Mask)
 +              v0.AuxInt = uint8ToAuxInt(13)
 +              v0.AddArg2(x, y)
 +              v.AddArg(v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpGreaterEqualInt8x64(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      typ := &b.Func.Config.Types
 +      // match: (GreaterEqualInt8x64 x y)
 +      // result: (VPMOVMToVec8x64 (VPCMPB512 [13] x y))
 +      for {
 +              x := v_0
 +              y := v_1
 +              v.reset(OpAMD64VPMOVMToVec8x64)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPCMPB512, typ.Mask)
 +              v0.AuxInt = uint8ToAuxInt(13)
 +              v0.AddArg2(x, y)
 +              v.AddArg(v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpGreaterEqualMaskedFloat32x16(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      typ := &b.Func.Config.Types
 +      // match: (GreaterEqualMaskedFloat32x16 x y mask)
 +      // result: (VPMOVMToVec32x16 (VCMPPSMasked512 [13] x y (VPMOVVec32x16ToM <types.TypeMask> mask)))
 +      for {
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VPMOVMToVec32x16)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VCMPPSMasked512, typ.Mask)
 +              v0.AuxInt = uint8ToAuxInt(13)
 +              v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x16ToM, types.TypeMask)
 +              v1.AddArg(mask)
 +              v0.AddArg3(x, y, v1)
 +              v.AddArg(v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpGreaterEqualMaskedFloat32x4(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      typ := &b.Func.Config.Types
 +      // match: (GreaterEqualMaskedFloat32x4 x y mask)
 +      // result: (VPMOVMToVec32x4 (VCMPPSMasked128 [13] x y (VPMOVVec32x4ToM <types.TypeMask> mask)))
 +      for {
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VPMOVMToVec32x4)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VCMPPSMasked128, typ.Mask)
 +              v0.AuxInt = uint8ToAuxInt(13)
 +              v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x4ToM, types.TypeMask)
 +              v1.AddArg(mask)
 +              v0.AddArg3(x, y, v1)
 +              v.AddArg(v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpGreaterEqualMaskedFloat32x8(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      typ := &b.Func.Config.Types
 +      // match: (GreaterEqualMaskedFloat32x8 x y mask)
 +      // result: (VPMOVMToVec32x8 (VCMPPSMasked256 [13] x y (VPMOVVec32x8ToM <types.TypeMask> mask)))
 +      for {
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VPMOVMToVec32x8)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VCMPPSMasked256, typ.Mask)
 +              v0.AuxInt = uint8ToAuxInt(13)
 +              v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x8ToM, types.TypeMask)
 +              v1.AddArg(mask)
 +              v0.AddArg3(x, y, v1)
 +              v.AddArg(v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpGreaterEqualMaskedFloat64x2(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      typ := &b.Func.Config.Types
 +      // match: (GreaterEqualMaskedFloat64x2 x y mask)
 +      // result: (VPMOVMToVec64x2 (VCMPPDMasked128 [13] x y (VPMOVVec64x2ToM <types.TypeMask> mask)))
 +      for {
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VPMOVMToVec64x2)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VCMPPDMasked128, typ.Mask)
 +              v0.AuxInt = uint8ToAuxInt(13)
 +              v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x2ToM, types.TypeMask)
 +              v1.AddArg(mask)
 +              v0.AddArg3(x, y, v1)
 +              v.AddArg(v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpGreaterEqualMaskedFloat64x4(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      typ := &b.Func.Config.Types
 +      // match: (GreaterEqualMaskedFloat64x4 x y mask)
 +      // result: (VPMOVMToVec64x4 (VCMPPDMasked256 [13] x y (VPMOVVec64x4ToM <types.TypeMask> mask)))
 +      for {
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VPMOVMToVec64x4)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VCMPPDMasked256, typ.Mask)
 +              v0.AuxInt = uint8ToAuxInt(13)
 +              v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x4ToM, types.TypeMask)
 +              v1.AddArg(mask)
 +              v0.AddArg3(x, y, v1)
 +              v.AddArg(v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpGreaterEqualMaskedFloat64x8(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      typ := &b.Func.Config.Types
 +      // match: (GreaterEqualMaskedFloat64x8 x y mask)
 +      // result: (VPMOVMToVec64x8 (VCMPPDMasked512 [13] x y (VPMOVVec64x8ToM <types.TypeMask> mask)))
 +      for {
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VPMOVMToVec64x8)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VCMPPDMasked512, typ.Mask)
 +              v0.AuxInt = uint8ToAuxInt(13)
 +              v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x8ToM, types.TypeMask)
 +              v1.AddArg(mask)
 +              v0.AddArg3(x, y, v1)
 +              v.AddArg(v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpGreaterEqualMaskedInt16x16(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      typ := &b.Func.Config.Types
 +      // match: (GreaterEqualMaskedInt16x16 x y mask)
 +      // result: (VPMOVMToVec16x16 (VPCMPWMasked256 [13] x y (VPMOVVec16x16ToM <types.TypeMask> mask)))
 +      for {
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VPMOVMToVec16x16)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPCMPWMasked256, typ.Mask)
 +              v0.AuxInt = uint8ToAuxInt(13)
 +              v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x16ToM, types.TypeMask)
 +              v1.AddArg(mask)
 +              v0.AddArg3(x, y, v1)
 +              v.AddArg(v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpGreaterEqualMaskedInt16x32(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      typ := &b.Func.Config.Types
 +      // match: (GreaterEqualMaskedInt16x32 x y mask)
 +      // result: (VPMOVMToVec16x32 (VPCMPWMasked512 [13] x y (VPMOVVec16x32ToM <types.TypeMask> mask)))
 +      for {
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VPMOVMToVec16x32)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPCMPWMasked512, typ.Mask)
 +              v0.AuxInt = uint8ToAuxInt(13)
 +              v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x32ToM, types.TypeMask)
 +              v1.AddArg(mask)
 +              v0.AddArg3(x, y, v1)
 +              v.AddArg(v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpGreaterEqualMaskedInt16x8(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      typ := &b.Func.Config.Types
 +      // match: (GreaterEqualMaskedInt16x8 x y mask)
 +      // result: (VPMOVMToVec16x8 (VPCMPWMasked128 [13] x y (VPMOVVec16x8ToM <types.TypeMask> mask)))
 +      for {
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VPMOVMToVec16x8)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPCMPWMasked128, typ.Mask)
 +              v0.AuxInt = uint8ToAuxInt(13)
 +              v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x8ToM, types.TypeMask)
 +              v1.AddArg(mask)
 +              v0.AddArg3(x, y, v1)
 +              v.AddArg(v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpGreaterEqualMaskedInt32x16(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      typ := &b.Func.Config.Types
 +      // match: (GreaterEqualMaskedInt32x16 x y mask)
 +      // result: (VPMOVMToVec32x16 (VPCMPDMasked512 [13] x y (VPMOVVec32x16ToM <types.TypeMask> mask)))
 +      for {
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VPMOVMToVec32x16)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPCMPDMasked512, typ.Mask)
 +              v0.AuxInt = uint8ToAuxInt(13)
 +              v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x16ToM, types.TypeMask)
 +              v1.AddArg(mask)
 +              v0.AddArg3(x, y, v1)
 +              v.AddArg(v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpGreaterEqualMaskedInt32x4(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      typ := &b.Func.Config.Types
 +      // match: (GreaterEqualMaskedInt32x4 x y mask)
 +      // result: (VPMOVMToVec32x4 (VPCMPDMasked128 [13] x y (VPMOVVec32x4ToM <types.TypeMask> mask)))
 +      for {
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VPMOVMToVec32x4)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPCMPDMasked128, typ.Mask)
 +              v0.AuxInt = uint8ToAuxInt(13)
 +              v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x4ToM, types.TypeMask)
 +              v1.AddArg(mask)
 +              v0.AddArg3(x, y, v1)
 +              v.AddArg(v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpGreaterEqualMaskedInt32x8(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      typ := &b.Func.Config.Types
 +      // match: (GreaterEqualMaskedInt32x8 x y mask)
 +      // result: (VPMOVMToVec32x8 (VPCMPDMasked256 [13] x y (VPMOVVec32x8ToM <types.TypeMask> mask)))
 +      for {
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VPMOVMToVec32x8)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPCMPDMasked256, typ.Mask)
 +              v0.AuxInt = uint8ToAuxInt(13)
 +              v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x8ToM, types.TypeMask)
 +              v1.AddArg(mask)
 +              v0.AddArg3(x, y, v1)
 +              v.AddArg(v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpGreaterEqualMaskedInt64x2(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      typ := &b.Func.Config.Types
 +      // match: (GreaterEqualMaskedInt64x2 x y mask)
 +      // result: (VPMOVMToVec64x2 (VPCMPQMasked128 [13] x y (VPMOVVec64x2ToM <types.TypeMask> mask)))
 +      for {
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VPMOVMToVec64x2)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPCMPQMasked128, typ.Mask)
 +              v0.AuxInt = uint8ToAuxInt(13)
 +              v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x2ToM, types.TypeMask)
 +              v1.AddArg(mask)
 +              v0.AddArg3(x, y, v1)
 +              v.AddArg(v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpGreaterEqualMaskedInt64x4(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      typ := &b.Func.Config.Types
 +      // match: (GreaterEqualMaskedInt64x4 x y mask)
 +      // result: (VPMOVMToVec64x4 (VPCMPQMasked256 [13] x y (VPMOVVec64x4ToM <types.TypeMask> mask)))
 +      for {
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VPMOVMToVec64x4)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPCMPQMasked256, typ.Mask)
 +              v0.AuxInt = uint8ToAuxInt(13)
 +              v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x4ToM, types.TypeMask)
 +              v1.AddArg(mask)
 +              v0.AddArg3(x, y, v1)
 +              v.AddArg(v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpGreaterEqualMaskedInt64x8(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      typ := &b.Func.Config.Types
 +      // match: (GreaterEqualMaskedInt64x8 x y mask)
 +      // result: (VPMOVMToVec64x8 (VPCMPQMasked512 [13] x y (VPMOVVec64x8ToM <types.TypeMask> mask)))
 +      for {
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VPMOVMToVec64x8)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPCMPQMasked512, typ.Mask)
 +              v0.AuxInt = uint8ToAuxInt(13)
 +              v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x8ToM, types.TypeMask)
 +              v1.AddArg(mask)
 +              v0.AddArg3(x, y, v1)
 +              v.AddArg(v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpGreaterEqualMaskedInt8x16(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      typ := &b.Func.Config.Types
 +      // match: (GreaterEqualMaskedInt8x16 x y mask)
 +      // result: (VPMOVMToVec8x16 (VPCMPBMasked128 [13] x y (VPMOVVec8x16ToM <types.TypeMask> mask)))
 +      for {
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VPMOVMToVec8x16)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPCMPBMasked128, typ.Mask)
 +              v0.AuxInt = uint8ToAuxInt(13)
 +              v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec8x16ToM, types.TypeMask)
 +              v1.AddArg(mask)
 +              v0.AddArg3(x, y, v1)
 +              v.AddArg(v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpGreaterEqualMaskedInt8x32(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      typ := &b.Func.Config.Types
 +      // match: (GreaterEqualMaskedInt8x32 x y mask)
 +      // result: (VPMOVMToVec8x32 (VPCMPBMasked256 [13] x y (VPMOVVec8x32ToM <types.TypeMask> mask)))
 +      for {
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VPMOVMToVec8x32)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPCMPBMasked256, typ.Mask)
 +              v0.AuxInt = uint8ToAuxInt(13)
 +              v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec8x32ToM, types.TypeMask)
 +              v1.AddArg(mask)
 +              v0.AddArg3(x, y, v1)
 +              v.AddArg(v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpGreaterEqualMaskedInt8x64(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      typ := &b.Func.Config.Types
 +      // match: (GreaterEqualMaskedInt8x64 x y mask)
 +      // result: (VPMOVMToVec8x64 (VPCMPBMasked512 [13] x y (VPMOVVec8x64ToM <types.TypeMask> mask)))
 +      for {
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VPMOVMToVec8x64)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPCMPBMasked512, typ.Mask)
 +              v0.AuxInt = uint8ToAuxInt(13)
 +              v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec8x64ToM, types.TypeMask)
 +              v1.AddArg(mask)
 +              v0.AddArg3(x, y, v1)
 +              v.AddArg(v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpGreaterEqualMaskedUint16x16(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      typ := &b.Func.Config.Types
 +      // match: (GreaterEqualMaskedUint16x16 x y mask)
 +      // result: (VPMOVMToVec16x16 (VPCMPUWMasked256 [13] x y (VPMOVVec16x16ToM <types.TypeMask> mask)))
 +      for {
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VPMOVMToVec16x16)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPCMPUWMasked256, typ.Mask)
 +              v0.AuxInt = uint8ToAuxInt(13)
 +              v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x16ToM, types.TypeMask)
 +              v1.AddArg(mask)
 +              v0.AddArg3(x, y, v1)
 +              v.AddArg(v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpGreaterEqualMaskedUint16x32(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      typ := &b.Func.Config.Types
 +      // match: (GreaterEqualMaskedUint16x32 x y mask)
 +      // result: (VPMOVMToVec16x32 (VPCMPUWMasked512 [13] x y (VPMOVVec16x32ToM <types.TypeMask> mask)))
 +      for {
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VPMOVMToVec16x32)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPCMPUWMasked512, typ.Mask)
 +              v0.AuxInt = uint8ToAuxInt(13)
 +              v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x32ToM, types.TypeMask)
 +              v1.AddArg(mask)
 +              v0.AddArg3(x, y, v1)
 +              v.AddArg(v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpGreaterEqualMaskedUint16x8(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      typ := &b.Func.Config.Types
 +      // match: (GreaterEqualMaskedUint16x8 x y mask)
 +      // result: (VPMOVMToVec16x8 (VPCMPUWMasked128 [13] x y (VPMOVVec16x8ToM <types.TypeMask> mask)))
 +      for {
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VPMOVMToVec16x8)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPCMPUWMasked128, typ.Mask)
 +              v0.AuxInt = uint8ToAuxInt(13)
 +              v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x8ToM, types.TypeMask)
 +              v1.AddArg(mask)
 +              v0.AddArg3(x, y, v1)
 +              v.AddArg(v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpGreaterEqualMaskedUint32x16(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      typ := &b.Func.Config.Types
 +      // match: (GreaterEqualMaskedUint32x16 x y mask)
 +      // result: (VPMOVMToVec32x16 (VPCMPUDMasked512 [13] x y (VPMOVVec32x16ToM <types.TypeMask> mask)))
 +      for {
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VPMOVMToVec32x16)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPCMPUDMasked512, typ.Mask)
 +              v0.AuxInt = uint8ToAuxInt(13)
 +              v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x16ToM, types.TypeMask)
 +              v1.AddArg(mask)
 +              v0.AddArg3(x, y, v1)
 +              v.AddArg(v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpGreaterEqualMaskedUint32x4(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      typ := &b.Func.Config.Types
 +      // match: (GreaterEqualMaskedUint32x4 x y mask)
 +      // result: (VPMOVMToVec32x4 (VPCMPUDMasked128 [13] x y (VPMOVVec32x4ToM <types.TypeMask> mask)))
 +      for {
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VPMOVMToVec32x4)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPCMPUDMasked128, typ.Mask)
 +              v0.AuxInt = uint8ToAuxInt(13)
 +              v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x4ToM, types.TypeMask)
 +              v1.AddArg(mask)
 +              v0.AddArg3(x, y, v1)
 +              v.AddArg(v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpGreaterEqualMaskedUint32x8(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      typ := &b.Func.Config.Types
 +      // match: (GreaterEqualMaskedUint32x8 x y mask)
 +      // result: (VPMOVMToVec32x8 (VPCMPUDMasked256 [13] x y (VPMOVVec32x8ToM <types.TypeMask> mask)))
 +      for {
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VPMOVMToVec32x8)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPCMPUDMasked256, typ.Mask)
 +              v0.AuxInt = uint8ToAuxInt(13)
 +              v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x8ToM, types.TypeMask)
 +              v1.AddArg(mask)
 +              v0.AddArg3(x, y, v1)
 +              v.AddArg(v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpGreaterEqualMaskedUint64x2(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      typ := &b.Func.Config.Types
 +      // match: (GreaterEqualMaskedUint64x2 x y mask)
 +      // result: (VPMOVMToVec64x2 (VPCMPUQMasked128 [13] x y (VPMOVVec64x2ToM <types.TypeMask> mask)))
 +      for {
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VPMOVMToVec64x2)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPCMPUQMasked128, typ.Mask)
 +              v0.AuxInt = uint8ToAuxInt(13)
 +              v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x2ToM, types.TypeMask)
 +              v1.AddArg(mask)
 +              v0.AddArg3(x, y, v1)
 +              v.AddArg(v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpGreaterEqualMaskedUint64x4(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      typ := &b.Func.Config.Types
 +      // match: (GreaterEqualMaskedUint64x4 x y mask)
 +      // result: (VPMOVMToVec64x4 (VPCMPUQMasked256 [13] x y (VPMOVVec64x4ToM <types.TypeMask> mask)))
 +      for {
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VPMOVMToVec64x4)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPCMPUQMasked256, typ.Mask)
 +              v0.AuxInt = uint8ToAuxInt(13)
 +              v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x4ToM, types.TypeMask)
 +              v1.AddArg(mask)
 +              v0.AddArg3(x, y, v1)
 +              v.AddArg(v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpGreaterEqualMaskedUint64x8(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      typ := &b.Func.Config.Types
 +      // match: (GreaterEqualMaskedUint64x8 x y mask)
 +      // result: (VPMOVMToVec64x8 (VPCMPUQMasked512 [13] x y (VPMOVVec64x8ToM <types.TypeMask> mask)))
 +      for {
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VPMOVMToVec64x8)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPCMPUQMasked512, typ.Mask)
 +              v0.AuxInt = uint8ToAuxInt(13)
 +              v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x8ToM, types.TypeMask)
 +              v1.AddArg(mask)
 +              v0.AddArg3(x, y, v1)
 +              v.AddArg(v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpGreaterEqualMaskedUint8x16(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      typ := &b.Func.Config.Types
 +      // match: (GreaterEqualMaskedUint8x16 x y mask)
 +      // result: (VPMOVMToVec8x16 (VPCMPUBMasked128 [13] x y (VPMOVVec8x16ToM <types.TypeMask> mask)))
 +      for {
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VPMOVMToVec8x16)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPCMPUBMasked128, typ.Mask)
 +              v0.AuxInt = uint8ToAuxInt(13)
 +              v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec8x16ToM, types.TypeMask)
 +              v1.AddArg(mask)
 +              v0.AddArg3(x, y, v1)
 +              v.AddArg(v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpGreaterEqualMaskedUint8x32(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      typ := &b.Func.Config.Types
 +      // match: (GreaterEqualMaskedUint8x32 x y mask)
 +      // result: (VPMOVMToVec8x32 (VPCMPUBMasked256 [13] x y (VPMOVVec8x32ToM <types.TypeMask> mask)))
 +      for {
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VPMOVMToVec8x32)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPCMPUBMasked256, typ.Mask)
 +              v0.AuxInt = uint8ToAuxInt(13)
 +              v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec8x32ToM, types.TypeMask)
 +              v1.AddArg(mask)
 +              v0.AddArg3(x, y, v1)
 +              v.AddArg(v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpGreaterEqualMaskedUint8x64(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      typ := &b.Func.Config.Types
 +      // match: (GreaterEqualMaskedUint8x64 x y mask)
 +      // result: (VPMOVMToVec8x64 (VPCMPUBMasked512 [13] x y (VPMOVVec8x64ToM <types.TypeMask> mask)))
 +      for {
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VPMOVMToVec8x64)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPCMPUBMasked512, typ.Mask)
 +              v0.AuxInt = uint8ToAuxInt(13)
 +              v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec8x64ToM, types.TypeMask)
 +              v1.AddArg(mask)
 +              v0.AddArg3(x, y, v1)
 +              v.AddArg(v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpGreaterEqualUint16x32(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      typ := &b.Func.Config.Types
 +      // match: (GreaterEqualUint16x32 x y)
 +      // result: (VPMOVMToVec16x32 (VPCMPUW512 [13] x y))
 +      for {
 +              x := v_0
 +              y := v_1
 +              v.reset(OpAMD64VPMOVMToVec16x32)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPCMPUW512, typ.Mask)
 +              v0.AuxInt = uint8ToAuxInt(13)
 +              v0.AddArg2(x, y)
 +              v.AddArg(v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpGreaterEqualUint32x16(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      typ := &b.Func.Config.Types
 +      // match: (GreaterEqualUint32x16 x y)
 +      // result: (VPMOVMToVec32x16 (VPCMPUD512 [13] x y))
 +      for {
 +              x := v_0
 +              y := v_1
 +              v.reset(OpAMD64VPMOVMToVec32x16)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPCMPUD512, typ.Mask)
 +              v0.AuxInt = uint8ToAuxInt(13)
 +              v0.AddArg2(x, y)
 +              v.AddArg(v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpGreaterEqualUint64x8(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      typ := &b.Func.Config.Types
 +      // match: (GreaterEqualUint64x8 x y)
 +      // result: (VPMOVMToVec64x8 (VPCMPUQ512 [13] x y))
 +      for {
 +              x := v_0
 +              y := v_1
 +              v.reset(OpAMD64VPMOVMToVec64x8)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPCMPUQ512, typ.Mask)
 +              v0.AuxInt = uint8ToAuxInt(13)
 +              v0.AddArg2(x, y)
 +              v.AddArg(v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpGreaterEqualUint8x64(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      typ := &b.Func.Config.Types
 +      // match: (GreaterEqualUint8x64 x y)
 +      // result: (VPMOVMToVec8x64 (VPCMPUB512 [13] x y))
 +      for {
 +              x := v_0
 +              y := v_1
 +              v.reset(OpAMD64VPMOVMToVec8x64)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPCMPUB512, typ.Mask)
 +              v0.AuxInt = uint8ToAuxInt(13)
 +              v0.AddArg2(x, y)
 +              v.AddArg(v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpGreaterFloat32x16(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      typ := &b.Func.Config.Types
 +      // match: (GreaterFloat32x16 x y)
 +      // result: (VPMOVMToVec32x16 (VCMPPS512 [14] x y))
 +      for {
 +              x := v_0
 +              y := v_1
 +              v.reset(OpAMD64VPMOVMToVec32x16)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VCMPPS512, typ.Mask)
 +              v0.AuxInt = uint8ToAuxInt(14)
 +              v0.AddArg2(x, y)
 +              v.AddArg(v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpGreaterFloat32x4(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      // match: (GreaterFloat32x4 x y)
 +      // result: (VCMPPS128 [14] x y)
 +      for {
 +              x := v_0
 +              y := v_1
 +              v.reset(OpAMD64VCMPPS128)
 +              v.AuxInt = uint8ToAuxInt(14)
 +              v.AddArg2(x, y)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpGreaterFloat32x8(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      // match: (GreaterFloat32x8 x y)
 +      // result: (VCMPPS256 [14] x y)
 +      for {
 +              x := v_0
 +              y := v_1
 +              v.reset(OpAMD64VCMPPS256)
 +              v.AuxInt = uint8ToAuxInt(14)
 +              v.AddArg2(x, y)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpGreaterFloat64x2(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      // match: (GreaterFloat64x2 x y)
 +      // result: (VCMPPD128 [14] x y)
 +      for {
 +              x := v_0
 +              y := v_1
 +              v.reset(OpAMD64VCMPPD128)
 +              v.AuxInt = uint8ToAuxInt(14)
 +              v.AddArg2(x, y)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpGreaterFloat64x4(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      // match: (GreaterFloat64x4 x y)
 +      // result: (VCMPPD256 [14] x y)
 +      for {
 +              x := v_0
 +              y := v_1
 +              v.reset(OpAMD64VCMPPD256)
 +              v.AuxInt = uint8ToAuxInt(14)
 +              v.AddArg2(x, y)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpGreaterFloat64x8(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      typ := &b.Func.Config.Types
 +      // match: (GreaterFloat64x8 x y)
 +      // result: (VPMOVMToVec64x8 (VCMPPD512 [14] x y))
 +      for {
 +              x := v_0
 +              y := v_1
 +              v.reset(OpAMD64VPMOVMToVec64x8)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VCMPPD512, typ.Mask)
 +              v0.AuxInt = uint8ToAuxInt(14)
 +              v0.AddArg2(x, y)
 +              v.AddArg(v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpGreaterInt16x32(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      typ := &b.Func.Config.Types
 +      // match: (GreaterInt16x32 x y)
 +      // result: (VPMOVMToVec16x32 (VPCMPGTW512 x y))
 +      for {
 +              x := v_0
 +              y := v_1
 +              v.reset(OpAMD64VPMOVMToVec16x32)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPCMPGTW512, typ.Mask)
 +              v0.AddArg2(x, y)
 +              v.AddArg(v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpGreaterInt32x16(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      typ := &b.Func.Config.Types
 +      // match: (GreaterInt32x16 x y)
 +      // result: (VPMOVMToVec32x16 (VPCMPGTD512 x y))
 +      for {
 +              x := v_0
 +              y := v_1
 +              v.reset(OpAMD64VPMOVMToVec32x16)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPCMPGTD512, typ.Mask)
 +              v0.AddArg2(x, y)
 +              v.AddArg(v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpGreaterInt64x8(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      typ := &b.Func.Config.Types
 +      // match: (GreaterInt64x8 x y)
 +      // result: (VPMOVMToVec64x8 (VPCMPGTQ512 x y))
 +      for {
 +              x := v_0
 +              y := v_1
 +              v.reset(OpAMD64VPMOVMToVec64x8)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPCMPGTQ512, typ.Mask)
 +              v0.AddArg2(x, y)
 +              v.AddArg(v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpGreaterInt8x64(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      typ := &b.Func.Config.Types
 +      // match: (GreaterInt8x64 x y)
 +      // result: (VPMOVMToVec8x64 (VPCMPGTB512 x y))
 +      for {
 +              x := v_0
 +              y := v_1
 +              v.reset(OpAMD64VPMOVMToVec8x64)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPCMPGTB512, typ.Mask)
 +              v0.AddArg2(x, y)
 +              v.AddArg(v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpGreaterMaskedFloat32x16(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      typ := &b.Func.Config.Types
 +      // match: (GreaterMaskedFloat32x16 x y mask)
 +      // result: (VPMOVMToVec32x16 (VCMPPSMasked512 [14] x y (VPMOVVec32x16ToM <types.TypeMask> mask)))
 +      for {
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VPMOVMToVec32x16)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VCMPPSMasked512, typ.Mask)
 +              v0.AuxInt = uint8ToAuxInt(14)
 +              v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x16ToM, types.TypeMask)
 +              v1.AddArg(mask)
 +              v0.AddArg3(x, y, v1)
 +              v.AddArg(v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpGreaterMaskedFloat32x4(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      typ := &b.Func.Config.Types
 +      // match: (GreaterMaskedFloat32x4 x y mask)
 +      // result: (VPMOVMToVec32x4 (VCMPPSMasked128 [14] x y (VPMOVVec32x4ToM <types.TypeMask> mask)))
 +      for {
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VPMOVMToVec32x4)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VCMPPSMasked128, typ.Mask)
 +              v0.AuxInt = uint8ToAuxInt(14)
 +              v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x4ToM, types.TypeMask)
 +              v1.AddArg(mask)
 +              v0.AddArg3(x, y, v1)
 +              v.AddArg(v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpGreaterMaskedFloat32x8(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      typ := &b.Func.Config.Types
 +      // match: (GreaterMaskedFloat32x8 x y mask)
 +      // result: (VPMOVMToVec32x8 (VCMPPSMasked256 [14] x y (VPMOVVec32x8ToM <types.TypeMask> mask)))
 +      for {
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VPMOVMToVec32x8)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VCMPPSMasked256, typ.Mask)
 +              v0.AuxInt = uint8ToAuxInt(14)
 +              v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x8ToM, types.TypeMask)
 +              v1.AddArg(mask)
 +              v0.AddArg3(x, y, v1)
 +              v.AddArg(v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpGreaterMaskedFloat64x2(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      typ := &b.Func.Config.Types
 +      // match: (GreaterMaskedFloat64x2 x y mask)
 +      // result: (VPMOVMToVec64x2 (VCMPPDMasked128 [14] x y (VPMOVVec64x2ToM <types.TypeMask> mask)))
 +      for {
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VPMOVMToVec64x2)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VCMPPDMasked128, typ.Mask)
 +              v0.AuxInt = uint8ToAuxInt(14)
 +              v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x2ToM, types.TypeMask)
 +              v1.AddArg(mask)
 +              v0.AddArg3(x, y, v1)
 +              v.AddArg(v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpGreaterMaskedFloat64x4(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      typ := &b.Func.Config.Types
 +      // match: (GreaterMaskedFloat64x4 x y mask)
 +      // result: (VPMOVMToVec64x4 (VCMPPDMasked256 [14] x y (VPMOVVec64x4ToM <types.TypeMask> mask)))
 +      for {
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VPMOVMToVec64x4)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VCMPPDMasked256, typ.Mask)
 +              v0.AuxInt = uint8ToAuxInt(14)
 +              v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x4ToM, types.TypeMask)
 +              v1.AddArg(mask)
 +              v0.AddArg3(x, y, v1)
 +              v.AddArg(v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpGreaterMaskedFloat64x8(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      typ := &b.Func.Config.Types
 +      // match: (GreaterMaskedFloat64x8 x y mask)
 +      // result: (VPMOVMToVec64x8 (VCMPPDMasked512 [14] x y (VPMOVVec64x8ToM <types.TypeMask> mask)))
 +      for {
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VPMOVMToVec64x8)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VCMPPDMasked512, typ.Mask)
 +              v0.AuxInt = uint8ToAuxInt(14)
 +              v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x8ToM, types.TypeMask)
 +              v1.AddArg(mask)
 +              v0.AddArg3(x, y, v1)
 +              v.AddArg(v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpGreaterMaskedInt16x16(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      typ := &b.Func.Config.Types
 +      // match: (GreaterMaskedInt16x16 x y mask)
 +      // result: (VPMOVMToVec16x16 (VPCMPWMasked256 [14] x y (VPMOVVec16x16ToM <types.TypeMask> mask)))
 +      for {
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VPMOVMToVec16x16)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPCMPWMasked256, typ.Mask)
 +              v0.AuxInt = uint8ToAuxInt(14)
 +              v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x16ToM, types.TypeMask)
 +              v1.AddArg(mask)
 +              v0.AddArg3(x, y, v1)
 +              v.AddArg(v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpGreaterMaskedInt16x32(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      typ := &b.Func.Config.Types
 +      // match: (GreaterMaskedInt16x32 x y mask)
 +      // result: (VPMOVMToVec16x32 (VPCMPWMasked512 [14] x y (VPMOVVec16x32ToM <types.TypeMask> mask)))
 +      for {
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VPMOVMToVec16x32)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPCMPWMasked512, typ.Mask)
 +              v0.AuxInt = uint8ToAuxInt(14)
 +              v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x32ToM, types.TypeMask)
 +              v1.AddArg(mask)
 +              v0.AddArg3(x, y, v1)
 +              v.AddArg(v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpGreaterMaskedInt16x8(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      typ := &b.Func.Config.Types
 +      // match: (GreaterMaskedInt16x8 x y mask)
 +      // result: (VPMOVMToVec16x8 (VPCMPWMasked128 [14] x y (VPMOVVec16x8ToM <types.TypeMask> mask)))
 +      for {
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VPMOVMToVec16x8)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPCMPWMasked128, typ.Mask)
 +              v0.AuxInt = uint8ToAuxInt(14)
 +              v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x8ToM, types.TypeMask)
 +              v1.AddArg(mask)
 +              v0.AddArg3(x, y, v1)
 +              v.AddArg(v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpGreaterMaskedInt32x16(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      typ := &b.Func.Config.Types
 +      // match: (GreaterMaskedInt32x16 x y mask)
 +      // result: (VPMOVMToVec32x16 (VPCMPDMasked512 [14] x y (VPMOVVec32x16ToM <types.TypeMask> mask)))
 +      for {
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VPMOVMToVec32x16)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPCMPDMasked512, typ.Mask)
 +              v0.AuxInt = uint8ToAuxInt(14)
 +              v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x16ToM, types.TypeMask)
 +              v1.AddArg(mask)
 +              v0.AddArg3(x, y, v1)
 +              v.AddArg(v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpGreaterMaskedInt32x4(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      typ := &b.Func.Config.Types
 +      // match: (GreaterMaskedInt32x4 x y mask)
 +      // result: (VPMOVMToVec32x4 (VPCMPDMasked128 [14] x y (VPMOVVec32x4ToM <types.TypeMask> mask)))
 +      for {
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VPMOVMToVec32x4)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPCMPDMasked128, typ.Mask)
 +              v0.AuxInt = uint8ToAuxInt(14)
 +              v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x4ToM, types.TypeMask)
 +              v1.AddArg(mask)
 +              v0.AddArg3(x, y, v1)
 +              v.AddArg(v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpGreaterMaskedInt32x8(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      typ := &b.Func.Config.Types
 +      // match: (GreaterMaskedInt32x8 x y mask)
 +      // result: (VPMOVMToVec32x8 (VPCMPDMasked256 [14] x y (VPMOVVec32x8ToM <types.TypeMask> mask)))
 +      for {
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VPMOVMToVec32x8)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPCMPDMasked256, typ.Mask)
 +              v0.AuxInt = uint8ToAuxInt(14)
 +              v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x8ToM, types.TypeMask)
 +              v1.AddArg(mask)
 +              v0.AddArg3(x, y, v1)
 +              v.AddArg(v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpGreaterMaskedInt64x2(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      typ := &b.Func.Config.Types
 +      // match: (GreaterMaskedInt64x2 x y mask)
 +      // result: (VPMOVMToVec64x2 (VPCMPQMasked128 [14] x y (VPMOVVec64x2ToM <types.TypeMask> mask)))
 +      for {
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VPMOVMToVec64x2)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPCMPQMasked128, typ.Mask)
 +              v0.AuxInt = uint8ToAuxInt(14)
 +              v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x2ToM, types.TypeMask)
 +              v1.AddArg(mask)
 +              v0.AddArg3(x, y, v1)
 +              v.AddArg(v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpGreaterMaskedInt64x4(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      typ := &b.Func.Config.Types
 +      // match: (GreaterMaskedInt64x4 x y mask)
 +      // result: (VPMOVMToVec64x4 (VPCMPQMasked256 [14] x y (VPMOVVec64x4ToM <types.TypeMask> mask)))
 +      for {
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VPMOVMToVec64x4)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPCMPQMasked256, typ.Mask)
 +              v0.AuxInt = uint8ToAuxInt(14)
 +              v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x4ToM, types.TypeMask)
 +              v1.AddArg(mask)
 +              v0.AddArg3(x, y, v1)
 +              v.AddArg(v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpGreaterMaskedInt64x8(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      typ := &b.Func.Config.Types
 +      // match: (GreaterMaskedInt64x8 x y mask)
 +      // result: (VPMOVMToVec64x8 (VPCMPQMasked512 [14] x y (VPMOVVec64x8ToM <types.TypeMask> mask)))
 +      for {
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VPMOVMToVec64x8)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPCMPQMasked512, typ.Mask)
 +              v0.AuxInt = uint8ToAuxInt(14)
 +              v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x8ToM, types.TypeMask)
 +              v1.AddArg(mask)
 +              v0.AddArg3(x, y, v1)
 +              v.AddArg(v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpGreaterMaskedInt8x16(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      typ := &b.Func.Config.Types
 +      // match: (GreaterMaskedInt8x16 x y mask)
 +      // result: (VPMOVMToVec8x16 (VPCMPBMasked128 [14] x y (VPMOVVec8x16ToM <types.TypeMask> mask)))
 +      for {
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VPMOVMToVec8x16)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPCMPBMasked128, typ.Mask)
 +              v0.AuxInt = uint8ToAuxInt(14)
 +              v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec8x16ToM, types.TypeMask)
 +              v1.AddArg(mask)
 +              v0.AddArg3(x, y, v1)
 +              v.AddArg(v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpGreaterMaskedInt8x32(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      typ := &b.Func.Config.Types
 +      // match: (GreaterMaskedInt8x32 x y mask)
 +      // result: (VPMOVMToVec8x32 (VPCMPBMasked256 [14] x y (VPMOVVec8x32ToM <types.TypeMask> mask)))
 +      for {
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VPMOVMToVec8x32)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPCMPBMasked256, typ.Mask)
 +              v0.AuxInt = uint8ToAuxInt(14)
 +              v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec8x32ToM, types.TypeMask)
 +              v1.AddArg(mask)
 +              v0.AddArg3(x, y, v1)
 +              v.AddArg(v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpGreaterMaskedInt8x64(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      typ := &b.Func.Config.Types
 +      // match: (GreaterMaskedInt8x64 x y mask)
 +      // result: (VPMOVMToVec8x64 (VPCMPBMasked512 [14] x y (VPMOVVec8x64ToM <types.TypeMask> mask)))
 +      for {
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VPMOVMToVec8x64)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPCMPBMasked512, typ.Mask)
 +              v0.AuxInt = uint8ToAuxInt(14)
 +              v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec8x64ToM, types.TypeMask)
 +              v1.AddArg(mask)
 +              v0.AddArg3(x, y, v1)
 +              v.AddArg(v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpGreaterMaskedUint16x16(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      typ := &b.Func.Config.Types
 +      // match: (GreaterMaskedUint16x16 x y mask)
 +      // result: (VPMOVMToVec16x16 (VPCMPUWMasked256 [14] x y (VPMOVVec16x16ToM <types.TypeMask> mask)))
 +      for {
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VPMOVMToVec16x16)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPCMPUWMasked256, typ.Mask)
 +              v0.AuxInt = uint8ToAuxInt(14)
 +              v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x16ToM, types.TypeMask)
 +              v1.AddArg(mask)
 +              v0.AddArg3(x, y, v1)
 +              v.AddArg(v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpGreaterMaskedUint16x32(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      typ := &b.Func.Config.Types
 +      // match: (GreaterMaskedUint16x32 x y mask)
 +      // result: (VPMOVMToVec16x32 (VPCMPUWMasked512 [14] x y (VPMOVVec16x32ToM <types.TypeMask> mask)))
 +      for {
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VPMOVMToVec16x32)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPCMPUWMasked512, typ.Mask)
 +              v0.AuxInt = uint8ToAuxInt(14)
 +              v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x32ToM, types.TypeMask)
 +              v1.AddArg(mask)
 +              v0.AddArg3(x, y, v1)
 +              v.AddArg(v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpGreaterMaskedUint16x8(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      typ := &b.Func.Config.Types
 +      // match: (GreaterMaskedUint16x8 x y mask)
 +      // result: (VPMOVMToVec16x8 (VPCMPUWMasked128 [14] x y (VPMOVVec16x8ToM <types.TypeMask> mask)))
 +      for {
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VPMOVMToVec16x8)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPCMPUWMasked128, typ.Mask)
 +              v0.AuxInt = uint8ToAuxInt(14)
 +              v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x8ToM, types.TypeMask)
 +              v1.AddArg(mask)
 +              v0.AddArg3(x, y, v1)
 +              v.AddArg(v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpGreaterMaskedUint32x16(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      typ := &b.Func.Config.Types
 +      // match: (GreaterMaskedUint32x16 x y mask)
 +      // result: (VPMOVMToVec32x16 (VPCMPUDMasked512 [14] x y (VPMOVVec32x16ToM <types.TypeMask> mask)))
 +      for {
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VPMOVMToVec32x16)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPCMPUDMasked512, typ.Mask)
 +              v0.AuxInt = uint8ToAuxInt(14)
 +              v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x16ToM, types.TypeMask)
 +              v1.AddArg(mask)
 +              v0.AddArg3(x, y, v1)
 +              v.AddArg(v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpGreaterMaskedUint32x4(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      typ := &b.Func.Config.Types
 +      // match: (GreaterMaskedUint32x4 x y mask)
 +      // result: (VPMOVMToVec32x4 (VPCMPUDMasked128 [14] x y (VPMOVVec32x4ToM <types.TypeMask> mask)))
 +      for {
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VPMOVMToVec32x4)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPCMPUDMasked128, typ.Mask)
 +              v0.AuxInt = uint8ToAuxInt(14)
 +              v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x4ToM, types.TypeMask)
 +              v1.AddArg(mask)
 +              v0.AddArg3(x, y, v1)
 +              v.AddArg(v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpGreaterMaskedUint32x8(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      typ := &b.Func.Config.Types
 +      // match: (GreaterMaskedUint32x8 x y mask)
 +      // result: (VPMOVMToVec32x8 (VPCMPUDMasked256 [14] x y (VPMOVVec32x8ToM <types.TypeMask> mask)))
 +      for {
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VPMOVMToVec32x8)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPCMPUDMasked256, typ.Mask)
 +              v0.AuxInt = uint8ToAuxInt(14)
 +              v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x8ToM, types.TypeMask)
 +              v1.AddArg(mask)
 +              v0.AddArg3(x, y, v1)
 +              v.AddArg(v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpGreaterMaskedUint64x2(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      typ := &b.Func.Config.Types
 +      // match: (GreaterMaskedUint64x2 x y mask)
 +      // result: (VPMOVMToVec64x2 (VPCMPUQMasked128 [14] x y (VPMOVVec64x2ToM <types.TypeMask> mask)))
 +      for {
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VPMOVMToVec64x2)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPCMPUQMasked128, typ.Mask)
 +              v0.AuxInt = uint8ToAuxInt(14)
 +              v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x2ToM, types.TypeMask)
 +              v1.AddArg(mask)
 +              v0.AddArg3(x, y, v1)
 +              v.AddArg(v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpGreaterMaskedUint64x4(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      typ := &b.Func.Config.Types
 +      // match: (GreaterMaskedUint64x4 x y mask)
 +      // result: (VPMOVMToVec64x4 (VPCMPUQMasked256 [14] x y (VPMOVVec64x4ToM <types.TypeMask> mask)))
 +      for {
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VPMOVMToVec64x4)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPCMPUQMasked256, typ.Mask)
 +              v0.AuxInt = uint8ToAuxInt(14)
 +              v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x4ToM, types.TypeMask)
 +              v1.AddArg(mask)
 +              v0.AddArg3(x, y, v1)
 +              v.AddArg(v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpGreaterMaskedUint64x8(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      typ := &b.Func.Config.Types
 +      // match: (GreaterMaskedUint64x8 x y mask)
 +      // result: (VPMOVMToVec64x8 (VPCMPUQMasked512 [14] x y (VPMOVVec64x8ToM <types.TypeMask> mask)))
 +      for {
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VPMOVMToVec64x8)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPCMPUQMasked512, typ.Mask)
 +              v0.AuxInt = uint8ToAuxInt(14)
 +              v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x8ToM, types.TypeMask)
 +              v1.AddArg(mask)
 +              v0.AddArg3(x, y, v1)
 +              v.AddArg(v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpGreaterMaskedUint8x16(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      typ := &b.Func.Config.Types
 +      // match: (GreaterMaskedUint8x16 x y mask)
 +      // result: (VPMOVMToVec8x16 (VPCMPUBMasked128 [14] x y (VPMOVVec8x16ToM <types.TypeMask> mask)))
 +      for {
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VPMOVMToVec8x16)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPCMPUBMasked128, typ.Mask)
 +              v0.AuxInt = uint8ToAuxInt(14)
 +              v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec8x16ToM, types.TypeMask)
 +              v1.AddArg(mask)
 +              v0.AddArg3(x, y, v1)
 +              v.AddArg(v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpGreaterMaskedUint8x32(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      typ := &b.Func.Config.Types
 +      // match: (GreaterMaskedUint8x32 x y mask)
 +      // result: (VPMOVMToVec8x32 (VPCMPUBMasked256 [14] x y (VPMOVVec8x32ToM <types.TypeMask> mask)))
 +      for {
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VPMOVMToVec8x32)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPCMPUBMasked256, typ.Mask)
 +              v0.AuxInt = uint8ToAuxInt(14)
 +              v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec8x32ToM, types.TypeMask)
 +              v1.AddArg(mask)
 +              v0.AddArg3(x, y, v1)
 +              v.AddArg(v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpGreaterMaskedUint8x64(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      typ := &b.Func.Config.Types
 +      // match: (GreaterMaskedUint8x64 x y mask)
 +      // result: (VPMOVMToVec8x64 (VPCMPUBMasked512 [14] x y (VPMOVVec8x64ToM <types.TypeMask> mask)))
 +      for {
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VPMOVMToVec8x64)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPCMPUBMasked512, typ.Mask)
 +              v0.AuxInt = uint8ToAuxInt(14)
 +              v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec8x64ToM, types.TypeMask)
 +              v1.AddArg(mask)
 +              v0.AddArg3(x, y, v1)
 +              v.AddArg(v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpGreaterUint16x32(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      typ := &b.Func.Config.Types
 +      // match: (GreaterUint16x32 x y)
 +      // result: (VPMOVMToVec16x32 (VPCMPUW512 [14] x y))
 +      for {
 +              x := v_0
 +              y := v_1
 +              v.reset(OpAMD64VPMOVMToVec16x32)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPCMPUW512, typ.Mask)
 +              v0.AuxInt = uint8ToAuxInt(14)
 +              v0.AddArg2(x, y)
 +              v.AddArg(v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpGreaterUint32x16(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      typ := &b.Func.Config.Types
 +      // match: (GreaterUint32x16 x y)
 +      // result: (VPMOVMToVec32x16 (VPCMPUD512 [14] x y))
 +      for {
 +              x := v_0
 +              y := v_1
 +              v.reset(OpAMD64VPMOVMToVec32x16)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPCMPUD512, typ.Mask)
 +              v0.AuxInt = uint8ToAuxInt(14)
 +              v0.AddArg2(x, y)
 +              v.AddArg(v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpGreaterUint64x8(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      typ := &b.Func.Config.Types
 +      // match: (GreaterUint64x8 x y)
 +      // result: (VPMOVMToVec64x8 (VPCMPUQ512 [14] x y))
 +      for {
 +              x := v_0
 +              y := v_1
 +              v.reset(OpAMD64VPMOVMToVec64x8)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPCMPUQ512, typ.Mask)
 +              v0.AuxInt = uint8ToAuxInt(14)
 +              v0.AddArg2(x, y)
 +              v.AddArg(v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpGreaterUint8x64(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      typ := &b.Func.Config.Types
 +      // match: (GreaterUint8x64 x y)
 +      // result: (VPMOVMToVec8x64 (VPCMPUB512 [14] x y))
 +      for {
 +              x := v_0
 +              y := v_1
 +              v.reset(OpAMD64VPMOVMToVec8x64)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPCMPUB512, typ.Mask)
 +              v0.AuxInt = uint8ToAuxInt(14)
 +              v0.AddArg2(x, y)
 +              v.AddArg(v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpHasCPUFeature(v *Value) bool {
 +      b := v.Block
 +      typ := &b.Func.Config.Types
 +      // match: (HasCPUFeature {s})
 +      // result: (SETNE (CMPLconst [0] (LoweredHasCPUFeature {s})))
 +      for {
 +              s := auxToSym(v.Aux)
 +              v.reset(OpAMD64SETNE)
 +              v0 := b.NewValue0(v.Pos, OpAMD64CMPLconst, types.TypeFlags)
 +              v0.AuxInt = int32ToAuxInt(0)
 +              v1 := b.NewValue0(v.Pos, OpAMD64LoweredHasCPUFeature, typ.UInt64)
 +              v1.Aux = symToAux(s)
 +              v0.AddArg(v1)
 +              v.AddArg(v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpIsInBounds(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (IsInBounds idx len)
 +      // result: (SETB (CMPQ idx len))
 +      for {
 +              idx := v_0
 +              len := v_1
 +              v.reset(OpAMD64SETB)
 +              v0 := b.NewValue0(v.Pos, OpAMD64CMPQ, types.TypeFlags)
 +              v0.AddArg2(idx, len)
 +              v.AddArg(v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpIsNanFloat32x16(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      typ := &b.Func.Config.Types
 +      // match: (IsNanFloat32x16 x y)
 +      // result: (VPMOVMToVec32x16 (VCMPPS512 [3] x y))
 +      for {
 +              x := v_0
 +              y := v_1
 +              v.reset(OpAMD64VPMOVMToVec32x16)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VCMPPS512, typ.Mask)
 +              v0.AuxInt = uint8ToAuxInt(3)
 +              v0.AddArg2(x, y)
 +              v.AddArg(v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpIsNanFloat32x4(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      // match: (IsNanFloat32x4 x y)
 +      // result: (VCMPPS128 [3] x y)
 +      for {
 +              x := v_0
 +              y := v_1
 +              v.reset(OpAMD64VCMPPS128)
 +              v.AuxInt = uint8ToAuxInt(3)
 +              v.AddArg2(x, y)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpIsNanFloat32x8(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      // match: (IsNanFloat32x8 x y)
 +      // result: (VCMPPS256 [3] x y)
 +      for {
 +              x := v_0
 +              y := v_1
 +              v.reset(OpAMD64VCMPPS256)
 +              v.AuxInt = uint8ToAuxInt(3)
 +              v.AddArg2(x, y)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpIsNanFloat64x2(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      // match: (IsNanFloat64x2 x y)
 +      // result: (VCMPPD128 [3] x y)
 +      for {
 +              x := v_0
 +              y := v_1
 +              v.reset(OpAMD64VCMPPD128)
 +              v.AuxInt = uint8ToAuxInt(3)
 +              v.AddArg2(x, y)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpIsNanFloat64x4(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      // match: (IsNanFloat64x4 x y)
 +      // result: (VCMPPD256 [3] x y)
 +      for {
 +              x := v_0
 +              y := v_1
 +              v.reset(OpAMD64VCMPPD256)
 +              v.AuxInt = uint8ToAuxInt(3)
 +              v.AddArg2(x, y)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpIsNanFloat64x8(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      typ := &b.Func.Config.Types
 +      // match: (IsNanFloat64x8 x y)
 +      // result: (VPMOVMToVec64x8 (VCMPPD512 [3] x y))
 +      for {
 +              x := v_0
 +              y := v_1
 +              v.reset(OpAMD64VPMOVMToVec64x8)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VCMPPD512, typ.Mask)
 +              v0.AuxInt = uint8ToAuxInt(3)
 +              v0.AddArg2(x, y)
 +              v.AddArg(v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpIsNanMaskedFloat32x16(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      typ := &b.Func.Config.Types
 +      // match: (IsNanMaskedFloat32x16 x y mask)
 +      // result: (VPMOVMToVec32x16 (VCMPPSMasked512 [3] x y (VPMOVVec32x16ToM <types.TypeMask> mask)))
 +      for {
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VPMOVMToVec32x16)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VCMPPSMasked512, typ.Mask)
 +              v0.AuxInt = uint8ToAuxInt(3)
 +              v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x16ToM, types.TypeMask)
 +              v1.AddArg(mask)
 +              v0.AddArg3(x, y, v1)
 +              v.AddArg(v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpIsNanMaskedFloat32x4(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      typ := &b.Func.Config.Types
 +      // match: (IsNanMaskedFloat32x4 x y mask)
 +      // result: (VPMOVMToVec32x4 (VCMPPSMasked128 [3] x y (VPMOVVec32x4ToM <types.TypeMask> mask)))
 +      for {
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VPMOVMToVec32x4)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VCMPPSMasked128, typ.Mask)
 +              v0.AuxInt = uint8ToAuxInt(3)
 +              v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x4ToM, types.TypeMask)
 +              v1.AddArg(mask)
 +              v0.AddArg3(x, y, v1)
 +              v.AddArg(v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpIsNanMaskedFloat32x8(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      typ := &b.Func.Config.Types
 +      // match: (IsNanMaskedFloat32x8 x y mask)
 +      // result: (VPMOVMToVec32x8 (VCMPPSMasked256 [3] x y (VPMOVVec32x8ToM <types.TypeMask> mask)))
 +      for {
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VPMOVMToVec32x8)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VCMPPSMasked256, typ.Mask)
 +              v0.AuxInt = uint8ToAuxInt(3)
 +              v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x8ToM, types.TypeMask)
 +              v1.AddArg(mask)
 +              v0.AddArg3(x, y, v1)
 +              v.AddArg(v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpIsNanMaskedFloat64x2(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      typ := &b.Func.Config.Types
 +      // match: (IsNanMaskedFloat64x2 x y mask)
 +      // result: (VPMOVMToVec64x2 (VCMPPDMasked128 [3] x y (VPMOVVec64x2ToM <types.TypeMask> mask)))
 +      for {
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VPMOVMToVec64x2)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VCMPPDMasked128, typ.Mask)
 +              v0.AuxInt = uint8ToAuxInt(3)
 +              v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x2ToM, types.TypeMask)
 +              v1.AddArg(mask)
 +              v0.AddArg3(x, y, v1)
 +              v.AddArg(v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpIsNanMaskedFloat64x4(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      typ := &b.Func.Config.Types
 +      // match: (IsNanMaskedFloat64x4 x y mask)
 +      // result: (VPMOVMToVec64x4 (VCMPPDMasked256 [3] x y (VPMOVVec64x4ToM <types.TypeMask> mask)))
 +      for {
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VPMOVMToVec64x4)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VCMPPDMasked256, typ.Mask)
 +              v0.AuxInt = uint8ToAuxInt(3)
 +              v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x4ToM, types.TypeMask)
 +              v1.AddArg(mask)
 +              v0.AddArg3(x, y, v1)
 +              v.AddArg(v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpIsNanMaskedFloat64x8(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      typ := &b.Func.Config.Types
 +      // match: (IsNanMaskedFloat64x8 x y mask)
 +      // result: (VPMOVMToVec64x8 (VCMPPDMasked512 [3] x y (VPMOVVec64x8ToM <types.TypeMask> mask)))
 +      for {
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VPMOVMToVec64x8)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VCMPPDMasked512, typ.Mask)
 +              v0.AuxInt = uint8ToAuxInt(3)
 +              v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x8ToM, types.TypeMask)
 +              v1.AddArg(mask)
 +              v0.AddArg3(x, y, v1)
 +              v.AddArg(v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpIsNonNil(v *Value) bool {
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (IsNonNil p)
 +      // result: (SETNE (TESTQ p p))
 +      for {
 +              p := v_0
 +              v.reset(OpAMD64SETNE)
 +              v0 := b.NewValue0(v.Pos, OpAMD64TESTQ, types.TypeFlags)
 +              v0.AddArg2(p, p)
 +              v.AddArg(v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpIsSliceInBounds(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (IsSliceInBounds idx len)
 +      // result: (SETBE (CMPQ idx len))
 +      for {
 +              idx := v_0
 +              len := v_1
 +              v.reset(OpAMD64SETBE)
 +              v0 := b.NewValue0(v.Pos, OpAMD64CMPQ, types.TypeFlags)
 +              v0.AddArg2(idx, len)
 +              v.AddArg(v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpLeq16(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (Leq16 x y)
 +      // result: (SETLE (CMPW x y))
 +      for {
 +              x := v_0
 +              y := v_1
 +              v.reset(OpAMD64SETLE)
 +              v0 := b.NewValue0(v.Pos, OpAMD64CMPW, types.TypeFlags)
 +              v0.AddArg2(x, y)
 +              v.AddArg(v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpLeq16U(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (Leq16U x y)
 +      // result: (SETBE (CMPW x y))
 +      for {
 +              x := v_0
 +              y := v_1
 +              v.reset(OpAMD64SETBE)
 +              v0 := b.NewValue0(v.Pos, OpAMD64CMPW, types.TypeFlags)
 +              v0.AddArg2(x, y)
 +              v.AddArg(v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpLeq32(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (Leq32 x y)
 +      // result: (SETLE (CMPL x y))
 +      for {
 +              x := v_0
 +              y := v_1
 +              v.reset(OpAMD64SETLE)
 +              v0 := b.NewValue0(v.Pos, OpAMD64CMPL, types.TypeFlags)
 +              v0.AddArg2(x, y)
 +              v.AddArg(v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpLeq32F(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (Leq32F x y)
 +      // result: (SETGEF (UCOMISS y x))
 +      for {
 +              x := v_0
 +              y := v_1
 +              v.reset(OpAMD64SETGEF)
 +              v0 := b.NewValue0(v.Pos, OpAMD64UCOMISS, types.TypeFlags)
 +              v0.AddArg2(y, x)
 +              v.AddArg(v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpLeq32U(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (Leq32U x y)
 +      // result: (SETBE (CMPL x y))
 +      for {
 +              x := v_0
 +              y := v_1
 +              v.reset(OpAMD64SETBE)
 +              v0 := b.NewValue0(v.Pos, OpAMD64CMPL, types.TypeFlags)
 +              v0.AddArg2(x, y)
 +              v.AddArg(v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpLeq64(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (Leq64 x y)
 +      // result: (SETLE (CMPQ x y))
 +      for {
 +              x := v_0
 +              y := v_1
 +              v.reset(OpAMD64SETLE)
 +              v0 := b.NewValue0(v.Pos, OpAMD64CMPQ, types.TypeFlags)
 +              v0.AddArg2(x, y)
 +              v.AddArg(v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpLeq64F(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (Leq64F x y)
 +      // result: (SETGEF (UCOMISD y x))
 +      for {
 +              x := v_0
 +              y := v_1
 +              v.reset(OpAMD64SETGEF)
 +              v0 := b.NewValue0(v.Pos, OpAMD64UCOMISD, types.TypeFlags)
 +              v0.AddArg2(y, x)
 +              v.AddArg(v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpLeq64U(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (Leq64U x y)
 +      // result: (SETBE (CMPQ x y))
 +      for {
 +              x := v_0
 +              y := v_1
 +              v.reset(OpAMD64SETBE)
 +              v0 := b.NewValue0(v.Pos, OpAMD64CMPQ, types.TypeFlags)
 +              v0.AddArg2(x, y)
 +              v.AddArg(v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpLeq8(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (Leq8 x y)
 +      // result: (SETLE (CMPB x y))
 +      for {
 +              x := v_0
 +              y := v_1
 +              v.reset(OpAMD64SETLE)
 +              v0 := b.NewValue0(v.Pos, OpAMD64CMPB, types.TypeFlags)
 +              v0.AddArg2(x, y)
 +              v.AddArg(v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpLeq8U(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (Leq8U x y)
 +      // result: (SETBE (CMPB x y))
 +      for {
 +              x := v_0
 +              y := v_1
 +              v.reset(OpAMD64SETBE)
 +              v0 := b.NewValue0(v.Pos, OpAMD64CMPB, types.TypeFlags)
 +              v0.AddArg2(x, y)
 +              v.AddArg(v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpLess16(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (Less16 x y)
 +      // result: (SETL (CMPW x y))
 +      for {
 +              x := v_0
 +              y := v_1
 +              v.reset(OpAMD64SETL)
 +              v0 := b.NewValue0(v.Pos, OpAMD64CMPW, types.TypeFlags)
 +              v0.AddArg2(x, y)
 +              v.AddArg(v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpLess16U(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (Less16U x y)
 +      // result: (SETB (CMPW x y))
 +      for {
 +              x := v_0
 +              y := v_1
 +              v.reset(OpAMD64SETB)
 +              v0 := b.NewValue0(v.Pos, OpAMD64CMPW, types.TypeFlags)
 +              v0.AddArg2(x, y)
 +              v.AddArg(v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpLess32(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (Less32 x y)
 +      // result: (SETL (CMPL x y))
 +      for {
 +              x := v_0
 +              y := v_1
 +              v.reset(OpAMD64SETL)
 +              v0 := b.NewValue0(v.Pos, OpAMD64CMPL, types.TypeFlags)
 +              v0.AddArg2(x, y)
 +              v.AddArg(v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpLess32F(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (Less32F x y)
 +      // result: (SETGF (UCOMISS y x))
 +      for {
 +              x := v_0
 +              y := v_1
 +              v.reset(OpAMD64SETGF)
 +              v0 := b.NewValue0(v.Pos, OpAMD64UCOMISS, types.TypeFlags)
 +              v0.AddArg2(y, x)
 +              v.AddArg(v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpLess32U(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (Less32U x y)
 +      // result: (SETB (CMPL x y))
 +      for {
 +              x := v_0
 +              y := v_1
 +              v.reset(OpAMD64SETB)
 +              v0 := b.NewValue0(v.Pos, OpAMD64CMPL, types.TypeFlags)
 +              v0.AddArg2(x, y)
 +              v.AddArg(v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpLess64(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (Less64 x y)
 +      // result: (SETL (CMPQ x y))
 +      for {
 +              x := v_0
 +              y := v_1
 +              v.reset(OpAMD64SETL)
 +              v0 := b.NewValue0(v.Pos, OpAMD64CMPQ, types.TypeFlags)
 +              v0.AddArg2(x, y)
 +              v.AddArg(v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpLess64F(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (Less64F x y)
 +      // result: (SETGF (UCOMISD y x))
 +      for {
 +              x := v_0
 +              y := v_1
 +              v.reset(OpAMD64SETGF)
 +              v0 := b.NewValue0(v.Pos, OpAMD64UCOMISD, types.TypeFlags)
 +              v0.AddArg2(y, x)
 +              v.AddArg(v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpLess64U(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (Less64U x y)
 +      // result: (SETB (CMPQ x y))
 +      for {
 +              x := v_0
 +              y := v_1
 +              v.reset(OpAMD64SETB)
 +              v0 := b.NewValue0(v.Pos, OpAMD64CMPQ, types.TypeFlags)
 +              v0.AddArg2(x, y)
 +              v.AddArg(v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpLess8(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (Less8 x y)
 +      // result: (SETL (CMPB x y))
 +      for {
 +              x := v_0
 +              y := v_1
 +              v.reset(OpAMD64SETL)
 +              v0 := b.NewValue0(v.Pos, OpAMD64CMPB, types.TypeFlags)
 +              v0.AddArg2(x, y)
 +              v.AddArg(v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpLess8U(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (Less8U x y)
 +      // result: (SETB (CMPB x y))
 +      for {
 +              x := v_0
 +              y := v_1
 +              v.reset(OpAMD64SETB)
 +              v0 := b.NewValue0(v.Pos, OpAMD64CMPB, types.TypeFlags)
 +              v0.AddArg2(x, y)
 +              v.AddArg(v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpLessEqualFloat32x16(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      typ := &b.Func.Config.Types
 +      // match: (LessEqualFloat32x16 x y)
 +      // result: (VPMOVMToVec32x16 (VCMPPS512 [2] x y))
 +      for {
 +              x := v_0
 +              y := v_1
 +              v.reset(OpAMD64VPMOVMToVec32x16)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VCMPPS512, typ.Mask)
 +              v0.AuxInt = uint8ToAuxInt(2)
 +              v0.AddArg2(x, y)
 +              v.AddArg(v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpLessEqualFloat32x4(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      // match: (LessEqualFloat32x4 x y)
 +      // result: (VCMPPS128 [2] x y)
 +      for {
 +              x := v_0
 +              y := v_1
 +              v.reset(OpAMD64VCMPPS128)
 +              v.AuxInt = uint8ToAuxInt(2)
 +              v.AddArg2(x, y)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpLessEqualFloat32x8(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      // match: (LessEqualFloat32x8 x y)
 +      // result: (VCMPPS256 [2] x y)
 +      for {
 +              x := v_0
 +              y := v_1
 +              v.reset(OpAMD64VCMPPS256)
 +              v.AuxInt = uint8ToAuxInt(2)
 +              v.AddArg2(x, y)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpLessEqualFloat64x2(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      // match: (LessEqualFloat64x2 x y)
 +      // result: (VCMPPD128 [2] x y)
 +      for {
 +              x := v_0
 +              y := v_1
 +              v.reset(OpAMD64VCMPPD128)
 +              v.AuxInt = uint8ToAuxInt(2)
 +              v.AddArg2(x, y)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpLessEqualFloat64x4(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      // match: (LessEqualFloat64x4 x y)
 +      // result: (VCMPPD256 [2] x y)
 +      for {
 +              x := v_0
 +              y := v_1
 +              v.reset(OpAMD64VCMPPD256)
 +              v.AuxInt = uint8ToAuxInt(2)
 +              v.AddArg2(x, y)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpLessEqualFloat64x8(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      typ := &b.Func.Config.Types
 +      // match: (LessEqualFloat64x8 x y)
 +      // result: (VPMOVMToVec64x8 (VCMPPD512 [2] x y))
 +      for {
 +              x := v_0
 +              y := v_1
 +              v.reset(OpAMD64VPMOVMToVec64x8)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VCMPPD512, typ.Mask)
 +              v0.AuxInt = uint8ToAuxInt(2)
 +              v0.AddArg2(x, y)
 +              v.AddArg(v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpLessEqualInt16x32(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      typ := &b.Func.Config.Types
 +      // match: (LessEqualInt16x32 x y)
 +      // result: (VPMOVMToVec16x32 (VPCMPW512 [2] x y))
 +      for {
 +              x := v_0
 +              y := v_1
 +              v.reset(OpAMD64VPMOVMToVec16x32)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPCMPW512, typ.Mask)
 +              v0.AuxInt = uint8ToAuxInt(2)
 +              v0.AddArg2(x, y)
 +              v.AddArg(v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpLessEqualInt32x16(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      typ := &b.Func.Config.Types
 +      // match: (LessEqualInt32x16 x y)
 +      // result: (VPMOVMToVec32x16 (VPCMPD512 [2] x y))
 +      for {
 +              x := v_0
 +              y := v_1
 +              v.reset(OpAMD64VPMOVMToVec32x16)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPCMPD512, typ.Mask)
 +              v0.AuxInt = uint8ToAuxInt(2)
 +              v0.AddArg2(x, y)
 +              v.AddArg(v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpLessEqualInt64x8(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      typ := &b.Func.Config.Types
 +      // match: (LessEqualInt64x8 x y)
 +      // result: (VPMOVMToVec64x8 (VPCMPQ512 [2] x y))
 +      for {
 +              x := v_0
 +              y := v_1
 +              v.reset(OpAMD64VPMOVMToVec64x8)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPCMPQ512, typ.Mask)
 +              v0.AuxInt = uint8ToAuxInt(2)
 +              v0.AddArg2(x, y)
 +              v.AddArg(v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpLessEqualInt8x64(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      typ := &b.Func.Config.Types
 +      // match: (LessEqualInt8x64 x y)
 +      // result: (VPMOVMToVec8x64 (VPCMPB512 [2] x y))
 +      for {
 +              x := v_0
 +              y := v_1
 +              v.reset(OpAMD64VPMOVMToVec8x64)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPCMPB512, typ.Mask)
 +              v0.AuxInt = uint8ToAuxInt(2)
 +              v0.AddArg2(x, y)
 +              v.AddArg(v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpLessEqualMaskedFloat32x16(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      typ := &b.Func.Config.Types
 +      // match: (LessEqualMaskedFloat32x16 x y mask)
 +      // result: (VPMOVMToVec32x16 (VCMPPSMasked512 [2] x y (VPMOVVec32x16ToM <types.TypeMask> mask)))
 +      for {
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VPMOVMToVec32x16)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VCMPPSMasked512, typ.Mask)
 +              v0.AuxInt = uint8ToAuxInt(2)
 +              v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x16ToM, types.TypeMask)
 +              v1.AddArg(mask)
 +              v0.AddArg3(x, y, v1)
 +              v.AddArg(v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpLessEqualMaskedFloat32x4(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      typ := &b.Func.Config.Types
 +      // match: (LessEqualMaskedFloat32x4 x y mask)
 +      // result: (VPMOVMToVec32x4 (VCMPPSMasked128 [2] x y (VPMOVVec32x4ToM <types.TypeMask> mask)))
 +      for {
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VPMOVMToVec32x4)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VCMPPSMasked128, typ.Mask)
 +              v0.AuxInt = uint8ToAuxInt(2)
 +              v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x4ToM, types.TypeMask)
 +              v1.AddArg(mask)
 +              v0.AddArg3(x, y, v1)
 +              v.AddArg(v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpLessEqualMaskedFloat32x8(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      typ := &b.Func.Config.Types
 +      // match: (LessEqualMaskedFloat32x8 x y mask)
 +      // result: (VPMOVMToVec32x8 (VCMPPSMasked256 [2] x y (VPMOVVec32x8ToM <types.TypeMask> mask)))
 +      for {
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VPMOVMToVec32x8)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VCMPPSMasked256, typ.Mask)
 +              v0.AuxInt = uint8ToAuxInt(2)
 +              v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x8ToM, types.TypeMask)
 +              v1.AddArg(mask)
 +              v0.AddArg3(x, y, v1)
 +              v.AddArg(v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpLessEqualMaskedFloat64x2(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      typ := &b.Func.Config.Types
 +      // match: (LessEqualMaskedFloat64x2 x y mask)
 +      // result: (VPMOVMToVec64x2 (VCMPPDMasked128 [2] x y (VPMOVVec64x2ToM <types.TypeMask> mask)))
 +      for {
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VPMOVMToVec64x2)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VCMPPDMasked128, typ.Mask)
 +              v0.AuxInt = uint8ToAuxInt(2)
 +              v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x2ToM, types.TypeMask)
 +              v1.AddArg(mask)
 +              v0.AddArg3(x, y, v1)
 +              v.AddArg(v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpLessEqualMaskedFloat64x4(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      typ := &b.Func.Config.Types
 +      // match: (LessEqualMaskedFloat64x4 x y mask)
 +      // result: (VPMOVMToVec64x4 (VCMPPDMasked256 [2] x y (VPMOVVec64x4ToM <types.TypeMask> mask)))
 +      for {
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VPMOVMToVec64x4)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VCMPPDMasked256, typ.Mask)
 +              v0.AuxInt = uint8ToAuxInt(2)
 +              v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x4ToM, types.TypeMask)
 +              v1.AddArg(mask)
 +              v0.AddArg3(x, y, v1)
 +              v.AddArg(v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpLessEqualMaskedFloat64x8(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      typ := &b.Func.Config.Types
 +      // match: (LessEqualMaskedFloat64x8 x y mask)
 +      // result: (VPMOVMToVec64x8 (VCMPPDMasked512 [2] x y (VPMOVVec64x8ToM <types.TypeMask> mask)))
 +      for {
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VPMOVMToVec64x8)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VCMPPDMasked512, typ.Mask)
 +              v0.AuxInt = uint8ToAuxInt(2)
 +              v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x8ToM, types.TypeMask)
 +              v1.AddArg(mask)
 +              v0.AddArg3(x, y, v1)
 +              v.AddArg(v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpLessEqualMaskedInt16x16(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      typ := &b.Func.Config.Types
 +      // match: (LessEqualMaskedInt16x16 x y mask)
 +      // result: (VPMOVMToVec16x16 (VPCMPWMasked256 [2] x y (VPMOVVec16x16ToM <types.TypeMask> mask)))
 +      for {
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VPMOVMToVec16x16)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPCMPWMasked256, typ.Mask)
 +              v0.AuxInt = uint8ToAuxInt(2)
 +              v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x16ToM, types.TypeMask)
 +              v1.AddArg(mask)
 +              v0.AddArg3(x, y, v1)
 +              v.AddArg(v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpLessEqualMaskedInt16x32(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      typ := &b.Func.Config.Types
 +      // match: (LessEqualMaskedInt16x32 x y mask)
 +      // result: (VPMOVMToVec16x32 (VPCMPWMasked512 [2] x y (VPMOVVec16x32ToM <types.TypeMask> mask)))
 +      for {
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VPMOVMToVec16x32)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPCMPWMasked512, typ.Mask)
 +              v0.AuxInt = uint8ToAuxInt(2)
 +              v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x32ToM, types.TypeMask)
 +              v1.AddArg(mask)
 +              v0.AddArg3(x, y, v1)
 +              v.AddArg(v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpLessEqualMaskedInt16x8(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      typ := &b.Func.Config.Types
 +      // match: (LessEqualMaskedInt16x8 x y mask)
 +      // result: (VPMOVMToVec16x8 (VPCMPWMasked128 [2] x y (VPMOVVec16x8ToM <types.TypeMask> mask)))
 +      for {
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VPMOVMToVec16x8)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPCMPWMasked128, typ.Mask)
 +              v0.AuxInt = uint8ToAuxInt(2)
 +              v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x8ToM, types.TypeMask)
 +              v1.AddArg(mask)
 +              v0.AddArg3(x, y, v1)
 +              v.AddArg(v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpLessEqualMaskedInt32x16(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      typ := &b.Func.Config.Types
 +      // match: (LessEqualMaskedInt32x16 x y mask)
 +      // result: (VPMOVMToVec32x16 (VPCMPDMasked512 [2] x y (VPMOVVec32x16ToM <types.TypeMask> mask)))
 +      for {
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VPMOVMToVec32x16)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPCMPDMasked512, typ.Mask)
 +              v0.AuxInt = uint8ToAuxInt(2)
 +              v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x16ToM, types.TypeMask)
 +              v1.AddArg(mask)
 +              v0.AddArg3(x, y, v1)
 +              v.AddArg(v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpLessEqualMaskedInt32x4(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      typ := &b.Func.Config.Types
 +      // match: (LessEqualMaskedInt32x4 x y mask)
 +      // result: (VPMOVMToVec32x4 (VPCMPDMasked128 [2] x y (VPMOVVec32x4ToM <types.TypeMask> mask)))
 +      for {
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VPMOVMToVec32x4)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPCMPDMasked128, typ.Mask)
 +              v0.AuxInt = uint8ToAuxInt(2)
 +              v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x4ToM, types.TypeMask)
 +              v1.AddArg(mask)
 +              v0.AddArg3(x, y, v1)
 +              v.AddArg(v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpLessEqualMaskedInt32x8(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      typ := &b.Func.Config.Types
 +      // match: (LessEqualMaskedInt32x8 x y mask)
 +      // result: (VPMOVMToVec32x8 (VPCMPDMasked256 [2] x y (VPMOVVec32x8ToM <types.TypeMask> mask)))
 +      for {
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VPMOVMToVec32x8)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPCMPDMasked256, typ.Mask)
 +              v0.AuxInt = uint8ToAuxInt(2)
 +              v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x8ToM, types.TypeMask)
 +              v1.AddArg(mask)
 +              v0.AddArg3(x, y, v1)
 +              v.AddArg(v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpLessEqualMaskedInt64x2(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      typ := &b.Func.Config.Types
 +      // match: (LessEqualMaskedInt64x2 x y mask)
 +      // result: (VPMOVMToVec64x2 (VPCMPQMasked128 [2] x y (VPMOVVec64x2ToM <types.TypeMask> mask)))
 +      for {
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VPMOVMToVec64x2)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPCMPQMasked128, typ.Mask)
 +              v0.AuxInt = uint8ToAuxInt(2)
 +              v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x2ToM, types.TypeMask)
 +              v1.AddArg(mask)
 +              v0.AddArg3(x, y, v1)
 +              v.AddArg(v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpLessEqualMaskedInt64x4(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      typ := &b.Func.Config.Types
 +      // match: (LessEqualMaskedInt64x4 x y mask)
 +      // result: (VPMOVMToVec64x4 (VPCMPQMasked256 [2] x y (VPMOVVec64x4ToM <types.TypeMask> mask)))
 +      for {
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VPMOVMToVec64x4)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPCMPQMasked256, typ.Mask)
 +              v0.AuxInt = uint8ToAuxInt(2)
 +              v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x4ToM, types.TypeMask)
 +              v1.AddArg(mask)
 +              v0.AddArg3(x, y, v1)
 +              v.AddArg(v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpLessEqualMaskedInt64x8(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      typ := &b.Func.Config.Types
 +      // match: (LessEqualMaskedInt64x8 x y mask)
 +      // result: (VPMOVMToVec64x8 (VPCMPQMasked512 [2] x y (VPMOVVec64x8ToM <types.TypeMask> mask)))
 +      for {
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VPMOVMToVec64x8)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPCMPQMasked512, typ.Mask)
 +              v0.AuxInt = uint8ToAuxInt(2)
 +              v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x8ToM, types.TypeMask)
 +              v1.AddArg(mask)
 +              v0.AddArg3(x, y, v1)
 +              v.AddArg(v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpLessEqualMaskedInt8x16(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      typ := &b.Func.Config.Types
 +      // match: (LessEqualMaskedInt8x16 x y mask)
 +      // result: (VPMOVMToVec8x16 (VPCMPBMasked128 [2] x y (VPMOVVec8x16ToM <types.TypeMask> mask)))
 +      for {
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VPMOVMToVec8x16)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPCMPBMasked128, typ.Mask)
 +              v0.AuxInt = uint8ToAuxInt(2)
 +              v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec8x16ToM, types.TypeMask)
 +              v1.AddArg(mask)
 +              v0.AddArg3(x, y, v1)
 +              v.AddArg(v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpLessEqualMaskedInt8x32(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      typ := &b.Func.Config.Types
 +      // match: (LessEqualMaskedInt8x32 x y mask)
 +      // result: (VPMOVMToVec8x32 (VPCMPBMasked256 [2] x y (VPMOVVec8x32ToM <types.TypeMask> mask)))
 +      for {
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VPMOVMToVec8x32)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPCMPBMasked256, typ.Mask)
 +              v0.AuxInt = uint8ToAuxInt(2)
 +              v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec8x32ToM, types.TypeMask)
 +              v1.AddArg(mask)
 +              v0.AddArg3(x, y, v1)
 +              v.AddArg(v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpLessEqualMaskedInt8x64(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      typ := &b.Func.Config.Types
 +      // match: (LessEqualMaskedInt8x64 x y mask)
 +      // result: (VPMOVMToVec8x64 (VPCMPBMasked512 [2] x y (VPMOVVec8x64ToM <types.TypeMask> mask)))
 +      for {
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VPMOVMToVec8x64)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPCMPBMasked512, typ.Mask)
 +              v0.AuxInt = uint8ToAuxInt(2)
 +              v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec8x64ToM, types.TypeMask)
 +              v1.AddArg(mask)
 +              v0.AddArg3(x, y, v1)
 +              v.AddArg(v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpLessEqualMaskedUint16x16(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      typ := &b.Func.Config.Types
 +      // match: (LessEqualMaskedUint16x16 x y mask)
 +      // result: (VPMOVMToVec16x16 (VPCMPUWMasked256 [2] x y (VPMOVVec16x16ToM <types.TypeMask> mask)))
 +      for {
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VPMOVMToVec16x16)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPCMPUWMasked256, typ.Mask)
 +              v0.AuxInt = uint8ToAuxInt(2)
 +              v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x16ToM, types.TypeMask)
 +              v1.AddArg(mask)
 +              v0.AddArg3(x, y, v1)
 +              v.AddArg(v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpLessEqualMaskedUint16x32(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      typ := &b.Func.Config.Types
 +      // match: (LessEqualMaskedUint16x32 x y mask)
 +      // result: (VPMOVMToVec16x32 (VPCMPUWMasked512 [2] x y (VPMOVVec16x32ToM <types.TypeMask> mask)))
 +      for {
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VPMOVMToVec16x32)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPCMPUWMasked512, typ.Mask)
 +              v0.AuxInt = uint8ToAuxInt(2)
 +              v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x32ToM, types.TypeMask)
 +              v1.AddArg(mask)
 +              v0.AddArg3(x, y, v1)
 +              v.AddArg(v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpLessEqualMaskedUint16x8(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      typ := &b.Func.Config.Types
 +      // match: (LessEqualMaskedUint16x8 x y mask)
 +      // result: (VPMOVMToVec16x8 (VPCMPUWMasked128 [2] x y (VPMOVVec16x8ToM <types.TypeMask> mask)))
 +      for {
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VPMOVMToVec16x8)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPCMPUWMasked128, typ.Mask)
 +              v0.AuxInt = uint8ToAuxInt(2)
 +              v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x8ToM, types.TypeMask)
 +              v1.AddArg(mask)
 +              v0.AddArg3(x, y, v1)
 +              v.AddArg(v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpLessEqualMaskedUint32x16(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      typ := &b.Func.Config.Types
 +      // match: (LessEqualMaskedUint32x16 x y mask)
 +      // result: (VPMOVMToVec32x16 (VPCMPUDMasked512 [2] x y (VPMOVVec32x16ToM <types.TypeMask> mask)))
 +      for {
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VPMOVMToVec32x16)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPCMPUDMasked512, typ.Mask)
 +              v0.AuxInt = uint8ToAuxInt(2)
 +              v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x16ToM, types.TypeMask)
 +              v1.AddArg(mask)
 +              v0.AddArg3(x, y, v1)
 +              v.AddArg(v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpLessEqualMaskedUint32x4(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      typ := &b.Func.Config.Types
 +      // match: (LessEqualMaskedUint32x4 x y mask)
 +      // result: (VPMOVMToVec32x4 (VPCMPUDMasked128 [2] x y (VPMOVVec32x4ToM <types.TypeMask> mask)))
 +      for {
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VPMOVMToVec32x4)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPCMPUDMasked128, typ.Mask)
 +              v0.AuxInt = uint8ToAuxInt(2)
 +              v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x4ToM, types.TypeMask)
 +              v1.AddArg(mask)
 +              v0.AddArg3(x, y, v1)
 +              v.AddArg(v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpLessEqualMaskedUint32x8(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      typ := &b.Func.Config.Types
 +      // match: (LessEqualMaskedUint32x8 x y mask)
 +      // result: (VPMOVMToVec32x8 (VPCMPUDMasked256 [2] x y (VPMOVVec32x8ToM <types.TypeMask> mask)))
 +      for {
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VPMOVMToVec32x8)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPCMPUDMasked256, typ.Mask)
 +              v0.AuxInt = uint8ToAuxInt(2)
 +              v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x8ToM, types.TypeMask)
 +              v1.AddArg(mask)
 +              v0.AddArg3(x, y, v1)
 +              v.AddArg(v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpLessEqualMaskedUint64x2(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      typ := &b.Func.Config.Types
 +      // match: (LessEqualMaskedUint64x2 x y mask)
 +      // result: (VPMOVMToVec64x2 (VPCMPUQMasked128 [2] x y (VPMOVVec64x2ToM <types.TypeMask> mask)))
 +      for {
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VPMOVMToVec64x2)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPCMPUQMasked128, typ.Mask)
 +              v0.AuxInt = uint8ToAuxInt(2)
 +              v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x2ToM, types.TypeMask)
 +              v1.AddArg(mask)
 +              v0.AddArg3(x, y, v1)
 +              v.AddArg(v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpLessEqualMaskedUint64x4(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      typ := &b.Func.Config.Types
 +      // match: (LessEqualMaskedUint64x4 x y mask)
 +      // result: (VPMOVMToVec64x4 (VPCMPUQMasked256 [2] x y (VPMOVVec64x4ToM <types.TypeMask> mask)))
 +      for {
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VPMOVMToVec64x4)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPCMPUQMasked256, typ.Mask)
 +              v0.AuxInt = uint8ToAuxInt(2)
 +              v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x4ToM, types.TypeMask)
 +              v1.AddArg(mask)
 +              v0.AddArg3(x, y, v1)
 +              v.AddArg(v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpLessEqualMaskedUint64x8(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      typ := &b.Func.Config.Types
 +      // match: (LessEqualMaskedUint64x8 x y mask)
 +      // result: (VPMOVMToVec64x8 (VPCMPUQMasked512 [2] x y (VPMOVVec64x8ToM <types.TypeMask> mask)))
 +      for {
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VPMOVMToVec64x8)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPCMPUQMasked512, typ.Mask)
 +              v0.AuxInt = uint8ToAuxInt(2)
 +              v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x8ToM, types.TypeMask)
 +              v1.AddArg(mask)
 +              v0.AddArg3(x, y, v1)
 +              v.AddArg(v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpLessEqualMaskedUint8x16(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      typ := &b.Func.Config.Types
 +      // match: (LessEqualMaskedUint8x16 x y mask)
 +      // result: (VPMOVMToVec8x16 (VPCMPUBMasked128 [2] x y (VPMOVVec8x16ToM <types.TypeMask> mask)))
 +      for {
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VPMOVMToVec8x16)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPCMPUBMasked128, typ.Mask)
 +              v0.AuxInt = uint8ToAuxInt(2)
 +              v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec8x16ToM, types.TypeMask)
 +              v1.AddArg(mask)
 +              v0.AddArg3(x, y, v1)
 +              v.AddArg(v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpLessEqualMaskedUint8x32(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      typ := &b.Func.Config.Types
 +      // match: (LessEqualMaskedUint8x32 x y mask)
 +      // result: (VPMOVMToVec8x32 (VPCMPUBMasked256 [2] x y (VPMOVVec8x32ToM <types.TypeMask> mask)))
 +      for {
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VPMOVMToVec8x32)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPCMPUBMasked256, typ.Mask)
 +              v0.AuxInt = uint8ToAuxInt(2)
 +              v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec8x32ToM, types.TypeMask)
 +              v1.AddArg(mask)
 +              v0.AddArg3(x, y, v1)
 +              v.AddArg(v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpLessEqualMaskedUint8x64(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      typ := &b.Func.Config.Types
 +      // match: (LessEqualMaskedUint8x64 x y mask)
 +      // result: (VPMOVMToVec8x64 (VPCMPUBMasked512 [2] x y (VPMOVVec8x64ToM <types.TypeMask> mask)))
 +      for {
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VPMOVMToVec8x64)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPCMPUBMasked512, typ.Mask)
 +              v0.AuxInt = uint8ToAuxInt(2)
 +              v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec8x64ToM, types.TypeMask)
 +              v1.AddArg(mask)
 +              v0.AddArg3(x, y, v1)
 +              v.AddArg(v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpLessEqualUint16x32(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      typ := &b.Func.Config.Types
 +      // match: (LessEqualUint16x32 x y)
 +      // result: (VPMOVMToVec16x32 (VPCMPUW512 [2] x y))
 +      for {
 +              x := v_0
 +              y := v_1
 +              v.reset(OpAMD64VPMOVMToVec16x32)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPCMPUW512, typ.Mask)
 +              v0.AuxInt = uint8ToAuxInt(2)
 +              v0.AddArg2(x, y)
 +              v.AddArg(v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpLessEqualUint32x16(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      typ := &b.Func.Config.Types
 +      // match: (LessEqualUint32x16 x y)
 +      // result: (VPMOVMToVec32x16 (VPCMPUD512 [2] x y))
 +      for {
 +              x := v_0
 +              y := v_1
 +              v.reset(OpAMD64VPMOVMToVec32x16)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPCMPUD512, typ.Mask)
 +              v0.AuxInt = uint8ToAuxInt(2)
 +              v0.AddArg2(x, y)
 +              v.AddArg(v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpLessEqualUint64x8(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      typ := &b.Func.Config.Types
 +      // match: (LessEqualUint64x8 x y)
 +      // result: (VPMOVMToVec64x8 (VPCMPUQ512 [2] x y))
 +      for {
 +              x := v_0
 +              y := v_1
 +              v.reset(OpAMD64VPMOVMToVec64x8)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPCMPUQ512, typ.Mask)
 +              v0.AuxInt = uint8ToAuxInt(2)
 +              v0.AddArg2(x, y)
 +              v.AddArg(v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpLessEqualUint8x64(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      typ := &b.Func.Config.Types
 +      // match: (LessEqualUint8x64 x y)
 +      // result: (VPMOVMToVec8x64 (VPCMPUB512 [2] x y))
 +      for {
 +              x := v_0
 +              y := v_1
 +              v.reset(OpAMD64VPMOVMToVec8x64)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPCMPUB512, typ.Mask)
 +              v0.AuxInt = uint8ToAuxInt(2)
 +              v0.AddArg2(x, y)
 +              v.AddArg(v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpLessFloat32x16(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      typ := &b.Func.Config.Types
 +      // match: (LessFloat32x16 x y)
 +      // result: (VPMOVMToVec32x16 (VCMPPS512 [1] x y))
 +      for {
 +              x := v_0
 +              y := v_1
 +              v.reset(OpAMD64VPMOVMToVec32x16)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VCMPPS512, typ.Mask)
 +              v0.AuxInt = uint8ToAuxInt(1)
 +              v0.AddArg2(x, y)
 +              v.AddArg(v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpLessFloat32x4(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      // match: (LessFloat32x4 x y)
 +      // result: (VCMPPS128 [1] x y)
 +      for {
 +              x := v_0
 +              y := v_1
 +              v.reset(OpAMD64VCMPPS128)
 +              v.AuxInt = uint8ToAuxInt(1)
 +              v.AddArg2(x, y)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpLessFloat32x8(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      // match: (LessFloat32x8 x y)
 +      // result: (VCMPPS256 [1] x y)
 +      for {
 +              x := v_0
 +              y := v_1
 +              v.reset(OpAMD64VCMPPS256)
 +              v.AuxInt = uint8ToAuxInt(1)
 +              v.AddArg2(x, y)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpLessFloat64x2(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      // match: (LessFloat64x2 x y)
 +      // result: (VCMPPD128 [1] x y)
 +      for {
 +              x := v_0
 +              y := v_1
 +              v.reset(OpAMD64VCMPPD128)
 +              v.AuxInt = uint8ToAuxInt(1)
 +              v.AddArg2(x, y)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpLessFloat64x4(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      // match: (LessFloat64x4 x y)
 +      // result: (VCMPPD256 [1] x y)
 +      for {
 +              x := v_0
 +              y := v_1
 +              v.reset(OpAMD64VCMPPD256)
 +              v.AuxInt = uint8ToAuxInt(1)
 +              v.AddArg2(x, y)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpLessFloat64x8(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      typ := &b.Func.Config.Types
 +      // match: (LessFloat64x8 x y)
 +      // result: (VPMOVMToVec64x8 (VCMPPD512 [1] x y))
 +      for {
 +              x := v_0
 +              y := v_1
 +              v.reset(OpAMD64VPMOVMToVec64x8)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VCMPPD512, typ.Mask)
 +              v0.AuxInt = uint8ToAuxInt(1)
 +              v0.AddArg2(x, y)
 +              v.AddArg(v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpLessInt16x32(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      typ := &b.Func.Config.Types
 +      // match: (LessInt16x32 x y)
 +      // result: (VPMOVMToVec16x32 (VPCMPW512 [1] x y))
 +      for {
 +              x := v_0
 +              y := v_1
 +              v.reset(OpAMD64VPMOVMToVec16x32)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPCMPW512, typ.Mask)
 +              v0.AuxInt = uint8ToAuxInt(1)
 +              v0.AddArg2(x, y)
 +              v.AddArg(v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpLessInt32x16(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      typ := &b.Func.Config.Types
 +      // match: (LessInt32x16 x y)
 +      // result: (VPMOVMToVec32x16 (VPCMPD512 [1] x y))
 +      for {
 +              x := v_0
 +              y := v_1
 +              v.reset(OpAMD64VPMOVMToVec32x16)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPCMPD512, typ.Mask)
 +              v0.AuxInt = uint8ToAuxInt(1)
 +              v0.AddArg2(x, y)
 +              v.AddArg(v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpLessInt64x8(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      typ := &b.Func.Config.Types
 +      // match: (LessInt64x8 x y)
 +      // result: (VPMOVMToVec64x8 (VPCMPQ512 [1] x y))
 +      for {
 +              x := v_0
 +              y := v_1
 +              v.reset(OpAMD64VPMOVMToVec64x8)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPCMPQ512, typ.Mask)
 +              v0.AuxInt = uint8ToAuxInt(1)
 +              v0.AddArg2(x, y)
 +              v.AddArg(v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpLessInt8x64(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      typ := &b.Func.Config.Types
 +      // match: (LessInt8x64 x y)
 +      // result: (VPMOVMToVec8x64 (VPCMPB512 [1] x y))
 +      for {
 +              x := v_0
 +              y := v_1
 +              v.reset(OpAMD64VPMOVMToVec8x64)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPCMPB512, typ.Mask)
 +              v0.AuxInt = uint8ToAuxInt(1)
 +              v0.AddArg2(x, y)
 +              v.AddArg(v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpLessMaskedFloat32x16(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      typ := &b.Func.Config.Types
 +      // match: (LessMaskedFloat32x16 x y mask)
 +      // result: (VPMOVMToVec32x16 (VCMPPSMasked512 [1] x y (VPMOVVec32x16ToM <types.TypeMask> mask)))
 +      for {
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VPMOVMToVec32x16)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VCMPPSMasked512, typ.Mask)
 +              v0.AuxInt = uint8ToAuxInt(1)
 +              v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x16ToM, types.TypeMask)
 +              v1.AddArg(mask)
 +              v0.AddArg3(x, y, v1)
 +              v.AddArg(v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpLessMaskedFloat32x4(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      typ := &b.Func.Config.Types
 +      // match: (LessMaskedFloat32x4 x y mask)
 +      // result: (VPMOVMToVec32x4 (VCMPPSMasked128 [1] x y (VPMOVVec32x4ToM <types.TypeMask> mask)))
 +      for {
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VPMOVMToVec32x4)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VCMPPSMasked128, typ.Mask)
 +              v0.AuxInt = uint8ToAuxInt(1)
 +              v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x4ToM, types.TypeMask)
 +              v1.AddArg(mask)
 +              v0.AddArg3(x, y, v1)
 +              v.AddArg(v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpLessMaskedFloat32x8(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      typ := &b.Func.Config.Types
 +      // match: (LessMaskedFloat32x8 x y mask)
 +      // result: (VPMOVMToVec32x8 (VCMPPSMasked256 [1] x y (VPMOVVec32x8ToM <types.TypeMask> mask)))
 +      for {
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VPMOVMToVec32x8)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VCMPPSMasked256, typ.Mask)
 +              v0.AuxInt = uint8ToAuxInt(1)
 +              v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x8ToM, types.TypeMask)
 +              v1.AddArg(mask)
 +              v0.AddArg3(x, y, v1)
 +              v.AddArg(v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpLessMaskedFloat64x2(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      typ := &b.Func.Config.Types
 +      // match: (LessMaskedFloat64x2 x y mask)
 +      // result: (VPMOVMToVec64x2 (VCMPPDMasked128 [1] x y (VPMOVVec64x2ToM <types.TypeMask> mask)))
 +      for {
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VPMOVMToVec64x2)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VCMPPDMasked128, typ.Mask)
 +              v0.AuxInt = uint8ToAuxInt(1)
 +              v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x2ToM, types.TypeMask)
 +              v1.AddArg(mask)
 +              v0.AddArg3(x, y, v1)
 +              v.AddArg(v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpLessMaskedFloat64x4(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      typ := &b.Func.Config.Types
 +      // match: (LessMaskedFloat64x4 x y mask)
 +      // result: (VPMOVMToVec64x4 (VCMPPDMasked256 [1] x y (VPMOVVec64x4ToM <types.TypeMask> mask)))
 +      for {
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VPMOVMToVec64x4)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VCMPPDMasked256, typ.Mask)
 +              v0.AuxInt = uint8ToAuxInt(1)
 +              v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x4ToM, types.TypeMask)
 +              v1.AddArg(mask)
 +              v0.AddArg3(x, y, v1)
 +              v.AddArg(v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpLessMaskedFloat64x8(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      typ := &b.Func.Config.Types
 +      // match: (LessMaskedFloat64x8 x y mask)
 +      // result: (VPMOVMToVec64x8 (VCMPPDMasked512 [1] x y (VPMOVVec64x8ToM <types.TypeMask> mask)))
 +      for {
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VPMOVMToVec64x8)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VCMPPDMasked512, typ.Mask)
 +              v0.AuxInt = uint8ToAuxInt(1)
 +              v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x8ToM, types.TypeMask)
 +              v1.AddArg(mask)
 +              v0.AddArg3(x, y, v1)
 +              v.AddArg(v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpLessMaskedInt16x16(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      typ := &b.Func.Config.Types
 +      // match: (LessMaskedInt16x16 x y mask)
 +      // result: (VPMOVMToVec16x16 (VPCMPWMasked256 [1] x y (VPMOVVec16x16ToM <types.TypeMask> mask)))
 +      for {
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VPMOVMToVec16x16)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPCMPWMasked256, typ.Mask)
 +              v0.AuxInt = uint8ToAuxInt(1)
 +              v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x16ToM, types.TypeMask)
 +              v1.AddArg(mask)
 +              v0.AddArg3(x, y, v1)
 +              v.AddArg(v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpLessMaskedInt16x32(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      typ := &b.Func.Config.Types
 +      // match: (LessMaskedInt16x32 x y mask)
 +      // result: (VPMOVMToVec16x32 (VPCMPWMasked512 [1] x y (VPMOVVec16x32ToM <types.TypeMask> mask)))
 +      for {
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VPMOVMToVec16x32)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPCMPWMasked512, typ.Mask)
 +              v0.AuxInt = uint8ToAuxInt(1)
 +              v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x32ToM, types.TypeMask)
 +              v1.AddArg(mask)
 +              v0.AddArg3(x, y, v1)
 +              v.AddArg(v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpLessMaskedInt16x8(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      typ := &b.Func.Config.Types
 +      // match: (LessMaskedInt16x8 x y mask)
 +      // result: (VPMOVMToVec16x8 (VPCMPWMasked128 [1] x y (VPMOVVec16x8ToM <types.TypeMask> mask)))
 +      for {
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VPMOVMToVec16x8)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPCMPWMasked128, typ.Mask)
 +              v0.AuxInt = uint8ToAuxInt(1)
 +              v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x8ToM, types.TypeMask)
 +              v1.AddArg(mask)
 +              v0.AddArg3(x, y, v1)
 +              v.AddArg(v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpLessMaskedInt32x16(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      typ := &b.Func.Config.Types
 +      // match: (LessMaskedInt32x16 x y mask)
 +      // result: (VPMOVMToVec32x16 (VPCMPDMasked512 [1] x y (VPMOVVec32x16ToM <types.TypeMask> mask)))
 +      for {
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VPMOVMToVec32x16)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPCMPDMasked512, typ.Mask)
 +              v0.AuxInt = uint8ToAuxInt(1)
 +              v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x16ToM, types.TypeMask)
 +              v1.AddArg(mask)
 +              v0.AddArg3(x, y, v1)
 +              v.AddArg(v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpLessMaskedInt32x4(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      typ := &b.Func.Config.Types
 +      // match: (LessMaskedInt32x4 x y mask)
 +      // result: (VPMOVMToVec32x4 (VPCMPDMasked128 [1] x y (VPMOVVec32x4ToM <types.TypeMask> mask)))
 +      for {
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VPMOVMToVec32x4)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPCMPDMasked128, typ.Mask)
 +              v0.AuxInt = uint8ToAuxInt(1)
 +              v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x4ToM, types.TypeMask)
 +              v1.AddArg(mask)
 +              v0.AddArg3(x, y, v1)
 +              v.AddArg(v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpLessMaskedInt32x8(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      typ := &b.Func.Config.Types
 +      // match: (LessMaskedInt32x8 x y mask)
 +      // result: (VPMOVMToVec32x8 (VPCMPDMasked256 [1] x y (VPMOVVec32x8ToM <types.TypeMask> mask)))
 +      for {
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VPMOVMToVec32x8)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPCMPDMasked256, typ.Mask)
 +              v0.AuxInt = uint8ToAuxInt(1)
 +              v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x8ToM, types.TypeMask)
 +              v1.AddArg(mask)
 +              v0.AddArg3(x, y, v1)
 +              v.AddArg(v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpLessMaskedInt64x2(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      typ := &b.Func.Config.Types
 +      // match: (LessMaskedInt64x2 x y mask)
 +      // result: (VPMOVMToVec64x2 (VPCMPQMasked128 [1] x y (VPMOVVec64x2ToM <types.TypeMask> mask)))
 +      for {
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VPMOVMToVec64x2)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPCMPQMasked128, typ.Mask)
 +              v0.AuxInt = uint8ToAuxInt(1)
 +              v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x2ToM, types.TypeMask)
 +              v1.AddArg(mask)
 +              v0.AddArg3(x, y, v1)
 +              v.AddArg(v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpLessMaskedInt64x4(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      typ := &b.Func.Config.Types
 +      // match: (LessMaskedInt64x4 x y mask)
 +      // result: (VPMOVMToVec64x4 (VPCMPQMasked256 [1] x y (VPMOVVec64x4ToM <types.TypeMask> mask)))
 +      for {
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VPMOVMToVec64x4)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPCMPQMasked256, typ.Mask)
 +              v0.AuxInt = uint8ToAuxInt(1)
 +              v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x4ToM, types.TypeMask)
 +              v1.AddArg(mask)
 +              v0.AddArg3(x, y, v1)
 +              v.AddArg(v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpLessMaskedInt64x8(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      typ := &b.Func.Config.Types
 +      // match: (LessMaskedInt64x8 x y mask)
 +      // result: (VPMOVMToVec64x8 (VPCMPQMasked512 [1] x y (VPMOVVec64x8ToM <types.TypeMask> mask)))
 +      for {
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VPMOVMToVec64x8)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPCMPQMasked512, typ.Mask)
 +              v0.AuxInt = uint8ToAuxInt(1)
 +              v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x8ToM, types.TypeMask)
 +              v1.AddArg(mask)
 +              v0.AddArg3(x, y, v1)
 +              v.AddArg(v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpLessMaskedInt8x16(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      typ := &b.Func.Config.Types
 +      // match: (LessMaskedInt8x16 x y mask)
 +      // result: (VPMOVMToVec8x16 (VPCMPBMasked128 [1] x y (VPMOVVec8x16ToM <types.TypeMask> mask)))
 +      for {
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VPMOVMToVec8x16)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPCMPBMasked128, typ.Mask)
 +              v0.AuxInt = uint8ToAuxInt(1)
 +              v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec8x16ToM, types.TypeMask)
 +              v1.AddArg(mask)
 +              v0.AddArg3(x, y, v1)
 +              v.AddArg(v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpLessMaskedInt8x32(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      typ := &b.Func.Config.Types
 +      // match: (LessMaskedInt8x32 x y mask)
 +      // result: (VPMOVMToVec8x32 (VPCMPBMasked256 [1] x y (VPMOVVec8x32ToM <types.TypeMask> mask)))
 +      for {
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VPMOVMToVec8x32)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPCMPBMasked256, typ.Mask)
 +              v0.AuxInt = uint8ToAuxInt(1)
 +              v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec8x32ToM, types.TypeMask)
 +              v1.AddArg(mask)
 +              v0.AddArg3(x, y, v1)
 +              v.AddArg(v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpLessMaskedInt8x64(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      typ := &b.Func.Config.Types
 +      // match: (LessMaskedInt8x64 x y mask)
 +      // result: (VPMOVMToVec8x64 (VPCMPBMasked512 [1] x y (VPMOVVec8x64ToM <types.TypeMask> mask)))
 +      for {
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VPMOVMToVec8x64)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPCMPBMasked512, typ.Mask)
 +              v0.AuxInt = uint8ToAuxInt(1)
 +              v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec8x64ToM, types.TypeMask)
 +              v1.AddArg(mask)
 +              v0.AddArg3(x, y, v1)
 +              v.AddArg(v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpLessMaskedUint16x16(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      typ := &b.Func.Config.Types
 +      // match: (LessMaskedUint16x16 x y mask)
 +      // result: (VPMOVMToVec16x16 (VPCMPUWMasked256 [1] x y (VPMOVVec16x16ToM <types.TypeMask> mask)))
 +      for {
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VPMOVMToVec16x16)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPCMPUWMasked256, typ.Mask)
 +              v0.AuxInt = uint8ToAuxInt(1)
 +              v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x16ToM, types.TypeMask)
 +              v1.AddArg(mask)
 +              v0.AddArg3(x, y, v1)
 +              v.AddArg(v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpLessMaskedUint16x32(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      typ := &b.Func.Config.Types
 +      // match: (LessMaskedUint16x32 x y mask)
 +      // result: (VPMOVMToVec16x32 (VPCMPUWMasked512 [1] x y (VPMOVVec16x32ToM <types.TypeMask> mask)))
 +      for {
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VPMOVMToVec16x32)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPCMPUWMasked512, typ.Mask)
 +              v0.AuxInt = uint8ToAuxInt(1)
 +              v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x32ToM, types.TypeMask)
 +              v1.AddArg(mask)
 +              v0.AddArg3(x, y, v1)
 +              v.AddArg(v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpLessMaskedUint16x8(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      typ := &b.Func.Config.Types
 +      // match: (LessMaskedUint16x8 x y mask)
 +      // result: (VPMOVMToVec16x8 (VPCMPUWMasked128 [1] x y (VPMOVVec16x8ToM <types.TypeMask> mask)))
 +      for {
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VPMOVMToVec16x8)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPCMPUWMasked128, typ.Mask)
 +              v0.AuxInt = uint8ToAuxInt(1)
 +              v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x8ToM, types.TypeMask)
 +              v1.AddArg(mask)
 +              v0.AddArg3(x, y, v1)
 +              v.AddArg(v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpLessMaskedUint32x16(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      typ := &b.Func.Config.Types
 +      // match: (LessMaskedUint32x16 x y mask)
 +      // result: (VPMOVMToVec32x16 (VPCMPUDMasked512 [1] x y (VPMOVVec32x16ToM <types.TypeMask> mask)))
 +      for {
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VPMOVMToVec32x16)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPCMPUDMasked512, typ.Mask)
 +              v0.AuxInt = uint8ToAuxInt(1)
 +              v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x16ToM, types.TypeMask)
 +              v1.AddArg(mask)
 +              v0.AddArg3(x, y, v1)
 +              v.AddArg(v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpLessMaskedUint32x4(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      typ := &b.Func.Config.Types
 +      // match: (LessMaskedUint32x4 x y mask)
 +      // result: (VPMOVMToVec32x4 (VPCMPUDMasked128 [1] x y (VPMOVVec32x4ToM <types.TypeMask> mask)))
 +      for {
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VPMOVMToVec32x4)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPCMPUDMasked128, typ.Mask)
 +              v0.AuxInt = uint8ToAuxInt(1)
 +              v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x4ToM, types.TypeMask)
 +              v1.AddArg(mask)
 +              v0.AddArg3(x, y, v1)
 +              v.AddArg(v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpLessMaskedUint32x8(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      typ := &b.Func.Config.Types
 +      // match: (LessMaskedUint32x8 x y mask)
 +      // result: (VPMOVMToVec32x8 (VPCMPUDMasked256 [1] x y (VPMOVVec32x8ToM <types.TypeMask> mask)))
 +      for {
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VPMOVMToVec32x8)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPCMPUDMasked256, typ.Mask)
 +              v0.AuxInt = uint8ToAuxInt(1)
 +              v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x8ToM, types.TypeMask)
 +              v1.AddArg(mask)
 +              v0.AddArg3(x, y, v1)
 +              v.AddArg(v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpLessMaskedUint64x2(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      typ := &b.Func.Config.Types
 +      // match: (LessMaskedUint64x2 x y mask)
 +      // result: (VPMOVMToVec64x2 (VPCMPUQMasked128 [1] x y (VPMOVVec64x2ToM <types.TypeMask> mask)))
 +      for {
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VPMOVMToVec64x2)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPCMPUQMasked128, typ.Mask)
 +              v0.AuxInt = uint8ToAuxInt(1)
 +              v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x2ToM, types.TypeMask)
 +              v1.AddArg(mask)
 +              v0.AddArg3(x, y, v1)
 +              v.AddArg(v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpLessMaskedUint64x4(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      typ := &b.Func.Config.Types
 +      // match: (LessMaskedUint64x4 x y mask)
 +      // result: (VPMOVMToVec64x4 (VPCMPUQMasked256 [1] x y (VPMOVVec64x4ToM <types.TypeMask> mask)))
 +      for {
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VPMOVMToVec64x4)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPCMPUQMasked256, typ.Mask)
 +              v0.AuxInt = uint8ToAuxInt(1)
 +              v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x4ToM, types.TypeMask)
 +              v1.AddArg(mask)
 +              v0.AddArg3(x, y, v1)
 +              v.AddArg(v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpLessMaskedUint64x8(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      typ := &b.Func.Config.Types
 +      // match: (LessMaskedUint64x8 x y mask)
 +      // result: (VPMOVMToVec64x8 (VPCMPUQMasked512 [1] x y (VPMOVVec64x8ToM <types.TypeMask> mask)))
 +      for {
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VPMOVMToVec64x8)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPCMPUQMasked512, typ.Mask)
 +              v0.AuxInt = uint8ToAuxInt(1)
 +              v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x8ToM, types.TypeMask)
 +              v1.AddArg(mask)
 +              v0.AddArg3(x, y, v1)
 +              v.AddArg(v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpLessMaskedUint8x16(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      typ := &b.Func.Config.Types
 +      // match: (LessMaskedUint8x16 x y mask)
 +      // result: (VPMOVMToVec8x16 (VPCMPUBMasked128 [1] x y (VPMOVVec8x16ToM <types.TypeMask> mask)))
 +      for {
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VPMOVMToVec8x16)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPCMPUBMasked128, typ.Mask)
 +              v0.AuxInt = uint8ToAuxInt(1)
 +              v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec8x16ToM, types.TypeMask)
 +              v1.AddArg(mask)
 +              v0.AddArg3(x, y, v1)
 +              v.AddArg(v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpLessMaskedUint8x32(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      typ := &b.Func.Config.Types
 +      // match: (LessMaskedUint8x32 x y mask)
 +      // result: (VPMOVMToVec8x32 (VPCMPUBMasked256 [1] x y (VPMOVVec8x32ToM <types.TypeMask> mask)))
 +      for {
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VPMOVMToVec8x32)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPCMPUBMasked256, typ.Mask)
 +              v0.AuxInt = uint8ToAuxInt(1)
 +              v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec8x32ToM, types.TypeMask)
 +              v1.AddArg(mask)
 +              v0.AddArg3(x, y, v1)
 +              v.AddArg(v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpLessMaskedUint8x64(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      typ := &b.Func.Config.Types
 +      // match: (LessMaskedUint8x64 x y mask)
 +      // result: (VPMOVMToVec8x64 (VPCMPUBMasked512 [1] x y (VPMOVVec8x64ToM <types.TypeMask> mask)))
 +      for {
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VPMOVMToVec8x64)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPCMPUBMasked512, typ.Mask)
 +              v0.AuxInt = uint8ToAuxInt(1)
 +              v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec8x64ToM, types.TypeMask)
 +              v1.AddArg(mask)
 +              v0.AddArg3(x, y, v1)
 +              v.AddArg(v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpLessUint16x32(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      typ := &b.Func.Config.Types
 +      // match: (LessUint16x32 x y)
 +      // result: (VPMOVMToVec16x32 (VPCMPUW512 [1] x y))
 +      for {
 +              x := v_0
 +              y := v_1
 +              v.reset(OpAMD64VPMOVMToVec16x32)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPCMPUW512, typ.Mask)
 +              v0.AuxInt = uint8ToAuxInt(1)
 +              v0.AddArg2(x, y)
 +              v.AddArg(v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpLessUint32x16(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      typ := &b.Func.Config.Types
 +      // match: (LessUint32x16 x y)
 +      // result: (VPMOVMToVec32x16 (VPCMPUD512 [1] x y))
 +      for {
 +              x := v_0
 +              y := v_1
 +              v.reset(OpAMD64VPMOVMToVec32x16)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPCMPUD512, typ.Mask)
 +              v0.AuxInt = uint8ToAuxInt(1)
 +              v0.AddArg2(x, y)
 +              v.AddArg(v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpLessUint64x8(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      typ := &b.Func.Config.Types
 +      // match: (LessUint64x8 x y)
 +      // result: (VPMOVMToVec64x8 (VPCMPUQ512 [1] x y))
 +      for {
 +              x := v_0
 +              y := v_1
 +              v.reset(OpAMD64VPMOVMToVec64x8)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPCMPUQ512, typ.Mask)
 +              v0.AuxInt = uint8ToAuxInt(1)
 +              v0.AddArg2(x, y)
 +              v.AddArg(v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpLessUint8x64(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      typ := &b.Func.Config.Types
 +      // match: (LessUint8x64 x y)
 +      // result: (VPMOVMToVec8x64 (VPCMPUB512 [1] x y))
 +      for {
 +              x := v_0
 +              y := v_1
 +              v.reset(OpAMD64VPMOVMToVec8x64)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPCMPUB512, typ.Mask)
 +              v0.AuxInt = uint8ToAuxInt(1)
 +              v0.AddArg2(x, y)
 +              v.AddArg(v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpLoad(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      // match: (Load <t> ptr mem)
 +      // cond: (is64BitInt(t) || isPtr(t))
 +      // result: (MOVQload ptr mem)
 +      for {
 +              t := v.Type
 +              ptr := v_0
 +              mem := v_1
 +              if !(is64BitInt(t) || isPtr(t)) {
 +                      break
 +              }
 +              v.reset(OpAMD64MOVQload)
 +              v.AddArg2(ptr, mem)
 +              return true
 +      }
 +      // match: (Load <t> ptr mem)
 +      // cond: is32BitInt(t)
 +      // result: (MOVLload ptr mem)
 +      for {
 +              t := v.Type
 +              ptr := v_0
 +              mem := v_1
 +              if !(is32BitInt(t)) {
 +                      break
 +              }
 +              v.reset(OpAMD64MOVLload)
 +              v.AddArg2(ptr, mem)
 +              return true
 +      }
 +      // match: (Load <t> ptr mem)
 +      // cond: is16BitInt(t)
 +      // result: (MOVWload ptr mem)
 +      for {
 +              t := v.Type
 +              ptr := v_0
 +              mem := v_1
 +              if !(is16BitInt(t)) {
 +                      break
 +              }
 +              v.reset(OpAMD64MOVWload)
 +              v.AddArg2(ptr, mem)
 +              return true
 +      }
 +      // match: (Load <t> ptr mem)
 +      // cond: (t.IsBoolean() || is8BitInt(t))
 +      // result: (MOVBload ptr mem)
 +      for {
 +              t := v.Type
 +              ptr := v_0
 +              mem := v_1
 +              if !(t.IsBoolean() || is8BitInt(t)) {
 +                      break
 +              }
 +              v.reset(OpAMD64MOVBload)
 +              v.AddArg2(ptr, mem)
 +              return true
 +      }
 +      // match: (Load <t> ptr mem)
 +      // cond: is32BitFloat(t)
 +      // result: (MOVSSload ptr mem)
 +      for {
 +              t := v.Type
 +              ptr := v_0
 +              mem := v_1
 +              if !(is32BitFloat(t)) {
 +                      break
 +              }
 +              v.reset(OpAMD64MOVSSload)
 +              v.AddArg2(ptr, mem)
 +              return true
 +      }
 +      // match: (Load <t> ptr mem)
 +      // cond: is64BitFloat(t)
 +      // result: (MOVSDload ptr mem)
 +      for {
 +              t := v.Type
 +              ptr := v_0
 +              mem := v_1
 +              if !(is64BitFloat(t)) {
 +                      break
 +              }
 +              v.reset(OpAMD64MOVSDload)
 +              v.AddArg2(ptr, mem)
 +              return true
 +      }
 +      // match: (Load <t> ptr mem)
 +      // cond: t.Size() == 16
 +      // result: (VMOVDQUload128 ptr mem)
 +      for {
 +              t := v.Type
 +              ptr := v_0
 +              mem := v_1
 +              if !(t.Size() == 16) {
 +                      break
 +              }
 +              v.reset(OpAMD64VMOVDQUload128)
 +              v.AddArg2(ptr, mem)
 +              return true
 +      }
 +      // match: (Load <t> ptr mem)
 +      // cond: t.Size() == 32
 +      // result: (VMOVDQUload256 ptr mem)
 +      for {
 +              t := v.Type
 +              ptr := v_0
 +              mem := v_1
 +              if !(t.Size() == 32) {
 +                      break
 +              }
 +              v.reset(OpAMD64VMOVDQUload256)
 +              v.AddArg2(ptr, mem)
 +              return true
 +      }
 +      // match: (Load <t> ptr mem)
 +      // cond: t.Size() == 64
 +      // result: (VMOVDQUload512 ptr mem)
 +      for {
 +              t := v.Type
 +              ptr := v_0
 +              mem := v_1
 +              if !(t.Size() == 64) {
 +                      break
 +              }
 +              v.reset(OpAMD64VMOVDQUload512)
 +              v.AddArg2(ptr, mem)
 +              return true
 +      }
 +      return false
 +}
 +func rewriteValueAMD64_OpLoadMask16x16(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (LoadMask16x16 <t> ptr mem)
 +      // result: (VPMOVMToVec16x16 <types.TypeVec256> (KMOVQload <t> ptr mem))
 +      for {
 +              t := v.Type
 +              ptr := v_0
 +              mem := v_1
 +              v.reset(OpAMD64VPMOVMToVec16x16)
 +              v.Type = types.TypeVec256
 +              v0 := b.NewValue0(v.Pos, OpAMD64KMOVQload, t)
 +              v0.AddArg2(ptr, mem)
 +              v.AddArg(v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpLoadMask16x32(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (LoadMask16x32 <t> ptr mem)
 +      // result: (VPMOVMToVec16x32 <types.TypeVec512> (KMOVQload <t> ptr mem))
 +      for {
 +              t := v.Type
 +              ptr := v_0
 +              mem := v_1
 +              v.reset(OpAMD64VPMOVMToVec16x32)
 +              v.Type = types.TypeVec512
 +              v0 := b.NewValue0(v.Pos, OpAMD64KMOVQload, t)
 +              v0.AddArg2(ptr, mem)
 +              v.AddArg(v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpLoadMask16x8(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (LoadMask16x8 <t> ptr mem)
 +      // result: (VPMOVMToVec16x8 <types.TypeVec128> (KMOVQload <t> ptr mem))
 +      for {
 +              t := v.Type
 +              ptr := v_0
 +              mem := v_1
 +              v.reset(OpAMD64VPMOVMToVec16x8)
 +              v.Type = types.TypeVec128
 +              v0 := b.NewValue0(v.Pos, OpAMD64KMOVQload, t)
 +              v0.AddArg2(ptr, mem)
 +              v.AddArg(v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpLoadMask32x16(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (LoadMask32x16 <t> ptr mem)
 +      // result: (VPMOVMToVec32x16 <types.TypeVec512> (KMOVQload <t> ptr mem))
 +      for {
 +              t := v.Type
 +              ptr := v_0
 +              mem := v_1
 +              v.reset(OpAMD64VPMOVMToVec32x16)
 +              v.Type = types.TypeVec512
 +              v0 := b.NewValue0(v.Pos, OpAMD64KMOVQload, t)
 +              v0.AddArg2(ptr, mem)
 +              v.AddArg(v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpLoadMask32x4(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (LoadMask32x4 <t> ptr mem)
 +      // result: (VPMOVMToVec32x4 <types.TypeVec128> (KMOVQload <t> ptr mem))
 +      for {
 +              t := v.Type
 +              ptr := v_0
 +              mem := v_1
 +              v.reset(OpAMD64VPMOVMToVec32x4)
 +              v.Type = types.TypeVec128
 +              v0 := b.NewValue0(v.Pos, OpAMD64KMOVQload, t)
 +              v0.AddArg2(ptr, mem)
 +              v.AddArg(v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpLoadMask32x8(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (LoadMask32x8 <t> ptr mem)
 +      // result: (VPMOVMToVec32x8 <types.TypeVec256> (KMOVQload <t> ptr mem))
 +      for {
 +              t := v.Type
 +              ptr := v_0
 +              mem := v_1
 +              v.reset(OpAMD64VPMOVMToVec32x8)
 +              v.Type = types.TypeVec256
 +              v0 := b.NewValue0(v.Pos, OpAMD64KMOVQload, t)
 +              v0.AddArg2(ptr, mem)
 +              v.AddArg(v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpLoadMask64x2(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (LoadMask64x2 <t> ptr mem)
 +      // result: (VPMOVMToVec64x2 <types.TypeVec128> (KMOVQload <t> ptr mem))
 +      for {
 +              t := v.Type
 +              ptr := v_0
 +              mem := v_1
 +              v.reset(OpAMD64VPMOVMToVec64x2)
 +              v.Type = types.TypeVec128
 +              v0 := b.NewValue0(v.Pos, OpAMD64KMOVQload, t)
 +              v0.AddArg2(ptr, mem)
 +              v.AddArg(v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpLoadMask64x4(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (LoadMask64x4 <t> ptr mem)
 +      // result: (VPMOVMToVec64x4 <types.TypeVec256> (KMOVQload <t> ptr mem))
 +      for {
 +              t := v.Type
 +              ptr := v_0
 +              mem := v_1
 +              v.reset(OpAMD64VPMOVMToVec64x4)
 +              v.Type = types.TypeVec256
 +              v0 := b.NewValue0(v.Pos, OpAMD64KMOVQload, t)
 +              v0.AddArg2(ptr, mem)
 +              v.AddArg(v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpLoadMask64x8(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (LoadMask64x8 <t> ptr mem)
 +      // result: (VPMOVMToVec64x8 <types.TypeVec512> (KMOVQload <t> ptr mem))
 +      for {
 +              t := v.Type
 +              ptr := v_0
 +              mem := v_1
 +              v.reset(OpAMD64VPMOVMToVec64x8)
 +              v.Type = types.TypeVec512
 +              v0 := b.NewValue0(v.Pos, OpAMD64KMOVQload, t)
 +              v0.AddArg2(ptr, mem)
 +              v.AddArg(v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpLoadMask8x16(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (LoadMask8x16 <t> ptr mem)
 +      // result: (VPMOVMToVec8x16 <types.TypeVec128> (KMOVQload <t> ptr mem))
 +      for {
 +              t := v.Type
 +              ptr := v_0
 +              mem := v_1
 +              v.reset(OpAMD64VPMOVMToVec8x16)
 +              v.Type = types.TypeVec128
 +              v0 := b.NewValue0(v.Pos, OpAMD64KMOVQload, t)
 +              v0.AddArg2(ptr, mem)
 +              v.AddArg(v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpLoadMask8x32(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (LoadMask8x32 <t> ptr mem)
 +      // result: (VPMOVMToVec8x32 <types.TypeVec256> (KMOVQload <t> ptr mem))
 +      for {
 +              t := v.Type
 +              ptr := v_0
 +              mem := v_1
 +              v.reset(OpAMD64VPMOVMToVec8x32)
 +              v.Type = types.TypeVec256
 +              v0 := b.NewValue0(v.Pos, OpAMD64KMOVQload, t)
 +              v0.AddArg2(ptr, mem)
 +              v.AddArg(v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpLoadMask8x64(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (LoadMask8x64 <t> ptr mem)
 +      // result: (VPMOVMToVec8x64 <types.TypeVec512> (KMOVQload <t> ptr mem))
 +      for {
 +              t := v.Type
 +              ptr := v_0
 +              mem := v_1
 +              v.reset(OpAMD64VPMOVMToVec8x64)
 +              v.Type = types.TypeVec512
 +              v0 := b.NewValue0(v.Pos, OpAMD64KMOVQload, t)
 +              v0.AddArg2(ptr, mem)
 +              v.AddArg(v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpLoadMasked16(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (LoadMasked16 <t> ptr mask mem)
 +      // cond: t.Size() == 64
 +      // result: (VPMASK16load512 ptr (VPMOVVec16x32ToM <types.TypeMask> mask) mem)
 +      for {
 +              t := v.Type
 +              ptr := v_0
 +              mask := v_1
 +              mem := v_2
 +              if !(t.Size() == 64) {
 +                      break
 +              }
 +              v.reset(OpAMD64VPMASK16load512)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x32ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg3(ptr, v0, mem)
 +              return true
 +      }
 +      return false
 +}
 +func rewriteValueAMD64_OpLoadMasked32(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (LoadMasked32 <t> ptr mask mem)
 +      // cond: t.Size() == 16
 +      // result: (VPMASK32load128 ptr mask mem)
 +      for {
 +              t := v.Type
 +              ptr := v_0
 +              mask := v_1
 +              mem := v_2
 +              if !(t.Size() == 16) {
 +                      break
 +              }
 +              v.reset(OpAMD64VPMASK32load128)
 +              v.AddArg3(ptr, mask, mem)
 +              return true
 +      }
 +      // match: (LoadMasked32 <t> ptr mask mem)
 +      // cond: t.Size() == 32
 +      // result: (VPMASK32load256 ptr mask mem)
 +      for {
 +              t := v.Type
 +              ptr := v_0
 +              mask := v_1
 +              mem := v_2
 +              if !(t.Size() == 32) {
 +                      break
 +              }
 +              v.reset(OpAMD64VPMASK32load256)
 +              v.AddArg3(ptr, mask, mem)
 +              return true
 +      }
 +      // match: (LoadMasked32 <t> ptr mask mem)
 +      // cond: t.Size() == 64
 +      // result: (VPMASK32load512 ptr (VPMOVVec32x16ToM <types.TypeMask> mask) mem)
 +      for {
 +              t := v.Type
 +              ptr := v_0
 +              mask := v_1
 +              mem := v_2
 +              if !(t.Size() == 64) {
 +                      break
 +              }
 +              v.reset(OpAMD64VPMASK32load512)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x16ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg3(ptr, v0, mem)
 +              return true
 +      }
 +      return false
 +}
 +func rewriteValueAMD64_OpLoadMasked64(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (LoadMasked64 <t> ptr mask mem)
 +      // cond: t.Size() == 16
 +      // result: (VPMASK64load128 ptr mask mem)
 +      for {
 +              t := v.Type
 +              ptr := v_0
 +              mask := v_1
 +              mem := v_2
 +              if !(t.Size() == 16) {
 +                      break
 +              }
 +              v.reset(OpAMD64VPMASK64load128)
 +              v.AddArg3(ptr, mask, mem)
 +              return true
 +      }
 +      // match: (LoadMasked64 <t> ptr mask mem)
 +      // cond: t.Size() == 32
 +      // result: (VPMASK64load256 ptr mask mem)
 +      for {
 +              t := v.Type
 +              ptr := v_0
 +              mask := v_1
 +              mem := v_2
 +              if !(t.Size() == 32) {
 +                      break
 +              }
 +              v.reset(OpAMD64VPMASK64load256)
 +              v.AddArg3(ptr, mask, mem)
 +              return true
 +      }
 +      // match: (LoadMasked64 <t> ptr mask mem)
 +      // cond: t.Size() == 64
 +      // result: (VPMASK64load512 ptr (VPMOVVec64x8ToM <types.TypeMask> mask) mem)
 +      for {
 +              t := v.Type
 +              ptr := v_0
 +              mask := v_1
 +              mem := v_2
 +              if !(t.Size() == 64) {
 +                      break
 +              }
 +              v.reset(OpAMD64VPMASK64load512)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x8ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg3(ptr, v0, mem)
 +              return true
 +      }
 +      return false
 +}
 +func rewriteValueAMD64_OpLoadMasked8(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (LoadMasked8 <t> ptr mask mem)
 +      // cond: t.Size() == 64
 +      // result: (VPMASK8load512 ptr (VPMOVVec8x64ToM <types.TypeMask> mask) mem)
 +      for {
 +              t := v.Type
 +              ptr := v_0
 +              mask := v_1
 +              mem := v_2
 +              if !(t.Size() == 64) {
 +                      break
 +              }
 +              v.reset(OpAMD64VPMASK8load512)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec8x64ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg3(ptr, v0, mem)
 +              return true
 +      }
 +      return false
 +}
 +func rewriteValueAMD64_OpLocalAddr(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      typ := &b.Func.Config.Types
 +      // match: (LocalAddr <t> {sym} base mem)
 +      // cond: t.Elem().HasPointers()
 +      // result: (LEAQ {sym} (SPanchored base mem))
 +      for {
 +              t := v.Type
 +              sym := auxToSym(v.Aux)
 +              base := v_0
 +              mem := v_1
 +              if !(t.Elem().HasPointers()) {
 +                      break
 +              }
 +              v.reset(OpAMD64LEAQ)
 +              v.Aux = symToAux(sym)
 +              v0 := b.NewValue0(v.Pos, OpSPanchored, typ.Uintptr)
 +              v0.AddArg2(base, mem)
 +              v.AddArg(v0)
 +              return true
 +      }
 +      // match: (LocalAddr <t> {sym} base _)
 +      // cond: !t.Elem().HasPointers()
 +      // result: (LEAQ {sym} base)
 +      for {
 +              t := v.Type
 +              sym := auxToSym(v.Aux)
 +              base := v_0
 +              if !(!t.Elem().HasPointers()) {
 +                      break
 +              }
 +              v.reset(OpAMD64LEAQ)
 +              v.Aux = symToAux(sym)
 +              v.AddArg(base)
 +              return true
 +      }
 +      return false
 +}
 +func rewriteValueAMD64_OpLsh16x16(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (Lsh16x16 <t> x y)
 +      // cond: !shiftIsBounded(v)
 +      // result: (ANDL (SHLL <t> x y) (SBBLcarrymask <t> (CMPWconst y [32])))
 +      for {
 +              t := v.Type
 +              x := v_0
 +              y := v_1
 +              if !(!shiftIsBounded(v)) {
 +                      break
 +              }
 +              v.reset(OpAMD64ANDL)
 +              v0 := b.NewValue0(v.Pos, OpAMD64SHLL, t)
 +              v0.AddArg2(x, y)
 +              v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t)
 +              v2 := b.NewValue0(v.Pos, OpAMD64CMPWconst, types.TypeFlags)
 +              v2.AuxInt = int16ToAuxInt(32)
 +              v2.AddArg(y)
 +              v1.AddArg(v2)
 +              v.AddArg2(v0, v1)
 +              return true
 +      }
 +      // match: (Lsh16x16 x y)
 +      // cond: shiftIsBounded(v)
 +      // result: (SHLL x y)
 +      for {
 +              x := v_0
 +              y := v_1
 +              if !(shiftIsBounded(v)) {
 +                      break
 +              }
 +              v.reset(OpAMD64SHLL)
 +              v.AddArg2(x, y)
 +              return true
 +      }
 +      return false
 +}
 +func rewriteValueAMD64_OpLsh16x32(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (Lsh16x32 <t> x y)
 +      // cond: !shiftIsBounded(v)
 +      // result: (ANDL (SHLL <t> x y) (SBBLcarrymask <t> (CMPLconst y [32])))
 +      for {
 +              t := v.Type
 +              x := v_0
 +              y := v_1
 +              if !(!shiftIsBounded(v)) {
 +                      break
 +              }
 +              v.reset(OpAMD64ANDL)
 +              v0 := b.NewValue0(v.Pos, OpAMD64SHLL, t)
 +              v0.AddArg2(x, y)
 +              v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t)
 +              v2 := b.NewValue0(v.Pos, OpAMD64CMPLconst, types.TypeFlags)
 +              v2.AuxInt = int32ToAuxInt(32)
 +              v2.AddArg(y)
 +              v1.AddArg(v2)
 +              v.AddArg2(v0, v1)
 +              return true
 +      }
 +      // match: (Lsh16x32 x y)
 +      // cond: shiftIsBounded(v)
 +      // result: (SHLL x y)
 +      for {
 +              x := v_0
 +              y := v_1
 +              if !(shiftIsBounded(v)) {
 +                      break
 +              }
 +              v.reset(OpAMD64SHLL)
 +              v.AddArg2(x, y)
 +              return true
 +      }
 +      return false
 +}
 +func rewriteValueAMD64_OpLsh16x64(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (Lsh16x64 <t> x y)
 +      // cond: !shiftIsBounded(v)
 +      // result: (ANDL (SHLL <t> x y) (SBBLcarrymask <t> (CMPQconst y [32])))
 +      for {
 +              t := v.Type
 +              x := v_0
 +              y := v_1
 +              if !(!shiftIsBounded(v)) {
 +                      break
 +              }
 +              v.reset(OpAMD64ANDL)
 +              v0 := b.NewValue0(v.Pos, OpAMD64SHLL, t)
 +              v0.AddArg2(x, y)
 +              v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t)
 +              v2 := b.NewValue0(v.Pos, OpAMD64CMPQconst, types.TypeFlags)
 +              v2.AuxInt = int32ToAuxInt(32)
 +              v2.AddArg(y)
 +              v1.AddArg(v2)
 +              v.AddArg2(v0, v1)
 +              return true
 +      }
 +      // match: (Lsh16x64 x y)
 +      // cond: shiftIsBounded(v)
 +      // result: (SHLL x y)
 +      for {
 +              x := v_0
 +              y := v_1
 +              if !(shiftIsBounded(v)) {
 +                      break
 +              }
 +              v.reset(OpAMD64SHLL)
 +              v.AddArg2(x, y)
 +              return true
 +      }
 +      return false
 +}
 +func rewriteValueAMD64_OpLsh16x8(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (Lsh16x8 <t> x y)
 +      // cond: !shiftIsBounded(v)
 +      // result: (ANDL (SHLL <t> x y) (SBBLcarrymask <t> (CMPBconst y [32])))
 +      for {
 +              t := v.Type
 +              x := v_0
 +              y := v_1
 +              if !(!shiftIsBounded(v)) {
 +                      break
 +              }
 +              v.reset(OpAMD64ANDL)
 +              v0 := b.NewValue0(v.Pos, OpAMD64SHLL, t)
 +              v0.AddArg2(x, y)
 +              v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t)
 +              v2 := b.NewValue0(v.Pos, OpAMD64CMPBconst, types.TypeFlags)
 +              v2.AuxInt = int8ToAuxInt(32)
 +              v2.AddArg(y)
 +              v1.AddArg(v2)
 +              v.AddArg2(v0, v1)
 +              return true
 +      }
 +      // match: (Lsh16x8 x y)
 +      // cond: shiftIsBounded(v)
 +      // result: (SHLL x y)
 +      for {
 +              x := v_0
 +              y := v_1
 +              if !(shiftIsBounded(v)) {
 +                      break
 +              }
 +              v.reset(OpAMD64SHLL)
 +              v.AddArg2(x, y)
 +              return true
 +      }
 +      return false
 +}
 +func rewriteValueAMD64_OpLsh32x16(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (Lsh32x16 <t> x y)
 +      // cond: !shiftIsBounded(v)
 +      // result: (ANDL (SHLL <t> x y) (SBBLcarrymask <t> (CMPWconst y [32])))
 +      for {
 +              t := v.Type
 +              x := v_0
 +              y := v_1
 +              if !(!shiftIsBounded(v)) {
 +                      break
 +              }
 +              v.reset(OpAMD64ANDL)
 +              v0 := b.NewValue0(v.Pos, OpAMD64SHLL, t)
 +              v0.AddArg2(x, y)
 +              v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t)
 +              v2 := b.NewValue0(v.Pos, OpAMD64CMPWconst, types.TypeFlags)
 +              v2.AuxInt = int16ToAuxInt(32)
 +              v2.AddArg(y)
 +              v1.AddArg(v2)
 +              v.AddArg2(v0, v1)
 +              return true
 +      }
 +      // match: (Lsh32x16 x y)
 +      // cond: shiftIsBounded(v)
 +      // result: (SHLL x y)
 +      for {
 +              x := v_0
 +              y := v_1
 +              if !(shiftIsBounded(v)) {
 +                      break
 +              }
 +              v.reset(OpAMD64SHLL)
 +              v.AddArg2(x, y)
 +              return true
 +      }
 +      return false
 +}
 +func rewriteValueAMD64_OpLsh32x32(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (Lsh32x32 <t> x y)
 +      // cond: !shiftIsBounded(v)
 +      // result: (ANDL (SHLL <t> x y) (SBBLcarrymask <t> (CMPLconst y [32])))
 +      for {
 +              t := v.Type
 +              x := v_0
 +              y := v_1
 +              if !(!shiftIsBounded(v)) {
 +                      break
 +              }
 +              v.reset(OpAMD64ANDL)
 +              v0 := b.NewValue0(v.Pos, OpAMD64SHLL, t)
 +              v0.AddArg2(x, y)
 +              v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t)
 +              v2 := b.NewValue0(v.Pos, OpAMD64CMPLconst, types.TypeFlags)
 +              v2.AuxInt = int32ToAuxInt(32)
 +              v2.AddArg(y)
 +              v1.AddArg(v2)
 +              v.AddArg2(v0, v1)
 +              return true
 +      }
 +      // match: (Lsh32x32 x y)
 +      // cond: shiftIsBounded(v)
 +      // result: (SHLL x y)
 +      for {
 +              x := v_0
 +              y := v_1
 +              if !(shiftIsBounded(v)) {
 +                      break
 +              }
 +              v.reset(OpAMD64SHLL)
 +              v.AddArg2(x, y)
 +              return true
 +      }
 +      return false
 +}
 +func rewriteValueAMD64_OpLsh32x64(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (Lsh32x64 <t> x y)
 +      // cond: !shiftIsBounded(v)
 +      // result: (ANDL (SHLL <t> x y) (SBBLcarrymask <t> (CMPQconst y [32])))
 +      for {
 +              t := v.Type
 +              x := v_0
 +              y := v_1
 +              if !(!shiftIsBounded(v)) {
 +                      break
 +              }
 +              v.reset(OpAMD64ANDL)
 +              v0 := b.NewValue0(v.Pos, OpAMD64SHLL, t)
 +              v0.AddArg2(x, y)
 +              v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t)
 +              v2 := b.NewValue0(v.Pos, OpAMD64CMPQconst, types.TypeFlags)
 +              v2.AuxInt = int32ToAuxInt(32)
 +              v2.AddArg(y)
 +              v1.AddArg(v2)
 +              v.AddArg2(v0, v1)
 +              return true
 +      }
 +      // match: (Lsh32x64 x y)
 +      // cond: shiftIsBounded(v)
 +      // result: (SHLL x y)
 +      for {
 +              x := v_0
 +              y := v_1
 +              if !(shiftIsBounded(v)) {
 +                      break
 +              }
 +              v.reset(OpAMD64SHLL)
 +              v.AddArg2(x, y)
 +              return true
 +      }
 +      return false
 +}
 +func rewriteValueAMD64_OpLsh32x8(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (Lsh32x8 <t> x y)
 +      // cond: !shiftIsBounded(v)
 +      // result: (ANDL (SHLL <t> x y) (SBBLcarrymask <t> (CMPBconst y [32])))
 +      for {
 +              t := v.Type
 +              x := v_0
 +              y := v_1
 +              if !(!shiftIsBounded(v)) {
 +                      break
 +              }
 +              v.reset(OpAMD64ANDL)
 +              v0 := b.NewValue0(v.Pos, OpAMD64SHLL, t)
 +              v0.AddArg2(x, y)
 +              v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t)
 +              v2 := b.NewValue0(v.Pos, OpAMD64CMPBconst, types.TypeFlags)
 +              v2.AuxInt = int8ToAuxInt(32)
 +              v2.AddArg(y)
 +              v1.AddArg(v2)
 +              v.AddArg2(v0, v1)
 +              return true
 +      }
 +      // match: (Lsh32x8 x y)
 +      // cond: shiftIsBounded(v)
 +      // result: (SHLL x y)
 +      for {
 +              x := v_0
 +              y := v_1
 +              if !(shiftIsBounded(v)) {
 +                      break
 +              }
 +              v.reset(OpAMD64SHLL)
 +              v.AddArg2(x, y)
 +              return true
 +      }
 +      return false
 +}
 +func rewriteValueAMD64_OpLsh64x16(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (Lsh64x16 <t> x y)
 +      // cond: !shiftIsBounded(v)
 +      // result: (ANDQ (SHLQ <t> x y) (SBBQcarrymask <t> (CMPWconst y [64])))
 +      for {
 +              t := v.Type
 +              x := v_0
 +              y := v_1
 +              if !(!shiftIsBounded(v)) {
 +                      break
 +              }
 +              v.reset(OpAMD64ANDQ)
 +              v0 := b.NewValue0(v.Pos, OpAMD64SHLQ, t)
 +              v0.AddArg2(x, y)
 +              v1 := b.NewValue0(v.Pos, OpAMD64SBBQcarrymask, t)
 +              v2 := b.NewValue0(v.Pos, OpAMD64CMPWconst, types.TypeFlags)
 +              v2.AuxInt = int16ToAuxInt(64)
 +              v2.AddArg(y)
 +              v1.AddArg(v2)
 +              v.AddArg2(v0, v1)
 +              return true
 +      }
 +      // match: (Lsh64x16 x y)
 +      // cond: shiftIsBounded(v)
 +      // result: (SHLQ x y)
 +      for {
 +              x := v_0
 +              y := v_1
 +              if !(shiftIsBounded(v)) {
 +                      break
 +              }
 +              v.reset(OpAMD64SHLQ)
 +              v.AddArg2(x, y)
 +              return true
 +      }
 +      return false
 +}
 +func rewriteValueAMD64_OpLsh64x32(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (Lsh64x32 <t> x y)
 +      // cond: !shiftIsBounded(v)
 +      // result: (ANDQ (SHLQ <t> x y) (SBBQcarrymask <t> (CMPLconst y [64])))
 +      for {
 +              t := v.Type
 +              x := v_0
 +              y := v_1
 +              if !(!shiftIsBounded(v)) {
 +                      break
 +              }
 +              v.reset(OpAMD64ANDQ)
 +              v0 := b.NewValue0(v.Pos, OpAMD64SHLQ, t)
 +              v0.AddArg2(x, y)
 +              v1 := b.NewValue0(v.Pos, OpAMD64SBBQcarrymask, t)
 +              v2 := b.NewValue0(v.Pos, OpAMD64CMPLconst, types.TypeFlags)
 +              v2.AuxInt = int32ToAuxInt(64)
 +              v2.AddArg(y)
 +              v1.AddArg(v2)
 +              v.AddArg2(v0, v1)
 +              return true
 +      }
 +      // match: (Lsh64x32 x y)
 +      // cond: shiftIsBounded(v)
 +      // result: (SHLQ x y)
 +      for {
 +              x := v_0
 +              y := v_1
 +              if !(shiftIsBounded(v)) {
 +                      break
 +              }
 +              v.reset(OpAMD64SHLQ)
 +              v.AddArg2(x, y)
 +              return true
 +      }
 +      return false
 +}
 +func rewriteValueAMD64_OpLsh64x64(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (Lsh64x64 <t> x y)
 +      // cond: !shiftIsBounded(v)
 +      // result: (ANDQ (SHLQ <t> x y) (SBBQcarrymask <t> (CMPQconst y [64])))
 +      for {
 +              t := v.Type
 +              x := v_0
 +              y := v_1
 +              if !(!shiftIsBounded(v)) {
 +                      break
 +              }
 +              v.reset(OpAMD64ANDQ)
 +              v0 := b.NewValue0(v.Pos, OpAMD64SHLQ, t)
 +              v0.AddArg2(x, y)
 +              v1 := b.NewValue0(v.Pos, OpAMD64SBBQcarrymask, t)
 +              v2 := b.NewValue0(v.Pos, OpAMD64CMPQconst, types.TypeFlags)
 +              v2.AuxInt = int32ToAuxInt(64)
 +              v2.AddArg(y)
 +              v1.AddArg(v2)
 +              v.AddArg2(v0, v1)
 +              return true
 +      }
 +      // match: (Lsh64x64 x y)
 +      // cond: shiftIsBounded(v)
 +      // result: (SHLQ x y)
 +      for {
 +              x := v_0
 +              y := v_1
 +              if !(shiftIsBounded(v)) {
 +                      break
 +              }
 +              v.reset(OpAMD64SHLQ)
 +              v.AddArg2(x, y)
 +              return true
 +      }
 +      return false
 +}
 +func rewriteValueAMD64_OpLsh64x8(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (Lsh64x8 <t> x y)
 +      // cond: !shiftIsBounded(v)
 +      // result: (ANDQ (SHLQ <t> x y) (SBBQcarrymask <t> (CMPBconst y [64])))
 +      for {
 +              t := v.Type
 +              x := v_0
 +              y := v_1
 +              if !(!shiftIsBounded(v)) {
 +                      break
 +              }
 +              v.reset(OpAMD64ANDQ)
 +              v0 := b.NewValue0(v.Pos, OpAMD64SHLQ, t)
 +              v0.AddArg2(x, y)
 +              v1 := b.NewValue0(v.Pos, OpAMD64SBBQcarrymask, t)
 +              v2 := b.NewValue0(v.Pos, OpAMD64CMPBconst, types.TypeFlags)
 +              v2.AuxInt = int8ToAuxInt(64)
 +              v2.AddArg(y)
 +              v1.AddArg(v2)
 +              v.AddArg2(v0, v1)
 +              return true
 +      }
 +      // match: (Lsh64x8 x y)
 +      // cond: shiftIsBounded(v)
 +      // result: (SHLQ x y)
 +      for {
 +              x := v_0
 +              y := v_1
 +              if !(shiftIsBounded(v)) {
 +                      break
 +              }
 +              v.reset(OpAMD64SHLQ)
 +              v.AddArg2(x, y)
 +              return true
 +      }
 +      return false
 +}
 +func rewriteValueAMD64_OpLsh8x16(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (Lsh8x16 <t> x y)
 +      // cond: !shiftIsBounded(v)
 +      // result: (ANDL (SHLL <t> x y) (SBBLcarrymask <t> (CMPWconst y [32])))
 +      for {
 +              t := v.Type
 +              x := v_0
 +              y := v_1
 +              if !(!shiftIsBounded(v)) {
 +                      break
 +              }
 +              v.reset(OpAMD64ANDL)
 +              v0 := b.NewValue0(v.Pos, OpAMD64SHLL, t)
 +              v0.AddArg2(x, y)
 +              v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t)
 +              v2 := b.NewValue0(v.Pos, OpAMD64CMPWconst, types.TypeFlags)
 +              v2.AuxInt = int16ToAuxInt(32)
 +              v2.AddArg(y)
 +              v1.AddArg(v2)
 +              v.AddArg2(v0, v1)
 +              return true
 +      }
 +      // match: (Lsh8x16 x y)
 +      // cond: shiftIsBounded(v)
 +      // result: (SHLL x y)
 +      for {
 +              x := v_0
 +              y := v_1
 +              if !(shiftIsBounded(v)) {
 +                      break
 +              }
 +              v.reset(OpAMD64SHLL)
 +              v.AddArg2(x, y)
 +              return true
 +      }
 +      return false
 +}
 +func rewriteValueAMD64_OpLsh8x32(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (Lsh8x32 <t> x y)
 +      // cond: !shiftIsBounded(v)
 +      // result: (ANDL (SHLL <t> x y) (SBBLcarrymask <t> (CMPLconst y [32])))
 +      for {
 +              t := v.Type
 +              x := v_0
 +              y := v_1
 +              if !(!shiftIsBounded(v)) {
 +                      break
 +              }
 +              v.reset(OpAMD64ANDL)
 +              v0 := b.NewValue0(v.Pos, OpAMD64SHLL, t)
 +              v0.AddArg2(x, y)
 +              v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t)
 +              v2 := b.NewValue0(v.Pos, OpAMD64CMPLconst, types.TypeFlags)
 +              v2.AuxInt = int32ToAuxInt(32)
 +              v2.AddArg(y)
 +              v1.AddArg(v2)
 +              v.AddArg2(v0, v1)
 +              return true
 +      }
 +      // match: (Lsh8x32 x y)
 +      // cond: shiftIsBounded(v)
 +      // result: (SHLL x y)
 +      for {
 +              x := v_0
 +              y := v_1
 +              if !(shiftIsBounded(v)) {
 +                      break
 +              }
 +              v.reset(OpAMD64SHLL)
 +              v.AddArg2(x, y)
 +              return true
 +      }
 +      return false
 +}
 +func rewriteValueAMD64_OpLsh8x64(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (Lsh8x64 <t> x y)
 +      // cond: !shiftIsBounded(v)
 +      // result: (ANDL (SHLL <t> x y) (SBBLcarrymask <t> (CMPQconst y [32])))
 +      for {
 +              t := v.Type
 +              x := v_0
 +              y := v_1
 +              if !(!shiftIsBounded(v)) {
 +                      break
 +              }
 +              v.reset(OpAMD64ANDL)
 +              v0 := b.NewValue0(v.Pos, OpAMD64SHLL, t)
 +              v0.AddArg2(x, y)
 +              v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t)
 +              v2 := b.NewValue0(v.Pos, OpAMD64CMPQconst, types.TypeFlags)
 +              v2.AuxInt = int32ToAuxInt(32)
 +              v2.AddArg(y)
 +              v1.AddArg(v2)
 +              v.AddArg2(v0, v1)
 +              return true
 +      }
 +      // match: (Lsh8x64 x y)
 +      // cond: shiftIsBounded(v)
 +      // result: (SHLL x y)
 +      for {
 +              x := v_0
 +              y := v_1
 +              if !(shiftIsBounded(v)) {
 +                      break
 +              }
 +              v.reset(OpAMD64SHLL)
 +              v.AddArg2(x, y)
 +              return true
 +      }
 +      return false
 +}
 +func rewriteValueAMD64_OpLsh8x8(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (Lsh8x8 <t> x y)
 +      // cond: !shiftIsBounded(v)
 +      // result: (ANDL (SHLL <t> x y) (SBBLcarrymask <t> (CMPBconst y [32])))
 +      for {
 +              t := v.Type
 +              x := v_0
 +              y := v_1
 +              if !(!shiftIsBounded(v)) {
 +                      break
 +              }
 +              v.reset(OpAMD64ANDL)
 +              v0 := b.NewValue0(v.Pos, OpAMD64SHLL, t)
 +              v0.AddArg2(x, y)
 +              v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t)
 +              v2 := b.NewValue0(v.Pos, OpAMD64CMPBconst, types.TypeFlags)
 +              v2.AuxInt = int8ToAuxInt(32)
 +              v2.AddArg(y)
 +              v1.AddArg(v2)
 +              v.AddArg2(v0, v1)
 +              return true
 +      }
 +      // match: (Lsh8x8 x y)
 +      // cond: shiftIsBounded(v)
 +      // result: (SHLL x y)
 +      for {
 +              x := v_0
 +              y := v_1
 +              if !(shiftIsBounded(v)) {
 +                      break
 +              }
 +              v.reset(OpAMD64SHLL)
 +              v.AddArg2(x, y)
 +              return true
 +      }
 +      return false
 +}
 +func rewriteValueAMD64_OpMax32F(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (Max32F <t> x y)
 +      // result: (Neg32F <t> (Min32F <t> (Neg32F <t> x) (Neg32F <t> y)))
 +      for {
 +              t := v.Type
 +              x := v_0
 +              y := v_1
 +              v.reset(OpNeg32F)
 +              v.Type = t
 +              v0 := b.NewValue0(v.Pos, OpMin32F, t)
 +              v1 := b.NewValue0(v.Pos, OpNeg32F, t)
 +              v1.AddArg(x)
 +              v2 := b.NewValue0(v.Pos, OpNeg32F, t)
 +              v2.AddArg(y)
 +              v0.AddArg2(v1, v2)
 +              v.AddArg(v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpMax64F(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (Max64F <t> x y)
 +      // result: (Neg64F <t> (Min64F <t> (Neg64F <t> x) (Neg64F <t> y)))
 +      for {
 +              t := v.Type
 +              x := v_0
 +              y := v_1
 +              v.reset(OpNeg64F)
 +              v.Type = t
 +              v0 := b.NewValue0(v.Pos, OpMin64F, t)
 +              v1 := b.NewValue0(v.Pos, OpNeg64F, t)
 +              v1.AddArg(x)
 +              v2 := b.NewValue0(v.Pos, OpNeg64F, t)
 +              v2.AddArg(y)
 +              v0.AddArg2(v1, v2)
 +              v.AddArg(v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpMaxMaskedFloat32x16(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (MaxMaskedFloat32x16 x y mask)
 +      // result: (VMAXPSMasked512 x y (VPMOVVec32x16ToM <types.TypeMask> mask))
 +      for {
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VMAXPSMasked512)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x16ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg3(x, y, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpMaxMaskedFloat32x4(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (MaxMaskedFloat32x4 x y mask)
 +      // result: (VMAXPSMasked128 x y (VPMOVVec32x4ToM <types.TypeMask> mask))
 +      for {
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VMAXPSMasked128)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x4ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg3(x, y, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpMaxMaskedFloat32x8(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (MaxMaskedFloat32x8 x y mask)
 +      // result: (VMAXPSMasked256 x y (VPMOVVec32x8ToM <types.TypeMask> mask))
 +      for {
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VMAXPSMasked256)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x8ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg3(x, y, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpMaxMaskedFloat64x2(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (MaxMaskedFloat64x2 x y mask)
 +      // result: (VMAXPDMasked128 x y (VPMOVVec64x2ToM <types.TypeMask> mask))
 +      for {
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VMAXPDMasked128)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x2ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg3(x, y, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpMaxMaskedFloat64x4(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (MaxMaskedFloat64x4 x y mask)
 +      // result: (VMAXPDMasked256 x y (VPMOVVec64x4ToM <types.TypeMask> mask))
 +      for {
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VMAXPDMasked256)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x4ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg3(x, y, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpMaxMaskedFloat64x8(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (MaxMaskedFloat64x8 x y mask)
 +      // result: (VMAXPDMasked512 x y (VPMOVVec64x8ToM <types.TypeMask> mask))
 +      for {
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VMAXPDMasked512)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x8ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg3(x, y, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpMaxMaskedInt16x16(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (MaxMaskedInt16x16 x y mask)
 +      // result: (VPMAXSWMasked256 x y (VPMOVVec16x16ToM <types.TypeMask> mask))
 +      for {
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VPMAXSWMasked256)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x16ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg3(x, y, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpMaxMaskedInt16x32(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (MaxMaskedInt16x32 x y mask)
 +      // result: (VPMAXSWMasked512 x y (VPMOVVec16x32ToM <types.TypeMask> mask))
 +      for {
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VPMAXSWMasked512)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x32ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg3(x, y, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpMaxMaskedInt16x8(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (MaxMaskedInt16x8 x y mask)
 +      // result: (VPMAXSWMasked128 x y (VPMOVVec16x8ToM <types.TypeMask> mask))
 +      for {
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VPMAXSWMasked128)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x8ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg3(x, y, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpMaxMaskedInt32x16(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (MaxMaskedInt32x16 x y mask)
 +      // result: (VPMAXSDMasked512 x y (VPMOVVec32x16ToM <types.TypeMask> mask))
 +      for {
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VPMAXSDMasked512)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x16ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg3(x, y, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpMaxMaskedInt32x4(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (MaxMaskedInt32x4 x y mask)
 +      // result: (VPMAXSDMasked128 x y (VPMOVVec32x4ToM <types.TypeMask> mask))
 +      for {
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VPMAXSDMasked128)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x4ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg3(x, y, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpMaxMaskedInt32x8(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (MaxMaskedInt32x8 x y mask)
 +      // result: (VPMAXSDMasked256 x y (VPMOVVec32x8ToM <types.TypeMask> mask))
 +      for {
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VPMAXSDMasked256)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x8ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg3(x, y, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpMaxMaskedInt64x2(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (MaxMaskedInt64x2 x y mask)
 +      // result: (VPMAXSQMasked128 x y (VPMOVVec64x2ToM <types.TypeMask> mask))
 +      for {
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VPMAXSQMasked128)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x2ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg3(x, y, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpMaxMaskedInt64x4(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (MaxMaskedInt64x4 x y mask)
 +      // result: (VPMAXSQMasked256 x y (VPMOVVec64x4ToM <types.TypeMask> mask))
 +      for {
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VPMAXSQMasked256)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x4ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg3(x, y, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpMaxMaskedInt64x8(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (MaxMaskedInt64x8 x y mask)
 +      // result: (VPMAXSQMasked512 x y (VPMOVVec64x8ToM <types.TypeMask> mask))
 +      for {
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VPMAXSQMasked512)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x8ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg3(x, y, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpMaxMaskedInt8x16(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (MaxMaskedInt8x16 x y mask)
 +      // result: (VPMAXSBMasked128 x y (VPMOVVec8x16ToM <types.TypeMask> mask))
 +      for {
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VPMAXSBMasked128)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec8x16ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg3(x, y, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpMaxMaskedInt8x32(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (MaxMaskedInt8x32 x y mask)
 +      // result: (VPMAXSBMasked256 x y (VPMOVVec8x32ToM <types.TypeMask> mask))
 +      for {
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VPMAXSBMasked256)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec8x32ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg3(x, y, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpMaxMaskedInt8x64(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (MaxMaskedInt8x64 x y mask)
 +      // result: (VPMAXSBMasked512 x y (VPMOVVec8x64ToM <types.TypeMask> mask))
 +      for {
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VPMAXSBMasked512)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec8x64ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg3(x, y, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpMaxMaskedUint16x16(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (MaxMaskedUint16x16 x y mask)
 +      // result: (VPMAXUWMasked256 x y (VPMOVVec16x16ToM <types.TypeMask> mask))
 +      for {
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VPMAXUWMasked256)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x16ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg3(x, y, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpMaxMaskedUint16x32(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (MaxMaskedUint16x32 x y mask)
 +      // result: (VPMAXUWMasked512 x y (VPMOVVec16x32ToM <types.TypeMask> mask))
 +      for {
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VPMAXUWMasked512)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x32ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg3(x, y, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpMaxMaskedUint16x8(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (MaxMaskedUint16x8 x y mask)
 +      // result: (VPMAXUWMasked128 x y (VPMOVVec16x8ToM <types.TypeMask> mask))
 +      for {
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VPMAXUWMasked128)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x8ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg3(x, y, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpMaxMaskedUint32x16(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (MaxMaskedUint32x16 x y mask)
 +      // result: (VPMAXUDMasked512 x y (VPMOVVec32x16ToM <types.TypeMask> mask))
 +      for {
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VPMAXUDMasked512)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x16ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg3(x, y, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpMaxMaskedUint32x4(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (MaxMaskedUint32x4 x y mask)
 +      // result: (VPMAXUDMasked128 x y (VPMOVVec32x4ToM <types.TypeMask> mask))
 +      for {
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VPMAXUDMasked128)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x4ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg3(x, y, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpMaxMaskedUint32x8(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (MaxMaskedUint32x8 x y mask)
 +      // result: (VPMAXUDMasked256 x y (VPMOVVec32x8ToM <types.TypeMask> mask))
 +      for {
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VPMAXUDMasked256)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x8ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg3(x, y, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpMaxMaskedUint64x2(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (MaxMaskedUint64x2 x y mask)
 +      // result: (VPMAXUQMasked128 x y (VPMOVVec64x2ToM <types.TypeMask> mask))
 +      for {
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VPMAXUQMasked128)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x2ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg3(x, y, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpMaxMaskedUint64x4(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (MaxMaskedUint64x4 x y mask)
 +      // result: (VPMAXUQMasked256 x y (VPMOVVec64x4ToM <types.TypeMask> mask))
 +      for {
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VPMAXUQMasked256)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x4ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg3(x, y, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpMaxMaskedUint64x8(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (MaxMaskedUint64x8 x y mask)
 +      // result: (VPMAXUQMasked512 x y (VPMOVVec64x8ToM <types.TypeMask> mask))
 +      for {
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VPMAXUQMasked512)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x8ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg3(x, y, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpMaxMaskedUint8x16(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (MaxMaskedUint8x16 x y mask)
 +      // result: (VPMAXUBMasked128 x y (VPMOVVec8x16ToM <types.TypeMask> mask))
 +      for {
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VPMAXUBMasked128)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec8x16ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg3(x, y, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpMaxMaskedUint8x32(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (MaxMaskedUint8x32 x y mask)
 +      // result: (VPMAXUBMasked256 x y (VPMOVVec8x32ToM <types.TypeMask> mask))
 +      for {
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VPMAXUBMasked256)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec8x32ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg3(x, y, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpMaxMaskedUint8x64(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (MaxMaskedUint8x64 x y mask)
 +      // result: (VPMAXUBMasked512 x y (VPMOVVec8x64ToM <types.TypeMask> mask))
 +      for {
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VPMAXUBMasked512)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec8x64ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg3(x, y, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpMin32F(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (Min32F <t> x y)
 +      // result: (POR (MINSS <t> (MINSS <t> x y) x) (MINSS <t> x y))
 +      for {
 +              t := v.Type
 +              x := v_0
 +              y := v_1
 +              v.reset(OpAMD64POR)
 +              v0 := b.NewValue0(v.Pos, OpAMD64MINSS, t)
 +              v1 := b.NewValue0(v.Pos, OpAMD64MINSS, t)
 +              v1.AddArg2(x, y)
 +              v0.AddArg2(v1, x)
 +              v.AddArg2(v0, v1)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpMin64F(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (Min64F <t> x y)
 +      // result: (POR (MINSD <t> (MINSD <t> x y) x) (MINSD <t> x y))
 +      for {
 +              t := v.Type
 +              x := v_0
 +              y := v_1
 +              v.reset(OpAMD64POR)
 +              v0 := b.NewValue0(v.Pos, OpAMD64MINSD, t)
 +              v1 := b.NewValue0(v.Pos, OpAMD64MINSD, t)
 +              v1.AddArg2(x, y)
 +              v0.AddArg2(v1, x)
 +              v.AddArg2(v0, v1)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpMinMaskedFloat32x16(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (MinMaskedFloat32x16 x y mask)
 +      // result: (VMINPSMasked512 x y (VPMOVVec32x16ToM <types.TypeMask> mask))
 +      for {
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VMINPSMasked512)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x16ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg3(x, y, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpMinMaskedFloat32x4(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (MinMaskedFloat32x4 x y mask)
 +      // result: (VMINPSMasked128 x y (VPMOVVec32x4ToM <types.TypeMask> mask))
 +      for {
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VMINPSMasked128)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x4ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg3(x, y, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpMinMaskedFloat32x8(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (MinMaskedFloat32x8 x y mask)
 +      // result: (VMINPSMasked256 x y (VPMOVVec32x8ToM <types.TypeMask> mask))
 +      for {
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VMINPSMasked256)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x8ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg3(x, y, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpMinMaskedFloat64x2(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (MinMaskedFloat64x2 x y mask)
 +      // result: (VMINPDMasked128 x y (VPMOVVec64x2ToM <types.TypeMask> mask))
 +      for {
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VMINPDMasked128)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x2ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg3(x, y, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpMinMaskedFloat64x4(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (MinMaskedFloat64x4 x y mask)
 +      // result: (VMINPDMasked256 x y (VPMOVVec64x4ToM <types.TypeMask> mask))
 +      for {
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VMINPDMasked256)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x4ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg3(x, y, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpMinMaskedFloat64x8(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (MinMaskedFloat64x8 x y mask)
 +      // result: (VMINPDMasked512 x y (VPMOVVec64x8ToM <types.TypeMask> mask))
 +      for {
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VMINPDMasked512)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x8ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg3(x, y, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpMinMaskedInt16x16(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (MinMaskedInt16x16 x y mask)
 +      // result: (VPMINSWMasked256 x y (VPMOVVec16x16ToM <types.TypeMask> mask))
 +      for {
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VPMINSWMasked256)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x16ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg3(x, y, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpMinMaskedInt16x32(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (MinMaskedInt16x32 x y mask)
 +      // result: (VPMINSWMasked512 x y (VPMOVVec16x32ToM <types.TypeMask> mask))
 +      for {
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VPMINSWMasked512)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x32ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg3(x, y, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpMinMaskedInt16x8(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (MinMaskedInt16x8 x y mask)
 +      // result: (VPMINSWMasked128 x y (VPMOVVec16x8ToM <types.TypeMask> mask))
 +      for {
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VPMINSWMasked128)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x8ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg3(x, y, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpMinMaskedInt32x16(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (MinMaskedInt32x16 x y mask)
 +      // result: (VPMINSDMasked512 x y (VPMOVVec32x16ToM <types.TypeMask> mask))
 +      for {
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VPMINSDMasked512)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x16ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg3(x, y, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpMinMaskedInt32x4(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (MinMaskedInt32x4 x y mask)
 +      // result: (VPMINSDMasked128 x y (VPMOVVec32x4ToM <types.TypeMask> mask))
 +      for {
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VPMINSDMasked128)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x4ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg3(x, y, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpMinMaskedInt32x8(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (MinMaskedInt32x8 x y mask)
 +      // result: (VPMINSDMasked256 x y (VPMOVVec32x8ToM <types.TypeMask> mask))
 +      for {
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VPMINSDMasked256)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x8ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg3(x, y, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpMinMaskedInt64x2(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (MinMaskedInt64x2 x y mask)
 +      // result: (VPMINSQMasked128 x y (VPMOVVec64x2ToM <types.TypeMask> mask))
 +      for {
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VPMINSQMasked128)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x2ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg3(x, y, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpMinMaskedInt64x4(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (MinMaskedInt64x4 x y mask)
 +      // result: (VPMINSQMasked256 x y (VPMOVVec64x4ToM <types.TypeMask> mask))
 +      for {
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VPMINSQMasked256)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x4ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg3(x, y, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpMinMaskedInt64x8(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (MinMaskedInt64x8 x y mask)
 +      // result: (VPMINSQMasked512 x y (VPMOVVec64x8ToM <types.TypeMask> mask))
 +      for {
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VPMINSQMasked512)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x8ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg3(x, y, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpMinMaskedInt8x16(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (MinMaskedInt8x16 x y mask)
 +      // result: (VPMINSBMasked128 x y (VPMOVVec8x16ToM <types.TypeMask> mask))
 +      for {
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VPMINSBMasked128)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec8x16ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg3(x, y, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpMinMaskedInt8x32(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (MinMaskedInt8x32 x y mask)
 +      // result: (VPMINSBMasked256 x y (VPMOVVec8x32ToM <types.TypeMask> mask))
 +      for {
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VPMINSBMasked256)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec8x32ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg3(x, y, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpMinMaskedInt8x64(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (MinMaskedInt8x64 x y mask)
 +      // result: (VPMINSBMasked512 x y (VPMOVVec8x64ToM <types.TypeMask> mask))
 +      for {
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VPMINSBMasked512)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec8x64ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg3(x, y, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpMinMaskedUint16x16(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (MinMaskedUint16x16 x y mask)
 +      // result: (VPMINUWMasked256 x y (VPMOVVec16x16ToM <types.TypeMask> mask))
 +      for {
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VPMINUWMasked256)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x16ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg3(x, y, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpMinMaskedUint16x32(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (MinMaskedUint16x32 x y mask)
 +      // result: (VPMINUWMasked512 x y (VPMOVVec16x32ToM <types.TypeMask> mask))
 +      for {
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VPMINUWMasked512)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x32ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg3(x, y, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpMinMaskedUint16x8(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (MinMaskedUint16x8 x y mask)
 +      // result: (VPMINUWMasked128 x y (VPMOVVec16x8ToM <types.TypeMask> mask))
 +      for {
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VPMINUWMasked128)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x8ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg3(x, y, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpMinMaskedUint32x16(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (MinMaskedUint32x16 x y mask)
 +      // result: (VPMINUDMasked512 x y (VPMOVVec32x16ToM <types.TypeMask> mask))
 +      for {
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VPMINUDMasked512)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x16ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg3(x, y, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpMinMaskedUint32x4(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (MinMaskedUint32x4 x y mask)
 +      // result: (VPMINUDMasked128 x y (VPMOVVec32x4ToM <types.TypeMask> mask))
 +      for {
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VPMINUDMasked128)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x4ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg3(x, y, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpMinMaskedUint32x8(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (MinMaskedUint32x8 x y mask)
 +      // result: (VPMINUDMasked256 x y (VPMOVVec32x8ToM <types.TypeMask> mask))
 +      for {
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VPMINUDMasked256)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x8ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg3(x, y, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpMinMaskedUint64x2(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (MinMaskedUint64x2 x y mask)
 +      // result: (VPMINUQMasked128 x y (VPMOVVec64x2ToM <types.TypeMask> mask))
 +      for {
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VPMINUQMasked128)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x2ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg3(x, y, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpMinMaskedUint64x4(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (MinMaskedUint64x4 x y mask)
 +      // result: (VPMINUQMasked256 x y (VPMOVVec64x4ToM <types.TypeMask> mask))
 +      for {
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VPMINUQMasked256)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x4ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg3(x, y, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpMinMaskedUint64x8(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (MinMaskedUint64x8 x y mask)
 +      // result: (VPMINUQMasked512 x y (VPMOVVec64x8ToM <types.TypeMask> mask))
 +      for {
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VPMINUQMasked512)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x8ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg3(x, y, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpMinMaskedUint8x16(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (MinMaskedUint8x16 x y mask)
 +      // result: (VPMINUBMasked128 x y (VPMOVVec8x16ToM <types.TypeMask> mask))
 +      for {
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VPMINUBMasked128)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec8x16ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg3(x, y, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpMinMaskedUint8x32(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (MinMaskedUint8x32 x y mask)
 +      // result: (VPMINUBMasked256 x y (VPMOVVec8x32ToM <types.TypeMask> mask))
 +      for {
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VPMINUBMasked256)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec8x32ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg3(x, y, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpMinMaskedUint8x64(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (MinMaskedUint8x64 x y mask)
 +      // result: (VPMINUBMasked512 x y (VPMOVVec8x64ToM <types.TypeMask> mask))
 +      for {
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VPMINUBMasked512)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec8x64ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg3(x, y, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpMod16(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      typ := &b.Func.Config.Types
 +      // match: (Mod16 [a] x y)
 +      // result: (Select1 (DIVW [a] x y))
 +      for {
 +              a := auxIntToBool(v.AuxInt)
 +              x := v_0
 +              y := v_1
 +              v.reset(OpSelect1)
 +              v0 := b.NewValue0(v.Pos, OpAMD64DIVW, types.NewTuple(typ.Int16, typ.Int16))
 +              v0.AuxInt = boolToAuxInt(a)
 +              v0.AddArg2(x, y)
 +              v.AddArg(v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpMod16u(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      typ := &b.Func.Config.Types
 +      // match: (Mod16u x y)
 +      // result: (Select1 (DIVWU x y))
 +      for {
 +              x := v_0
 +              y := v_1
 +              v.reset(OpSelect1)
 +              v0 := b.NewValue0(v.Pos, OpAMD64DIVWU, types.NewTuple(typ.UInt16, typ.UInt16))
 +              v0.AddArg2(x, y)
 +              v.AddArg(v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpMod32(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      typ := &b.Func.Config.Types
 +      // match: (Mod32 [a] x y)
 +      // result: (Select1 (DIVL [a] x y))
 +      for {
 +              a := auxIntToBool(v.AuxInt)
 +              x := v_0
 +              y := v_1
 +              v.reset(OpSelect1)
 +              v0 := b.NewValue0(v.Pos, OpAMD64DIVL, types.NewTuple(typ.Int32, typ.Int32))
 +              v0.AuxInt = boolToAuxInt(a)
 +              v0.AddArg2(x, y)
 +              v.AddArg(v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpMod32u(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      typ := &b.Func.Config.Types
 +      // match: (Mod32u x y)
 +      // result: (Select1 (DIVLU x y))
 +      for {
 +              x := v_0
 +              y := v_1
 +              v.reset(OpSelect1)
 +              v0 := b.NewValue0(v.Pos, OpAMD64DIVLU, types.NewTuple(typ.UInt32, typ.UInt32))
 +              v0.AddArg2(x, y)
 +              v.AddArg(v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpMod64(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      typ := &b.Func.Config.Types
 +      // match: (Mod64 [a] x y)
 +      // result: (Select1 (DIVQ [a] x y))
 +      for {
 +              a := auxIntToBool(v.AuxInt)
 +              x := v_0
 +              y := v_1
 +              v.reset(OpSelect1)
 +              v0 := b.NewValue0(v.Pos, OpAMD64DIVQ, types.NewTuple(typ.Int64, typ.Int64))
 +              v0.AuxInt = boolToAuxInt(a)
 +              v0.AddArg2(x, y)
 +              v.AddArg(v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpMod64u(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      typ := &b.Func.Config.Types
 +      // match: (Mod64u x y)
 +      // result: (Select1 (DIVQU x y))
 +      for {
 +              x := v_0
 +              y := v_1
 +              v.reset(OpSelect1)
 +              v0 := b.NewValue0(v.Pos, OpAMD64DIVQU, types.NewTuple(typ.UInt64, typ.UInt64))
 +              v0.AddArg2(x, y)
 +              v.AddArg(v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpMod8(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      typ := &b.Func.Config.Types
 +      // match: (Mod8 x y)
 +      // result: (Select1 (DIVW (SignExt8to16 x) (SignExt8to16 y)))
 +      for {
 +              x := v_0
 +              y := v_1
 +              v.reset(OpSelect1)
 +              v0 := b.NewValue0(v.Pos, OpAMD64DIVW, types.NewTuple(typ.Int16, typ.Int16))
 +              v1 := b.NewValue0(v.Pos, OpSignExt8to16, typ.Int16)
 +              v1.AddArg(x)
 +              v2 := b.NewValue0(v.Pos, OpSignExt8to16, typ.Int16)
 +              v2.AddArg(y)
 +              v0.AddArg2(v1, v2)
 +              v.AddArg(v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpMod8u(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      typ := &b.Func.Config.Types
 +      // match: (Mod8u x y)
 +      // result: (Select1 (DIVWU (ZeroExt8to16 x) (ZeroExt8to16 y)))
 +      for {
 +              x := v_0
 +              y := v_1
 +              v.reset(OpSelect1)
 +              v0 := b.NewValue0(v.Pos, OpAMD64DIVWU, types.NewTuple(typ.UInt16, typ.UInt16))
 +              v1 := b.NewValue0(v.Pos, OpZeroExt8to16, typ.UInt16)
 +              v1.AddArg(x)
 +              v2 := b.NewValue0(v.Pos, OpZeroExt8to16, typ.UInt16)
 +              v2.AddArg(y)
 +              v0.AddArg2(v1, v2)
 +              v.AddArg(v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpMove(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      typ := &b.Func.Config.Types
 +      // match: (Move [0] _ _ mem)
 +      // result: mem
 +      for {
 +              if auxIntToInt64(v.AuxInt) != 0 {
 +                      break
 +              }
 +              mem := v_2
 +              v.copyOf(mem)
 +              return true
 +      }
 +      // match: (Move [1] dst src mem)
 +      // result: (MOVBstore dst (MOVBload src mem) mem)
 +      for {
 +              if auxIntToInt64(v.AuxInt) != 1 {
 +                      break
 +              }
 +              dst := v_0
 +              src := v_1
 +              mem := v_2
 +              v.reset(OpAMD64MOVBstore)
 +              v0 := b.NewValue0(v.Pos, OpAMD64MOVBload, typ.UInt8)
 +              v0.AddArg2(src, mem)
 +              v.AddArg3(dst, v0, mem)
 +              return true
 +      }
 +      // match: (Move [2] dst src mem)
 +      // result: (MOVWstore dst (MOVWload src mem) mem)
 +      for {
 +              if auxIntToInt64(v.AuxInt) != 2 {
 +                      break
 +              }
 +              dst := v_0
 +              src := v_1
 +              mem := v_2
 +              v.reset(OpAMD64MOVWstore)
 +              v0 := b.NewValue0(v.Pos, OpAMD64MOVWload, typ.UInt16)
 +              v0.AddArg2(src, mem)
 +              v.AddArg3(dst, v0, mem)
 +              return true
 +      }
 +      // match: (Move [4] dst src mem)
 +      // result: (MOVLstore dst (MOVLload src mem) mem)
 +      for {
 +              if auxIntToInt64(v.AuxInt) != 4 {
 +                      break
 +              }
 +              dst := v_0
 +              src := v_1
 +              mem := v_2
 +              v.reset(OpAMD64MOVLstore)
 +              v0 := b.NewValue0(v.Pos, OpAMD64MOVLload, typ.UInt32)
 +              v0.AddArg2(src, mem)
 +              v.AddArg3(dst, v0, mem)
 +              return true
 +      }
 +      // match: (Move [8] dst src mem)
 +      // result: (MOVQstore dst (MOVQload src mem) mem)
 +      for {
 +              if auxIntToInt64(v.AuxInt) != 8 {
 +                      break
 +              }
 +              dst := v_0
 +              src := v_1
 +              mem := v_2
 +              v.reset(OpAMD64MOVQstore)
 +              v0 := b.NewValue0(v.Pos, OpAMD64MOVQload, typ.UInt64)
 +              v0.AddArg2(src, mem)
 +              v.AddArg3(dst, v0, mem)
 +              return true
 +      }
 +      // match: (Move [16] dst src mem)
 +      // result: (MOVOstore dst (MOVOload src mem) mem)
 +      for {
 +              if auxIntToInt64(v.AuxInt) != 16 {
 +                      break
 +              }
 +              dst := v_0
 +              src := v_1
 +              mem := v_2
 +              v.reset(OpAMD64MOVOstore)
 +              v0 := b.NewValue0(v.Pos, OpAMD64MOVOload, types.TypeInt128)
 +              v0.AddArg2(src, mem)
 +              v.AddArg3(dst, v0, mem)
 +              return true
 +      }
-       // match: (Move [32] dst src mem)
-       // result: (Move [16] (OffPtr <dst.Type> dst [16]) (OffPtr <src.Type> src [16]) (Move [16] dst src mem))
-       for {
-               if auxIntToInt64(v.AuxInt) != 32 {
-                       break
-               }
-               dst := v_0
-               src := v_1
-               mem := v_2
-               v.reset(OpMove)
-               v.AuxInt = int64ToAuxInt(16)
-               v0 := b.NewValue0(v.Pos, OpOffPtr, dst.Type)
-               v0.AuxInt = int64ToAuxInt(16)
-               v0.AddArg(dst)
-               v1 := b.NewValue0(v.Pos, OpOffPtr, src.Type)
-               v1.AuxInt = int64ToAuxInt(16)
-               v1.AddArg(src)
-               v2 := b.NewValue0(v.Pos, OpMove, types.TypeMem)
-               v2.AuxInt = int64ToAuxInt(16)
-               v2.AddArg3(dst, src, mem)
-               v.AddArg3(v0, v1, v2)
-               return true
-       }
-       // match: (Move [48] dst src mem)
-       // result: (Move [32] (OffPtr <dst.Type> dst [16]) (OffPtr <src.Type> src [16]) (Move [16] dst src mem))
-       for {
-               if auxIntToInt64(v.AuxInt) != 48 {
-                       break
-               }
-               dst := v_0
-               src := v_1
-               mem := v_2
-               v.reset(OpMove)
-               v.AuxInt = int64ToAuxInt(32)
-               v0 := b.NewValue0(v.Pos, OpOffPtr, dst.Type)
-               v0.AuxInt = int64ToAuxInt(16)
-               v0.AddArg(dst)
-               v1 := b.NewValue0(v.Pos, OpOffPtr, src.Type)
-               v1.AuxInt = int64ToAuxInt(16)
-               v1.AddArg(src)
-               v2 := b.NewValue0(v.Pos, OpMove, types.TypeMem)
-               v2.AuxInt = int64ToAuxInt(16)
-               v2.AddArg3(dst, src, mem)
-               v.AddArg3(v0, v1, v2)
-               return true
-       }
-       // match: (Move [64] dst src mem)
-       // result: (Move [32] (OffPtr <dst.Type> dst [32]) (OffPtr <src.Type> src [32]) (Move [32] dst src mem))
-       for {
-               if auxIntToInt64(v.AuxInt) != 64 {
-                       break
-               }
-               dst := v_0
-               src := v_1
-               mem := v_2
-               v.reset(OpMove)
-               v.AuxInt = int64ToAuxInt(32)
-               v0 := b.NewValue0(v.Pos, OpOffPtr, dst.Type)
-               v0.AuxInt = int64ToAuxInt(32)
-               v0.AddArg(dst)
-               v1 := b.NewValue0(v.Pos, OpOffPtr, src.Type)
-               v1.AuxInt = int64ToAuxInt(32)
-               v1.AddArg(src)
-               v2 := b.NewValue0(v.Pos, OpMove, types.TypeMem)
-               v2.AuxInt = int64ToAuxInt(32)
-               v2.AddArg3(dst, src, mem)
-               v.AddArg3(v0, v1, v2)
-               return true
-       }
 +      // match: (Move [3] dst src mem)
 +      // result: (MOVBstore [2] dst (MOVBload [2] src mem) (MOVWstore dst (MOVWload src mem) mem))
 +      for {
 +              if auxIntToInt64(v.AuxInt) != 3 {
 +                      break
 +              }
 +              dst := v_0
 +              src := v_1
 +              mem := v_2
 +              v.reset(OpAMD64MOVBstore)
 +              v.AuxInt = int32ToAuxInt(2)
 +              v0 := b.NewValue0(v.Pos, OpAMD64MOVBload, typ.UInt8)
 +              v0.AuxInt = int32ToAuxInt(2)
 +              v0.AddArg2(src, mem)
 +              v1 := b.NewValue0(v.Pos, OpAMD64MOVWstore, types.TypeMem)
 +              v2 := b.NewValue0(v.Pos, OpAMD64MOVWload, typ.UInt16)
 +              v2.AddArg2(src, mem)
 +              v1.AddArg3(dst, v2, mem)
 +              v.AddArg3(dst, v0, v1)
 +              return true
 +      }
 +      // match: (Move [5] dst src mem)
 +      // result: (MOVBstore [4] dst (MOVBload [4] src mem) (MOVLstore dst (MOVLload src mem) mem))
 +      for {
 +              if auxIntToInt64(v.AuxInt) != 5 {
 +                      break
 +              }
 +              dst := v_0
 +              src := v_1
 +              mem := v_2
 +              v.reset(OpAMD64MOVBstore)
 +              v.AuxInt = int32ToAuxInt(4)
 +              v0 := b.NewValue0(v.Pos, OpAMD64MOVBload, typ.UInt8)
 +              v0.AuxInt = int32ToAuxInt(4)
 +              v0.AddArg2(src, mem)
 +              v1 := b.NewValue0(v.Pos, OpAMD64MOVLstore, types.TypeMem)
 +              v2 := b.NewValue0(v.Pos, OpAMD64MOVLload, typ.UInt32)
 +              v2.AddArg2(src, mem)
 +              v1.AddArg3(dst, v2, mem)
 +              v.AddArg3(dst, v0, v1)
 +              return true
 +      }
 +      // match: (Move [6] dst src mem)
 +      // result: (MOVWstore [4] dst (MOVWload [4] src mem) (MOVLstore dst (MOVLload src mem) mem))
 +      for {
 +              if auxIntToInt64(v.AuxInt) != 6 {
 +                      break
 +              }
 +              dst := v_0
 +              src := v_1
 +              mem := v_2
 +              v.reset(OpAMD64MOVWstore)
 +              v.AuxInt = int32ToAuxInt(4)
 +              v0 := b.NewValue0(v.Pos, OpAMD64MOVWload, typ.UInt16)
 +              v0.AuxInt = int32ToAuxInt(4)
 +              v0.AddArg2(src, mem)
 +              v1 := b.NewValue0(v.Pos, OpAMD64MOVLstore, types.TypeMem)
 +              v2 := b.NewValue0(v.Pos, OpAMD64MOVLload, typ.UInt32)
 +              v2.AddArg2(src, mem)
 +              v1.AddArg3(dst, v2, mem)
 +              v.AddArg3(dst, v0, v1)
 +              return true
 +      }
 +      // match: (Move [7] dst src mem)
 +      // result: (MOVLstore [3] dst (MOVLload [3] src mem) (MOVLstore dst (MOVLload src mem) mem))
 +      for {
 +              if auxIntToInt64(v.AuxInt) != 7 {
 +                      break
 +              }
 +              dst := v_0
 +              src := v_1
 +              mem := v_2
 +              v.reset(OpAMD64MOVLstore)
 +              v.AuxInt = int32ToAuxInt(3)
 +              v0 := b.NewValue0(v.Pos, OpAMD64MOVLload, typ.UInt32)
 +              v0.AuxInt = int32ToAuxInt(3)
 +              v0.AddArg2(src, mem)
 +              v1 := b.NewValue0(v.Pos, OpAMD64MOVLstore, types.TypeMem)
 +              v2 := b.NewValue0(v.Pos, OpAMD64MOVLload, typ.UInt32)
 +              v2.AddArg2(src, mem)
 +              v1.AddArg3(dst, v2, mem)
 +              v.AddArg3(dst, v0, v1)
 +              return true
 +      }
 +      // match: (Move [9] dst src mem)
 +      // result: (MOVBstore [8] dst (MOVBload [8] src mem) (MOVQstore dst (MOVQload src mem) mem))
 +      for {
 +              if auxIntToInt64(v.AuxInt) != 9 {
 +                      break
 +              }
 +              dst := v_0
 +              src := v_1
 +              mem := v_2
 +              v.reset(OpAMD64MOVBstore)
 +              v.AuxInt = int32ToAuxInt(8)
 +              v0 := b.NewValue0(v.Pos, OpAMD64MOVBload, typ.UInt8)
 +              v0.AuxInt = int32ToAuxInt(8)
 +              v0.AddArg2(src, mem)
 +              v1 := b.NewValue0(v.Pos, OpAMD64MOVQstore, types.TypeMem)
 +              v2 := b.NewValue0(v.Pos, OpAMD64MOVQload, typ.UInt64)
 +              v2.AddArg2(src, mem)
 +              v1.AddArg3(dst, v2, mem)
 +              v.AddArg3(dst, v0, v1)
 +              return true
 +      }
 +      // match: (Move [10] dst src mem)
 +      // result: (MOVWstore [8] dst (MOVWload [8] src mem) (MOVQstore dst (MOVQload src mem) mem))
 +      for {
 +              if auxIntToInt64(v.AuxInt) != 10 {
 +                      break
 +              }
 +              dst := v_0
 +              src := v_1
 +              mem := v_2
 +              v.reset(OpAMD64MOVWstore)
 +              v.AuxInt = int32ToAuxInt(8)
 +              v0 := b.NewValue0(v.Pos, OpAMD64MOVWload, typ.UInt16)
 +              v0.AuxInt = int32ToAuxInt(8)
 +              v0.AddArg2(src, mem)
 +              v1 := b.NewValue0(v.Pos, OpAMD64MOVQstore, types.TypeMem)
 +              v2 := b.NewValue0(v.Pos, OpAMD64MOVQload, typ.UInt64)
 +              v2.AddArg2(src, mem)
 +              v1.AddArg3(dst, v2, mem)
 +              v.AddArg3(dst, v0, v1)
 +              return true
 +      }
 +      // match: (Move [11] dst src mem)
 +      // result: (MOVLstore [7] dst (MOVLload [7] src mem) (MOVQstore dst (MOVQload src mem) mem))
 +      for {
 +              if auxIntToInt64(v.AuxInt) != 11 {
 +                      break
 +              }
 +              dst := v_0
 +              src := v_1
 +              mem := v_2
 +              v.reset(OpAMD64MOVLstore)
 +              v.AuxInt = int32ToAuxInt(7)
 +              v0 := b.NewValue0(v.Pos, OpAMD64MOVLload, typ.UInt32)
 +              v0.AuxInt = int32ToAuxInt(7)
 +              v0.AddArg2(src, mem)
 +              v1 := b.NewValue0(v.Pos, OpAMD64MOVQstore, types.TypeMem)
 +              v2 := b.NewValue0(v.Pos, OpAMD64MOVQload, typ.UInt64)
 +              v2.AddArg2(src, mem)
 +              v1.AddArg3(dst, v2, mem)
 +              v.AddArg3(dst, v0, v1)
 +              return true
 +      }
 +      // match: (Move [12] dst src mem)
 +      // result: (MOVLstore [8] dst (MOVLload [8] src mem) (MOVQstore dst (MOVQload src mem) mem))
 +      for {
 +              if auxIntToInt64(v.AuxInt) != 12 {
 +                      break
 +              }
 +              dst := v_0
 +              src := v_1
 +              mem := v_2
 +              v.reset(OpAMD64MOVLstore)
 +              v.AuxInt = int32ToAuxInt(8)
 +              v0 := b.NewValue0(v.Pos, OpAMD64MOVLload, typ.UInt32)
 +              v0.AuxInt = int32ToAuxInt(8)
 +              v0.AddArg2(src, mem)
 +              v1 := b.NewValue0(v.Pos, OpAMD64MOVQstore, types.TypeMem)
 +              v2 := b.NewValue0(v.Pos, OpAMD64MOVQload, typ.UInt64)
 +              v2.AddArg2(src, mem)
 +              v1.AddArg3(dst, v2, mem)
 +              v.AddArg3(dst, v0, v1)
 +              return true
 +      }
 +      // match: (Move [s] dst src mem)
 +      // cond: s >= 13 && s <= 15
 +      // result: (MOVQstore [int32(s-8)] dst (MOVQload [int32(s-8)] src mem) (MOVQstore dst (MOVQload src mem) mem))
 +      for {
 +              s := auxIntToInt64(v.AuxInt)
 +              dst := v_0
 +              src := v_1
 +              mem := v_2
 +              if !(s >= 13 && s <= 15) {
 +                      break
 +              }
 +              v.reset(OpAMD64MOVQstore)
 +              v.AuxInt = int32ToAuxInt(int32(s - 8))
 +              v0 := b.NewValue0(v.Pos, OpAMD64MOVQload, typ.UInt64)
 +              v0.AuxInt = int32ToAuxInt(int32(s - 8))
 +              v0.AddArg2(src, mem)
 +              v1 := b.NewValue0(v.Pos, OpAMD64MOVQstore, types.TypeMem)
 +              v2 := b.NewValue0(v.Pos, OpAMD64MOVQload, typ.UInt64)
 +              v2.AddArg2(src, mem)
 +              v1.AddArg3(dst, v2, mem)
 +              v.AddArg3(dst, v0, v1)
 +              return true
 +      }
 +      // match: (Move [s] dst src mem)
-       // cond: s > 16 && s%16 != 0 && s%16 <= 8
-       // result: (Move [s-s%16] (OffPtr <dst.Type> dst [s%16]) (OffPtr <src.Type> src [s%16]) (MOVQstore dst (MOVQload src mem) mem))
++      // cond: s > 16 && s < 192 && logLargeCopy(v, s)
++      // result: (LoweredMove [s] dst src mem)
 +      for {
 +              s := auxIntToInt64(v.AuxInt)
 +              dst := v_0
 +              src := v_1
 +              mem := v_2
-               if !(s > 16 && s%16 != 0 && s%16 <= 8) {
++              if !(s > 16 && s < 192 && logLargeCopy(v, s)) {
 +                      break
 +              }
-               v.reset(OpMove)
-               v.AuxInt = int64ToAuxInt(s - s%16)
-               v0 := b.NewValue0(v.Pos, OpOffPtr, dst.Type)
-               v0.AuxInt = int64ToAuxInt(s % 16)
-               v0.AddArg(dst)
-               v1 := b.NewValue0(v.Pos, OpOffPtr, src.Type)
-               v1.AuxInt = int64ToAuxInt(s % 16)
-               v1.AddArg(src)
-               v2 := b.NewValue0(v.Pos, OpAMD64MOVQstore, types.TypeMem)
-               v3 := b.NewValue0(v.Pos, OpAMD64MOVQload, typ.UInt64)
-               v3.AddArg2(src, mem)
-               v2.AddArg3(dst, v3, mem)
-               v.AddArg3(v0, v1, v2)
++              v.reset(OpAMD64LoweredMove)
++              v.AuxInt = int64ToAuxInt(s)
++              v.AddArg3(dst, src, mem)
 +              return true
 +      }
 +      // match: (Move [s] dst src mem)
-       // cond: s > 16 && s%16 != 0 && s%16 > 8
-       // result: (Move [s-s%16] (OffPtr <dst.Type> dst [s%16]) (OffPtr <src.Type> src [s%16]) (MOVOstore dst (MOVOload src mem) mem))
++      // cond: s >= 192 && s <= repMoveThreshold && logLargeCopy(v, s)
++      // result: (LoweredMoveLoop [s] dst src mem)
 +      for {
 +              s := auxIntToInt64(v.AuxInt)
 +              dst := v_0
 +              src := v_1
 +              mem := v_2
-               if !(s > 16 && s%16 != 0 && s%16 > 8) {
++              if !(s >= 192 && s <= repMoveThreshold && logLargeCopy(v, s)) {
 +                      break
 +              }
-               v.reset(OpMove)
-               v.AuxInt = int64ToAuxInt(s - s%16)
-               v0 := b.NewValue0(v.Pos, OpOffPtr, dst.Type)
-               v0.AuxInt = int64ToAuxInt(s % 16)
-               v0.AddArg(dst)
-               v1 := b.NewValue0(v.Pos, OpOffPtr, src.Type)
-               v1.AuxInt = int64ToAuxInt(s % 16)
-               v1.AddArg(src)
-               v2 := b.NewValue0(v.Pos, OpAMD64MOVOstore, types.TypeMem)
-               v3 := b.NewValue0(v.Pos, OpAMD64MOVOload, types.TypeInt128)
-               v3.AddArg2(src, mem)
-               v2.AddArg3(dst, v3, mem)
-               v.AddArg3(v0, v1, v2)
++              v.reset(OpAMD64LoweredMoveLoop)
++              v.AuxInt = int64ToAuxInt(s)
++              v.AddArg3(dst, src, mem)
 +              return true
 +      }
 +      // match: (Move [s] dst src mem)
-       // cond: s > 64 && s <= 16*64 && s%16 == 0 && logLargeCopy(v, s)
-       // result: (DUFFCOPY [s] dst src mem)
++      // cond: s > repMoveThreshold && s%8 != 0
++      // result: (Move [s-s%8] (OffPtr <dst.Type> dst [s%8]) (OffPtr <src.Type> src [s%8]) (MOVQstore dst (MOVQload src mem) mem))
 +      for {
 +              s := auxIntToInt64(v.AuxInt)
 +              dst := v_0
 +              src := v_1
                mem := v_2
-               if !(s > 64 && s <= 16*64 && s%16 == 0 && logLargeCopy(v, s)) {
+               if !(s > repMoveThreshold && s%8 != 0) {
                        break
                }
-               v.reset(OpAMD64DUFFCOPY)
-               v.AuxInt = int64ToAuxInt(s)
-               v.AddArg3(dst, src, mem)
+               v.reset(OpMove)
 -              v.AuxInt = int64ToAuxInt(s - s%8)
 -              v0 := b.NewValue0(v.Pos, OpOffPtr, dst.Type)
 -              v0.AuxInt = int64ToAuxInt(s % 8)
 -              v0.AddArg(dst)
 -              v1 := b.NewValue0(v.Pos, OpOffPtr, src.Type)
 -              v1.AuxInt = int64ToAuxInt(s % 8)
 -              v1.AddArg(src)
 -              v2 := b.NewValue0(v.Pos, OpAMD64MOVQstore, types.TypeMem)
 -              v3 := b.NewValue0(v.Pos, OpAMD64MOVQload, typ.UInt64)
 -              v3.AddArg2(src, mem)
 -              v2.AddArg3(dst, v3, mem)
 -              v.AddArg3(v0, v1, v2)
++              v.AuxInt = int64ToAuxInt(s - s%8)
++              v0 := b.NewValue0(v.Pos, OpOffPtr, dst.Type)
++              v0.AuxInt = int64ToAuxInt(s % 8)
++              v0.AddArg(dst)
++              v1 := b.NewValue0(v.Pos, OpOffPtr, src.Type)
++              v1.AuxInt = int64ToAuxInt(s % 8)
++              v1.AddArg(src)
++              v2 := b.NewValue0(v.Pos, OpAMD64MOVQstore, types.TypeMem)
++              v3 := b.NewValue0(v.Pos, OpAMD64MOVQload, typ.UInt64)
++              v3.AddArg2(src, mem)
++              v2.AddArg3(dst, v3, mem)
++              v.AddArg3(v0, v1, v2)
 +              return true
 +      }
 +      // match: (Move [s] dst src mem)
-       // cond: s > 16*64 && s%8 == 0 && logLargeCopy(v, s)
++      // cond: s > repMoveThreshold && s%8 == 0 && logLargeCopy(v, s)
 +      // result: (REPMOVSQ dst src (MOVQconst [s/8]) mem)
 +      for {
 +              s := auxIntToInt64(v.AuxInt)
 +              dst := v_0
 +              src := v_1
 +              mem := v_2
-               if !(s > 16*64 && s%8 == 0 && logLargeCopy(v, s)) {
++              if !(s > repMoveThreshold && s%8 == 0 && logLargeCopy(v, s)) {
 +                      break
 +              }
 +              v.reset(OpAMD64REPMOVSQ)
 +              v0 := b.NewValue0(v.Pos, OpAMD64MOVQconst, typ.UInt64)
 +              v0.AuxInt = int64ToAuxInt(s / 8)
 +              v.AddArg4(dst, src, v0, mem)
 +              return true
 +      }
 +      return false
 +}
 +func rewriteValueAMD64_OpMulAddMaskedFloat32x16(v *Value) bool {
 +      v_3 := v.Args[3]
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (MulAddMaskedFloat32x16 x y z mask)
 +      // result: (VFMADD213PSMasked512 x y z (VPMOVVec32x16ToM <types.TypeMask> mask))
 +      for {
 +              x := v_0
 +              y := v_1
 +              z := v_2
 +              mask := v_3
 +              v.reset(OpAMD64VFMADD213PSMasked512)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x16ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg4(x, y, z, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpMulAddMaskedFloat32x4(v *Value) bool {
 +      v_3 := v.Args[3]
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (MulAddMaskedFloat32x4 x y z mask)
 +      // result: (VFMADD213PSMasked128 x y z (VPMOVVec32x4ToM <types.TypeMask> mask))
 +      for {
 +              x := v_0
 +              y := v_1
 +              z := v_2
 +              mask := v_3
 +              v.reset(OpAMD64VFMADD213PSMasked128)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x4ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg4(x, y, z, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpMulAddMaskedFloat32x8(v *Value) bool {
 +      v_3 := v.Args[3]
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (MulAddMaskedFloat32x8 x y z mask)
 +      // result: (VFMADD213PSMasked256 x y z (VPMOVVec32x8ToM <types.TypeMask> mask))
 +      for {
 +              x := v_0
 +              y := v_1
 +              z := v_2
 +              mask := v_3
 +              v.reset(OpAMD64VFMADD213PSMasked256)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x8ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg4(x, y, z, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpMulAddMaskedFloat64x2(v *Value) bool {
 +      v_3 := v.Args[3]
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (MulAddMaskedFloat64x2 x y z mask)
 +      // result: (VFMADD213PDMasked128 x y z (VPMOVVec64x2ToM <types.TypeMask> mask))
 +      for {
 +              x := v_0
 +              y := v_1
 +              z := v_2
 +              mask := v_3
 +              v.reset(OpAMD64VFMADD213PDMasked128)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x2ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg4(x, y, z, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpMulAddMaskedFloat64x4(v *Value) bool {
 +      v_3 := v.Args[3]
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (MulAddMaskedFloat64x4 x y z mask)
 +      // result: (VFMADD213PDMasked256 x y z (VPMOVVec64x4ToM <types.TypeMask> mask))
 +      for {
 +              x := v_0
 +              y := v_1
 +              z := v_2
 +              mask := v_3
 +              v.reset(OpAMD64VFMADD213PDMasked256)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x4ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg4(x, y, z, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpMulAddMaskedFloat64x8(v *Value) bool {
 +      v_3 := v.Args[3]
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (MulAddMaskedFloat64x8 x y z mask)
 +      // result: (VFMADD213PDMasked512 x y z (VPMOVVec64x8ToM <types.TypeMask> mask))
 +      for {
 +              x := v_0
 +              y := v_1
 +              z := v_2
 +              mask := v_3
 +              v.reset(OpAMD64VFMADD213PDMasked512)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x8ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg4(x, y, z, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpMulAddSubMaskedFloat32x16(v *Value) bool {
 +      v_3 := v.Args[3]
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (MulAddSubMaskedFloat32x16 x y z mask)
 +      // result: (VFMADDSUB213PSMasked512 x y z (VPMOVVec32x16ToM <types.TypeMask> mask))
 +      for {
 +              x := v_0
 +              y := v_1
 +              z := v_2
 +              mask := v_3
 +              v.reset(OpAMD64VFMADDSUB213PSMasked512)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x16ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg4(x, y, z, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpMulAddSubMaskedFloat32x4(v *Value) bool {
 +      v_3 := v.Args[3]
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (MulAddSubMaskedFloat32x4 x y z mask)
 +      // result: (VFMADDSUB213PSMasked128 x y z (VPMOVVec32x4ToM <types.TypeMask> mask))
 +      for {
 +              x := v_0
 +              y := v_1
 +              z := v_2
 +              mask := v_3
 +              v.reset(OpAMD64VFMADDSUB213PSMasked128)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x4ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg4(x, y, z, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpMulAddSubMaskedFloat32x8(v *Value) bool {
 +      v_3 := v.Args[3]
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (MulAddSubMaskedFloat32x8 x y z mask)
 +      // result: (VFMADDSUB213PSMasked256 x y z (VPMOVVec32x8ToM <types.TypeMask> mask))
 +      for {
 +              x := v_0
 +              y := v_1
 +              z := v_2
 +              mask := v_3
 +              v.reset(OpAMD64VFMADDSUB213PSMasked256)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x8ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg4(x, y, z, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpMulAddSubMaskedFloat64x2(v *Value) bool {
 +      v_3 := v.Args[3]
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (MulAddSubMaskedFloat64x2 x y z mask)
 +      // result: (VFMADDSUB213PDMasked128 x y z (VPMOVVec64x2ToM <types.TypeMask> mask))
 +      for {
 +              x := v_0
 +              y := v_1
 +              z := v_2
 +              mask := v_3
 +              v.reset(OpAMD64VFMADDSUB213PDMasked128)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x2ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg4(x, y, z, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpMulAddSubMaskedFloat64x4(v *Value) bool {
 +      v_3 := v.Args[3]
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (MulAddSubMaskedFloat64x4 x y z mask)
 +      // result: (VFMADDSUB213PDMasked256 x y z (VPMOVVec64x4ToM <types.TypeMask> mask))
 +      for {
 +              x := v_0
 +              y := v_1
 +              z := v_2
 +              mask := v_3
 +              v.reset(OpAMD64VFMADDSUB213PDMasked256)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x4ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg4(x, y, z, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpMulAddSubMaskedFloat64x8(v *Value) bool {
 +      v_3 := v.Args[3]
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (MulAddSubMaskedFloat64x8 x y z mask)
 +      // result: (VFMADDSUB213PDMasked512 x y z (VPMOVVec64x8ToM <types.TypeMask> mask))
 +      for {
 +              x := v_0
 +              y := v_1
 +              z := v_2
 +              mask := v_3
 +              v.reset(OpAMD64VFMADDSUB213PDMasked512)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x8ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg4(x, y, z, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpMulHighMaskedInt16x16(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (MulHighMaskedInt16x16 x y mask)
 +      // result: (VPMULHWMasked256 x y (VPMOVVec16x16ToM <types.TypeMask> mask))
 +      for {
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VPMULHWMasked256)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x16ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg3(x, y, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpMulHighMaskedInt16x32(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (MulHighMaskedInt16x32 x y mask)
 +      // result: (VPMULHWMasked512 x y (VPMOVVec16x32ToM <types.TypeMask> mask))
 +      for {
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VPMULHWMasked512)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x32ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg3(x, y, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpMulHighMaskedInt16x8(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (MulHighMaskedInt16x8 x y mask)
 +      // result: (VPMULHWMasked128 x y (VPMOVVec16x8ToM <types.TypeMask> mask))
 +      for {
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VPMULHWMasked128)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x8ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg3(x, y, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpMulHighMaskedUint16x16(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (MulHighMaskedUint16x16 x y mask)
 +      // result: (VPMULHUWMasked256 x y (VPMOVVec16x16ToM <types.TypeMask> mask))
 +      for {
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VPMULHUWMasked256)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x16ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg3(x, y, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpMulHighMaskedUint16x32(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (MulHighMaskedUint16x32 x y mask)
 +      // result: (VPMULHUWMasked512 x y (VPMOVVec16x32ToM <types.TypeMask> mask))
 +      for {
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VPMULHUWMasked512)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x32ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg3(x, y, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpMulHighMaskedUint16x8(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (MulHighMaskedUint16x8 x y mask)
 +      // result: (VPMULHUWMasked128 x y (VPMOVVec16x8ToM <types.TypeMask> mask))
 +      for {
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VPMULHUWMasked128)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x8ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg3(x, y, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpMulMaskedFloat32x16(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (MulMaskedFloat32x16 x y mask)
 +      // result: (VMULPSMasked512 x y (VPMOVVec32x16ToM <types.TypeMask> mask))
 +      for {
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VMULPSMasked512)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x16ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg3(x, y, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpMulMaskedFloat32x4(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (MulMaskedFloat32x4 x y mask)
 +      // result: (VMULPSMasked128 x y (VPMOVVec32x4ToM <types.TypeMask> mask))
 +      for {
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VMULPSMasked128)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x4ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg3(x, y, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpMulMaskedFloat32x8(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (MulMaskedFloat32x8 x y mask)
 +      // result: (VMULPSMasked256 x y (VPMOVVec32x8ToM <types.TypeMask> mask))
 +      for {
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VMULPSMasked256)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x8ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg3(x, y, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpMulMaskedFloat64x2(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (MulMaskedFloat64x2 x y mask)
 +      // result: (VMULPDMasked128 x y (VPMOVVec64x2ToM <types.TypeMask> mask))
 +      for {
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VMULPDMasked128)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x2ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg3(x, y, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpMulMaskedFloat64x4(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (MulMaskedFloat64x4 x y mask)
 +      // result: (VMULPDMasked256 x y (VPMOVVec64x4ToM <types.TypeMask> mask))
 +      for {
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VMULPDMasked256)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x4ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg3(x, y, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpMulMaskedFloat64x8(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (MulMaskedFloat64x8 x y mask)
 +      // result: (VMULPDMasked512 x y (VPMOVVec64x8ToM <types.TypeMask> mask))
 +      for {
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VMULPDMasked512)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x8ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg3(x, y, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpMulMaskedInt16x16(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (MulMaskedInt16x16 x y mask)
 +      // result: (VPMULLWMasked256 x y (VPMOVVec16x16ToM <types.TypeMask> mask))
 +      for {
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VPMULLWMasked256)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x16ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg3(x, y, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpMulMaskedInt16x32(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (MulMaskedInt16x32 x y mask)
 +      // result: (VPMULLWMasked512 x y (VPMOVVec16x32ToM <types.TypeMask> mask))
 +      for {
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VPMULLWMasked512)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x32ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg3(x, y, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpMulMaskedInt16x8(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (MulMaskedInt16x8 x y mask)
 +      // result: (VPMULLWMasked128 x y (VPMOVVec16x8ToM <types.TypeMask> mask))
 +      for {
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VPMULLWMasked128)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x8ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg3(x, y, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpMulMaskedInt32x16(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (MulMaskedInt32x16 x y mask)
 +      // result: (VPMULLDMasked512 x y (VPMOVVec32x16ToM <types.TypeMask> mask))
 +      for {
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VPMULLDMasked512)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x16ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg3(x, y, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpMulMaskedInt32x4(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (MulMaskedInt32x4 x y mask)
 +      // result: (VPMULLDMasked128 x y (VPMOVVec32x4ToM <types.TypeMask> mask))
 +      for {
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VPMULLDMasked128)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x4ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg3(x, y, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpMulMaskedInt32x8(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (MulMaskedInt32x8 x y mask)
 +      // result: (VPMULLDMasked256 x y (VPMOVVec32x8ToM <types.TypeMask> mask))
 +      for {
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VPMULLDMasked256)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x8ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg3(x, y, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpMulMaskedInt64x2(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (MulMaskedInt64x2 x y mask)
 +      // result: (VPMULLQMasked128 x y (VPMOVVec64x2ToM <types.TypeMask> mask))
 +      for {
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VPMULLQMasked128)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x2ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg3(x, y, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpMulMaskedInt64x4(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (MulMaskedInt64x4 x y mask)
 +      // result: (VPMULLQMasked256 x y (VPMOVVec64x4ToM <types.TypeMask> mask))
 +      for {
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VPMULLQMasked256)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x4ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg3(x, y, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpMulMaskedInt64x8(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (MulMaskedInt64x8 x y mask)
 +      // result: (VPMULLQMasked512 x y (VPMOVVec64x8ToM <types.TypeMask> mask))
 +      for {
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VPMULLQMasked512)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x8ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg3(x, y, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpMulMaskedUint16x16(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (MulMaskedUint16x16 x y mask)
 +      // result: (VPMULLWMasked256 x y (VPMOVVec16x16ToM <types.TypeMask> mask))
 +      for {
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VPMULLWMasked256)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x16ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg3(x, y, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpMulMaskedUint16x32(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (MulMaskedUint16x32 x y mask)
 +      // result: (VPMULLWMasked512 x y (VPMOVVec16x32ToM <types.TypeMask> mask))
 +      for {
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VPMULLWMasked512)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x32ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg3(x, y, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpMulMaskedUint16x8(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (MulMaskedUint16x8 x y mask)
 +      // result: (VPMULLWMasked128 x y (VPMOVVec16x8ToM <types.TypeMask> mask))
 +      for {
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VPMULLWMasked128)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x8ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg3(x, y, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpMulMaskedUint32x16(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (MulMaskedUint32x16 x y mask)
 +      // result: (VPMULLDMasked512 x y (VPMOVVec32x16ToM <types.TypeMask> mask))
 +      for {
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VPMULLDMasked512)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x16ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg3(x, y, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpMulMaskedUint32x4(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (MulMaskedUint32x4 x y mask)
 +      // result: (VPMULLDMasked128 x y (VPMOVVec32x4ToM <types.TypeMask> mask))
 +      for {
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VPMULLDMasked128)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x4ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg3(x, y, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpMulMaskedUint32x8(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (MulMaskedUint32x8 x y mask)
 +      // result: (VPMULLDMasked256 x y (VPMOVVec32x8ToM <types.TypeMask> mask))
 +      for {
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VPMULLDMasked256)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x8ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg3(x, y, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpMulMaskedUint64x2(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (MulMaskedUint64x2 x y mask)
 +      // result: (VPMULLQMasked128 x y (VPMOVVec64x2ToM <types.TypeMask> mask))
 +      for {
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VPMULLQMasked128)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x2ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg3(x, y, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpMulMaskedUint64x4(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (MulMaskedUint64x4 x y mask)
 +      // result: (VPMULLQMasked256 x y (VPMOVVec64x4ToM <types.TypeMask> mask))
 +      for {
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VPMULLQMasked256)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x4ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg3(x, y, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpMulMaskedUint64x8(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (MulMaskedUint64x8 x y mask)
 +      // result: (VPMULLQMasked512 x y (VPMOVVec64x8ToM <types.TypeMask> mask))
 +      for {
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VPMULLQMasked512)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x8ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg3(x, y, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpMulSubAddMaskedFloat32x16(v *Value) bool {
 +      v_3 := v.Args[3]
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (MulSubAddMaskedFloat32x16 x y z mask)
 +      // result: (VFMSUBADD213PSMasked512 x y z (VPMOVVec32x16ToM <types.TypeMask> mask))
 +      for {
 +              x := v_0
 +              y := v_1
 +              z := v_2
 +              mask := v_3
 +              v.reset(OpAMD64VFMSUBADD213PSMasked512)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x16ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg4(x, y, z, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpMulSubAddMaskedFloat32x4(v *Value) bool {
 +      v_3 := v.Args[3]
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (MulSubAddMaskedFloat32x4 x y z mask)
 +      // result: (VFMSUBADD213PSMasked128 x y z (VPMOVVec32x4ToM <types.TypeMask> mask))
 +      for {
 +              x := v_0
 +              y := v_1
 +              z := v_2
 +              mask := v_3
 +              v.reset(OpAMD64VFMSUBADD213PSMasked128)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x4ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg4(x, y, z, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpMulSubAddMaskedFloat32x8(v *Value) bool {
 +      v_3 := v.Args[3]
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (MulSubAddMaskedFloat32x8 x y z mask)
 +      // result: (VFMSUBADD213PSMasked256 x y z (VPMOVVec32x8ToM <types.TypeMask> mask))
 +      for {
 +              x := v_0
 +              y := v_1
 +              z := v_2
 +              mask := v_3
 +              v.reset(OpAMD64VFMSUBADD213PSMasked256)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x8ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg4(x, y, z, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpMulSubAddMaskedFloat64x2(v *Value) bool {
 +      v_3 := v.Args[3]
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (MulSubAddMaskedFloat64x2 x y z mask)
 +      // result: (VFMSUBADD213PDMasked128 x y z (VPMOVVec64x2ToM <types.TypeMask> mask))
 +      for {
 +              x := v_0
 +              y := v_1
 +              z := v_2
 +              mask := v_3
 +              v.reset(OpAMD64VFMSUBADD213PDMasked128)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x2ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg4(x, y, z, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpMulSubAddMaskedFloat64x4(v *Value) bool {
 +      v_3 := v.Args[3]
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (MulSubAddMaskedFloat64x4 x y z mask)
 +      // result: (VFMSUBADD213PDMasked256 x y z (VPMOVVec64x4ToM <types.TypeMask> mask))
 +      for {
 +              x := v_0
 +              y := v_1
 +              z := v_2
 +              mask := v_3
 +              v.reset(OpAMD64VFMSUBADD213PDMasked256)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x4ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg4(x, y, z, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpMulSubAddMaskedFloat64x8(v *Value) bool {
 +      v_3 := v.Args[3]
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (MulSubAddMaskedFloat64x8 x y z mask)
 +      // result: (VFMSUBADD213PDMasked512 x y z (VPMOVVec64x8ToM <types.TypeMask> mask))
 +      for {
 +              x := v_0
 +              y := v_1
 +              z := v_2
 +              mask := v_3
 +              v.reset(OpAMD64VFMSUBADD213PDMasked512)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x8ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg4(x, y, z, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpNeg32F(v *Value) bool {
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      typ := &b.Func.Config.Types
 +      // match: (Neg32F x)
 +      // result: (PXOR x (MOVSSconst <typ.Float32> [float32(math.Copysign(0, -1))]))
 +      for {
 +              x := v_0
 +              v.reset(OpAMD64PXOR)
 +              v0 := b.NewValue0(v.Pos, OpAMD64MOVSSconst, typ.Float32)
 +              v0.AuxInt = float32ToAuxInt(float32(math.Copysign(0, -1)))
 +              v.AddArg2(x, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpNeg64F(v *Value) bool {
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      typ := &b.Func.Config.Types
 +      // match: (Neg64F x)
 +      // result: (PXOR x (MOVSDconst <typ.Float64> [math.Copysign(0, -1)]))
 +      for {
 +              x := v_0
 +              v.reset(OpAMD64PXOR)
 +              v0 := b.NewValue0(v.Pos, OpAMD64MOVSDconst, typ.Float64)
 +              v0.AuxInt = float64ToAuxInt(math.Copysign(0, -1))
 +              v.AddArg2(x, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpNeq16(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (Neq16 x y)
 +      // result: (SETNE (CMPW x y))
 +      for {
 +              x := v_0
 +              y := v_1
 +              v.reset(OpAMD64SETNE)
 +              v0 := b.NewValue0(v.Pos, OpAMD64CMPW, types.TypeFlags)
 +              v0.AddArg2(x, y)
 +              v.AddArg(v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpNeq32(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (Neq32 x y)
 +      // result: (SETNE (CMPL x y))
 +      for {
 +              x := v_0
 +              y := v_1
 +              v.reset(OpAMD64SETNE)
 +              v0 := b.NewValue0(v.Pos, OpAMD64CMPL, types.TypeFlags)
 +              v0.AddArg2(x, y)
 +              v.AddArg(v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpNeq32F(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (Neq32F x y)
 +      // result: (SETNEF (UCOMISS x y))
 +      for {
 +              x := v_0
 +              y := v_1
 +              v.reset(OpAMD64SETNEF)
 +              v0 := b.NewValue0(v.Pos, OpAMD64UCOMISS, types.TypeFlags)
 +              v0.AddArg2(x, y)
 +              v.AddArg(v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpNeq64(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (Neq64 x y)
 +      // result: (SETNE (CMPQ x y))
 +      for {
 +              x := v_0
 +              y := v_1
 +              v.reset(OpAMD64SETNE)
 +              v0 := b.NewValue0(v.Pos, OpAMD64CMPQ, types.TypeFlags)
 +              v0.AddArg2(x, y)
 +              v.AddArg(v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpNeq64F(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (Neq64F x y)
 +      // result: (SETNEF (UCOMISD x y))
 +      for {
 +              x := v_0
 +              y := v_1
 +              v.reset(OpAMD64SETNEF)
 +              v0 := b.NewValue0(v.Pos, OpAMD64UCOMISD, types.TypeFlags)
 +              v0.AddArg2(x, y)
 +              v.AddArg(v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpNeq8(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (Neq8 x y)
 +      // result: (SETNE (CMPB x y))
 +      for {
 +              x := v_0
 +              y := v_1
 +              v.reset(OpAMD64SETNE)
 +              v0 := b.NewValue0(v.Pos, OpAMD64CMPB, types.TypeFlags)
 +              v0.AddArg2(x, y)
 +              v.AddArg(v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpNeqB(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (NeqB x y)
 +      // result: (SETNE (CMPB x y))
 +      for {
 +              x := v_0
 +              y := v_1
 +              v.reset(OpAMD64SETNE)
 +              v0 := b.NewValue0(v.Pos, OpAMD64CMPB, types.TypeFlags)
 +              v0.AddArg2(x, y)
 +              v.AddArg(v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpNeqPtr(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (NeqPtr x y)
 +      // result: (SETNE (CMPQ x y))
 +      for {
 +              x := v_0
 +              y := v_1
 +              v.reset(OpAMD64SETNE)
 +              v0 := b.NewValue0(v.Pos, OpAMD64CMPQ, types.TypeFlags)
 +              v0.AddArg2(x, y)
 +              v.AddArg(v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpNot(v *Value) bool {
 +      v_0 := v.Args[0]
 +      // match: (Not x)
 +      // result: (XORLconst [1] x)
 +      for {
 +              x := v_0
 +              v.reset(OpAMD64XORLconst)
 +              v.AuxInt = int32ToAuxInt(1)
 +              v.AddArg(x)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpNotEqualFloat32x16(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      typ := &b.Func.Config.Types
 +      // match: (NotEqualFloat32x16 x y)
 +      // result: (VPMOVMToVec32x16 (VCMPPS512 [4] x y))
 +      for {
 +              x := v_0
 +              y := v_1
 +              v.reset(OpAMD64VPMOVMToVec32x16)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VCMPPS512, typ.Mask)
 +              v0.AuxInt = uint8ToAuxInt(4)
 +              v0.AddArg2(x, y)
 +              v.AddArg(v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpNotEqualFloat32x4(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      // match: (NotEqualFloat32x4 x y)
 +      // result: (VCMPPS128 [4] x y)
 +      for {
 +              x := v_0
 +              y := v_1
 +              v.reset(OpAMD64VCMPPS128)
 +              v.AuxInt = uint8ToAuxInt(4)
 +              v.AddArg2(x, y)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpNotEqualFloat32x8(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      // match: (NotEqualFloat32x8 x y)
 +      // result: (VCMPPS256 [4] x y)
 +      for {
 +              x := v_0
 +              y := v_1
 +              v.reset(OpAMD64VCMPPS256)
 +              v.AuxInt = uint8ToAuxInt(4)
 +              v.AddArg2(x, y)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpNotEqualFloat64x2(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      // match: (NotEqualFloat64x2 x y)
 +      // result: (VCMPPD128 [4] x y)
 +      for {
 +              x := v_0
 +              y := v_1
 +              v.reset(OpAMD64VCMPPD128)
 +              v.AuxInt = uint8ToAuxInt(4)
 +              v.AddArg2(x, y)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpNotEqualFloat64x4(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      // match: (NotEqualFloat64x4 x y)
 +      // result: (VCMPPD256 [4] x y)
 +      for {
 +              x := v_0
 +              y := v_1
 +              v.reset(OpAMD64VCMPPD256)
 +              v.AuxInt = uint8ToAuxInt(4)
 +              v.AddArg2(x, y)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpNotEqualFloat64x8(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      typ := &b.Func.Config.Types
 +      // match: (NotEqualFloat64x8 x y)
 +      // result: (VPMOVMToVec64x8 (VCMPPD512 [4] x y))
 +      for {
 +              x := v_0
 +              y := v_1
 +              v.reset(OpAMD64VPMOVMToVec64x8)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VCMPPD512, typ.Mask)
 +              v0.AuxInt = uint8ToAuxInt(4)
 +              v0.AddArg2(x, y)
 +              v.AddArg(v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpNotEqualInt16x32(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      typ := &b.Func.Config.Types
 +      // match: (NotEqualInt16x32 x y)
 +      // result: (VPMOVMToVec16x32 (VPCMPW512 [4] x y))
 +      for {
 +              x := v_0
 +              y := v_1
 +              v.reset(OpAMD64VPMOVMToVec16x32)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPCMPW512, typ.Mask)
 +              v0.AuxInt = uint8ToAuxInt(4)
 +              v0.AddArg2(x, y)
 +              v.AddArg(v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpNotEqualInt32x16(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      typ := &b.Func.Config.Types
 +      // match: (NotEqualInt32x16 x y)
 +      // result: (VPMOVMToVec32x16 (VPCMPD512 [4] x y))
 +      for {
 +              x := v_0
 +              y := v_1
 +              v.reset(OpAMD64VPMOVMToVec32x16)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPCMPD512, typ.Mask)
 +              v0.AuxInt = uint8ToAuxInt(4)
 +              v0.AddArg2(x, y)
 +              v.AddArg(v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpNotEqualInt64x8(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      typ := &b.Func.Config.Types
 +      // match: (NotEqualInt64x8 x y)
 +      // result: (VPMOVMToVec64x8 (VPCMPQ512 [4] x y))
 +      for {
 +              x := v_0
 +              y := v_1
 +              v.reset(OpAMD64VPMOVMToVec64x8)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPCMPQ512, typ.Mask)
 +              v0.AuxInt = uint8ToAuxInt(4)
 +              v0.AddArg2(x, y)
 +              v.AddArg(v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpNotEqualInt8x64(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      typ := &b.Func.Config.Types
 +      // match: (NotEqualInt8x64 x y)
 +      // result: (VPMOVMToVec8x64 (VPCMPB512 [4] x y))
 +      for {
 +              x := v_0
 +              y := v_1
 +              v.reset(OpAMD64VPMOVMToVec8x64)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPCMPB512, typ.Mask)
 +              v0.AuxInt = uint8ToAuxInt(4)
 +              v0.AddArg2(x, y)
 +              v.AddArg(v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpNotEqualMaskedFloat32x16(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      typ := &b.Func.Config.Types
 +      // match: (NotEqualMaskedFloat32x16 x y mask)
 +      // result: (VPMOVMToVec32x16 (VCMPPSMasked512 [4] x y (VPMOVVec32x16ToM <types.TypeMask> mask)))
 +      for {
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VPMOVMToVec32x16)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VCMPPSMasked512, typ.Mask)
 +              v0.AuxInt = uint8ToAuxInt(4)
 +              v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x16ToM, types.TypeMask)
 +              v1.AddArg(mask)
 +              v0.AddArg3(x, y, v1)
 +              v.AddArg(v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpNotEqualMaskedFloat32x4(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      typ := &b.Func.Config.Types
 +      // match: (NotEqualMaskedFloat32x4 x y mask)
 +      // result: (VPMOVMToVec32x4 (VCMPPSMasked128 [4] x y (VPMOVVec32x4ToM <types.TypeMask> mask)))
 +      for {
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VPMOVMToVec32x4)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VCMPPSMasked128, typ.Mask)
 +              v0.AuxInt = uint8ToAuxInt(4)
 +              v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x4ToM, types.TypeMask)
 +              v1.AddArg(mask)
 +              v0.AddArg3(x, y, v1)
 +              v.AddArg(v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpNotEqualMaskedFloat32x8(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      typ := &b.Func.Config.Types
 +      // match: (NotEqualMaskedFloat32x8 x y mask)
 +      // result: (VPMOVMToVec32x8 (VCMPPSMasked256 [4] x y (VPMOVVec32x8ToM <types.TypeMask> mask)))
 +      for {
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VPMOVMToVec32x8)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VCMPPSMasked256, typ.Mask)
 +              v0.AuxInt = uint8ToAuxInt(4)
 +              v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x8ToM, types.TypeMask)
 +              v1.AddArg(mask)
 +              v0.AddArg3(x, y, v1)
 +              v.AddArg(v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpNotEqualMaskedFloat64x2(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      typ := &b.Func.Config.Types
 +      // match: (NotEqualMaskedFloat64x2 x y mask)
 +      // result: (VPMOVMToVec64x2 (VCMPPDMasked128 [4] x y (VPMOVVec64x2ToM <types.TypeMask> mask)))
 +      for {
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VPMOVMToVec64x2)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VCMPPDMasked128, typ.Mask)
 +              v0.AuxInt = uint8ToAuxInt(4)
 +              v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x2ToM, types.TypeMask)
 +              v1.AddArg(mask)
 +              v0.AddArg3(x, y, v1)
 +              v.AddArg(v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpNotEqualMaskedFloat64x4(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      typ := &b.Func.Config.Types
 +      // match: (NotEqualMaskedFloat64x4 x y mask)
 +      // result: (VPMOVMToVec64x4 (VCMPPDMasked256 [4] x y (VPMOVVec64x4ToM <types.TypeMask> mask)))
 +      for {
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VPMOVMToVec64x4)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VCMPPDMasked256, typ.Mask)
 +              v0.AuxInt = uint8ToAuxInt(4)
 +              v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x4ToM, types.TypeMask)
 +              v1.AddArg(mask)
 +              v0.AddArg3(x, y, v1)
 +              v.AddArg(v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpNotEqualMaskedFloat64x8(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      typ := &b.Func.Config.Types
 +      // match: (NotEqualMaskedFloat64x8 x y mask)
 +      // result: (VPMOVMToVec64x8 (VCMPPDMasked512 [4] x y (VPMOVVec64x8ToM <types.TypeMask> mask)))
 +      for {
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VPMOVMToVec64x8)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VCMPPDMasked512, typ.Mask)
 +              v0.AuxInt = uint8ToAuxInt(4)
 +              v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x8ToM, types.TypeMask)
 +              v1.AddArg(mask)
 +              v0.AddArg3(x, y, v1)
 +              v.AddArg(v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpNotEqualMaskedInt16x16(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      typ := &b.Func.Config.Types
 +      // match: (NotEqualMaskedInt16x16 x y mask)
 +      // result: (VPMOVMToVec16x16 (VPCMPWMasked256 [4] x y (VPMOVVec16x16ToM <types.TypeMask> mask)))
 +      for {
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VPMOVMToVec16x16)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPCMPWMasked256, typ.Mask)
 +              v0.AuxInt = uint8ToAuxInt(4)
 +              v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x16ToM, types.TypeMask)
 +              v1.AddArg(mask)
 +              v0.AddArg3(x, y, v1)
 +              v.AddArg(v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpNotEqualMaskedInt16x32(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      typ := &b.Func.Config.Types
 +      // match: (NotEqualMaskedInt16x32 x y mask)
 +      // result: (VPMOVMToVec16x32 (VPCMPWMasked512 [4] x y (VPMOVVec16x32ToM <types.TypeMask> mask)))
 +      for {
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VPMOVMToVec16x32)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPCMPWMasked512, typ.Mask)
 +              v0.AuxInt = uint8ToAuxInt(4)
 +              v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x32ToM, types.TypeMask)
 +              v1.AddArg(mask)
 +              v0.AddArg3(x, y, v1)
 +              v.AddArg(v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpNotEqualMaskedInt16x8(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      typ := &b.Func.Config.Types
 +      // match: (NotEqualMaskedInt16x8 x y mask)
 +      // result: (VPMOVMToVec16x8 (VPCMPWMasked128 [4] x y (VPMOVVec16x8ToM <types.TypeMask> mask)))
 +      for {
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VPMOVMToVec16x8)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPCMPWMasked128, typ.Mask)
 +              v0.AuxInt = uint8ToAuxInt(4)
 +              v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x8ToM, types.TypeMask)
 +              v1.AddArg(mask)
 +              v0.AddArg3(x, y, v1)
 +              v.AddArg(v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpNotEqualMaskedInt32x16(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      typ := &b.Func.Config.Types
 +      // match: (NotEqualMaskedInt32x16 x y mask)
 +      // result: (VPMOVMToVec32x16 (VPCMPDMasked512 [4] x y (VPMOVVec32x16ToM <types.TypeMask> mask)))
 +      for {
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VPMOVMToVec32x16)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPCMPDMasked512, typ.Mask)
 +              v0.AuxInt = uint8ToAuxInt(4)
 +              v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x16ToM, types.TypeMask)
 +              v1.AddArg(mask)
 +              v0.AddArg3(x, y, v1)
 +              v.AddArg(v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpNotEqualMaskedInt32x4(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      typ := &b.Func.Config.Types
 +      // match: (NotEqualMaskedInt32x4 x y mask)
 +      // result: (VPMOVMToVec32x4 (VPCMPDMasked128 [4] x y (VPMOVVec32x4ToM <types.TypeMask> mask)))
 +      for {
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VPMOVMToVec32x4)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPCMPDMasked128, typ.Mask)
 +              v0.AuxInt = uint8ToAuxInt(4)
 +              v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x4ToM, types.TypeMask)
 +              v1.AddArg(mask)
 +              v0.AddArg3(x, y, v1)
 +              v.AddArg(v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpNotEqualMaskedInt32x8(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      typ := &b.Func.Config.Types
 +      // match: (NotEqualMaskedInt32x8 x y mask)
 +      // result: (VPMOVMToVec32x8 (VPCMPDMasked256 [4] x y (VPMOVVec32x8ToM <types.TypeMask> mask)))
 +      for {
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VPMOVMToVec32x8)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPCMPDMasked256, typ.Mask)
 +              v0.AuxInt = uint8ToAuxInt(4)
 +              v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x8ToM, types.TypeMask)
 +              v1.AddArg(mask)
 +              v0.AddArg3(x, y, v1)
 +              v.AddArg(v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpNotEqualMaskedInt64x2(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      typ := &b.Func.Config.Types
 +      // match: (NotEqualMaskedInt64x2 x y mask)
 +      // result: (VPMOVMToVec64x2 (VPCMPQMasked128 [4] x y (VPMOVVec64x2ToM <types.TypeMask> mask)))
 +      for {
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VPMOVMToVec64x2)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPCMPQMasked128, typ.Mask)
 +              v0.AuxInt = uint8ToAuxInt(4)
 +              v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x2ToM, types.TypeMask)
 +              v1.AddArg(mask)
 +              v0.AddArg3(x, y, v1)
 +              v.AddArg(v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpNotEqualMaskedInt64x4(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      typ := &b.Func.Config.Types
 +      // match: (NotEqualMaskedInt64x4 x y mask)
 +      // result: (VPMOVMToVec64x4 (VPCMPQMasked256 [4] x y (VPMOVVec64x4ToM <types.TypeMask> mask)))
 +      for {
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VPMOVMToVec64x4)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPCMPQMasked256, typ.Mask)
 +              v0.AuxInt = uint8ToAuxInt(4)
 +              v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x4ToM, types.TypeMask)
 +              v1.AddArg(mask)
 +              v0.AddArg3(x, y, v1)
 +              v.AddArg(v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpNotEqualMaskedInt64x8(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      typ := &b.Func.Config.Types
 +      // match: (NotEqualMaskedInt64x8 x y mask)
 +      // result: (VPMOVMToVec64x8 (VPCMPQMasked512 [4] x y (VPMOVVec64x8ToM <types.TypeMask> mask)))
 +      for {
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VPMOVMToVec64x8)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPCMPQMasked512, typ.Mask)
 +              v0.AuxInt = uint8ToAuxInt(4)
 +              v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x8ToM, types.TypeMask)
 +              v1.AddArg(mask)
 +              v0.AddArg3(x, y, v1)
 +              v.AddArg(v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpNotEqualMaskedInt8x16(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      typ := &b.Func.Config.Types
 +      // match: (NotEqualMaskedInt8x16 x y mask)
 +      // result: (VPMOVMToVec8x16 (VPCMPBMasked128 [4] x y (VPMOVVec8x16ToM <types.TypeMask> mask)))
 +      for {
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VPMOVMToVec8x16)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPCMPBMasked128, typ.Mask)
 +              v0.AuxInt = uint8ToAuxInt(4)
 +              v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec8x16ToM, types.TypeMask)
 +              v1.AddArg(mask)
 +              v0.AddArg3(x, y, v1)
 +              v.AddArg(v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpNotEqualMaskedInt8x32(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      typ := &b.Func.Config.Types
 +      // match: (NotEqualMaskedInt8x32 x y mask)
 +      // result: (VPMOVMToVec8x32 (VPCMPBMasked256 [4] x y (VPMOVVec8x32ToM <types.TypeMask> mask)))
 +      for {
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VPMOVMToVec8x32)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPCMPBMasked256, typ.Mask)
 +              v0.AuxInt = uint8ToAuxInt(4)
 +              v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec8x32ToM, types.TypeMask)
 +              v1.AddArg(mask)
 +              v0.AddArg3(x, y, v1)
 +              v.AddArg(v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpNotEqualMaskedInt8x64(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      typ := &b.Func.Config.Types
 +      // match: (NotEqualMaskedInt8x64 x y mask)
 +      // result: (VPMOVMToVec8x64 (VPCMPBMasked512 [4] x y (VPMOVVec8x64ToM <types.TypeMask> mask)))
 +      for {
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VPMOVMToVec8x64)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPCMPBMasked512, typ.Mask)
 +              v0.AuxInt = uint8ToAuxInt(4)
 +              v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec8x64ToM, types.TypeMask)
 +              v1.AddArg(mask)
 +              v0.AddArg3(x, y, v1)
 +              v.AddArg(v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpNotEqualMaskedUint16x16(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      typ := &b.Func.Config.Types
 +      // match: (NotEqualMaskedUint16x16 x y mask)
 +      // result: (VPMOVMToVec16x16 (VPCMPUWMasked256 [4] x y (VPMOVVec16x16ToM <types.TypeMask> mask)))
 +      for {
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VPMOVMToVec16x16)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPCMPUWMasked256, typ.Mask)
 +              v0.AuxInt = uint8ToAuxInt(4)
 +              v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x16ToM, types.TypeMask)
 +              v1.AddArg(mask)
 +              v0.AddArg3(x, y, v1)
 +              v.AddArg(v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpNotEqualMaskedUint16x32(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      typ := &b.Func.Config.Types
 +      // match: (NotEqualMaskedUint16x32 x y mask)
 +      // result: (VPMOVMToVec16x32 (VPCMPUWMasked512 [4] x y (VPMOVVec16x32ToM <types.TypeMask> mask)))
 +      for {
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VPMOVMToVec16x32)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPCMPUWMasked512, typ.Mask)
 +              v0.AuxInt = uint8ToAuxInt(4)
 +              v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x32ToM, types.TypeMask)
 +              v1.AddArg(mask)
 +              v0.AddArg3(x, y, v1)
 +              v.AddArg(v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpNotEqualMaskedUint16x8(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      typ := &b.Func.Config.Types
 +      // match: (NotEqualMaskedUint16x8 x y mask)
 +      // result: (VPMOVMToVec16x8 (VPCMPUWMasked128 [4] x y (VPMOVVec16x8ToM <types.TypeMask> mask)))
 +      for {
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VPMOVMToVec16x8)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPCMPUWMasked128, typ.Mask)
 +              v0.AuxInt = uint8ToAuxInt(4)
 +              v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x8ToM, types.TypeMask)
 +              v1.AddArg(mask)
 +              v0.AddArg3(x, y, v1)
 +              v.AddArg(v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpNotEqualMaskedUint32x16(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      typ := &b.Func.Config.Types
 +      // match: (NotEqualMaskedUint32x16 x y mask)
 +      // result: (VPMOVMToVec32x16 (VPCMPUDMasked512 [4] x y (VPMOVVec32x16ToM <types.TypeMask> mask)))
 +      for {
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VPMOVMToVec32x16)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPCMPUDMasked512, typ.Mask)
 +              v0.AuxInt = uint8ToAuxInt(4)
 +              v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x16ToM, types.TypeMask)
 +              v1.AddArg(mask)
 +              v0.AddArg3(x, y, v1)
 +              v.AddArg(v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpNotEqualMaskedUint32x4(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      typ := &b.Func.Config.Types
 +      // match: (NotEqualMaskedUint32x4 x y mask)
 +      // result: (VPMOVMToVec32x4 (VPCMPUDMasked128 [4] x y (VPMOVVec32x4ToM <types.TypeMask> mask)))
 +      for {
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VPMOVMToVec32x4)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPCMPUDMasked128, typ.Mask)
 +              v0.AuxInt = uint8ToAuxInt(4)
 +              v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x4ToM, types.TypeMask)
 +              v1.AddArg(mask)
 +              v0.AddArg3(x, y, v1)
 +              v.AddArg(v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpNotEqualMaskedUint32x8(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      typ := &b.Func.Config.Types
 +      // match: (NotEqualMaskedUint32x8 x y mask)
 +      // result: (VPMOVMToVec32x8 (VPCMPUDMasked256 [4] x y (VPMOVVec32x8ToM <types.TypeMask> mask)))
 +      for {
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VPMOVMToVec32x8)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPCMPUDMasked256, typ.Mask)
 +              v0.AuxInt = uint8ToAuxInt(4)
 +              v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x8ToM, types.TypeMask)
 +              v1.AddArg(mask)
 +              v0.AddArg3(x, y, v1)
 +              v.AddArg(v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpNotEqualMaskedUint64x2(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      typ := &b.Func.Config.Types
 +      // match: (NotEqualMaskedUint64x2 x y mask)
 +      // result: (VPMOVMToVec64x2 (VPCMPUQMasked128 [4] x y (VPMOVVec64x2ToM <types.TypeMask> mask)))
 +      for {
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VPMOVMToVec64x2)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPCMPUQMasked128, typ.Mask)
 +              v0.AuxInt = uint8ToAuxInt(4)
 +              v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x2ToM, types.TypeMask)
 +              v1.AddArg(mask)
 +              v0.AddArg3(x, y, v1)
 +              v.AddArg(v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpNotEqualMaskedUint64x4(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      typ := &b.Func.Config.Types
 +      // match: (NotEqualMaskedUint64x4 x y mask)
 +      // result: (VPMOVMToVec64x4 (VPCMPUQMasked256 [4] x y (VPMOVVec64x4ToM <types.TypeMask> mask)))
 +      for {
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VPMOVMToVec64x4)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPCMPUQMasked256, typ.Mask)
 +              v0.AuxInt = uint8ToAuxInt(4)
 +              v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x4ToM, types.TypeMask)
 +              v1.AddArg(mask)
 +              v0.AddArg3(x, y, v1)
 +              v.AddArg(v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpNotEqualMaskedUint64x8(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      typ := &b.Func.Config.Types
 +      // match: (NotEqualMaskedUint64x8 x y mask)
 +      // result: (VPMOVMToVec64x8 (VPCMPUQMasked512 [4] x y (VPMOVVec64x8ToM <types.TypeMask> mask)))
 +      for {
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VPMOVMToVec64x8)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPCMPUQMasked512, typ.Mask)
 +              v0.AuxInt = uint8ToAuxInt(4)
 +              v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x8ToM, types.TypeMask)
 +              v1.AddArg(mask)
 +              v0.AddArg3(x, y, v1)
 +              v.AddArg(v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpNotEqualMaskedUint8x16(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      typ := &b.Func.Config.Types
 +      // match: (NotEqualMaskedUint8x16 x y mask)
 +      // result: (VPMOVMToVec8x16 (VPCMPUBMasked128 [4] x y (VPMOVVec8x16ToM <types.TypeMask> mask)))
 +      for {
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VPMOVMToVec8x16)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPCMPUBMasked128, typ.Mask)
 +              v0.AuxInt = uint8ToAuxInt(4)
 +              v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec8x16ToM, types.TypeMask)
 +              v1.AddArg(mask)
 +              v0.AddArg3(x, y, v1)
 +              v.AddArg(v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpNotEqualMaskedUint8x32(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      typ := &b.Func.Config.Types
 +      // match: (NotEqualMaskedUint8x32 x y mask)
 +      // result: (VPMOVMToVec8x32 (VPCMPUBMasked256 [4] x y (VPMOVVec8x32ToM <types.TypeMask> mask)))
 +      for {
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VPMOVMToVec8x32)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPCMPUBMasked256, typ.Mask)
 +              v0.AuxInt = uint8ToAuxInt(4)
 +              v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec8x32ToM, types.TypeMask)
 +              v1.AddArg(mask)
 +              v0.AddArg3(x, y, v1)
 +              v.AddArg(v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpNotEqualMaskedUint8x64(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      typ := &b.Func.Config.Types
 +      // match: (NotEqualMaskedUint8x64 x y mask)
 +      // result: (VPMOVMToVec8x64 (VPCMPUBMasked512 [4] x y (VPMOVVec8x64ToM <types.TypeMask> mask)))
 +      for {
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VPMOVMToVec8x64)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPCMPUBMasked512, typ.Mask)
 +              v0.AuxInt = uint8ToAuxInt(4)
 +              v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec8x64ToM, types.TypeMask)
 +              v1.AddArg(mask)
 +              v0.AddArg3(x, y, v1)
 +              v.AddArg(v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpNotEqualUint16x32(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      typ := &b.Func.Config.Types
 +      // match: (NotEqualUint16x32 x y)
 +      // result: (VPMOVMToVec16x32 (VPCMPUW512 [4] x y))
 +      for {
 +              x := v_0
 +              y := v_1
 +              v.reset(OpAMD64VPMOVMToVec16x32)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPCMPUW512, typ.Mask)
 +              v0.AuxInt = uint8ToAuxInt(4)
 +              v0.AddArg2(x, y)
 +              v.AddArg(v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpNotEqualUint32x16(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      typ := &b.Func.Config.Types
 +      // match: (NotEqualUint32x16 x y)
 +      // result: (VPMOVMToVec32x16 (VPCMPUD512 [4] x y))
 +      for {
 +              x := v_0
 +              y := v_1
 +              v.reset(OpAMD64VPMOVMToVec32x16)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPCMPUD512, typ.Mask)
 +              v0.AuxInt = uint8ToAuxInt(4)
 +              v0.AddArg2(x, y)
 +              v.AddArg(v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpNotEqualUint64x8(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      typ := &b.Func.Config.Types
 +      // match: (NotEqualUint64x8 x y)
 +      // result: (VPMOVMToVec64x8 (VPCMPUQ512 [4] x y))
 +      for {
 +              x := v_0
 +              y := v_1
 +              v.reset(OpAMD64VPMOVMToVec64x8)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPCMPUQ512, typ.Mask)
 +              v0.AuxInt = uint8ToAuxInt(4)
 +              v0.AddArg2(x, y)
 +              v.AddArg(v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpNotEqualUint8x64(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      typ := &b.Func.Config.Types
 +      // match: (NotEqualUint8x64 x y)
 +      // result: (VPMOVMToVec8x64 (VPCMPUB512 [4] x y))
 +      for {
 +              x := v_0
 +              y := v_1
 +              v.reset(OpAMD64VPMOVMToVec8x64)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPCMPUB512, typ.Mask)
 +              v0.AuxInt = uint8ToAuxInt(4)
 +              v0.AddArg2(x, y)
 +              v.AddArg(v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpOffPtr(v *Value) bool {
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      typ := &b.Func.Config.Types
 +      // match: (OffPtr [off] ptr)
 +      // cond: is32Bit(off)
 +      // result: (ADDQconst [int32(off)] ptr)
 +      for {
 +              off := auxIntToInt64(v.AuxInt)
 +              ptr := v_0
 +              if !(is32Bit(off)) {
 +                      break
 +              }
 +              v.reset(OpAMD64ADDQconst)
 +              v.AuxInt = int32ToAuxInt(int32(off))
 +              v.AddArg(ptr)
 +              return true
 +      }
 +      // match: (OffPtr [off] ptr)
 +      // result: (ADDQ (MOVQconst [off]) ptr)
 +      for {
 +              off := auxIntToInt64(v.AuxInt)
 +              ptr := v_0
 +              v.reset(OpAMD64ADDQ)
 +              v0 := b.NewValue0(v.Pos, OpAMD64MOVQconst, typ.UInt64)
 +              v0.AuxInt = int64ToAuxInt(off)
 +              v.AddArg2(v0, ptr)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpOnesCountMaskedInt16x16(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (OnesCountMaskedInt16x16 x mask)
 +      // result: (VPOPCNTWMasked256 x (VPMOVVec16x16ToM <types.TypeMask> mask))
 +      for {
 +              x := v_0
 +              mask := v_1
 +              v.reset(OpAMD64VPOPCNTWMasked256)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x16ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg2(x, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpOnesCountMaskedInt16x32(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (OnesCountMaskedInt16x32 x mask)
 +      // result: (VPOPCNTWMasked512 x (VPMOVVec16x32ToM <types.TypeMask> mask))
 +      for {
 +              x := v_0
 +              mask := v_1
 +              v.reset(OpAMD64VPOPCNTWMasked512)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x32ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg2(x, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpOnesCountMaskedInt16x8(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (OnesCountMaskedInt16x8 x mask)
 +      // result: (VPOPCNTWMasked128 x (VPMOVVec16x8ToM <types.TypeMask> mask))
 +      for {
 +              x := v_0
 +              mask := v_1
 +              v.reset(OpAMD64VPOPCNTWMasked128)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x8ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg2(x, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpOnesCountMaskedInt32x16(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (OnesCountMaskedInt32x16 x mask)
 +      // result: (VPOPCNTDMasked512 x (VPMOVVec32x16ToM <types.TypeMask> mask))
 +      for {
 +              x := v_0
 +              mask := v_1
 +              v.reset(OpAMD64VPOPCNTDMasked512)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x16ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg2(x, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpOnesCountMaskedInt32x4(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (OnesCountMaskedInt32x4 x mask)
 +      // result: (VPOPCNTDMasked128 x (VPMOVVec32x4ToM <types.TypeMask> mask))
 +      for {
 +              x := v_0
 +              mask := v_1
 +              v.reset(OpAMD64VPOPCNTDMasked128)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x4ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg2(x, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpOnesCountMaskedInt32x8(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (OnesCountMaskedInt32x8 x mask)
 +      // result: (VPOPCNTDMasked256 x (VPMOVVec32x8ToM <types.TypeMask> mask))
 +      for {
 +              x := v_0
 +              mask := v_1
 +              v.reset(OpAMD64VPOPCNTDMasked256)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x8ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg2(x, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpOnesCountMaskedInt64x2(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (OnesCountMaskedInt64x2 x mask)
 +      // result: (VPOPCNTQMasked128 x (VPMOVVec64x2ToM <types.TypeMask> mask))
 +      for {
 +              x := v_0
 +              mask := v_1
 +              v.reset(OpAMD64VPOPCNTQMasked128)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x2ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg2(x, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpOnesCountMaskedInt64x4(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (OnesCountMaskedInt64x4 x mask)
 +      // result: (VPOPCNTQMasked256 x (VPMOVVec64x4ToM <types.TypeMask> mask))
 +      for {
 +              x := v_0
 +              mask := v_1
 +              v.reset(OpAMD64VPOPCNTQMasked256)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x4ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg2(x, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpOnesCountMaskedInt64x8(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (OnesCountMaskedInt64x8 x mask)
 +      // result: (VPOPCNTQMasked512 x (VPMOVVec64x8ToM <types.TypeMask> mask))
 +      for {
 +              x := v_0
 +              mask := v_1
 +              v.reset(OpAMD64VPOPCNTQMasked512)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x8ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg2(x, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpOnesCountMaskedInt8x16(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (OnesCountMaskedInt8x16 x mask)
 +      // result: (VPOPCNTBMasked128 x (VPMOVVec8x16ToM <types.TypeMask> mask))
 +      for {
 +              x := v_0
 +              mask := v_1
 +              v.reset(OpAMD64VPOPCNTBMasked128)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec8x16ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg2(x, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpOnesCountMaskedInt8x32(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (OnesCountMaskedInt8x32 x mask)
 +      // result: (VPOPCNTBMasked256 x (VPMOVVec8x32ToM <types.TypeMask> mask))
 +      for {
 +              x := v_0
 +              mask := v_1
 +              v.reset(OpAMD64VPOPCNTBMasked256)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec8x32ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg2(x, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpOnesCountMaskedInt8x64(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (OnesCountMaskedInt8x64 x mask)
 +      // result: (VPOPCNTBMasked512 x (VPMOVVec8x64ToM <types.TypeMask> mask))
 +      for {
 +              x := v_0
 +              mask := v_1
 +              v.reset(OpAMD64VPOPCNTBMasked512)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec8x64ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg2(x, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpOnesCountMaskedUint16x16(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (OnesCountMaskedUint16x16 x mask)
 +      // result: (VPOPCNTWMasked256 x (VPMOVVec16x16ToM <types.TypeMask> mask))
 +      for {
 +              x := v_0
 +              mask := v_1
 +              v.reset(OpAMD64VPOPCNTWMasked256)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x16ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg2(x, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpOnesCountMaskedUint16x32(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (OnesCountMaskedUint16x32 x mask)
 +      // result: (VPOPCNTWMasked512 x (VPMOVVec16x32ToM <types.TypeMask> mask))
 +      for {
 +              x := v_0
 +              mask := v_1
 +              v.reset(OpAMD64VPOPCNTWMasked512)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x32ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg2(x, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpOnesCountMaskedUint16x8(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (OnesCountMaskedUint16x8 x mask)
 +      // result: (VPOPCNTWMasked128 x (VPMOVVec16x8ToM <types.TypeMask> mask))
 +      for {
 +              x := v_0
 +              mask := v_1
 +              v.reset(OpAMD64VPOPCNTWMasked128)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x8ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg2(x, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpOnesCountMaskedUint32x16(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (OnesCountMaskedUint32x16 x mask)
 +      // result: (VPOPCNTDMasked512 x (VPMOVVec32x16ToM <types.TypeMask> mask))
 +      for {
 +              x := v_0
 +              mask := v_1
 +              v.reset(OpAMD64VPOPCNTDMasked512)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x16ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg2(x, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpOnesCountMaskedUint32x4(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (OnesCountMaskedUint32x4 x mask)
 +      // result: (VPOPCNTDMasked128 x (VPMOVVec32x4ToM <types.TypeMask> mask))
 +      for {
 +              x := v_0
 +              mask := v_1
 +              v.reset(OpAMD64VPOPCNTDMasked128)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x4ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg2(x, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpOnesCountMaskedUint32x8(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (OnesCountMaskedUint32x8 x mask)
 +      // result: (VPOPCNTDMasked256 x (VPMOVVec32x8ToM <types.TypeMask> mask))
 +      for {
 +              x := v_0
 +              mask := v_1
 +              v.reset(OpAMD64VPOPCNTDMasked256)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x8ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg2(x, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpOnesCountMaskedUint64x2(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (OnesCountMaskedUint64x2 x mask)
 +      // result: (VPOPCNTQMasked128 x (VPMOVVec64x2ToM <types.TypeMask> mask))
 +      for {
 +              x := v_0
 +              mask := v_1
 +              v.reset(OpAMD64VPOPCNTQMasked128)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x2ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg2(x, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpOnesCountMaskedUint64x4(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (OnesCountMaskedUint64x4 x mask)
 +      // result: (VPOPCNTQMasked256 x (VPMOVVec64x4ToM <types.TypeMask> mask))
 +      for {
 +              x := v_0
 +              mask := v_1
 +              v.reset(OpAMD64VPOPCNTQMasked256)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x4ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg2(x, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpOnesCountMaskedUint64x8(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (OnesCountMaskedUint64x8 x mask)
 +      // result: (VPOPCNTQMasked512 x (VPMOVVec64x8ToM <types.TypeMask> mask))
 +      for {
 +              x := v_0
 +              mask := v_1
 +              v.reset(OpAMD64VPOPCNTQMasked512)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x8ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg2(x, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpOnesCountMaskedUint8x16(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (OnesCountMaskedUint8x16 x mask)
 +      // result: (VPOPCNTBMasked128 x (VPMOVVec8x16ToM <types.TypeMask> mask))
 +      for {
 +              x := v_0
 +              mask := v_1
 +              v.reset(OpAMD64VPOPCNTBMasked128)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec8x16ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg2(x, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpOnesCountMaskedUint8x32(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (OnesCountMaskedUint8x32 x mask)
 +      // result: (VPOPCNTBMasked256 x (VPMOVVec8x32ToM <types.TypeMask> mask))
 +      for {
 +              x := v_0
 +              mask := v_1
 +              v.reset(OpAMD64VPOPCNTBMasked256)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec8x32ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg2(x, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpOnesCountMaskedUint8x64(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (OnesCountMaskedUint8x64 x mask)
 +      // result: (VPOPCNTBMasked512 x (VPMOVVec8x64ToM <types.TypeMask> mask))
 +      for {
 +              x := v_0
 +              mask := v_1
 +              v.reset(OpAMD64VPOPCNTBMasked512)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec8x64ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg2(x, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpOrMaskedInt32x16(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (OrMaskedInt32x16 x y mask)
 +      // result: (VPORDMasked512 x y (VPMOVVec32x16ToM <types.TypeMask> mask))
 +      for {
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VPORDMasked512)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x16ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg3(x, y, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpOrMaskedInt32x4(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (OrMaskedInt32x4 x y mask)
 +      // result: (VPORDMasked128 x y (VPMOVVec32x4ToM <types.TypeMask> mask))
 +      for {
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VPORDMasked128)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x4ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg3(x, y, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpOrMaskedInt32x8(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (OrMaskedInt32x8 x y mask)
 +      // result: (VPORDMasked256 x y (VPMOVVec32x8ToM <types.TypeMask> mask))
 +      for {
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VPORDMasked256)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x8ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg3(x, y, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpOrMaskedInt64x2(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (OrMaskedInt64x2 x y mask)
 +      // result: (VPORQMasked128 x y (VPMOVVec64x2ToM <types.TypeMask> mask))
 +      for {
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VPORQMasked128)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x2ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg3(x, y, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpOrMaskedInt64x4(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (OrMaskedInt64x4 x y mask)
 +      // result: (VPORQMasked256 x y (VPMOVVec64x4ToM <types.TypeMask> mask))
 +      for {
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VPORQMasked256)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x4ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg3(x, y, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpOrMaskedInt64x8(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (OrMaskedInt64x8 x y mask)
 +      // result: (VPORQMasked512 x y (VPMOVVec64x8ToM <types.TypeMask> mask))
 +      for {
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VPORQMasked512)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x8ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg3(x, y, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpOrMaskedUint32x16(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (OrMaskedUint32x16 x y mask)
 +      // result: (VPORDMasked512 x y (VPMOVVec32x16ToM <types.TypeMask> mask))
 +      for {
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VPORDMasked512)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x16ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg3(x, y, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpOrMaskedUint32x4(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (OrMaskedUint32x4 x y mask)
 +      // result: (VPORDMasked128 x y (VPMOVVec32x4ToM <types.TypeMask> mask))
 +      for {
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VPORDMasked128)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x4ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg3(x, y, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpOrMaskedUint32x8(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (OrMaskedUint32x8 x y mask)
 +      // result: (VPORDMasked256 x y (VPMOVVec32x8ToM <types.TypeMask> mask))
 +      for {
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VPORDMasked256)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x8ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg3(x, y, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpOrMaskedUint64x2(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (OrMaskedUint64x2 x y mask)
 +      // result: (VPORQMasked128 x y (VPMOVVec64x2ToM <types.TypeMask> mask))
 +      for {
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VPORQMasked128)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x2ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg3(x, y, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpOrMaskedUint64x4(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (OrMaskedUint64x4 x y mask)
 +      // result: (VPORQMasked256 x y (VPMOVVec64x4ToM <types.TypeMask> mask))
 +      for {
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VPORQMasked256)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x4ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg3(x, y, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpOrMaskedUint64x8(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (OrMaskedUint64x8 x y mask)
 +      // result: (VPORQMasked512 x y (VPMOVVec64x8ToM <types.TypeMask> mask))
 +      for {
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VPORQMasked512)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x8ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg3(x, y, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpPermute2MaskedFloat32x16(v *Value) bool {
 +      v_3 := v.Args[3]
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (Permute2MaskedFloat32x16 x y z mask)
 +      // result: (VPERMI2PSMasked512 x y z (VPMOVVec32x16ToM <types.TypeMask> mask))
 +      for {
 +              x := v_0
 +              y := v_1
 +              z := v_2
 +              mask := v_3
 +              v.reset(OpAMD64VPERMI2PSMasked512)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x16ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg4(x, y, z, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpPermute2MaskedFloat32x4(v *Value) bool {
 +      v_3 := v.Args[3]
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (Permute2MaskedFloat32x4 x y z mask)
 +      // result: (VPERMI2PSMasked128 x y z (VPMOVVec32x4ToM <types.TypeMask> mask))
 +      for {
 +              x := v_0
 +              y := v_1
 +              z := v_2
 +              mask := v_3
 +              v.reset(OpAMD64VPERMI2PSMasked128)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x4ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg4(x, y, z, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpPermute2MaskedFloat32x8(v *Value) bool {
 +      v_3 := v.Args[3]
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (Permute2MaskedFloat32x8 x y z mask)
 +      // result: (VPERMI2PSMasked256 x y z (VPMOVVec32x8ToM <types.TypeMask> mask))
 +      for {
 +              x := v_0
 +              y := v_1
 +              z := v_2
 +              mask := v_3
 +              v.reset(OpAMD64VPERMI2PSMasked256)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x8ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg4(x, y, z, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpPermute2MaskedFloat64x2(v *Value) bool {
 +      v_3 := v.Args[3]
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (Permute2MaskedFloat64x2 x y z mask)
 +      // result: (VPERMI2PDMasked128 x y z (VPMOVVec64x2ToM <types.TypeMask> mask))
 +      for {
 +              x := v_0
 +              y := v_1
 +              z := v_2
 +              mask := v_3
 +              v.reset(OpAMD64VPERMI2PDMasked128)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x2ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg4(x, y, z, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpPermute2MaskedFloat64x4(v *Value) bool {
 +      v_3 := v.Args[3]
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (Permute2MaskedFloat64x4 x y z mask)
 +      // result: (VPERMI2PDMasked256 x y z (VPMOVVec64x4ToM <types.TypeMask> mask))
 +      for {
 +              x := v_0
 +              y := v_1
 +              z := v_2
 +              mask := v_3
 +              v.reset(OpAMD64VPERMI2PDMasked256)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x4ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg4(x, y, z, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpPermute2MaskedFloat64x8(v *Value) bool {
 +      v_3 := v.Args[3]
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (Permute2MaskedFloat64x8 x y z mask)
 +      // result: (VPERMI2PDMasked512 x y z (VPMOVVec64x8ToM <types.TypeMask> mask))
 +      for {
 +              x := v_0
 +              y := v_1
 +              z := v_2
 +              mask := v_3
 +              v.reset(OpAMD64VPERMI2PDMasked512)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x8ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg4(x, y, z, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpPermute2MaskedInt16x16(v *Value) bool {
 +      v_3 := v.Args[3]
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (Permute2MaskedInt16x16 x y z mask)
 +      // result: (VPERMI2WMasked256 x y z (VPMOVVec16x16ToM <types.TypeMask> mask))
 +      for {
 +              x := v_0
 +              y := v_1
 +              z := v_2
 +              mask := v_3
 +              v.reset(OpAMD64VPERMI2WMasked256)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x16ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg4(x, y, z, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpPermute2MaskedInt16x32(v *Value) bool {
 +      v_3 := v.Args[3]
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (Permute2MaskedInt16x32 x y z mask)
 +      // result: (VPERMI2WMasked512 x y z (VPMOVVec16x32ToM <types.TypeMask> mask))
 +      for {
 +              x := v_0
 +              y := v_1
 +              z := v_2
 +              mask := v_3
 +              v.reset(OpAMD64VPERMI2WMasked512)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x32ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg4(x, y, z, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpPermute2MaskedInt16x8(v *Value) bool {
 +      v_3 := v.Args[3]
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (Permute2MaskedInt16x8 x y z mask)
 +      // result: (VPERMI2WMasked128 x y z (VPMOVVec16x8ToM <types.TypeMask> mask))
 +      for {
 +              x := v_0
 +              y := v_1
 +              z := v_2
 +              mask := v_3
 +              v.reset(OpAMD64VPERMI2WMasked128)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x8ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg4(x, y, z, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpPermute2MaskedInt32x16(v *Value) bool {
 +      v_3 := v.Args[3]
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (Permute2MaskedInt32x16 x y z mask)
 +      // result: (VPERMI2DMasked512 x y z (VPMOVVec32x16ToM <types.TypeMask> mask))
 +      for {
 +              x := v_0
 +              y := v_1
 +              z := v_2
 +              mask := v_3
 +              v.reset(OpAMD64VPERMI2DMasked512)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x16ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg4(x, y, z, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpPermute2MaskedInt32x4(v *Value) bool {
 +      v_3 := v.Args[3]
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (Permute2MaskedInt32x4 x y z mask)
 +      // result: (VPERMI2DMasked128 x y z (VPMOVVec32x4ToM <types.TypeMask> mask))
 +      for {
 +              x := v_0
 +              y := v_1
 +              z := v_2
 +              mask := v_3
 +              v.reset(OpAMD64VPERMI2DMasked128)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x4ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg4(x, y, z, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpPermute2MaskedInt32x8(v *Value) bool {
 +      v_3 := v.Args[3]
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (Permute2MaskedInt32x8 x y z mask)
 +      // result: (VPERMI2DMasked256 x y z (VPMOVVec32x8ToM <types.TypeMask> mask))
 +      for {
 +              x := v_0
 +              y := v_1
 +              z := v_2
 +              mask := v_3
 +              v.reset(OpAMD64VPERMI2DMasked256)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x8ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg4(x, y, z, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpPermute2MaskedInt64x2(v *Value) bool {
 +      v_3 := v.Args[3]
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (Permute2MaskedInt64x2 x y z mask)
 +      // result: (VPERMI2QMasked128 x y z (VPMOVVec64x2ToM <types.TypeMask> mask))
 +      for {
 +              x := v_0
 +              y := v_1
 +              z := v_2
 +              mask := v_3
 +              v.reset(OpAMD64VPERMI2QMasked128)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x2ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg4(x, y, z, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpPermute2MaskedInt64x4(v *Value) bool {
 +      v_3 := v.Args[3]
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (Permute2MaskedInt64x4 x y z mask)
 +      // result: (VPERMI2QMasked256 x y z (VPMOVVec64x4ToM <types.TypeMask> mask))
 +      for {
 +              x := v_0
 +              y := v_1
 +              z := v_2
 +              mask := v_3
 +              v.reset(OpAMD64VPERMI2QMasked256)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x4ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg4(x, y, z, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpPermute2MaskedInt64x8(v *Value) bool {
 +      v_3 := v.Args[3]
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (Permute2MaskedInt64x8 x y z mask)
 +      // result: (VPERMI2QMasked512 x y z (VPMOVVec64x8ToM <types.TypeMask> mask))
 +      for {
 +              x := v_0
 +              y := v_1
 +              z := v_2
 +              mask := v_3
 +              v.reset(OpAMD64VPERMI2QMasked512)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x8ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg4(x, y, z, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpPermute2MaskedInt8x16(v *Value) bool {
 +      v_3 := v.Args[3]
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (Permute2MaskedInt8x16 x y z mask)
 +      // result: (VPERMI2BMasked128 x y z (VPMOVVec8x16ToM <types.TypeMask> mask))
 +      for {
 +              x := v_0
 +              y := v_1
 +              z := v_2
 +              mask := v_3
 +              v.reset(OpAMD64VPERMI2BMasked128)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec8x16ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg4(x, y, z, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpPermute2MaskedInt8x32(v *Value) bool {
 +      v_3 := v.Args[3]
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (Permute2MaskedInt8x32 x y z mask)
 +      // result: (VPERMI2BMasked256 x y z (VPMOVVec8x32ToM <types.TypeMask> mask))
 +      for {
 +              x := v_0
 +              y := v_1
 +              z := v_2
 +              mask := v_3
 +              v.reset(OpAMD64VPERMI2BMasked256)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec8x32ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg4(x, y, z, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpPermute2MaskedInt8x64(v *Value) bool {
 +      v_3 := v.Args[3]
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (Permute2MaskedInt8x64 x y z mask)
 +      // result: (VPERMI2BMasked512 x y z (VPMOVVec8x64ToM <types.TypeMask> mask))
 +      for {
 +              x := v_0
 +              y := v_1
 +              z := v_2
 +              mask := v_3
 +              v.reset(OpAMD64VPERMI2BMasked512)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec8x64ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg4(x, y, z, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpPermute2MaskedUint16x16(v *Value) bool {
 +      v_3 := v.Args[3]
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (Permute2MaskedUint16x16 x y z mask)
 +      // result: (VPERMI2WMasked256 x y z (VPMOVVec16x16ToM <types.TypeMask> mask))
 +      for {
 +              x := v_0
 +              y := v_1
 +              z := v_2
 +              mask := v_3
 +              v.reset(OpAMD64VPERMI2WMasked256)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x16ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg4(x, y, z, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpPermute2MaskedUint16x32(v *Value) bool {
 +      v_3 := v.Args[3]
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (Permute2MaskedUint16x32 x y z mask)
 +      // result: (VPERMI2WMasked512 x y z (VPMOVVec16x32ToM <types.TypeMask> mask))
 +      for {
 +              x := v_0
 +              y := v_1
 +              z := v_2
 +              mask := v_3
 +              v.reset(OpAMD64VPERMI2WMasked512)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x32ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg4(x, y, z, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpPermute2MaskedUint16x8(v *Value) bool {
 +      v_3 := v.Args[3]
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (Permute2MaskedUint16x8 x y z mask)
 +      // result: (VPERMI2WMasked128 x y z (VPMOVVec16x8ToM <types.TypeMask> mask))
 +      for {
 +              x := v_0
 +              y := v_1
 +              z := v_2
 +              mask := v_3
 +              v.reset(OpAMD64VPERMI2WMasked128)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x8ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg4(x, y, z, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpPermute2MaskedUint32x16(v *Value) bool {
 +      v_3 := v.Args[3]
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (Permute2MaskedUint32x16 x y z mask)
 +      // result: (VPERMI2DMasked512 x y z (VPMOVVec32x16ToM <types.TypeMask> mask))
 +      for {
 +              x := v_0
 +              y := v_1
 +              z := v_2
 +              mask := v_3
 +              v.reset(OpAMD64VPERMI2DMasked512)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x16ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg4(x, y, z, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpPermute2MaskedUint32x4(v *Value) bool {
 +      v_3 := v.Args[3]
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (Permute2MaskedUint32x4 x y z mask)
 +      // result: (VPERMI2DMasked128 x y z (VPMOVVec32x4ToM <types.TypeMask> mask))
 +      for {
 +              x := v_0
 +              y := v_1
 +              z := v_2
 +              mask := v_3
 +              v.reset(OpAMD64VPERMI2DMasked128)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x4ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg4(x, y, z, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpPermute2MaskedUint32x8(v *Value) bool {
 +      v_3 := v.Args[3]
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (Permute2MaskedUint32x8 x y z mask)
 +      // result: (VPERMI2DMasked256 x y z (VPMOVVec32x8ToM <types.TypeMask> mask))
 +      for {
 +              x := v_0
 +              y := v_1
 +              z := v_2
 +              mask := v_3
 +              v.reset(OpAMD64VPERMI2DMasked256)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x8ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg4(x, y, z, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpPermute2MaskedUint64x2(v *Value) bool {
 +      v_3 := v.Args[3]
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (Permute2MaskedUint64x2 x y z mask)
 +      // result: (VPERMI2QMasked128 x y z (VPMOVVec64x2ToM <types.TypeMask> mask))
 +      for {
 +              x := v_0
 +              y := v_1
 +              z := v_2
 +              mask := v_3
 +              v.reset(OpAMD64VPERMI2QMasked128)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x2ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg4(x, y, z, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpPermute2MaskedUint64x4(v *Value) bool {
 +      v_3 := v.Args[3]
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (Permute2MaskedUint64x4 x y z mask)
 +      // result: (VPERMI2QMasked256 x y z (VPMOVVec64x4ToM <types.TypeMask> mask))
 +      for {
 +              x := v_0
 +              y := v_1
 +              z := v_2
 +              mask := v_3
 +              v.reset(OpAMD64VPERMI2QMasked256)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x4ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg4(x, y, z, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpPermute2MaskedUint64x8(v *Value) bool {
 +      v_3 := v.Args[3]
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (Permute2MaskedUint64x8 x y z mask)
 +      // result: (VPERMI2QMasked512 x y z (VPMOVVec64x8ToM <types.TypeMask> mask))
 +      for {
 +              x := v_0
 +              y := v_1
 +              z := v_2
 +              mask := v_3
 +              v.reset(OpAMD64VPERMI2QMasked512)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x8ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg4(x, y, z, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpPermute2MaskedUint8x16(v *Value) bool {
 +      v_3 := v.Args[3]
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (Permute2MaskedUint8x16 x y z mask)
 +      // result: (VPERMI2BMasked128 x y z (VPMOVVec8x16ToM <types.TypeMask> mask))
 +      for {
 +              x := v_0
 +              y := v_1
 +              z := v_2
 +              mask := v_3
 +              v.reset(OpAMD64VPERMI2BMasked128)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec8x16ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg4(x, y, z, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpPermute2MaskedUint8x32(v *Value) bool {
 +      v_3 := v.Args[3]
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (Permute2MaskedUint8x32 x y z mask)
 +      // result: (VPERMI2BMasked256 x y z (VPMOVVec8x32ToM <types.TypeMask> mask))
 +      for {
 +              x := v_0
 +              y := v_1
 +              z := v_2
 +              mask := v_3
 +              v.reset(OpAMD64VPERMI2BMasked256)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec8x32ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg4(x, y, z, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpPermute2MaskedUint8x64(v *Value) bool {
 +      v_3 := v.Args[3]
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (Permute2MaskedUint8x64 x y z mask)
 +      // result: (VPERMI2BMasked512 x y z (VPMOVVec8x64ToM <types.TypeMask> mask))
 +      for {
 +              x := v_0
 +              y := v_1
 +              z := v_2
 +              mask := v_3
 +              v.reset(OpAMD64VPERMI2BMasked512)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec8x64ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg4(x, y, z, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpPermuteMaskedFloat32x16(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (PermuteMaskedFloat32x16 x y mask)
 +      // result: (VPERMPSMasked512 x y (VPMOVVec32x16ToM <types.TypeMask> mask))
 +      for {
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VPERMPSMasked512)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x16ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg3(x, y, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpPermuteMaskedFloat32x8(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (PermuteMaskedFloat32x8 x y mask)
 +      // result: (VPERMPSMasked256 x y (VPMOVVec32x8ToM <types.TypeMask> mask))
 +      for {
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VPERMPSMasked256)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x8ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg3(x, y, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpPermuteMaskedFloat64x4(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (PermuteMaskedFloat64x4 x y mask)
 +      // result: (VPERMPDMasked256 x y (VPMOVVec64x4ToM <types.TypeMask> mask))
 +      for {
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VPERMPDMasked256)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x4ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg3(x, y, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpPermuteMaskedFloat64x8(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (PermuteMaskedFloat64x8 x y mask)
 +      // result: (VPERMPDMasked512 x y (VPMOVVec64x8ToM <types.TypeMask> mask))
 +      for {
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VPERMPDMasked512)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x8ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg3(x, y, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpPermuteMaskedInt16x16(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (PermuteMaskedInt16x16 x y mask)
 +      // result: (VPERMWMasked256 x y (VPMOVVec16x16ToM <types.TypeMask> mask))
 +      for {
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VPERMWMasked256)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x16ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg3(x, y, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpPermuteMaskedInt16x32(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (PermuteMaskedInt16x32 x y mask)
 +      // result: (VPERMWMasked512 x y (VPMOVVec16x32ToM <types.TypeMask> mask))
 +      for {
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VPERMWMasked512)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x32ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg3(x, y, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpPermuteMaskedInt16x8(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (PermuteMaskedInt16x8 x y mask)
 +      // result: (VPERMWMasked128 x y (VPMOVVec16x8ToM <types.TypeMask> mask))
 +      for {
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VPERMWMasked128)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x8ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg3(x, y, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpPermuteMaskedInt32x16(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (PermuteMaskedInt32x16 x y mask)
 +      // result: (VPERMDMasked512 x y (VPMOVVec32x16ToM <types.TypeMask> mask))
 +      for {
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VPERMDMasked512)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x16ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg3(x, y, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpPermuteMaskedInt32x8(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (PermuteMaskedInt32x8 x y mask)
 +      // result: (VPERMDMasked256 x y (VPMOVVec32x8ToM <types.TypeMask> mask))
 +      for {
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VPERMDMasked256)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x8ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg3(x, y, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpPermuteMaskedInt64x4(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (PermuteMaskedInt64x4 x y mask)
 +      // result: (VPERMQMasked256 x y (VPMOVVec64x4ToM <types.TypeMask> mask))
 +      for {
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VPERMQMasked256)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x4ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg3(x, y, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpPermuteMaskedInt64x8(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (PermuteMaskedInt64x8 x y mask)
 +      // result: (VPERMQMasked512 x y (VPMOVVec64x8ToM <types.TypeMask> mask))
 +      for {
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VPERMQMasked512)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x8ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg3(x, y, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpPermuteMaskedInt8x16(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (PermuteMaskedInt8x16 x y mask)
 +      // result: (VPERMBMasked128 x y (VPMOVVec8x16ToM <types.TypeMask> mask))
 +      for {
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VPERMBMasked128)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec8x16ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg3(x, y, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpPermuteMaskedInt8x32(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (PermuteMaskedInt8x32 x y mask)
 +      // result: (VPERMBMasked256 x y (VPMOVVec8x32ToM <types.TypeMask> mask))
 +      for {
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VPERMBMasked256)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec8x32ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg3(x, y, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpPermuteMaskedInt8x64(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (PermuteMaskedInt8x64 x y mask)
 +      // result: (VPERMBMasked512 x y (VPMOVVec8x64ToM <types.TypeMask> mask))
 +      for {
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VPERMBMasked512)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec8x64ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg3(x, y, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpPermuteMaskedUint16x16(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (PermuteMaskedUint16x16 x y mask)
 +      // result: (VPERMWMasked256 x y (VPMOVVec16x16ToM <types.TypeMask> mask))
 +      for {
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VPERMWMasked256)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x16ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg3(x, y, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpPermuteMaskedUint16x32(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (PermuteMaskedUint16x32 x y mask)
 +      // result: (VPERMWMasked512 x y (VPMOVVec16x32ToM <types.TypeMask> mask))
 +      for {
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VPERMWMasked512)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x32ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg3(x, y, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpPermuteMaskedUint16x8(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (PermuteMaskedUint16x8 x y mask)
 +      // result: (VPERMWMasked128 x y (VPMOVVec16x8ToM <types.TypeMask> mask))
 +      for {
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VPERMWMasked128)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x8ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg3(x, y, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpPermuteMaskedUint32x16(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (PermuteMaskedUint32x16 x y mask)
 +      // result: (VPERMDMasked512 x y (VPMOVVec32x16ToM <types.TypeMask> mask))
 +      for {
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VPERMDMasked512)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x16ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg3(x, y, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpPermuteMaskedUint32x8(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (PermuteMaskedUint32x8 x y mask)
 +      // result: (VPERMDMasked256 x y (VPMOVVec32x8ToM <types.TypeMask> mask))
 +      for {
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VPERMDMasked256)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x8ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg3(x, y, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpPermuteMaskedUint64x4(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (PermuteMaskedUint64x4 x y mask)
 +      // result: (VPERMQMasked256 x y (VPMOVVec64x4ToM <types.TypeMask> mask))
 +      for {
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VPERMQMasked256)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x4ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg3(x, y, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpPermuteMaskedUint64x8(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (PermuteMaskedUint64x8 x y mask)
 +      // result: (VPERMQMasked512 x y (VPMOVVec64x8ToM <types.TypeMask> mask))
 +      for {
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VPERMQMasked512)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x8ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg3(x, y, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpPermuteMaskedUint8x16(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (PermuteMaskedUint8x16 x y mask)
 +      // result: (VPERMBMasked128 x y (VPMOVVec8x16ToM <types.TypeMask> mask))
 +      for {
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VPERMBMasked128)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec8x16ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg3(x, y, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpPermuteMaskedUint8x32(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (PermuteMaskedUint8x32 x y mask)
 +      // result: (VPERMBMasked256 x y (VPMOVVec8x32ToM <types.TypeMask> mask))
 +      for {
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VPERMBMasked256)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec8x32ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg3(x, y, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpPermuteMaskedUint8x64(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (PermuteMaskedUint8x64 x y mask)
 +      // result: (VPERMBMasked512 x y (VPMOVVec8x64ToM <types.TypeMask> mask))
 +      for {
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VPERMBMasked512)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec8x64ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg3(x, y, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpPopCount16(v *Value) bool {
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      typ := &b.Func.Config.Types
 +      // match: (PopCount16 x)
 +      // result: (POPCNTL (MOVWQZX <typ.UInt32> x))
 +      for {
 +              x := v_0
 +              v.reset(OpAMD64POPCNTL)
 +              v0 := b.NewValue0(v.Pos, OpAMD64MOVWQZX, typ.UInt32)
 +              v0.AddArg(x)
 +              v.AddArg(v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpPopCount8(v *Value) bool {
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      typ := &b.Func.Config.Types
 +      // match: (PopCount8 x)
 +      // result: (POPCNTL (MOVBQZX <typ.UInt32> x))
 +      for {
 +              x := v_0
 +              v.reset(OpAMD64POPCNTL)
 +              v0 := b.NewValue0(v.Pos, OpAMD64MOVBQZX, typ.UInt32)
 +              v0.AddArg(x)
 +              v.AddArg(v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpReciprocalMaskedFloat32x16(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (ReciprocalMaskedFloat32x16 x mask)
 +      // result: (VRCP14PSMasked512 x (VPMOVVec32x16ToM <types.TypeMask> mask))
 +      for {
 +              x := v_0
 +              mask := v_1
 +              v.reset(OpAMD64VRCP14PSMasked512)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x16ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg2(x, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpReciprocalMaskedFloat32x4(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (ReciprocalMaskedFloat32x4 x mask)
 +      // result: (VRCP14PSMasked128 x (VPMOVVec32x4ToM <types.TypeMask> mask))
 +      for {
 +              x := v_0
 +              mask := v_1
 +              v.reset(OpAMD64VRCP14PSMasked128)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x4ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg2(x, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpReciprocalMaskedFloat32x8(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (ReciprocalMaskedFloat32x8 x mask)
 +      // result: (VRCP14PSMasked256 x (VPMOVVec32x8ToM <types.TypeMask> mask))
 +      for {
 +              x := v_0
 +              mask := v_1
 +              v.reset(OpAMD64VRCP14PSMasked256)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x8ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg2(x, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpReciprocalMaskedFloat64x2(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (ReciprocalMaskedFloat64x2 x mask)
 +      // result: (VRCP14PDMasked128 x (VPMOVVec64x2ToM <types.TypeMask> mask))
 +      for {
 +              x := v_0
 +              mask := v_1
 +              v.reset(OpAMD64VRCP14PDMasked128)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x2ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg2(x, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpReciprocalMaskedFloat64x4(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (ReciprocalMaskedFloat64x4 x mask)
 +      // result: (VRCP14PDMasked256 x (VPMOVVec64x4ToM <types.TypeMask> mask))
 +      for {
 +              x := v_0
 +              mask := v_1
 +              v.reset(OpAMD64VRCP14PDMasked256)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x4ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg2(x, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpReciprocalMaskedFloat64x8(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (ReciprocalMaskedFloat64x8 x mask)
 +      // result: (VRCP14PDMasked512 x (VPMOVVec64x8ToM <types.TypeMask> mask))
 +      for {
 +              x := v_0
 +              mask := v_1
 +              v.reset(OpAMD64VRCP14PDMasked512)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x8ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg2(x, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpReciprocalSqrtMaskedFloat32x16(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (ReciprocalSqrtMaskedFloat32x16 x mask)
 +      // result: (VRSQRT14PSMasked512 x (VPMOVVec32x16ToM <types.TypeMask> mask))
 +      for {
 +              x := v_0
 +              mask := v_1
 +              v.reset(OpAMD64VRSQRT14PSMasked512)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x16ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg2(x, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpReciprocalSqrtMaskedFloat32x4(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (ReciprocalSqrtMaskedFloat32x4 x mask)
 +      // result: (VRSQRT14PSMasked128 x (VPMOVVec32x4ToM <types.TypeMask> mask))
 +      for {
 +              x := v_0
 +              mask := v_1
 +              v.reset(OpAMD64VRSQRT14PSMasked128)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x4ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg2(x, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpReciprocalSqrtMaskedFloat32x8(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (ReciprocalSqrtMaskedFloat32x8 x mask)
 +      // result: (VRSQRT14PSMasked256 x (VPMOVVec32x8ToM <types.TypeMask> mask))
 +      for {
 +              x := v_0
 +              mask := v_1
 +              v.reset(OpAMD64VRSQRT14PSMasked256)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x8ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg2(x, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpReciprocalSqrtMaskedFloat64x2(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (ReciprocalSqrtMaskedFloat64x2 x mask)
 +      // result: (VRSQRT14PDMasked128 x (VPMOVVec64x2ToM <types.TypeMask> mask))
 +      for {
 +              x := v_0
 +              mask := v_1
 +              v.reset(OpAMD64VRSQRT14PDMasked128)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x2ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg2(x, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpReciprocalSqrtMaskedFloat64x4(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (ReciprocalSqrtMaskedFloat64x4 x mask)
 +      // result: (VRSQRT14PDMasked256 x (VPMOVVec64x4ToM <types.TypeMask> mask))
 +      for {
 +              x := v_0
 +              mask := v_1
 +              v.reset(OpAMD64VRSQRT14PDMasked256)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x4ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg2(x, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpReciprocalSqrtMaskedFloat64x8(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (ReciprocalSqrtMaskedFloat64x8 x mask)
 +      // result: (VRSQRT14PDMasked512 x (VPMOVVec64x8ToM <types.TypeMask> mask))
 +      for {
 +              x := v_0
 +              mask := v_1
 +              v.reset(OpAMD64VRSQRT14PDMasked512)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x8ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg2(x, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpRotateAllLeftMaskedInt32x16(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (RotateAllLeftMaskedInt32x16 [a] x mask)
 +      // result: (VPROLDMasked512 [a] x (VPMOVVec32x16ToM <types.TypeMask> mask))
 +      for {
 +              a := auxIntToUint8(v.AuxInt)
 +              x := v_0
 +              mask := v_1
 +              v.reset(OpAMD64VPROLDMasked512)
 +              v.AuxInt = uint8ToAuxInt(a)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x16ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg2(x, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpRotateAllLeftMaskedInt32x4(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (RotateAllLeftMaskedInt32x4 [a] x mask)
 +      // result: (VPROLDMasked128 [a] x (VPMOVVec32x4ToM <types.TypeMask> mask))
 +      for {
 +              a := auxIntToUint8(v.AuxInt)
 +              x := v_0
 +              mask := v_1
 +              v.reset(OpAMD64VPROLDMasked128)
 +              v.AuxInt = uint8ToAuxInt(a)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x4ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg2(x, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpRotateAllLeftMaskedInt32x8(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (RotateAllLeftMaskedInt32x8 [a] x mask)
 +      // result: (VPROLDMasked256 [a] x (VPMOVVec32x8ToM <types.TypeMask> mask))
 +      for {
 +              a := auxIntToUint8(v.AuxInt)
 +              x := v_0
 +              mask := v_1
 +              v.reset(OpAMD64VPROLDMasked256)
 +              v.AuxInt = uint8ToAuxInt(a)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x8ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg2(x, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpRotateAllLeftMaskedInt64x2(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (RotateAllLeftMaskedInt64x2 [a] x mask)
 +      // result: (VPROLQMasked128 [a] x (VPMOVVec64x2ToM <types.TypeMask> mask))
 +      for {
 +              a := auxIntToUint8(v.AuxInt)
 +              x := v_0
 +              mask := v_1
 +              v.reset(OpAMD64VPROLQMasked128)
 +              v.AuxInt = uint8ToAuxInt(a)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x2ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg2(x, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpRotateAllLeftMaskedInt64x4(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (RotateAllLeftMaskedInt64x4 [a] x mask)
 +      // result: (VPROLQMasked256 [a] x (VPMOVVec64x4ToM <types.TypeMask> mask))
 +      for {
 +              a := auxIntToUint8(v.AuxInt)
 +              x := v_0
 +              mask := v_1
 +              v.reset(OpAMD64VPROLQMasked256)
 +              v.AuxInt = uint8ToAuxInt(a)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x4ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg2(x, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpRotateAllLeftMaskedInt64x8(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (RotateAllLeftMaskedInt64x8 [a] x mask)
 +      // result: (VPROLQMasked512 [a] x (VPMOVVec64x8ToM <types.TypeMask> mask))
 +      for {
 +              a := auxIntToUint8(v.AuxInt)
 +              x := v_0
 +              mask := v_1
 +              v.reset(OpAMD64VPROLQMasked512)
 +              v.AuxInt = uint8ToAuxInt(a)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x8ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg2(x, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpRotateAllLeftMaskedUint32x16(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (RotateAllLeftMaskedUint32x16 [a] x mask)
 +      // result: (VPROLDMasked512 [a] x (VPMOVVec32x16ToM <types.TypeMask> mask))
 +      for {
 +              a := auxIntToUint8(v.AuxInt)
 +              x := v_0
 +              mask := v_1
 +              v.reset(OpAMD64VPROLDMasked512)
 +              v.AuxInt = uint8ToAuxInt(a)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x16ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg2(x, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpRotateAllLeftMaskedUint32x4(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (RotateAllLeftMaskedUint32x4 [a] x mask)
 +      // result: (VPROLDMasked128 [a] x (VPMOVVec32x4ToM <types.TypeMask> mask))
 +      for {
 +              a := auxIntToUint8(v.AuxInt)
 +              x := v_0
 +              mask := v_1
 +              v.reset(OpAMD64VPROLDMasked128)
 +              v.AuxInt = uint8ToAuxInt(a)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x4ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg2(x, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpRotateAllLeftMaskedUint32x8(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (RotateAllLeftMaskedUint32x8 [a] x mask)
 +      // result: (VPROLDMasked256 [a] x (VPMOVVec32x8ToM <types.TypeMask> mask))
 +      for {
 +              a := auxIntToUint8(v.AuxInt)
 +              x := v_0
 +              mask := v_1
 +              v.reset(OpAMD64VPROLDMasked256)
 +              v.AuxInt = uint8ToAuxInt(a)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x8ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg2(x, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpRotateAllLeftMaskedUint64x2(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (RotateAllLeftMaskedUint64x2 [a] x mask)
 +      // result: (VPROLQMasked128 [a] x (VPMOVVec64x2ToM <types.TypeMask> mask))
 +      for {
 +              a := auxIntToUint8(v.AuxInt)
 +              x := v_0
 +              mask := v_1
 +              v.reset(OpAMD64VPROLQMasked128)
 +              v.AuxInt = uint8ToAuxInt(a)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x2ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg2(x, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpRotateAllLeftMaskedUint64x4(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (RotateAllLeftMaskedUint64x4 [a] x mask)
 +      // result: (VPROLQMasked256 [a] x (VPMOVVec64x4ToM <types.TypeMask> mask))
 +      for {
 +              a := auxIntToUint8(v.AuxInt)
 +              x := v_0
 +              mask := v_1
 +              v.reset(OpAMD64VPROLQMasked256)
 +              v.AuxInt = uint8ToAuxInt(a)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x4ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg2(x, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpRotateAllLeftMaskedUint64x8(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (RotateAllLeftMaskedUint64x8 [a] x mask)
 +      // result: (VPROLQMasked512 [a] x (VPMOVVec64x8ToM <types.TypeMask> mask))
 +      for {
 +              a := auxIntToUint8(v.AuxInt)
 +              x := v_0
 +              mask := v_1
 +              v.reset(OpAMD64VPROLQMasked512)
 +              v.AuxInt = uint8ToAuxInt(a)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x8ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg2(x, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpRotateAllRightMaskedInt32x16(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (RotateAllRightMaskedInt32x16 [a] x mask)
 +      // result: (VPRORDMasked512 [a] x (VPMOVVec32x16ToM <types.TypeMask> mask))
 +      for {
 +              a := auxIntToUint8(v.AuxInt)
 +              x := v_0
 +              mask := v_1
 +              v.reset(OpAMD64VPRORDMasked512)
 +              v.AuxInt = uint8ToAuxInt(a)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x16ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg2(x, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpRotateAllRightMaskedInt32x4(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (RotateAllRightMaskedInt32x4 [a] x mask)
 +      // result: (VPRORDMasked128 [a] x (VPMOVVec32x4ToM <types.TypeMask> mask))
 +      for {
 +              a := auxIntToUint8(v.AuxInt)
 +              x := v_0
 +              mask := v_1
 +              v.reset(OpAMD64VPRORDMasked128)
 +              v.AuxInt = uint8ToAuxInt(a)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x4ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg2(x, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpRotateAllRightMaskedInt32x8(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (RotateAllRightMaskedInt32x8 [a] x mask)
 +      // result: (VPRORDMasked256 [a] x (VPMOVVec32x8ToM <types.TypeMask> mask))
 +      for {
 +              a := auxIntToUint8(v.AuxInt)
 +              x := v_0
 +              mask := v_1
 +              v.reset(OpAMD64VPRORDMasked256)
 +              v.AuxInt = uint8ToAuxInt(a)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x8ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg2(x, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpRotateAllRightMaskedInt64x2(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (RotateAllRightMaskedInt64x2 [a] x mask)
 +      // result: (VPRORQMasked128 [a] x (VPMOVVec64x2ToM <types.TypeMask> mask))
 +      for {
 +              a := auxIntToUint8(v.AuxInt)
 +              x := v_0
 +              mask := v_1
 +              v.reset(OpAMD64VPRORQMasked128)
 +              v.AuxInt = uint8ToAuxInt(a)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x2ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg2(x, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpRotateAllRightMaskedInt64x4(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (RotateAllRightMaskedInt64x4 [a] x mask)
 +      // result: (VPRORQMasked256 [a] x (VPMOVVec64x4ToM <types.TypeMask> mask))
 +      for {
 +              a := auxIntToUint8(v.AuxInt)
 +              x := v_0
 +              mask := v_1
 +              v.reset(OpAMD64VPRORQMasked256)
 +              v.AuxInt = uint8ToAuxInt(a)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x4ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg2(x, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpRotateAllRightMaskedInt64x8(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (RotateAllRightMaskedInt64x8 [a] x mask)
 +      // result: (VPRORQMasked512 [a] x (VPMOVVec64x8ToM <types.TypeMask> mask))
 +      for {
 +              a := auxIntToUint8(v.AuxInt)
 +              x := v_0
 +              mask := v_1
 +              v.reset(OpAMD64VPRORQMasked512)
 +              v.AuxInt = uint8ToAuxInt(a)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x8ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg2(x, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpRotateAllRightMaskedUint32x16(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (RotateAllRightMaskedUint32x16 [a] x mask)
 +      // result: (VPRORDMasked512 [a] x (VPMOVVec32x16ToM <types.TypeMask> mask))
 +      for {
 +              a := auxIntToUint8(v.AuxInt)
 +              x := v_0
 +              mask := v_1
 +              v.reset(OpAMD64VPRORDMasked512)
 +              v.AuxInt = uint8ToAuxInt(a)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x16ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg2(x, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpRotateAllRightMaskedUint32x4(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (RotateAllRightMaskedUint32x4 [a] x mask)
 +      // result: (VPRORDMasked128 [a] x (VPMOVVec32x4ToM <types.TypeMask> mask))
 +      for {
 +              a := auxIntToUint8(v.AuxInt)
 +              x := v_0
 +              mask := v_1
 +              v.reset(OpAMD64VPRORDMasked128)
 +              v.AuxInt = uint8ToAuxInt(a)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x4ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg2(x, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpRotateAllRightMaskedUint32x8(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (RotateAllRightMaskedUint32x8 [a] x mask)
 +      // result: (VPRORDMasked256 [a] x (VPMOVVec32x8ToM <types.TypeMask> mask))
 +      for {
 +              a := auxIntToUint8(v.AuxInt)
 +              x := v_0
 +              mask := v_1
 +              v.reset(OpAMD64VPRORDMasked256)
 +              v.AuxInt = uint8ToAuxInt(a)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x8ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg2(x, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpRotateAllRightMaskedUint64x2(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (RotateAllRightMaskedUint64x2 [a] x mask)
 +      // result: (VPRORQMasked128 [a] x (VPMOVVec64x2ToM <types.TypeMask> mask))
 +      for {
 +              a := auxIntToUint8(v.AuxInt)
 +              x := v_0
 +              mask := v_1
 +              v.reset(OpAMD64VPRORQMasked128)
 +              v.AuxInt = uint8ToAuxInt(a)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x2ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg2(x, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpRotateAllRightMaskedUint64x4(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (RotateAllRightMaskedUint64x4 [a] x mask)
 +      // result: (VPRORQMasked256 [a] x (VPMOVVec64x4ToM <types.TypeMask> mask))
 +      for {
 +              a := auxIntToUint8(v.AuxInt)
 +              x := v_0
 +              mask := v_1
 +              v.reset(OpAMD64VPRORQMasked256)
 +              v.AuxInt = uint8ToAuxInt(a)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x4ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg2(x, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpRotateAllRightMaskedUint64x8(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (RotateAllRightMaskedUint64x8 [a] x mask)
 +      // result: (VPRORQMasked512 [a] x (VPMOVVec64x8ToM <types.TypeMask> mask))
 +      for {
 +              a := auxIntToUint8(v.AuxInt)
 +              x := v_0
 +              mask := v_1
 +              v.reset(OpAMD64VPRORQMasked512)
 +              v.AuxInt = uint8ToAuxInt(a)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x8ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg2(x, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpRotateLeftMaskedInt32x16(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (RotateLeftMaskedInt32x16 x y mask)
 +      // result: (VPROLVDMasked512 x y (VPMOVVec32x16ToM <types.TypeMask> mask))
 +      for {
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VPROLVDMasked512)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x16ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg3(x, y, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpRotateLeftMaskedInt32x4(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (RotateLeftMaskedInt32x4 x y mask)
 +      // result: (VPROLVDMasked128 x y (VPMOVVec32x4ToM <types.TypeMask> mask))
 +      for {
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VPROLVDMasked128)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x4ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg3(x, y, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpRotateLeftMaskedInt32x8(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (RotateLeftMaskedInt32x8 x y mask)
 +      // result: (VPROLVDMasked256 x y (VPMOVVec32x8ToM <types.TypeMask> mask))
 +      for {
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VPROLVDMasked256)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x8ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg3(x, y, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpRotateLeftMaskedInt64x2(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (RotateLeftMaskedInt64x2 x y mask)
 +      // result: (VPROLVQMasked128 x y (VPMOVVec64x2ToM <types.TypeMask> mask))
 +      for {
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VPROLVQMasked128)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x2ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg3(x, y, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpRotateLeftMaskedInt64x4(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (RotateLeftMaskedInt64x4 x y mask)
 +      // result: (VPROLVQMasked256 x y (VPMOVVec64x4ToM <types.TypeMask> mask))
 +      for {
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VPROLVQMasked256)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x4ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg3(x, y, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpRotateLeftMaskedInt64x8(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (RotateLeftMaskedInt64x8 x y mask)
 +      // result: (VPROLVQMasked512 x y (VPMOVVec64x8ToM <types.TypeMask> mask))
 +      for {
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VPROLVQMasked512)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x8ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg3(x, y, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpRotateLeftMaskedUint32x16(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (RotateLeftMaskedUint32x16 x y mask)
 +      // result: (VPROLVDMasked512 x y (VPMOVVec32x16ToM <types.TypeMask> mask))
 +      for {
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VPROLVDMasked512)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x16ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg3(x, y, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpRotateLeftMaskedUint32x4(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (RotateLeftMaskedUint32x4 x y mask)
 +      // result: (VPROLVDMasked128 x y (VPMOVVec32x4ToM <types.TypeMask> mask))
 +      for {
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VPROLVDMasked128)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x4ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg3(x, y, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpRotateLeftMaskedUint32x8(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (RotateLeftMaskedUint32x8 x y mask)
 +      // result: (VPROLVDMasked256 x y (VPMOVVec32x8ToM <types.TypeMask> mask))
 +      for {
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VPROLVDMasked256)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x8ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg3(x, y, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpRotateLeftMaskedUint64x2(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (RotateLeftMaskedUint64x2 x y mask)
 +      // result: (VPROLVQMasked128 x y (VPMOVVec64x2ToM <types.TypeMask> mask))
 +      for {
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VPROLVQMasked128)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x2ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg3(x, y, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpRotateLeftMaskedUint64x4(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (RotateLeftMaskedUint64x4 x y mask)
 +      // result: (VPROLVQMasked256 x y (VPMOVVec64x4ToM <types.TypeMask> mask))
 +      for {
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VPROLVQMasked256)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x4ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg3(x, y, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpRotateLeftMaskedUint64x8(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (RotateLeftMaskedUint64x8 x y mask)
 +      // result: (VPROLVQMasked512 x y (VPMOVVec64x8ToM <types.TypeMask> mask))
 +      for {
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VPROLVQMasked512)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x8ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg3(x, y, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpRotateRightMaskedInt32x16(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (RotateRightMaskedInt32x16 x y mask)
 +      // result: (VPRORVDMasked512 x y (VPMOVVec32x16ToM <types.TypeMask> mask))
 +      for {
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VPRORVDMasked512)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x16ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg3(x, y, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpRotateRightMaskedInt32x4(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (RotateRightMaskedInt32x4 x y mask)
 +      // result: (VPRORVDMasked128 x y (VPMOVVec32x4ToM <types.TypeMask> mask))
 +      for {
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VPRORVDMasked128)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x4ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg3(x, y, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpRotateRightMaskedInt32x8(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (RotateRightMaskedInt32x8 x y mask)
 +      // result: (VPRORVDMasked256 x y (VPMOVVec32x8ToM <types.TypeMask> mask))
 +      for {
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VPRORVDMasked256)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x8ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg3(x, y, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpRotateRightMaskedInt64x2(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (RotateRightMaskedInt64x2 x y mask)
 +      // result: (VPRORVQMasked128 x y (VPMOVVec64x2ToM <types.TypeMask> mask))
 +      for {
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VPRORVQMasked128)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x2ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg3(x, y, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpRotateRightMaskedInt64x4(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (RotateRightMaskedInt64x4 x y mask)
 +      // result: (VPRORVQMasked256 x y (VPMOVVec64x4ToM <types.TypeMask> mask))
 +      for {
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VPRORVQMasked256)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x4ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg3(x, y, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpRotateRightMaskedInt64x8(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (RotateRightMaskedInt64x8 x y mask)
 +      // result: (VPRORVQMasked512 x y (VPMOVVec64x8ToM <types.TypeMask> mask))
 +      for {
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VPRORVQMasked512)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x8ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg3(x, y, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpRotateRightMaskedUint32x16(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (RotateRightMaskedUint32x16 x y mask)
 +      // result: (VPRORVDMasked512 x y (VPMOVVec32x16ToM <types.TypeMask> mask))
 +      for {
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VPRORVDMasked512)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x16ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg3(x, y, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpRotateRightMaskedUint32x4(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (RotateRightMaskedUint32x4 x y mask)
 +      // result: (VPRORVDMasked128 x y (VPMOVVec32x4ToM <types.TypeMask> mask))
 +      for {
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VPRORVDMasked128)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x4ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg3(x, y, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpRotateRightMaskedUint32x8(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (RotateRightMaskedUint32x8 x y mask)
 +      // result: (VPRORVDMasked256 x y (VPMOVVec32x8ToM <types.TypeMask> mask))
 +      for {
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VPRORVDMasked256)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x8ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg3(x, y, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpRotateRightMaskedUint64x2(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (RotateRightMaskedUint64x2 x y mask)
 +      // result: (VPRORVQMasked128 x y (VPMOVVec64x2ToM <types.TypeMask> mask))
 +      for {
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VPRORVQMasked128)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x2ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg3(x, y, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpRotateRightMaskedUint64x4(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (RotateRightMaskedUint64x4 x y mask)
 +      // result: (VPRORVQMasked256 x y (VPMOVVec64x4ToM <types.TypeMask> mask))
 +      for {
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VPRORVQMasked256)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x4ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg3(x, y, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpRotateRightMaskedUint64x8(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (RotateRightMaskedUint64x8 x y mask)
 +      // result: (VPRORVQMasked512 x y (VPMOVVec64x8ToM <types.TypeMask> mask))
 +      for {
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VPRORVQMasked512)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x8ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg3(x, y, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpRoundToEven(v *Value) bool {
 +      v_0 := v.Args[0]
 +      // match: (RoundToEven x)
 +      // result: (ROUNDSD [0] x)
 +      for {
 +              x := v_0
 +              v.reset(OpAMD64ROUNDSD)
 +              v.AuxInt = int8ToAuxInt(0)
 +              v.AddArg(x)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpRoundToEvenFloat32x4(v *Value) bool {
 +      v_0 := v.Args[0]
 +      // match: (RoundToEvenFloat32x4 x)
 +      // result: (VROUNDPS128 [0] x)
 +      for {
 +              x := v_0
 +              v.reset(OpAMD64VROUNDPS128)
 +              v.AuxInt = uint8ToAuxInt(0)
 +              v.AddArg(x)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpRoundToEvenFloat32x8(v *Value) bool {
 +      v_0 := v.Args[0]
 +      // match: (RoundToEvenFloat32x8 x)
 +      // result: (VROUNDPS256 [0] x)
 +      for {
 +              x := v_0
 +              v.reset(OpAMD64VROUNDPS256)
 +              v.AuxInt = uint8ToAuxInt(0)
 +              v.AddArg(x)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpRoundToEvenFloat64x2(v *Value) bool {
 +      v_0 := v.Args[0]
 +      // match: (RoundToEvenFloat64x2 x)
 +      // result: (VROUNDPD128 [0] x)
 +      for {
 +              x := v_0
 +              v.reset(OpAMD64VROUNDPD128)
 +              v.AuxInt = uint8ToAuxInt(0)
 +              v.AddArg(x)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpRoundToEvenFloat64x4(v *Value) bool {
 +      v_0 := v.Args[0]
 +      // match: (RoundToEvenFloat64x4 x)
 +      // result: (VROUNDPD256 [0] x)
 +      for {
 +              x := v_0
 +              v.reset(OpAMD64VROUNDPD256)
 +              v.AuxInt = uint8ToAuxInt(0)
 +              v.AddArg(x)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpRoundToEvenScaledFloat32x16(v *Value) bool {
 +      v_0 := v.Args[0]
 +      // match: (RoundToEvenScaledFloat32x16 [a] x)
 +      // result: (VRNDSCALEPS512 [a+0] x)
 +      for {
 +              a := auxIntToUint8(v.AuxInt)
 +              x := v_0
 +              v.reset(OpAMD64VRNDSCALEPS512)
 +              v.AuxInt = uint8ToAuxInt(a + 0)
 +              v.AddArg(x)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpRoundToEvenScaledFloat32x4(v *Value) bool {
 +      v_0 := v.Args[0]
 +      // match: (RoundToEvenScaledFloat32x4 [a] x)
 +      // result: (VRNDSCALEPS128 [a+0] x)
 +      for {
 +              a := auxIntToUint8(v.AuxInt)
 +              x := v_0
 +              v.reset(OpAMD64VRNDSCALEPS128)
 +              v.AuxInt = uint8ToAuxInt(a + 0)
 +              v.AddArg(x)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpRoundToEvenScaledFloat32x8(v *Value) bool {
 +      v_0 := v.Args[0]
 +      // match: (RoundToEvenScaledFloat32x8 [a] x)
 +      // result: (VRNDSCALEPS256 [a+0] x)
 +      for {
 +              a := auxIntToUint8(v.AuxInt)
 +              x := v_0
 +              v.reset(OpAMD64VRNDSCALEPS256)
 +              v.AuxInt = uint8ToAuxInt(a + 0)
 +              v.AddArg(x)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpRoundToEvenScaledFloat64x2(v *Value) bool {
 +      v_0 := v.Args[0]
 +      // match: (RoundToEvenScaledFloat64x2 [a] x)
 +      // result: (VRNDSCALEPD128 [a+0] x)
 +      for {
 +              a := auxIntToUint8(v.AuxInt)
 +              x := v_0
 +              v.reset(OpAMD64VRNDSCALEPD128)
 +              v.AuxInt = uint8ToAuxInt(a + 0)
 +              v.AddArg(x)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpRoundToEvenScaledFloat64x4(v *Value) bool {
 +      v_0 := v.Args[0]
 +      // match: (RoundToEvenScaledFloat64x4 [a] x)
 +      // result: (VRNDSCALEPD256 [a+0] x)
 +      for {
 +              a := auxIntToUint8(v.AuxInt)
 +              x := v_0
 +              v.reset(OpAMD64VRNDSCALEPD256)
 +              v.AuxInt = uint8ToAuxInt(a + 0)
 +              v.AddArg(x)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpRoundToEvenScaledFloat64x8(v *Value) bool {
 +      v_0 := v.Args[0]
 +      // match: (RoundToEvenScaledFloat64x8 [a] x)
 +      // result: (VRNDSCALEPD512 [a+0] x)
 +      for {
 +              a := auxIntToUint8(v.AuxInt)
 +              x := v_0
 +              v.reset(OpAMD64VRNDSCALEPD512)
 +              v.AuxInt = uint8ToAuxInt(a + 0)
 +              v.AddArg(x)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpRoundToEvenScaledMaskedFloat32x16(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (RoundToEvenScaledMaskedFloat32x16 [a] x mask)
 +      // result: (VRNDSCALEPSMasked512 [a+0] x (VPMOVVec32x16ToM <types.TypeMask> mask))
 +      for {
 +              a := auxIntToUint8(v.AuxInt)
 +              x := v_0
 +              mask := v_1
 +              v.reset(OpAMD64VRNDSCALEPSMasked512)
 +              v.AuxInt = uint8ToAuxInt(a + 0)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x16ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg2(x, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpRoundToEvenScaledMaskedFloat32x4(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (RoundToEvenScaledMaskedFloat32x4 [a] x mask)
 +      // result: (VRNDSCALEPSMasked128 [a+0] x (VPMOVVec32x4ToM <types.TypeMask> mask))
 +      for {
 +              a := auxIntToUint8(v.AuxInt)
 +              x := v_0
 +              mask := v_1
 +              v.reset(OpAMD64VRNDSCALEPSMasked128)
 +              v.AuxInt = uint8ToAuxInt(a + 0)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x4ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg2(x, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpRoundToEvenScaledMaskedFloat32x8(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (RoundToEvenScaledMaskedFloat32x8 [a] x mask)
 +      // result: (VRNDSCALEPSMasked256 [a+0] x (VPMOVVec32x8ToM <types.TypeMask> mask))
 +      for {
 +              a := auxIntToUint8(v.AuxInt)
 +              x := v_0
 +              mask := v_1
 +              v.reset(OpAMD64VRNDSCALEPSMasked256)
 +              v.AuxInt = uint8ToAuxInt(a + 0)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x8ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg2(x, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpRoundToEvenScaledMaskedFloat64x2(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (RoundToEvenScaledMaskedFloat64x2 [a] x mask)
 +      // result: (VRNDSCALEPDMasked128 [a+0] x (VPMOVVec64x2ToM <types.TypeMask> mask))
 +      for {
 +              a := auxIntToUint8(v.AuxInt)
 +              x := v_0
 +              mask := v_1
 +              v.reset(OpAMD64VRNDSCALEPDMasked128)
 +              v.AuxInt = uint8ToAuxInt(a + 0)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x2ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg2(x, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpRoundToEvenScaledMaskedFloat64x4(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (RoundToEvenScaledMaskedFloat64x4 [a] x mask)
 +      // result: (VRNDSCALEPDMasked256 [a+0] x (VPMOVVec64x4ToM <types.TypeMask> mask))
 +      for {
 +              a := auxIntToUint8(v.AuxInt)
 +              x := v_0
 +              mask := v_1
 +              v.reset(OpAMD64VRNDSCALEPDMasked256)
 +              v.AuxInt = uint8ToAuxInt(a + 0)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x4ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg2(x, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpRoundToEvenScaledMaskedFloat64x8(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (RoundToEvenScaledMaskedFloat64x8 [a] x mask)
 +      // result: (VRNDSCALEPDMasked512 [a+0] x (VPMOVVec64x8ToM <types.TypeMask> mask))
 +      for {
 +              a := auxIntToUint8(v.AuxInt)
 +              x := v_0
 +              mask := v_1
 +              v.reset(OpAMD64VRNDSCALEPDMasked512)
 +              v.AuxInt = uint8ToAuxInt(a + 0)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x8ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg2(x, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpRoundToEvenScaledResidueFloat32x16(v *Value) bool {
 +      v_0 := v.Args[0]
 +      // match: (RoundToEvenScaledResidueFloat32x16 [a] x)
 +      // result: (VREDUCEPS512 [a+0] x)
 +      for {
 +              a := auxIntToUint8(v.AuxInt)
 +              x := v_0
 +              v.reset(OpAMD64VREDUCEPS512)
 +              v.AuxInt = uint8ToAuxInt(a + 0)
 +              v.AddArg(x)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpRoundToEvenScaledResidueFloat32x4(v *Value) bool {
 +      v_0 := v.Args[0]
 +      // match: (RoundToEvenScaledResidueFloat32x4 [a] x)
 +      // result: (VREDUCEPS128 [a+0] x)
 +      for {
 +              a := auxIntToUint8(v.AuxInt)
 +              x := v_0
 +              v.reset(OpAMD64VREDUCEPS128)
 +              v.AuxInt = uint8ToAuxInt(a + 0)
 +              v.AddArg(x)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpRoundToEvenScaledResidueFloat32x8(v *Value) bool {
 +      v_0 := v.Args[0]
 +      // match: (RoundToEvenScaledResidueFloat32x8 [a] x)
 +      // result: (VREDUCEPS256 [a+0] x)
 +      for {
 +              a := auxIntToUint8(v.AuxInt)
 +              x := v_0
 +              v.reset(OpAMD64VREDUCEPS256)
 +              v.AuxInt = uint8ToAuxInt(a + 0)
 +              v.AddArg(x)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpRoundToEvenScaledResidueFloat64x2(v *Value) bool {
 +      v_0 := v.Args[0]
 +      // match: (RoundToEvenScaledResidueFloat64x2 [a] x)
 +      // result: (VREDUCEPD128 [a+0] x)
 +      for {
 +              a := auxIntToUint8(v.AuxInt)
 +              x := v_0
 +              v.reset(OpAMD64VREDUCEPD128)
 +              v.AuxInt = uint8ToAuxInt(a + 0)
 +              v.AddArg(x)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpRoundToEvenScaledResidueFloat64x4(v *Value) bool {
 +      v_0 := v.Args[0]
 +      // match: (RoundToEvenScaledResidueFloat64x4 [a] x)
 +      // result: (VREDUCEPD256 [a+0] x)
 +      for {
 +              a := auxIntToUint8(v.AuxInt)
 +              x := v_0
 +              v.reset(OpAMD64VREDUCEPD256)
 +              v.AuxInt = uint8ToAuxInt(a + 0)
 +              v.AddArg(x)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpRoundToEvenScaledResidueFloat64x8(v *Value) bool {
 +      v_0 := v.Args[0]
 +      // match: (RoundToEvenScaledResidueFloat64x8 [a] x)
 +      // result: (VREDUCEPD512 [a+0] x)
 +      for {
 +              a := auxIntToUint8(v.AuxInt)
 +              x := v_0
 +              v.reset(OpAMD64VREDUCEPD512)
 +              v.AuxInt = uint8ToAuxInt(a + 0)
 +              v.AddArg(x)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpRoundToEvenScaledResidueMaskedFloat32x16(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (RoundToEvenScaledResidueMaskedFloat32x16 [a] x mask)
 +      // result: (VREDUCEPSMasked512 [a+0] x (VPMOVVec32x16ToM <types.TypeMask> mask))
 +      for {
 +              a := auxIntToUint8(v.AuxInt)
 +              x := v_0
 +              mask := v_1
 +              v.reset(OpAMD64VREDUCEPSMasked512)
 +              v.AuxInt = uint8ToAuxInt(a + 0)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x16ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg2(x, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpRoundToEvenScaledResidueMaskedFloat32x4(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (RoundToEvenScaledResidueMaskedFloat32x4 [a] x mask)
 +      // result: (VREDUCEPSMasked128 [a+0] x (VPMOVVec32x4ToM <types.TypeMask> mask))
 +      for {
 +              a := auxIntToUint8(v.AuxInt)
 +              x := v_0
 +              mask := v_1
 +              v.reset(OpAMD64VREDUCEPSMasked128)
 +              v.AuxInt = uint8ToAuxInt(a + 0)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x4ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg2(x, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpRoundToEvenScaledResidueMaskedFloat32x8(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (RoundToEvenScaledResidueMaskedFloat32x8 [a] x mask)
 +      // result: (VREDUCEPSMasked256 [a+0] x (VPMOVVec32x8ToM <types.TypeMask> mask))
 +      for {
 +              a := auxIntToUint8(v.AuxInt)
 +              x := v_0
 +              mask := v_1
 +              v.reset(OpAMD64VREDUCEPSMasked256)
 +              v.AuxInt = uint8ToAuxInt(a + 0)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x8ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg2(x, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpRoundToEvenScaledResidueMaskedFloat64x2(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (RoundToEvenScaledResidueMaskedFloat64x2 [a] x mask)
 +      // result: (VREDUCEPDMasked128 [a+0] x (VPMOVVec64x2ToM <types.TypeMask> mask))
 +      for {
 +              a := auxIntToUint8(v.AuxInt)
 +              x := v_0
 +              mask := v_1
 +              v.reset(OpAMD64VREDUCEPDMasked128)
 +              v.AuxInt = uint8ToAuxInt(a + 0)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x2ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg2(x, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpRoundToEvenScaledResidueMaskedFloat64x4(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (RoundToEvenScaledResidueMaskedFloat64x4 [a] x mask)
 +      // result: (VREDUCEPDMasked256 [a+0] x (VPMOVVec64x4ToM <types.TypeMask> mask))
 +      for {
 +              a := auxIntToUint8(v.AuxInt)
 +              x := v_0
 +              mask := v_1
 +              v.reset(OpAMD64VREDUCEPDMasked256)
 +              v.AuxInt = uint8ToAuxInt(a + 0)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x4ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg2(x, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpRoundToEvenScaledResidueMaskedFloat64x8(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (RoundToEvenScaledResidueMaskedFloat64x8 [a] x mask)
 +      // result: (VREDUCEPDMasked512 [a+0] x (VPMOVVec64x8ToM <types.TypeMask> mask))
 +      for {
 +              a := auxIntToUint8(v.AuxInt)
 +              x := v_0
 +              mask := v_1
 +              v.reset(OpAMD64VREDUCEPDMasked512)
 +              v.AuxInt = uint8ToAuxInt(a + 0)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x8ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg2(x, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpRsh16Ux16(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (Rsh16Ux16 <t> x y)
 +      // cond: !shiftIsBounded(v)
 +      // result: (ANDL (SHRW <t> x y) (SBBLcarrymask <t> (CMPWconst y [16])))
 +      for {
 +              t := v.Type
 +              x := v_0
 +              y := v_1
 +              if !(!shiftIsBounded(v)) {
 +                      break
 +              }
 +              v.reset(OpAMD64ANDL)
 +              v0 := b.NewValue0(v.Pos, OpAMD64SHRW, t)
 +              v0.AddArg2(x, y)
 +              v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t)
 +              v2 := b.NewValue0(v.Pos, OpAMD64CMPWconst, types.TypeFlags)
 +              v2.AuxInt = int16ToAuxInt(16)
 +              v2.AddArg(y)
 +              v1.AddArg(v2)
 +              v.AddArg2(v0, v1)
 +              return true
 +      }
 +      // match: (Rsh16Ux16 x y)
 +      // cond: shiftIsBounded(v)
 +      // result: (SHRW x y)
 +      for {
 +              x := v_0
 +              y := v_1
 +              if !(shiftIsBounded(v)) {
 +                      break
 +              }
 +              v.reset(OpAMD64SHRW)
 +              v.AddArg2(x, y)
 +              return true
 +      }
 +      return false
 +}
 +func rewriteValueAMD64_OpRsh16Ux32(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (Rsh16Ux32 <t> x y)
 +      // cond: !shiftIsBounded(v)
 +      // result: (ANDL (SHRW <t> x y) (SBBLcarrymask <t> (CMPLconst y [16])))
 +      for {
 +              t := v.Type
 +              x := v_0
 +              y := v_1
 +              if !(!shiftIsBounded(v)) {
 +                      break
 +              }
 +              v.reset(OpAMD64ANDL)
 +              v0 := b.NewValue0(v.Pos, OpAMD64SHRW, t)
 +              v0.AddArg2(x, y)
 +              v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t)
 +              v2 := b.NewValue0(v.Pos, OpAMD64CMPLconst, types.TypeFlags)
 +              v2.AuxInt = int32ToAuxInt(16)
 +              v2.AddArg(y)
 +              v1.AddArg(v2)
 +              v.AddArg2(v0, v1)
 +              return true
 +      }
 +      // match: (Rsh16Ux32 x y)
 +      // cond: shiftIsBounded(v)
 +      // result: (SHRW x y)
 +      for {
 +              x := v_0
 +              y := v_1
 +              if !(shiftIsBounded(v)) {
 +                      break
 +              }
 +              v.reset(OpAMD64SHRW)
 +              v.AddArg2(x, y)
 +              return true
 +      }
 +      return false
 +}
 +func rewriteValueAMD64_OpRsh16Ux64(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (Rsh16Ux64 <t> x y)
 +      // cond: !shiftIsBounded(v)
 +      // result: (ANDL (SHRW <t> x y) (SBBLcarrymask <t> (CMPQconst y [16])))
 +      for {
 +              t := v.Type
 +              x := v_0
 +              y := v_1
 +              if !(!shiftIsBounded(v)) {
 +                      break
 +              }
 +              v.reset(OpAMD64ANDL)
 +              v0 := b.NewValue0(v.Pos, OpAMD64SHRW, t)
 +              v0.AddArg2(x, y)
 +              v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t)
 +              v2 := b.NewValue0(v.Pos, OpAMD64CMPQconst, types.TypeFlags)
 +              v2.AuxInt = int32ToAuxInt(16)
 +              v2.AddArg(y)
 +              v1.AddArg(v2)
 +              v.AddArg2(v0, v1)
 +              return true
 +      }
 +      // match: (Rsh16Ux64 x y)
 +      // cond: shiftIsBounded(v)
 +      // result: (SHRW x y)
 +      for {
 +              x := v_0
 +              y := v_1
 +              if !(shiftIsBounded(v)) {
 +                      break
 +              }
 +              v.reset(OpAMD64SHRW)
 +              v.AddArg2(x, y)
 +              return true
 +      }
 +      return false
 +}
 +func rewriteValueAMD64_OpRsh16Ux8(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (Rsh16Ux8 <t> x y)
 +      // cond: !shiftIsBounded(v)
 +      // result: (ANDL (SHRW <t> x y) (SBBLcarrymask <t> (CMPBconst y [16])))
 +      for {
 +              t := v.Type
 +              x := v_0
 +              y := v_1
 +              if !(!shiftIsBounded(v)) {
 +                      break
 +              }
 +              v.reset(OpAMD64ANDL)
 +              v0 := b.NewValue0(v.Pos, OpAMD64SHRW, t)
 +              v0.AddArg2(x, y)
 +              v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t)
 +              v2 := b.NewValue0(v.Pos, OpAMD64CMPBconst, types.TypeFlags)
 +              v2.AuxInt = int8ToAuxInt(16)
 +              v2.AddArg(y)
 +              v1.AddArg(v2)
 +              v.AddArg2(v0, v1)
 +              return true
 +      }
 +      // match: (Rsh16Ux8 x y)
 +      // cond: shiftIsBounded(v)
 +      // result: (SHRW x y)
 +      for {
 +              x := v_0
 +              y := v_1
 +              if !(shiftIsBounded(v)) {
 +                      break
 +              }
 +              v.reset(OpAMD64SHRW)
 +              v.AddArg2(x, y)
 +              return true
 +      }
 +      return false
 +}
 +func rewriteValueAMD64_OpRsh16x16(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (Rsh16x16 <t> x y)
 +      // cond: !shiftIsBounded(v)
 +      // result: (SARW <t> x (ORL <y.Type> y (NOTL <y.Type> (SBBLcarrymask <y.Type> (CMPWconst y [16])))))
 +      for {
 +              t := v.Type
 +              x := v_0
 +              y := v_1
 +              if !(!shiftIsBounded(v)) {
 +                      break
 +              }
 +              v.reset(OpAMD64SARW)
 +              v.Type = t
 +              v0 := b.NewValue0(v.Pos, OpAMD64ORL, y.Type)
 +              v1 := b.NewValue0(v.Pos, OpAMD64NOTL, y.Type)
 +              v2 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, y.Type)
 +              v3 := b.NewValue0(v.Pos, OpAMD64CMPWconst, types.TypeFlags)
 +              v3.AuxInt = int16ToAuxInt(16)
 +              v3.AddArg(y)
 +              v2.AddArg(v3)
 +              v1.AddArg(v2)
 +              v0.AddArg2(y, v1)
 +              v.AddArg2(x, v0)
 +              return true
 +      }
 +      // match: (Rsh16x16 x y)
 +      // cond: shiftIsBounded(v)
 +      // result: (SARW x y)
 +      for {
 +              x := v_0
 +              y := v_1
 +              if !(shiftIsBounded(v)) {
 +                      break
 +              }
 +              v.reset(OpAMD64SARW)
 +              v.AddArg2(x, y)
 +              return true
 +      }
 +      return false
 +}
 +func rewriteValueAMD64_OpRsh16x32(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (Rsh16x32 <t> x y)
 +      // cond: !shiftIsBounded(v)
 +      // result: (SARW <t> x (ORL <y.Type> y (NOTL <y.Type> (SBBLcarrymask <y.Type> (CMPLconst y [16])))))
 +      for {
 +              t := v.Type
 +              x := v_0
 +              y := v_1
 +              if !(!shiftIsBounded(v)) {
 +                      break
 +              }
 +              v.reset(OpAMD64SARW)
 +              v.Type = t
 +              v0 := b.NewValue0(v.Pos, OpAMD64ORL, y.Type)
 +              v1 := b.NewValue0(v.Pos, OpAMD64NOTL, y.Type)
 +              v2 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, y.Type)
 +              v3 := b.NewValue0(v.Pos, OpAMD64CMPLconst, types.TypeFlags)
 +              v3.AuxInt = int32ToAuxInt(16)
 +              v3.AddArg(y)
 +              v2.AddArg(v3)
 +              v1.AddArg(v2)
 +              v0.AddArg2(y, v1)
 +              v.AddArg2(x, v0)
 +              return true
 +      }
 +      // match: (Rsh16x32 x y)
 +      // cond: shiftIsBounded(v)
 +      // result: (SARW x y)
 +      for {
 +              x := v_0
 +              y := v_1
 +              if !(shiftIsBounded(v)) {
 +                      break
 +              }
 +              v.reset(OpAMD64SARW)
 +              v.AddArg2(x, y)
 +              return true
 +      }
 +      return false
 +}
 +func rewriteValueAMD64_OpRsh16x64(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (Rsh16x64 <t> x y)
 +      // cond: !shiftIsBounded(v)
 +      // result: (SARW <t> x (ORQ <y.Type> y (NOTQ <y.Type> (SBBQcarrymask <y.Type> (CMPQconst y [16])))))
 +      for {
 +              t := v.Type
 +              x := v_0
 +              y := v_1
 +              if !(!shiftIsBounded(v)) {
 +                      break
 +              }
 +              v.reset(OpAMD64SARW)
 +              v.Type = t
 +              v0 := b.NewValue0(v.Pos, OpAMD64ORQ, y.Type)
 +              v1 := b.NewValue0(v.Pos, OpAMD64NOTQ, y.Type)
 +              v2 := b.NewValue0(v.Pos, OpAMD64SBBQcarrymask, y.Type)
 +              v3 := b.NewValue0(v.Pos, OpAMD64CMPQconst, types.TypeFlags)
 +              v3.AuxInt = int32ToAuxInt(16)
 +              v3.AddArg(y)
 +              v2.AddArg(v3)
 +              v1.AddArg(v2)
 +              v0.AddArg2(y, v1)
 +              v.AddArg2(x, v0)
 +              return true
 +      }
 +      // match: (Rsh16x64 x y)
 +      // cond: shiftIsBounded(v)
 +      // result: (SARW x y)
 +      for {
 +              x := v_0
 +              y := v_1
 +              if !(shiftIsBounded(v)) {
 +                      break
 +              }
 +              v.reset(OpAMD64SARW)
 +              v.AddArg2(x, y)
 +              return true
 +      }
 +      return false
 +}
 +func rewriteValueAMD64_OpRsh16x8(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (Rsh16x8 <t> x y)
 +      // cond: !shiftIsBounded(v)
 +      // result: (SARW <t> x (ORL <y.Type> y (NOTL <y.Type> (SBBLcarrymask <y.Type> (CMPBconst y [16])))))
 +      for {
 +              t := v.Type
 +              x := v_0
 +              y := v_1
 +              if !(!shiftIsBounded(v)) {
 +                      break
 +              }
 +              v.reset(OpAMD64SARW)
 +              v.Type = t
 +              v0 := b.NewValue0(v.Pos, OpAMD64ORL, y.Type)
 +              v1 := b.NewValue0(v.Pos, OpAMD64NOTL, y.Type)
 +              v2 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, y.Type)
 +              v3 := b.NewValue0(v.Pos, OpAMD64CMPBconst, types.TypeFlags)
 +              v3.AuxInt = int8ToAuxInt(16)
 +              v3.AddArg(y)
 +              v2.AddArg(v3)
 +              v1.AddArg(v2)
 +              v0.AddArg2(y, v1)
 +              v.AddArg2(x, v0)
 +              return true
 +      }
 +      // match: (Rsh16x8 x y)
 +      // cond: shiftIsBounded(v)
 +      // result: (SARW x y)
 +      for {
 +              x := v_0
 +              y := v_1
 +              if !(shiftIsBounded(v)) {
 +                      break
 +              }
 +              v.reset(OpAMD64SARW)
 +              v.AddArg2(x, y)
 +              return true
 +      }
 +      return false
 +}
 +func rewriteValueAMD64_OpRsh32Ux16(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (Rsh32Ux16 <t> x y)
 +      // cond: !shiftIsBounded(v)
 +      // result: (ANDL (SHRL <t> x y) (SBBLcarrymask <t> (CMPWconst y [32])))
 +      for {
 +              t := v.Type
 +              x := v_0
 +              y := v_1
 +              if !(!shiftIsBounded(v)) {
 +                      break
 +              }
 +              v.reset(OpAMD64ANDL)
 +              v0 := b.NewValue0(v.Pos, OpAMD64SHRL, t)
 +              v0.AddArg2(x, y)
 +              v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t)
 +              v2 := b.NewValue0(v.Pos, OpAMD64CMPWconst, types.TypeFlags)
 +              v2.AuxInt = int16ToAuxInt(32)
 +              v2.AddArg(y)
 +              v1.AddArg(v2)
 +              v.AddArg2(v0, v1)
 +              return true
 +      }
 +      // match: (Rsh32Ux16 x y)
 +      // cond: shiftIsBounded(v)
 +      // result: (SHRL x y)
 +      for {
 +              x := v_0
 +              y := v_1
 +              if !(shiftIsBounded(v)) {
 +                      break
 +              }
 +              v.reset(OpAMD64SHRL)
 +              v.AddArg2(x, y)
 +              return true
 +      }
 +      return false
 +}
 +func rewriteValueAMD64_OpRsh32Ux32(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (Rsh32Ux32 <t> x y)
 +      // cond: !shiftIsBounded(v)
 +      // result: (ANDL (SHRL <t> x y) (SBBLcarrymask <t> (CMPLconst y [32])))
 +      for {
 +              t := v.Type
 +              x := v_0
 +              y := v_1
 +              if !(!shiftIsBounded(v)) {
 +                      break
 +              }
 +              v.reset(OpAMD64ANDL)
 +              v0 := b.NewValue0(v.Pos, OpAMD64SHRL, t)
 +              v0.AddArg2(x, y)
 +              v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t)
 +              v2 := b.NewValue0(v.Pos, OpAMD64CMPLconst, types.TypeFlags)
 +              v2.AuxInt = int32ToAuxInt(32)
 +              v2.AddArg(y)
 +              v1.AddArg(v2)
 +              v.AddArg2(v0, v1)
 +              return true
 +      }
 +      // match: (Rsh32Ux32 x y)
 +      // cond: shiftIsBounded(v)
 +      // result: (SHRL x y)
 +      for {
 +              x := v_0
 +              y := v_1
 +              if !(shiftIsBounded(v)) {
 +                      break
 +              }
 +              v.reset(OpAMD64SHRL)
 +              v.AddArg2(x, y)
 +              return true
 +      }
 +      return false
 +}
 +func rewriteValueAMD64_OpRsh32Ux64(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (Rsh32Ux64 <t> x y)
 +      // cond: !shiftIsBounded(v)
 +      // result: (ANDL (SHRL <t> x y) (SBBLcarrymask <t> (CMPQconst y [32])))
 +      for {
 +              t := v.Type
 +              x := v_0
 +              y := v_1
 +              if !(!shiftIsBounded(v)) {
 +                      break
 +              }
 +              v.reset(OpAMD64ANDL)
 +              v0 := b.NewValue0(v.Pos, OpAMD64SHRL, t)
 +              v0.AddArg2(x, y)
 +              v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t)
 +              v2 := b.NewValue0(v.Pos, OpAMD64CMPQconst, types.TypeFlags)
 +              v2.AuxInt = int32ToAuxInt(32)
 +              v2.AddArg(y)
 +              v1.AddArg(v2)
 +              v.AddArg2(v0, v1)
 +              return true
 +      }
 +      // match: (Rsh32Ux64 x y)
 +      // cond: shiftIsBounded(v)
 +      // result: (SHRL x y)
 +      for {
 +              x := v_0
 +              y := v_1
 +              if !(shiftIsBounded(v)) {
 +                      break
 +              }
 +              v.reset(OpAMD64SHRL)
 +              v.AddArg2(x, y)
 +              return true
 +      }
 +      return false
 +}
 +func rewriteValueAMD64_OpRsh32Ux8(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (Rsh32Ux8 <t> x y)
 +      // cond: !shiftIsBounded(v)
 +      // result: (ANDL (SHRL <t> x y) (SBBLcarrymask <t> (CMPBconst y [32])))
 +      for {
 +              t := v.Type
 +              x := v_0
 +              y := v_1
 +              if !(!shiftIsBounded(v)) {
 +                      break
 +              }
 +              v.reset(OpAMD64ANDL)
 +              v0 := b.NewValue0(v.Pos, OpAMD64SHRL, t)
 +              v0.AddArg2(x, y)
 +              v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t)
 +              v2 := b.NewValue0(v.Pos, OpAMD64CMPBconst, types.TypeFlags)
 +              v2.AuxInt = int8ToAuxInt(32)
 +              v2.AddArg(y)
 +              v1.AddArg(v2)
 +              v.AddArg2(v0, v1)
 +              return true
 +      }
 +      // match: (Rsh32Ux8 x y)
 +      // cond: shiftIsBounded(v)
 +      // result: (SHRL x y)
 +      for {
 +              x := v_0
 +              y := v_1
 +              if !(shiftIsBounded(v)) {
 +                      break
 +              }
 +              v.reset(OpAMD64SHRL)
 +              v.AddArg2(x, y)
 +              return true
 +      }
 +      return false
 +}
 +func rewriteValueAMD64_OpRsh32x16(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (Rsh32x16 <t> x y)
 +      // cond: !shiftIsBounded(v)
 +      // result: (SARL <t> x (ORL <y.Type> y (NOTL <y.Type> (SBBLcarrymask <y.Type> (CMPWconst y [32])))))
 +      for {
 +              t := v.Type
 +              x := v_0
 +              y := v_1
 +              if !(!shiftIsBounded(v)) {
 +                      break
 +              }
 +              v.reset(OpAMD64SARL)
 +              v.Type = t
 +              v0 := b.NewValue0(v.Pos, OpAMD64ORL, y.Type)
 +              v1 := b.NewValue0(v.Pos, OpAMD64NOTL, y.Type)
 +              v2 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, y.Type)
 +              v3 := b.NewValue0(v.Pos, OpAMD64CMPWconst, types.TypeFlags)
 +              v3.AuxInt = int16ToAuxInt(32)
 +              v3.AddArg(y)
 +              v2.AddArg(v3)
 +              v1.AddArg(v2)
 +              v0.AddArg2(y, v1)
 +              v.AddArg2(x, v0)
 +              return true
 +      }
 +      // match: (Rsh32x16 x y)
 +      // cond: shiftIsBounded(v)
 +      // result: (SARL x y)
 +      for {
 +              x := v_0
 +              y := v_1
 +              if !(shiftIsBounded(v)) {
 +                      break
 +              }
 +              v.reset(OpAMD64SARL)
 +              v.AddArg2(x, y)
 +              return true
 +      }
 +      return false
 +}
 +func rewriteValueAMD64_OpRsh32x32(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (Rsh32x32 <t> x y)
 +      // cond: !shiftIsBounded(v)
 +      // result: (SARL <t> x (ORL <y.Type> y (NOTL <y.Type> (SBBLcarrymask <y.Type> (CMPLconst y [32])))))
 +      for {
 +              t := v.Type
 +              x := v_0
 +              y := v_1
 +              if !(!shiftIsBounded(v)) {
 +                      break
 +              }
 +              v.reset(OpAMD64SARL)
 +              v.Type = t
 +              v0 := b.NewValue0(v.Pos, OpAMD64ORL, y.Type)
 +              v1 := b.NewValue0(v.Pos, OpAMD64NOTL, y.Type)
 +              v2 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, y.Type)
 +              v3 := b.NewValue0(v.Pos, OpAMD64CMPLconst, types.TypeFlags)
 +              v3.AuxInt = int32ToAuxInt(32)
 +              v3.AddArg(y)
 +              v2.AddArg(v3)
 +              v1.AddArg(v2)
 +              v0.AddArg2(y, v1)
 +              v.AddArg2(x, v0)
 +              return true
 +      }
 +      // match: (Rsh32x32 x y)
 +      // cond: shiftIsBounded(v)
 +      // result: (SARL x y)
 +      for {
 +              x := v_0
 +              y := v_1
 +              if !(shiftIsBounded(v)) {
 +                      break
 +              }
 +              v.reset(OpAMD64SARL)
 +              v.AddArg2(x, y)
 +              return true
 +      }
 +      return false
 +}
 +func rewriteValueAMD64_OpRsh32x64(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (Rsh32x64 <t> x y)
 +      // cond: !shiftIsBounded(v)
 +      // result: (SARL <t> x (ORQ <y.Type> y (NOTQ <y.Type> (SBBQcarrymask <y.Type> (CMPQconst y [32])))))
 +      for {
 +              t := v.Type
 +              x := v_0
 +              y := v_1
 +              if !(!shiftIsBounded(v)) {
 +                      break
 +              }
 +              v.reset(OpAMD64SARL)
 +              v.Type = t
 +              v0 := b.NewValue0(v.Pos, OpAMD64ORQ, y.Type)
 +              v1 := b.NewValue0(v.Pos, OpAMD64NOTQ, y.Type)
 +              v2 := b.NewValue0(v.Pos, OpAMD64SBBQcarrymask, y.Type)
 +              v3 := b.NewValue0(v.Pos, OpAMD64CMPQconst, types.TypeFlags)
 +              v3.AuxInt = int32ToAuxInt(32)
 +              v3.AddArg(y)
 +              v2.AddArg(v3)
 +              v1.AddArg(v2)
 +              v0.AddArg2(y, v1)
 +              v.AddArg2(x, v0)
 +              return true
 +      }
 +      // match: (Rsh32x64 x y)
 +      // cond: shiftIsBounded(v)
 +      // result: (SARL x y)
 +      for {
 +              x := v_0
 +              y := v_1
 +              if !(shiftIsBounded(v)) {
 +                      break
 +              }
 +              v.reset(OpAMD64SARL)
 +              v.AddArg2(x, y)
 +              return true
 +      }
 +      return false
 +}
 +func rewriteValueAMD64_OpRsh32x8(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (Rsh32x8 <t> x y)
 +      // cond: !shiftIsBounded(v)
 +      // result: (SARL <t> x (ORL <y.Type> y (NOTL <y.Type> (SBBLcarrymask <y.Type> (CMPBconst y [32])))))
 +      for {
 +              t := v.Type
 +              x := v_0
 +              y := v_1
 +              if !(!shiftIsBounded(v)) {
 +                      break
 +              }
 +              v.reset(OpAMD64SARL)
 +              v.Type = t
 +              v0 := b.NewValue0(v.Pos, OpAMD64ORL, y.Type)
 +              v1 := b.NewValue0(v.Pos, OpAMD64NOTL, y.Type)
 +              v2 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, y.Type)
 +              v3 := b.NewValue0(v.Pos, OpAMD64CMPBconst, types.TypeFlags)
 +              v3.AuxInt = int8ToAuxInt(32)
 +              v3.AddArg(y)
 +              v2.AddArg(v3)
 +              v1.AddArg(v2)
 +              v0.AddArg2(y, v1)
 +              v.AddArg2(x, v0)
 +              return true
 +      }
 +      // match: (Rsh32x8 x y)
 +      // cond: shiftIsBounded(v)
 +      // result: (SARL x y)
 +      for {
 +              x := v_0
 +              y := v_1
 +              if !(shiftIsBounded(v)) {
 +                      break
 +              }
 +              v.reset(OpAMD64SARL)
 +              v.AddArg2(x, y)
 +              return true
 +      }
 +      return false
 +}
 +func rewriteValueAMD64_OpRsh64Ux16(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (Rsh64Ux16 <t> x y)
 +      // cond: !shiftIsBounded(v)
 +      // result: (ANDQ (SHRQ <t> x y) (SBBQcarrymask <t> (CMPWconst y [64])))
 +      for {
 +              t := v.Type
 +              x := v_0
 +              y := v_1
 +              if !(!shiftIsBounded(v)) {
 +                      break
 +              }
 +              v.reset(OpAMD64ANDQ)
 +              v0 := b.NewValue0(v.Pos, OpAMD64SHRQ, t)
 +              v0.AddArg2(x, y)
 +              v1 := b.NewValue0(v.Pos, OpAMD64SBBQcarrymask, t)
 +              v2 := b.NewValue0(v.Pos, OpAMD64CMPWconst, types.TypeFlags)
 +              v2.AuxInt = int16ToAuxInt(64)
 +              v2.AddArg(y)
 +              v1.AddArg(v2)
 +              v.AddArg2(v0, v1)
 +              return true
 +      }
 +      // match: (Rsh64Ux16 x y)
 +      // cond: shiftIsBounded(v)
 +      // result: (SHRQ x y)
 +      for {
 +              x := v_0
 +              y := v_1
 +              if !(shiftIsBounded(v)) {
 +                      break
 +              }
 +              v.reset(OpAMD64SHRQ)
 +              v.AddArg2(x, y)
 +              return true
 +      }
 +      return false
 +}
 +func rewriteValueAMD64_OpRsh64Ux32(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (Rsh64Ux32 <t> x y)
 +      // cond: !shiftIsBounded(v)
 +      // result: (ANDQ (SHRQ <t> x y) (SBBQcarrymask <t> (CMPLconst y [64])))
 +      for {
 +              t := v.Type
 +              x := v_0
 +              y := v_1
 +              if !(!shiftIsBounded(v)) {
 +                      break
 +              }
 +              v.reset(OpAMD64ANDQ)
 +              v0 := b.NewValue0(v.Pos, OpAMD64SHRQ, t)
 +              v0.AddArg2(x, y)
 +              v1 := b.NewValue0(v.Pos, OpAMD64SBBQcarrymask, t)
 +              v2 := b.NewValue0(v.Pos, OpAMD64CMPLconst, types.TypeFlags)
 +              v2.AuxInt = int32ToAuxInt(64)
 +              v2.AddArg(y)
 +              v1.AddArg(v2)
 +              v.AddArg2(v0, v1)
 +              return true
 +      }
 +      // match: (Rsh64Ux32 x y)
 +      // cond: shiftIsBounded(v)
 +      // result: (SHRQ x y)
 +      for {
 +              x := v_0
 +              y := v_1
 +              if !(shiftIsBounded(v)) {
 +                      break
 +              }
 +              v.reset(OpAMD64SHRQ)
 +              v.AddArg2(x, y)
 +              return true
 +      }
 +      return false
 +}
 +func rewriteValueAMD64_OpRsh64Ux64(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (Rsh64Ux64 <t> x y)
 +      // cond: !shiftIsBounded(v)
 +      // result: (ANDQ (SHRQ <t> x y) (SBBQcarrymask <t> (CMPQconst y [64])))
 +      for {
 +              t := v.Type
 +              x := v_0
 +              y := v_1
 +              if !(!shiftIsBounded(v)) {
 +                      break
 +              }
 +              v.reset(OpAMD64ANDQ)
 +              v0 := b.NewValue0(v.Pos, OpAMD64SHRQ, t)
 +              v0.AddArg2(x, y)
 +              v1 := b.NewValue0(v.Pos, OpAMD64SBBQcarrymask, t)
 +              v2 := b.NewValue0(v.Pos, OpAMD64CMPQconst, types.TypeFlags)
 +              v2.AuxInt = int32ToAuxInt(64)
 +              v2.AddArg(y)
 +              v1.AddArg(v2)
 +              v.AddArg2(v0, v1)
 +              return true
 +      }
 +      // match: (Rsh64Ux64 x y)
 +      // cond: shiftIsBounded(v)
 +      // result: (SHRQ x y)
 +      for {
 +              x := v_0
 +              y := v_1
 +              if !(shiftIsBounded(v)) {
 +                      break
 +              }
 +              v.reset(OpAMD64SHRQ)
 +              v.AddArg2(x, y)
 +              return true
 +      }
 +      return false
 +}
 +func rewriteValueAMD64_OpRsh64Ux8(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (Rsh64Ux8 <t> x y)
 +      // cond: !shiftIsBounded(v)
 +      // result: (ANDQ (SHRQ <t> x y) (SBBQcarrymask <t> (CMPBconst y [64])))
 +      for {
 +              t := v.Type
 +              x := v_0
 +              y := v_1
 +              if !(!shiftIsBounded(v)) {
 +                      break
 +              }
 +              v.reset(OpAMD64ANDQ)
 +              v0 := b.NewValue0(v.Pos, OpAMD64SHRQ, t)
 +              v0.AddArg2(x, y)
 +              v1 := b.NewValue0(v.Pos, OpAMD64SBBQcarrymask, t)
 +              v2 := b.NewValue0(v.Pos, OpAMD64CMPBconst, types.TypeFlags)
 +              v2.AuxInt = int8ToAuxInt(64)
 +              v2.AddArg(y)
 +              v1.AddArg(v2)
 +              v.AddArg2(v0, v1)
 +              return true
 +      }
 +      // match: (Rsh64Ux8 x y)
 +      // cond: shiftIsBounded(v)
 +      // result: (SHRQ x y)
 +      for {
 +              x := v_0
 +              y := v_1
 +              if !(shiftIsBounded(v)) {
 +                      break
 +              }
 +              v.reset(OpAMD64SHRQ)
 +              v.AddArg2(x, y)
 +              return true
 +      }
 +      return false
 +}
 +func rewriteValueAMD64_OpRsh64x16(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (Rsh64x16 <t> x y)
 +      // cond: !shiftIsBounded(v)
 +      // result: (SARQ <t> x (ORL <y.Type> y (NOTL <y.Type> (SBBLcarrymask <y.Type> (CMPWconst y [64])))))
 +      for {
 +              t := v.Type
 +              x := v_0
 +              y := v_1
 +              if !(!shiftIsBounded(v)) {
 +                      break
 +              }
 +              v.reset(OpAMD64SARQ)
 +              v.Type = t
 +              v0 := b.NewValue0(v.Pos, OpAMD64ORL, y.Type)
 +              v1 := b.NewValue0(v.Pos, OpAMD64NOTL, y.Type)
 +              v2 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, y.Type)
 +              v3 := b.NewValue0(v.Pos, OpAMD64CMPWconst, types.TypeFlags)
 +              v3.AuxInt = int16ToAuxInt(64)
 +              v3.AddArg(y)
 +              v2.AddArg(v3)
 +              v1.AddArg(v2)
 +              v0.AddArg2(y, v1)
 +              v.AddArg2(x, v0)
 +              return true
 +      }
 +      // match: (Rsh64x16 x y)
 +      // cond: shiftIsBounded(v)
 +      // result: (SARQ x y)
 +      for {
 +              x := v_0
 +              y := v_1
 +              if !(shiftIsBounded(v)) {
 +                      break
 +              }
 +              v.reset(OpAMD64SARQ)
 +              v.AddArg2(x, y)
 +              return true
 +      }
 +      return false
 +}
 +func rewriteValueAMD64_OpRsh64x32(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (Rsh64x32 <t> x y)
 +      // cond: !shiftIsBounded(v)
 +      // result: (SARQ <t> x (ORL <y.Type> y (NOTL <y.Type> (SBBLcarrymask <y.Type> (CMPLconst y [64])))))
 +      for {
 +              t := v.Type
 +              x := v_0
 +              y := v_1
 +              if !(!shiftIsBounded(v)) {
 +                      break
 +              }
 +              v.reset(OpAMD64SARQ)
 +              v.Type = t
 +              v0 := b.NewValue0(v.Pos, OpAMD64ORL, y.Type)
 +              v1 := b.NewValue0(v.Pos, OpAMD64NOTL, y.Type)
 +              v2 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, y.Type)
 +              v3 := b.NewValue0(v.Pos, OpAMD64CMPLconst, types.TypeFlags)
 +              v3.AuxInt = int32ToAuxInt(64)
 +              v3.AddArg(y)
 +              v2.AddArg(v3)
 +              v1.AddArg(v2)
 +              v0.AddArg2(y, v1)
 +              v.AddArg2(x, v0)
 +              return true
 +      }
 +      // match: (Rsh64x32 x y)
 +      // cond: shiftIsBounded(v)
 +      // result: (SARQ x y)
 +      for {
 +              x := v_0
 +              y := v_1
 +              if !(shiftIsBounded(v)) {
 +                      break
 +              }
 +              v.reset(OpAMD64SARQ)
 +              v.AddArg2(x, y)
 +              return true
 +      }
 +      return false
 +}
 +func rewriteValueAMD64_OpRsh64x64(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (Rsh64x64 <t> x y)
 +      // cond: !shiftIsBounded(v)
 +      // result: (SARQ <t> x (ORQ <y.Type> y (NOTQ <y.Type> (SBBQcarrymask <y.Type> (CMPQconst y [64])))))
 +      for {
 +              t := v.Type
 +              x := v_0
 +              y := v_1
 +              if !(!shiftIsBounded(v)) {
 +                      break
 +              }
 +              v.reset(OpAMD64SARQ)
 +              v.Type = t
 +              v0 := b.NewValue0(v.Pos, OpAMD64ORQ, y.Type)
 +              v1 := b.NewValue0(v.Pos, OpAMD64NOTQ, y.Type)
 +              v2 := b.NewValue0(v.Pos, OpAMD64SBBQcarrymask, y.Type)
 +              v3 := b.NewValue0(v.Pos, OpAMD64CMPQconst, types.TypeFlags)
 +              v3.AuxInt = int32ToAuxInt(64)
 +              v3.AddArg(y)
 +              v2.AddArg(v3)
 +              v1.AddArg(v2)
 +              v0.AddArg2(y, v1)
 +              v.AddArg2(x, v0)
 +              return true
 +      }
 +      // match: (Rsh64x64 x y)
 +      // cond: shiftIsBounded(v)
 +      // result: (SARQ x y)
 +      for {
 +              x := v_0
 +              y := v_1
 +              if !(shiftIsBounded(v)) {
 +                      break
 +              }
 +              v.reset(OpAMD64SARQ)
 +              v.AddArg2(x, y)
 +              return true
 +      }
 +      return false
 +}
 +func rewriteValueAMD64_OpRsh64x8(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (Rsh64x8 <t> x y)
 +      // cond: !shiftIsBounded(v)
 +      // result: (SARQ <t> x (ORL <y.Type> y (NOTL <y.Type> (SBBLcarrymask <y.Type> (CMPBconst y [64])))))
 +      for {
 +              t := v.Type
 +              x := v_0
 +              y := v_1
 +              if !(!shiftIsBounded(v)) {
 +                      break
 +              }
 +              v.reset(OpAMD64SARQ)
 +              v.Type = t
 +              v0 := b.NewValue0(v.Pos, OpAMD64ORL, y.Type)
 +              v1 := b.NewValue0(v.Pos, OpAMD64NOTL, y.Type)
 +              v2 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, y.Type)
 +              v3 := b.NewValue0(v.Pos, OpAMD64CMPBconst, types.TypeFlags)
 +              v3.AuxInt = int8ToAuxInt(64)
 +              v3.AddArg(y)
 +              v2.AddArg(v3)
 +              v1.AddArg(v2)
 +              v0.AddArg2(y, v1)
 +              v.AddArg2(x, v0)
 +              return true
 +      }
 +      // match: (Rsh64x8 x y)
 +      // cond: shiftIsBounded(v)
 +      // result: (SARQ x y)
 +      for {
 +              x := v_0
 +              y := v_1
 +              if !(shiftIsBounded(v)) {
 +                      break
 +              }
 +              v.reset(OpAMD64SARQ)
 +              v.AddArg2(x, y)
 +              return true
 +      }
 +      return false
 +}
 +func rewriteValueAMD64_OpRsh8Ux16(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (Rsh8Ux16 <t> x y)
 +      // cond: !shiftIsBounded(v)
 +      // result: (ANDL (SHRB <t> x y) (SBBLcarrymask <t> (CMPWconst y [8])))
 +      for {
 +              t := v.Type
 +              x := v_0
 +              y := v_1
 +              if !(!shiftIsBounded(v)) {
 +                      break
 +              }
 +              v.reset(OpAMD64ANDL)
 +              v0 := b.NewValue0(v.Pos, OpAMD64SHRB, t)
 +              v0.AddArg2(x, y)
 +              v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t)
 +              v2 := b.NewValue0(v.Pos, OpAMD64CMPWconst, types.TypeFlags)
 +              v2.AuxInt = int16ToAuxInt(8)
 +              v2.AddArg(y)
 +              v1.AddArg(v2)
 +              v.AddArg2(v0, v1)
 +              return true
 +      }
 +      // match: (Rsh8Ux16 x y)
 +      // cond: shiftIsBounded(v)
 +      // result: (SHRB x y)
 +      for {
 +              x := v_0
 +              y := v_1
 +              if !(shiftIsBounded(v)) {
 +                      break
 +              }
 +              v.reset(OpAMD64SHRB)
 +              v.AddArg2(x, y)
 +              return true
 +      }
 +      return false
 +}
 +func rewriteValueAMD64_OpRsh8Ux32(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (Rsh8Ux32 <t> x y)
 +      // cond: !shiftIsBounded(v)
 +      // result: (ANDL (SHRB <t> x y) (SBBLcarrymask <t> (CMPLconst y [8])))
 +      for {
 +              t := v.Type
 +              x := v_0
 +              y := v_1
 +              if !(!shiftIsBounded(v)) {
 +                      break
 +              }
 +              v.reset(OpAMD64ANDL)
 +              v0 := b.NewValue0(v.Pos, OpAMD64SHRB, t)
 +              v0.AddArg2(x, y)
 +              v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t)
 +              v2 := b.NewValue0(v.Pos, OpAMD64CMPLconst, types.TypeFlags)
 +              v2.AuxInt = int32ToAuxInt(8)
 +              v2.AddArg(y)
 +              v1.AddArg(v2)
 +              v.AddArg2(v0, v1)
 +              return true
 +      }
 +      // match: (Rsh8Ux32 x y)
 +      // cond: shiftIsBounded(v)
 +      // result: (SHRB x y)
 +      for {
 +              x := v_0
 +              y := v_1
 +              if !(shiftIsBounded(v)) {
 +                      break
 +              }
 +              v.reset(OpAMD64SHRB)
 +              v.AddArg2(x, y)
 +              return true
 +      }
 +      return false
 +}
 +func rewriteValueAMD64_OpRsh8Ux64(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (Rsh8Ux64 <t> x y)
 +      // cond: !shiftIsBounded(v)
 +      // result: (ANDL (SHRB <t> x y) (SBBLcarrymask <t> (CMPQconst y [8])))
 +      for {
 +              t := v.Type
 +              x := v_0
 +              y := v_1
 +              if !(!shiftIsBounded(v)) {
 +                      break
 +              }
 +              v.reset(OpAMD64ANDL)
 +              v0 := b.NewValue0(v.Pos, OpAMD64SHRB, t)
 +              v0.AddArg2(x, y)
 +              v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t)
 +              v2 := b.NewValue0(v.Pos, OpAMD64CMPQconst, types.TypeFlags)
 +              v2.AuxInt = int32ToAuxInt(8)
 +              v2.AddArg(y)
 +              v1.AddArg(v2)
 +              v.AddArg2(v0, v1)
 +              return true
 +      }
 +      // match: (Rsh8Ux64 x y)
 +      // cond: shiftIsBounded(v)
 +      // result: (SHRB x y)
 +      for {
 +              x := v_0
 +              y := v_1
 +              if !(shiftIsBounded(v)) {
 +                      break
 +              }
 +              v.reset(OpAMD64SHRB)
 +              v.AddArg2(x, y)
 +              return true
 +      }
 +      return false
 +}
 +func rewriteValueAMD64_OpRsh8Ux8(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (Rsh8Ux8 <t> x y)
 +      // cond: !shiftIsBounded(v)
 +      // result: (ANDL (SHRB <t> x y) (SBBLcarrymask <t> (CMPBconst y [8])))
 +      for {
 +              t := v.Type
 +              x := v_0
 +              y := v_1
 +              if !(!shiftIsBounded(v)) {
 +                      break
 +              }
 +              v.reset(OpAMD64ANDL)
 +              v0 := b.NewValue0(v.Pos, OpAMD64SHRB, t)
 +              v0.AddArg2(x, y)
 +              v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t)
 +              v2 := b.NewValue0(v.Pos, OpAMD64CMPBconst, types.TypeFlags)
 +              v2.AuxInt = int8ToAuxInt(8)
 +              v2.AddArg(y)
 +              v1.AddArg(v2)
 +              v.AddArg2(v0, v1)
 +              return true
 +      }
 +      // match: (Rsh8Ux8 x y)
 +      // cond: shiftIsBounded(v)
 +      // result: (SHRB x y)
 +      for {
 +              x := v_0
 +              y := v_1
 +              if !(shiftIsBounded(v)) {
 +                      break
 +              }
 +              v.reset(OpAMD64SHRB)
 +              v.AddArg2(x, y)
 +              return true
 +      }
 +      return false
 +}
 +func rewriteValueAMD64_OpRsh8x16(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (Rsh8x16 <t> x y)
 +      // cond: !shiftIsBounded(v)
 +      // result: (SARB <t> x (ORL <y.Type> y (NOTL <y.Type> (SBBLcarrymask <y.Type> (CMPWconst y [8])))))
 +      for {
 +              t := v.Type
 +              x := v_0
 +              y := v_1
 +              if !(!shiftIsBounded(v)) {
 +                      break
 +              }
 +              v.reset(OpAMD64SARB)
 +              v.Type = t
 +              v0 := b.NewValue0(v.Pos, OpAMD64ORL, y.Type)
 +              v1 := b.NewValue0(v.Pos, OpAMD64NOTL, y.Type)
 +              v2 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, y.Type)
 +              v3 := b.NewValue0(v.Pos, OpAMD64CMPWconst, types.TypeFlags)
 +              v3.AuxInt = int16ToAuxInt(8)
 +              v3.AddArg(y)
 +              v2.AddArg(v3)
 +              v1.AddArg(v2)
 +              v0.AddArg2(y, v1)
 +              v.AddArg2(x, v0)
 +              return true
 +      }
 +      // match: (Rsh8x16 x y)
 +      // cond: shiftIsBounded(v)
 +      // result: (SARB x y)
 +      for {
 +              x := v_0
 +              y := v_1
 +              if !(shiftIsBounded(v)) {
 +                      break
 +              }
 +              v.reset(OpAMD64SARB)
 +              v.AddArg2(x, y)
 +              return true
 +      }
 +      return false
 +}
 +func rewriteValueAMD64_OpRsh8x32(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (Rsh8x32 <t> x y)
 +      // cond: !shiftIsBounded(v)
 +      // result: (SARB <t> x (ORL <y.Type> y (NOTL <y.Type> (SBBLcarrymask <y.Type> (CMPLconst y [8])))))
 +      for {
 +              t := v.Type
 +              x := v_0
 +              y := v_1
 +              if !(!shiftIsBounded(v)) {
 +                      break
 +              }
 +              v.reset(OpAMD64SARB)
 +              v.Type = t
 +              v0 := b.NewValue0(v.Pos, OpAMD64ORL, y.Type)
 +              v1 := b.NewValue0(v.Pos, OpAMD64NOTL, y.Type)
 +              v2 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, y.Type)
 +              v3 := b.NewValue0(v.Pos, OpAMD64CMPLconst, types.TypeFlags)
 +              v3.AuxInt = int32ToAuxInt(8)
 +              v3.AddArg(y)
 +              v2.AddArg(v3)
 +              v1.AddArg(v2)
 +              v0.AddArg2(y, v1)
 +              v.AddArg2(x, v0)
 +              return true
 +      }
 +      // match: (Rsh8x32 x y)
 +      // cond: shiftIsBounded(v)
 +      // result: (SARB x y)
 +      for {
 +              x := v_0
 +              y := v_1
 +              if !(shiftIsBounded(v)) {
 +                      break
 +              }
 +              v.reset(OpAMD64SARB)
 +              v.AddArg2(x, y)
 +              return true
 +      }
 +      return false
 +}
 +func rewriteValueAMD64_OpRsh8x64(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (Rsh8x64 <t> x y)
 +      // cond: !shiftIsBounded(v)
 +      // result: (SARB <t> x (ORQ <y.Type> y (NOTQ <y.Type> (SBBQcarrymask <y.Type> (CMPQconst y [8])))))
 +      for {
 +              t := v.Type
 +              x := v_0
 +              y := v_1
 +              if !(!shiftIsBounded(v)) {
 +                      break
 +              }
 +              v.reset(OpAMD64SARB)
 +              v.Type = t
 +              v0 := b.NewValue0(v.Pos, OpAMD64ORQ, y.Type)
 +              v1 := b.NewValue0(v.Pos, OpAMD64NOTQ, y.Type)
 +              v2 := b.NewValue0(v.Pos, OpAMD64SBBQcarrymask, y.Type)
 +              v3 := b.NewValue0(v.Pos, OpAMD64CMPQconst, types.TypeFlags)
 +              v3.AuxInt = int32ToAuxInt(8)
 +              v3.AddArg(y)
 +              v2.AddArg(v3)
 +              v1.AddArg(v2)
 +              v0.AddArg2(y, v1)
 +              v.AddArg2(x, v0)
 +              return true
 +      }
 +      // match: (Rsh8x64 x y)
 +      // cond: shiftIsBounded(v)
 +      // result: (SARB x y)
 +      for {
 +              x := v_0
 +              y := v_1
 +              if !(shiftIsBounded(v)) {
 +                      break
 +              }
 +              v.reset(OpAMD64SARB)
 +              v.AddArg2(x, y)
 +              return true
 +      }
 +      return false
 +}
 +func rewriteValueAMD64_OpRsh8x8(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (Rsh8x8 <t> x y)
 +      // cond: !shiftIsBounded(v)
 +      // result: (SARB <t> x (ORL <y.Type> y (NOTL <y.Type> (SBBLcarrymask <y.Type> (CMPBconst y [8])))))
 +      for {
 +              t := v.Type
 +              x := v_0
 +              y := v_1
 +              if !(!shiftIsBounded(v)) {
 +                      break
 +              }
 +              v.reset(OpAMD64SARB)
 +              v.Type = t
 +              v0 := b.NewValue0(v.Pos, OpAMD64ORL, y.Type)
 +              v1 := b.NewValue0(v.Pos, OpAMD64NOTL, y.Type)
 +              v2 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, y.Type)
 +              v3 := b.NewValue0(v.Pos, OpAMD64CMPBconst, types.TypeFlags)
 +              v3.AuxInt = int8ToAuxInt(8)
 +              v3.AddArg(y)
 +              v2.AddArg(v3)
 +              v1.AddArg(v2)
 +              v0.AddArg2(y, v1)
 +              v.AddArg2(x, v0)
 +              return true
 +      }
 +      // match: (Rsh8x8 x y)
 +      // cond: shiftIsBounded(v)
 +      // result: (SARB x y)
 +      for {
 +              x := v_0
 +              y := v_1
 +              if !(shiftIsBounded(v)) {
 +                      break
 +              }
 +              v.reset(OpAMD64SARB)
 +              v.AddArg2(x, y)
 +              return true
 +      }
 +      return false
 +}
 +func rewriteValueAMD64_OpScaleMaskedFloat32x16(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (ScaleMaskedFloat32x16 x y mask)
 +      // result: (VSCALEFPSMasked512 x y (VPMOVVec32x16ToM <types.TypeMask> mask))
 +      for {
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VSCALEFPSMasked512)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x16ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg3(x, y, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpScaleMaskedFloat32x4(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (ScaleMaskedFloat32x4 x y mask)
 +      // result: (VSCALEFPSMasked128 x y (VPMOVVec32x4ToM <types.TypeMask> mask))
 +      for {
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VSCALEFPSMasked128)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x4ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg3(x, y, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpScaleMaskedFloat32x8(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (ScaleMaskedFloat32x8 x y mask)
 +      // result: (VSCALEFPSMasked256 x y (VPMOVVec32x8ToM <types.TypeMask> mask))
 +      for {
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VSCALEFPSMasked256)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x8ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg3(x, y, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpScaleMaskedFloat64x2(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (ScaleMaskedFloat64x2 x y mask)
 +      // result: (VSCALEFPDMasked128 x y (VPMOVVec64x2ToM <types.TypeMask> mask))
 +      for {
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VSCALEFPDMasked128)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x2ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg3(x, y, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpScaleMaskedFloat64x4(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (ScaleMaskedFloat64x4 x y mask)
 +      // result: (VSCALEFPDMasked256 x y (VPMOVVec64x4ToM <types.TypeMask> mask))
 +      for {
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VSCALEFPDMasked256)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x4ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg3(x, y, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpScaleMaskedFloat64x8(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (ScaleMaskedFloat64x8 x y mask)
 +      // result: (VSCALEFPDMasked512 x y (VPMOVVec64x8ToM <types.TypeMask> mask))
 +      for {
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VSCALEFPDMasked512)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x8ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg3(x, y, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpSelect0(v *Value) bool {
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      typ := &b.Func.Config.Types
 +      // match: (Select0 (Mul64uover x y))
 +      // result: (Select0 <typ.UInt64> (MULQU x y))
 +      for {
 +              if v_0.Op != OpMul64uover {
 +                      break
 +              }
 +              y := v_0.Args[1]
 +              x := v_0.Args[0]
 +              v.reset(OpSelect0)
 +              v.Type = typ.UInt64
 +              v0 := b.NewValue0(v.Pos, OpAMD64MULQU, types.NewTuple(typ.UInt64, types.TypeFlags))
 +              v0.AddArg2(x, y)
 +              v.AddArg(v0)
 +              return true
 +      }
 +      // match: (Select0 (Mul32uover x y))
 +      // result: (Select0 <typ.UInt32> (MULLU x y))
 +      for {
 +              if v_0.Op != OpMul32uover {
 +                      break
 +              }
 +              y := v_0.Args[1]
 +              x := v_0.Args[0]
 +              v.reset(OpSelect0)
 +              v.Type = typ.UInt32
 +              v0 := b.NewValue0(v.Pos, OpAMD64MULLU, types.NewTuple(typ.UInt32, types.TypeFlags))
 +              v0.AddArg2(x, y)
 +              v.AddArg(v0)
 +              return true
 +      }
 +      // match: (Select0 (Add64carry x y c))
 +      // result: (Select0 <typ.UInt64> (ADCQ x y (Select1 <types.TypeFlags> (NEGLflags c))))
 +      for {
 +              if v_0.Op != OpAdd64carry {
 +                      break
 +              }
 +              c := v_0.Args[2]
 +              x := v_0.Args[0]
 +              y := v_0.Args[1]
 +              v.reset(OpSelect0)
 +              v.Type = typ.UInt64
 +              v0 := b.NewValue0(v.Pos, OpAMD64ADCQ, types.NewTuple(typ.UInt64, types.TypeFlags))
 +              v1 := b.NewValue0(v.Pos, OpSelect1, types.TypeFlags)
 +              v2 := b.NewValue0(v.Pos, OpAMD64NEGLflags, types.NewTuple(typ.UInt32, types.TypeFlags))
 +              v2.AddArg(c)
 +              v1.AddArg(v2)
 +              v0.AddArg3(x, y, v1)
 +              v.AddArg(v0)
 +              return true
 +      }
 +      // match: (Select0 (Sub64borrow x y c))
 +      // result: (Select0 <typ.UInt64> (SBBQ x y (Select1 <types.TypeFlags> (NEGLflags c))))
 +      for {
 +              if v_0.Op != OpSub64borrow {
 +                      break
 +              }
 +              c := v_0.Args[2]
 +              x := v_0.Args[0]
 +              y := v_0.Args[1]
 +              v.reset(OpSelect0)
 +              v.Type = typ.UInt64
 +              v0 := b.NewValue0(v.Pos, OpAMD64SBBQ, types.NewTuple(typ.UInt64, types.TypeFlags))
 +              v1 := b.NewValue0(v.Pos, OpSelect1, types.TypeFlags)
 +              v2 := b.NewValue0(v.Pos, OpAMD64NEGLflags, types.NewTuple(typ.UInt32, types.TypeFlags))
 +              v2.AddArg(c)
 +              v1.AddArg(v2)
 +              v0.AddArg3(x, y, v1)
 +              v.AddArg(v0)
 +              return true
 +      }
 +      // match: (Select0 <t> (AddTupleFirst32 val tuple))
 +      // result: (ADDL val (Select0 <t> tuple))
 +      for {
 +              t := v.Type
 +              if v_0.Op != OpAMD64AddTupleFirst32 {
 +                      break
 +              }
 +              tuple := v_0.Args[1]
 +              val := v_0.Args[0]
 +              v.reset(OpAMD64ADDL)
 +              v0 := b.NewValue0(v.Pos, OpSelect0, t)
 +              v0.AddArg(tuple)
 +              v.AddArg2(val, v0)
 +              return true
 +      }
 +      // match: (Select0 <t> (AddTupleFirst64 val tuple))
 +      // result: (ADDQ val (Select0 <t> tuple))
 +      for {
 +              t := v.Type
 +              if v_0.Op != OpAMD64AddTupleFirst64 {
 +                      break
 +              }
 +              tuple := v_0.Args[1]
 +              val := v_0.Args[0]
 +              v.reset(OpAMD64ADDQ)
 +              v0 := b.NewValue0(v.Pos, OpSelect0, t)
 +              v0.AddArg(tuple)
 +              v.AddArg2(val, v0)
 +              return true
 +      }
 +      // match: (Select0 a:(ADDQconstflags [c] x))
 +      // cond: a.Uses == 1
 +      // result: (ADDQconst [c] x)
 +      for {
 +              a := v_0
 +              if a.Op != OpAMD64ADDQconstflags {
 +                      break
 +              }
 +              c := auxIntToInt32(a.AuxInt)
 +              x := a.Args[0]
 +              if !(a.Uses == 1) {
 +                      break
 +              }
 +              v.reset(OpAMD64ADDQconst)
 +              v.AuxInt = int32ToAuxInt(c)
 +              v.AddArg(x)
 +              return true
 +      }
 +      // match: (Select0 a:(ADDLconstflags [c] x))
 +      // cond: a.Uses == 1
 +      // result: (ADDLconst [c] x)
 +      for {
 +              a := v_0
 +              if a.Op != OpAMD64ADDLconstflags {
 +                      break
 +              }
 +              c := auxIntToInt32(a.AuxInt)
 +              x := a.Args[0]
 +              if !(a.Uses == 1) {
 +                      break
 +              }
 +              v.reset(OpAMD64ADDLconst)
 +              v.AuxInt = int32ToAuxInt(c)
 +              v.AddArg(x)
 +              return true
 +      }
 +      return false
 +}
 +func rewriteValueAMD64_OpSelect1(v *Value) bool {
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      typ := &b.Func.Config.Types
 +      // match: (Select1 (Mul64uover x y))
 +      // result: (SETO (Select1 <types.TypeFlags> (MULQU x y)))
 +      for {
 +              if v_0.Op != OpMul64uover {
 +                      break
 +              }
 +              y := v_0.Args[1]
 +              x := v_0.Args[0]
 +              v.reset(OpAMD64SETO)
 +              v0 := b.NewValue0(v.Pos, OpSelect1, types.TypeFlags)
 +              v1 := b.NewValue0(v.Pos, OpAMD64MULQU, types.NewTuple(typ.UInt64, types.TypeFlags))
 +              v1.AddArg2(x, y)
 +              v0.AddArg(v1)
 +              v.AddArg(v0)
 +              return true
 +      }
 +      // match: (Select1 (Mul32uover x y))
 +      // result: (SETO (Select1 <types.TypeFlags> (MULLU x y)))
 +      for {
 +              if v_0.Op != OpMul32uover {
 +                      break
 +              }
 +              y := v_0.Args[1]
 +              x := v_0.Args[0]
 +              v.reset(OpAMD64SETO)
 +              v0 := b.NewValue0(v.Pos, OpSelect1, types.TypeFlags)
 +              v1 := b.NewValue0(v.Pos, OpAMD64MULLU, types.NewTuple(typ.UInt32, types.TypeFlags))
 +              v1.AddArg2(x, y)
 +              v0.AddArg(v1)
 +              v.AddArg(v0)
 +              return true
 +      }
 +      // match: (Select1 (Add64carry x y c))
 +      // result: (NEGQ <typ.UInt64> (SBBQcarrymask <typ.UInt64> (Select1 <types.TypeFlags> (ADCQ x y (Select1 <types.TypeFlags> (NEGLflags c))))))
 +      for {
 +              if v_0.Op != OpAdd64carry {
 +                      break
 +              }
 +              c := v_0.Args[2]
 +              x := v_0.Args[0]
 +              y := v_0.Args[1]
 +              v.reset(OpAMD64NEGQ)
 +              v.Type = typ.UInt64
 +              v0 := b.NewValue0(v.Pos, OpAMD64SBBQcarrymask, typ.UInt64)
 +              v1 := b.NewValue0(v.Pos, OpSelect1, types.TypeFlags)
 +              v2 := b.NewValue0(v.Pos, OpAMD64ADCQ, types.NewTuple(typ.UInt64, types.TypeFlags))
 +              v3 := b.NewValue0(v.Pos, OpSelect1, types.TypeFlags)
 +              v4 := b.NewValue0(v.Pos, OpAMD64NEGLflags, types.NewTuple(typ.UInt32, types.TypeFlags))
 +              v4.AddArg(c)
 +              v3.AddArg(v4)
 +              v2.AddArg3(x, y, v3)
 +              v1.AddArg(v2)
 +              v0.AddArg(v1)
 +              v.AddArg(v0)
 +              return true
 +      }
 +      // match: (Select1 (Sub64borrow x y c))
 +      // result: (NEGQ <typ.UInt64> (SBBQcarrymask <typ.UInt64> (Select1 <types.TypeFlags> (SBBQ x y (Select1 <types.TypeFlags> (NEGLflags c))))))
 +      for {
 +              if v_0.Op != OpSub64borrow {
 +                      break
 +              }
 +              c := v_0.Args[2]
 +              x := v_0.Args[0]
 +              y := v_0.Args[1]
 +              v.reset(OpAMD64NEGQ)
 +              v.Type = typ.UInt64
 +              v0 := b.NewValue0(v.Pos, OpAMD64SBBQcarrymask, typ.UInt64)
 +              v1 := b.NewValue0(v.Pos, OpSelect1, types.TypeFlags)
 +              v2 := b.NewValue0(v.Pos, OpAMD64SBBQ, types.NewTuple(typ.UInt64, types.TypeFlags))
 +              v3 := b.NewValue0(v.Pos, OpSelect1, types.TypeFlags)
 +              v4 := b.NewValue0(v.Pos, OpAMD64NEGLflags, types.NewTuple(typ.UInt32, types.TypeFlags))
 +              v4.AddArg(c)
 +              v3.AddArg(v4)
 +              v2.AddArg3(x, y, v3)
 +              v1.AddArg(v2)
 +              v0.AddArg(v1)
 +              v.AddArg(v0)
 +              return true
 +      }
 +      // match: (Select1 (NEGLflags (MOVQconst [0])))
 +      // result: (FlagEQ)
 +      for {
 +              if v_0.Op != OpAMD64NEGLflags {
 +                      break
 +              }
 +              v_0_0 := v_0.Args[0]
 +              if v_0_0.Op != OpAMD64MOVQconst || auxIntToInt64(v_0_0.AuxInt) != 0 {
 +                      break
 +              }
 +              v.reset(OpAMD64FlagEQ)
 +              return true
 +      }
 +      // match: (Select1 (NEGLflags (NEGQ (SBBQcarrymask x))))
 +      // result: x
 +      for {
 +              if v_0.Op != OpAMD64NEGLflags {
 +                      break
 +              }
 +              v_0_0 := v_0.Args[0]
 +              if v_0_0.Op != OpAMD64NEGQ {
 +                      break
 +              }
 +              v_0_0_0 := v_0_0.Args[0]
 +              if v_0_0_0.Op != OpAMD64SBBQcarrymask {
 +                      break
 +              }
 +              x := v_0_0_0.Args[0]
 +              v.copyOf(x)
 +              return true
 +      }
 +      // match: (Select1 (AddTupleFirst32 _ tuple))
 +      // result: (Select1 tuple)
 +      for {
 +              if v_0.Op != OpAMD64AddTupleFirst32 {
 +                      break
 +              }
 +              tuple := v_0.Args[1]
 +              v.reset(OpSelect1)
 +              v.AddArg(tuple)
 +              return true
 +      }
 +      // match: (Select1 (AddTupleFirst64 _ tuple))
 +      // result: (Select1 tuple)
 +      for {
 +              if v_0.Op != OpAMD64AddTupleFirst64 {
 +                      break
 +              }
 +              tuple := v_0.Args[1]
 +              v.reset(OpSelect1)
 +              v.AddArg(tuple)
 +              return true
 +      }
 +      // match: (Select1 a:(LoweredAtomicAnd64 ptr val mem))
 +      // cond: a.Uses == 1 && clobber(a)
 +      // result: (ANDQlock ptr val mem)
 +      for {
 +              a := v_0
 +              if a.Op != OpAMD64LoweredAtomicAnd64 {
 +                      break
 +              }
 +              mem := a.Args[2]
 +              ptr := a.Args[0]
 +              val := a.Args[1]
 +              if !(a.Uses == 1 && clobber(a)) {
 +                      break
 +              }
 +              v.reset(OpAMD64ANDQlock)
 +              v.AddArg3(ptr, val, mem)
 +              return true
 +      }
 +      // match: (Select1 a:(LoweredAtomicAnd32 ptr val mem))
 +      // cond: a.Uses == 1 && clobber(a)
 +      // result: (ANDLlock ptr val mem)
 +      for {
 +              a := v_0
 +              if a.Op != OpAMD64LoweredAtomicAnd32 {
 +                      break
 +              }
 +              mem := a.Args[2]
 +              ptr := a.Args[0]
 +              val := a.Args[1]
 +              if !(a.Uses == 1 && clobber(a)) {
 +                      break
 +              }
 +              v.reset(OpAMD64ANDLlock)
 +              v.AddArg3(ptr, val, mem)
 +              return true
 +      }
 +      // match: (Select1 a:(LoweredAtomicOr64 ptr val mem))
 +      // cond: a.Uses == 1 && clobber(a)
 +      // result: (ORQlock ptr val mem)
 +      for {
 +              a := v_0
 +              if a.Op != OpAMD64LoweredAtomicOr64 {
 +                      break
 +              }
 +              mem := a.Args[2]
 +              ptr := a.Args[0]
 +              val := a.Args[1]
 +              if !(a.Uses == 1 && clobber(a)) {
 +                      break
 +              }
 +              v.reset(OpAMD64ORQlock)
 +              v.AddArg3(ptr, val, mem)
 +              return true
 +      }
 +      // match: (Select1 a:(LoweredAtomicOr32 ptr val mem))
 +      // cond: a.Uses == 1 && clobber(a)
 +      // result: (ORLlock ptr val mem)
 +      for {
 +              a := v_0
 +              if a.Op != OpAMD64LoweredAtomicOr32 {
 +                      break
 +              }
 +              mem := a.Args[2]
 +              ptr := a.Args[0]
 +              val := a.Args[1]
 +              if !(a.Uses == 1 && clobber(a)) {
 +                      break
 +              }
 +              v.reset(OpAMD64ORLlock)
 +              v.AddArg3(ptr, val, mem)
 +              return true
 +      }
 +      return false
 +}
 +func rewriteValueAMD64_OpSelectN(v *Value) bool {
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      config := b.Func.Config
 +      // match: (SelectN [0] call:(CALLstatic {sym} s1:(MOVQstoreconst _ [sc] s2:(MOVQstore _ src s3:(MOVQstore _ dst mem)))))
 +      // cond: sc.Val64() >= 0 && isSameCall(sym, "runtime.memmove") && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && isInlinableMemmove(dst, src, sc.Val64(), config) && clobber(s1, s2, s3, call)
 +      // result: (Move [sc.Val64()] dst src mem)
 +      for {
 +              if auxIntToInt64(v.AuxInt) != 0 {
 +                      break
 +              }
 +              call := v_0
 +              if call.Op != OpAMD64CALLstatic || len(call.Args) != 1 {
 +                      break
 +              }
 +              sym := auxToCall(call.Aux)
 +              s1 := call.Args[0]
 +              if s1.Op != OpAMD64MOVQstoreconst {
 +                      break
 +              }
 +              sc := auxIntToValAndOff(s1.AuxInt)
 +              _ = s1.Args[1]
 +              s2 := s1.Args[1]
 +              if s2.Op != OpAMD64MOVQstore {
 +                      break
 +              }
 +              _ = s2.Args[2]
 +              src := s2.Args[1]
 +              s3 := s2.Args[2]
 +              if s3.Op != OpAMD64MOVQstore {
 +                      break
 +              }
 +              mem := s3.Args[2]
 +              dst := s3.Args[1]
 +              if !(sc.Val64() >= 0 && isSameCall(sym, "runtime.memmove") && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && isInlinableMemmove(dst, src, sc.Val64(), config) && clobber(s1, s2, s3, call)) {
 +                      break
 +              }
 +              v.reset(OpMove)
 +              v.AuxInt = int64ToAuxInt(sc.Val64())
 +              v.AddArg3(dst, src, mem)
 +              return true
 +      }
 +      // match: (SelectN [0] call:(CALLstatic {sym} dst src (MOVQconst [sz]) mem))
 +      // cond: sz >= 0 && isSameCall(sym, "runtime.memmove") && call.Uses == 1 && isInlinableMemmove(dst, src, sz, config) && clobber(call)
 +      // result: (Move [sz] dst src mem)
 +      for {
 +              if auxIntToInt64(v.AuxInt) != 0 {
 +                      break
 +              }
 +              call := v_0
 +              if call.Op != OpAMD64CALLstatic || len(call.Args) != 4 {
 +                      break
 +              }
 +              sym := auxToCall(call.Aux)
 +              mem := call.Args[3]
 +              dst := call.Args[0]
 +              src := call.Args[1]
 +              call_2 := call.Args[2]
 +              if call_2.Op != OpAMD64MOVQconst {
 +                      break
 +              }
 +              sz := auxIntToInt64(call_2.AuxInt)
 +              if !(sz >= 0 && isSameCall(sym, "runtime.memmove") && call.Uses == 1 && isInlinableMemmove(dst, src, sz, config) && clobber(call)) {
 +                      break
 +              }
 +              v.reset(OpMove)
 +              v.AuxInt = int64ToAuxInt(sz)
 +              v.AddArg3(dst, src, mem)
 +              return true
 +      }
 +      return false
 +}
 +func rewriteValueAMD64_OpSetHiFloat32x16(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      // match: (SetHiFloat32x16 x y)
 +      // result: (VINSERTF64X4512 [1] x y)
 +      for {
 +              x := v_0
 +              y := v_1
 +              v.reset(OpAMD64VINSERTF64X4512)
 +              v.AuxInt = uint8ToAuxInt(1)
 +              v.AddArg2(x, y)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpSetHiFloat32x8(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      // match: (SetHiFloat32x8 x y)
 +      // result: (VINSERTF128256 [1] x y)
 +      for {
 +              x := v_0
 +              y := v_1
 +              v.reset(OpAMD64VINSERTF128256)
 +              v.AuxInt = uint8ToAuxInt(1)
 +              v.AddArg2(x, y)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpSetHiFloat64x4(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      // match: (SetHiFloat64x4 x y)
 +      // result: (VINSERTF128256 [1] x y)
 +      for {
 +              x := v_0
 +              y := v_1
 +              v.reset(OpAMD64VINSERTF128256)
 +              v.AuxInt = uint8ToAuxInt(1)
 +              v.AddArg2(x, y)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpSetHiFloat64x8(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      // match: (SetHiFloat64x8 x y)
 +      // result: (VINSERTF64X4512 [1] x y)
 +      for {
 +              x := v_0
 +              y := v_1
 +              v.reset(OpAMD64VINSERTF64X4512)
 +              v.AuxInt = uint8ToAuxInt(1)
 +              v.AddArg2(x, y)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpSetHiInt16x16(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      // match: (SetHiInt16x16 x y)
 +      // result: (VINSERTI128256 [1] x y)
 +      for {
 +              x := v_0
 +              y := v_1
 +              v.reset(OpAMD64VINSERTI128256)
 +              v.AuxInt = uint8ToAuxInt(1)
 +              v.AddArg2(x, y)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpSetHiInt16x32(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      // match: (SetHiInt16x32 x y)
 +      // result: (VINSERTI64X4512 [1] x y)
 +      for {
 +              x := v_0
 +              y := v_1
 +              v.reset(OpAMD64VINSERTI64X4512)
 +              v.AuxInt = uint8ToAuxInt(1)
 +              v.AddArg2(x, y)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpSetHiInt32x16(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      // match: (SetHiInt32x16 x y)
 +      // result: (VINSERTI64X4512 [1] x y)
 +      for {
 +              x := v_0
 +              y := v_1
 +              v.reset(OpAMD64VINSERTI64X4512)
 +              v.AuxInt = uint8ToAuxInt(1)
 +              v.AddArg2(x, y)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpSetHiInt32x8(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      // match: (SetHiInt32x8 x y)
 +      // result: (VINSERTI128256 [1] x y)
 +      for {
 +              x := v_0
 +              y := v_1
 +              v.reset(OpAMD64VINSERTI128256)
 +              v.AuxInt = uint8ToAuxInt(1)
 +              v.AddArg2(x, y)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpSetHiInt64x4(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      // match: (SetHiInt64x4 x y)
 +      // result: (VINSERTI128256 [1] x y)
 +      for {
 +              x := v_0
 +              y := v_1
 +              v.reset(OpAMD64VINSERTI128256)
 +              v.AuxInt = uint8ToAuxInt(1)
 +              v.AddArg2(x, y)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpSetHiInt64x8(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      // match: (SetHiInt64x8 x y)
 +      // result: (VINSERTI64X4512 [1] x y)
 +      for {
 +              x := v_0
 +              y := v_1
 +              v.reset(OpAMD64VINSERTI64X4512)
 +              v.AuxInt = uint8ToAuxInt(1)
 +              v.AddArg2(x, y)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpSetHiInt8x32(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      // match: (SetHiInt8x32 x y)
 +      // result: (VINSERTI128256 [1] x y)
 +      for {
 +              x := v_0
 +              y := v_1
 +              v.reset(OpAMD64VINSERTI128256)
 +              v.AuxInt = uint8ToAuxInt(1)
 +              v.AddArg2(x, y)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpSetHiInt8x64(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      // match: (SetHiInt8x64 x y)
 +      // result: (VINSERTI64X4512 [1] x y)
 +      for {
 +              x := v_0
 +              y := v_1
 +              v.reset(OpAMD64VINSERTI64X4512)
 +              v.AuxInt = uint8ToAuxInt(1)
 +              v.AddArg2(x, y)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpSetHiUint16x16(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      // match: (SetHiUint16x16 x y)
 +      // result: (VINSERTI128256 [1] x y)
 +      for {
 +              x := v_0
 +              y := v_1
 +              v.reset(OpAMD64VINSERTI128256)
 +              v.AuxInt = uint8ToAuxInt(1)
 +              v.AddArg2(x, y)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpSetHiUint16x32(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      // match: (SetHiUint16x32 x y)
 +      // result: (VINSERTI64X4512 [1] x y)
 +      for {
 +              x := v_0
 +              y := v_1
 +              v.reset(OpAMD64VINSERTI64X4512)
 +              v.AuxInt = uint8ToAuxInt(1)
 +              v.AddArg2(x, y)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpSetHiUint32x16(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      // match: (SetHiUint32x16 x y)
 +      // result: (VINSERTI64X4512 [1] x y)
 +      for {
 +              x := v_0
 +              y := v_1
 +              v.reset(OpAMD64VINSERTI64X4512)
 +              v.AuxInt = uint8ToAuxInt(1)
 +              v.AddArg2(x, y)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpSetHiUint32x8(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      // match: (SetHiUint32x8 x y)
 +      // result: (VINSERTI128256 [1] x y)
 +      for {
 +              x := v_0
 +              y := v_1
 +              v.reset(OpAMD64VINSERTI128256)
 +              v.AuxInt = uint8ToAuxInt(1)
 +              v.AddArg2(x, y)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpSetHiUint64x4(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      // match: (SetHiUint64x4 x y)
 +      // result: (VINSERTI128256 [1] x y)
 +      for {
 +              x := v_0
 +              y := v_1
 +              v.reset(OpAMD64VINSERTI128256)
 +              v.AuxInt = uint8ToAuxInt(1)
 +              v.AddArg2(x, y)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpSetHiUint64x8(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      // match: (SetHiUint64x8 x y)
 +      // result: (VINSERTI64X4512 [1] x y)
 +      for {
 +              x := v_0
 +              y := v_1
 +              v.reset(OpAMD64VINSERTI64X4512)
 +              v.AuxInt = uint8ToAuxInt(1)
 +              v.AddArg2(x, y)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpSetHiUint8x32(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      // match: (SetHiUint8x32 x y)
 +      // result: (VINSERTI128256 [1] x y)
 +      for {
 +              x := v_0
 +              y := v_1
 +              v.reset(OpAMD64VINSERTI128256)
 +              v.AuxInt = uint8ToAuxInt(1)
 +              v.AddArg2(x, y)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpSetHiUint8x64(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      // match: (SetHiUint8x64 x y)
 +      // result: (VINSERTI64X4512 [1] x y)
 +      for {
 +              x := v_0
 +              y := v_1
 +              v.reset(OpAMD64VINSERTI64X4512)
 +              v.AuxInt = uint8ToAuxInt(1)
 +              v.AddArg2(x, y)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpSetLoFloat32x16(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      // match: (SetLoFloat32x16 x y)
 +      // result: (VINSERTF64X4512 [0] x y)
 +      for {
 +              x := v_0
 +              y := v_1
 +              v.reset(OpAMD64VINSERTF64X4512)
 +              v.AuxInt = uint8ToAuxInt(0)
 +              v.AddArg2(x, y)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpSetLoFloat32x8(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      // match: (SetLoFloat32x8 x y)
 +      // result: (VINSERTF128256 [0] x y)
 +      for {
 +              x := v_0
 +              y := v_1
 +              v.reset(OpAMD64VINSERTF128256)
 +              v.AuxInt = uint8ToAuxInt(0)
 +              v.AddArg2(x, y)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpSetLoFloat64x4(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      // match: (SetLoFloat64x4 x y)
 +      // result: (VINSERTF128256 [0] x y)
 +      for {
 +              x := v_0
 +              y := v_1
 +              v.reset(OpAMD64VINSERTF128256)
 +              v.AuxInt = uint8ToAuxInt(0)
 +              v.AddArg2(x, y)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpSetLoFloat64x8(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      // match: (SetLoFloat64x8 x y)
 +      // result: (VINSERTF64X4512 [0] x y)
 +      for {
 +              x := v_0
 +              y := v_1
 +              v.reset(OpAMD64VINSERTF64X4512)
 +              v.AuxInt = uint8ToAuxInt(0)
 +              v.AddArg2(x, y)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpSetLoInt16x16(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      // match: (SetLoInt16x16 x y)
 +      // result: (VINSERTI128256 [0] x y)
 +      for {
 +              x := v_0
 +              y := v_1
 +              v.reset(OpAMD64VINSERTI128256)
 +              v.AuxInt = uint8ToAuxInt(0)
 +              v.AddArg2(x, y)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpSetLoInt16x32(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      // match: (SetLoInt16x32 x y)
 +      // result: (VINSERTI64X4512 [0] x y)
 +      for {
 +              x := v_0
 +              y := v_1
 +              v.reset(OpAMD64VINSERTI64X4512)
 +              v.AuxInt = uint8ToAuxInt(0)
 +              v.AddArg2(x, y)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpSetLoInt32x16(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      // match: (SetLoInt32x16 x y)
 +      // result: (VINSERTI64X4512 [0] x y)
 +      for {
 +              x := v_0
 +              y := v_1
 +              v.reset(OpAMD64VINSERTI64X4512)
 +              v.AuxInt = uint8ToAuxInt(0)
 +              v.AddArg2(x, y)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpSetLoInt32x8(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      // match: (SetLoInt32x8 x y)
 +      // result: (VINSERTI128256 [0] x y)
 +      for {
 +              x := v_0
 +              y := v_1
 +              v.reset(OpAMD64VINSERTI128256)
 +              v.AuxInt = uint8ToAuxInt(0)
 +              v.AddArg2(x, y)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpSetLoInt64x4(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      // match: (SetLoInt64x4 x y)
 +      // result: (VINSERTI128256 [0] x y)
 +      for {
 +              x := v_0
 +              y := v_1
 +              v.reset(OpAMD64VINSERTI128256)
 +              v.AuxInt = uint8ToAuxInt(0)
 +              v.AddArg2(x, y)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpSetLoInt64x8(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      // match: (SetLoInt64x8 x y)
 +      // result: (VINSERTI64X4512 [0] x y)
 +      for {
 +              x := v_0
 +              y := v_1
 +              v.reset(OpAMD64VINSERTI64X4512)
 +              v.AuxInt = uint8ToAuxInt(0)
 +              v.AddArg2(x, y)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpSetLoInt8x32(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      // match: (SetLoInt8x32 x y)
 +      // result: (VINSERTI128256 [0] x y)
 +      for {
 +              x := v_0
 +              y := v_1
 +              v.reset(OpAMD64VINSERTI128256)
 +              v.AuxInt = uint8ToAuxInt(0)
 +              v.AddArg2(x, y)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpSetLoInt8x64(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      // match: (SetLoInt8x64 x y)
 +      // result: (VINSERTI64X4512 [0] x y)
 +      for {
 +              x := v_0
 +              y := v_1
 +              v.reset(OpAMD64VINSERTI64X4512)
 +              v.AuxInt = uint8ToAuxInt(0)
 +              v.AddArg2(x, y)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpSetLoUint16x16(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      // match: (SetLoUint16x16 x y)
 +      // result: (VINSERTI128256 [0] x y)
 +      for {
 +              x := v_0
 +              y := v_1
 +              v.reset(OpAMD64VINSERTI128256)
 +              v.AuxInt = uint8ToAuxInt(0)
 +              v.AddArg2(x, y)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpSetLoUint16x32(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      // match: (SetLoUint16x32 x y)
 +      // result: (VINSERTI64X4512 [0] x y)
 +      for {
 +              x := v_0
 +              y := v_1
 +              v.reset(OpAMD64VINSERTI64X4512)
 +              v.AuxInt = uint8ToAuxInt(0)
 +              v.AddArg2(x, y)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpSetLoUint32x16(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      // match: (SetLoUint32x16 x y)
 +      // result: (VINSERTI64X4512 [0] x y)
 +      for {
 +              x := v_0
 +              y := v_1
 +              v.reset(OpAMD64VINSERTI64X4512)
 +              v.AuxInt = uint8ToAuxInt(0)
 +              v.AddArg2(x, y)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpSetLoUint32x8(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      // match: (SetLoUint32x8 x y)
 +      // result: (VINSERTI128256 [0] x y)
 +      for {
 +              x := v_0
 +              y := v_1
 +              v.reset(OpAMD64VINSERTI128256)
 +              v.AuxInt = uint8ToAuxInt(0)
 +              v.AddArg2(x, y)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpSetLoUint64x4(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      // match: (SetLoUint64x4 x y)
 +      // result: (VINSERTI128256 [0] x y)
 +      for {
 +              x := v_0
 +              y := v_1
 +              v.reset(OpAMD64VINSERTI128256)
 +              v.AuxInt = uint8ToAuxInt(0)
 +              v.AddArg2(x, y)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpSetLoUint64x8(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      // match: (SetLoUint64x8 x y)
 +      // result: (VINSERTI64X4512 [0] x y)
 +      for {
 +              x := v_0
 +              y := v_1
 +              v.reset(OpAMD64VINSERTI64X4512)
 +              v.AuxInt = uint8ToAuxInt(0)
 +              v.AddArg2(x, y)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpSetLoUint8x32(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      // match: (SetLoUint8x32 x y)
 +      // result: (VINSERTI128256 [0] x y)
 +      for {
 +              x := v_0
 +              y := v_1
 +              v.reset(OpAMD64VINSERTI128256)
 +              v.AuxInt = uint8ToAuxInt(0)
 +              v.AddArg2(x, y)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpSetLoUint8x64(v *Value) bool {
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      // match: (SetLoUint8x64 x y)
 +      // result: (VINSERTI64X4512 [0] x y)
 +      for {
 +              x := v_0
 +              y := v_1
 +              v.reset(OpAMD64VINSERTI64X4512)
 +              v.AuxInt = uint8ToAuxInt(0)
 +              v.AddArg2(x, y)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpShiftAllLeftConcatMaskedInt16x16(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (ShiftAllLeftConcatMaskedInt16x16 [a] x y mask)
 +      // result: (VPSHLDWMasked256 [a] x y (VPMOVVec16x16ToM <types.TypeMask> mask))
 +      for {
 +              a := auxIntToUint8(v.AuxInt)
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VPSHLDWMasked256)
 +              v.AuxInt = uint8ToAuxInt(a)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x16ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg3(x, y, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpShiftAllLeftConcatMaskedInt16x32(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (ShiftAllLeftConcatMaskedInt16x32 [a] x y mask)
 +      // result: (VPSHLDWMasked512 [a] x y (VPMOVVec16x32ToM <types.TypeMask> mask))
 +      for {
 +              a := auxIntToUint8(v.AuxInt)
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VPSHLDWMasked512)
 +              v.AuxInt = uint8ToAuxInt(a)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x32ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg3(x, y, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpShiftAllLeftConcatMaskedInt16x8(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (ShiftAllLeftConcatMaskedInt16x8 [a] x y mask)
 +      // result: (VPSHLDWMasked128 [a] x y (VPMOVVec16x8ToM <types.TypeMask> mask))
 +      for {
 +              a := auxIntToUint8(v.AuxInt)
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VPSHLDWMasked128)
 +              v.AuxInt = uint8ToAuxInt(a)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x8ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg3(x, y, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpShiftAllLeftConcatMaskedInt32x16(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (ShiftAllLeftConcatMaskedInt32x16 [a] x y mask)
 +      // result: (VPSHLDDMasked512 [a] x y (VPMOVVec32x16ToM <types.TypeMask> mask))
 +      for {
 +              a := auxIntToUint8(v.AuxInt)
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VPSHLDDMasked512)
 +              v.AuxInt = uint8ToAuxInt(a)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x16ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg3(x, y, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpShiftAllLeftConcatMaskedInt32x4(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (ShiftAllLeftConcatMaskedInt32x4 [a] x y mask)
 +      // result: (VPSHLDDMasked128 [a] x y (VPMOVVec32x4ToM <types.TypeMask> mask))
 +      for {
 +              a := auxIntToUint8(v.AuxInt)
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VPSHLDDMasked128)
 +              v.AuxInt = uint8ToAuxInt(a)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x4ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg3(x, y, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpShiftAllLeftConcatMaskedInt32x8(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (ShiftAllLeftConcatMaskedInt32x8 [a] x y mask)
 +      // result: (VPSHLDDMasked256 [a] x y (VPMOVVec32x8ToM <types.TypeMask> mask))
 +      for {
 +              a := auxIntToUint8(v.AuxInt)
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VPSHLDDMasked256)
 +              v.AuxInt = uint8ToAuxInt(a)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x8ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg3(x, y, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpShiftAllLeftConcatMaskedInt64x2(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (ShiftAllLeftConcatMaskedInt64x2 [a] x y mask)
 +      // result: (VPSHLDQMasked128 [a] x y (VPMOVVec64x2ToM <types.TypeMask> mask))
 +      for {
 +              a := auxIntToUint8(v.AuxInt)
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VPSHLDQMasked128)
 +              v.AuxInt = uint8ToAuxInt(a)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x2ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg3(x, y, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpShiftAllLeftConcatMaskedInt64x4(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (ShiftAllLeftConcatMaskedInt64x4 [a] x y mask)
 +      // result: (VPSHLDQMasked256 [a] x y (VPMOVVec64x4ToM <types.TypeMask> mask))
 +      for {
 +              a := auxIntToUint8(v.AuxInt)
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VPSHLDQMasked256)
 +              v.AuxInt = uint8ToAuxInt(a)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x4ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg3(x, y, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpShiftAllLeftConcatMaskedInt64x8(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (ShiftAllLeftConcatMaskedInt64x8 [a] x y mask)
 +      // result: (VPSHLDQMasked512 [a] x y (VPMOVVec64x8ToM <types.TypeMask> mask))
 +      for {
 +              a := auxIntToUint8(v.AuxInt)
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VPSHLDQMasked512)
 +              v.AuxInt = uint8ToAuxInt(a)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x8ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg3(x, y, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpShiftAllLeftConcatMaskedUint16x16(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (ShiftAllLeftConcatMaskedUint16x16 [a] x y mask)
 +      // result: (VPSHLDWMasked256 [a] x y (VPMOVVec16x16ToM <types.TypeMask> mask))
 +      for {
 +              a := auxIntToUint8(v.AuxInt)
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VPSHLDWMasked256)
 +              v.AuxInt = uint8ToAuxInt(a)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x16ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg3(x, y, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpShiftAllLeftConcatMaskedUint16x32(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (ShiftAllLeftConcatMaskedUint16x32 [a] x y mask)
 +      // result: (VPSHLDWMasked512 [a] x y (VPMOVVec16x32ToM <types.TypeMask> mask))
 +      for {
 +              a := auxIntToUint8(v.AuxInt)
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VPSHLDWMasked512)
 +              v.AuxInt = uint8ToAuxInt(a)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x32ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg3(x, y, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpShiftAllLeftConcatMaskedUint16x8(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (ShiftAllLeftConcatMaskedUint16x8 [a] x y mask)
 +      // result: (VPSHLDWMasked128 [a] x y (VPMOVVec16x8ToM <types.TypeMask> mask))
 +      for {
 +              a := auxIntToUint8(v.AuxInt)
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VPSHLDWMasked128)
 +              v.AuxInt = uint8ToAuxInt(a)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x8ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg3(x, y, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpShiftAllLeftConcatMaskedUint32x16(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (ShiftAllLeftConcatMaskedUint32x16 [a] x y mask)
 +      // result: (VPSHLDDMasked512 [a] x y (VPMOVVec32x16ToM <types.TypeMask> mask))
 +      for {
 +              a := auxIntToUint8(v.AuxInt)
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VPSHLDDMasked512)
 +              v.AuxInt = uint8ToAuxInt(a)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x16ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg3(x, y, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpShiftAllLeftConcatMaskedUint32x4(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (ShiftAllLeftConcatMaskedUint32x4 [a] x y mask)
 +      // result: (VPSHLDDMasked128 [a] x y (VPMOVVec32x4ToM <types.TypeMask> mask))
 +      for {
 +              a := auxIntToUint8(v.AuxInt)
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VPSHLDDMasked128)
 +              v.AuxInt = uint8ToAuxInt(a)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x4ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg3(x, y, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpShiftAllLeftConcatMaskedUint32x8(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (ShiftAllLeftConcatMaskedUint32x8 [a] x y mask)
 +      // result: (VPSHLDDMasked256 [a] x y (VPMOVVec32x8ToM <types.TypeMask> mask))
 +      for {
 +              a := auxIntToUint8(v.AuxInt)
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VPSHLDDMasked256)
 +              v.AuxInt = uint8ToAuxInt(a)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x8ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg3(x, y, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpShiftAllLeftConcatMaskedUint64x2(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (ShiftAllLeftConcatMaskedUint64x2 [a] x y mask)
 +      // result: (VPSHLDQMasked128 [a] x y (VPMOVVec64x2ToM <types.TypeMask> mask))
 +      for {
 +              a := auxIntToUint8(v.AuxInt)
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VPSHLDQMasked128)
 +              v.AuxInt = uint8ToAuxInt(a)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x2ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg3(x, y, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpShiftAllLeftConcatMaskedUint64x4(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (ShiftAllLeftConcatMaskedUint64x4 [a] x y mask)
 +      // result: (VPSHLDQMasked256 [a] x y (VPMOVVec64x4ToM <types.TypeMask> mask))
 +      for {
 +              a := auxIntToUint8(v.AuxInt)
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VPSHLDQMasked256)
 +              v.AuxInt = uint8ToAuxInt(a)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x4ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg3(x, y, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpShiftAllLeftConcatMaskedUint64x8(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (ShiftAllLeftConcatMaskedUint64x8 [a] x y mask)
 +      // result: (VPSHLDQMasked512 [a] x y (VPMOVVec64x8ToM <types.TypeMask> mask))
 +      for {
 +              a := auxIntToUint8(v.AuxInt)
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VPSHLDQMasked512)
 +              v.AuxInt = uint8ToAuxInt(a)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x8ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg3(x, y, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpShiftAllLeftMaskedInt16x16(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (ShiftAllLeftMaskedInt16x16 x y mask)
 +      // result: (VPSLLWMasked256 x y (VPMOVVec16x16ToM <types.TypeMask> mask))
 +      for {
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VPSLLWMasked256)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x16ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg3(x, y, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpShiftAllLeftMaskedInt16x32(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (ShiftAllLeftMaskedInt16x32 x y mask)
 +      // result: (VPSLLWMasked512 x y (VPMOVVec16x32ToM <types.TypeMask> mask))
 +      for {
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VPSLLWMasked512)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x32ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg3(x, y, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpShiftAllLeftMaskedInt16x8(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (ShiftAllLeftMaskedInt16x8 x y mask)
 +      // result: (VPSLLWMasked128 x y (VPMOVVec16x8ToM <types.TypeMask> mask))
 +      for {
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VPSLLWMasked128)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x8ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg3(x, y, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpShiftAllLeftMaskedInt32x16(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (ShiftAllLeftMaskedInt32x16 x y mask)
 +      // result: (VPSLLDMasked512 x y (VPMOVVec32x16ToM <types.TypeMask> mask))
 +      for {
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VPSLLDMasked512)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x16ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg3(x, y, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpShiftAllLeftMaskedInt32x4(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (ShiftAllLeftMaskedInt32x4 x y mask)
 +      // result: (VPSLLDMasked128 x y (VPMOVVec32x4ToM <types.TypeMask> mask))
 +      for {
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VPSLLDMasked128)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x4ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg3(x, y, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpShiftAllLeftMaskedInt32x8(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (ShiftAllLeftMaskedInt32x8 x y mask)
 +      // result: (VPSLLDMasked256 x y (VPMOVVec32x8ToM <types.TypeMask> mask))
 +      for {
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VPSLLDMasked256)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x8ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg3(x, y, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpShiftAllLeftMaskedInt64x2(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (ShiftAllLeftMaskedInt64x2 x y mask)
 +      // result: (VPSLLQMasked128 x y (VPMOVVec64x2ToM <types.TypeMask> mask))
 +      for {
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VPSLLQMasked128)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x2ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg3(x, y, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpShiftAllLeftMaskedInt64x4(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (ShiftAllLeftMaskedInt64x4 x y mask)
 +      // result: (VPSLLQMasked256 x y (VPMOVVec64x4ToM <types.TypeMask> mask))
 +      for {
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VPSLLQMasked256)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x4ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg3(x, y, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpShiftAllLeftMaskedInt64x8(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (ShiftAllLeftMaskedInt64x8 x y mask)
 +      // result: (VPSLLQMasked512 x y (VPMOVVec64x8ToM <types.TypeMask> mask))
 +      for {
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VPSLLQMasked512)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x8ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg3(x, y, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpShiftAllLeftMaskedUint16x16(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (ShiftAllLeftMaskedUint16x16 x y mask)
 +      // result: (VPSLLWMasked256 x y (VPMOVVec16x16ToM <types.TypeMask> mask))
 +      for {
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VPSLLWMasked256)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x16ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg3(x, y, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpShiftAllLeftMaskedUint16x32(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (ShiftAllLeftMaskedUint16x32 x y mask)
 +      // result: (VPSLLWMasked512 x y (VPMOVVec16x32ToM <types.TypeMask> mask))
 +      for {
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VPSLLWMasked512)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x32ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg3(x, y, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpShiftAllLeftMaskedUint16x8(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (ShiftAllLeftMaskedUint16x8 x y mask)
 +      // result: (VPSLLWMasked128 x y (VPMOVVec16x8ToM <types.TypeMask> mask))
 +      for {
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VPSLLWMasked128)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x8ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg3(x, y, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpShiftAllLeftMaskedUint32x16(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (ShiftAllLeftMaskedUint32x16 x y mask)
 +      // result: (VPSLLDMasked512 x y (VPMOVVec32x16ToM <types.TypeMask> mask))
 +      for {
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VPSLLDMasked512)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x16ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg3(x, y, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpShiftAllLeftMaskedUint32x4(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (ShiftAllLeftMaskedUint32x4 x y mask)
 +      // result: (VPSLLDMasked128 x y (VPMOVVec32x4ToM <types.TypeMask> mask))
 +      for {
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VPSLLDMasked128)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x4ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg3(x, y, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpShiftAllLeftMaskedUint32x8(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (ShiftAllLeftMaskedUint32x8 x y mask)
 +      // result: (VPSLLDMasked256 x y (VPMOVVec32x8ToM <types.TypeMask> mask))
 +      for {
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VPSLLDMasked256)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x8ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg3(x, y, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpShiftAllLeftMaskedUint64x2(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (ShiftAllLeftMaskedUint64x2 x y mask)
 +      // result: (VPSLLQMasked128 x y (VPMOVVec64x2ToM <types.TypeMask> mask))
 +      for {
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VPSLLQMasked128)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x2ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg3(x, y, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpShiftAllLeftMaskedUint64x4(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (ShiftAllLeftMaskedUint64x4 x y mask)
 +      // result: (VPSLLQMasked256 x y (VPMOVVec64x4ToM <types.TypeMask> mask))
 +      for {
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VPSLLQMasked256)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x4ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg3(x, y, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpShiftAllLeftMaskedUint64x8(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (ShiftAllLeftMaskedUint64x8 x y mask)
 +      // result: (VPSLLQMasked512 x y (VPMOVVec64x8ToM <types.TypeMask> mask))
 +      for {
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VPSLLQMasked512)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x8ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg3(x, y, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpShiftAllRightConcatMaskedInt16x16(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (ShiftAllRightConcatMaskedInt16x16 [a] x y mask)
 +      // result: (VPSHRDWMasked256 [a] x y (VPMOVVec16x16ToM <types.TypeMask> mask))
 +      for {
 +              a := auxIntToUint8(v.AuxInt)
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VPSHRDWMasked256)
 +              v.AuxInt = uint8ToAuxInt(a)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x16ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg3(x, y, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpShiftAllRightConcatMaskedInt16x32(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (ShiftAllRightConcatMaskedInt16x32 [a] x y mask)
 +      // result: (VPSHRDWMasked512 [a] x y (VPMOVVec16x32ToM <types.TypeMask> mask))
 +      for {
 +              a := auxIntToUint8(v.AuxInt)
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VPSHRDWMasked512)
 +              v.AuxInt = uint8ToAuxInt(a)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x32ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg3(x, y, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpShiftAllRightConcatMaskedInt16x8(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (ShiftAllRightConcatMaskedInt16x8 [a] x y mask)
 +      // result: (VPSHRDWMasked128 [a] x y (VPMOVVec16x8ToM <types.TypeMask> mask))
 +      for {
 +              a := auxIntToUint8(v.AuxInt)
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VPSHRDWMasked128)
 +              v.AuxInt = uint8ToAuxInt(a)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x8ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg3(x, y, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpShiftAllRightConcatMaskedInt32x16(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (ShiftAllRightConcatMaskedInt32x16 [a] x y mask)
 +      // result: (VPSHRDDMasked512 [a] x y (VPMOVVec32x16ToM <types.TypeMask> mask))
 +      for {
 +              a := auxIntToUint8(v.AuxInt)
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VPSHRDDMasked512)
 +              v.AuxInt = uint8ToAuxInt(a)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x16ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg3(x, y, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpShiftAllRightConcatMaskedInt32x4(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (ShiftAllRightConcatMaskedInt32x4 [a] x y mask)
 +      // result: (VPSHRDDMasked128 [a] x y (VPMOVVec32x4ToM <types.TypeMask> mask))
 +      for {
 +              a := auxIntToUint8(v.AuxInt)
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VPSHRDDMasked128)
 +              v.AuxInt = uint8ToAuxInt(a)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x4ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg3(x, y, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpShiftAllRightConcatMaskedInt32x8(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (ShiftAllRightConcatMaskedInt32x8 [a] x y mask)
 +      // result: (VPSHRDDMasked256 [a] x y (VPMOVVec32x8ToM <types.TypeMask> mask))
 +      for {
 +              a := auxIntToUint8(v.AuxInt)
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VPSHRDDMasked256)
 +              v.AuxInt = uint8ToAuxInt(a)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x8ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg3(x, y, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpShiftAllRightConcatMaskedInt64x2(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (ShiftAllRightConcatMaskedInt64x2 [a] x y mask)
 +      // result: (VPSHRDQMasked128 [a] x y (VPMOVVec64x2ToM <types.TypeMask> mask))
 +      for {
 +              a := auxIntToUint8(v.AuxInt)
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VPSHRDQMasked128)
 +              v.AuxInt = uint8ToAuxInt(a)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x2ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg3(x, y, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpShiftAllRightConcatMaskedInt64x4(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (ShiftAllRightConcatMaskedInt64x4 [a] x y mask)
 +      // result: (VPSHRDQMasked256 [a] x y (VPMOVVec64x4ToM <types.TypeMask> mask))
 +      for {
 +              a := auxIntToUint8(v.AuxInt)
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VPSHRDQMasked256)
 +              v.AuxInt = uint8ToAuxInt(a)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x4ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg3(x, y, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpShiftAllRightConcatMaskedInt64x8(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (ShiftAllRightConcatMaskedInt64x8 [a] x y mask)
 +      // result: (VPSHRDQMasked512 [a] x y (VPMOVVec64x8ToM <types.TypeMask> mask))
 +      for {
 +              a := auxIntToUint8(v.AuxInt)
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VPSHRDQMasked512)
 +              v.AuxInt = uint8ToAuxInt(a)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x8ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg3(x, y, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpShiftAllRightConcatMaskedUint16x16(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (ShiftAllRightConcatMaskedUint16x16 [a] x y mask)
 +      // result: (VPSHRDWMasked256 [a] x y (VPMOVVec16x16ToM <types.TypeMask> mask))
 +      for {
 +              a := auxIntToUint8(v.AuxInt)
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VPSHRDWMasked256)
 +              v.AuxInt = uint8ToAuxInt(a)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x16ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg3(x, y, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpShiftAllRightConcatMaskedUint16x32(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (ShiftAllRightConcatMaskedUint16x32 [a] x y mask)
 +      // result: (VPSHRDWMasked512 [a] x y (VPMOVVec16x32ToM <types.TypeMask> mask))
 +      for {
 +              a := auxIntToUint8(v.AuxInt)
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VPSHRDWMasked512)
 +              v.AuxInt = uint8ToAuxInt(a)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x32ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg3(x, y, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpShiftAllRightConcatMaskedUint16x8(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (ShiftAllRightConcatMaskedUint16x8 [a] x y mask)
 +      // result: (VPSHRDWMasked128 [a] x y (VPMOVVec16x8ToM <types.TypeMask> mask))
 +      for {
 +              a := auxIntToUint8(v.AuxInt)
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VPSHRDWMasked128)
 +              v.AuxInt = uint8ToAuxInt(a)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x8ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg3(x, y, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpShiftAllRightConcatMaskedUint32x16(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (ShiftAllRightConcatMaskedUint32x16 [a] x y mask)
 +      // result: (VPSHRDDMasked512 [a] x y (VPMOVVec32x16ToM <types.TypeMask> mask))
 +      for {
 +              a := auxIntToUint8(v.AuxInt)
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VPSHRDDMasked512)
 +              v.AuxInt = uint8ToAuxInt(a)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x16ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg3(x, y, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpShiftAllRightConcatMaskedUint32x4(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (ShiftAllRightConcatMaskedUint32x4 [a] x y mask)
 +      // result: (VPSHRDDMasked128 [a] x y (VPMOVVec32x4ToM <types.TypeMask> mask))
 +      for {
 +              a := auxIntToUint8(v.AuxInt)
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VPSHRDDMasked128)
 +              v.AuxInt = uint8ToAuxInt(a)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x4ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg3(x, y, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpShiftAllRightConcatMaskedUint32x8(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (ShiftAllRightConcatMaskedUint32x8 [a] x y mask)
 +      // result: (VPSHRDDMasked256 [a] x y (VPMOVVec32x8ToM <types.TypeMask> mask))
 +      for {
 +              a := auxIntToUint8(v.AuxInt)
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VPSHRDDMasked256)
 +              v.AuxInt = uint8ToAuxInt(a)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x8ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg3(x, y, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpShiftAllRightConcatMaskedUint64x2(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (ShiftAllRightConcatMaskedUint64x2 [a] x y mask)
 +      // result: (VPSHRDQMasked128 [a] x y (VPMOVVec64x2ToM <types.TypeMask> mask))
 +      for {
 +              a := auxIntToUint8(v.AuxInt)
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VPSHRDQMasked128)
 +              v.AuxInt = uint8ToAuxInt(a)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x2ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg3(x, y, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpShiftAllRightConcatMaskedUint64x4(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (ShiftAllRightConcatMaskedUint64x4 [a] x y mask)
 +      // result: (VPSHRDQMasked256 [a] x y (VPMOVVec64x4ToM <types.TypeMask> mask))
 +      for {
 +              a := auxIntToUint8(v.AuxInt)
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VPSHRDQMasked256)
 +              v.AuxInt = uint8ToAuxInt(a)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x4ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg3(x, y, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpShiftAllRightConcatMaskedUint64x8(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (ShiftAllRightConcatMaskedUint64x8 [a] x y mask)
 +      // result: (VPSHRDQMasked512 [a] x y (VPMOVVec64x8ToM <types.TypeMask> mask))
 +      for {
 +              a := auxIntToUint8(v.AuxInt)
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VPSHRDQMasked512)
 +              v.AuxInt = uint8ToAuxInt(a)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x8ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg3(x, y, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpShiftAllRightMaskedInt16x16(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (ShiftAllRightMaskedInt16x16 x y mask)
 +      // result: (VPSRAWMasked256 x y (VPMOVVec16x16ToM <types.TypeMask> mask))
 +      for {
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VPSRAWMasked256)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x16ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg3(x, y, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpShiftAllRightMaskedInt16x32(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (ShiftAllRightMaskedInt16x32 x y mask)
 +      // result: (VPSRAWMasked512 x y (VPMOVVec16x32ToM <types.TypeMask> mask))
 +      for {
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VPSRAWMasked512)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x32ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg3(x, y, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpShiftAllRightMaskedInt16x8(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (ShiftAllRightMaskedInt16x8 x y mask)
 +      // result: (VPSRAWMasked128 x y (VPMOVVec16x8ToM <types.TypeMask> mask))
 +      for {
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VPSRAWMasked128)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x8ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg3(x, y, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpShiftAllRightMaskedInt32x16(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (ShiftAllRightMaskedInt32x16 x y mask)
 +      // result: (VPSRADMasked512 x y (VPMOVVec32x16ToM <types.TypeMask> mask))
 +      for {
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VPSRADMasked512)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x16ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg3(x, y, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpShiftAllRightMaskedInt32x4(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (ShiftAllRightMaskedInt32x4 x y mask)
 +      // result: (VPSRADMasked128 x y (VPMOVVec32x4ToM <types.TypeMask> mask))
 +      for {
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VPSRADMasked128)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x4ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg3(x, y, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpShiftAllRightMaskedInt32x8(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (ShiftAllRightMaskedInt32x8 x y mask)
 +      // result: (VPSRADMasked256 x y (VPMOVVec32x8ToM <types.TypeMask> mask))
 +      for {
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VPSRADMasked256)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x8ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg3(x, y, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpShiftAllRightMaskedInt64x2(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (ShiftAllRightMaskedInt64x2 x y mask)
 +      // result: (VPSRAQMasked128 x y (VPMOVVec64x2ToM <types.TypeMask> mask))
 +      for {
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VPSRAQMasked128)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x2ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg3(x, y, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpShiftAllRightMaskedInt64x4(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (ShiftAllRightMaskedInt64x4 x y mask)
 +      // result: (VPSRAQMasked256 x y (VPMOVVec64x4ToM <types.TypeMask> mask))
 +      for {
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VPSRAQMasked256)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x4ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg3(x, y, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpShiftAllRightMaskedInt64x8(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (ShiftAllRightMaskedInt64x8 x y mask)
 +      // result: (VPSRAQMasked512 x y (VPMOVVec64x8ToM <types.TypeMask> mask))
 +      for {
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VPSRAQMasked512)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x8ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg3(x, y, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpShiftAllRightMaskedUint16x16(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (ShiftAllRightMaskedUint16x16 x y mask)
 +      // result: (VPSRLWMasked256 x y (VPMOVVec16x16ToM <types.TypeMask> mask))
 +      for {
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VPSRLWMasked256)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x16ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg3(x, y, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpShiftAllRightMaskedUint16x32(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (ShiftAllRightMaskedUint16x32 x y mask)
 +      // result: (VPSRLWMasked512 x y (VPMOVVec16x32ToM <types.TypeMask> mask))
 +      for {
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VPSRLWMasked512)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x32ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg3(x, y, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpShiftAllRightMaskedUint16x8(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (ShiftAllRightMaskedUint16x8 x y mask)
 +      // result: (VPSRLWMasked128 x y (VPMOVVec16x8ToM <types.TypeMask> mask))
 +      for {
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VPSRLWMasked128)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x8ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg3(x, y, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpShiftAllRightMaskedUint32x16(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (ShiftAllRightMaskedUint32x16 x y mask)
 +      // result: (VPSRLDMasked512 x y (VPMOVVec32x16ToM <types.TypeMask> mask))
 +      for {
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VPSRLDMasked512)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x16ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg3(x, y, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpShiftAllRightMaskedUint32x4(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (ShiftAllRightMaskedUint32x4 x y mask)
 +      // result: (VPSRLDMasked128 x y (VPMOVVec32x4ToM <types.TypeMask> mask))
 +      for {
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VPSRLDMasked128)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x4ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg3(x, y, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpShiftAllRightMaskedUint32x8(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (ShiftAllRightMaskedUint32x8 x y mask)
 +      // result: (VPSRLDMasked256 x y (VPMOVVec32x8ToM <types.TypeMask> mask))
 +      for {
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VPSRLDMasked256)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x8ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg3(x, y, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpShiftAllRightMaskedUint64x2(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (ShiftAllRightMaskedUint64x2 x y mask)
 +      // result: (VPSRLQMasked128 x y (VPMOVVec64x2ToM <types.TypeMask> mask))
 +      for {
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VPSRLQMasked128)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x2ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg3(x, y, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpShiftAllRightMaskedUint64x4(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (ShiftAllRightMaskedUint64x4 x y mask)
 +      // result: (VPSRLQMasked256 x y (VPMOVVec64x4ToM <types.TypeMask> mask))
 +      for {
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VPSRLQMasked256)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x4ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg3(x, y, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpShiftAllRightMaskedUint64x8(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (ShiftAllRightMaskedUint64x8 x y mask)
 +      // result: (VPSRLQMasked512 x y (VPMOVVec64x8ToM <types.TypeMask> mask))
 +      for {
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VPSRLQMasked512)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x8ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg3(x, y, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpShiftLeftConcatMaskedInt16x16(v *Value) bool {
 +      v_3 := v.Args[3]
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (ShiftLeftConcatMaskedInt16x16 x y z mask)
 +      // result: (VPSHLDVWMasked256 x y z (VPMOVVec16x16ToM <types.TypeMask> mask))
 +      for {
 +              x := v_0
 +              y := v_1
 +              z := v_2
 +              mask := v_3
 +              v.reset(OpAMD64VPSHLDVWMasked256)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x16ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg4(x, y, z, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpShiftLeftConcatMaskedInt16x32(v *Value) bool {
 +      v_3 := v.Args[3]
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (ShiftLeftConcatMaskedInt16x32 x y z mask)
 +      // result: (VPSHLDVWMasked512 x y z (VPMOVVec16x32ToM <types.TypeMask> mask))
 +      for {
 +              x := v_0
 +              y := v_1
 +              z := v_2
 +              mask := v_3
 +              v.reset(OpAMD64VPSHLDVWMasked512)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x32ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg4(x, y, z, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpShiftLeftConcatMaskedInt16x8(v *Value) bool {
 +      v_3 := v.Args[3]
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (ShiftLeftConcatMaskedInt16x8 x y z mask)
 +      // result: (VPSHLDVWMasked128 x y z (VPMOVVec16x8ToM <types.TypeMask> mask))
 +      for {
 +              x := v_0
 +              y := v_1
 +              z := v_2
 +              mask := v_3
 +              v.reset(OpAMD64VPSHLDVWMasked128)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x8ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg4(x, y, z, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpShiftLeftConcatMaskedInt32x16(v *Value) bool {
 +      v_3 := v.Args[3]
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (ShiftLeftConcatMaskedInt32x16 x y z mask)
 +      // result: (VPSHLDVDMasked512 x y z (VPMOVVec32x16ToM <types.TypeMask> mask))
 +      for {
 +              x := v_0
 +              y := v_1
 +              z := v_2
 +              mask := v_3
 +              v.reset(OpAMD64VPSHLDVDMasked512)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x16ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg4(x, y, z, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpShiftLeftConcatMaskedInt32x4(v *Value) bool {
 +      v_3 := v.Args[3]
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (ShiftLeftConcatMaskedInt32x4 x y z mask)
 +      // result: (VPSHLDVDMasked128 x y z (VPMOVVec32x4ToM <types.TypeMask> mask))
 +      for {
 +              x := v_0
 +              y := v_1
 +              z := v_2
 +              mask := v_3
 +              v.reset(OpAMD64VPSHLDVDMasked128)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x4ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg4(x, y, z, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpShiftLeftConcatMaskedInt32x8(v *Value) bool {
 +      v_3 := v.Args[3]
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (ShiftLeftConcatMaskedInt32x8 x y z mask)
 +      // result: (VPSHLDVDMasked256 x y z (VPMOVVec32x8ToM <types.TypeMask> mask))
 +      for {
 +              x := v_0
 +              y := v_1
 +              z := v_2
 +              mask := v_3
 +              v.reset(OpAMD64VPSHLDVDMasked256)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x8ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg4(x, y, z, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpShiftLeftConcatMaskedInt64x2(v *Value) bool {
 +      v_3 := v.Args[3]
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (ShiftLeftConcatMaskedInt64x2 x y z mask)
 +      // result: (VPSHLDVQMasked128 x y z (VPMOVVec64x2ToM <types.TypeMask> mask))
 +      for {
 +              x := v_0
 +              y := v_1
 +              z := v_2
 +              mask := v_3
 +              v.reset(OpAMD64VPSHLDVQMasked128)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x2ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg4(x, y, z, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpShiftLeftConcatMaskedInt64x4(v *Value) bool {
 +      v_3 := v.Args[3]
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (ShiftLeftConcatMaskedInt64x4 x y z mask)
 +      // result: (VPSHLDVQMasked256 x y z (VPMOVVec64x4ToM <types.TypeMask> mask))
 +      for {
 +              x := v_0
 +              y := v_1
 +              z := v_2
 +              mask := v_3
 +              v.reset(OpAMD64VPSHLDVQMasked256)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x4ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg4(x, y, z, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpShiftLeftConcatMaskedInt64x8(v *Value) bool {
 +      v_3 := v.Args[3]
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (ShiftLeftConcatMaskedInt64x8 x y z mask)
 +      // result: (VPSHLDVQMasked512 x y z (VPMOVVec64x8ToM <types.TypeMask> mask))
 +      for {
 +              x := v_0
 +              y := v_1
 +              z := v_2
 +              mask := v_3
 +              v.reset(OpAMD64VPSHLDVQMasked512)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x8ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg4(x, y, z, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpShiftLeftConcatMaskedUint16x16(v *Value) bool {
 +      v_3 := v.Args[3]
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (ShiftLeftConcatMaskedUint16x16 x y z mask)
 +      // result: (VPSHLDVWMasked256 x y z (VPMOVVec16x16ToM <types.TypeMask> mask))
 +      for {
 +              x := v_0
 +              y := v_1
 +              z := v_2
 +              mask := v_3
 +              v.reset(OpAMD64VPSHLDVWMasked256)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x16ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg4(x, y, z, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpShiftLeftConcatMaskedUint16x32(v *Value) bool {
 +      v_3 := v.Args[3]
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (ShiftLeftConcatMaskedUint16x32 x y z mask)
 +      // result: (VPSHLDVWMasked512 x y z (VPMOVVec16x32ToM <types.TypeMask> mask))
 +      for {
 +              x := v_0
 +              y := v_1
 +              z := v_2
 +              mask := v_3
 +              v.reset(OpAMD64VPSHLDVWMasked512)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x32ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg4(x, y, z, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpShiftLeftConcatMaskedUint16x8(v *Value) bool {
 +      v_3 := v.Args[3]
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (ShiftLeftConcatMaskedUint16x8 x y z mask)
 +      // result: (VPSHLDVWMasked128 x y z (VPMOVVec16x8ToM <types.TypeMask> mask))
 +      for {
 +              x := v_0
 +              y := v_1
 +              z := v_2
 +              mask := v_3
 +              v.reset(OpAMD64VPSHLDVWMasked128)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x8ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg4(x, y, z, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpShiftLeftConcatMaskedUint32x16(v *Value) bool {
 +      v_3 := v.Args[3]
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (ShiftLeftConcatMaskedUint32x16 x y z mask)
 +      // result: (VPSHLDVDMasked512 x y z (VPMOVVec32x16ToM <types.TypeMask> mask))
 +      for {
 +              x := v_0
 +              y := v_1
 +              z := v_2
 +              mask := v_3
 +              v.reset(OpAMD64VPSHLDVDMasked512)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x16ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg4(x, y, z, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpShiftLeftConcatMaskedUint32x4(v *Value) bool {
 +      v_3 := v.Args[3]
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (ShiftLeftConcatMaskedUint32x4 x y z mask)
 +      // result: (VPSHLDVDMasked128 x y z (VPMOVVec32x4ToM <types.TypeMask> mask))
 +      for {
 +              x := v_0
 +              y := v_1
 +              z := v_2
 +              mask := v_3
 +              v.reset(OpAMD64VPSHLDVDMasked128)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x4ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg4(x, y, z, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpShiftLeftConcatMaskedUint32x8(v *Value) bool {
 +      v_3 := v.Args[3]
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (ShiftLeftConcatMaskedUint32x8 x y z mask)
 +      // result: (VPSHLDVDMasked256 x y z (VPMOVVec32x8ToM <types.TypeMask> mask))
 +      for {
 +              x := v_0
 +              y := v_1
 +              z := v_2
 +              mask := v_3
 +              v.reset(OpAMD64VPSHLDVDMasked256)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x8ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg4(x, y, z, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpShiftLeftConcatMaskedUint64x2(v *Value) bool {
 +      v_3 := v.Args[3]
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (ShiftLeftConcatMaskedUint64x2 x y z mask)
 +      // result: (VPSHLDVQMasked128 x y z (VPMOVVec64x2ToM <types.TypeMask> mask))
 +      for {
 +              x := v_0
 +              y := v_1
 +              z := v_2
 +              mask := v_3
 +              v.reset(OpAMD64VPSHLDVQMasked128)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x2ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg4(x, y, z, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpShiftLeftConcatMaskedUint64x4(v *Value) bool {
 +      v_3 := v.Args[3]
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (ShiftLeftConcatMaskedUint64x4 x y z mask)
 +      // result: (VPSHLDVQMasked256 x y z (VPMOVVec64x4ToM <types.TypeMask> mask))
 +      for {
 +              x := v_0
 +              y := v_1
 +              z := v_2
 +              mask := v_3
 +              v.reset(OpAMD64VPSHLDVQMasked256)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x4ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg4(x, y, z, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpShiftLeftConcatMaskedUint64x8(v *Value) bool {
 +      v_3 := v.Args[3]
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (ShiftLeftConcatMaskedUint64x8 x y z mask)
 +      // result: (VPSHLDVQMasked512 x y z (VPMOVVec64x8ToM <types.TypeMask> mask))
 +      for {
 +              x := v_0
 +              y := v_1
 +              z := v_2
 +              mask := v_3
 +              v.reset(OpAMD64VPSHLDVQMasked512)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x8ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg4(x, y, z, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpShiftLeftMaskedInt16x16(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (ShiftLeftMaskedInt16x16 x y mask)
 +      // result: (VPSLLVWMasked256 x y (VPMOVVec16x16ToM <types.TypeMask> mask))
 +      for {
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VPSLLVWMasked256)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x16ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg3(x, y, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpShiftLeftMaskedInt16x32(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (ShiftLeftMaskedInt16x32 x y mask)
 +      // result: (VPSLLVWMasked512 x y (VPMOVVec16x32ToM <types.TypeMask> mask))
 +      for {
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VPSLLVWMasked512)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x32ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg3(x, y, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpShiftLeftMaskedInt16x8(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (ShiftLeftMaskedInt16x8 x y mask)
 +      // result: (VPSLLVWMasked128 x y (VPMOVVec16x8ToM <types.TypeMask> mask))
 +      for {
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VPSLLVWMasked128)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x8ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg3(x, y, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpShiftLeftMaskedInt32x16(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (ShiftLeftMaskedInt32x16 x y mask)
 +      // result: (VPSLLVDMasked512 x y (VPMOVVec32x16ToM <types.TypeMask> mask))
 +      for {
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VPSLLVDMasked512)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x16ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg3(x, y, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpShiftLeftMaskedInt32x4(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (ShiftLeftMaskedInt32x4 x y mask)
 +      // result: (VPSLLVDMasked128 x y (VPMOVVec32x4ToM <types.TypeMask> mask))
 +      for {
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VPSLLVDMasked128)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x4ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg3(x, y, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpShiftLeftMaskedInt32x8(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (ShiftLeftMaskedInt32x8 x y mask)
 +      // result: (VPSLLVDMasked256 x y (VPMOVVec32x8ToM <types.TypeMask> mask))
 +      for {
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VPSLLVDMasked256)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x8ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg3(x, y, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpShiftLeftMaskedInt64x2(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (ShiftLeftMaskedInt64x2 x y mask)
 +      // result: (VPSLLVQMasked128 x y (VPMOVVec64x2ToM <types.TypeMask> mask))
 +      for {
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VPSLLVQMasked128)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x2ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg3(x, y, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpShiftLeftMaskedInt64x4(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (ShiftLeftMaskedInt64x4 x y mask)
 +      // result: (VPSLLVQMasked256 x y (VPMOVVec64x4ToM <types.TypeMask> mask))
 +      for {
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VPSLLVQMasked256)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x4ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg3(x, y, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpShiftLeftMaskedInt64x8(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (ShiftLeftMaskedInt64x8 x y mask)
 +      // result: (VPSLLVQMasked512 x y (VPMOVVec64x8ToM <types.TypeMask> mask))
 +      for {
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VPSLLVQMasked512)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x8ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg3(x, y, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpShiftLeftMaskedUint16x16(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (ShiftLeftMaskedUint16x16 x y mask)
 +      // result: (VPSLLVWMasked256 x y (VPMOVVec16x16ToM <types.TypeMask> mask))
 +      for {
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VPSLLVWMasked256)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x16ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg3(x, y, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpShiftLeftMaskedUint16x32(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (ShiftLeftMaskedUint16x32 x y mask)
 +      // result: (VPSLLVWMasked512 x y (VPMOVVec16x32ToM <types.TypeMask> mask))
 +      for {
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VPSLLVWMasked512)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x32ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg3(x, y, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpShiftLeftMaskedUint16x8(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (ShiftLeftMaskedUint16x8 x y mask)
 +      // result: (VPSLLVWMasked128 x y (VPMOVVec16x8ToM <types.TypeMask> mask))
 +      for {
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VPSLLVWMasked128)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x8ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg3(x, y, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpShiftLeftMaskedUint32x16(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (ShiftLeftMaskedUint32x16 x y mask)
 +      // result: (VPSLLVDMasked512 x y (VPMOVVec32x16ToM <types.TypeMask> mask))
 +      for {
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VPSLLVDMasked512)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x16ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg3(x, y, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpShiftLeftMaskedUint32x4(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (ShiftLeftMaskedUint32x4 x y mask)
 +      // result: (VPSLLVDMasked128 x y (VPMOVVec32x4ToM <types.TypeMask> mask))
 +      for {
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VPSLLVDMasked128)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x4ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg3(x, y, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpShiftLeftMaskedUint32x8(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (ShiftLeftMaskedUint32x8 x y mask)
 +      // result: (VPSLLVDMasked256 x y (VPMOVVec32x8ToM <types.TypeMask> mask))
 +      for {
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VPSLLVDMasked256)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x8ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg3(x, y, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpShiftLeftMaskedUint64x2(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (ShiftLeftMaskedUint64x2 x y mask)
 +      // result: (VPSLLVQMasked128 x y (VPMOVVec64x2ToM <types.TypeMask> mask))
 +      for {
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VPSLLVQMasked128)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x2ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg3(x, y, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpShiftLeftMaskedUint64x4(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (ShiftLeftMaskedUint64x4 x y mask)
 +      // result: (VPSLLVQMasked256 x y (VPMOVVec64x4ToM <types.TypeMask> mask))
 +      for {
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VPSLLVQMasked256)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x4ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg3(x, y, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpShiftLeftMaskedUint64x8(v *Value) bool {
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (ShiftLeftMaskedUint64x8 x y mask)
 +      // result: (VPSLLVQMasked512 x y (VPMOVVec64x8ToM <types.TypeMask> mask))
 +      for {
 +              x := v_0
 +              y := v_1
 +              mask := v_2
 +              v.reset(OpAMD64VPSLLVQMasked512)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x8ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg3(x, y, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpShiftRightConcatMaskedInt16x16(v *Value) bool {
 +      v_3 := v.Args[3]
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (ShiftRightConcatMaskedInt16x16 x y z mask)
 +      // result: (VPSHRDVWMasked256 x y z (VPMOVVec16x16ToM <types.TypeMask> mask))
 +      for {
 +              x := v_0
 +              y := v_1
 +              z := v_2
 +              mask := v_3
 +              v.reset(OpAMD64VPSHRDVWMasked256)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x16ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg4(x, y, z, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpShiftRightConcatMaskedInt16x32(v *Value) bool {
 +      v_3 := v.Args[3]
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (ShiftRightConcatMaskedInt16x32 x y z mask)
 +      // result: (VPSHRDVWMasked512 x y z (VPMOVVec16x32ToM <types.TypeMask> mask))
 +      for {
 +              x := v_0
 +              y := v_1
 +              z := v_2
 +              mask := v_3
 +              v.reset(OpAMD64VPSHRDVWMasked512)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x32ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg4(x, y, z, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpShiftRightConcatMaskedInt16x8(v *Value) bool {
 +      v_3 := v.Args[3]
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (ShiftRightConcatMaskedInt16x8 x y z mask)
 +      // result: (VPSHRDVWMasked128 x y z (VPMOVVec16x8ToM <types.TypeMask> mask))
 +      for {
 +              x := v_0
 +              y := v_1
 +              z := v_2
 +              mask := v_3
 +              v.reset(OpAMD64VPSHRDVWMasked128)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x8ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg4(x, y, z, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpShiftRightConcatMaskedInt32x16(v *Value) bool {
 +      v_3 := v.Args[3]
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (ShiftRightConcatMaskedInt32x16 x y z mask)
 +      // result: (VPSHRDVDMasked512 x y z (VPMOVVec32x16ToM <types.TypeMask> mask))
 +      for {
 +              x := v_0
 +              y := v_1
 +              z := v_2
 +              mask := v_3
 +              v.reset(OpAMD64VPSHRDVDMasked512)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x16ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg4(x, y, z, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpShiftRightConcatMaskedInt32x4(v *Value) bool {
 +      v_3 := v.Args[3]
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (ShiftRightConcatMaskedInt32x4 x y z mask)
 +      // result: (VPSHRDVDMasked128 x y z (VPMOVVec32x4ToM <types.TypeMask> mask))
 +      for {
 +              x := v_0
 +              y := v_1
 +              z := v_2
 +              mask := v_3
 +              v.reset(OpAMD64VPSHRDVDMasked128)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x4ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg4(x, y, z, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpShiftRightConcatMaskedInt32x8(v *Value) bool {
 +      v_3 := v.Args[3]
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (ShiftRightConcatMaskedInt32x8 x y z mask)
 +      // result: (VPSHRDVDMasked256 x y z (VPMOVVec32x8ToM <types.TypeMask> mask))
 +      for {
 +              x := v_0
 +              y := v_1
 +              z := v_2
 +              mask := v_3
 +              v.reset(OpAMD64VPSHRDVDMasked256)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x8ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg4(x, y, z, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpShiftRightConcatMaskedInt64x2(v *Value) bool {
 +      v_3 := v.Args[3]
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (ShiftRightConcatMaskedInt64x2 x y z mask)
 +      // result: (VPSHRDVQMasked128 x y z (VPMOVVec64x2ToM <types.TypeMask> mask))
 +      for {
 +              x := v_0
 +              y := v_1
 +              z := v_2
 +              mask := v_3
 +              v.reset(OpAMD64VPSHRDVQMasked128)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x2ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg4(x, y, z, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpShiftRightConcatMaskedInt64x4(v *Value) bool {
 +      v_3 := v.Args[3]
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (ShiftRightConcatMaskedInt64x4 x y z mask)
 +      // result: (VPSHRDVQMasked256 x y z (VPMOVVec64x4ToM <types.TypeMask> mask))
 +      for {
 +              x := v_0
 +              y := v_1
 +              z := v_2
 +              mask := v_3
 +              v.reset(OpAMD64VPSHRDVQMasked256)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x4ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg4(x, y, z, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpShiftRightConcatMaskedInt64x8(v *Value) bool {
 +      v_3 := v.Args[3]
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (ShiftRightConcatMaskedInt64x8 x y z mask)
 +      // result: (VPSHRDVQMasked512 x y z (VPMOVVec64x8ToM <types.TypeMask> mask))
 +      for {
 +              x := v_0
 +              y := v_1
 +              z := v_2
 +              mask := v_3
 +              v.reset(OpAMD64VPSHRDVQMasked512)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x8ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg4(x, y, z, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpShiftRightConcatMaskedUint16x16(v *Value) bool {
 +      v_3 := v.Args[3]
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (ShiftRightConcatMaskedUint16x16 x y z mask)
 +      // result: (VPSHRDVWMasked256 x y z (VPMOVVec16x16ToM <types.TypeMask> mask))
 +      for {
 +              x := v_0
 +              y := v_1
 +              z := v_2
 +              mask := v_3
 +              v.reset(OpAMD64VPSHRDVWMasked256)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x16ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg4(x, y, z, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpShiftRightConcatMaskedUint16x32(v *Value) bool {
 +      v_3 := v.Args[3]
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (ShiftRightConcatMaskedUint16x32 x y z mask)
 +      // result: (VPSHRDVWMasked512 x y z (VPMOVVec16x32ToM <types.TypeMask> mask))
 +      for {
 +              x := v_0
 +              y := v_1
 +              z := v_2
 +              mask := v_3
 +              v.reset(OpAMD64VPSHRDVWMasked512)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x32ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg4(x, y, z, v0)
 +              return true
 +      }
 +}
 +func rewriteValueAMD64_OpShiftRightConcatMaskedUint16x8(v *Value) bool {
 +      v_3 := v.Args[3]
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (ShiftRightConcatMaskedUint16x8 x y z mask)
 +      // result: (VPSHRDVWMasked128 x y z (VPMOVVec16x8ToM <types.TypeMask> mask))
 +      for {
 +              x := v_0
 +              y := v_1
 +              z := v_2
 +              mask := v_3
 +              v.reset(OpAMD64VPSHRDVWMasked128)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x8ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg4(x, y, z, v0)
                return true
        }
 -      // match: (Move [s] dst src mem)
 -      // cond: s > repMoveThreshold && s%8 == 0 && logLargeCopy(v, s)
 -      // result: (REPMOVSQ dst src (MOVQconst [s/8]) mem)
 +}
 +func rewriteValueAMD64_OpShiftRightConcatMaskedUint32x16(v *Value) bool {
 +      v_3 := v.Args[3]
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
 +      v_0 := v.Args[0]
 +      b := v.Block
 +      // match: (ShiftRightConcatMaskedUint32x16 x y z mask)
 +      // result: (VPSHRDVDMasked512 x y z (VPMOVVec32x16ToM <types.TypeMask> mask))
        for {
 -              s := auxIntToInt64(v.AuxInt)
 -              dst := v_0
 -              src := v_1
 -              mem := v_2
 -              if !(s > repMoveThreshold && s%8 == 0 && logLargeCopy(v, s)) {
 -                      break
 -              }
 -              v.reset(OpAMD64REPMOVSQ)
 -              v0 := b.NewValue0(v.Pos, OpAMD64MOVQconst, typ.UInt64)
 -              v0.AuxInt = int64ToAuxInt(s / 8)
 -              v.AddArg4(dst, src, v0, mem)
 +              x := v_0
 +              y := v_1
 +              z := v_2
 +              mask := v_3
 +              v.reset(OpAMD64VPSHRDVDMasked512)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x16ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg4(x, y, z, v0)
                return true
        }
 -      return false
  }
 -func rewriteValueAMD64_OpNeg32F(v *Value) bool {
 +func rewriteValueAMD64_OpShiftRightConcatMaskedUint32x4(v *Value) bool {
 +      v_3 := v.Args[3]
 +      v_2 := v.Args[2]
 +      v_1 := v.Args[1]
        v_0 := v.Args[0]
        b := v.Block
 -      typ := &b.Func.Config.Types
 -      // match: (Neg32F x)
 -      // result: (PXOR x (MOVSSconst <typ.Float32> [float32(math.Copysign(0, -1))]))
 +      // match: (ShiftRightConcatMaskedUint32x4 x y z mask)
 +      // result: (VPSHRDVDMasked128 x y z (VPMOVVec32x4ToM <types.TypeMask> mask))
        for {
                x := v_0
 -              v.reset(OpAMD64PXOR)
 -              v0 := b.NewValue0(v.Pos, OpAMD64MOVSSconst, typ.Float32)
 -              v0.AuxInt = float32ToAuxInt(float32(math.Copysign(0, -1)))
 -              v.AddArg2(x, v0)
 +              y := v_1
 +              z := v_2
 +              mask := v_3
 +              v.reset(OpAMD64VPSHRDVDMasked128)
 +              v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x4ToM, types.TypeMask)
 +              v0.AddArg(mask)
 +              v.AddArg4(x, y, z, v0)
                return true
        }
  }

diff --cc src/cmd/compile/internal/ssagen/ssa.go
index 221f979996374401f2beef7ec857d311c5651b61,1e2159579dfbf2e46167f731ed79d22b896aae38..abb6370a15f743f7df0c51fb0643cfb135375931
--- 1/src/cmd/compile/internal/ssagen/ssa.go
--- 2/src/cmd/compile/internal/ssagen/ssa.go
+++ b/src/cmd/compile/internal/ssagen/ssa.go
@@@ -7768,11 -7699,4 +7709,9 @@@ func SpillSlotAddr(spill ssa.Spill, bas
        }
  }
  
- var (
-       BoundsCheckFunc [ssa.BoundsKindCount]*obj.LSym
-       ExtendCheckFunc [ssa.BoundsKindCount]*obj.LSym
- )
 +func isStructNotSIMD(t *types.Type) bool {
 +      return t.IsStruct() && !t.IsSIMD()
 +}
 +
+ var BoundsCheckFunc [ssa.BoundsKindCount]*obj.LSym
++

diff --cc src/cmd/compile/internal/types/type.go
Simple merge

diff --cc src/cmd/compile/internal/types2/stdlib_test.go
Simple merge

diff --cc src/go/build/deps_test.go
Simple merge

diff --cc src/go/types/stdlib_test.go
Simple merge

diff --cc src/internal/buildcfg/exp.go
index 9199b7906f3131f185fddc47740692bd67b7ef0b,310226bc0146e58914000e3059c3bff07809bde8..41823def65e30a7601acaad571f5508e8fb27388
--- 1/src/internal/buildcfg/exp.go
--- 2/src/internal/buildcfg/exp.go
+++ b/src/internal/buildcfg/exp.go
@@@ -79,11 -79,9 +79,10 @@@ func ParseGOEXPERIMENT(goos, goarch, go
        dwarf5Supported := (goos != "darwin" && goos != "ios" && goos != "aix")
  
        baseline := goexperiment.Flags{
 -              RegabiWrappers: regabiSupported,
 -              RegabiArgs:     regabiSupported,
 -              Dwarf5:         dwarf5Supported,
 +              RegabiWrappers:  regabiSupported,
 +              RegabiArgs:      regabiSupported,
-               AliasTypeParams: true,
 +              SIMD:            goarch == "amd64", // TODO remove this (default to false) when dev.simd is merged
 +              Dwarf5:          dwarf5Supported,
        }
  
        // Start with the statically enabled set of experiments.

diff --cc src/internal/cpu/cpu.go
Simple merge

diff --cc src/internal/cpu/cpu_x86.go
index 76742706b5d0ecb2c2802487891cf463cab8ac13,6fa30b776310b3e4bc3c927be03826c1c7b727af..f07fc82df1cfcb4f8253d1afecd247a0c18bf979
--- 1/src/internal/cpu/cpu_x86.go
--- 2/src/internal/cpu/cpu_x86.go
+++ b/src/internal/cpu/cpu_x86.go
@@@ -18,28 -18,19 +18,28 @@@ func xgetbv() (eax, edx uint32
  func getGOAMD64level() int32
  
  const (
 -      // Bits returned in ECX for CPUID EAX=0x1 ECX=0x0
 -      cpuid_SSE3      = 1 << 0
 -      cpuid_PCLMULQDQ = 1 << 1
 -      cpuid_SSSE3     = 1 << 9
 -      cpuid_FMA       = 1 << 12
 -      cpuid_SSE41     = 1 << 19
 -      cpuid_SSE42     = 1 << 20
 -      cpuid_POPCNT    = 1 << 23
 -      cpuid_AES       = 1 << 25
 -      cpuid_OSXSAVE   = 1 << 27
 -      cpuid_AVX       = 1 << 28
 +      // eax bits
 +      cpuid_AVXVNNI = 1 << 4
 +
 +      // ecx bits
 +      cpuid_SSE3            = 1 << 0
 +      cpuid_PCLMULQDQ       = 1 << 1
 +      cpuid_AVX512VBMI      = 1 << 1
 +      cpuid_AVX512VBMI2     = 1 << 6
 +      cpuid_SSSE3           = 1 << 9
 +      cpuid_AVX512GFNI      = 1 << 8
 +      cpuid_AVX512VNNI      = 1 << 11
 +      cpuid_AVX512BITALG    = 1 << 12
 +      cpuid_FMA             = 1 << 12
 +      cpuid_AVX512VPOPCNTDQ = 1 << 14
 +      cpuid_SSE41           = 1 << 19
 +      cpuid_SSE42           = 1 << 20
 +      cpuid_POPCNT          = 1 << 23
 +      cpuid_AES             = 1 << 25
 +      cpuid_OSXSAVE         = 1 << 27
 +      cpuid_AVX             = 1 << 28
  
-       // ebx bits
+       // "Extended Feature Flag" bits returned in EBX for CPUID EAX=0x7 ECX=0x0
        cpuid_BMI1     = 1 << 3
        cpuid_AVX2     = 1 << 5
        cpuid_BMI2     = 1 << 8
@@@ -171,13 -166,11 +175,17 @@@ func doinit() 
                X86.HasAVX512BW = isSet(ebx7, cpuid_AVX512BW)
                X86.HasAVX512DQ = isSet(ebx7, cpuid_AVX512DQ)
                X86.HasAVX512VL = isSet(ebx7, cpuid_AVX512VL)
 +              X86.HasAVX512GFNI = isSet(ecx7, cpuid_AVX512GFNI)
 +              X86.HasAVX512BITALG = isSet(ecx7, cpuid_AVX512BITALG)
 +              X86.HasAVX512VPOPCNTDQ = isSet(ecx7, cpuid_AVX512VPOPCNTDQ)
 +              X86.HasAVX512VBMI = isSet(ecx7, cpuid_AVX512VBMI)
 +              X86.HasAVX512VBMI2 = isSet(ecx7, cpuid_AVX512VBMI2)
 +              X86.HasAVX512VNNI = isSet(ecx7, cpuid_AVX512VNNI)
                X86.HasAVX512VPCLMULQDQ = isSet(ecx7, cpuid_AVX512VPCLMULQDQ)
+               X86.HasAVX512VBMI = isSet(ecx7, cpuid_AVX512_VBMI)
+               X86.HasAVX512VBMI2 = isSet(ecx7, cpuid_AVX512_VBMI2)
+               X86.HasGFNI = isSet(ecx7, cpuid_GFNI)
+               X86.HasAVX512BITALG = isSet(ecx7, cpuid_AVX512_BITALG)
        }
  
        X86.HasFSRM = isSet(edx7, cpuid_FSRM)
@@@ -202,12 -195,6 +210,13 @@@
                // included in AVX10.1.
                X86.HasAVX512 = X86.HasAVX512F && X86.HasAVX512CD && X86.HasAVX512BW && X86.HasAVX512DQ && X86.HasAVX512VL
        }
++
 +      if eax7 >= 1 {
 +              eax71, _, _, _ := cpuid(7, 1)
 +              if X86.HasAVX {
 +                      X86.HasAVXVNNI = isSet(4, eax71)
 +              }
 +      }
  }
  
  func isSet(hwc uint32, value uint32) bool {

diff --cc src/internal/goexperiment/flags.go
Simple merge