cmd/internal/obj/loong64: add aliases to 32-bit arithmetic instructions

Both the MULW and MUL instructions point to the mul.w instruction
in the loong64 ISA. Previously, MULW was not encoded; now it is
encoded and used as an alias for MUL.
The same applies to the following instructions: ADD, SUB, DIV.
For consistency, we have added additional aliases for DIVU, REM and REMU.

Change-Id: Iba201a3c4c2893ff7d301ef877fad9c81e54291b
Reviewed-on: https://go-review.googlesource.com/c/go/+/721523
Reviewed-by: Cherry Mui <cherryyz@google.com>
Auto-Submit: abner chenc <chenguoqi@loongson.cn>
Reviewed-by: abner chenc <chenguoqi@loongson.cn>
Reviewed-by: Meidan Li <limeidan@loongson.cn>
Reviewed-by: Dmitri Shuralyov <dmitshur@google.com>
LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com>

diff --git a/src/cmd/asm/internal/asm/testdata/loong64enc1.s b/src/cmd/asm/internal/asm/testdata/loong64enc1.s
index fc6e27741690889782a4eaf985a407a19b5a055f..20fd01443406897a7ab85602767fa935764d42a6 100644 (file)
--- a/src/cmd/asm/internal/asm/testdata/loong64enc1.s
+++ b/src/cmd/asm/internal/asm/testdata/loong64enc1.s
@@ -33,13 +33,17 @@ lable2:
        MOVV    R4, R5                  // 85001500
        MOVBU   R4, R5                  // 85fc4303
        SUB     R4, R5, R6              // a6101100
+       SUBW    R4, R5, R6              // a6101100
        SUBV    R4, R5, R6              // a6901100
        ADD     R4, R5, R6              // a6101000
+       ADDW    R4, R5, R6              // a6101000
        ADDV    R4, R5, R6              // a6901000
        AND     R4, R5, R6              // a6901400
        SUB     R4, R5                  // a5101100
+       SUBW    R4, R5                  // a5101100
        SUBV    R4, R5                  // a5901100
        ADD     R4, R5                  // a5101000
+       ADDW    R4, R5                  // a5101000
        ADDV    R4, R5                  // a5901000
        AND     R4, R5                  // a5901400
        NEGW    R4, R5                  // 05101100
@@ -115,6 +119,8 @@ lable2:
        MOVV    $1, R4                  // 04048003
        ADD     $-1, R4, R5             // 85fcbf02
        ADD     $-1, R4                 // 84fcbf02
+       ADDW    $-1, R4, R5             // 85fcbf02
+       ADDW    $-1, R4                 // 84fcbf02
        ADDV    $-1, R4, R5             // 85fcff02
        ADDV    $-1, R4                 // 84fcff02
        AND     $1, R4, R5              // 85044003
@@ -165,6 +171,8 @@ lable2:
        // mul
        MUL     R4, R5                  // a5101c00
        MUL     R4, R5, R6              // a6101c00
+       MULW    R4, R5                  // a5101c00
+       MULW    R4, R5, R6              // a6101c00
        MULV    R4, R5                  // a5901d00
        MULV    R4, R5, R6              // a6901d00
        MULVU   R4, R5                  // a5901d00
@@ -199,12 +207,20 @@ lable2:
        MULHU   R4, R5, R6              // a6101d00
        REM     R4, R5                  // a5902000
        REM     R4, R5, R6              // a6902000
+       REMW    R4, R5                  // a5902000
+       REMW    R4, R5, R6              // a6902000
        REMU    R4, R5                  // a5902100
        REMU    R4, R5, R6              // a6902100
+       REMWU   R4, R5                  // a5902100
+       REMWU   R4, R5, R6              // a6902100
        DIV     R4, R5                  // a5102000
        DIV     R4, R5, R6              // a6102000
+       DIVW    R4, R5                  // a5102000
+       DIVW    R4, R5, R6              // a6102000
        DIVU    R4, R5                  // a5102100
        DIVU    R4, R5, R6              // a6102100
+       DIVWU   R4, R5                  // a5102100
+       DIVWU   R4, R5, R6              // a6102100
        SRLV    R4, R5                  // a5101900
        SRLV    R4, R5, R6              // a6101900
        SRLV    $4, R4, R5              // 85104500

diff --git a/src/cmd/asm/internal/asm/testdata/loong64enc2.s b/src/cmd/asm/internal/asm/testdata/loong64enc2.s
index 91aed4e2c7007d8c1e0204136b22469e40f2f1e1..0ac85f32252e3fa3b2db2d5d1108e029700d1336 100644 (file)
--- a/src/cmd/asm/internal/asm/testdata/loong64enc2.s
+++ b/src/cmd/asm/internal/asm/testdata/loong64enc2.s
@@ -21,6 +21,10 @@ TEXT asmtest(SB),DUPOK|NOSPLIT,$0
        ADD     $4096, R4, R5           // 3e00001485781000
        ADD     $65536, R4              // 1e02001484781000
        ADD     $4096, R4               // 3e00001484781000
+       ADDW    $65536, R4, R5          // 1e02001485781000
+       ADDW    $4096, R4, R5           // 3e00001485781000
+       ADDW    $65536, R4              // 1e02001484781000
+       ADDW    $4096, R4               // 3e00001484781000
        ADDV    $65536, R4, R5          // 1e02001485f81000
        ADDV    $4096, R4, R5           // 3e00001485f81000
        ADDV    $65536, R4              // 1e02001484f81000

diff --git a/src/cmd/asm/internal/asm/testdata/loong64enc3.s b/src/cmd/asm/internal/asm/testdata/loong64enc3.s
index 2dc6529dcb0131b8ae374f0b8368df7793f7a730..c8fb1acb396d5071cae99aaa630ff06d7bc07ccb 100644 (file)
--- a/src/cmd/asm/internal/asm/testdata/loong64enc3.s
+++ b/src/cmd/asm/internal/asm/testdata/loong64enc3.s
@@ -11,12 +11,16 @@ TEXT asmtest(SB),DUPOK|NOSPLIT,$0
        MOVV    $4096(R4), R5                   // 3e000014de03800385f81000
        ADD     $74565, R4                      // 5e020014de178d0384781000
        ADD     $4097, R4                       // 3e000014de07800384781000
+       ADDW    $74565, R4                      // 5e020014de178d0384781000
+       ADDW    $4097, R4                       // 3e000014de07800384781000
        ADDV    $74565, R4                      // 5e020014de178d0384f81000
        ADDV    $4097, R4                       // 3e000014de07800384f81000
        AND     $74565, R4                      // 5e020014de178d0384f81400
        AND     $4097, R4                       // 3e000014de07800384f81400
        ADD     $74565, R4, R5                  // 5e020014de178d0385781000
        ADD     $4097, R4, R5                   // 3e000014de07800385781000
+       ADDW    $74565, R4, R5                  // 5e020014de178d0385781000
+       ADDW    $4097, R4, R5                   // 3e000014de07800385781000
        ADDV    $74565, R4, R5                  // 5e020014de178d0385f81000
        ADDV    $4097, R4, R5                   // 3e000014de07800385f81000
        AND     $74565, R4, R5                  // 5e020014de178d0385f81400

diff --git a/src/cmd/internal/obj/loong64/a.out.go b/src/cmd/internal/obj/loong64/a.out.go
index 96f0889199dc19bedfa0b815fd03103382efcf70..2458fb2e8e884349f665f0c52b5376cd459df8af 100644 (file)
--- a/src/cmd/internal/obj/loong64/a.out.go
+++ b/src/cmd/internal/obj/loong64/a.out.go
@@ -468,6 +468,7 @@ const (
        ADIVF
        ADIVU
        ADIVW
+       ADIVWU
 
        ALL
        ALLV
@@ -508,7 +509,9 @@ const (
        ANOR
        AOR
        AREM
+       AREMW
        AREMU
+       AREMWU
 
        ARFE
 

diff --git a/src/cmd/internal/obj/loong64/anames.go b/src/cmd/internal/obj/loong64/anames.go
index 0ee911401f03698f333ca0de2f912ba0f35d6496..18f818cebaa63df88b9a33118e121cee49984222 100644 (file)
--- a/src/cmd/internal/obj/loong64/anames.go
+++ b/src/cmd/internal/obj/loong64/anames.go
@@ -43,6 +43,7 @@ var Anames = []string{
        "DIVF",
        "DIVU",
        "DIVW",
+       "DIVWU",
        "LL",
        "LLV",
        "LUI",
@@ -74,7 +75,9 @@ var Anames = []string{
        "NOR",
        "OR",
        "REM",
+       "REMW",
        "REMU",
+       "REMWU",
        "RFE",
        "SC",
        "SCV",

diff --git a/src/cmd/internal/obj/loong64/asm.go b/src/cmd/internal/obj/loong64/asm.go
index 9aff344931dcaa69a0c34e9144dd6e93d99ac1bb..6a2346009847fad09abaf2cb5e4f4085737645a7 100644 (file)
--- a/src/cmd/internal/obj/loong64/asm.go
+++ b/src/cmd/internal/obj/loong64/asm.go
@@ -1428,6 +1428,7 @@ func buildop(ctxt *obj.Link) {
                        opset(AFTINTRNEVD, r0)
 
                case AADD:
+                       opset(AADDW, r0)
                        opset(ASGT, r0)
                        opset(ASGTU, r0)
                        opset(AADDU, r0)
@@ -1512,18 +1513,24 @@ func buildop(ctxt *obj.Link) {
                        opset(ABSTRINSV, r0)
 
                case ASUB:
+                       opset(ASUBW, r0)
                        opset(ASUBU, r0)
                        opset(ANOR, r0)
                        opset(ASUBV, r0)
                        opset(ASUBVU, r0)
                        opset(AMUL, r0)
+                       opset(AMULW, r0)
                        opset(AMULU, r0)
                        opset(AMULH, r0)
                        opset(AMULHU, r0)
                        opset(AREM, r0)
+                       opset(AREMW, r0)
                        opset(AREMU, r0)
+                       opset(AREMWU, r0)
                        opset(ADIV, r0)
+                       opset(ADIVW, r0)
                        opset(ADIVU, r0)
+                       opset(ADIVWU, r0)
                        opset(AMULV, r0)
                        opset(AMULVU, r0)
                        opset(AMULHV, r0)
@@ -3244,7 +3251,7 @@ func (c *ctxt0) oprrrr(a obj.As) uint32 {
 
 func (c *ctxt0) oprrr(a obj.As) uint32 {
        switch a {
-       case AADD:
+       case AADD, AADDW:
                return 0x20 << 15
        case AADDU:
                return 0x20 << 15
@@ -3266,7 +3273,7 @@ func (c *ctxt0) oprrr(a obj.As) uint32 {
                return 0x2c << 15 // orn
        case AANDN:
                return 0x2d << 15 // andn
-       case ASUB:
+       case ASUB, ASUBW:
                return 0x22 << 15
        case ASUBU, ANEGW:
                return 0x22 << 15
@@ -3297,7 +3304,7 @@ func (c *ctxt0) oprrr(a obj.As) uint32 {
        case ASUBVU, ANEGV:
                return 0x23 << 15
 
-       case AMUL:
+       case AMUL, AMULW:
                return 0x38 << 15 // mul.w
        case AMULU:
                return 0x38 << 15 // mul.w
@@ -3317,17 +3324,17 @@ func (c *ctxt0) oprrr(a obj.As) uint32 {
                return 0x3e << 15 // mulw.d.w
        case AMULWVWU:
                return 0x3f << 15 // mulw.d.wu
-       case ADIV:
+       case ADIV, ADIVW:
                return 0x40 << 15 // div.w
-       case ADIVU:
+       case ADIVU, ADIVWU:
                return 0x42 << 15 // div.wu
        case ADIVV:
                return 0x44 << 15 // div.d
        case ADIVVU:
                return 0x46 << 15 // div.du
-       case AREM:
+       case AREM, AREMW:
                return 0x41 << 15 // mod.w
-       case AREMU:
+       case AREMU, AREMWU:
                return 0x43 << 15 // mod.wu
        case AREMV:
                return 0x45 << 15 // mod.d
@@ -4485,7 +4492,7 @@ func (c *ctxt0) opir(a obj.As) uint32 {
 
 func (c *ctxt0) opirr(a obj.As) uint32 {
        switch a {
-       case AADD, AADDU:
+       case AADD, AADDW, AADDU:
                return 0x00a << 22
        case ASGT:
                return 0x008 << 22