MOVHU R4, 1(R5) // a4044029
MOVHU y+8(FP), R4 // 6440402a
MOVHU 1(R5), R4 // a404402a
- MULU R4, R5 // a5101c00
- MULU R4, R5, R6 // a6101c00
MULH R4, R5 // a5901c00
MULH R4, R5, R6 // a6901c00
MULHU R4, R5 // a5101d00
SGTU $4096, R4, R5 // 3e00001485f81200
SGTU $65536, R4 // 1e02001484f81200
SGTU $4096, R4 // 3e00001484f81200
- ADDU $65536, R4, R5 // 1e02001485781000
- ADDU $4096, R4, R5 // 3e00001485781000
- ADDU $65536, R4 // 1e02001484781000
- ADDU $4096, R4 // 3e00001484781000
ADDVU $65536, R4, R5 // 1e02001485f81000
ADDVU $4096, R4, R5 // 3e00001485f81000
ADDVU $65536, R4 // 1e02001484f81000
SGTU $74565, R4, R5 // 5e020014de178d0385f81200
SGTU $4097, R4 // 3e000014de07800384f81200
SGTU $4097, R4, R5 // 3e000014de07800385f81200
- ADDU $74565, R4 // 5e020014de178d0384781000
- ADDU $74565, R4, R5 // 5e020014de178d0385781000
- ADDU $4097, R4 // 3e000014de07800384781000
- ADDU $4097, R4, R5 // 3e000014de07800385781000
ADDVU $4097, R4 // 3e000014de07800384f81000
ADDVU $4097, R4, R5 // 3e000014de07800385f81000
ADDVU $74565, R4 // 5e020014de178d0384f81000
AADD
AADDD
AADDF
- AADDU
AADDW
AAND
AMUL
AMULD
AMULF
- AMULU
AMULH
AMULHU
AMULW
ASUBD
ASUBF
- ASUBU
ASUBW
ADBAR
ASYSCALL
"ADD",
"ADDD",
"ADDF",
- "ADDU",
"ADDW",
"AND",
"BEQ",
"MUL",
"MULD",
"MULF",
- "MULU",
"MULH",
"MULHU",
"MULW",
"SUB",
"SUBD",
"SUBF",
- "SUBU",
"SUBW",
"DBAR",
"SYSCALL",
opset(AADDW, r0)
opset(ASGT, r0)
opset(ASGTU, r0)
- opset(AADDU, r0)
case AADDV:
opset(AADDVU, r0)
case ASUB:
opset(ASUBW, r0)
- opset(ASUBU, r0)
opset(ANOR, r0)
opset(ASUBV, r0)
opset(ASUBVU, r0)
opset(AMUL, r0)
opset(AMULW, r0)
- opset(AMULU, r0)
opset(AMULH, r0)
opset(AMULHU, r0)
opset(AREM, r0)
o5 := uint32(0)
o6 := uint32(0)
- add := AADDU
- add = AADDVU
+ add := AADDVU
switch o.type_ {
default:
v := c.regoff(&p.From)
a := AOR
if v < 0 {
- a = AADDU
+ a = AADD
}
o1 = OP_12IRR(c.opirr(a), uint32(v), uint32(0), uint32(REGTMP))
r := int(p.Reg)
case 34: // mov $con,fr
v := c.regoff(&p.From)
- a := AADDU
+ a := AADD
if v > 0 {
a = AOR
}
switch a {
case AADD, AADDW:
return 0x20 << 15
- case AADDU:
- return 0x20 << 15
case ASGT:
return 0x24 << 15 // SLT
case ASGTU:
return 0x2c << 15 // orn
case AANDN:
return 0x2d << 15 // andn
- case ASUB, ASUBW:
- return 0x22 << 15
- case ASUBU, ANEGW:
+ case ASUB, ASUBW, ANEGW:
return 0x22 << 15
case ANOR:
return 0x28 << 15
case AMUL, AMULW:
return 0x38 << 15 // mul.w
- case AMULU:
- return 0x38 << 15 // mul.w
case AMULH:
return 0x39 << 15 // mulh.w
case AMULHU:
func (c *ctxt0) opirr(a obj.As) uint32 {
switch a {
- case AADD, AADDW, AADDU:
+ case AADD, AADDW:
return 0x00a << 22
case ASGT:
return 0x008 << 22
p.As = AADD
}
- case ASUBU:
- if p.From.Type == obj.TYPE_CONST {
- p.From.Offset = -p.From.Offset
- p.As = AADDU
- }
-
case ASUBV:
if p.From.Type == obj.TYPE_CONST {
p.From.Offset = -p.From.Offset
q.Link = q1
case AADD,
- AADDU,
AADDV,
AADDVU:
if p.To.Type == obj.TYPE_REG && p.To.Reg == REGSP && p.From.Type == obj.TYPE_CONST {