[dev.simd] cmd/compile: add VZEROUPPER and VZEROALL inst

Change-Id: I41d60561fefdfa676e8b22648871ff1004711ac9
Reviewed-on: https://go-review.googlesource.com/c/go/+/686840
LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com>
Reviewed-by: David Chase <drchase@google.com>

diff --git a/src/cmd/compile/internal/amd64/ssa.go b/src/cmd/compile/internal/amd64/ssa.go
index 3e45097edf4c0c46f329b7372a671c7eb932102c..9c31b77e7031fbd7f369fd388fdf80e14044af85 100644 (file)
--- a/src/cmd/compile/internal/amd64/ssa.go
+++ b/src/cmd/compile/internal/amd64/ssa.go
@@ -1445,6 +1445,8 @@ func ssaGenValue(s *ssagen.State, v *ssa.Value) {
 
        // XXX SIMD
        // XXX may change depending on how we handle aliased registers
+       case ssa.OpAMD64VZEROUPPER, ssa.OpAMD64VZEROALL:
+               s.Prog(v.Op.Asm())
        case ssa.OpAMD64Zero128, ssa.OpAMD64Zero256, ssa.OpAMD64Zero512:
                p := s.Prog(v.Op.Asm())
                p.From.Type = obj.TYPE_REG

diff --git a/src/cmd/compile/internal/ssa/_gen/AMD64Ops.go b/src/cmd/compile/internal/ssa/_gen/AMD64Ops.go
index 35d26dfdfa16ddceff28c34d6a0212bd9805c210..543233f4d831fe56d47c562f9aae169fda596f05 100644 (file)
--- a/src/cmd/compile/internal/ssa/_gen/AMD64Ops.go
+++ b/src/cmd/compile/internal/ssa/_gen/AMD64Ops.go
@@ -1311,6 +1311,9 @@ func init() {
                {name: "Zero128", argLength: 0, reg: v01, asm: "VPXOR"},
                {name: "Zero256", argLength: 0, reg: v01, asm: "VPXOR"},
                {name: "Zero512", argLength: 0, reg: w01, asm: "VPXORQ"},
+
+               {name: "VZEROUPPER", argLength: 0, asm: "VZEROUPPER"},
+               {name: "VZEROALL", argLength: 0, asm: "VZEROALL"},
        }
 
        var AMD64blocks = []blockData{

diff --git a/src/cmd/compile/internal/ssa/opGen.go b/src/cmd/compile/internal/ssa/opGen.go
index dc84a1f4fa813d869459d69aa4b11e9757eeb28a..119badedcc6e1450f580cac83c67bc44fc68c6bd 100644 (file)
--- a/src/cmd/compile/internal/ssa/opGen.go
+++ b/src/cmd/compile/internal/ssa/opGen.go
@@ -1196,6 +1196,8 @@ const (
        OpAMD64Zero128
        OpAMD64Zero256
        OpAMD64Zero512
+       OpAMD64VZEROUPPER
+       OpAMD64VZEROALL
        OpAMD64VADDPS512
        OpAMD64VADDPSMasked512
        OpAMD64VRCP14PS512
@@ -18565,6 +18567,18 @@ var opcodeTable = [...]opInfo{
                        },
                },
        },
+       {
+               name:   "VZEROUPPER",
+               argLen: 0,
+               asm:    x86.AVZEROUPPER,
+               reg:    regInfo{},
+       },
+       {
+               name:   "VZEROALL",
+               argLen: 0,
+               asm:    x86.AVZEROALL,
+               reg:    regInfo{},
+       },
        {
                name:        "VADDPS512",
                argLen:      2,