ssa.OpAMD64VPBROADCASTW512,
ssa.OpAMD64VPBROADCASTD512,
ssa.OpAMD64VPBROADCASTQ512,
+ ssa.OpAMD64VCVTDQ2PS128,
+ ssa.OpAMD64VCVTDQ2PS256,
+ ssa.OpAMD64VCVTDQ2PS512,
+ ssa.OpAMD64VCVTQQ2PSX128,
+ ssa.OpAMD64VCVTQQ2PSY128,
+ ssa.OpAMD64VCVTQQ2PS256,
+ ssa.OpAMD64VCVTUDQ2PS128,
+ ssa.OpAMD64VCVTUDQ2PS256,
+ ssa.OpAMD64VCVTUDQ2PS512,
+ ssa.OpAMD64VCVTUQQ2PSX128,
+ ssa.OpAMD64VCVTUQQ2PSY128,
+ ssa.OpAMD64VCVTUQQ2PS256,
+ ssa.OpAMD64VCVTDQ2PD256,
+ ssa.OpAMD64VCVTDQ2PD512,
+ ssa.OpAMD64VCVTQQ2PD128,
+ ssa.OpAMD64VCVTQQ2PD256,
+ ssa.OpAMD64VCVTQQ2PD512,
+ ssa.OpAMD64VCVTUDQ2PD256,
+ ssa.OpAMD64VCVTUDQ2PD512,
+ ssa.OpAMD64VCVTUQQ2PD128,
+ ssa.OpAMD64VCVTUQQ2PD256,
+ ssa.OpAMD64VCVTUQQ2PD512,
ssa.OpAMD64VCVTTPS2DQ128,
ssa.OpAMD64VCVTTPS2DQ256,
ssa.OpAMD64VCVTTPS2DQ512,
ssa.OpAMD64VPCOMPRESSQMasked128,
ssa.OpAMD64VPCOMPRESSQMasked256,
ssa.OpAMD64VPCOMPRESSQMasked512,
+ ssa.OpAMD64VCVTDQ2PSMasked128,
+ ssa.OpAMD64VCVTDQ2PSMasked256,
+ ssa.OpAMD64VCVTDQ2PSMasked512,
+ ssa.OpAMD64VCVTQQ2PSXMasked128,
+ ssa.OpAMD64VCVTQQ2PSYMasked128,
+ ssa.OpAMD64VCVTQQ2PSMasked256,
+ ssa.OpAMD64VCVTUDQ2PSMasked128,
+ ssa.OpAMD64VCVTUDQ2PSMasked256,
+ ssa.OpAMD64VCVTUDQ2PSMasked512,
+ ssa.OpAMD64VCVTUQQ2PSXMasked128,
+ ssa.OpAMD64VCVTUQQ2PSYMasked128,
+ ssa.OpAMD64VCVTUQQ2PSMasked256,
+ ssa.OpAMD64VCVTDQ2PDMasked256,
+ ssa.OpAMD64VCVTDQ2PDMasked512,
+ ssa.OpAMD64VCVTQQ2PDMasked128,
+ ssa.OpAMD64VCVTQQ2PDMasked256,
+ ssa.OpAMD64VCVTQQ2PDMasked512,
+ ssa.OpAMD64VCVTUDQ2PDMasked256,
+ ssa.OpAMD64VCVTUDQ2PDMasked512,
+ ssa.OpAMD64VCVTUQQ2PDMasked128,
+ ssa.OpAMD64VCVTUQQ2PDMasked256,
+ ssa.OpAMD64VCVTUQQ2PDMasked512,
ssa.OpAMD64VCVTTPS2DQMasked128,
ssa.OpAMD64VCVTTPS2DQMasked256,
ssa.OpAMD64VCVTTPS2DQMasked512,
ssa.OpAMD64VPABSQMasked128load,
ssa.OpAMD64VPABSQMasked256load,
ssa.OpAMD64VPABSQMasked512load,
+ ssa.OpAMD64VCVTDQ2PSMasked128load,
+ ssa.OpAMD64VCVTDQ2PSMasked256load,
+ ssa.OpAMD64VCVTDQ2PSMasked512load,
+ ssa.OpAMD64VCVTQQ2PSXMasked128load,
+ ssa.OpAMD64VCVTQQ2PSYMasked128load,
+ ssa.OpAMD64VCVTQQ2PSMasked256load,
+ ssa.OpAMD64VCVTUDQ2PSMasked128load,
+ ssa.OpAMD64VCVTUDQ2PSMasked256load,
+ ssa.OpAMD64VCVTUDQ2PSMasked512load,
+ ssa.OpAMD64VCVTUQQ2PSXMasked128load,
+ ssa.OpAMD64VCVTUQQ2PSYMasked128load,
+ ssa.OpAMD64VCVTUQQ2PSMasked256load,
+ ssa.OpAMD64VCVTDQ2PDMasked256load,
+ ssa.OpAMD64VCVTDQ2PDMasked512load,
+ ssa.OpAMD64VCVTQQ2PDMasked128load,
+ ssa.OpAMD64VCVTQQ2PDMasked256load,
+ ssa.OpAMD64VCVTQQ2PDMasked512load,
+ ssa.OpAMD64VCVTUDQ2PDMasked256load,
+ ssa.OpAMD64VCVTUDQ2PDMasked512load,
+ ssa.OpAMD64VCVTUQQ2PDMasked128load,
+ ssa.OpAMD64VCVTUQQ2PDMasked256load,
+ ssa.OpAMD64VCVTUQQ2PDMasked512load,
ssa.OpAMD64VCVTTPS2DQMasked128load,
ssa.OpAMD64VCVTTPS2DQMasked256load,
ssa.OpAMD64VCVTTPS2DQMasked512load,
ssa.OpAMD64VPABSQ128load,
ssa.OpAMD64VPABSQ256load,
ssa.OpAMD64VPABSQ512load,
+ ssa.OpAMD64VCVTDQ2PS512load,
+ ssa.OpAMD64VCVTQQ2PSX128load,
+ ssa.OpAMD64VCVTQQ2PSY128load,
+ ssa.OpAMD64VCVTQQ2PS256load,
+ ssa.OpAMD64VCVTUDQ2PS128load,
+ ssa.OpAMD64VCVTUDQ2PS256load,
+ ssa.OpAMD64VCVTUDQ2PS512load,
+ ssa.OpAMD64VCVTUQQ2PSX128load,
+ ssa.OpAMD64VCVTUQQ2PSY128load,
+ ssa.OpAMD64VCVTUQQ2PS256load,
+ ssa.OpAMD64VCVTDQ2PD512load,
+ ssa.OpAMD64VCVTQQ2PD128load,
+ ssa.OpAMD64VCVTQQ2PD256load,
+ ssa.OpAMD64VCVTQQ2PD512load,
+ ssa.OpAMD64VCVTUDQ2PD256load,
+ ssa.OpAMD64VCVTUDQ2PD512load,
+ ssa.OpAMD64VCVTUQQ2PD128load,
+ ssa.OpAMD64VCVTUQQ2PD256load,
+ ssa.OpAMD64VCVTUQQ2PD512load,
ssa.OpAMD64VCVTTPS2DQ512load,
ssa.OpAMD64VCVTTPD2DQ256load,
ssa.OpAMD64VCVTTPS2QQ256load,
ssa.OpAMD64VREDUCEPDMasked128Merging,
ssa.OpAMD64VREDUCEPDMasked256Merging,
ssa.OpAMD64VREDUCEPDMasked512Merging,
+ ssa.OpAMD64VCVTDQ2PSMasked128Merging,
+ ssa.OpAMD64VCVTDQ2PSMasked256Merging,
+ ssa.OpAMD64VCVTDQ2PSMasked512Merging,
+ ssa.OpAMD64VCVTQQ2PSXMasked128Merging,
+ ssa.OpAMD64VCVTQQ2PSYMasked128Merging,
+ ssa.OpAMD64VCVTQQ2PSMasked256Merging,
+ ssa.OpAMD64VCVTUDQ2PSMasked128Merging,
+ ssa.OpAMD64VCVTUDQ2PSMasked256Merging,
+ ssa.OpAMD64VCVTUDQ2PSMasked512Merging,
+ ssa.OpAMD64VCVTUQQ2PSXMasked128Merging,
+ ssa.OpAMD64VCVTUQQ2PSYMasked128Merging,
+ ssa.OpAMD64VCVTUQQ2PSMasked256Merging,
+ ssa.OpAMD64VCVTDQ2PDMasked256Merging,
+ ssa.OpAMD64VCVTDQ2PDMasked512Merging,
+ ssa.OpAMD64VCVTQQ2PDMasked128Merging,
+ ssa.OpAMD64VCVTQQ2PDMasked256Merging,
+ ssa.OpAMD64VCVTQQ2PDMasked512Merging,
+ ssa.OpAMD64VCVTUDQ2PDMasked256Merging,
+ ssa.OpAMD64VCVTUDQ2PDMasked512Merging,
+ ssa.OpAMD64VCVTUQQ2PDMasked128Merging,
+ ssa.OpAMD64VCVTUQQ2PDMasked256Merging,
+ ssa.OpAMD64VCVTUQQ2PDMasked512Merging,
ssa.OpAMD64VCVTTPS2DQMasked128Merging,
ssa.OpAMD64VCVTTPS2DQMasked256Merging,
ssa.OpAMD64VCVTTPS2DQMasked512Merging,
ssa.OpAMD64VPALIGNRMasked256,
ssa.OpAMD64VPALIGNRMasked512,
ssa.OpAMD64VPALIGNRMasked128,
+ ssa.OpAMD64VCVTDQ2PSMasked128,
+ ssa.OpAMD64VCVTDQ2PSMasked128load,
+ ssa.OpAMD64VCVTDQ2PSMasked256,
+ ssa.OpAMD64VCVTDQ2PSMasked256load,
+ ssa.OpAMD64VCVTDQ2PSMasked512,
+ ssa.OpAMD64VCVTDQ2PSMasked512load,
+ ssa.OpAMD64VCVTQQ2PSXMasked128,
+ ssa.OpAMD64VCVTQQ2PSXMasked128load,
+ ssa.OpAMD64VCVTQQ2PSYMasked128,
+ ssa.OpAMD64VCVTQQ2PSYMasked128load,
+ ssa.OpAMD64VCVTQQ2PSMasked256,
+ ssa.OpAMD64VCVTQQ2PSMasked256load,
+ ssa.OpAMD64VCVTUDQ2PSMasked128,
+ ssa.OpAMD64VCVTUDQ2PSMasked128load,
+ ssa.OpAMD64VCVTUDQ2PSMasked256,
+ ssa.OpAMD64VCVTUDQ2PSMasked256load,
+ ssa.OpAMD64VCVTUDQ2PSMasked512,
+ ssa.OpAMD64VCVTUDQ2PSMasked512load,
+ ssa.OpAMD64VCVTUQQ2PSXMasked128,
+ ssa.OpAMD64VCVTUQQ2PSXMasked128load,
+ ssa.OpAMD64VCVTUQQ2PSYMasked128,
+ ssa.OpAMD64VCVTUQQ2PSYMasked128load,
+ ssa.OpAMD64VCVTUQQ2PSMasked256,
+ ssa.OpAMD64VCVTUQQ2PSMasked256load,
+ ssa.OpAMD64VCVTDQ2PDMasked256,
+ ssa.OpAMD64VCVTDQ2PDMasked256load,
+ ssa.OpAMD64VCVTDQ2PDMasked512,
+ ssa.OpAMD64VCVTDQ2PDMasked512load,
+ ssa.OpAMD64VCVTQQ2PDMasked128,
+ ssa.OpAMD64VCVTQQ2PDMasked128load,
+ ssa.OpAMD64VCVTQQ2PDMasked256,
+ ssa.OpAMD64VCVTQQ2PDMasked256load,
+ ssa.OpAMD64VCVTQQ2PDMasked512,
+ ssa.OpAMD64VCVTQQ2PDMasked512load,
+ ssa.OpAMD64VCVTUDQ2PDMasked256,
+ ssa.OpAMD64VCVTUDQ2PDMasked256load,
+ ssa.OpAMD64VCVTUDQ2PDMasked512,
+ ssa.OpAMD64VCVTUDQ2PDMasked512load,
+ ssa.OpAMD64VCVTUQQ2PDMasked128,
+ ssa.OpAMD64VCVTUQQ2PDMasked128load,
+ ssa.OpAMD64VCVTUQQ2PDMasked256,
+ ssa.OpAMD64VCVTUQQ2PDMasked256load,
+ ssa.OpAMD64VCVTUQQ2PDMasked512,
+ ssa.OpAMD64VCVTUQQ2PDMasked512load,
ssa.OpAMD64VCVTTPS2DQMasked128,
ssa.OpAMD64VCVTTPS2DQMasked128load,
ssa.OpAMD64VCVTTPS2DQMasked256,
(ConcatShiftBytesRightUint8x16 ...) => (VPALIGNR128 ...)
(ConcatShiftBytesRightGroupedUint8x32 ...) => (VPALIGNR256 ...)
(ConcatShiftBytesRightGroupedUint8x64 ...) => (VPALIGNR512 ...)
+(ConvertToFloat32Int32x4 ...) => (VCVTDQ2PS128 ...)
+(ConvertToFloat32Int32x8 ...) => (VCVTDQ2PS256 ...)
+(ConvertToFloat32Int32x16 ...) => (VCVTDQ2PS512 ...)
+(ConvertToFloat32Int64x2 ...) => (VCVTQQ2PSX128 ...)
+(ConvertToFloat32Int64x4 ...) => (VCVTQQ2PSY128 ...)
+(ConvertToFloat32Int64x8 ...) => (VCVTQQ2PS256 ...)
+(ConvertToFloat32Uint32x4 ...) => (VCVTUDQ2PS128 ...)
+(ConvertToFloat32Uint32x8 ...) => (VCVTUDQ2PS256 ...)
+(ConvertToFloat32Uint32x16 ...) => (VCVTUDQ2PS512 ...)
+(ConvertToFloat32Uint64x2 ...) => (VCVTUQQ2PSX128 ...)
+(ConvertToFloat32Uint64x4 ...) => (VCVTUQQ2PSY128 ...)
+(ConvertToFloat32Uint64x8 ...) => (VCVTUQQ2PS256 ...)
+(ConvertToFloat64Int32x4 ...) => (VCVTDQ2PD256 ...)
+(ConvertToFloat64Int32x8 ...) => (VCVTDQ2PD512 ...)
+(ConvertToFloat64Int64x2 ...) => (VCVTQQ2PD128 ...)
+(ConvertToFloat64Int64x4 ...) => (VCVTQQ2PD256 ...)
+(ConvertToFloat64Int64x8 ...) => (VCVTQQ2PD512 ...)
+(ConvertToFloat64Uint32x4 ...) => (VCVTUDQ2PD256 ...)
+(ConvertToFloat64Uint32x8 ...) => (VCVTUDQ2PD512 ...)
+(ConvertToFloat64Uint64x2 ...) => (VCVTUQQ2PD128 ...)
+(ConvertToFloat64Uint64x4 ...) => (VCVTUQQ2PD256 ...)
+(ConvertToFloat64Uint64x8 ...) => (VCVTUQQ2PD512 ...)
(ConvertToInt32Float32x4 ...) => (VCVTTPS2DQ128 ...)
(ConvertToInt32Float32x8 ...) => (VCVTTPS2DQ256 ...)
(ConvertToInt32Float32x16 ...) => (VCVTTPS2DQ512 ...)
(VMOVDQU8Masked256 (VPALIGNR256 [a] x y) mask) => (VPALIGNRMasked256 [a] x y mask)
(VMOVDQU8Masked512 (VPALIGNR512 [a] x y) mask) => (VPALIGNRMasked512 [a] x y mask)
(VMOVDQU8Masked128 (VPALIGNR128 [a] x y) mask) => (VPALIGNRMasked128 [a] x y mask)
+(VMOVDQU32Masked128 (VCVTDQ2PS128 x) mask) => (VCVTDQ2PSMasked128 x mask)
+(VMOVDQU32Masked256 (VCVTDQ2PS256 x) mask) => (VCVTDQ2PSMasked256 x mask)
+(VMOVDQU32Masked512 (VCVTDQ2PS512 x) mask) => (VCVTDQ2PSMasked512 x mask)
+(VMOVDQU64Masked128 (VCVTQQ2PSX128 x) mask) => (VCVTQQ2PSXMasked128 x mask)
+(VMOVDQU64Masked128 (VCVTQQ2PSY128 x) mask) => (VCVTQQ2PSYMasked128 x mask)
+(VMOVDQU64Masked256 (VCVTQQ2PS256 x) mask) => (VCVTQQ2PSMasked256 x mask)
+(VMOVDQU32Masked128 (VCVTUDQ2PS128 x) mask) => (VCVTUDQ2PSMasked128 x mask)
+(VMOVDQU32Masked256 (VCVTUDQ2PS256 x) mask) => (VCVTUDQ2PSMasked256 x mask)
+(VMOVDQU32Masked512 (VCVTUDQ2PS512 x) mask) => (VCVTUDQ2PSMasked512 x mask)
+(VMOVDQU64Masked128 (VCVTUQQ2PSX128 x) mask) => (VCVTUQQ2PSXMasked128 x mask)
+(VMOVDQU64Masked128 (VCVTUQQ2PSY128 x) mask) => (VCVTUQQ2PSYMasked128 x mask)
+(VMOVDQU64Masked256 (VCVTUQQ2PS256 x) mask) => (VCVTUQQ2PSMasked256 x mask)
+(VMOVDQU32Masked256 (VCVTDQ2PD256 x) mask) => (VCVTDQ2PDMasked256 x mask)
+(VMOVDQU32Masked512 (VCVTDQ2PD512 x) mask) => (VCVTDQ2PDMasked512 x mask)
+(VMOVDQU64Masked128 (VCVTQQ2PD128 x) mask) => (VCVTQQ2PDMasked128 x mask)
+(VMOVDQU64Masked256 (VCVTQQ2PD256 x) mask) => (VCVTQQ2PDMasked256 x mask)
+(VMOVDQU64Masked512 (VCVTQQ2PD512 x) mask) => (VCVTQQ2PDMasked512 x mask)
+(VMOVDQU32Masked256 (VCVTUDQ2PD256 x) mask) => (VCVTUDQ2PDMasked256 x mask)
+(VMOVDQU32Masked512 (VCVTUDQ2PD512 x) mask) => (VCVTUDQ2PDMasked512 x mask)
+(VMOVDQU64Masked128 (VCVTUQQ2PD128 x) mask) => (VCVTUQQ2PDMasked128 x mask)
+(VMOVDQU64Masked256 (VCVTUQQ2PD256 x) mask) => (VCVTUQQ2PDMasked256 x mask)
+(VMOVDQU64Masked512 (VCVTUQQ2PD512 x) mask) => (VCVTUQQ2PDMasked512 x mask)
(VMOVDQU32Masked128 (VCVTTPS2DQ128 x) mask) => (VCVTTPS2DQMasked128 x mask)
(VMOVDQU32Masked256 (VCVTTPS2DQ256 x) mask) => (VCVTTPS2DQMasked256 x mask)
(VMOVDQU32Masked512 (VCVTTPS2DQ512 x) mask) => (VCVTTPS2DQMasked512 x mask)
(VPBLENDMBMasked512 dst (VPSUBSB512 x y) mask) => (VPSUBSBMasked512Merging dst x y mask)
(VPBLENDMBMasked512 dst (VPSUBUSB512 x y) mask) => (VPSUBUSBMasked512Merging dst x y mask)
(VPBLENDMDMasked512 dst (VADDPS512 x y) mask) => (VADDPSMasked512Merging dst x y mask)
+(VPBLENDMDMasked512 dst (VCVTDQ2PS512 x) mask) => (VCVTDQ2PSMasked512Merging dst x mask)
(VPBLENDMDMasked512 dst (VCVTTPS2DQ512 x) mask) => (VCVTTPS2DQMasked512Merging dst x mask)
(VPBLENDMDMasked512 dst (VCVTTPS2UDQ512 x) mask) => (VCVTTPS2UDQMasked512Merging dst x mask)
+(VPBLENDMDMasked512 dst (VCVTUDQ2PS512 x) mask) => (VCVTUDQ2PSMasked512Merging dst x mask)
(VPBLENDMDMasked512 dst (VDIVPS512 x y) mask) => (VDIVPSMasked512Merging dst x y mask)
(VPBLENDMDMasked512 dst (VMAXPS512 x y) mask) => (VMAXPSMasked512Merging dst x y mask)
(VPBLENDMDMasked512 dst (VMINPS512 x y) mask) => (VMINPSMasked512Merging dst x y mask)
(VPBLENDMDMasked512 dst (VSQRTPS512 x) mask) => (VSQRTPSMasked512Merging dst x mask)
(VPBLENDMDMasked512 dst (VSUBPS512 x y) mask) => (VSUBPSMasked512Merging dst x y mask)
(VPBLENDMQMasked512 dst (VADDPD512 x y) mask) => (VADDPDMasked512Merging dst x y mask)
+(VPBLENDMQMasked512 dst (VCVTQQ2PD512 x) mask) => (VCVTQQ2PDMasked512Merging dst x mask)
+(VPBLENDMQMasked512 dst (VCVTQQ2PS256 x) mask) => (VCVTQQ2PSMasked256Merging dst x mask)
(VPBLENDMQMasked512 dst (VCVTTPD2DQ256 x) mask) => (VCVTTPD2DQMasked256Merging dst x mask)
(VPBLENDMQMasked512 dst (VCVTTPD2QQ512 x) mask) => (VCVTTPD2QQMasked512Merging dst x mask)
(VPBLENDMQMasked512 dst (VCVTTPD2UDQ256 x) mask) => (VCVTTPD2UDQMasked256Merging dst x mask)
(VPBLENDMQMasked512 dst (VCVTTPD2UQQ512 x) mask) => (VCVTTPD2UQQMasked512Merging dst x mask)
+(VPBLENDMQMasked512 dst (VCVTUQQ2PD512 x) mask) => (VCVTUQQ2PDMasked512Merging dst x mask)
+(VPBLENDMQMasked512 dst (VCVTUQQ2PS256 x) mask) => (VCVTUQQ2PSMasked256Merging dst x mask)
(VPBLENDMQMasked512 dst (VDIVPD512 x y) mask) => (VDIVPDMasked512Merging dst x y mask)
(VPBLENDMQMasked512 dst (VMAXPD512 x y) mask) => (VMAXPDMasked512Merging dst x y mask)
(VPBLENDMQMasked512 dst (VMINPD512 x y) mask) => (VMINPDMasked512Merging dst x y mask)
(VPBLENDVB128 dst (VBROADCASTSS128 x) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VBROADCASTSSMasked128Merging dst x (VPMOVVec32x4ToM <types.TypeMask> mask))
(VPBLENDVB128 dst (VBROADCASTSS256 x) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VBROADCASTSSMasked256Merging dst x (VPMOVVec32x4ToM <types.TypeMask> mask))
(VPBLENDVB128 dst (VBROADCASTSS512 x) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VBROADCASTSSMasked512Merging dst x (VPMOVVec32x4ToM <types.TypeMask> mask))
+(VPBLENDVB128 dst (VCVTDQ2PD256 x) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VCVTDQ2PDMasked256Merging dst x (VPMOVVec32x4ToM <types.TypeMask> mask))
+(VPBLENDVB128 dst (VCVTDQ2PS128 x) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VCVTDQ2PSMasked128Merging dst x (VPMOVVec32x4ToM <types.TypeMask> mask))
+(VPBLENDVB128 dst (VCVTQQ2PD128 x) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VCVTQQ2PDMasked128Merging dst x (VPMOVVec64x2ToM <types.TypeMask> mask))
+(VPBLENDVB128 dst (VCVTQQ2PSX128 x) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VCVTQQ2PSXMasked128Merging dst x (VPMOVVec64x2ToM <types.TypeMask> mask))
(VPBLENDVB128 dst (VCVTTPD2DQX128 x) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VCVTTPD2DQXMasked128Merging dst x (VPMOVVec64x2ToM <types.TypeMask> mask))
(VPBLENDVB128 dst (VCVTTPD2QQ128 x) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VCVTTPD2QQMasked128Merging dst x (VPMOVVec64x2ToM <types.TypeMask> mask))
(VPBLENDVB128 dst (VCVTTPD2UDQX128 x) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VCVTTPD2UDQXMasked128Merging dst x (VPMOVVec64x2ToM <types.TypeMask> mask))
(VPBLENDVB128 dst (VCVTTPS2QQ256 x) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VCVTTPS2QQMasked256Merging dst x (VPMOVVec32x4ToM <types.TypeMask> mask))
(VPBLENDVB128 dst (VCVTTPS2UDQ128 x) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VCVTTPS2UDQMasked128Merging dst x (VPMOVVec32x4ToM <types.TypeMask> mask))
(VPBLENDVB128 dst (VCVTTPS2UQQ256 x) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VCVTTPS2UQQMasked256Merging dst x (VPMOVVec32x4ToM <types.TypeMask> mask))
+(VPBLENDVB128 dst (VCVTUDQ2PD256 x) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VCVTUDQ2PDMasked256Merging dst x (VPMOVVec32x4ToM <types.TypeMask> mask))
+(VPBLENDVB128 dst (VCVTUDQ2PS128 x) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VCVTUDQ2PSMasked128Merging dst x (VPMOVVec32x4ToM <types.TypeMask> mask))
+(VPBLENDVB128 dst (VCVTUQQ2PD128 x) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VCVTUQQ2PDMasked128Merging dst x (VPMOVVec64x2ToM <types.TypeMask> mask))
+(VPBLENDVB128 dst (VCVTUQQ2PSX128 x) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VCVTUQQ2PSXMasked128Merging dst x (VPMOVVec64x2ToM <types.TypeMask> mask))
(VPBLENDVB128 dst (VDIVPD128 x y) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VDIVPDMasked128Merging dst x y (VPMOVVec64x2ToM <types.TypeMask> mask))
(VPBLENDVB128 dst (VDIVPS128 x y) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VDIVPSMasked128Merging dst x y (VPMOVVec32x4ToM <types.TypeMask> mask))
(VPBLENDVB128 dst (VGF2P8MULB128 x y) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VGF2P8MULBMasked128Merging dst x y (VPMOVVec8x16ToM <types.TypeMask> mask))
(VPBLENDVB128 dst (VSUBPS128 x y) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VSUBPSMasked128Merging dst x y (VPMOVVec32x4ToM <types.TypeMask> mask))
(VPBLENDVB256 dst (VADDPD256 x y) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VADDPDMasked256Merging dst x y (VPMOVVec64x4ToM <types.TypeMask> mask))
(VPBLENDVB256 dst (VADDPS256 x y) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VADDPSMasked256Merging dst x y (VPMOVVec32x8ToM <types.TypeMask> mask))
+(VPBLENDVB256 dst (VCVTDQ2PD512 x) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VCVTDQ2PDMasked512Merging dst x (VPMOVVec32x8ToM <types.TypeMask> mask))
+(VPBLENDVB256 dst (VCVTDQ2PS256 x) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VCVTDQ2PSMasked256Merging dst x (VPMOVVec32x8ToM <types.TypeMask> mask))
+(VPBLENDVB256 dst (VCVTQQ2PD256 x) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VCVTQQ2PDMasked256Merging dst x (VPMOVVec64x4ToM <types.TypeMask> mask))
+(VPBLENDVB256 dst (VCVTQQ2PSY128 x) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VCVTQQ2PSYMasked128Merging dst x (VPMOVVec64x4ToM <types.TypeMask> mask))
(VPBLENDVB256 dst (VCVTTPD2DQY128 x) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VCVTTPD2DQYMasked128Merging dst x (VPMOVVec64x4ToM <types.TypeMask> mask))
(VPBLENDVB256 dst (VCVTTPD2QQ256 x) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VCVTTPD2QQMasked256Merging dst x (VPMOVVec64x4ToM <types.TypeMask> mask))
(VPBLENDVB256 dst (VCVTTPD2UDQY128 x) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VCVTTPD2UDQYMasked128Merging dst x (VPMOVVec64x4ToM <types.TypeMask> mask))
(VPBLENDVB256 dst (VCVTTPS2QQ512 x) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VCVTTPS2QQMasked512Merging dst x (VPMOVVec32x8ToM <types.TypeMask> mask))
(VPBLENDVB256 dst (VCVTTPS2UDQ256 x) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VCVTTPS2UDQMasked256Merging dst x (VPMOVVec32x8ToM <types.TypeMask> mask))
(VPBLENDVB256 dst (VCVTTPS2UQQ512 x) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VCVTTPS2UQQMasked512Merging dst x (VPMOVVec32x8ToM <types.TypeMask> mask))
+(VPBLENDVB256 dst (VCVTUDQ2PD512 x) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VCVTUDQ2PDMasked512Merging dst x (VPMOVVec32x8ToM <types.TypeMask> mask))
+(VPBLENDVB256 dst (VCVTUDQ2PS256 x) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VCVTUDQ2PSMasked256Merging dst x (VPMOVVec32x8ToM <types.TypeMask> mask))
+(VPBLENDVB256 dst (VCVTUQQ2PD256 x) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VCVTUQQ2PDMasked256Merging dst x (VPMOVVec64x4ToM <types.TypeMask> mask))
+(VPBLENDVB256 dst (VCVTUQQ2PSY128 x) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VCVTUQQ2PSYMasked128Merging dst x (VPMOVVec64x4ToM <types.TypeMask> mask))
(VPBLENDVB256 dst (VDIVPD256 x y) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VDIVPDMasked256Merging dst x y (VPMOVVec64x4ToM <types.TypeMask> mask))
(VPBLENDVB256 dst (VDIVPS256 x y) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VDIVPSMasked256Merging dst x y (VPMOVVec32x8ToM <types.TypeMask> mask))
(VPBLENDVB256 dst (VGF2P8MULB256 x y) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VGF2P8MULBMasked256Merging dst x y (VPMOVVec8x32ToM <types.TypeMask> mask))
(VPERMI2QMasked256 x y l:(VMOVDQUload256 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPERMI2QMasked256load {sym} [off] x y ptr mask mem)
(VPERMI2PDMasked512 x y l:(VMOVDQUload512 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPERMI2PDMasked512load {sym} [off] x y ptr mask mem)
(VPERMI2QMasked512 x y l:(VMOVDQUload512 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPERMI2QMasked512load {sym} [off] x y ptr mask mem)
+(VCVTDQ2PS512 l:(VMOVDQUload512 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VCVTDQ2PS512load {sym} [off] ptr mem)
+(VCVTQQ2PSX128 l:(VMOVDQUload128 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VCVTQQ2PSX128load {sym} [off] ptr mem)
+(VCVTQQ2PSY128 l:(VMOVDQUload256 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VCVTQQ2PSY128load {sym} [off] ptr mem)
+(VCVTQQ2PS256 l:(VMOVDQUload512 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VCVTQQ2PS256load {sym} [off] ptr mem)
+(VCVTUDQ2PS128 l:(VMOVDQUload128 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VCVTUDQ2PS128load {sym} [off] ptr mem)
+(VCVTUDQ2PS256 l:(VMOVDQUload256 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VCVTUDQ2PS256load {sym} [off] ptr mem)
+(VCVTUDQ2PS512 l:(VMOVDQUload512 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VCVTUDQ2PS512load {sym} [off] ptr mem)
+(VCVTUQQ2PSX128 l:(VMOVDQUload128 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VCVTUQQ2PSX128load {sym} [off] ptr mem)
+(VCVTUQQ2PSY128 l:(VMOVDQUload256 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VCVTUQQ2PSY128load {sym} [off] ptr mem)
+(VCVTUQQ2PS256 l:(VMOVDQUload512 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VCVTUQQ2PS256load {sym} [off] ptr mem)
+(VCVTDQ2PSMasked128 l:(VMOVDQUload128 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VCVTDQ2PSMasked128load {sym} [off] ptr mask mem)
+(VCVTDQ2PSMasked256 l:(VMOVDQUload256 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VCVTDQ2PSMasked256load {sym} [off] ptr mask mem)
+(VCVTDQ2PSMasked512 l:(VMOVDQUload512 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VCVTDQ2PSMasked512load {sym} [off] ptr mask mem)
+(VCVTQQ2PSXMasked128 l:(VMOVDQUload128 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VCVTQQ2PSXMasked128load {sym} [off] ptr mask mem)
+(VCVTQQ2PSYMasked128 l:(VMOVDQUload256 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VCVTQQ2PSYMasked128load {sym} [off] ptr mask mem)
+(VCVTQQ2PSMasked256 l:(VMOVDQUload512 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VCVTQQ2PSMasked256load {sym} [off] ptr mask mem)
+(VCVTUDQ2PSMasked128 l:(VMOVDQUload128 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VCVTUDQ2PSMasked128load {sym} [off] ptr mask mem)
+(VCVTUDQ2PSMasked256 l:(VMOVDQUload256 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VCVTUDQ2PSMasked256load {sym} [off] ptr mask mem)
+(VCVTUDQ2PSMasked512 l:(VMOVDQUload512 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VCVTUDQ2PSMasked512load {sym} [off] ptr mask mem)
+(VCVTUQQ2PSXMasked128 l:(VMOVDQUload128 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VCVTUQQ2PSXMasked128load {sym} [off] ptr mask mem)
+(VCVTUQQ2PSYMasked128 l:(VMOVDQUload256 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VCVTUQQ2PSYMasked128load {sym} [off] ptr mask mem)
+(VCVTUQQ2PSMasked256 l:(VMOVDQUload512 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VCVTUQQ2PSMasked256load {sym} [off] ptr mask mem)
+(VCVTDQ2PD512 l:(VMOVDQUload256 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VCVTDQ2PD512load {sym} [off] ptr mem)
+(VCVTQQ2PD128 l:(VMOVDQUload128 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VCVTQQ2PD128load {sym} [off] ptr mem)
+(VCVTQQ2PD256 l:(VMOVDQUload256 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VCVTQQ2PD256load {sym} [off] ptr mem)
+(VCVTQQ2PD512 l:(VMOVDQUload512 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VCVTQQ2PD512load {sym} [off] ptr mem)
+(VCVTUDQ2PD256 l:(VMOVDQUload128 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VCVTUDQ2PD256load {sym} [off] ptr mem)
+(VCVTUDQ2PD512 l:(VMOVDQUload256 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VCVTUDQ2PD512load {sym} [off] ptr mem)
+(VCVTUQQ2PD128 l:(VMOVDQUload128 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VCVTUQQ2PD128load {sym} [off] ptr mem)
+(VCVTUQQ2PD256 l:(VMOVDQUload256 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VCVTUQQ2PD256load {sym} [off] ptr mem)
+(VCVTUQQ2PD512 l:(VMOVDQUload512 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VCVTUQQ2PD512load {sym} [off] ptr mem)
+(VCVTDQ2PDMasked256 l:(VMOVDQUload128 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VCVTDQ2PDMasked256load {sym} [off] ptr mask mem)
+(VCVTDQ2PDMasked512 l:(VMOVDQUload256 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VCVTDQ2PDMasked512load {sym} [off] ptr mask mem)
+(VCVTQQ2PDMasked128 l:(VMOVDQUload128 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VCVTQQ2PDMasked128load {sym} [off] ptr mask mem)
+(VCVTQQ2PDMasked256 l:(VMOVDQUload256 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VCVTQQ2PDMasked256load {sym} [off] ptr mask mem)
+(VCVTQQ2PDMasked512 l:(VMOVDQUload512 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VCVTQQ2PDMasked512load {sym} [off] ptr mask mem)
+(VCVTUDQ2PDMasked256 l:(VMOVDQUload128 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VCVTUDQ2PDMasked256load {sym} [off] ptr mask mem)
+(VCVTUDQ2PDMasked512 l:(VMOVDQUload256 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VCVTUDQ2PDMasked512load {sym} [off] ptr mask mem)
+(VCVTUQQ2PDMasked128 l:(VMOVDQUload128 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VCVTUQQ2PDMasked128load {sym} [off] ptr mask mem)
+(VCVTUQQ2PDMasked256 l:(VMOVDQUload256 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VCVTUQQ2PDMasked256load {sym} [off] ptr mask mem)
+(VCVTUQQ2PDMasked512 l:(VMOVDQUload512 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VCVTUQQ2PDMasked512load {sym} [off] ptr mask mem)
(VCVTTPS2DQ512 l:(VMOVDQUload512 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VCVTTPS2DQ512load {sym} [off] ptr mem)
(VCVTTPD2DQ256 l:(VMOVDQUload512 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VCVTTPD2DQ256load {sym} [off] ptr mem)
(VCVTTPS2DQMasked128 l:(VMOVDQUload128 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VCVTTPS2DQMasked128load {sym} [off] ptr mask mem)
{name: "VCOMPRESSPSMasked128", argLength: 2, reg: wkw, asm: "VCOMPRESSPS", commutative: false, typ: "Vec128", resultInArg0: false},
{name: "VCOMPRESSPSMasked256", argLength: 2, reg: wkw, asm: "VCOMPRESSPS", commutative: false, typ: "Vec256", resultInArg0: false},
{name: "VCOMPRESSPSMasked512", argLength: 2, reg: wkw, asm: "VCOMPRESSPS", commutative: false, typ: "Vec512", resultInArg0: false},
+ {name: "VCVTDQ2PD256", argLength: 1, reg: v11, asm: "VCVTDQ2PD", commutative: false, typ: "Vec256", resultInArg0: false},
+ {name: "VCVTDQ2PD512", argLength: 1, reg: w11, asm: "VCVTDQ2PD", commutative: false, typ: "Vec512", resultInArg0: false},
+ {name: "VCVTDQ2PDMasked256", argLength: 2, reg: wkw, asm: "VCVTDQ2PD", commutative: false, typ: "Vec256", resultInArg0: false},
+ {name: "VCVTDQ2PDMasked512", argLength: 2, reg: wkw, asm: "VCVTDQ2PD", commutative: false, typ: "Vec512", resultInArg0: false},
+ {name: "VCVTDQ2PS128", argLength: 1, reg: v11, asm: "VCVTDQ2PS", commutative: false, typ: "Vec128", resultInArg0: false},
+ {name: "VCVTDQ2PS256", argLength: 1, reg: v11, asm: "VCVTDQ2PS", commutative: false, typ: "Vec256", resultInArg0: false},
+ {name: "VCVTDQ2PS512", argLength: 1, reg: w11, asm: "VCVTDQ2PS", commutative: false, typ: "Vec512", resultInArg0: false},
+ {name: "VCVTDQ2PSMasked128", argLength: 2, reg: wkw, asm: "VCVTDQ2PS", commutative: false, typ: "Vec128", resultInArg0: false},
+ {name: "VCVTDQ2PSMasked256", argLength: 2, reg: wkw, asm: "VCVTDQ2PS", commutative: false, typ: "Vec256", resultInArg0: false},
+ {name: "VCVTDQ2PSMasked512", argLength: 2, reg: wkw, asm: "VCVTDQ2PS", commutative: false, typ: "Vec512", resultInArg0: false},
+ {name: "VCVTQQ2PD128", argLength: 1, reg: w11, asm: "VCVTQQ2PD", commutative: false, typ: "Vec128", resultInArg0: false},
+ {name: "VCVTQQ2PD256", argLength: 1, reg: w11, asm: "VCVTQQ2PD", commutative: false, typ: "Vec256", resultInArg0: false},
+ {name: "VCVTQQ2PD512", argLength: 1, reg: w11, asm: "VCVTQQ2PD", commutative: false, typ: "Vec512", resultInArg0: false},
+ {name: "VCVTQQ2PDMasked128", argLength: 2, reg: wkw, asm: "VCVTQQ2PD", commutative: false, typ: "Vec128", resultInArg0: false},
+ {name: "VCVTQQ2PDMasked256", argLength: 2, reg: wkw, asm: "VCVTQQ2PD", commutative: false, typ: "Vec256", resultInArg0: false},
+ {name: "VCVTQQ2PDMasked512", argLength: 2, reg: wkw, asm: "VCVTQQ2PD", commutative: false, typ: "Vec512", resultInArg0: false},
+ {name: "VCVTQQ2PS256", argLength: 1, reg: w11, asm: "VCVTQQ2PS", commutative: false, typ: "Vec256", resultInArg0: false},
+ {name: "VCVTQQ2PSMasked256", argLength: 2, reg: wkw, asm: "VCVTQQ2PS", commutative: false, typ: "Vec256", resultInArg0: false},
+ {name: "VCVTQQ2PSX128", argLength: 1, reg: w11, asm: "VCVTQQ2PSX", commutative: false, typ: "Vec128", resultInArg0: false},
+ {name: "VCVTQQ2PSXMasked128", argLength: 2, reg: wkw, asm: "VCVTQQ2PSX", commutative: false, typ: "Vec128", resultInArg0: false},
+ {name: "VCVTQQ2PSY128", argLength: 1, reg: w11, asm: "VCVTQQ2PSY", commutative: false, typ: "Vec128", resultInArg0: false},
+ {name: "VCVTQQ2PSYMasked128", argLength: 2, reg: wkw, asm: "VCVTQQ2PSY", commutative: false, typ: "Vec128", resultInArg0: false},
{name: "VCVTTPD2DQ256", argLength: 1, reg: w11, asm: "VCVTTPD2DQ", commutative: false, typ: "Vec256", resultInArg0: false},
{name: "VCVTTPD2DQMasked256", argLength: 2, reg: wkw, asm: "VCVTTPD2DQ", commutative: false, typ: "Vec256", resultInArg0: false},
{name: "VCVTTPD2DQX128", argLength: 1, reg: v11, asm: "VCVTTPD2DQX", commutative: false, typ: "Vec128", resultInArg0: false},
{name: "VCVTTPS2UQQ512", argLength: 1, reg: w11, asm: "VCVTTPS2UQQ", commutative: false, typ: "Vec512", resultInArg0: false},
{name: "VCVTTPS2UQQMasked256", argLength: 2, reg: wkw, asm: "VCVTTPS2UQQ", commutative: false, typ: "Vec256", resultInArg0: false},
{name: "VCVTTPS2UQQMasked512", argLength: 2, reg: wkw, asm: "VCVTTPS2UQQ", commutative: false, typ: "Vec512", resultInArg0: false},
+ {name: "VCVTUDQ2PD256", argLength: 1, reg: w11, asm: "VCVTUDQ2PD", commutative: false, typ: "Vec256", resultInArg0: false},
+ {name: "VCVTUDQ2PD512", argLength: 1, reg: w11, asm: "VCVTUDQ2PD", commutative: false, typ: "Vec512", resultInArg0: false},
+ {name: "VCVTUDQ2PDMasked256", argLength: 2, reg: wkw, asm: "VCVTUDQ2PD", commutative: false, typ: "Vec256", resultInArg0: false},
+ {name: "VCVTUDQ2PDMasked512", argLength: 2, reg: wkw, asm: "VCVTUDQ2PD", commutative: false, typ: "Vec512", resultInArg0: false},
+ {name: "VCVTUDQ2PS128", argLength: 1, reg: w11, asm: "VCVTUDQ2PS", commutative: false, typ: "Vec128", resultInArg0: false},
+ {name: "VCVTUDQ2PS256", argLength: 1, reg: w11, asm: "VCVTUDQ2PS", commutative: false, typ: "Vec256", resultInArg0: false},
+ {name: "VCVTUDQ2PS512", argLength: 1, reg: w11, asm: "VCVTUDQ2PS", commutative: false, typ: "Vec512", resultInArg0: false},
+ {name: "VCVTUDQ2PSMasked128", argLength: 2, reg: wkw, asm: "VCVTUDQ2PS", commutative: false, typ: "Vec128", resultInArg0: false},
+ {name: "VCVTUDQ2PSMasked256", argLength: 2, reg: wkw, asm: "VCVTUDQ2PS", commutative: false, typ: "Vec256", resultInArg0: false},
+ {name: "VCVTUDQ2PSMasked512", argLength: 2, reg: wkw, asm: "VCVTUDQ2PS", commutative: false, typ: "Vec512", resultInArg0: false},
+ {name: "VCVTUQQ2PD128", argLength: 1, reg: w11, asm: "VCVTUQQ2PD", commutative: false, typ: "Vec128", resultInArg0: false},
+ {name: "VCVTUQQ2PD256", argLength: 1, reg: w11, asm: "VCVTUQQ2PD", commutative: false, typ: "Vec256", resultInArg0: false},
+ {name: "VCVTUQQ2PD512", argLength: 1, reg: w11, asm: "VCVTUQQ2PD", commutative: false, typ: "Vec512", resultInArg0: false},
+ {name: "VCVTUQQ2PDMasked128", argLength: 2, reg: wkw, asm: "VCVTUQQ2PD", commutative: false, typ: "Vec128", resultInArg0: false},
+ {name: "VCVTUQQ2PDMasked256", argLength: 2, reg: wkw, asm: "VCVTUQQ2PD", commutative: false, typ: "Vec256", resultInArg0: false},
+ {name: "VCVTUQQ2PDMasked512", argLength: 2, reg: wkw, asm: "VCVTUQQ2PD", commutative: false, typ: "Vec512", resultInArg0: false},
+ {name: "VCVTUQQ2PS256", argLength: 1, reg: w11, asm: "VCVTUQQ2PS", commutative: false, typ: "Vec256", resultInArg0: false},
+ {name: "VCVTUQQ2PSMasked256", argLength: 2, reg: wkw, asm: "VCVTUQQ2PS", commutative: false, typ: "Vec256", resultInArg0: false},
+ {name: "VCVTUQQ2PSX128", argLength: 1, reg: w11, asm: "VCVTUQQ2PSX", commutative: false, typ: "Vec128", resultInArg0: false},
+ {name: "VCVTUQQ2PSXMasked128", argLength: 2, reg: wkw, asm: "VCVTUQQ2PSX", commutative: false, typ: "Vec128", resultInArg0: false},
+ {name: "VCVTUQQ2PSY128", argLength: 1, reg: w11, asm: "VCVTUQQ2PSY", commutative: false, typ: "Vec128", resultInArg0: false},
+ {name: "VCVTUQQ2PSYMasked128", argLength: 2, reg: wkw, asm: "VCVTUQQ2PSY", commutative: false, typ: "Vec128", resultInArg0: false},
{name: "VDIVPD128", argLength: 2, reg: v21, asm: "VDIVPD", commutative: false, typ: "Vec128", resultInArg0: false},
{name: "VDIVPD256", argLength: 2, reg: v21, asm: "VDIVPD", commutative: false, typ: "Vec256", resultInArg0: false},
{name: "VDIVPD512", argLength: 2, reg: w21, asm: "VDIVPD", commutative: false, typ: "Vec512", resultInArg0: false},
{name: "VADDPSMasked128load", argLength: 4, reg: w2kwload, asm: "VADDPS", commutative: false, typ: "Vec128", aux: "SymOff", symEffect: "Read", resultInArg0: false},
{name: "VADDPSMasked256load", argLength: 4, reg: w2kwload, asm: "VADDPS", commutative: false, typ: "Vec256", aux: "SymOff", symEffect: "Read", resultInArg0: false},
{name: "VADDPSMasked512load", argLength: 4, reg: w2kwload, asm: "VADDPS", commutative: false, typ: "Vec512", aux: "SymOff", symEffect: "Read", resultInArg0: false},
+ {name: "VCVTDQ2PD512load", argLength: 2, reg: w11load, asm: "VCVTDQ2PD", commutative: false, typ: "Vec512", aux: "SymOff", symEffect: "Read", resultInArg0: false},
+ {name: "VCVTDQ2PDMasked256load", argLength: 3, reg: wkwload, asm: "VCVTDQ2PD", commutative: false, typ: "Vec256", aux: "SymOff", symEffect: "Read", resultInArg0: false},
+ {name: "VCVTDQ2PDMasked512load", argLength: 3, reg: wkwload, asm: "VCVTDQ2PD", commutative: false, typ: "Vec512", aux: "SymOff", symEffect: "Read", resultInArg0: false},
+ {name: "VCVTDQ2PS512load", argLength: 2, reg: w11load, asm: "VCVTDQ2PS", commutative: false, typ: "Vec512", aux: "SymOff", symEffect: "Read", resultInArg0: false},
+ {name: "VCVTDQ2PSMasked128load", argLength: 3, reg: wkwload, asm: "VCVTDQ2PS", commutative: false, typ: "Vec128", aux: "SymOff", symEffect: "Read", resultInArg0: false},
+ {name: "VCVTDQ2PSMasked256load", argLength: 3, reg: wkwload, asm: "VCVTDQ2PS", commutative: false, typ: "Vec256", aux: "SymOff", symEffect: "Read", resultInArg0: false},
+ {name: "VCVTDQ2PSMasked512load", argLength: 3, reg: wkwload, asm: "VCVTDQ2PS", commutative: false, typ: "Vec512", aux: "SymOff", symEffect: "Read", resultInArg0: false},
+ {name: "VCVTQQ2PD128load", argLength: 2, reg: w11load, asm: "VCVTQQ2PD", commutative: false, typ: "Vec128", aux: "SymOff", symEffect: "Read", resultInArg0: false},
+ {name: "VCVTQQ2PD256load", argLength: 2, reg: w11load, asm: "VCVTQQ2PD", commutative: false, typ: "Vec256", aux: "SymOff", symEffect: "Read", resultInArg0: false},
+ {name: "VCVTQQ2PD512load", argLength: 2, reg: w11load, asm: "VCVTQQ2PD", commutative: false, typ: "Vec512", aux: "SymOff", symEffect: "Read", resultInArg0: false},
+ {name: "VCVTQQ2PDMasked128load", argLength: 3, reg: wkwload, asm: "VCVTQQ2PD", commutative: false, typ: "Vec128", aux: "SymOff", symEffect: "Read", resultInArg0: false},
+ {name: "VCVTQQ2PDMasked256load", argLength: 3, reg: wkwload, asm: "VCVTQQ2PD", commutative: false, typ: "Vec256", aux: "SymOff", symEffect: "Read", resultInArg0: false},
+ {name: "VCVTQQ2PDMasked512load", argLength: 3, reg: wkwload, asm: "VCVTQQ2PD", commutative: false, typ: "Vec512", aux: "SymOff", symEffect: "Read", resultInArg0: false},
+ {name: "VCVTQQ2PS256load", argLength: 2, reg: w11load, asm: "VCVTQQ2PS", commutative: false, typ: "Vec256", aux: "SymOff", symEffect: "Read", resultInArg0: false},
+ {name: "VCVTQQ2PSMasked256load", argLength: 3, reg: wkwload, asm: "VCVTQQ2PS", commutative: false, typ: "Vec256", aux: "SymOff", symEffect: "Read", resultInArg0: false},
+ {name: "VCVTQQ2PSX128load", argLength: 2, reg: w11load, asm: "VCVTQQ2PSX", commutative: false, typ: "Vec128", aux: "SymOff", symEffect: "Read", resultInArg0: false},
+ {name: "VCVTQQ2PSXMasked128load", argLength: 3, reg: wkwload, asm: "VCVTQQ2PSX", commutative: false, typ: "Vec128", aux: "SymOff", symEffect: "Read", resultInArg0: false},
+ {name: "VCVTQQ2PSY128load", argLength: 2, reg: w11load, asm: "VCVTQQ2PSY", commutative: false, typ: "Vec128", aux: "SymOff", symEffect: "Read", resultInArg0: false},
+ {name: "VCVTQQ2PSYMasked128load", argLength: 3, reg: wkwload, asm: "VCVTQQ2PSY", commutative: false, typ: "Vec128", aux: "SymOff", symEffect: "Read", resultInArg0: false},
{name: "VCVTTPD2DQ256load", argLength: 2, reg: w11load, asm: "VCVTTPD2DQ", commutative: false, typ: "Vec256", aux: "SymOff", symEffect: "Read", resultInArg0: false},
{name: "VCVTTPD2DQMasked256load", argLength: 3, reg: wkwload, asm: "VCVTTPD2DQ", commutative: false, typ: "Vec256", aux: "SymOff", symEffect: "Read", resultInArg0: false},
{name: "VCVTTPD2DQXMasked128load", argLength: 3, reg: wkwload, asm: "VCVTTPD2DQX", commutative: false, typ: "Vec128", aux: "SymOff", symEffect: "Read", resultInArg0: false},
{name: "VCVTTPS2UQQ512load", argLength: 2, reg: w11load, asm: "VCVTTPS2UQQ", commutative: false, typ: "Vec512", aux: "SymOff", symEffect: "Read", resultInArg0: false},
{name: "VCVTTPS2UQQMasked256load", argLength: 3, reg: wkwload, asm: "VCVTTPS2UQQ", commutative: false, typ: "Vec256", aux: "SymOff", symEffect: "Read", resultInArg0: false},
{name: "VCVTTPS2UQQMasked512load", argLength: 3, reg: wkwload, asm: "VCVTTPS2UQQ", commutative: false, typ: "Vec512", aux: "SymOff", symEffect: "Read", resultInArg0: false},
+ {name: "VCVTUDQ2PD256load", argLength: 2, reg: w11load, asm: "VCVTUDQ2PD", commutative: false, typ: "Vec256", aux: "SymOff", symEffect: "Read", resultInArg0: false},
+ {name: "VCVTUDQ2PD512load", argLength: 2, reg: w11load, asm: "VCVTUDQ2PD", commutative: false, typ: "Vec512", aux: "SymOff", symEffect: "Read", resultInArg0: false},
+ {name: "VCVTUDQ2PDMasked256load", argLength: 3, reg: wkwload, asm: "VCVTUDQ2PD", commutative: false, typ: "Vec256", aux: "SymOff", symEffect: "Read", resultInArg0: false},
+ {name: "VCVTUDQ2PDMasked512load", argLength: 3, reg: wkwload, asm: "VCVTUDQ2PD", commutative: false, typ: "Vec512", aux: "SymOff", symEffect: "Read", resultInArg0: false},
+ {name: "VCVTUDQ2PS128load", argLength: 2, reg: w11load, asm: "VCVTUDQ2PS", commutative: false, typ: "Vec128", aux: "SymOff", symEffect: "Read", resultInArg0: false},
+ {name: "VCVTUDQ2PS256load", argLength: 2, reg: w11load, asm: "VCVTUDQ2PS", commutative: false, typ: "Vec256", aux: "SymOff", symEffect: "Read", resultInArg0: false},
+ {name: "VCVTUDQ2PS512load", argLength: 2, reg: w11load, asm: "VCVTUDQ2PS", commutative: false, typ: "Vec512", aux: "SymOff", symEffect: "Read", resultInArg0: false},
+ {name: "VCVTUDQ2PSMasked128load", argLength: 3, reg: wkwload, asm: "VCVTUDQ2PS", commutative: false, typ: "Vec128", aux: "SymOff", symEffect: "Read", resultInArg0: false},
+ {name: "VCVTUDQ2PSMasked256load", argLength: 3, reg: wkwload, asm: "VCVTUDQ2PS", commutative: false, typ: "Vec256", aux: "SymOff", symEffect: "Read", resultInArg0: false},
+ {name: "VCVTUDQ2PSMasked512load", argLength: 3, reg: wkwload, asm: "VCVTUDQ2PS", commutative: false, typ: "Vec512", aux: "SymOff", symEffect: "Read", resultInArg0: false},
+ {name: "VCVTUQQ2PD128load", argLength: 2, reg: w11load, asm: "VCVTUQQ2PD", commutative: false, typ: "Vec128", aux: "SymOff", symEffect: "Read", resultInArg0: false},
+ {name: "VCVTUQQ2PD256load", argLength: 2, reg: w11load, asm: "VCVTUQQ2PD", commutative: false, typ: "Vec256", aux: "SymOff", symEffect: "Read", resultInArg0: false},
+ {name: "VCVTUQQ2PD512load", argLength: 2, reg: w11load, asm: "VCVTUQQ2PD", commutative: false, typ: "Vec512", aux: "SymOff", symEffect: "Read", resultInArg0: false},
+ {name: "VCVTUQQ2PDMasked128load", argLength: 3, reg: wkwload, asm: "VCVTUQQ2PD", commutative: false, typ: "Vec128", aux: "SymOff", symEffect: "Read", resultInArg0: false},
+ {name: "VCVTUQQ2PDMasked256load", argLength: 3, reg: wkwload, asm: "VCVTUQQ2PD", commutative: false, typ: "Vec256", aux: "SymOff", symEffect: "Read", resultInArg0: false},
+ {name: "VCVTUQQ2PDMasked512load", argLength: 3, reg: wkwload, asm: "VCVTUQQ2PD", commutative: false, typ: "Vec512", aux: "SymOff", symEffect: "Read", resultInArg0: false},
+ {name: "VCVTUQQ2PS256load", argLength: 2, reg: w11load, asm: "VCVTUQQ2PS", commutative: false, typ: "Vec256", aux: "SymOff", symEffect: "Read", resultInArg0: false},
+ {name: "VCVTUQQ2PSMasked256load", argLength: 3, reg: wkwload, asm: "VCVTUQQ2PS", commutative: false, typ: "Vec256", aux: "SymOff", symEffect: "Read", resultInArg0: false},
+ {name: "VCVTUQQ2PSX128load", argLength: 2, reg: w11load, asm: "VCVTUQQ2PSX", commutative: false, typ: "Vec128", aux: "SymOff", symEffect: "Read", resultInArg0: false},
+ {name: "VCVTUQQ2PSXMasked128load", argLength: 3, reg: wkwload, asm: "VCVTUQQ2PSX", commutative: false, typ: "Vec128", aux: "SymOff", symEffect: "Read", resultInArg0: false},
+ {name: "VCVTUQQ2PSY128load", argLength: 2, reg: w11load, asm: "VCVTUQQ2PSY", commutative: false, typ: "Vec128", aux: "SymOff", symEffect: "Read", resultInArg0: false},
+ {name: "VCVTUQQ2PSYMasked128load", argLength: 3, reg: wkwload, asm: "VCVTUQQ2PSY", commutative: false, typ: "Vec128", aux: "SymOff", symEffect: "Read", resultInArg0: false},
{name: "VDIVPD512load", argLength: 3, reg: w21load, asm: "VDIVPD", commutative: false, typ: "Vec512", aux: "SymOff", symEffect: "Read", resultInArg0: false},
{name: "VDIVPDMasked128load", argLength: 4, reg: w2kwload, asm: "VDIVPD", commutative: false, typ: "Vec128", aux: "SymOff", symEffect: "Read", resultInArg0: false},
{name: "VDIVPDMasked256load", argLength: 4, reg: w2kwload, asm: "VDIVPD", commutative: false, typ: "Vec256", aux: "SymOff", symEffect: "Read", resultInArg0: false},
{name: "VBROADCASTSSMasked128Merging", argLength: 3, reg: w2kw, asm: "VBROADCASTSS", commutative: false, typ: "Vec128", resultInArg0: true},
{name: "VBROADCASTSSMasked256Merging", argLength: 3, reg: w2kw, asm: "VBROADCASTSS", commutative: false, typ: "Vec256", resultInArg0: true},
{name: "VBROADCASTSSMasked512Merging", argLength: 3, reg: w2kw, asm: "VBROADCASTSS", commutative: false, typ: "Vec512", resultInArg0: true},
+ {name: "VCVTDQ2PDMasked256Merging", argLength: 3, reg: w2kw, asm: "VCVTDQ2PD", commutative: false, typ: "Vec256", resultInArg0: true},
+ {name: "VCVTDQ2PDMasked512Merging", argLength: 3, reg: w2kw, asm: "VCVTDQ2PD", commutative: false, typ: "Vec512", resultInArg0: true},
+ {name: "VCVTDQ2PSMasked128Merging", argLength: 3, reg: w2kw, asm: "VCVTDQ2PS", commutative: false, typ: "Vec128", resultInArg0: true},
+ {name: "VCVTDQ2PSMasked256Merging", argLength: 3, reg: w2kw, asm: "VCVTDQ2PS", commutative: false, typ: "Vec256", resultInArg0: true},
+ {name: "VCVTDQ2PSMasked512Merging", argLength: 3, reg: w2kw, asm: "VCVTDQ2PS", commutative: false, typ: "Vec512", resultInArg0: true},
+ {name: "VCVTQQ2PDMasked128Merging", argLength: 3, reg: w2kw, asm: "VCVTQQ2PD", commutative: false, typ: "Vec128", resultInArg0: true},
+ {name: "VCVTQQ2PDMasked256Merging", argLength: 3, reg: w2kw, asm: "VCVTQQ2PD", commutative: false, typ: "Vec256", resultInArg0: true},
+ {name: "VCVTQQ2PDMasked512Merging", argLength: 3, reg: w2kw, asm: "VCVTQQ2PD", commutative: false, typ: "Vec512", resultInArg0: true},
+ {name: "VCVTQQ2PSMasked256Merging", argLength: 3, reg: w2kw, asm: "VCVTQQ2PS", commutative: false, typ: "Vec256", resultInArg0: true},
+ {name: "VCVTQQ2PSXMasked128Merging", argLength: 3, reg: w2kw, asm: "VCVTQQ2PSX", commutative: false, typ: "Vec128", resultInArg0: true},
+ {name: "VCVTQQ2PSYMasked128Merging", argLength: 3, reg: w2kw, asm: "VCVTQQ2PSY", commutative: false, typ: "Vec128", resultInArg0: true},
{name: "VCVTTPD2DQMasked256Merging", argLength: 3, reg: w2kw, asm: "VCVTTPD2DQ", commutative: false, typ: "Vec256", resultInArg0: true},
{name: "VCVTTPD2DQXMasked128Merging", argLength: 3, reg: w2kw, asm: "VCVTTPD2DQX", commutative: false, typ: "Vec128", resultInArg0: true},
{name: "VCVTTPD2DQYMasked128Merging", argLength: 3, reg: w2kw, asm: "VCVTTPD2DQY", commutative: false, typ: "Vec128", resultInArg0: true},
{name: "VCVTTPS2UDQMasked512Merging", argLength: 3, reg: w2kw, asm: "VCVTTPS2UDQ", commutative: false, typ: "Vec512", resultInArg0: true},
{name: "VCVTTPS2UQQMasked256Merging", argLength: 3, reg: w2kw, asm: "VCVTTPS2UQQ", commutative: false, typ: "Vec256", resultInArg0: true},
{name: "VCVTTPS2UQQMasked512Merging", argLength: 3, reg: w2kw, asm: "VCVTTPS2UQQ", commutative: false, typ: "Vec512", resultInArg0: true},
+ {name: "VCVTUDQ2PDMasked256Merging", argLength: 3, reg: w2kw, asm: "VCVTUDQ2PD", commutative: false, typ: "Vec256", resultInArg0: true},
+ {name: "VCVTUDQ2PDMasked512Merging", argLength: 3, reg: w2kw, asm: "VCVTUDQ2PD", commutative: false, typ: "Vec512", resultInArg0: true},
+ {name: "VCVTUDQ2PSMasked128Merging", argLength: 3, reg: w2kw, asm: "VCVTUDQ2PS", commutative: false, typ: "Vec128", resultInArg0: true},
+ {name: "VCVTUDQ2PSMasked256Merging", argLength: 3, reg: w2kw, asm: "VCVTUDQ2PS", commutative: false, typ: "Vec256", resultInArg0: true},
+ {name: "VCVTUDQ2PSMasked512Merging", argLength: 3, reg: w2kw, asm: "VCVTUDQ2PS", commutative: false, typ: "Vec512", resultInArg0: true},
+ {name: "VCVTUQQ2PDMasked128Merging", argLength: 3, reg: w2kw, asm: "VCVTUQQ2PD", commutative: false, typ: "Vec128", resultInArg0: true},
+ {name: "VCVTUQQ2PDMasked256Merging", argLength: 3, reg: w2kw, asm: "VCVTUQQ2PD", commutative: false, typ: "Vec256", resultInArg0: true},
+ {name: "VCVTUQQ2PDMasked512Merging", argLength: 3, reg: w2kw, asm: "VCVTUQQ2PD", commutative: false, typ: "Vec512", resultInArg0: true},
+ {name: "VCVTUQQ2PSMasked256Merging", argLength: 3, reg: w2kw, asm: "VCVTUQQ2PS", commutative: false, typ: "Vec256", resultInArg0: true},
+ {name: "VCVTUQQ2PSXMasked128Merging", argLength: 3, reg: w2kw, asm: "VCVTUQQ2PSX", commutative: false, typ: "Vec128", resultInArg0: true},
+ {name: "VCVTUQQ2PSYMasked128Merging", argLength: 3, reg: w2kw, asm: "VCVTUQQ2PSY", commutative: false, typ: "Vec128", resultInArg0: true},
{name: "VDIVPDMasked128Merging", argLength: 4, reg: w3kw, asm: "VDIVPD", commutative: false, typ: "Vec128", resultInArg0: true},
{name: "VDIVPDMasked256Merging", argLength: 4, reg: w3kw, asm: "VDIVPD", commutative: false, typ: "Vec256", resultInArg0: true},
{name: "VDIVPDMasked512Merging", argLength: 4, reg: w3kw, asm: "VDIVPD", commutative: false, typ: "Vec512", resultInArg0: true},
{name: "ConcatPermuteUint64x2", argLength: 3, commutative: false},
{name: "ConcatPermuteUint64x4", argLength: 3, commutative: false},
{name: "ConcatPermuteUint64x8", argLength: 3, commutative: false},
+ {name: "ConvertToFloat32Int32x4", argLength: 1, commutative: false},
+ {name: "ConvertToFloat32Int32x8", argLength: 1, commutative: false},
+ {name: "ConvertToFloat32Int32x16", argLength: 1, commutative: false},
+ {name: "ConvertToFloat32Int64x2", argLength: 1, commutative: false},
+ {name: "ConvertToFloat32Int64x4", argLength: 1, commutative: false},
+ {name: "ConvertToFloat32Int64x8", argLength: 1, commutative: false},
+ {name: "ConvertToFloat32Uint32x4", argLength: 1, commutative: false},
+ {name: "ConvertToFloat32Uint32x8", argLength: 1, commutative: false},
+ {name: "ConvertToFloat32Uint32x16", argLength: 1, commutative: false},
+ {name: "ConvertToFloat32Uint64x2", argLength: 1, commutative: false},
+ {name: "ConvertToFloat32Uint64x4", argLength: 1, commutative: false},
+ {name: "ConvertToFloat32Uint64x8", argLength: 1, commutative: false},
+ {name: "ConvertToFloat64Int32x4", argLength: 1, commutative: false},
+ {name: "ConvertToFloat64Int32x8", argLength: 1, commutative: false},
+ {name: "ConvertToFloat64Int64x2", argLength: 1, commutative: false},
+ {name: "ConvertToFloat64Int64x4", argLength: 1, commutative: false},
+ {name: "ConvertToFloat64Int64x8", argLength: 1, commutative: false},
+ {name: "ConvertToFloat64Uint32x4", argLength: 1, commutative: false},
+ {name: "ConvertToFloat64Uint32x8", argLength: 1, commutative: false},
+ {name: "ConvertToFloat64Uint64x2", argLength: 1, commutative: false},
+ {name: "ConvertToFloat64Uint64x4", argLength: 1, commutative: false},
+ {name: "ConvertToFloat64Uint64x8", argLength: 1, commutative: false},
{name: "ConvertToInt32Float32x4", argLength: 1, commutative: false},
{name: "ConvertToInt32Float32x8", argLength: 1, commutative: false},
{name: "ConvertToInt32Float32x16", argLength: 1, commutative: false},
OpAMD64VCOMPRESSPSMasked128
OpAMD64VCOMPRESSPSMasked256
OpAMD64VCOMPRESSPSMasked512
+ OpAMD64VCVTDQ2PD256
+ OpAMD64VCVTDQ2PD512
+ OpAMD64VCVTDQ2PDMasked256
+ OpAMD64VCVTDQ2PDMasked512
+ OpAMD64VCVTDQ2PS128
+ OpAMD64VCVTDQ2PS256
+ OpAMD64VCVTDQ2PS512
+ OpAMD64VCVTDQ2PSMasked128
+ OpAMD64VCVTDQ2PSMasked256
+ OpAMD64VCVTDQ2PSMasked512
+ OpAMD64VCVTQQ2PD128
+ OpAMD64VCVTQQ2PD256
+ OpAMD64VCVTQQ2PD512
+ OpAMD64VCVTQQ2PDMasked128
+ OpAMD64VCVTQQ2PDMasked256
+ OpAMD64VCVTQQ2PDMasked512
+ OpAMD64VCVTQQ2PS256
+ OpAMD64VCVTQQ2PSMasked256
+ OpAMD64VCVTQQ2PSX128
+ OpAMD64VCVTQQ2PSXMasked128
+ OpAMD64VCVTQQ2PSY128
+ OpAMD64VCVTQQ2PSYMasked128
OpAMD64VCVTTPD2DQ256
OpAMD64VCVTTPD2DQMasked256
OpAMD64VCVTTPD2DQX128
OpAMD64VCVTTPS2UQQ512
OpAMD64VCVTTPS2UQQMasked256
OpAMD64VCVTTPS2UQQMasked512
+ OpAMD64VCVTUDQ2PD256
+ OpAMD64VCVTUDQ2PD512
+ OpAMD64VCVTUDQ2PDMasked256
+ OpAMD64VCVTUDQ2PDMasked512
+ OpAMD64VCVTUDQ2PS128
+ OpAMD64VCVTUDQ2PS256
+ OpAMD64VCVTUDQ2PS512
+ OpAMD64VCVTUDQ2PSMasked128
+ OpAMD64VCVTUDQ2PSMasked256
+ OpAMD64VCVTUDQ2PSMasked512
+ OpAMD64VCVTUQQ2PD128
+ OpAMD64VCVTUQQ2PD256
+ OpAMD64VCVTUQQ2PD512
+ OpAMD64VCVTUQQ2PDMasked128
+ OpAMD64VCVTUQQ2PDMasked256
+ OpAMD64VCVTUQQ2PDMasked512
+ OpAMD64VCVTUQQ2PS256
+ OpAMD64VCVTUQQ2PSMasked256
+ OpAMD64VCVTUQQ2PSX128
+ OpAMD64VCVTUQQ2PSXMasked128
+ OpAMD64VCVTUQQ2PSY128
+ OpAMD64VCVTUQQ2PSYMasked128
OpAMD64VDIVPD128
OpAMD64VDIVPD256
OpAMD64VDIVPD512
OpAMD64VADDPSMasked128load
OpAMD64VADDPSMasked256load
OpAMD64VADDPSMasked512load
+ OpAMD64VCVTDQ2PD512load
+ OpAMD64VCVTDQ2PDMasked256load
+ OpAMD64VCVTDQ2PDMasked512load
+ OpAMD64VCVTDQ2PS512load
+ OpAMD64VCVTDQ2PSMasked128load
+ OpAMD64VCVTDQ2PSMasked256load
+ OpAMD64VCVTDQ2PSMasked512load
+ OpAMD64VCVTQQ2PD128load
+ OpAMD64VCVTQQ2PD256load
+ OpAMD64VCVTQQ2PD512load
+ OpAMD64VCVTQQ2PDMasked128load
+ OpAMD64VCVTQQ2PDMasked256load
+ OpAMD64VCVTQQ2PDMasked512load
+ OpAMD64VCVTQQ2PS256load
+ OpAMD64VCVTQQ2PSMasked256load
+ OpAMD64VCVTQQ2PSX128load
+ OpAMD64VCVTQQ2PSXMasked128load
+ OpAMD64VCVTQQ2PSY128load
+ OpAMD64VCVTQQ2PSYMasked128load
OpAMD64VCVTTPD2DQ256load
OpAMD64VCVTTPD2DQMasked256load
OpAMD64VCVTTPD2DQXMasked128load
OpAMD64VCVTTPS2UQQ512load
OpAMD64VCVTTPS2UQQMasked256load
OpAMD64VCVTTPS2UQQMasked512load
+ OpAMD64VCVTUDQ2PD256load
+ OpAMD64VCVTUDQ2PD512load
+ OpAMD64VCVTUDQ2PDMasked256load
+ OpAMD64VCVTUDQ2PDMasked512load
+ OpAMD64VCVTUDQ2PS128load
+ OpAMD64VCVTUDQ2PS256load
+ OpAMD64VCVTUDQ2PS512load
+ OpAMD64VCVTUDQ2PSMasked128load
+ OpAMD64VCVTUDQ2PSMasked256load
+ OpAMD64VCVTUDQ2PSMasked512load
+ OpAMD64VCVTUQQ2PD128load
+ OpAMD64VCVTUQQ2PD256load
+ OpAMD64VCVTUQQ2PD512load
+ OpAMD64VCVTUQQ2PDMasked128load
+ OpAMD64VCVTUQQ2PDMasked256load
+ OpAMD64VCVTUQQ2PDMasked512load
+ OpAMD64VCVTUQQ2PS256load
+ OpAMD64VCVTUQQ2PSMasked256load
+ OpAMD64VCVTUQQ2PSX128load
+ OpAMD64VCVTUQQ2PSXMasked128load
+ OpAMD64VCVTUQQ2PSY128load
+ OpAMD64VCVTUQQ2PSYMasked128load
OpAMD64VDIVPD512load
OpAMD64VDIVPDMasked128load
OpAMD64VDIVPDMasked256load
OpAMD64VBROADCASTSSMasked128Merging
OpAMD64VBROADCASTSSMasked256Merging
OpAMD64VBROADCASTSSMasked512Merging
+ OpAMD64VCVTDQ2PDMasked256Merging
+ OpAMD64VCVTDQ2PDMasked512Merging
+ OpAMD64VCVTDQ2PSMasked128Merging
+ OpAMD64VCVTDQ2PSMasked256Merging
+ OpAMD64VCVTDQ2PSMasked512Merging
+ OpAMD64VCVTQQ2PDMasked128Merging
+ OpAMD64VCVTQQ2PDMasked256Merging
+ OpAMD64VCVTQQ2PDMasked512Merging
+ OpAMD64VCVTQQ2PSMasked256Merging
+ OpAMD64VCVTQQ2PSXMasked128Merging
+ OpAMD64VCVTQQ2PSYMasked128Merging
OpAMD64VCVTTPD2DQMasked256Merging
OpAMD64VCVTTPD2DQXMasked128Merging
OpAMD64VCVTTPD2DQYMasked128Merging
OpAMD64VCVTTPS2UDQMasked512Merging
OpAMD64VCVTTPS2UQQMasked256Merging
OpAMD64VCVTTPS2UQQMasked512Merging
+ OpAMD64VCVTUDQ2PDMasked256Merging
+ OpAMD64VCVTUDQ2PDMasked512Merging
+ OpAMD64VCVTUDQ2PSMasked128Merging
+ OpAMD64VCVTUDQ2PSMasked256Merging
+ OpAMD64VCVTUDQ2PSMasked512Merging
+ OpAMD64VCVTUQQ2PDMasked128Merging
+ OpAMD64VCVTUQQ2PDMasked256Merging
+ OpAMD64VCVTUQQ2PDMasked512Merging
+ OpAMD64VCVTUQQ2PSMasked256Merging
+ OpAMD64VCVTUQQ2PSXMasked128Merging
+ OpAMD64VCVTUQQ2PSYMasked128Merging
OpAMD64VDIVPDMasked128Merging
OpAMD64VDIVPDMasked256Merging
OpAMD64VDIVPDMasked512Merging
OpConcatPermuteUint64x2
OpConcatPermuteUint64x4
OpConcatPermuteUint64x8
+ OpConvertToFloat32Int32x4
+ OpConvertToFloat32Int32x8
+ OpConvertToFloat32Int32x16
+ OpConvertToFloat32Int64x2
+ OpConvertToFloat32Int64x4
+ OpConvertToFloat32Int64x8
+ OpConvertToFloat32Uint32x4
+ OpConvertToFloat32Uint32x8
+ OpConvertToFloat32Uint32x16
+ OpConvertToFloat32Uint64x2
+ OpConvertToFloat32Uint64x4
+ OpConvertToFloat32Uint64x8
+ OpConvertToFloat64Int32x4
+ OpConvertToFloat64Int32x8
+ OpConvertToFloat64Int64x2
+ OpConvertToFloat64Int64x4
+ OpConvertToFloat64Int64x8
+ OpConvertToFloat64Uint32x4
+ OpConvertToFloat64Uint32x8
+ OpConvertToFloat64Uint64x2
+ OpConvertToFloat64Uint64x4
+ OpConvertToFloat64Uint64x8
OpConvertToInt32Float32x4
OpConvertToInt32Float32x8
OpConvertToInt32Float32x16
},
},
},
+ {
+ name: "VCVTDQ2PD256",
+ argLen: 1,
+ asm: x86.AVCVTDQ2PD,
+ reg: regInfo{
+ inputs: []inputInfo{
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ },
+ outputs: []outputInfo{
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ },
+ },
+ },
+ {
+ name: "VCVTDQ2PD512",
+ argLen: 1,
+ asm: x86.AVCVTDQ2PD,
+ reg: regInfo{
+ inputs: []inputInfo{
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ },
+ outputs: []outputInfo{
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ },
+ },
+ },
+ {
+ name: "VCVTDQ2PDMasked256",
+ argLen: 2,
+ asm: x86.AVCVTDQ2PD,
+ reg: regInfo{
+ inputs: []inputInfo{
+ {1, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+ {0, 281474976645120}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ },
+ outputs: []outputInfo{
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ },
+ },
+ },
+ {
+ name: "VCVTDQ2PDMasked512",
+ argLen: 2,
+ asm: x86.AVCVTDQ2PD,
+ reg: regInfo{
+ inputs: []inputInfo{
+ {1, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+ {0, 281474976645120}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ },
+ outputs: []outputInfo{
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ },
+ },
+ },
+ {
+ name: "VCVTDQ2PS128",
+ argLen: 1,
+ asm: x86.AVCVTDQ2PS,
+ reg: regInfo{
+ inputs: []inputInfo{
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ },
+ outputs: []outputInfo{
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ },
+ },
+ },
+ {
+ name: "VCVTDQ2PS256",
+ argLen: 1,
+ asm: x86.AVCVTDQ2PS,
+ reg: regInfo{
+ inputs: []inputInfo{
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ },
+ outputs: []outputInfo{
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ },
+ },
+ },
+ {
+ name: "VCVTDQ2PS512",
+ argLen: 1,
+ asm: x86.AVCVTDQ2PS,
+ reg: regInfo{
+ inputs: []inputInfo{
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ },
+ outputs: []outputInfo{
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ },
+ },
+ },
+ {
+ name: "VCVTDQ2PSMasked128",
+ argLen: 2,
+ asm: x86.AVCVTDQ2PS,
+ reg: regInfo{
+ inputs: []inputInfo{
+ {1, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+ {0, 281474976645120}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ },
+ outputs: []outputInfo{
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ },
+ },
+ },
+ {
+ name: "VCVTDQ2PSMasked256",
+ argLen: 2,
+ asm: x86.AVCVTDQ2PS,
+ reg: regInfo{
+ inputs: []inputInfo{
+ {1, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+ {0, 281474976645120}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ },
+ outputs: []outputInfo{
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ },
+ },
+ },
+ {
+ name: "VCVTDQ2PSMasked512",
+ argLen: 2,
+ asm: x86.AVCVTDQ2PS,
+ reg: regInfo{
+ inputs: []inputInfo{
+ {1, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+ {0, 281474976645120}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ },
+ outputs: []outputInfo{
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ },
+ },
+ },
+ {
+ name: "VCVTQQ2PD128",
+ argLen: 1,
+ asm: x86.AVCVTQQ2PD,
+ reg: regInfo{
+ inputs: []inputInfo{
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ },
+ outputs: []outputInfo{
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ },
+ },
+ },
+ {
+ name: "VCVTQQ2PD256",
+ argLen: 1,
+ asm: x86.AVCVTQQ2PD,
+ reg: regInfo{
+ inputs: []inputInfo{
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ },
+ outputs: []outputInfo{
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ },
+ },
+ },
+ {
+ name: "VCVTQQ2PD512",
+ argLen: 1,
+ asm: x86.AVCVTQQ2PD,
+ reg: regInfo{
+ inputs: []inputInfo{
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ },
+ outputs: []outputInfo{
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ },
+ },
+ },
+ {
+ name: "VCVTQQ2PDMasked128",
+ argLen: 2,
+ asm: x86.AVCVTQQ2PD,
+ reg: regInfo{
+ inputs: []inputInfo{
+ {1, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+ {0, 281474976645120}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ },
+ outputs: []outputInfo{
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ },
+ },
+ },
+ {
+ name: "VCVTQQ2PDMasked256",
+ argLen: 2,
+ asm: x86.AVCVTQQ2PD,
+ reg: regInfo{
+ inputs: []inputInfo{
+ {1, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+ {0, 281474976645120}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ },
+ outputs: []outputInfo{
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ },
+ },
+ },
+ {
+ name: "VCVTQQ2PDMasked512",
+ argLen: 2,
+ asm: x86.AVCVTQQ2PD,
+ reg: regInfo{
+ inputs: []inputInfo{
+ {1, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+ {0, 281474976645120}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ },
+ outputs: []outputInfo{
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ },
+ },
+ },
+ {
+ name: "VCVTQQ2PS256",
+ argLen: 1,
+ asm: x86.AVCVTQQ2PS,
+ reg: regInfo{
+ inputs: []inputInfo{
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ },
+ outputs: []outputInfo{
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ },
+ },
+ },
+ {
+ name: "VCVTQQ2PSMasked256",
+ argLen: 2,
+ asm: x86.AVCVTQQ2PS,
+ reg: regInfo{
+ inputs: []inputInfo{
+ {1, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+ {0, 281474976645120}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ },
+ outputs: []outputInfo{
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ },
+ },
+ },
+ {
+ name: "VCVTQQ2PSX128",
+ argLen: 1,
+ asm: x86.AVCVTQQ2PSX,
+ reg: regInfo{
+ inputs: []inputInfo{
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ },
+ outputs: []outputInfo{
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ },
+ },
+ },
+ {
+ name: "VCVTQQ2PSXMasked128",
+ argLen: 2,
+ asm: x86.AVCVTQQ2PSX,
+ reg: regInfo{
+ inputs: []inputInfo{
+ {1, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+ {0, 281474976645120}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ },
+ outputs: []outputInfo{
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ },
+ },
+ },
+ {
+ name: "VCVTQQ2PSY128",
+ argLen: 1,
+ asm: x86.AVCVTQQ2PSY,
+ reg: regInfo{
+ inputs: []inputInfo{
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ },
+ outputs: []outputInfo{
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ },
+ },
+ },
+ {
+ name: "VCVTQQ2PSYMasked128",
+ argLen: 2,
+ asm: x86.AVCVTQQ2PSY,
+ reg: regInfo{
+ inputs: []inputInfo{
+ {1, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+ {0, 281474976645120}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ },
+ outputs: []outputInfo{
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ },
+ },
+ },
{
name: "VCVTTPD2DQ256",
argLen: 1,
},
},
},
+ {
+ name: "VCVTUDQ2PD256",
+ argLen: 1,
+ asm: x86.AVCVTUDQ2PD,
+ reg: regInfo{
+ inputs: []inputInfo{
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ },
+ outputs: []outputInfo{
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ },
+ },
+ },
+ {
+ name: "VCVTUDQ2PD512",
+ argLen: 1,
+ asm: x86.AVCVTUDQ2PD,
+ reg: regInfo{
+ inputs: []inputInfo{
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ },
+ outputs: []outputInfo{
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ },
+ },
+ },
+ {
+ name: "VCVTUDQ2PDMasked256",
+ argLen: 2,
+ asm: x86.AVCVTUDQ2PD,
+ reg: regInfo{
+ inputs: []inputInfo{
+ {1, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+ {0, 281474976645120}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ },
+ outputs: []outputInfo{
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ },
+ },
+ },
+ {
+ name: "VCVTUDQ2PDMasked512",
+ argLen: 2,
+ asm: x86.AVCVTUDQ2PD,
+ reg: regInfo{
+ inputs: []inputInfo{
+ {1, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+ {0, 281474976645120}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ },
+ outputs: []outputInfo{
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ },
+ },
+ },
+ {
+ name: "VCVTUDQ2PS128",
+ argLen: 1,
+ asm: x86.AVCVTUDQ2PS,
+ reg: regInfo{
+ inputs: []inputInfo{
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ },
+ outputs: []outputInfo{
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ },
+ },
+ },
+ {
+ name: "VCVTUDQ2PS256",
+ argLen: 1,
+ asm: x86.AVCVTUDQ2PS,
+ reg: regInfo{
+ inputs: []inputInfo{
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ },
+ outputs: []outputInfo{
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ },
+ },
+ },
+ {
+ name: "VCVTUDQ2PS512",
+ argLen: 1,
+ asm: x86.AVCVTUDQ2PS,
+ reg: regInfo{
+ inputs: []inputInfo{
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ },
+ outputs: []outputInfo{
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ },
+ },
+ },
+ {
+ name: "VCVTUDQ2PSMasked128",
+ argLen: 2,
+ asm: x86.AVCVTUDQ2PS,
+ reg: regInfo{
+ inputs: []inputInfo{
+ {1, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+ {0, 281474976645120}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ },
+ outputs: []outputInfo{
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ },
+ },
+ },
+ {
+ name: "VCVTUDQ2PSMasked256",
+ argLen: 2,
+ asm: x86.AVCVTUDQ2PS,
+ reg: regInfo{
+ inputs: []inputInfo{
+ {1, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+ {0, 281474976645120}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ },
+ outputs: []outputInfo{
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ },
+ },
+ },
+ {
+ name: "VCVTUDQ2PSMasked512",
+ argLen: 2,
+ asm: x86.AVCVTUDQ2PS,
+ reg: regInfo{
+ inputs: []inputInfo{
+ {1, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+ {0, 281474976645120}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ },
+ outputs: []outputInfo{
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ },
+ },
+ },
+ {
+ name: "VCVTUQQ2PD128",
+ argLen: 1,
+ asm: x86.AVCVTUQQ2PD,
+ reg: regInfo{
+ inputs: []inputInfo{
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ },
+ outputs: []outputInfo{
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ },
+ },
+ },
+ {
+ name: "VCVTUQQ2PD256",
+ argLen: 1,
+ asm: x86.AVCVTUQQ2PD,
+ reg: regInfo{
+ inputs: []inputInfo{
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ },
+ outputs: []outputInfo{
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ },
+ },
+ },
+ {
+ name: "VCVTUQQ2PD512",
+ argLen: 1,
+ asm: x86.AVCVTUQQ2PD,
+ reg: regInfo{
+ inputs: []inputInfo{
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ },
+ outputs: []outputInfo{
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ },
+ },
+ },
+ {
+ name: "VCVTUQQ2PDMasked128",
+ argLen: 2,
+ asm: x86.AVCVTUQQ2PD,
+ reg: regInfo{
+ inputs: []inputInfo{
+ {1, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+ {0, 281474976645120}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ },
+ outputs: []outputInfo{
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ },
+ },
+ },
+ {
+ name: "VCVTUQQ2PDMasked256",
+ argLen: 2,
+ asm: x86.AVCVTUQQ2PD,
+ reg: regInfo{
+ inputs: []inputInfo{
+ {1, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+ {0, 281474976645120}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ },
+ outputs: []outputInfo{
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ },
+ },
+ },
+ {
+ name: "VCVTUQQ2PDMasked512",
+ argLen: 2,
+ asm: x86.AVCVTUQQ2PD,
+ reg: regInfo{
+ inputs: []inputInfo{
+ {1, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+ {0, 281474976645120}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ },
+ outputs: []outputInfo{
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ },
+ },
+ },
+ {
+ name: "VCVTUQQ2PS256",
+ argLen: 1,
+ asm: x86.AVCVTUQQ2PS,
+ reg: regInfo{
+ inputs: []inputInfo{
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ },
+ outputs: []outputInfo{
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ },
+ },
+ },
+ {
+ name: "VCVTUQQ2PSMasked256",
+ argLen: 2,
+ asm: x86.AVCVTUQQ2PS,
+ reg: regInfo{
+ inputs: []inputInfo{
+ {1, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+ {0, 281474976645120}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ },
+ outputs: []outputInfo{
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ },
+ },
+ },
+ {
+ name: "VCVTUQQ2PSX128",
+ argLen: 1,
+ asm: x86.AVCVTUQQ2PSX,
+ reg: regInfo{
+ inputs: []inputInfo{
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ },
+ outputs: []outputInfo{
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ },
+ },
+ },
+ {
+ name: "VCVTUQQ2PSXMasked128",
+ argLen: 2,
+ asm: x86.AVCVTUQQ2PSX,
+ reg: regInfo{
+ inputs: []inputInfo{
+ {1, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+ {0, 281474976645120}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ },
+ outputs: []outputInfo{
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ },
+ },
+ },
+ {
+ name: "VCVTUQQ2PSY128",
+ argLen: 1,
+ asm: x86.AVCVTUQQ2PSY,
+ reg: regInfo{
+ inputs: []inputInfo{
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ },
+ outputs: []outputInfo{
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ },
+ },
+ },
+ {
+ name: "VCVTUQQ2PSYMasked128",
+ argLen: 2,
+ asm: x86.AVCVTUQQ2PSY,
+ reg: regInfo{
+ inputs: []inputInfo{
+ {1, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+ {0, 281474976645120}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ },
+ outputs: []outputInfo{
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ },
+ },
+ },
{
name: "VDIVPD128",
argLen: 2,
},
},
},
+ {
+ name: "VCVTDQ2PD512load",
+ auxType: auxSymOff,
+ argLen: 2,
+ symEffect: SymRead,
+ asm: x86.AVCVTDQ2PD,
+ reg: regInfo{
+ inputs: []inputInfo{
+ {0, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
+ },
+ outputs: []outputInfo{
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ },
+ },
+ },
+ {
+ name: "VCVTDQ2PDMasked256load",
+ auxType: auxSymOff,
+ argLen: 3,
+ symEffect: SymRead,
+ asm: x86.AVCVTDQ2PD,
+ reg: regInfo{
+ inputs: []inputInfo{
+ {1, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+ {0, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
+ },
+ outputs: []outputInfo{
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ },
+ },
+ },
+ {
+ name: "VCVTDQ2PDMasked512load",
+ auxType: auxSymOff,
+ argLen: 3,
+ symEffect: SymRead,
+ asm: x86.AVCVTDQ2PD,
+ reg: regInfo{
+ inputs: []inputInfo{
+ {1, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+ {0, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
+ },
+ outputs: []outputInfo{
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ },
+ },
+ },
+ {
+ name: "VCVTDQ2PS512load",
+ auxType: auxSymOff,
+ argLen: 2,
+ symEffect: SymRead,
+ asm: x86.AVCVTDQ2PS,
+ reg: regInfo{
+ inputs: []inputInfo{
+ {0, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
+ },
+ outputs: []outputInfo{
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ },
+ },
+ },
+ {
+ name: "VCVTDQ2PSMasked128load",
+ auxType: auxSymOff,
+ argLen: 3,
+ symEffect: SymRead,
+ asm: x86.AVCVTDQ2PS,
+ reg: regInfo{
+ inputs: []inputInfo{
+ {1, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+ {0, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
+ },
+ outputs: []outputInfo{
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ },
+ },
+ },
+ {
+ name: "VCVTDQ2PSMasked256load",
+ auxType: auxSymOff,
+ argLen: 3,
+ symEffect: SymRead,
+ asm: x86.AVCVTDQ2PS,
+ reg: regInfo{
+ inputs: []inputInfo{
+ {1, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+ {0, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
+ },
+ outputs: []outputInfo{
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ },
+ },
+ },
+ {
+ name: "VCVTDQ2PSMasked512load",
+ auxType: auxSymOff,
+ argLen: 3,
+ symEffect: SymRead,
+ asm: x86.AVCVTDQ2PS,
+ reg: regInfo{
+ inputs: []inputInfo{
+ {1, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+ {0, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
+ },
+ outputs: []outputInfo{
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ },
+ },
+ },
+ {
+ name: "VCVTQQ2PD128load",
+ auxType: auxSymOff,
+ argLen: 2,
+ symEffect: SymRead,
+ asm: x86.AVCVTQQ2PD,
+ reg: regInfo{
+ inputs: []inputInfo{
+ {0, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
+ },
+ outputs: []outputInfo{
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ },
+ },
+ },
+ {
+ name: "VCVTQQ2PD256load",
+ auxType: auxSymOff,
+ argLen: 2,
+ symEffect: SymRead,
+ asm: x86.AVCVTQQ2PD,
+ reg: regInfo{
+ inputs: []inputInfo{
+ {0, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
+ },
+ outputs: []outputInfo{
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ },
+ },
+ },
+ {
+ name: "VCVTQQ2PD512load",
+ auxType: auxSymOff,
+ argLen: 2,
+ symEffect: SymRead,
+ asm: x86.AVCVTQQ2PD,
+ reg: regInfo{
+ inputs: []inputInfo{
+ {0, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
+ },
+ outputs: []outputInfo{
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ },
+ },
+ },
+ {
+ name: "VCVTQQ2PDMasked128load",
+ auxType: auxSymOff,
+ argLen: 3,
+ symEffect: SymRead,
+ asm: x86.AVCVTQQ2PD,
+ reg: regInfo{
+ inputs: []inputInfo{
+ {1, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+ {0, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
+ },
+ outputs: []outputInfo{
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ },
+ },
+ },
+ {
+ name: "VCVTQQ2PDMasked256load",
+ auxType: auxSymOff,
+ argLen: 3,
+ symEffect: SymRead,
+ asm: x86.AVCVTQQ2PD,
+ reg: regInfo{
+ inputs: []inputInfo{
+ {1, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+ {0, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
+ },
+ outputs: []outputInfo{
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ },
+ },
+ },
+ {
+ name: "VCVTQQ2PDMasked512load",
+ auxType: auxSymOff,
+ argLen: 3,
+ symEffect: SymRead,
+ asm: x86.AVCVTQQ2PD,
+ reg: regInfo{
+ inputs: []inputInfo{
+ {1, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+ {0, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
+ },
+ outputs: []outputInfo{
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ },
+ },
+ },
+ {
+ name: "VCVTQQ2PS256load",
+ auxType: auxSymOff,
+ argLen: 2,
+ symEffect: SymRead,
+ asm: x86.AVCVTQQ2PS,
+ reg: regInfo{
+ inputs: []inputInfo{
+ {0, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
+ },
+ outputs: []outputInfo{
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ },
+ },
+ },
+ {
+ name: "VCVTQQ2PSMasked256load",
+ auxType: auxSymOff,
+ argLen: 3,
+ symEffect: SymRead,
+ asm: x86.AVCVTQQ2PS,
+ reg: regInfo{
+ inputs: []inputInfo{
+ {1, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+ {0, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
+ },
+ outputs: []outputInfo{
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ },
+ },
+ },
+ {
+ name: "VCVTQQ2PSX128load",
+ auxType: auxSymOff,
+ argLen: 2,
+ symEffect: SymRead,
+ asm: x86.AVCVTQQ2PSX,
+ reg: regInfo{
+ inputs: []inputInfo{
+ {0, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
+ },
+ outputs: []outputInfo{
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ },
+ },
+ },
+ {
+ name: "VCVTQQ2PSXMasked128load",
+ auxType: auxSymOff,
+ argLen: 3,
+ symEffect: SymRead,
+ asm: x86.AVCVTQQ2PSX,
+ reg: regInfo{
+ inputs: []inputInfo{
+ {1, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+ {0, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
+ },
+ outputs: []outputInfo{
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ },
+ },
+ },
+ {
+ name: "VCVTQQ2PSY128load",
+ auxType: auxSymOff,
+ argLen: 2,
+ symEffect: SymRead,
+ asm: x86.AVCVTQQ2PSY,
+ reg: regInfo{
+ inputs: []inputInfo{
+ {0, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
+ },
+ outputs: []outputInfo{
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ },
+ },
+ },
+ {
+ name: "VCVTQQ2PSYMasked128load",
+ auxType: auxSymOff,
+ argLen: 3,
+ symEffect: SymRead,
+ asm: x86.AVCVTQQ2PSY,
+ reg: regInfo{
+ inputs: []inputInfo{
+ {1, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+ {0, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
+ },
+ outputs: []outputInfo{
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ },
+ },
+ },
{
name: "VCVTTPD2DQ256load",
auxType: auxSymOff,
},
},
},
+ {
+ name: "VCVTUDQ2PD256load",
+ auxType: auxSymOff,
+ argLen: 2,
+ symEffect: SymRead,
+ asm: x86.AVCVTUDQ2PD,
+ reg: regInfo{
+ inputs: []inputInfo{
+ {0, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
+ },
+ outputs: []outputInfo{
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ },
+ },
+ },
+ {
+ name: "VCVTUDQ2PD512load",
+ auxType: auxSymOff,
+ argLen: 2,
+ symEffect: SymRead,
+ asm: x86.AVCVTUDQ2PD,
+ reg: regInfo{
+ inputs: []inputInfo{
+ {0, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
+ },
+ outputs: []outputInfo{
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ },
+ },
+ },
+ {
+ name: "VCVTUDQ2PDMasked256load",
+ auxType: auxSymOff,
+ argLen: 3,
+ symEffect: SymRead,
+ asm: x86.AVCVTUDQ2PD,
+ reg: regInfo{
+ inputs: []inputInfo{
+ {1, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+ {0, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
+ },
+ outputs: []outputInfo{
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ },
+ },
+ },
+ {
+ name: "VCVTUDQ2PDMasked512load",
+ auxType: auxSymOff,
+ argLen: 3,
+ symEffect: SymRead,
+ asm: x86.AVCVTUDQ2PD,
+ reg: regInfo{
+ inputs: []inputInfo{
+ {1, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+ {0, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
+ },
+ outputs: []outputInfo{
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ },
+ },
+ },
+ {
+ name: "VCVTUDQ2PS128load",
+ auxType: auxSymOff,
+ argLen: 2,
+ symEffect: SymRead,
+ asm: x86.AVCVTUDQ2PS,
+ reg: regInfo{
+ inputs: []inputInfo{
+ {0, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
+ },
+ outputs: []outputInfo{
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ },
+ },
+ },
+ {
+ name: "VCVTUDQ2PS256load",
+ auxType: auxSymOff,
+ argLen: 2,
+ symEffect: SymRead,
+ asm: x86.AVCVTUDQ2PS,
+ reg: regInfo{
+ inputs: []inputInfo{
+ {0, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
+ },
+ outputs: []outputInfo{
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ },
+ },
+ },
+ {
+ name: "VCVTUDQ2PS512load",
+ auxType: auxSymOff,
+ argLen: 2,
+ symEffect: SymRead,
+ asm: x86.AVCVTUDQ2PS,
+ reg: regInfo{
+ inputs: []inputInfo{
+ {0, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
+ },
+ outputs: []outputInfo{
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ },
+ },
+ },
+ {
+ name: "VCVTUDQ2PSMasked128load",
+ auxType: auxSymOff,
+ argLen: 3,
+ symEffect: SymRead,
+ asm: x86.AVCVTUDQ2PS,
+ reg: regInfo{
+ inputs: []inputInfo{
+ {1, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+ {0, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
+ },
+ outputs: []outputInfo{
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ },
+ },
+ },
+ {
+ name: "VCVTUDQ2PSMasked256load",
+ auxType: auxSymOff,
+ argLen: 3,
+ symEffect: SymRead,
+ asm: x86.AVCVTUDQ2PS,
+ reg: regInfo{
+ inputs: []inputInfo{
+ {1, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+ {0, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
+ },
+ outputs: []outputInfo{
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ },
+ },
+ },
+ {
+ name: "VCVTUDQ2PSMasked512load",
+ auxType: auxSymOff,
+ argLen: 3,
+ symEffect: SymRead,
+ asm: x86.AVCVTUDQ2PS,
+ reg: regInfo{
+ inputs: []inputInfo{
+ {1, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+ {0, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
+ },
+ outputs: []outputInfo{
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ },
+ },
+ },
+ {
+ name: "VCVTUQQ2PD128load",
+ auxType: auxSymOff,
+ argLen: 2,
+ symEffect: SymRead,
+ asm: x86.AVCVTUQQ2PD,
+ reg: regInfo{
+ inputs: []inputInfo{
+ {0, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
+ },
+ outputs: []outputInfo{
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ },
+ },
+ },
+ {
+ name: "VCVTUQQ2PD256load",
+ auxType: auxSymOff,
+ argLen: 2,
+ symEffect: SymRead,
+ asm: x86.AVCVTUQQ2PD,
+ reg: regInfo{
+ inputs: []inputInfo{
+ {0, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
+ },
+ outputs: []outputInfo{
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ },
+ },
+ },
+ {
+ name: "VCVTUQQ2PD512load",
+ auxType: auxSymOff,
+ argLen: 2,
+ symEffect: SymRead,
+ asm: x86.AVCVTUQQ2PD,
+ reg: regInfo{
+ inputs: []inputInfo{
+ {0, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
+ },
+ outputs: []outputInfo{
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ },
+ },
+ },
+ {
+ name: "VCVTUQQ2PDMasked128load",
+ auxType: auxSymOff,
+ argLen: 3,
+ symEffect: SymRead,
+ asm: x86.AVCVTUQQ2PD,
+ reg: regInfo{
+ inputs: []inputInfo{
+ {1, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+ {0, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
+ },
+ outputs: []outputInfo{
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ },
+ },
+ },
+ {
+ name: "VCVTUQQ2PDMasked256load",
+ auxType: auxSymOff,
+ argLen: 3,
+ symEffect: SymRead,
+ asm: x86.AVCVTUQQ2PD,
+ reg: regInfo{
+ inputs: []inputInfo{
+ {1, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+ {0, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
+ },
+ outputs: []outputInfo{
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ },
+ },
+ },
+ {
+ name: "VCVTUQQ2PDMasked512load",
+ auxType: auxSymOff,
+ argLen: 3,
+ symEffect: SymRead,
+ asm: x86.AVCVTUQQ2PD,
+ reg: regInfo{
+ inputs: []inputInfo{
+ {1, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+ {0, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
+ },
+ outputs: []outputInfo{
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ },
+ },
+ },
+ {
+ name: "VCVTUQQ2PS256load",
+ auxType: auxSymOff,
+ argLen: 2,
+ symEffect: SymRead,
+ asm: x86.AVCVTUQQ2PS,
+ reg: regInfo{
+ inputs: []inputInfo{
+ {0, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
+ },
+ outputs: []outputInfo{
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ },
+ },
+ },
+ {
+ name: "VCVTUQQ2PSMasked256load",
+ auxType: auxSymOff,
+ argLen: 3,
+ symEffect: SymRead,
+ asm: x86.AVCVTUQQ2PS,
+ reg: regInfo{
+ inputs: []inputInfo{
+ {1, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+ {0, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
+ },
+ outputs: []outputInfo{
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ },
+ },
+ },
+ {
+ name: "VCVTUQQ2PSX128load",
+ auxType: auxSymOff,
+ argLen: 2,
+ symEffect: SymRead,
+ asm: x86.AVCVTUQQ2PSX,
+ reg: regInfo{
+ inputs: []inputInfo{
+ {0, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
+ },
+ outputs: []outputInfo{
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ },
+ },
+ },
+ {
+ name: "VCVTUQQ2PSXMasked128load",
+ auxType: auxSymOff,
+ argLen: 3,
+ symEffect: SymRead,
+ asm: x86.AVCVTUQQ2PSX,
+ reg: regInfo{
+ inputs: []inputInfo{
+ {1, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+ {0, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
+ },
+ outputs: []outputInfo{
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ },
+ },
+ },
+ {
+ name: "VCVTUQQ2PSY128load",
+ auxType: auxSymOff,
+ argLen: 2,
+ symEffect: SymRead,
+ asm: x86.AVCVTUQQ2PSY,
+ reg: regInfo{
+ inputs: []inputInfo{
+ {0, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
+ },
+ outputs: []outputInfo{
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ },
+ },
+ },
+ {
+ name: "VCVTUQQ2PSYMasked128load",
+ auxType: auxSymOff,
+ argLen: 3,
+ symEffect: SymRead,
+ asm: x86.AVCVTUQQ2PSY,
+ reg: regInfo{
+ inputs: []inputInfo{
+ {1, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+ {0, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
+ },
+ outputs: []outputInfo{
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ },
+ },
+ },
{
name: "VDIVPD512load",
auxType: auxSymOff,
},
},
},
+ {
+ name: "VCVTDQ2PDMasked256Merging",
+ argLen: 3,
+ resultInArg0: true,
+ asm: x86.AVCVTDQ2PD,
+ reg: regInfo{
+ inputs: []inputInfo{
+ {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ {1, 281474976645120}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ },
+ outputs: []outputInfo{
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ },
+ },
+ },
+ {
+ name: "VCVTDQ2PDMasked512Merging",
+ argLen: 3,
+ resultInArg0: true,
+ asm: x86.AVCVTDQ2PD,
+ reg: regInfo{
+ inputs: []inputInfo{
+ {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ {1, 281474976645120}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ },
+ outputs: []outputInfo{
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ },
+ },
+ },
+ {
+ name: "VCVTDQ2PSMasked128Merging",
+ argLen: 3,
+ resultInArg0: true,
+ asm: x86.AVCVTDQ2PS,
+ reg: regInfo{
+ inputs: []inputInfo{
+ {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ {1, 281474976645120}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ },
+ outputs: []outputInfo{
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ },
+ },
+ },
+ {
+ name: "VCVTDQ2PSMasked256Merging",
+ argLen: 3,
+ resultInArg0: true,
+ asm: x86.AVCVTDQ2PS,
+ reg: regInfo{
+ inputs: []inputInfo{
+ {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ {1, 281474976645120}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ },
+ outputs: []outputInfo{
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ },
+ },
+ },
+ {
+ name: "VCVTDQ2PSMasked512Merging",
+ argLen: 3,
+ resultInArg0: true,
+ asm: x86.AVCVTDQ2PS,
+ reg: regInfo{
+ inputs: []inputInfo{
+ {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ {1, 281474976645120}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ },
+ outputs: []outputInfo{
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ },
+ },
+ },
+ {
+ name: "VCVTQQ2PDMasked128Merging",
+ argLen: 3,
+ resultInArg0: true,
+ asm: x86.AVCVTQQ2PD,
+ reg: regInfo{
+ inputs: []inputInfo{
+ {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ {1, 281474976645120}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ },
+ outputs: []outputInfo{
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ },
+ },
+ },
+ {
+ name: "VCVTQQ2PDMasked256Merging",
+ argLen: 3,
+ resultInArg0: true,
+ asm: x86.AVCVTQQ2PD,
+ reg: regInfo{
+ inputs: []inputInfo{
+ {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ {1, 281474976645120}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ },
+ outputs: []outputInfo{
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ },
+ },
+ },
+ {
+ name: "VCVTQQ2PDMasked512Merging",
+ argLen: 3,
+ resultInArg0: true,
+ asm: x86.AVCVTQQ2PD,
+ reg: regInfo{
+ inputs: []inputInfo{
+ {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ {1, 281474976645120}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ },
+ outputs: []outputInfo{
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ },
+ },
+ },
+ {
+ name: "VCVTQQ2PSMasked256Merging",
+ argLen: 3,
+ resultInArg0: true,
+ asm: x86.AVCVTQQ2PS,
+ reg: regInfo{
+ inputs: []inputInfo{
+ {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ {1, 281474976645120}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ },
+ outputs: []outputInfo{
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ },
+ },
+ },
+ {
+ name: "VCVTQQ2PSXMasked128Merging",
+ argLen: 3,
+ resultInArg0: true,
+ asm: x86.AVCVTQQ2PSX,
+ reg: regInfo{
+ inputs: []inputInfo{
+ {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ {1, 281474976645120}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ },
+ outputs: []outputInfo{
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ },
+ },
+ },
+ {
+ name: "VCVTQQ2PSYMasked128Merging",
+ argLen: 3,
+ resultInArg0: true,
+ asm: x86.AVCVTQQ2PSY,
+ reg: regInfo{
+ inputs: []inputInfo{
+ {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ {1, 281474976645120}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ },
+ outputs: []outputInfo{
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ },
+ },
+ },
{
name: "VCVTTPD2DQMasked256Merging",
argLen: 3,
},
},
},
+ {
+ name: "VCVTUDQ2PDMasked256Merging",
+ argLen: 3,
+ resultInArg0: true,
+ asm: x86.AVCVTUDQ2PD,
+ reg: regInfo{
+ inputs: []inputInfo{
+ {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ {1, 281474976645120}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ },
+ outputs: []outputInfo{
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ },
+ },
+ },
+ {
+ name: "VCVTUDQ2PDMasked512Merging",
+ argLen: 3,
+ resultInArg0: true,
+ asm: x86.AVCVTUDQ2PD,
+ reg: regInfo{
+ inputs: []inputInfo{
+ {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ {1, 281474976645120}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ },
+ outputs: []outputInfo{
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ },
+ },
+ },
+ {
+ name: "VCVTUDQ2PSMasked128Merging",
+ argLen: 3,
+ resultInArg0: true,
+ asm: x86.AVCVTUDQ2PS,
+ reg: regInfo{
+ inputs: []inputInfo{
+ {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ {1, 281474976645120}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ },
+ outputs: []outputInfo{
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ },
+ },
+ },
+ {
+ name: "VCVTUDQ2PSMasked256Merging",
+ argLen: 3,
+ resultInArg0: true,
+ asm: x86.AVCVTUDQ2PS,
+ reg: regInfo{
+ inputs: []inputInfo{
+ {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ {1, 281474976645120}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ },
+ outputs: []outputInfo{
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ },
+ },
+ },
+ {
+ name: "VCVTUDQ2PSMasked512Merging",
+ argLen: 3,
+ resultInArg0: true,
+ asm: x86.AVCVTUDQ2PS,
+ reg: regInfo{
+ inputs: []inputInfo{
+ {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ {1, 281474976645120}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ },
+ outputs: []outputInfo{
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ },
+ },
+ },
+ {
+ name: "VCVTUQQ2PDMasked128Merging",
+ argLen: 3,
+ resultInArg0: true,
+ asm: x86.AVCVTUQQ2PD,
+ reg: regInfo{
+ inputs: []inputInfo{
+ {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ {1, 281474976645120}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ },
+ outputs: []outputInfo{
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ },
+ },
+ },
+ {
+ name: "VCVTUQQ2PDMasked256Merging",
+ argLen: 3,
+ resultInArg0: true,
+ asm: x86.AVCVTUQQ2PD,
+ reg: regInfo{
+ inputs: []inputInfo{
+ {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ {1, 281474976645120}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ },
+ outputs: []outputInfo{
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ },
+ },
+ },
+ {
+ name: "VCVTUQQ2PDMasked512Merging",
+ argLen: 3,
+ resultInArg0: true,
+ asm: x86.AVCVTUQQ2PD,
+ reg: regInfo{
+ inputs: []inputInfo{
+ {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ {1, 281474976645120}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ },
+ outputs: []outputInfo{
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ },
+ },
+ },
+ {
+ name: "VCVTUQQ2PSMasked256Merging",
+ argLen: 3,
+ resultInArg0: true,
+ asm: x86.AVCVTUQQ2PS,
+ reg: regInfo{
+ inputs: []inputInfo{
+ {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ {1, 281474976645120}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ },
+ outputs: []outputInfo{
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ },
+ },
+ },
+ {
+ name: "VCVTUQQ2PSXMasked128Merging",
+ argLen: 3,
+ resultInArg0: true,
+ asm: x86.AVCVTUQQ2PSX,
+ reg: regInfo{
+ inputs: []inputInfo{
+ {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ {1, 281474976645120}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ },
+ outputs: []outputInfo{
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ },
+ },
+ },
+ {
+ name: "VCVTUQQ2PSYMasked128Merging",
+ argLen: 3,
+ resultInArg0: true,
+ asm: x86.AVCVTUQQ2PSY,
+ reg: regInfo{
+ inputs: []inputInfo{
+ {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ {1, 281474976645120}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ },
+ outputs: []outputInfo{
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ },
+ },
+ },
{
name: "VDIVPDMasked128Merging",
argLen: 4,
argLen: 3,
generic: true,
},
+ {
+ name: "ConvertToFloat32Int32x4",
+ argLen: 1,
+ generic: true,
+ },
+ {
+ name: "ConvertToFloat32Int32x8",
+ argLen: 1,
+ generic: true,
+ },
+ {
+ name: "ConvertToFloat32Int32x16",
+ argLen: 1,
+ generic: true,
+ },
+ {
+ name: "ConvertToFloat32Int64x2",
+ argLen: 1,
+ generic: true,
+ },
+ {
+ name: "ConvertToFloat32Int64x4",
+ argLen: 1,
+ generic: true,
+ },
+ {
+ name: "ConvertToFloat32Int64x8",
+ argLen: 1,
+ generic: true,
+ },
+ {
+ name: "ConvertToFloat32Uint32x4",
+ argLen: 1,
+ generic: true,
+ },
+ {
+ name: "ConvertToFloat32Uint32x8",
+ argLen: 1,
+ generic: true,
+ },
+ {
+ name: "ConvertToFloat32Uint32x16",
+ argLen: 1,
+ generic: true,
+ },
+ {
+ name: "ConvertToFloat32Uint64x2",
+ argLen: 1,
+ generic: true,
+ },
+ {
+ name: "ConvertToFloat32Uint64x4",
+ argLen: 1,
+ generic: true,
+ },
+ {
+ name: "ConvertToFloat32Uint64x8",
+ argLen: 1,
+ generic: true,
+ },
+ {
+ name: "ConvertToFloat64Int32x4",
+ argLen: 1,
+ generic: true,
+ },
+ {
+ name: "ConvertToFloat64Int32x8",
+ argLen: 1,
+ generic: true,
+ },
+ {
+ name: "ConvertToFloat64Int64x2",
+ argLen: 1,
+ generic: true,
+ },
+ {
+ name: "ConvertToFloat64Int64x4",
+ argLen: 1,
+ generic: true,
+ },
+ {
+ name: "ConvertToFloat64Int64x8",
+ argLen: 1,
+ generic: true,
+ },
+ {
+ name: "ConvertToFloat64Uint32x4",
+ argLen: 1,
+ generic: true,
+ },
+ {
+ name: "ConvertToFloat64Uint32x8",
+ argLen: 1,
+ generic: true,
+ },
+ {
+ name: "ConvertToFloat64Uint64x2",
+ argLen: 1,
+ generic: true,
+ },
+ {
+ name: "ConvertToFloat64Uint64x4",
+ argLen: 1,
+ generic: true,
+ },
+ {
+ name: "ConvertToFloat64Uint64x8",
+ argLen: 1,
+ generic: true,
+ },
{
name: "ConvertToInt32Float32x4",
argLen: 1,
return rewriteValueAMD64_OpAMD64VCMPPSMasked256(v)
case OpAMD64VCMPPSMasked512:
return rewriteValueAMD64_OpAMD64VCMPPSMasked512(v)
+ case OpAMD64VCVTDQ2PD512:
+ return rewriteValueAMD64_OpAMD64VCVTDQ2PD512(v)
+ case OpAMD64VCVTDQ2PDMasked256:
+ return rewriteValueAMD64_OpAMD64VCVTDQ2PDMasked256(v)
+ case OpAMD64VCVTDQ2PDMasked512:
+ return rewriteValueAMD64_OpAMD64VCVTDQ2PDMasked512(v)
+ case OpAMD64VCVTDQ2PS512:
+ return rewriteValueAMD64_OpAMD64VCVTDQ2PS512(v)
+ case OpAMD64VCVTDQ2PSMasked128:
+ return rewriteValueAMD64_OpAMD64VCVTDQ2PSMasked128(v)
+ case OpAMD64VCVTDQ2PSMasked256:
+ return rewriteValueAMD64_OpAMD64VCVTDQ2PSMasked256(v)
+ case OpAMD64VCVTDQ2PSMasked512:
+ return rewriteValueAMD64_OpAMD64VCVTDQ2PSMasked512(v)
+ case OpAMD64VCVTQQ2PD128:
+ return rewriteValueAMD64_OpAMD64VCVTQQ2PD128(v)
+ case OpAMD64VCVTQQ2PD256:
+ return rewriteValueAMD64_OpAMD64VCVTQQ2PD256(v)
+ case OpAMD64VCVTQQ2PD512:
+ return rewriteValueAMD64_OpAMD64VCVTQQ2PD512(v)
+ case OpAMD64VCVTQQ2PDMasked128:
+ return rewriteValueAMD64_OpAMD64VCVTQQ2PDMasked128(v)
+ case OpAMD64VCVTQQ2PDMasked256:
+ return rewriteValueAMD64_OpAMD64VCVTQQ2PDMasked256(v)
+ case OpAMD64VCVTQQ2PDMasked512:
+ return rewriteValueAMD64_OpAMD64VCVTQQ2PDMasked512(v)
+ case OpAMD64VCVTQQ2PS256:
+ return rewriteValueAMD64_OpAMD64VCVTQQ2PS256(v)
+ case OpAMD64VCVTQQ2PSMasked256:
+ return rewriteValueAMD64_OpAMD64VCVTQQ2PSMasked256(v)
+ case OpAMD64VCVTQQ2PSX128:
+ return rewriteValueAMD64_OpAMD64VCVTQQ2PSX128(v)
+ case OpAMD64VCVTQQ2PSXMasked128:
+ return rewriteValueAMD64_OpAMD64VCVTQQ2PSXMasked128(v)
+ case OpAMD64VCVTQQ2PSY128:
+ return rewriteValueAMD64_OpAMD64VCVTQQ2PSY128(v)
+ case OpAMD64VCVTQQ2PSYMasked128:
+ return rewriteValueAMD64_OpAMD64VCVTQQ2PSYMasked128(v)
case OpAMD64VCVTTPD2DQ256:
return rewriteValueAMD64_OpAMD64VCVTTPD2DQ256(v)
case OpAMD64VCVTTPD2DQMasked256:
return rewriteValueAMD64_OpAMD64VCVTTPS2UQQMasked256(v)
case OpAMD64VCVTTPS2UQQMasked512:
return rewriteValueAMD64_OpAMD64VCVTTPS2UQQMasked512(v)
+ case OpAMD64VCVTUDQ2PD256:
+ return rewriteValueAMD64_OpAMD64VCVTUDQ2PD256(v)
+ case OpAMD64VCVTUDQ2PD512:
+ return rewriteValueAMD64_OpAMD64VCVTUDQ2PD512(v)
+ case OpAMD64VCVTUDQ2PDMasked256:
+ return rewriteValueAMD64_OpAMD64VCVTUDQ2PDMasked256(v)
+ case OpAMD64VCVTUDQ2PDMasked512:
+ return rewriteValueAMD64_OpAMD64VCVTUDQ2PDMasked512(v)
+ case OpAMD64VCVTUDQ2PS128:
+ return rewriteValueAMD64_OpAMD64VCVTUDQ2PS128(v)
+ case OpAMD64VCVTUDQ2PS256:
+ return rewriteValueAMD64_OpAMD64VCVTUDQ2PS256(v)
+ case OpAMD64VCVTUDQ2PS512:
+ return rewriteValueAMD64_OpAMD64VCVTUDQ2PS512(v)
+ case OpAMD64VCVTUDQ2PSMasked128:
+ return rewriteValueAMD64_OpAMD64VCVTUDQ2PSMasked128(v)
+ case OpAMD64VCVTUDQ2PSMasked256:
+ return rewriteValueAMD64_OpAMD64VCVTUDQ2PSMasked256(v)
+ case OpAMD64VCVTUDQ2PSMasked512:
+ return rewriteValueAMD64_OpAMD64VCVTUDQ2PSMasked512(v)
+ case OpAMD64VCVTUQQ2PD128:
+ return rewriteValueAMD64_OpAMD64VCVTUQQ2PD128(v)
+ case OpAMD64VCVTUQQ2PD256:
+ return rewriteValueAMD64_OpAMD64VCVTUQQ2PD256(v)
+ case OpAMD64VCVTUQQ2PD512:
+ return rewriteValueAMD64_OpAMD64VCVTUQQ2PD512(v)
+ case OpAMD64VCVTUQQ2PDMasked128:
+ return rewriteValueAMD64_OpAMD64VCVTUQQ2PDMasked128(v)
+ case OpAMD64VCVTUQQ2PDMasked256:
+ return rewriteValueAMD64_OpAMD64VCVTUQQ2PDMasked256(v)
+ case OpAMD64VCVTUQQ2PDMasked512:
+ return rewriteValueAMD64_OpAMD64VCVTUQQ2PDMasked512(v)
+ case OpAMD64VCVTUQQ2PS256:
+ return rewriteValueAMD64_OpAMD64VCVTUQQ2PS256(v)
+ case OpAMD64VCVTUQQ2PSMasked256:
+ return rewriteValueAMD64_OpAMD64VCVTUQQ2PSMasked256(v)
+ case OpAMD64VCVTUQQ2PSX128:
+ return rewriteValueAMD64_OpAMD64VCVTUQQ2PSX128(v)
+ case OpAMD64VCVTUQQ2PSXMasked128:
+ return rewriteValueAMD64_OpAMD64VCVTUQQ2PSXMasked128(v)
+ case OpAMD64VCVTUQQ2PSY128:
+ return rewriteValueAMD64_OpAMD64VCVTUQQ2PSY128(v)
+ case OpAMD64VCVTUQQ2PSYMasked128:
+ return rewriteValueAMD64_OpAMD64VCVTUQQ2PSYMasked128(v)
case OpAMD64VDIVPD512:
return rewriteValueAMD64_OpAMD64VDIVPD512(v)
case OpAMD64VDIVPDMasked128:
return rewriteValueAMD64_OpConstBool(v)
case OpConstNil:
return rewriteValueAMD64_OpConstNil(v)
+ case OpConvertToFloat32Int32x16:
+ v.Op = OpAMD64VCVTDQ2PS512
+ return true
+ case OpConvertToFloat32Int32x4:
+ v.Op = OpAMD64VCVTDQ2PS128
+ return true
+ case OpConvertToFloat32Int32x8:
+ v.Op = OpAMD64VCVTDQ2PS256
+ return true
+ case OpConvertToFloat32Int64x2:
+ v.Op = OpAMD64VCVTQQ2PSX128
+ return true
+ case OpConvertToFloat32Int64x4:
+ v.Op = OpAMD64VCVTQQ2PSY128
+ return true
+ case OpConvertToFloat32Int64x8:
+ v.Op = OpAMD64VCVTQQ2PS256
+ return true
+ case OpConvertToFloat32Uint32x16:
+ v.Op = OpAMD64VCVTUDQ2PS512
+ return true
+ case OpConvertToFloat32Uint32x4:
+ v.Op = OpAMD64VCVTUDQ2PS128
+ return true
+ case OpConvertToFloat32Uint32x8:
+ v.Op = OpAMD64VCVTUDQ2PS256
+ return true
+ case OpConvertToFloat32Uint64x2:
+ v.Op = OpAMD64VCVTUQQ2PSX128
+ return true
+ case OpConvertToFloat32Uint64x4:
+ v.Op = OpAMD64VCVTUQQ2PSY128
+ return true
+ case OpConvertToFloat32Uint64x8:
+ v.Op = OpAMD64VCVTUQQ2PS256
+ return true
+ case OpConvertToFloat64Int32x4:
+ v.Op = OpAMD64VCVTDQ2PD256
+ return true
+ case OpConvertToFloat64Int32x8:
+ v.Op = OpAMD64VCVTDQ2PD512
+ return true
+ case OpConvertToFloat64Int64x2:
+ v.Op = OpAMD64VCVTQQ2PD128
+ return true
+ case OpConvertToFloat64Int64x4:
+ v.Op = OpAMD64VCVTQQ2PD256
+ return true
+ case OpConvertToFloat64Int64x8:
+ v.Op = OpAMD64VCVTQQ2PD512
+ return true
+ case OpConvertToFloat64Uint32x4:
+ v.Op = OpAMD64VCVTUDQ2PD256
+ return true
+ case OpConvertToFloat64Uint32x8:
+ v.Op = OpAMD64VCVTUDQ2PD512
+ return true
+ case OpConvertToFloat64Uint64x2:
+ v.Op = OpAMD64VCVTUQQ2PD128
+ return true
+ case OpConvertToFloat64Uint64x4:
+ v.Op = OpAMD64VCVTUQQ2PD256
+ return true
+ case OpConvertToFloat64Uint64x8:
+ v.Op = OpAMD64VCVTUQQ2PD512
+ return true
case OpConvertToInt32Float32x16:
v.Op = OpAMD64VCVTTPS2DQ512
return true
}
return false
}
+func rewriteValueAMD64_OpAMD64VCVTDQ2PD512(v *Value) bool {
+ v_0 := v.Args[0]
+ // match: (VCVTDQ2PD512 l:(VMOVDQUload256 {sym} [off] ptr mem))
+ // cond: canMergeLoad(v, l) && clobber(l)
+ // result: (VCVTDQ2PD512load {sym} [off] ptr mem)
+ for {
+ l := v_0
+ if l.Op != OpAMD64VMOVDQUload256 {
+ break
+ }
+ off := auxIntToInt32(l.AuxInt)
+ sym := auxToSym(l.Aux)
+ mem := l.Args[1]
+ ptr := l.Args[0]
+ if !(canMergeLoad(v, l) && clobber(l)) {
+ break
+ }
+ v.reset(OpAMD64VCVTDQ2PD512load)
+ v.AuxInt = int32ToAuxInt(off)
+ v.Aux = symToAux(sym)
+ v.AddArg2(ptr, mem)
+ return true
+ }
+ return false
+}
+func rewriteValueAMD64_OpAMD64VCVTDQ2PDMasked256(v *Value) bool {
+ v_1 := v.Args[1]
+ v_0 := v.Args[0]
+ // match: (VCVTDQ2PDMasked256 l:(VMOVDQUload128 {sym} [off] ptr mem) mask)
+ // cond: canMergeLoad(v, l) && clobber(l)
+ // result: (VCVTDQ2PDMasked256load {sym} [off] ptr mask mem)
+ for {
+ l := v_0
+ if l.Op != OpAMD64VMOVDQUload128 {
+ break
+ }
+ off := auxIntToInt32(l.AuxInt)
+ sym := auxToSym(l.Aux)
+ mem := l.Args[1]
+ ptr := l.Args[0]
+ mask := v_1
+ if !(canMergeLoad(v, l) && clobber(l)) {
+ break
+ }
+ v.reset(OpAMD64VCVTDQ2PDMasked256load)
+ v.AuxInt = int32ToAuxInt(off)
+ v.Aux = symToAux(sym)
+ v.AddArg3(ptr, mask, mem)
+ return true
+ }
+ return false
+}
+func rewriteValueAMD64_OpAMD64VCVTDQ2PDMasked512(v *Value) bool {
+ v_1 := v.Args[1]
+ v_0 := v.Args[0]
+ // match: (VCVTDQ2PDMasked512 l:(VMOVDQUload256 {sym} [off] ptr mem) mask)
+ // cond: canMergeLoad(v, l) && clobber(l)
+ // result: (VCVTDQ2PDMasked512load {sym} [off] ptr mask mem)
+ for {
+ l := v_0
+ if l.Op != OpAMD64VMOVDQUload256 {
+ break
+ }
+ off := auxIntToInt32(l.AuxInt)
+ sym := auxToSym(l.Aux)
+ mem := l.Args[1]
+ ptr := l.Args[0]
+ mask := v_1
+ if !(canMergeLoad(v, l) && clobber(l)) {
+ break
+ }
+ v.reset(OpAMD64VCVTDQ2PDMasked512load)
+ v.AuxInt = int32ToAuxInt(off)
+ v.Aux = symToAux(sym)
+ v.AddArg3(ptr, mask, mem)
+ return true
+ }
+ return false
+}
+func rewriteValueAMD64_OpAMD64VCVTDQ2PS512(v *Value) bool {
+ v_0 := v.Args[0]
+ // match: (VCVTDQ2PS512 l:(VMOVDQUload512 {sym} [off] ptr mem))
+ // cond: canMergeLoad(v, l) && clobber(l)
+ // result: (VCVTDQ2PS512load {sym} [off] ptr mem)
+ for {
+ l := v_0
+ if l.Op != OpAMD64VMOVDQUload512 {
+ break
+ }
+ off := auxIntToInt32(l.AuxInt)
+ sym := auxToSym(l.Aux)
+ mem := l.Args[1]
+ ptr := l.Args[0]
+ if !(canMergeLoad(v, l) && clobber(l)) {
+ break
+ }
+ v.reset(OpAMD64VCVTDQ2PS512load)
+ v.AuxInt = int32ToAuxInt(off)
+ v.Aux = symToAux(sym)
+ v.AddArg2(ptr, mem)
+ return true
+ }
+ return false
+}
+func rewriteValueAMD64_OpAMD64VCVTDQ2PSMasked128(v *Value) bool {
+ v_1 := v.Args[1]
+ v_0 := v.Args[0]
+ // match: (VCVTDQ2PSMasked128 l:(VMOVDQUload128 {sym} [off] ptr mem) mask)
+ // cond: canMergeLoad(v, l) && clobber(l)
+ // result: (VCVTDQ2PSMasked128load {sym} [off] ptr mask mem)
+ for {
+ l := v_0
+ if l.Op != OpAMD64VMOVDQUload128 {
+ break
+ }
+ off := auxIntToInt32(l.AuxInt)
+ sym := auxToSym(l.Aux)
+ mem := l.Args[1]
+ ptr := l.Args[0]
+ mask := v_1
+ if !(canMergeLoad(v, l) && clobber(l)) {
+ break
+ }
+ v.reset(OpAMD64VCVTDQ2PSMasked128load)
+ v.AuxInt = int32ToAuxInt(off)
+ v.Aux = symToAux(sym)
+ v.AddArg3(ptr, mask, mem)
+ return true
+ }
+ return false
+}
+func rewriteValueAMD64_OpAMD64VCVTDQ2PSMasked256(v *Value) bool {
+ v_1 := v.Args[1]
+ v_0 := v.Args[0]
+ // match: (VCVTDQ2PSMasked256 l:(VMOVDQUload256 {sym} [off] ptr mem) mask)
+ // cond: canMergeLoad(v, l) && clobber(l)
+ // result: (VCVTDQ2PSMasked256load {sym} [off] ptr mask mem)
+ for {
+ l := v_0
+ if l.Op != OpAMD64VMOVDQUload256 {
+ break
+ }
+ off := auxIntToInt32(l.AuxInt)
+ sym := auxToSym(l.Aux)
+ mem := l.Args[1]
+ ptr := l.Args[0]
+ mask := v_1
+ if !(canMergeLoad(v, l) && clobber(l)) {
+ break
+ }
+ v.reset(OpAMD64VCVTDQ2PSMasked256load)
+ v.AuxInt = int32ToAuxInt(off)
+ v.Aux = symToAux(sym)
+ v.AddArg3(ptr, mask, mem)
+ return true
+ }
+ return false
+}
+func rewriteValueAMD64_OpAMD64VCVTDQ2PSMasked512(v *Value) bool {
+ v_1 := v.Args[1]
+ v_0 := v.Args[0]
+ // match: (VCVTDQ2PSMasked512 l:(VMOVDQUload512 {sym} [off] ptr mem) mask)
+ // cond: canMergeLoad(v, l) && clobber(l)
+ // result: (VCVTDQ2PSMasked512load {sym} [off] ptr mask mem)
+ for {
+ l := v_0
+ if l.Op != OpAMD64VMOVDQUload512 {
+ break
+ }
+ off := auxIntToInt32(l.AuxInt)
+ sym := auxToSym(l.Aux)
+ mem := l.Args[1]
+ ptr := l.Args[0]
+ mask := v_1
+ if !(canMergeLoad(v, l) && clobber(l)) {
+ break
+ }
+ v.reset(OpAMD64VCVTDQ2PSMasked512load)
+ v.AuxInt = int32ToAuxInt(off)
+ v.Aux = symToAux(sym)
+ v.AddArg3(ptr, mask, mem)
+ return true
+ }
+ return false
+}
+func rewriteValueAMD64_OpAMD64VCVTQQ2PD128(v *Value) bool {
+ v_0 := v.Args[0]
+ // match: (VCVTQQ2PD128 l:(VMOVDQUload128 {sym} [off] ptr mem))
+ // cond: canMergeLoad(v, l) && clobber(l)
+ // result: (VCVTQQ2PD128load {sym} [off] ptr mem)
+ for {
+ l := v_0
+ if l.Op != OpAMD64VMOVDQUload128 {
+ break
+ }
+ off := auxIntToInt32(l.AuxInt)
+ sym := auxToSym(l.Aux)
+ mem := l.Args[1]
+ ptr := l.Args[0]
+ if !(canMergeLoad(v, l) && clobber(l)) {
+ break
+ }
+ v.reset(OpAMD64VCVTQQ2PD128load)
+ v.AuxInt = int32ToAuxInt(off)
+ v.Aux = symToAux(sym)
+ v.AddArg2(ptr, mem)
+ return true
+ }
+ return false
+}
+func rewriteValueAMD64_OpAMD64VCVTQQ2PD256(v *Value) bool {
+ v_0 := v.Args[0]
+ // match: (VCVTQQ2PD256 l:(VMOVDQUload256 {sym} [off] ptr mem))
+ // cond: canMergeLoad(v, l) && clobber(l)
+ // result: (VCVTQQ2PD256load {sym} [off] ptr mem)
+ for {
+ l := v_0
+ if l.Op != OpAMD64VMOVDQUload256 {
+ break
+ }
+ off := auxIntToInt32(l.AuxInt)
+ sym := auxToSym(l.Aux)
+ mem := l.Args[1]
+ ptr := l.Args[0]
+ if !(canMergeLoad(v, l) && clobber(l)) {
+ break
+ }
+ v.reset(OpAMD64VCVTQQ2PD256load)
+ v.AuxInt = int32ToAuxInt(off)
+ v.Aux = symToAux(sym)
+ v.AddArg2(ptr, mem)
+ return true
+ }
+ return false
+}
+func rewriteValueAMD64_OpAMD64VCVTQQ2PD512(v *Value) bool {
+ v_0 := v.Args[0]
+ // match: (VCVTQQ2PD512 l:(VMOVDQUload512 {sym} [off] ptr mem))
+ // cond: canMergeLoad(v, l) && clobber(l)
+ // result: (VCVTQQ2PD512load {sym} [off] ptr mem)
+ for {
+ l := v_0
+ if l.Op != OpAMD64VMOVDQUload512 {
+ break
+ }
+ off := auxIntToInt32(l.AuxInt)
+ sym := auxToSym(l.Aux)
+ mem := l.Args[1]
+ ptr := l.Args[0]
+ if !(canMergeLoad(v, l) && clobber(l)) {
+ break
+ }
+ v.reset(OpAMD64VCVTQQ2PD512load)
+ v.AuxInt = int32ToAuxInt(off)
+ v.Aux = symToAux(sym)
+ v.AddArg2(ptr, mem)
+ return true
+ }
+ return false
+}
+func rewriteValueAMD64_OpAMD64VCVTQQ2PDMasked128(v *Value) bool {
+ v_1 := v.Args[1]
+ v_0 := v.Args[0]
+ // match: (VCVTQQ2PDMasked128 l:(VMOVDQUload128 {sym} [off] ptr mem) mask)
+ // cond: canMergeLoad(v, l) && clobber(l)
+ // result: (VCVTQQ2PDMasked128load {sym} [off] ptr mask mem)
+ for {
+ l := v_0
+ if l.Op != OpAMD64VMOVDQUload128 {
+ break
+ }
+ off := auxIntToInt32(l.AuxInt)
+ sym := auxToSym(l.Aux)
+ mem := l.Args[1]
+ ptr := l.Args[0]
+ mask := v_1
+ if !(canMergeLoad(v, l) && clobber(l)) {
+ break
+ }
+ v.reset(OpAMD64VCVTQQ2PDMasked128load)
+ v.AuxInt = int32ToAuxInt(off)
+ v.Aux = symToAux(sym)
+ v.AddArg3(ptr, mask, mem)
+ return true
+ }
+ return false
+}
+func rewriteValueAMD64_OpAMD64VCVTQQ2PDMasked256(v *Value) bool {
+ v_1 := v.Args[1]
+ v_0 := v.Args[0]
+ // match: (VCVTQQ2PDMasked256 l:(VMOVDQUload256 {sym} [off] ptr mem) mask)
+ // cond: canMergeLoad(v, l) && clobber(l)
+ // result: (VCVTQQ2PDMasked256load {sym} [off] ptr mask mem)
+ for {
+ l := v_0
+ if l.Op != OpAMD64VMOVDQUload256 {
+ break
+ }
+ off := auxIntToInt32(l.AuxInt)
+ sym := auxToSym(l.Aux)
+ mem := l.Args[1]
+ ptr := l.Args[0]
+ mask := v_1
+ if !(canMergeLoad(v, l) && clobber(l)) {
+ break
+ }
+ v.reset(OpAMD64VCVTQQ2PDMasked256load)
+ v.AuxInt = int32ToAuxInt(off)
+ v.Aux = symToAux(sym)
+ v.AddArg3(ptr, mask, mem)
+ return true
+ }
+ return false
+}
+func rewriteValueAMD64_OpAMD64VCVTQQ2PDMasked512(v *Value) bool {
+ v_1 := v.Args[1]
+ v_0 := v.Args[0]
+ // match: (VCVTQQ2PDMasked512 l:(VMOVDQUload512 {sym} [off] ptr mem) mask)
+ // cond: canMergeLoad(v, l) && clobber(l)
+ // result: (VCVTQQ2PDMasked512load {sym} [off] ptr mask mem)
+ for {
+ l := v_0
+ if l.Op != OpAMD64VMOVDQUload512 {
+ break
+ }
+ off := auxIntToInt32(l.AuxInt)
+ sym := auxToSym(l.Aux)
+ mem := l.Args[1]
+ ptr := l.Args[0]
+ mask := v_1
+ if !(canMergeLoad(v, l) && clobber(l)) {
+ break
+ }
+ v.reset(OpAMD64VCVTQQ2PDMasked512load)
+ v.AuxInt = int32ToAuxInt(off)
+ v.Aux = symToAux(sym)
+ v.AddArg3(ptr, mask, mem)
+ return true
+ }
+ return false
+}
+func rewriteValueAMD64_OpAMD64VCVTQQ2PS256(v *Value) bool {
+ v_0 := v.Args[0]
+ // match: (VCVTQQ2PS256 l:(VMOVDQUload512 {sym} [off] ptr mem))
+ // cond: canMergeLoad(v, l) && clobber(l)
+ // result: (VCVTQQ2PS256load {sym} [off] ptr mem)
+ for {
+ l := v_0
+ if l.Op != OpAMD64VMOVDQUload512 {
+ break
+ }
+ off := auxIntToInt32(l.AuxInt)
+ sym := auxToSym(l.Aux)
+ mem := l.Args[1]
+ ptr := l.Args[0]
+ if !(canMergeLoad(v, l) && clobber(l)) {
+ break
+ }
+ v.reset(OpAMD64VCVTQQ2PS256load)
+ v.AuxInt = int32ToAuxInt(off)
+ v.Aux = symToAux(sym)
+ v.AddArg2(ptr, mem)
+ return true
+ }
+ return false
+}
+func rewriteValueAMD64_OpAMD64VCVTQQ2PSMasked256(v *Value) bool {
+ v_1 := v.Args[1]
+ v_0 := v.Args[0]
+ // match: (VCVTQQ2PSMasked256 l:(VMOVDQUload512 {sym} [off] ptr mem) mask)
+ // cond: canMergeLoad(v, l) && clobber(l)
+ // result: (VCVTQQ2PSMasked256load {sym} [off] ptr mask mem)
+ for {
+ l := v_0
+ if l.Op != OpAMD64VMOVDQUload512 {
+ break
+ }
+ off := auxIntToInt32(l.AuxInt)
+ sym := auxToSym(l.Aux)
+ mem := l.Args[1]
+ ptr := l.Args[0]
+ mask := v_1
+ if !(canMergeLoad(v, l) && clobber(l)) {
+ break
+ }
+ v.reset(OpAMD64VCVTQQ2PSMasked256load)
+ v.AuxInt = int32ToAuxInt(off)
+ v.Aux = symToAux(sym)
+ v.AddArg3(ptr, mask, mem)
+ return true
+ }
+ return false
+}
+func rewriteValueAMD64_OpAMD64VCVTQQ2PSX128(v *Value) bool {
+ v_0 := v.Args[0]
+ // match: (VCVTQQ2PSX128 l:(VMOVDQUload128 {sym} [off] ptr mem))
+ // cond: canMergeLoad(v, l) && clobber(l)
+ // result: (VCVTQQ2PSX128load {sym} [off] ptr mem)
+ for {
+ l := v_0
+ if l.Op != OpAMD64VMOVDQUload128 {
+ break
+ }
+ off := auxIntToInt32(l.AuxInt)
+ sym := auxToSym(l.Aux)
+ mem := l.Args[1]
+ ptr := l.Args[0]
+ if !(canMergeLoad(v, l) && clobber(l)) {
+ break
+ }
+ v.reset(OpAMD64VCVTQQ2PSX128load)
+ v.AuxInt = int32ToAuxInt(off)
+ v.Aux = symToAux(sym)
+ v.AddArg2(ptr, mem)
+ return true
+ }
+ return false
+}
+func rewriteValueAMD64_OpAMD64VCVTQQ2PSXMasked128(v *Value) bool {
+ v_1 := v.Args[1]
+ v_0 := v.Args[0]
+ // match: (VCVTQQ2PSXMasked128 l:(VMOVDQUload128 {sym} [off] ptr mem) mask)
+ // cond: canMergeLoad(v, l) && clobber(l)
+ // result: (VCVTQQ2PSXMasked128load {sym} [off] ptr mask mem)
+ for {
+ l := v_0
+ if l.Op != OpAMD64VMOVDQUload128 {
+ break
+ }
+ off := auxIntToInt32(l.AuxInt)
+ sym := auxToSym(l.Aux)
+ mem := l.Args[1]
+ ptr := l.Args[0]
+ mask := v_1
+ if !(canMergeLoad(v, l) && clobber(l)) {
+ break
+ }
+ v.reset(OpAMD64VCVTQQ2PSXMasked128load)
+ v.AuxInt = int32ToAuxInt(off)
+ v.Aux = symToAux(sym)
+ v.AddArg3(ptr, mask, mem)
+ return true
+ }
+ return false
+}
+func rewriteValueAMD64_OpAMD64VCVTQQ2PSY128(v *Value) bool {
+ v_0 := v.Args[0]
+ // match: (VCVTQQ2PSY128 l:(VMOVDQUload256 {sym} [off] ptr mem))
+ // cond: canMergeLoad(v, l) && clobber(l)
+ // result: (VCVTQQ2PSY128load {sym} [off] ptr mem)
+ for {
+ l := v_0
+ if l.Op != OpAMD64VMOVDQUload256 {
+ break
+ }
+ off := auxIntToInt32(l.AuxInt)
+ sym := auxToSym(l.Aux)
+ mem := l.Args[1]
+ ptr := l.Args[0]
+ if !(canMergeLoad(v, l) && clobber(l)) {
+ break
+ }
+ v.reset(OpAMD64VCVTQQ2PSY128load)
+ v.AuxInt = int32ToAuxInt(off)
+ v.Aux = symToAux(sym)
+ v.AddArg2(ptr, mem)
+ return true
+ }
+ return false
+}
+func rewriteValueAMD64_OpAMD64VCVTQQ2PSYMasked128(v *Value) bool {
+ v_1 := v.Args[1]
+ v_0 := v.Args[0]
+ // match: (VCVTQQ2PSYMasked128 l:(VMOVDQUload256 {sym} [off] ptr mem) mask)
+ // cond: canMergeLoad(v, l) && clobber(l)
+ // result: (VCVTQQ2PSYMasked128load {sym} [off] ptr mask mem)
+ for {
+ l := v_0
+ if l.Op != OpAMD64VMOVDQUload256 {
+ break
+ }
+ off := auxIntToInt32(l.AuxInt)
+ sym := auxToSym(l.Aux)
+ mem := l.Args[1]
+ ptr := l.Args[0]
+ mask := v_1
+ if !(canMergeLoad(v, l) && clobber(l)) {
+ break
+ }
+ v.reset(OpAMD64VCVTQQ2PSYMasked128load)
+ v.AuxInt = int32ToAuxInt(off)
+ v.Aux = symToAux(sym)
+ v.AddArg3(ptr, mask, mem)
+ return true
+ }
+ return false
+}
func rewriteValueAMD64_OpAMD64VCVTTPD2DQ256(v *Value) bool {
v_0 := v.Args[0]
// match: (VCVTTPD2DQ256 l:(VMOVDQUload512 {sym} [off] ptr mem))
}
return false
}
+func rewriteValueAMD64_OpAMD64VCVTUDQ2PD256(v *Value) bool {
+ v_0 := v.Args[0]
+ // match: (VCVTUDQ2PD256 l:(VMOVDQUload128 {sym} [off] ptr mem))
+ // cond: canMergeLoad(v, l) && clobber(l)
+ // result: (VCVTUDQ2PD256load {sym} [off] ptr mem)
+ for {
+ l := v_0
+ if l.Op != OpAMD64VMOVDQUload128 {
+ break
+ }
+ off := auxIntToInt32(l.AuxInt)
+ sym := auxToSym(l.Aux)
+ mem := l.Args[1]
+ ptr := l.Args[0]
+ if !(canMergeLoad(v, l) && clobber(l)) {
+ break
+ }
+ v.reset(OpAMD64VCVTUDQ2PD256load)
+ v.AuxInt = int32ToAuxInt(off)
+ v.Aux = symToAux(sym)
+ v.AddArg2(ptr, mem)
+ return true
+ }
+ return false
+}
+func rewriteValueAMD64_OpAMD64VCVTUDQ2PD512(v *Value) bool {
+ v_0 := v.Args[0]
+ // match: (VCVTUDQ2PD512 l:(VMOVDQUload256 {sym} [off] ptr mem))
+ // cond: canMergeLoad(v, l) && clobber(l)
+ // result: (VCVTUDQ2PD512load {sym} [off] ptr mem)
+ for {
+ l := v_0
+ if l.Op != OpAMD64VMOVDQUload256 {
+ break
+ }
+ off := auxIntToInt32(l.AuxInt)
+ sym := auxToSym(l.Aux)
+ mem := l.Args[1]
+ ptr := l.Args[0]
+ if !(canMergeLoad(v, l) && clobber(l)) {
+ break
+ }
+ v.reset(OpAMD64VCVTUDQ2PD512load)
+ v.AuxInt = int32ToAuxInt(off)
+ v.Aux = symToAux(sym)
+ v.AddArg2(ptr, mem)
+ return true
+ }
+ return false
+}
+func rewriteValueAMD64_OpAMD64VCVTUDQ2PDMasked256(v *Value) bool {
+ v_1 := v.Args[1]
+ v_0 := v.Args[0]
+ // match: (VCVTUDQ2PDMasked256 l:(VMOVDQUload128 {sym} [off] ptr mem) mask)
+ // cond: canMergeLoad(v, l) && clobber(l)
+ // result: (VCVTUDQ2PDMasked256load {sym} [off] ptr mask mem)
+ for {
+ l := v_0
+ if l.Op != OpAMD64VMOVDQUload128 {
+ break
+ }
+ off := auxIntToInt32(l.AuxInt)
+ sym := auxToSym(l.Aux)
+ mem := l.Args[1]
+ ptr := l.Args[0]
+ mask := v_1
+ if !(canMergeLoad(v, l) && clobber(l)) {
+ break
+ }
+ v.reset(OpAMD64VCVTUDQ2PDMasked256load)
+ v.AuxInt = int32ToAuxInt(off)
+ v.Aux = symToAux(sym)
+ v.AddArg3(ptr, mask, mem)
+ return true
+ }
+ return false
+}
+func rewriteValueAMD64_OpAMD64VCVTUDQ2PDMasked512(v *Value) bool {
+ v_1 := v.Args[1]
+ v_0 := v.Args[0]
+ // match: (VCVTUDQ2PDMasked512 l:(VMOVDQUload256 {sym} [off] ptr mem) mask)
+ // cond: canMergeLoad(v, l) && clobber(l)
+ // result: (VCVTUDQ2PDMasked512load {sym} [off] ptr mask mem)
+ for {
+ l := v_0
+ if l.Op != OpAMD64VMOVDQUload256 {
+ break
+ }
+ off := auxIntToInt32(l.AuxInt)
+ sym := auxToSym(l.Aux)
+ mem := l.Args[1]
+ ptr := l.Args[0]
+ mask := v_1
+ if !(canMergeLoad(v, l) && clobber(l)) {
+ break
+ }
+ v.reset(OpAMD64VCVTUDQ2PDMasked512load)
+ v.AuxInt = int32ToAuxInt(off)
+ v.Aux = symToAux(sym)
+ v.AddArg3(ptr, mask, mem)
+ return true
+ }
+ return false
+}
+func rewriteValueAMD64_OpAMD64VCVTUDQ2PS128(v *Value) bool {
+ v_0 := v.Args[0]
+ // match: (VCVTUDQ2PS128 l:(VMOVDQUload128 {sym} [off] ptr mem))
+ // cond: canMergeLoad(v, l) && clobber(l)
+ // result: (VCVTUDQ2PS128load {sym} [off] ptr mem)
+ for {
+ l := v_0
+ if l.Op != OpAMD64VMOVDQUload128 {
+ break
+ }
+ off := auxIntToInt32(l.AuxInt)
+ sym := auxToSym(l.Aux)
+ mem := l.Args[1]
+ ptr := l.Args[0]
+ if !(canMergeLoad(v, l) && clobber(l)) {
+ break
+ }
+ v.reset(OpAMD64VCVTUDQ2PS128load)
+ v.AuxInt = int32ToAuxInt(off)
+ v.Aux = symToAux(sym)
+ v.AddArg2(ptr, mem)
+ return true
+ }
+ return false
+}
+func rewriteValueAMD64_OpAMD64VCVTUDQ2PS256(v *Value) bool {
+ v_0 := v.Args[0]
+ // match: (VCVTUDQ2PS256 l:(VMOVDQUload256 {sym} [off] ptr mem))
+ // cond: canMergeLoad(v, l) && clobber(l)
+ // result: (VCVTUDQ2PS256load {sym} [off] ptr mem)
+ for {
+ l := v_0
+ if l.Op != OpAMD64VMOVDQUload256 {
+ break
+ }
+ off := auxIntToInt32(l.AuxInt)
+ sym := auxToSym(l.Aux)
+ mem := l.Args[1]
+ ptr := l.Args[0]
+ if !(canMergeLoad(v, l) && clobber(l)) {
+ break
+ }
+ v.reset(OpAMD64VCVTUDQ2PS256load)
+ v.AuxInt = int32ToAuxInt(off)
+ v.Aux = symToAux(sym)
+ v.AddArg2(ptr, mem)
+ return true
+ }
+ return false
+}
+func rewriteValueAMD64_OpAMD64VCVTUDQ2PS512(v *Value) bool {
+ v_0 := v.Args[0]
+ // match: (VCVTUDQ2PS512 l:(VMOVDQUload512 {sym} [off] ptr mem))
+ // cond: canMergeLoad(v, l) && clobber(l)
+ // result: (VCVTUDQ2PS512load {sym} [off] ptr mem)
+ for {
+ l := v_0
+ if l.Op != OpAMD64VMOVDQUload512 {
+ break
+ }
+ off := auxIntToInt32(l.AuxInt)
+ sym := auxToSym(l.Aux)
+ mem := l.Args[1]
+ ptr := l.Args[0]
+ if !(canMergeLoad(v, l) && clobber(l)) {
+ break
+ }
+ v.reset(OpAMD64VCVTUDQ2PS512load)
+ v.AuxInt = int32ToAuxInt(off)
+ v.Aux = symToAux(sym)
+ v.AddArg2(ptr, mem)
+ return true
+ }
+ return false
+}
+func rewriteValueAMD64_OpAMD64VCVTUDQ2PSMasked128(v *Value) bool {
+ v_1 := v.Args[1]
+ v_0 := v.Args[0]
+ // match: (VCVTUDQ2PSMasked128 l:(VMOVDQUload128 {sym} [off] ptr mem) mask)
+ // cond: canMergeLoad(v, l) && clobber(l)
+ // result: (VCVTUDQ2PSMasked128load {sym} [off] ptr mask mem)
+ for {
+ l := v_0
+ if l.Op != OpAMD64VMOVDQUload128 {
+ break
+ }
+ off := auxIntToInt32(l.AuxInt)
+ sym := auxToSym(l.Aux)
+ mem := l.Args[1]
+ ptr := l.Args[0]
+ mask := v_1
+ if !(canMergeLoad(v, l) && clobber(l)) {
+ break
+ }
+ v.reset(OpAMD64VCVTUDQ2PSMasked128load)
+ v.AuxInt = int32ToAuxInt(off)
+ v.Aux = symToAux(sym)
+ v.AddArg3(ptr, mask, mem)
+ return true
+ }
+ return false
+}
+func rewriteValueAMD64_OpAMD64VCVTUDQ2PSMasked256(v *Value) bool {
+ v_1 := v.Args[1]
+ v_0 := v.Args[0]
+ // match: (VCVTUDQ2PSMasked256 l:(VMOVDQUload256 {sym} [off] ptr mem) mask)
+ // cond: canMergeLoad(v, l) && clobber(l)
+ // result: (VCVTUDQ2PSMasked256load {sym} [off] ptr mask mem)
+ for {
+ l := v_0
+ if l.Op != OpAMD64VMOVDQUload256 {
+ break
+ }
+ off := auxIntToInt32(l.AuxInt)
+ sym := auxToSym(l.Aux)
+ mem := l.Args[1]
+ ptr := l.Args[0]
+ mask := v_1
+ if !(canMergeLoad(v, l) && clobber(l)) {
+ break
+ }
+ v.reset(OpAMD64VCVTUDQ2PSMasked256load)
+ v.AuxInt = int32ToAuxInt(off)
+ v.Aux = symToAux(sym)
+ v.AddArg3(ptr, mask, mem)
+ return true
+ }
+ return false
+}
+func rewriteValueAMD64_OpAMD64VCVTUDQ2PSMasked512(v *Value) bool {
+ v_1 := v.Args[1]
+ v_0 := v.Args[0]
+ // match: (VCVTUDQ2PSMasked512 l:(VMOVDQUload512 {sym} [off] ptr mem) mask)
+ // cond: canMergeLoad(v, l) && clobber(l)
+ // result: (VCVTUDQ2PSMasked512load {sym} [off] ptr mask mem)
+ for {
+ l := v_0
+ if l.Op != OpAMD64VMOVDQUload512 {
+ break
+ }
+ off := auxIntToInt32(l.AuxInt)
+ sym := auxToSym(l.Aux)
+ mem := l.Args[1]
+ ptr := l.Args[0]
+ mask := v_1
+ if !(canMergeLoad(v, l) && clobber(l)) {
+ break
+ }
+ v.reset(OpAMD64VCVTUDQ2PSMasked512load)
+ v.AuxInt = int32ToAuxInt(off)
+ v.Aux = symToAux(sym)
+ v.AddArg3(ptr, mask, mem)
+ return true
+ }
+ return false
+}
+func rewriteValueAMD64_OpAMD64VCVTUQQ2PD128(v *Value) bool {
+ v_0 := v.Args[0]
+ // match: (VCVTUQQ2PD128 l:(VMOVDQUload128 {sym} [off] ptr mem))
+ // cond: canMergeLoad(v, l) && clobber(l)
+ // result: (VCVTUQQ2PD128load {sym} [off] ptr mem)
+ for {
+ l := v_0
+ if l.Op != OpAMD64VMOVDQUload128 {
+ break
+ }
+ off := auxIntToInt32(l.AuxInt)
+ sym := auxToSym(l.Aux)
+ mem := l.Args[1]
+ ptr := l.Args[0]
+ if !(canMergeLoad(v, l) && clobber(l)) {
+ break
+ }
+ v.reset(OpAMD64VCVTUQQ2PD128load)
+ v.AuxInt = int32ToAuxInt(off)
+ v.Aux = symToAux(sym)
+ v.AddArg2(ptr, mem)
+ return true
+ }
+ return false
+}
+func rewriteValueAMD64_OpAMD64VCVTUQQ2PD256(v *Value) bool {
+ v_0 := v.Args[0]
+ // match: (VCVTUQQ2PD256 l:(VMOVDQUload256 {sym} [off] ptr mem))
+ // cond: canMergeLoad(v, l) && clobber(l)
+ // result: (VCVTUQQ2PD256load {sym} [off] ptr mem)
+ for {
+ l := v_0
+ if l.Op != OpAMD64VMOVDQUload256 {
+ break
+ }
+ off := auxIntToInt32(l.AuxInt)
+ sym := auxToSym(l.Aux)
+ mem := l.Args[1]
+ ptr := l.Args[0]
+ if !(canMergeLoad(v, l) && clobber(l)) {
+ break
+ }
+ v.reset(OpAMD64VCVTUQQ2PD256load)
+ v.AuxInt = int32ToAuxInt(off)
+ v.Aux = symToAux(sym)
+ v.AddArg2(ptr, mem)
+ return true
+ }
+ return false
+}
+func rewriteValueAMD64_OpAMD64VCVTUQQ2PD512(v *Value) bool {
+ v_0 := v.Args[0]
+ // match: (VCVTUQQ2PD512 l:(VMOVDQUload512 {sym} [off] ptr mem))
+ // cond: canMergeLoad(v, l) && clobber(l)
+ // result: (VCVTUQQ2PD512load {sym} [off] ptr mem)
+ for {
+ l := v_0
+ if l.Op != OpAMD64VMOVDQUload512 {
+ break
+ }
+ off := auxIntToInt32(l.AuxInt)
+ sym := auxToSym(l.Aux)
+ mem := l.Args[1]
+ ptr := l.Args[0]
+ if !(canMergeLoad(v, l) && clobber(l)) {
+ break
+ }
+ v.reset(OpAMD64VCVTUQQ2PD512load)
+ v.AuxInt = int32ToAuxInt(off)
+ v.Aux = symToAux(sym)
+ v.AddArg2(ptr, mem)
+ return true
+ }
+ return false
+}
+func rewriteValueAMD64_OpAMD64VCVTUQQ2PDMasked128(v *Value) bool {
+ v_1 := v.Args[1]
+ v_0 := v.Args[0]
+ // match: (VCVTUQQ2PDMasked128 l:(VMOVDQUload128 {sym} [off] ptr mem) mask)
+ // cond: canMergeLoad(v, l) && clobber(l)
+ // result: (VCVTUQQ2PDMasked128load {sym} [off] ptr mask mem)
+ for {
+ l := v_0
+ if l.Op != OpAMD64VMOVDQUload128 {
+ break
+ }
+ off := auxIntToInt32(l.AuxInt)
+ sym := auxToSym(l.Aux)
+ mem := l.Args[1]
+ ptr := l.Args[0]
+ mask := v_1
+ if !(canMergeLoad(v, l) && clobber(l)) {
+ break
+ }
+ v.reset(OpAMD64VCVTUQQ2PDMasked128load)
+ v.AuxInt = int32ToAuxInt(off)
+ v.Aux = symToAux(sym)
+ v.AddArg3(ptr, mask, mem)
+ return true
+ }
+ return false
+}
+func rewriteValueAMD64_OpAMD64VCVTUQQ2PDMasked256(v *Value) bool {
+ v_1 := v.Args[1]
+ v_0 := v.Args[0]
+ // match: (VCVTUQQ2PDMasked256 l:(VMOVDQUload256 {sym} [off] ptr mem) mask)
+ // cond: canMergeLoad(v, l) && clobber(l)
+ // result: (VCVTUQQ2PDMasked256load {sym} [off] ptr mask mem)
+ for {
+ l := v_0
+ if l.Op != OpAMD64VMOVDQUload256 {
+ break
+ }
+ off := auxIntToInt32(l.AuxInt)
+ sym := auxToSym(l.Aux)
+ mem := l.Args[1]
+ ptr := l.Args[0]
+ mask := v_1
+ if !(canMergeLoad(v, l) && clobber(l)) {
+ break
+ }
+ v.reset(OpAMD64VCVTUQQ2PDMasked256load)
+ v.AuxInt = int32ToAuxInt(off)
+ v.Aux = symToAux(sym)
+ v.AddArg3(ptr, mask, mem)
+ return true
+ }
+ return false
+}
+func rewriteValueAMD64_OpAMD64VCVTUQQ2PDMasked512(v *Value) bool {
+ v_1 := v.Args[1]
+ v_0 := v.Args[0]
+ // match: (VCVTUQQ2PDMasked512 l:(VMOVDQUload512 {sym} [off] ptr mem) mask)
+ // cond: canMergeLoad(v, l) && clobber(l)
+ // result: (VCVTUQQ2PDMasked512load {sym} [off] ptr mask mem)
+ for {
+ l := v_0
+ if l.Op != OpAMD64VMOVDQUload512 {
+ break
+ }
+ off := auxIntToInt32(l.AuxInt)
+ sym := auxToSym(l.Aux)
+ mem := l.Args[1]
+ ptr := l.Args[0]
+ mask := v_1
+ if !(canMergeLoad(v, l) && clobber(l)) {
+ break
+ }
+ v.reset(OpAMD64VCVTUQQ2PDMasked512load)
+ v.AuxInt = int32ToAuxInt(off)
+ v.Aux = symToAux(sym)
+ v.AddArg3(ptr, mask, mem)
+ return true
+ }
+ return false
+}
+func rewriteValueAMD64_OpAMD64VCVTUQQ2PS256(v *Value) bool {
+ v_0 := v.Args[0]
+ // match: (VCVTUQQ2PS256 l:(VMOVDQUload512 {sym} [off] ptr mem))
+ // cond: canMergeLoad(v, l) && clobber(l)
+ // result: (VCVTUQQ2PS256load {sym} [off] ptr mem)
+ for {
+ l := v_0
+ if l.Op != OpAMD64VMOVDQUload512 {
+ break
+ }
+ off := auxIntToInt32(l.AuxInt)
+ sym := auxToSym(l.Aux)
+ mem := l.Args[1]
+ ptr := l.Args[0]
+ if !(canMergeLoad(v, l) && clobber(l)) {
+ break
+ }
+ v.reset(OpAMD64VCVTUQQ2PS256load)
+ v.AuxInt = int32ToAuxInt(off)
+ v.Aux = symToAux(sym)
+ v.AddArg2(ptr, mem)
+ return true
+ }
+ return false
+}
+func rewriteValueAMD64_OpAMD64VCVTUQQ2PSMasked256(v *Value) bool {
+ v_1 := v.Args[1]
+ v_0 := v.Args[0]
+ // match: (VCVTUQQ2PSMasked256 l:(VMOVDQUload512 {sym} [off] ptr mem) mask)
+ // cond: canMergeLoad(v, l) && clobber(l)
+ // result: (VCVTUQQ2PSMasked256load {sym} [off] ptr mask mem)
+ for {
+ l := v_0
+ if l.Op != OpAMD64VMOVDQUload512 {
+ break
+ }
+ off := auxIntToInt32(l.AuxInt)
+ sym := auxToSym(l.Aux)
+ mem := l.Args[1]
+ ptr := l.Args[0]
+ mask := v_1
+ if !(canMergeLoad(v, l) && clobber(l)) {
+ break
+ }
+ v.reset(OpAMD64VCVTUQQ2PSMasked256load)
+ v.AuxInt = int32ToAuxInt(off)
+ v.Aux = symToAux(sym)
+ v.AddArg3(ptr, mask, mem)
+ return true
+ }
+ return false
+}
+func rewriteValueAMD64_OpAMD64VCVTUQQ2PSX128(v *Value) bool {
+ v_0 := v.Args[0]
+ // match: (VCVTUQQ2PSX128 l:(VMOVDQUload128 {sym} [off] ptr mem))
+ // cond: canMergeLoad(v, l) && clobber(l)
+ // result: (VCVTUQQ2PSX128load {sym} [off] ptr mem)
+ for {
+ l := v_0
+ if l.Op != OpAMD64VMOVDQUload128 {
+ break
+ }
+ off := auxIntToInt32(l.AuxInt)
+ sym := auxToSym(l.Aux)
+ mem := l.Args[1]
+ ptr := l.Args[0]
+ if !(canMergeLoad(v, l) && clobber(l)) {
+ break
+ }
+ v.reset(OpAMD64VCVTUQQ2PSX128load)
+ v.AuxInt = int32ToAuxInt(off)
+ v.Aux = symToAux(sym)
+ v.AddArg2(ptr, mem)
+ return true
+ }
+ return false
+}
+func rewriteValueAMD64_OpAMD64VCVTUQQ2PSXMasked128(v *Value) bool {
+ v_1 := v.Args[1]
+ v_0 := v.Args[0]
+ // match: (VCVTUQQ2PSXMasked128 l:(VMOVDQUload128 {sym} [off] ptr mem) mask)
+ // cond: canMergeLoad(v, l) && clobber(l)
+ // result: (VCVTUQQ2PSXMasked128load {sym} [off] ptr mask mem)
+ for {
+ l := v_0
+ if l.Op != OpAMD64VMOVDQUload128 {
+ break
+ }
+ off := auxIntToInt32(l.AuxInt)
+ sym := auxToSym(l.Aux)
+ mem := l.Args[1]
+ ptr := l.Args[0]
+ mask := v_1
+ if !(canMergeLoad(v, l) && clobber(l)) {
+ break
+ }
+ v.reset(OpAMD64VCVTUQQ2PSXMasked128load)
+ v.AuxInt = int32ToAuxInt(off)
+ v.Aux = symToAux(sym)
+ v.AddArg3(ptr, mask, mem)
+ return true
+ }
+ return false
+}
+func rewriteValueAMD64_OpAMD64VCVTUQQ2PSY128(v *Value) bool {
+ v_0 := v.Args[0]
+ // match: (VCVTUQQ2PSY128 l:(VMOVDQUload256 {sym} [off] ptr mem))
+ // cond: canMergeLoad(v, l) && clobber(l)
+ // result: (VCVTUQQ2PSY128load {sym} [off] ptr mem)
+ for {
+ l := v_0
+ if l.Op != OpAMD64VMOVDQUload256 {
+ break
+ }
+ off := auxIntToInt32(l.AuxInt)
+ sym := auxToSym(l.Aux)
+ mem := l.Args[1]
+ ptr := l.Args[0]
+ if !(canMergeLoad(v, l) && clobber(l)) {
+ break
+ }
+ v.reset(OpAMD64VCVTUQQ2PSY128load)
+ v.AuxInt = int32ToAuxInt(off)
+ v.Aux = symToAux(sym)
+ v.AddArg2(ptr, mem)
+ return true
+ }
+ return false
+}
+func rewriteValueAMD64_OpAMD64VCVTUQQ2PSYMasked128(v *Value) bool {
+ v_1 := v.Args[1]
+ v_0 := v.Args[0]
+ // match: (VCVTUQQ2PSYMasked128 l:(VMOVDQUload256 {sym} [off] ptr mem) mask)
+ // cond: canMergeLoad(v, l) && clobber(l)
+ // result: (VCVTUQQ2PSYMasked128load {sym} [off] ptr mask mem)
+ for {
+ l := v_0
+ if l.Op != OpAMD64VMOVDQUload256 {
+ break
+ }
+ off := auxIntToInt32(l.AuxInt)
+ sym := auxToSym(l.Aux)
+ mem := l.Args[1]
+ ptr := l.Args[0]
+ mask := v_1
+ if !(canMergeLoad(v, l) && clobber(l)) {
+ break
+ }
+ v.reset(OpAMD64VCVTUQQ2PSYMasked128load)
+ v.AuxInt = int32ToAuxInt(off)
+ v.Aux = symToAux(sym)
+ v.AddArg3(ptr, mask, mem)
+ return true
+ }
+ return false
+}
func rewriteValueAMD64_OpAMD64VDIVPD512(v *Value) bool {
v_1 := v.Args[1]
v_0 := v.Args[0]
v.AddArg4(x, y, z, mask)
return true
}
+ // match: (VMOVDQU32Masked128 (VCVTDQ2PS128 x) mask)
+ // result: (VCVTDQ2PSMasked128 x mask)
+ for {
+ if v_0.Op != OpAMD64VCVTDQ2PS128 {
+ break
+ }
+ x := v_0.Args[0]
+ mask := v_1
+ v.reset(OpAMD64VCVTDQ2PSMasked128)
+ v.AddArg2(x, mask)
+ return true
+ }
+ // match: (VMOVDQU32Masked128 (VCVTUDQ2PS128 x) mask)
+ // result: (VCVTUDQ2PSMasked128 x mask)
+ for {
+ if v_0.Op != OpAMD64VCVTUDQ2PS128 {
+ break
+ }
+ x := v_0.Args[0]
+ mask := v_1
+ v.reset(OpAMD64VCVTUDQ2PSMasked128)
+ v.AddArg2(x, mask)
+ return true
+ }
// match: (VMOVDQU32Masked128 (VCVTTPS2DQ128 x) mask)
// result: (VCVTTPS2DQMasked128 x mask)
for {
v.AddArg4(x, y, z, mask)
return true
}
+ // match: (VMOVDQU32Masked256 (VCVTDQ2PS256 x) mask)
+ // result: (VCVTDQ2PSMasked256 x mask)
+ for {
+ if v_0.Op != OpAMD64VCVTDQ2PS256 {
+ break
+ }
+ x := v_0.Args[0]
+ mask := v_1
+ v.reset(OpAMD64VCVTDQ2PSMasked256)
+ v.AddArg2(x, mask)
+ return true
+ }
+ // match: (VMOVDQU32Masked256 (VCVTUDQ2PS256 x) mask)
+ // result: (VCVTUDQ2PSMasked256 x mask)
+ for {
+ if v_0.Op != OpAMD64VCVTUDQ2PS256 {
+ break
+ }
+ x := v_0.Args[0]
+ mask := v_1
+ v.reset(OpAMD64VCVTUDQ2PSMasked256)
+ v.AddArg2(x, mask)
+ return true
+ }
+ // match: (VMOVDQU32Masked256 (VCVTDQ2PD256 x) mask)
+ // result: (VCVTDQ2PDMasked256 x mask)
+ for {
+ if v_0.Op != OpAMD64VCVTDQ2PD256 {
+ break
+ }
+ x := v_0.Args[0]
+ mask := v_1
+ v.reset(OpAMD64VCVTDQ2PDMasked256)
+ v.AddArg2(x, mask)
+ return true
+ }
+ // match: (VMOVDQU32Masked256 (VCVTUDQ2PD256 x) mask)
+ // result: (VCVTUDQ2PDMasked256 x mask)
+ for {
+ if v_0.Op != OpAMD64VCVTUDQ2PD256 {
+ break
+ }
+ x := v_0.Args[0]
+ mask := v_1
+ v.reset(OpAMD64VCVTUDQ2PDMasked256)
+ v.AddArg2(x, mask)
+ return true
+ }
// match: (VMOVDQU32Masked256 (VCVTTPS2DQ256 x) mask)
// result: (VCVTTPS2DQMasked256 x mask)
for {
v.AddArg4(x, y, z, mask)
return true
}
+ // match: (VMOVDQU32Masked512 (VCVTDQ2PS512 x) mask)
+ // result: (VCVTDQ2PSMasked512 x mask)
+ for {
+ if v_0.Op != OpAMD64VCVTDQ2PS512 {
+ break
+ }
+ x := v_0.Args[0]
+ mask := v_1
+ v.reset(OpAMD64VCVTDQ2PSMasked512)
+ v.AddArg2(x, mask)
+ return true
+ }
+ // match: (VMOVDQU32Masked512 (VCVTUDQ2PS512 x) mask)
+ // result: (VCVTUDQ2PSMasked512 x mask)
+ for {
+ if v_0.Op != OpAMD64VCVTUDQ2PS512 {
+ break
+ }
+ x := v_0.Args[0]
+ mask := v_1
+ v.reset(OpAMD64VCVTUDQ2PSMasked512)
+ v.AddArg2(x, mask)
+ return true
+ }
+ // match: (VMOVDQU32Masked512 (VCVTDQ2PD512 x) mask)
+ // result: (VCVTDQ2PDMasked512 x mask)
+ for {
+ if v_0.Op != OpAMD64VCVTDQ2PD512 {
+ break
+ }
+ x := v_0.Args[0]
+ mask := v_1
+ v.reset(OpAMD64VCVTDQ2PDMasked512)
+ v.AddArg2(x, mask)
+ return true
+ }
+ // match: (VMOVDQU32Masked512 (VCVTUDQ2PD512 x) mask)
+ // result: (VCVTUDQ2PDMasked512 x mask)
+ for {
+ if v_0.Op != OpAMD64VCVTUDQ2PD512 {
+ break
+ }
+ x := v_0.Args[0]
+ mask := v_1
+ v.reset(OpAMD64VCVTUDQ2PDMasked512)
+ v.AddArg2(x, mask)
+ return true
+ }
// match: (VMOVDQU32Masked512 (VCVTTPS2DQ512 x) mask)
// result: (VCVTTPS2DQMasked512 x mask)
for {
v.AddArg4(x, y, z, mask)
return true
}
+ // match: (VMOVDQU64Masked128 (VCVTQQ2PSX128 x) mask)
+ // result: (VCVTQQ2PSXMasked128 x mask)
+ for {
+ if v_0.Op != OpAMD64VCVTQQ2PSX128 {
+ break
+ }
+ x := v_0.Args[0]
+ mask := v_1
+ v.reset(OpAMD64VCVTQQ2PSXMasked128)
+ v.AddArg2(x, mask)
+ return true
+ }
+ // match: (VMOVDQU64Masked128 (VCVTQQ2PSY128 x) mask)
+ // result: (VCVTQQ2PSYMasked128 x mask)
+ for {
+ if v_0.Op != OpAMD64VCVTQQ2PSY128 {
+ break
+ }
+ x := v_0.Args[0]
+ mask := v_1
+ v.reset(OpAMD64VCVTQQ2PSYMasked128)
+ v.AddArg2(x, mask)
+ return true
+ }
+ // match: (VMOVDQU64Masked128 (VCVTUQQ2PSX128 x) mask)
+ // result: (VCVTUQQ2PSXMasked128 x mask)
+ for {
+ if v_0.Op != OpAMD64VCVTUQQ2PSX128 {
+ break
+ }
+ x := v_0.Args[0]
+ mask := v_1
+ v.reset(OpAMD64VCVTUQQ2PSXMasked128)
+ v.AddArg2(x, mask)
+ return true
+ }
+ // match: (VMOVDQU64Masked128 (VCVTUQQ2PSY128 x) mask)
+ // result: (VCVTUQQ2PSYMasked128 x mask)
+ for {
+ if v_0.Op != OpAMD64VCVTUQQ2PSY128 {
+ break
+ }
+ x := v_0.Args[0]
+ mask := v_1
+ v.reset(OpAMD64VCVTUQQ2PSYMasked128)
+ v.AddArg2(x, mask)
+ return true
+ }
+ // match: (VMOVDQU64Masked128 (VCVTQQ2PD128 x) mask)
+ // result: (VCVTQQ2PDMasked128 x mask)
+ for {
+ if v_0.Op != OpAMD64VCVTQQ2PD128 {
+ break
+ }
+ x := v_0.Args[0]
+ mask := v_1
+ v.reset(OpAMD64VCVTQQ2PDMasked128)
+ v.AddArg2(x, mask)
+ return true
+ }
+ // match: (VMOVDQU64Masked128 (VCVTUQQ2PD128 x) mask)
+ // result: (VCVTUQQ2PDMasked128 x mask)
+ for {
+ if v_0.Op != OpAMD64VCVTUQQ2PD128 {
+ break
+ }
+ x := v_0.Args[0]
+ mask := v_1
+ v.reset(OpAMD64VCVTUQQ2PDMasked128)
+ v.AddArg2(x, mask)
+ return true
+ }
// match: (VMOVDQU64Masked128 (VCVTTPD2DQX128 x) mask)
// result: (VCVTTPD2DQXMasked128 x mask)
for {
v.AddArg4(x, y, z, mask)
return true
}
+ // match: (VMOVDQU64Masked256 (VCVTQQ2PS256 x) mask)
+ // result: (VCVTQQ2PSMasked256 x mask)
+ for {
+ if v_0.Op != OpAMD64VCVTQQ2PS256 {
+ break
+ }
+ x := v_0.Args[0]
+ mask := v_1
+ v.reset(OpAMD64VCVTQQ2PSMasked256)
+ v.AddArg2(x, mask)
+ return true
+ }
+ // match: (VMOVDQU64Masked256 (VCVTUQQ2PS256 x) mask)
+ // result: (VCVTUQQ2PSMasked256 x mask)
+ for {
+ if v_0.Op != OpAMD64VCVTUQQ2PS256 {
+ break
+ }
+ x := v_0.Args[0]
+ mask := v_1
+ v.reset(OpAMD64VCVTUQQ2PSMasked256)
+ v.AddArg2(x, mask)
+ return true
+ }
+ // match: (VMOVDQU64Masked256 (VCVTQQ2PD256 x) mask)
+ // result: (VCVTQQ2PDMasked256 x mask)
+ for {
+ if v_0.Op != OpAMD64VCVTQQ2PD256 {
+ break
+ }
+ x := v_0.Args[0]
+ mask := v_1
+ v.reset(OpAMD64VCVTQQ2PDMasked256)
+ v.AddArg2(x, mask)
+ return true
+ }
+ // match: (VMOVDQU64Masked256 (VCVTUQQ2PD256 x) mask)
+ // result: (VCVTUQQ2PDMasked256 x mask)
+ for {
+ if v_0.Op != OpAMD64VCVTUQQ2PD256 {
+ break
+ }
+ x := v_0.Args[0]
+ mask := v_1
+ v.reset(OpAMD64VCVTUQQ2PDMasked256)
+ v.AddArg2(x, mask)
+ return true
+ }
// match: (VMOVDQU64Masked256 (VCVTTPD2DQ256 x) mask)
// result: (VCVTTPD2DQMasked256 x mask)
for {
v.AddArg4(x, y, z, mask)
return true
}
+ // match: (VMOVDQU64Masked512 (VCVTQQ2PD512 x) mask)
+ // result: (VCVTQQ2PDMasked512 x mask)
+ for {
+ if v_0.Op != OpAMD64VCVTQQ2PD512 {
+ break
+ }
+ x := v_0.Args[0]
+ mask := v_1
+ v.reset(OpAMD64VCVTQQ2PDMasked512)
+ v.AddArg2(x, mask)
+ return true
+ }
+ // match: (VMOVDQU64Masked512 (VCVTUQQ2PD512 x) mask)
+ // result: (VCVTUQQ2PDMasked512 x mask)
+ for {
+ if v_0.Op != OpAMD64VCVTUQQ2PD512 {
+ break
+ }
+ x := v_0.Args[0]
+ mask := v_1
+ v.reset(OpAMD64VCVTUQQ2PDMasked512)
+ v.AddArg2(x, mask)
+ return true
+ }
// match: (VMOVDQU64Masked512 (VCVTTPD2QQ512 x) mask)
// result: (VCVTTPD2QQMasked512 x mask)
for {
v.AddArg4(dst, x, y, mask)
return true
}
+ // match: (VPBLENDMDMasked512 dst (VCVTDQ2PS512 x) mask)
+ // result: (VCVTDQ2PSMasked512Merging dst x mask)
+ for {
+ dst := v_0
+ if v_1.Op != OpAMD64VCVTDQ2PS512 {
+ break
+ }
+ x := v_1.Args[0]
+ mask := v_2
+ v.reset(OpAMD64VCVTDQ2PSMasked512Merging)
+ v.AddArg3(dst, x, mask)
+ return true
+ }
// match: (VPBLENDMDMasked512 dst (VCVTTPS2DQ512 x) mask)
// result: (VCVTTPS2DQMasked512Merging dst x mask)
for {
v.AddArg3(dst, x, mask)
return true
}
+ // match: (VPBLENDMDMasked512 dst (VCVTUDQ2PS512 x) mask)
+ // result: (VCVTUDQ2PSMasked512Merging dst x mask)
+ for {
+ dst := v_0
+ if v_1.Op != OpAMD64VCVTUDQ2PS512 {
+ break
+ }
+ x := v_1.Args[0]
+ mask := v_2
+ v.reset(OpAMD64VCVTUDQ2PSMasked512Merging)
+ v.AddArg3(dst, x, mask)
+ return true
+ }
// match: (VPBLENDMDMasked512 dst (VDIVPS512 x y) mask)
// result: (VDIVPSMasked512Merging dst x y mask)
for {
v.AddArg4(dst, x, y, mask)
return true
}
+ // match: (VPBLENDMQMasked512 dst (VCVTQQ2PD512 x) mask)
+ // result: (VCVTQQ2PDMasked512Merging dst x mask)
+ for {
+ dst := v_0
+ if v_1.Op != OpAMD64VCVTQQ2PD512 {
+ break
+ }
+ x := v_1.Args[0]
+ mask := v_2
+ v.reset(OpAMD64VCVTQQ2PDMasked512Merging)
+ v.AddArg3(dst, x, mask)
+ return true
+ }
+ // match: (VPBLENDMQMasked512 dst (VCVTQQ2PS256 x) mask)
+ // result: (VCVTQQ2PSMasked256Merging dst x mask)
+ for {
+ dst := v_0
+ if v_1.Op != OpAMD64VCVTQQ2PS256 {
+ break
+ }
+ x := v_1.Args[0]
+ mask := v_2
+ v.reset(OpAMD64VCVTQQ2PSMasked256Merging)
+ v.AddArg3(dst, x, mask)
+ return true
+ }
// match: (VPBLENDMQMasked512 dst (VCVTTPD2DQ256 x) mask)
// result: (VCVTTPD2DQMasked256Merging dst x mask)
for {
v.AddArg3(dst, x, mask)
return true
}
+ // match: (VPBLENDMQMasked512 dst (VCVTUQQ2PD512 x) mask)
+ // result: (VCVTUQQ2PDMasked512Merging dst x mask)
+ for {
+ dst := v_0
+ if v_1.Op != OpAMD64VCVTUQQ2PD512 {
+ break
+ }
+ x := v_1.Args[0]
+ mask := v_2
+ v.reset(OpAMD64VCVTUQQ2PDMasked512Merging)
+ v.AddArg3(dst, x, mask)
+ return true
+ }
+ // match: (VPBLENDMQMasked512 dst (VCVTUQQ2PS256 x) mask)
+ // result: (VCVTUQQ2PSMasked256Merging dst x mask)
+ for {
+ dst := v_0
+ if v_1.Op != OpAMD64VCVTUQQ2PS256 {
+ break
+ }
+ x := v_1.Args[0]
+ mask := v_2
+ v.reset(OpAMD64VCVTUQQ2PSMasked256Merging)
+ v.AddArg3(dst, x, mask)
+ return true
+ }
// match: (VPBLENDMQMasked512 dst (VDIVPD512 x y) mask)
// result: (VDIVPDMasked512Merging dst x y mask)
for {
v.AddArg3(dst, x, v0)
return true
}
+ // match: (VPBLENDVB128 dst (VCVTDQ2PD256 x) mask)
+ // cond: v.Block.CPUfeatures.hasFeature(CPUavx512)
+ // result: (VCVTDQ2PDMasked256Merging dst x (VPMOVVec32x4ToM <types.TypeMask> mask))
+ for {
+ dst := v_0
+ if v_1.Op != OpAMD64VCVTDQ2PD256 {
+ break
+ }
+ x := v_1.Args[0]
+ mask := v_2
+ if !(v.Block.CPUfeatures.hasFeature(CPUavx512)) {
+ break
+ }
+ v.reset(OpAMD64VCVTDQ2PDMasked256Merging)
+ v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x4ToM, types.TypeMask)
+ v0.AddArg(mask)
+ v.AddArg3(dst, x, v0)
+ return true
+ }
+ // match: (VPBLENDVB128 dst (VCVTDQ2PS128 x) mask)
+ // cond: v.Block.CPUfeatures.hasFeature(CPUavx512)
+ // result: (VCVTDQ2PSMasked128Merging dst x (VPMOVVec32x4ToM <types.TypeMask> mask))
+ for {
+ dst := v_0
+ if v_1.Op != OpAMD64VCVTDQ2PS128 {
+ break
+ }
+ x := v_1.Args[0]
+ mask := v_2
+ if !(v.Block.CPUfeatures.hasFeature(CPUavx512)) {
+ break
+ }
+ v.reset(OpAMD64VCVTDQ2PSMasked128Merging)
+ v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x4ToM, types.TypeMask)
+ v0.AddArg(mask)
+ v.AddArg3(dst, x, v0)
+ return true
+ }
+ // match: (VPBLENDVB128 dst (VCVTQQ2PD128 x) mask)
+ // cond: v.Block.CPUfeatures.hasFeature(CPUavx512)
+ // result: (VCVTQQ2PDMasked128Merging dst x (VPMOVVec64x2ToM <types.TypeMask> mask))
+ for {
+ dst := v_0
+ if v_1.Op != OpAMD64VCVTQQ2PD128 {
+ break
+ }
+ x := v_1.Args[0]
+ mask := v_2
+ if !(v.Block.CPUfeatures.hasFeature(CPUavx512)) {
+ break
+ }
+ v.reset(OpAMD64VCVTQQ2PDMasked128Merging)
+ v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x2ToM, types.TypeMask)
+ v0.AddArg(mask)
+ v.AddArg3(dst, x, v0)
+ return true
+ }
+ // match: (VPBLENDVB128 dst (VCVTQQ2PSX128 x) mask)
+ // cond: v.Block.CPUfeatures.hasFeature(CPUavx512)
+ // result: (VCVTQQ2PSXMasked128Merging dst x (VPMOVVec64x2ToM <types.TypeMask> mask))
+ for {
+ dst := v_0
+ if v_1.Op != OpAMD64VCVTQQ2PSX128 {
+ break
+ }
+ x := v_1.Args[0]
+ mask := v_2
+ if !(v.Block.CPUfeatures.hasFeature(CPUavx512)) {
+ break
+ }
+ v.reset(OpAMD64VCVTQQ2PSXMasked128Merging)
+ v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x2ToM, types.TypeMask)
+ v0.AddArg(mask)
+ v.AddArg3(dst, x, v0)
+ return true
+ }
// match: (VPBLENDVB128 dst (VCVTTPD2DQX128 x) mask)
// cond: v.Block.CPUfeatures.hasFeature(CPUavx512)
// result: (VCVTTPD2DQXMasked128Merging dst x (VPMOVVec64x2ToM <types.TypeMask> mask))
v.AddArg3(dst, x, v0)
return true
}
+ // match: (VPBLENDVB128 dst (VCVTUDQ2PD256 x) mask)
+ // cond: v.Block.CPUfeatures.hasFeature(CPUavx512)
+ // result: (VCVTUDQ2PDMasked256Merging dst x (VPMOVVec32x4ToM <types.TypeMask> mask))
+ for {
+ dst := v_0
+ if v_1.Op != OpAMD64VCVTUDQ2PD256 {
+ break
+ }
+ x := v_1.Args[0]
+ mask := v_2
+ if !(v.Block.CPUfeatures.hasFeature(CPUavx512)) {
+ break
+ }
+ v.reset(OpAMD64VCVTUDQ2PDMasked256Merging)
+ v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x4ToM, types.TypeMask)
+ v0.AddArg(mask)
+ v.AddArg3(dst, x, v0)
+ return true
+ }
+ // match: (VPBLENDVB128 dst (VCVTUDQ2PS128 x) mask)
+ // cond: v.Block.CPUfeatures.hasFeature(CPUavx512)
+ // result: (VCVTUDQ2PSMasked128Merging dst x (VPMOVVec32x4ToM <types.TypeMask> mask))
+ for {
+ dst := v_0
+ if v_1.Op != OpAMD64VCVTUDQ2PS128 {
+ break
+ }
+ x := v_1.Args[0]
+ mask := v_2
+ if !(v.Block.CPUfeatures.hasFeature(CPUavx512)) {
+ break
+ }
+ v.reset(OpAMD64VCVTUDQ2PSMasked128Merging)
+ v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x4ToM, types.TypeMask)
+ v0.AddArg(mask)
+ v.AddArg3(dst, x, v0)
+ return true
+ }
+ // match: (VPBLENDVB128 dst (VCVTUQQ2PD128 x) mask)
+ // cond: v.Block.CPUfeatures.hasFeature(CPUavx512)
+ // result: (VCVTUQQ2PDMasked128Merging dst x (VPMOVVec64x2ToM <types.TypeMask> mask))
+ for {
+ dst := v_0
+ if v_1.Op != OpAMD64VCVTUQQ2PD128 {
+ break
+ }
+ x := v_1.Args[0]
+ mask := v_2
+ if !(v.Block.CPUfeatures.hasFeature(CPUavx512)) {
+ break
+ }
+ v.reset(OpAMD64VCVTUQQ2PDMasked128Merging)
+ v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x2ToM, types.TypeMask)
+ v0.AddArg(mask)
+ v.AddArg3(dst, x, v0)
+ return true
+ }
+ // match: (VPBLENDVB128 dst (VCVTUQQ2PSX128 x) mask)
+ // cond: v.Block.CPUfeatures.hasFeature(CPUavx512)
+ // result: (VCVTUQQ2PSXMasked128Merging dst x (VPMOVVec64x2ToM <types.TypeMask> mask))
+ for {
+ dst := v_0
+ if v_1.Op != OpAMD64VCVTUQQ2PSX128 {
+ break
+ }
+ x := v_1.Args[0]
+ mask := v_2
+ if !(v.Block.CPUfeatures.hasFeature(CPUavx512)) {
+ break
+ }
+ v.reset(OpAMD64VCVTUQQ2PSXMasked128Merging)
+ v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x2ToM, types.TypeMask)
+ v0.AddArg(mask)
+ v.AddArg3(dst, x, v0)
+ return true
+ }
// match: (VPBLENDVB128 dst (VDIVPD128 x y) mask)
// cond: v.Block.CPUfeatures.hasFeature(CPUavx512)
// result: (VDIVPDMasked128Merging dst x y (VPMOVVec64x2ToM <types.TypeMask> mask))
v.AddArg4(dst, x, y, v0)
return true
}
+ // match: (VPBLENDVB256 dst (VCVTDQ2PD512 x) mask)
+ // cond: v.Block.CPUfeatures.hasFeature(CPUavx512)
+ // result: (VCVTDQ2PDMasked512Merging dst x (VPMOVVec32x8ToM <types.TypeMask> mask))
+ for {
+ dst := v_0
+ if v_1.Op != OpAMD64VCVTDQ2PD512 {
+ break
+ }
+ x := v_1.Args[0]
+ mask := v_2
+ if !(v.Block.CPUfeatures.hasFeature(CPUavx512)) {
+ break
+ }
+ v.reset(OpAMD64VCVTDQ2PDMasked512Merging)
+ v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x8ToM, types.TypeMask)
+ v0.AddArg(mask)
+ v.AddArg3(dst, x, v0)
+ return true
+ }
+ // match: (VPBLENDVB256 dst (VCVTDQ2PS256 x) mask)
+ // cond: v.Block.CPUfeatures.hasFeature(CPUavx512)
+ // result: (VCVTDQ2PSMasked256Merging dst x (VPMOVVec32x8ToM <types.TypeMask> mask))
+ for {
+ dst := v_0
+ if v_1.Op != OpAMD64VCVTDQ2PS256 {
+ break
+ }
+ x := v_1.Args[0]
+ mask := v_2
+ if !(v.Block.CPUfeatures.hasFeature(CPUavx512)) {
+ break
+ }
+ v.reset(OpAMD64VCVTDQ2PSMasked256Merging)
+ v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x8ToM, types.TypeMask)
+ v0.AddArg(mask)
+ v.AddArg3(dst, x, v0)
+ return true
+ }
+ // match: (VPBLENDVB256 dst (VCVTQQ2PD256 x) mask)
+ // cond: v.Block.CPUfeatures.hasFeature(CPUavx512)
+ // result: (VCVTQQ2PDMasked256Merging dst x (VPMOVVec64x4ToM <types.TypeMask> mask))
+ for {
+ dst := v_0
+ if v_1.Op != OpAMD64VCVTQQ2PD256 {
+ break
+ }
+ x := v_1.Args[0]
+ mask := v_2
+ if !(v.Block.CPUfeatures.hasFeature(CPUavx512)) {
+ break
+ }
+ v.reset(OpAMD64VCVTQQ2PDMasked256Merging)
+ v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x4ToM, types.TypeMask)
+ v0.AddArg(mask)
+ v.AddArg3(dst, x, v0)
+ return true
+ }
+ // match: (VPBLENDVB256 dst (VCVTQQ2PSY128 x) mask)
+ // cond: v.Block.CPUfeatures.hasFeature(CPUavx512)
+ // result: (VCVTQQ2PSYMasked128Merging dst x (VPMOVVec64x4ToM <types.TypeMask> mask))
+ for {
+ dst := v_0
+ if v_1.Op != OpAMD64VCVTQQ2PSY128 {
+ break
+ }
+ x := v_1.Args[0]
+ mask := v_2
+ if !(v.Block.CPUfeatures.hasFeature(CPUavx512)) {
+ break
+ }
+ v.reset(OpAMD64VCVTQQ2PSYMasked128Merging)
+ v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x4ToM, types.TypeMask)
+ v0.AddArg(mask)
+ v.AddArg3(dst, x, v0)
+ return true
+ }
// match: (VPBLENDVB256 dst (VCVTTPD2DQY128 x) mask)
// cond: v.Block.CPUfeatures.hasFeature(CPUavx512)
// result: (VCVTTPD2DQYMasked128Merging dst x (VPMOVVec64x4ToM <types.TypeMask> mask))
v.AddArg3(dst, x, v0)
return true
}
+ // match: (VPBLENDVB256 dst (VCVTUDQ2PD512 x) mask)
+ // cond: v.Block.CPUfeatures.hasFeature(CPUavx512)
+ // result: (VCVTUDQ2PDMasked512Merging dst x (VPMOVVec32x8ToM <types.TypeMask> mask))
+ for {
+ dst := v_0
+ if v_1.Op != OpAMD64VCVTUDQ2PD512 {
+ break
+ }
+ x := v_1.Args[0]
+ mask := v_2
+ if !(v.Block.CPUfeatures.hasFeature(CPUavx512)) {
+ break
+ }
+ v.reset(OpAMD64VCVTUDQ2PDMasked512Merging)
+ v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x8ToM, types.TypeMask)
+ v0.AddArg(mask)
+ v.AddArg3(dst, x, v0)
+ return true
+ }
+ // match: (VPBLENDVB256 dst (VCVTUDQ2PS256 x) mask)
+ // cond: v.Block.CPUfeatures.hasFeature(CPUavx512)
+ // result: (VCVTUDQ2PSMasked256Merging dst x (VPMOVVec32x8ToM <types.TypeMask> mask))
+ for {
+ dst := v_0
+ if v_1.Op != OpAMD64VCVTUDQ2PS256 {
+ break
+ }
+ x := v_1.Args[0]
+ mask := v_2
+ if !(v.Block.CPUfeatures.hasFeature(CPUavx512)) {
+ break
+ }
+ v.reset(OpAMD64VCVTUDQ2PSMasked256Merging)
+ v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x8ToM, types.TypeMask)
+ v0.AddArg(mask)
+ v.AddArg3(dst, x, v0)
+ return true
+ }
+ // match: (VPBLENDVB256 dst (VCVTUQQ2PD256 x) mask)
+ // cond: v.Block.CPUfeatures.hasFeature(CPUavx512)
+ // result: (VCVTUQQ2PDMasked256Merging dst x (VPMOVVec64x4ToM <types.TypeMask> mask))
+ for {
+ dst := v_0
+ if v_1.Op != OpAMD64VCVTUQQ2PD256 {
+ break
+ }
+ x := v_1.Args[0]
+ mask := v_2
+ if !(v.Block.CPUfeatures.hasFeature(CPUavx512)) {
+ break
+ }
+ v.reset(OpAMD64VCVTUQQ2PDMasked256Merging)
+ v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x4ToM, types.TypeMask)
+ v0.AddArg(mask)
+ v.AddArg3(dst, x, v0)
+ return true
+ }
+ // match: (VPBLENDVB256 dst (VCVTUQQ2PSY128 x) mask)
+ // cond: v.Block.CPUfeatures.hasFeature(CPUavx512)
+ // result: (VCVTUQQ2PSYMasked128Merging dst x (VPMOVVec64x4ToM <types.TypeMask> mask))
+ for {
+ dst := v_0
+ if v_1.Op != OpAMD64VCVTUQQ2PSY128 {
+ break
+ }
+ x := v_1.Args[0]
+ mask := v_2
+ if !(v.Block.CPUfeatures.hasFeature(CPUavx512)) {
+ break
+ }
+ v.reset(OpAMD64VCVTUQQ2PSYMasked128Merging)
+ v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x4ToM, types.TypeMask)
+ v0.AddArg(mask)
+ v.AddArg3(dst, x, v0)
+ return true
+ }
// match: (VPBLENDVB256 dst (VDIVPD256 x y) mask)
// cond: v.Block.CPUfeatures.hasFeature(CPUavx512)
// result: (VDIVPDMasked256Merging dst x y (VPMOVVec64x4ToM <types.TypeMask> mask))
addF(simdPackage, "Uint8x16.ConcatShiftBytesRight", opLen2Imm8(ssa.OpConcatShiftBytesRightUint8x16, types.TypeVec128, 0), sys.AMD64)
addF(simdPackage, "Uint8x32.ConcatShiftBytesRightGrouped", opLen2Imm8(ssa.OpConcatShiftBytesRightGroupedUint8x32, types.TypeVec256, 0), sys.AMD64)
addF(simdPackage, "Uint8x64.ConcatShiftBytesRightGrouped", opLen2Imm8(ssa.OpConcatShiftBytesRightGroupedUint8x64, types.TypeVec512, 0), sys.AMD64)
+ addF(simdPackage, "Int32x4.ConvertToFloat32", opLen1(ssa.OpConvertToFloat32Int32x4, types.TypeVec128), sys.AMD64)
+ addF(simdPackage, "Int32x8.ConvertToFloat32", opLen1(ssa.OpConvertToFloat32Int32x8, types.TypeVec256), sys.AMD64)
+ addF(simdPackage, "Int32x16.ConvertToFloat32", opLen1(ssa.OpConvertToFloat32Int32x16, types.TypeVec512), sys.AMD64)
+ addF(simdPackage, "Int64x2.ConvertToFloat32", opLen1(ssa.OpConvertToFloat32Int64x2, types.TypeVec128), sys.AMD64)
+ addF(simdPackage, "Int64x4.ConvertToFloat32", opLen1(ssa.OpConvertToFloat32Int64x4, types.TypeVec128), sys.AMD64)
+ addF(simdPackage, "Int64x8.ConvertToFloat32", opLen1(ssa.OpConvertToFloat32Int64x8, types.TypeVec256), sys.AMD64)
+ addF(simdPackage, "Uint32x4.ConvertToFloat32", opLen1(ssa.OpConvertToFloat32Uint32x4, types.TypeVec128), sys.AMD64)
+ addF(simdPackage, "Uint32x8.ConvertToFloat32", opLen1(ssa.OpConvertToFloat32Uint32x8, types.TypeVec256), sys.AMD64)
+ addF(simdPackage, "Uint32x16.ConvertToFloat32", opLen1(ssa.OpConvertToFloat32Uint32x16, types.TypeVec512), sys.AMD64)
+ addF(simdPackage, "Uint64x2.ConvertToFloat32", opLen1(ssa.OpConvertToFloat32Uint64x2, types.TypeVec128), sys.AMD64)
+ addF(simdPackage, "Uint64x4.ConvertToFloat32", opLen1(ssa.OpConvertToFloat32Uint64x4, types.TypeVec128), sys.AMD64)
+ addF(simdPackage, "Uint64x8.ConvertToFloat32", opLen1(ssa.OpConvertToFloat32Uint64x8, types.TypeVec256), sys.AMD64)
+ addF(simdPackage, "Int32x4.ConvertToFloat64", opLen1(ssa.OpConvertToFloat64Int32x4, types.TypeVec256), sys.AMD64)
+ addF(simdPackage, "Int32x8.ConvertToFloat64", opLen1(ssa.OpConvertToFloat64Int32x8, types.TypeVec512), sys.AMD64)
+ addF(simdPackage, "Int64x2.ConvertToFloat64", opLen1(ssa.OpConvertToFloat64Int64x2, types.TypeVec128), sys.AMD64)
+ addF(simdPackage, "Int64x4.ConvertToFloat64", opLen1(ssa.OpConvertToFloat64Int64x4, types.TypeVec256), sys.AMD64)
+ addF(simdPackage, "Int64x8.ConvertToFloat64", opLen1(ssa.OpConvertToFloat64Int64x8, types.TypeVec512), sys.AMD64)
+ addF(simdPackage, "Uint32x4.ConvertToFloat64", opLen1(ssa.OpConvertToFloat64Uint32x4, types.TypeVec256), sys.AMD64)
+ addF(simdPackage, "Uint32x8.ConvertToFloat64", opLen1(ssa.OpConvertToFloat64Uint32x8, types.TypeVec512), sys.AMD64)
+ addF(simdPackage, "Uint64x2.ConvertToFloat64", opLen1(ssa.OpConvertToFloat64Uint64x2, types.TypeVec128), sys.AMD64)
+ addF(simdPackage, "Uint64x4.ConvertToFloat64", opLen1(ssa.OpConvertToFloat64Uint64x4, types.TypeVec256), sys.AMD64)
+ addF(simdPackage, "Uint64x8.ConvertToFloat64", opLen1(ssa.OpConvertToFloat64Uint64x8, types.TypeVec512), sys.AMD64)
addF(simdPackage, "Float32x4.ConvertToInt32", opLen1(ssa.OpConvertToInt32Float32x4, types.TypeVec128), sys.AMD64)
addF(simdPackage, "Float32x8.ConvertToInt32", opLen1(ssa.OpConvertToInt32Float32x8, types.TypeVec256), sys.AMD64)
addF(simdPackage, "Float32x16.ConvertToInt32", opLen1(ssa.OpConvertToInt32Float32x16, types.TypeVec512), sys.AMD64)
// adjustAsm adjusts the asm to make it align with Go's assembler.
func (op *Operation) adjustAsm() {
- if op.Asm == "VCVTTPD2DQ" || op.Asm == "VCVTTPD2UDQ" {
+ if op.Asm == "VCVTTPD2DQ" || op.Asm == "VCVTTPD2UDQ" || op.Asm == "VCVTQQ2PS" || op.Asm == "VCVTUQQ2PS" {
switch *op.In[0].Bits {
case 128:
op.Asm += "X"
documentation: !string |-
// NAME converts element values to int32.
// When a conversion is inexact, a truncated (round toward zero) value is returned.
- // If a converted result is larger than the maximum int32, the indefinite value is returned.
+ // If a converted result cannot be represented in int32, an implementation-defined
+ // architecture-specific value is returned.
- go: "ConvertToUint32"
commutative: false
regexpTag: "convert"
documentation: !string |-
// NAME converts element values to uint32.
// When a conversion is inexact, a truncated (round toward zero) value is returned.
- // If a converted result is larger than the maximum uint32, the maximum uint32 value is returned.
+ // If a converted result cannot be represented in uint32, an implementation-defined
+ // architecture-specific value is returned.
- go: "ConvertToInt64"
commutative: false
regexpTag: "convert"
documentation: !string |-
// NAME converts element values to int64.
// When a conversion is inexact, a truncated (round toward zero) value is returned.
- // If a converted result is larger than the maximum int64, the indefinite value is returned.
+ // If a converted result cannot be represented in int64, an implementation-defined
+ // architecture-specific value is returned.
- go: "ConvertToUint64"
commutative: false
regexpTag: "convert"
documentation: !string |-
// NAME converts element values to uint64.
// When a conversion is inexact, a truncated (round toward zero) value is returned.
- // If a converted result is larger than the maximum uint64, the maximum uint64 value is returned.
+ // If a converted result cannot be represented in uint64, an implementation-defined
+ // architecture-specific value is returned.
+- go: "ConvertToFloat32"
+ commutative: false
+ regexpTag: "convert"
+ documentation: !string |-
+ // NAME converts element values to float32.
+- go: "ConvertToFloat64"
+ commutative: false
+ regexpTag: "convert"
+ documentation: !string |-
+ // NAME converts element values to float64.
# Int <-> Int conversions
- go: "(Extend|Saturate|Truncate)?ToInt8"
base: uint
elemBits: 64
bits: 256|512
+# int -> float32
+- go: ConvertToFloat32
+ regexpTag: "convert"
+ asm: "VCVT[DQ]Q2PS"
+ in: &int
+ - go: $i
+ base: int
+ out:
+ - *fp
+# int -> float64
+- go: ConvertToFloat64
+ regexpTag: "convert"
+ asm: "VCVTQQ2PD"
+ in: *int
+ out:
+ - *fp
+- go: ConvertToFloat64
+ regexpTag: "convert"
+ asm: "VCVTDQ2PD"
+ in: *int
+ out:
+ - base: float
+ bits: 256|512
+# uint -> float32
+- go: ConvertToFloat32
+ regexpTag: "convert"
+ asm: "VCVTU[DQ]Q2PS"
+ in: &uint
+ - go: $u
+ base: uint
+ out:
+ - *fp
+# uint -> float64
+- go: ConvertToFloat64
+ regexpTag: "convert"
+ asm: "VCVTUQQ2PD"
+ in: *uint
+ out:
+ - *fp
+- go: ConvertToFloat64
+ regexpTag: "convert"
+ asm: "VCVTUDQ2PD"
+ in: *uint
+ out:
+ - base: float
+ bits: 256|512
# Widening integer conversions.
# uint8 -> uint16
// Asm: VPALIGNR, CPU Feature: AVX512
func (x Uint8x64) ConcatShiftBytesRightGrouped(constant uint8, y Uint8x64) Uint8x64
+/* ConvertToFloat32 */
+
+// ConvertToFloat32 converts element values to float32.
+//
+// Asm: VCVTDQ2PS, CPU Feature: AVX
+func (x Int32x4) ConvertToFloat32() Float32x4
+
+// ConvertToFloat32 converts element values to float32.
+//
+// Asm: VCVTDQ2PS, CPU Feature: AVX
+func (x Int32x8) ConvertToFloat32() Float32x8
+
+// ConvertToFloat32 converts element values to float32.
+//
+// Asm: VCVTDQ2PS, CPU Feature: AVX512
+func (x Int32x16) ConvertToFloat32() Float32x16
+
+// ConvertToFloat32 converts element values to float32.
+//
+// Asm: VCVTQQ2PSX, CPU Feature: AVX512
+func (x Int64x2) ConvertToFloat32() Float32x4
+
+// ConvertToFloat32 converts element values to float32.
+//
+// Asm: VCVTQQ2PSY, CPU Feature: AVX512
+func (x Int64x4) ConvertToFloat32() Float32x4
+
+// ConvertToFloat32 converts element values to float32.
+//
+// Asm: VCVTQQ2PS, CPU Feature: AVX512
+func (x Int64x8) ConvertToFloat32() Float32x8
+
+// ConvertToFloat32 converts element values to float32.
+//
+// Asm: VCVTUDQ2PS, CPU Feature: AVX512
+func (x Uint32x4) ConvertToFloat32() Float32x4
+
+// ConvertToFloat32 converts element values to float32.
+//
+// Asm: VCVTUDQ2PS, CPU Feature: AVX512
+func (x Uint32x8) ConvertToFloat32() Float32x8
+
+// ConvertToFloat32 converts element values to float32.
+//
+// Asm: VCVTUDQ2PS, CPU Feature: AVX512
+func (x Uint32x16) ConvertToFloat32() Float32x16
+
+// ConvertToFloat32 converts element values to float32.
+//
+// Asm: VCVTUQQ2PSX, CPU Feature: AVX512
+func (x Uint64x2) ConvertToFloat32() Float32x4
+
+// ConvertToFloat32 converts element values to float32.
+//
+// Asm: VCVTUQQ2PSY, CPU Feature: AVX512
+func (x Uint64x4) ConvertToFloat32() Float32x4
+
+// ConvertToFloat32 converts element values to float32.
+//
+// Asm: VCVTUQQ2PS, CPU Feature: AVX512
+func (x Uint64x8) ConvertToFloat32() Float32x8
+
+/* ConvertToFloat64 */
+
+// ConvertToFloat64 converts element values to float64.
+//
+// Asm: VCVTDQ2PD, CPU Feature: AVX
+func (x Int32x4) ConvertToFloat64() Float64x4
+
+// ConvertToFloat64 converts element values to float64.
+//
+// Asm: VCVTDQ2PD, CPU Feature: AVX512
+func (x Int32x8) ConvertToFloat64() Float64x8
+
+// ConvertToFloat64 converts element values to float64.
+//
+// Asm: VCVTQQ2PD, CPU Feature: AVX512
+func (x Int64x2) ConvertToFloat64() Float64x2
+
+// ConvertToFloat64 converts element values to float64.
+//
+// Asm: VCVTQQ2PD, CPU Feature: AVX512
+func (x Int64x4) ConvertToFloat64() Float64x4
+
+// ConvertToFloat64 converts element values to float64.
+//
+// Asm: VCVTQQ2PD, CPU Feature: AVX512
+func (x Int64x8) ConvertToFloat64() Float64x8
+
+// ConvertToFloat64 converts element values to float64.
+//
+// Asm: VCVTUDQ2PD, CPU Feature: AVX512
+func (x Uint32x4) ConvertToFloat64() Float64x4
+
+// ConvertToFloat64 converts element values to float64.
+//
+// Asm: VCVTUDQ2PD, CPU Feature: AVX512
+func (x Uint32x8) ConvertToFloat64() Float64x8
+
+// ConvertToFloat64 converts element values to float64.
+//
+// Asm: VCVTUQQ2PD, CPU Feature: AVX512
+func (x Uint64x2) ConvertToFloat64() Float64x2
+
+// ConvertToFloat64 converts element values to float64.
+//
+// Asm: VCVTUQQ2PD, CPU Feature: AVX512
+func (x Uint64x4) ConvertToFloat64() Float64x4
+
+// ConvertToFloat64 converts element values to float64.
+//
+// Asm: VCVTUQQ2PD, CPU Feature: AVX512
+func (x Uint64x8) ConvertToFloat64() Float64x8
+
/* ConvertToInt32 */
// ConvertToInt32 converts element values to int32.
// When a conversion is inexact, a truncated (round toward zero) value is returned.
-// If a converted result is larger than the maximum int32, the indefinite value is returned.
+// If a converted result cannot be represented in int32, an implementation-defined
+// architecture-specific value is returned.
//
// Asm: VCVTTPS2DQ, CPU Feature: AVX
func (x Float32x4) ConvertToInt32() Int32x4
// ConvertToInt32 converts element values to int32.
// When a conversion is inexact, a truncated (round toward zero) value is returned.
-// If a converted result is larger than the maximum int32, the indefinite value is returned.
+// If a converted result cannot be represented in int32, an implementation-defined
+// architecture-specific value is returned.
//
// Asm: VCVTTPS2DQ, CPU Feature: AVX
func (x Float32x8) ConvertToInt32() Int32x8
// ConvertToInt32 converts element values to int32.
// When a conversion is inexact, a truncated (round toward zero) value is returned.
-// If a converted result is larger than the maximum int32, the indefinite value is returned.
+// If a converted result cannot be represented in int32, an implementation-defined
+// architecture-specific value is returned.
//
// Asm: VCVTTPS2DQ, CPU Feature: AVX512
func (x Float32x16) ConvertToInt32() Int32x16
// ConvertToInt32 converts element values to int32.
// When a conversion is inexact, a truncated (round toward zero) value is returned.
-// If a converted result is larger than the maximum int32, the indefinite value is returned.
+// If a converted result cannot be represented in int32, an implementation-defined
+// architecture-specific value is returned.
//
// Asm: VCVTTPD2DQX, CPU Feature: AVX
func (x Float64x2) ConvertToInt32() Int32x4
// ConvertToInt32 converts element values to int32.
// When a conversion is inexact, a truncated (round toward zero) value is returned.
-// If a converted result is larger than the maximum int32, the indefinite value is returned.
+// If a converted result cannot be represented in int32, an implementation-defined
+// architecture-specific value is returned.
//
// Asm: VCVTTPD2DQY, CPU Feature: AVX
func (x Float64x4) ConvertToInt32() Int32x4
// ConvertToInt32 converts element values to int32.
// When a conversion is inexact, a truncated (round toward zero) value is returned.
-// If a converted result is larger than the maximum int32, the indefinite value is returned.
+// If a converted result cannot be represented in int32, an implementation-defined
+// architecture-specific value is returned.
//
// Asm: VCVTTPD2DQ, CPU Feature: AVX512
func (x Float64x8) ConvertToInt32() Int32x8
// ConvertToInt64 converts element values to int64.
// When a conversion is inexact, a truncated (round toward zero) value is returned.
-// If a converted result is larger than the maximum int64, the indefinite value is returned.
+// If a converted result cannot be represented in int64, an implementation-defined
+// architecture-specific value is returned.
//
// Asm: VCVTTPS2QQ, CPU Feature: AVX512
func (x Float32x4) ConvertToInt64() Int64x4
// ConvertToInt64 converts element values to int64.
// When a conversion is inexact, a truncated (round toward zero) value is returned.
-// If a converted result is larger than the maximum int64, the indefinite value is returned.
+// If a converted result cannot be represented in int64, an implementation-defined
+// architecture-specific value is returned.
//
// Asm: VCVTTPS2QQ, CPU Feature: AVX512
func (x Float32x8) ConvertToInt64() Int64x8
// ConvertToInt64 converts element values to int64.
// When a conversion is inexact, a truncated (round toward zero) value is returned.
-// If a converted result is larger than the maximum int64, the indefinite value is returned.
+// If a converted result cannot be represented in int64, an implementation-defined
+// architecture-specific value is returned.
//
// Asm: VCVTTPD2QQ, CPU Feature: AVX512
func (x Float64x2) ConvertToInt64() Int64x2
// ConvertToInt64 converts element values to int64.
// When a conversion is inexact, a truncated (round toward zero) value is returned.
-// If a converted result is larger than the maximum int64, the indefinite value is returned.
+// If a converted result cannot be represented in int64, an implementation-defined
+// architecture-specific value is returned.
//
// Asm: VCVTTPD2QQ, CPU Feature: AVX512
func (x Float64x4) ConvertToInt64() Int64x4
// ConvertToInt64 converts element values to int64.
// When a conversion is inexact, a truncated (round toward zero) value is returned.
-// If a converted result is larger than the maximum int64, the indefinite value is returned.
+// If a converted result cannot be represented in int64, an implementation-defined
+// architecture-specific value is returned.
//
// Asm: VCVTTPD2QQ, CPU Feature: AVX512
func (x Float64x8) ConvertToInt64() Int64x8
// ConvertToUint32 converts element values to uint32.
// When a conversion is inexact, a truncated (round toward zero) value is returned.
-// If a converted result is larger than the maximum uint32, the maximum uint32 value is returned.
+// If a converted result cannot be represented in uint32, an implementation-defined
+// architecture-specific value is returned.
//
// Asm: VCVTTPS2UDQ, CPU Feature: AVX512
func (x Float32x4) ConvertToUint32() Uint32x4
// ConvertToUint32 converts element values to uint32.
// When a conversion is inexact, a truncated (round toward zero) value is returned.
-// If a converted result is larger than the maximum uint32, the maximum uint32 value is returned.
+// If a converted result cannot be represented in uint32, an implementation-defined
+// architecture-specific value is returned.
//
// Asm: VCVTTPS2UDQ, CPU Feature: AVX512
func (x Float32x8) ConvertToUint32() Uint32x8
// ConvertToUint32 converts element values to uint32.
// When a conversion is inexact, a truncated (round toward zero) value is returned.
-// If a converted result is larger than the maximum uint32, the maximum uint32 value is returned.
+// If a converted result cannot be represented in uint32, an implementation-defined
+// architecture-specific value is returned.
//
// Asm: VCVTTPS2UDQ, CPU Feature: AVX512
func (x Float32x16) ConvertToUint32() Uint32x16
// ConvertToUint32 converts element values to uint32.
// When a conversion is inexact, a truncated (round toward zero) value is returned.
-// If a converted result is larger than the maximum uint32, the maximum uint32 value is returned.
+// If a converted result cannot be represented in uint32, an implementation-defined
+// architecture-specific value is returned.
//
// Asm: VCVTTPD2UDQX, CPU Feature: AVX512
func (x Float64x2) ConvertToUint32() Uint32x4
// ConvertToUint32 converts element values to uint32.
// When a conversion is inexact, a truncated (round toward zero) value is returned.
-// If a converted result is larger than the maximum uint32, the maximum uint32 value is returned.
+// If a converted result cannot be represented in uint32, an implementation-defined
+// architecture-specific value is returned.
//
// Asm: VCVTTPD2UDQY, CPU Feature: AVX512
func (x Float64x4) ConvertToUint32() Uint32x4
// ConvertToUint32 converts element values to uint32.
// When a conversion is inexact, a truncated (round toward zero) value is returned.
-// If a converted result is larger than the maximum uint32, the maximum uint32 value is returned.
+// If a converted result cannot be represented in uint32, an implementation-defined
+// architecture-specific value is returned.
//
// Asm: VCVTTPD2UDQ, CPU Feature: AVX512
func (x Float64x8) ConvertToUint32() Uint32x8
// ConvertToUint64 converts element values to uint64.
// When a conversion is inexact, a truncated (round toward zero) value is returned.
-// If a converted result is larger than the maximum uint64, the maximum uint64 value is returned.
+// If a converted result cannot be represented in uint64, an implementation-defined
+// architecture-specific value is returned.
//
// Asm: VCVTTPS2UQQ, CPU Feature: AVX512
func (x Float32x4) ConvertToUint64() Uint64x4
// ConvertToUint64 converts element values to uint64.
// When a conversion is inexact, a truncated (round toward zero) value is returned.
-// If a converted result is larger than the maximum uint64, the maximum uint64 value is returned.
+// If a converted result cannot be represented in uint64, an implementation-defined
+// architecture-specific value is returned.
//
// Asm: VCVTTPS2UQQ, CPU Feature: AVX512
func (x Float32x8) ConvertToUint64() Uint64x8
// ConvertToUint64 converts element values to uint64.
// When a conversion is inexact, a truncated (round toward zero) value is returned.
-// If a converted result is larger than the maximum uint64, the maximum uint64 value is returned.
+// If a converted result cannot be represented in uint64, an implementation-defined
+// architecture-specific value is returned.
//
// Asm: VCVTTPD2UQQ, CPU Feature: AVX512
func (x Float64x2) ConvertToUint64() Uint64x2
// ConvertToUint64 converts element values to uint64.
// When a conversion is inexact, a truncated (round toward zero) value is returned.
-// If a converted result is larger than the maximum uint64, the maximum uint64 value is returned.
+// If a converted result cannot be represented in uint64, an implementation-defined
+// architecture-specific value is returned.
//
// Asm: VCVTTPD2UQQ, CPU Feature: AVX512
func (x Float64x4) ConvertToUint64() Uint64x4
// ConvertToUint64 converts element values to uint64.
// When a conversion is inexact, a truncated (round toward zero) value is returned.
-// If a converted result is larger than the maximum uint64, the maximum uint64 value is returned.
+// If a converted result cannot be represented in uint64, an implementation-defined
+// architecture-specific value is returned.
//
// Asm: VCVTTPD2UQQ, CPU Feature: AVX512
func (x Float64x8) ConvertToUint64() Uint64x8