[dev.simd] all: merge master (ca37d24) into dev.simd

Conflicts:

- src/cmd/compile/internal/typecheck/builtin.go

Merge List:

+ 2025-11-20 ca37d24e0b net/http: drop unused "broken" field from persistConn
+ 2025-11-20 4b740af56a cmd/internal/obj/x86: handle global reference in From3 in dynlink mode
+ 2025-11-20 790384c6c2 spec: adjust rule for type parameter on RHS of alias declaration
+ 2025-11-20 a49b0302d0 net/http: correctly close fake net.Conns
+ 2025-11-20 32f5aadd2f cmd/compile: stack allocate backing stores during append
+ 2025-11-20 a18aff8057 runtime: select GC mark workers during start-the-world
+ 2025-11-20 829779f4fe runtime: split findRunnableGCWorker in two
+ 2025-11-20 ab59569099 go/version: use "custom" as an example of a version suffix
+ 2025-11-19 c4bb9653ba cmd/compile: Implement LoweredZeroLoop with LSX Instruction on loong64
+ 2025-11-19 7f2ae21fb4 cmd/internal/obj/loong64: add MULW.D.W[U] instructions
+ 2025-11-19 a2946f2385 crypto: add Encapsulator and Decapsulator interfaces
+ 2025-11-19 6b83bd7146 crypto/ecdh: add KeyExchanger interface
+ 2025-11-19 4fef9f8b55 go/types, types2: fix object path for grouped declaration statements
+ 2025-11-19 33529db142 spec: escape double-ampersands
+ 2025-11-19 dc42565a20 cmd/compile: fix control flow for unsigned divisions proof relations
+ 2025-11-19 e64023dcbf cmd/compile: cleanup useless if statement in prove
+ 2025-11-19 2239520d1c test: go fmt prove.go tests
+ 2025-11-19 489d3dafb7 math: switch s390x math.Pow to generic implementation
+ 2025-11-18 8c41a482f9 runtime: add dlog.hexdump
+ 2025-11-18 e912618bd2 runtime: add hexdumper
+ 2025-11-18 2cf9d4b62f Revert "net/http: do not discard body content when closing it within request handlers"
+ 2025-11-18 4d0658bb08 cmd/compile: prefer fixed registers for values
+ 2025-11-18 ba634ca5c7 cmd/compile: fold boolean NOT into branches
+ 2025-11-18 8806d53c10 cmd/link: align sections, not symbols after DWARF compress
+ 2025-11-18 c93766007d runtime: do not print recovered when double panic with the same value
+ 2025-11-18 9859b43643 cmd/asm,cmd/compile,cmd/internal/obj/riscv: use compressed instructions on riscv64
+ 2025-11-17 b9ef0633f6 cmd/internal/sys,internal/goarch,runtime: enable the use of compressed instructions on riscv64
+ 2025-11-17 a087dea869 debug/elf: sync new loong64 relocation types up to LoongArch ELF psABI v20250521
+ 2025-11-17 e1a12c781f cmd/compile: use 32x32->64 multiplies on arm64
+ 2025-11-17 6caab99026 runtime: relax TestMemoryLimit on darwin a bit more
+ 2025-11-17 eda2e8c683 runtime: clear frame pointer at thread entry points
+ 2025-11-17 6919858338 runtime: rename findrunnable references to findRunnable
+ 2025-11-17 8e734ec954 go/ast: fix BasicLit.End position for raw strings containing \r
+ 2025-11-17 592775ec7d crypto/mlkem: avoid a few unnecessary inverse NTT calls
+ 2025-11-17 590cf18daf crypto/mlkem/mlkemtest: add derandomized Encapsulate768/1024
+ 2025-11-17 c12c337099 cmd/compile: teach prove about subtract idioms
+ 2025-11-17 bc15963813 cmd/compile: clean up prove pass
+ 2025-11-17 1297fae708 go/token: add (*File).End method
+ 2025-11-17 65c09eafdf runtime: hoist invariant code out of heapBitsSmallForAddrInline
+ 2025-11-17 594129b80c internal/runtime/maps: update doc for table.Clear
+ 2025-11-15 c58d075e9a crypto/rsa: deprecate PKCS#1 v1.5 encryption
+ 2025-11-14 d55ecea9e5 runtime: usleep before stealing runnext only if not in syscall
+ 2025-11-14 410ef44f00 cmd: update x/tools to 59ff18c
+ 2025-11-14 50128a2154 runtime: support runtime.freegc in size-specialized mallocs for noscan objects
+ 2025-11-14 c3708350a4 cmd/go: tests: rename git-min-vers->git-sha256
+ 2025-11-14 aea881230d std: fix printf("%q", int) mistakes
+ 2025-11-14 120f1874ef runtime: add more precise test of assist credit handling for runtime.freegc
+ 2025-11-14 fecfcaa4f6 runtime: add runtime.freegc to reduce GC work
+ 2025-11-14 5a347b775e runtime: set GOEXPERIMENT=runtimefreegc to disabled by default
+ 2025-11-14 1a03d0db3f runtime: skip tests for GOEXPERIMENT=arenas that do not handle clobberfree=1
+ 2025-11-14 cb0d9980f5 net/http: do not discard body content when closing it within request handlers
+ 2025-11-14 03ed43988f cmd/compile: allow multi-field structs to be stored directly in interfaces
+ 2025-11-14 1bb1f2bf0c runtime: put AddCleanup cleanup arguments in their own allocation
+ 2025-11-14 9fd2e44439 runtime: add AddCleanup benchmark
+ 2025-11-14 80c91eedbb runtime: ensure weak handles end up in their own allocation
+ 2025-11-14 7a8d0b5d53 runtime: add debug mode to extend _Grunning-without-P windows
+ 2025-11-14 710abf74da internal/runtime/cgobench: add Go function call benchmark for comparison
+ 2025-11-14 b24aec598b doc, cmd/internal/obj/riscv: document the riscv64 assembler
+ 2025-11-14 a0e738c657 cmd/compile/internal: remove incorrect riscv64 SLTI rule
+ 2025-11-14 2cdcc4150b cmd/compile: fold negation into multiplication
+ 2025-11-14 b57962b7c7 bytes: fix panic in bytes.Buffer.Peek
+ 2025-11-14 0a569528ea cmd/compile: optimize comparisons with single bit difference
+ 2025-11-14 1e5e6663e9 cmd/compile: remove unnecessary casts and types from riscv64 rules
+ 2025-11-14 ddd8558e61 go/types, types2: swap object.color for Checker.objPathIdx
+ 2025-11-14 9daaab305c cmd/link/internal/ld: make runtime.buildVersion with experiments valid
+ 2025-11-13 d50a571ddf test: fix tests to work with sizespecializedmalloc turned off
+ 2025-11-13 704f841eab cmd/trace: annotation proc start/stop with thread and proc always
+ 2025-11-13 17a02b9106 net/http: remove unused isLitOrSingle and isNotToken
+ 2025-11-13 ff61991aed cmd/go: fix flaky TestScript/mod_get_direct
+ 2025-11-13 129d0cb543 net/http/cgi: accept INCLUDED as protocol for server side includes
+ 2025-11-13 77c5130100 go/types: minor simplification
+ 2025-11-13 7601cd3880 go/types: generate cycles.go
+ 2025-11-13 7a372affd9 go/types, types2: rename definedType to declaredType and clarify docs

Change-Id: Ibaa9bdb982364892f80e511c1bb12661fcd5fb86

diff --cc src/cmd/compile/internal/gc/main.go
Simple merge

diff --cc src/cmd/compile/internal/ir/expr.go
Simple merge

diff --cc src/cmd/compile/internal/ir/symtab.go
Simple merge

diff --cc src/cmd/compile/internal/ssa/_gen/AMD64Ops.go
Simple merge

diff --cc src/cmd/compile/internal/ssa/_gen/generic.rules
Simple merge

diff --cc src/cmd/compile/internal/ssa/expand_calls.go
Simple merge

diff --cc src/cmd/compile/internal/ssa/opGen.go
index 9c5d79fa56f3b775b9190b37b583194a43e569a7,f13373d2c05f75dfccfad0c81e5bfc27dedb6616..ea5491362f83a5566cb56c4af530c5af4eda6ea1
--- 1/src/cmd/compile/internal/ssa/opGen.go
--- 2/src/cmd/compile/internal/ssa/opGen.go
+++ b/src/cmd/compile/internal/ssa/opGen.go
@@@ -46549,44156 -40710,71 +46549,44157 @@@ var opcodeTable = [...]opInfo
                        },
                },
        },
 -
        {
 -              name:    "Last",
 -              argLen:  -1,
 -              generic: true,
 +              name:      "VPSLLVQ512load",
 +              auxType:   auxSymOff,
 +              argLen:    3,
 +              symEffect: SymRead,
 +              asm:       x86.AVPSLLVQ,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
 +                              {0, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
        },
        {
 -              name:        "Add8",
 -              argLen:      2,
 -              commutative: true,
 -              generic:     true,
 +              name:      "VPSLLVQMasked128load",
 +              auxType:   auxSymOff,
 +              argLen:    4,
 +              symEffect: SymRead,
 +              asm:       x86.AVPSLLVQ,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {1, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
 +                              {0, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
        },
        {
 -              name:        "Add16",
 -              argLen:      2,
 -              commutative: true,
 -              generic:     true,
 +              name:      "VPSLLVQMasked256load",
 +              auxType:   auxSymOff,
 +              argLen:    4,
 +              symEffect: SymRead,
 +              asm:       x86.AVPSLLVQ,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {1, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
 +                              {0, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
        },
        {
 -              name:        "Add32",
 -              argLen:      2,
 -              commutative: true,
 -              generic:     true,
 +              name:      "VPSLLVQMasked512load",
 +              auxType:   auxSymOff,
 +              argLen:    4,
 +              symEffect: SymRead,
 +              asm:       x86.AVPSLLVQ,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {1, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
 +                              {0, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
        },
        {
 -              name:        "Add64",
 -              argLen:      2,
 -              commutative: true,
 -              generic:     true,
 +              name:      "VPSRAVD512load",
 +              auxType:   auxSymOff,
 +              argLen:    3,
 +              symEffect: SymRead,
 +              asm:       x86.AVPSRAVD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
 +                              {0, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
        },
        {
 -              name:    "AddPtr",
 -              argLen:  2,
 -              generic: true,
 +              name:      "VPSRAVDMasked128load",
 +              auxType:   auxSymOff,
 +              argLen:    4,
 +              symEffect: SymRead,
 +              asm:       x86.AVPSRAVD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {1, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
 +                              {0, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
        },
        {
 -              name:        "Add32F",
 -              argLen:      2,
 -              commutative: true,
 -              generic:     true,
 +              name:      "VPSRAVDMasked256load",
 +              auxType:   auxSymOff,
 +              argLen:    4,
 +              symEffect: SymRead,
 +              asm:       x86.AVPSRAVD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {1, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
 +                              {0, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
        },
        {
 -              name:        "Add64F",
 -              argLen:      2,
 -              commutative: true,
 -              generic:     true,
 +              name:      "VPSRAVDMasked512load",
 +              auxType:   auxSymOff,
 +              argLen:    4,
 +              symEffect: SymRead,
 +              asm:       x86.AVPSRAVD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {1, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
 +                              {0, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
        },
        {
 -              name:    "Sub8",
 -              argLen:  2,
 -              generic: true,
 +              name:      "VPSRAVQ128load",
 +              auxType:   auxSymOff,
 +              argLen:    3,
 +              symEffect: SymRead,
 +              asm:       x86.AVPSRAVQ,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
 +                              {0, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
        },
        {
 -              name:    "Sub16",
 -              argLen:  2,
 -              generic: true,
 +              name:      "VPSRAVQ256load",
 +              auxType:   auxSymOff,
 +              argLen:    3,
 +              symEffect: SymRead,
 +              asm:       x86.AVPSRAVQ,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
 +                              {0, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
        },
        {
 -              name:    "Sub32",
 -              argLen:  2,
 -              generic: true,
 +              name:      "VPSRAVQ512load",
 +              auxType:   auxSymOff,
 +              argLen:    3,
 +              symEffect: SymRead,
 +              asm:       x86.AVPSRAVQ,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
 +                              {0, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
        },
        {
 -              name:    "Sub64",
 -              argLen:  2,
 +              name:      "VPSRAVQMasked128load",
 +              auxType:   auxSymOff,
 +              argLen:    4,
 +              symEffect: SymRead,
 +              asm:       x86.AVPSRAVQ,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {1, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
 +                              {0, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:      "VPSRAVQMasked256load",
 +              auxType:   auxSymOff,
 +              argLen:    4,
 +              symEffect: SymRead,
 +              asm:       x86.AVPSRAVQ,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {1, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
 +                              {0, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:      "VPSRAVQMasked512load",
 +              auxType:   auxSymOff,
 +              argLen:    4,
 +              symEffect: SymRead,
 +              asm:       x86.AVPSRAVQ,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {1, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
 +                              {0, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:      "VPSRLVD512load",
 +              auxType:   auxSymOff,
 +              argLen:    3,
 +              symEffect: SymRead,
 +              asm:       x86.AVPSRLVD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
 +                              {0, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:      "VPSRLVDMasked128load",
 +              auxType:   auxSymOff,
 +              argLen:    4,
 +              symEffect: SymRead,
 +              asm:       x86.AVPSRLVD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {1, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
 +                              {0, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:      "VPSRLVDMasked256load",
 +              auxType:   auxSymOff,
 +              argLen:    4,
 +              symEffect: SymRead,
 +              asm:       x86.AVPSRLVD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {1, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
 +                              {0, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:      "VPSRLVDMasked512load",
 +              auxType:   auxSymOff,
 +              argLen:    4,
 +              symEffect: SymRead,
 +              asm:       x86.AVPSRLVD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {1, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
 +                              {0, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:      "VPSRLVQ512load",
 +              auxType:   auxSymOff,
 +              argLen:    3,
 +              symEffect: SymRead,
 +              asm:       x86.AVPSRLVQ,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
 +                              {0, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:      "VPSRLVQMasked128load",
 +              auxType:   auxSymOff,
 +              argLen:    4,
 +              symEffect: SymRead,
 +              asm:       x86.AVPSRLVQ,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {1, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
 +                              {0, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:      "VPSRLVQMasked256load",
 +              auxType:   auxSymOff,
 +              argLen:    4,
 +              symEffect: SymRead,
 +              asm:       x86.AVPSRLVQ,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {1, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
 +                              {0, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:      "VPSRLVQMasked512load",
 +              auxType:   auxSymOff,
 +              argLen:    4,
 +              symEffect: SymRead,
 +              asm:       x86.AVPSRLVQ,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {1, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
 +                              {0, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:      "VPSUBD512load",
 +              auxType:   auxSymOff,
 +              argLen:    3,
 +              symEffect: SymRead,
 +              asm:       x86.AVPSUBD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
 +                              {0, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:      "VPSUBDMasked128load",
 +              auxType:   auxSymOff,
 +              argLen:    4,
 +              symEffect: SymRead,
 +              asm:       x86.AVPSUBD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {1, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
 +                              {0, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:      "VPSUBDMasked256load",
 +              auxType:   auxSymOff,
 +              argLen:    4,
 +              symEffect: SymRead,
 +              asm:       x86.AVPSUBD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {1, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
 +                              {0, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:      "VPSUBDMasked512load",
 +              auxType:   auxSymOff,
 +              argLen:    4,
 +              symEffect: SymRead,
 +              asm:       x86.AVPSUBD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {1, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
 +                              {0, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:      "VPSUBQ512load",
 +              auxType:   auxSymOff,
 +              argLen:    3,
 +              symEffect: SymRead,
 +              asm:       x86.AVPSUBQ,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
 +                              {0, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:      "VPSUBQMasked128load",
 +              auxType:   auxSymOff,
 +              argLen:    4,
 +              symEffect: SymRead,
 +              asm:       x86.AVPSUBQ,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {1, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
 +                              {0, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:      "VPSUBQMasked256load",
 +              auxType:   auxSymOff,
 +              argLen:    4,
 +              symEffect: SymRead,
 +              asm:       x86.AVPSUBQ,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {1, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
 +                              {0, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:      "VPSUBQMasked512load",
 +              auxType:   auxSymOff,
 +              argLen:    4,
 +              symEffect: SymRead,
 +              asm:       x86.AVPSUBQ,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {1, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
 +                              {0, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:      "VPUNPCKHDQ512load",
 +              auxType:   auxSymOff,
 +              argLen:    3,
 +              symEffect: SymRead,
 +              asm:       x86.AVPUNPCKHDQ,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
 +                              {0, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:      "VPUNPCKHQDQ512load",
 +              auxType:   auxSymOff,
 +              argLen:    3,
 +              symEffect: SymRead,
 +              asm:       x86.AVPUNPCKHQDQ,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
 +                              {0, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:      "VPUNPCKLDQ512load",
 +              auxType:   auxSymOff,
 +              argLen:    3,
 +              symEffect: SymRead,
 +              asm:       x86.AVPUNPCKLDQ,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
 +                              {0, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:      "VPUNPCKLQDQ512load",
 +              auxType:   auxSymOff,
 +              argLen:    3,
 +              symEffect: SymRead,
 +              asm:       x86.AVPUNPCKLQDQ,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
 +                              {0, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:      "VPXORD512load",
 +              auxType:   auxSymOff,
 +              argLen:    3,
 +              symEffect: SymRead,
 +              asm:       x86.AVPXORD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
 +                              {0, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:      "VPXORDMasked128load",
 +              auxType:   auxSymOff,
 +              argLen:    4,
 +              symEffect: SymRead,
 +              asm:       x86.AVPXORD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {1, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
 +                              {0, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:      "VPXORDMasked256load",
 +              auxType:   auxSymOff,
 +              argLen:    4,
 +              symEffect: SymRead,
 +              asm:       x86.AVPXORD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {1, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
 +                              {0, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:      "VPXORDMasked512load",
 +              auxType:   auxSymOff,
 +              argLen:    4,
 +              symEffect: SymRead,
 +              asm:       x86.AVPXORD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {1, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
 +                              {0, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:      "VPXORQ512load",
 +              auxType:   auxSymOff,
 +              argLen:    3,
 +              symEffect: SymRead,
 +              asm:       x86.AVPXORQ,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
 +                              {0, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:      "VPXORQMasked128load",
 +              auxType:   auxSymOff,
 +              argLen:    4,
 +              symEffect: SymRead,
 +              asm:       x86.AVPXORQ,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {1, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
 +                              {0, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:      "VPXORQMasked256load",
 +              auxType:   auxSymOff,
 +              argLen:    4,
 +              symEffect: SymRead,
 +              asm:       x86.AVPXORQ,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {1, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
 +                              {0, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:      "VPXORQMasked512load",
 +              auxType:   auxSymOff,
 +              argLen:    4,
 +              symEffect: SymRead,
 +              asm:       x86.AVPXORQ,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {1, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
 +                              {0, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:      "VRCP14PD128load",
 +              auxType:   auxSymOff,
 +              argLen:    2,
 +              symEffect: SymRead,
 +              asm:       x86.AVRCP14PD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:      "VRCP14PD256load",
 +              auxType:   auxSymOff,
 +              argLen:    2,
 +              symEffect: SymRead,
 +              asm:       x86.AVRCP14PD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:      "VRCP14PD512load",
 +              auxType:   auxSymOff,
 +              argLen:    2,
 +              symEffect: SymRead,
 +              asm:       x86.AVRCP14PD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:      "VRCP14PDMasked128load",
 +              auxType:   auxSymOff,
 +              argLen:    3,
 +              symEffect: SymRead,
 +              asm:       x86.AVRCP14PD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:      "VRCP14PDMasked256load",
 +              auxType:   auxSymOff,
 +              argLen:    3,
 +              symEffect: SymRead,
 +              asm:       x86.AVRCP14PD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:      "VRCP14PDMasked512load",
 +              auxType:   auxSymOff,
 +              argLen:    3,
 +              symEffect: SymRead,
 +              asm:       x86.AVRCP14PD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:      "VRCP14PS512load",
 +              auxType:   auxSymOff,
 +              argLen:    2,
 +              symEffect: SymRead,
 +              asm:       x86.AVRCP14PS,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:      "VRCP14PSMasked128load",
 +              auxType:   auxSymOff,
 +              argLen:    3,
 +              symEffect: SymRead,
 +              asm:       x86.AVRCP14PS,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:      "VRCP14PSMasked256load",
 +              auxType:   auxSymOff,
 +              argLen:    3,
 +              symEffect: SymRead,
 +              asm:       x86.AVRCP14PS,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:      "VRCP14PSMasked512load",
 +              auxType:   auxSymOff,
 +              argLen:    3,
 +              symEffect: SymRead,
 +              asm:       x86.AVRCP14PS,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:      "VRSQRT14PD128load",
 +              auxType:   auxSymOff,
 +              argLen:    2,
 +              symEffect: SymRead,
 +              asm:       x86.AVRSQRT14PD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:      "VRSQRT14PD256load",
 +              auxType:   auxSymOff,
 +              argLen:    2,
 +              symEffect: SymRead,
 +              asm:       x86.AVRSQRT14PD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:      "VRSQRT14PD512load",
 +              auxType:   auxSymOff,
 +              argLen:    2,
 +              symEffect: SymRead,
 +              asm:       x86.AVRSQRT14PD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:      "VRSQRT14PDMasked128load",
 +              auxType:   auxSymOff,
 +              argLen:    3,
 +              symEffect: SymRead,
 +              asm:       x86.AVRSQRT14PD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:      "VRSQRT14PDMasked256load",
 +              auxType:   auxSymOff,
 +              argLen:    3,
 +              symEffect: SymRead,
 +              asm:       x86.AVRSQRT14PD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:      "VRSQRT14PDMasked512load",
 +              auxType:   auxSymOff,
 +              argLen:    3,
 +              symEffect: SymRead,
 +              asm:       x86.AVRSQRT14PD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:      "VRSQRT14PS512load",
 +              auxType:   auxSymOff,
 +              argLen:    2,
 +              symEffect: SymRead,
 +              asm:       x86.AVRSQRT14PS,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:      "VRSQRT14PSMasked128load",
 +              auxType:   auxSymOff,
 +              argLen:    3,
 +              symEffect: SymRead,
 +              asm:       x86.AVRSQRT14PS,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:      "VRSQRT14PSMasked256load",
 +              auxType:   auxSymOff,
 +              argLen:    3,
 +              symEffect: SymRead,
 +              asm:       x86.AVRSQRT14PS,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:      "VRSQRT14PSMasked512load",
 +              auxType:   auxSymOff,
 +              argLen:    3,
 +              symEffect: SymRead,
 +              asm:       x86.AVRSQRT14PS,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:      "VSCALEFPD128load",
 +              auxType:   auxSymOff,
 +              argLen:    3,
 +              symEffect: SymRead,
 +              asm:       x86.AVSCALEFPD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
 +                              {0, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:      "VSCALEFPD256load",
 +              auxType:   auxSymOff,
 +              argLen:    3,
 +              symEffect: SymRead,
 +              asm:       x86.AVSCALEFPD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
 +                              {0, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:      "VSCALEFPD512load",
 +              auxType:   auxSymOff,
 +              argLen:    3,
 +              symEffect: SymRead,
 +              asm:       x86.AVSCALEFPD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
 +                              {0, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:      "VSCALEFPDMasked128load",
 +              auxType:   auxSymOff,
 +              argLen:    4,
 +              symEffect: SymRead,
 +              asm:       x86.AVSCALEFPD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {1, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
 +                              {0, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:      "VSCALEFPDMasked256load",
 +              auxType:   auxSymOff,
 +              argLen:    4,
 +              symEffect: SymRead,
 +              asm:       x86.AVSCALEFPD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {1, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
 +                              {0, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:      "VSCALEFPDMasked512load",
 +              auxType:   auxSymOff,
 +              argLen:    4,
 +              symEffect: SymRead,
 +              asm:       x86.AVSCALEFPD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {1, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
 +                              {0, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:      "VSCALEFPS128load",
 +              auxType:   auxSymOff,
 +              argLen:    3,
 +              symEffect: SymRead,
 +              asm:       x86.AVSCALEFPS,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
 +                              {0, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:      "VSCALEFPS256load",
 +              auxType:   auxSymOff,
 +              argLen:    3,
 +              symEffect: SymRead,
 +              asm:       x86.AVSCALEFPS,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
 +                              {0, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:      "VSCALEFPS512load",
 +              auxType:   auxSymOff,
 +              argLen:    3,
 +              symEffect: SymRead,
 +              asm:       x86.AVSCALEFPS,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
 +                              {0, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:      "VSCALEFPSMasked128load",
 +              auxType:   auxSymOff,
 +              argLen:    4,
 +              symEffect: SymRead,
 +              asm:       x86.AVSCALEFPS,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {1, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
 +                              {0, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:      "VSCALEFPSMasked256load",
 +              auxType:   auxSymOff,
 +              argLen:    4,
 +              symEffect: SymRead,
 +              asm:       x86.AVSCALEFPS,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {1, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
 +                              {0, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:      "VSCALEFPSMasked512load",
 +              auxType:   auxSymOff,
 +              argLen:    4,
 +              symEffect: SymRead,
 +              asm:       x86.AVSCALEFPS,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {1, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
 +                              {0, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:      "VSQRTPD512load",
 +              auxType:   auxSymOff,
 +              argLen:    2,
 +              symEffect: SymRead,
 +              asm:       x86.AVSQRTPD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:      "VSQRTPDMasked128load",
 +              auxType:   auxSymOff,
 +              argLen:    3,
 +              symEffect: SymRead,
 +              asm:       x86.AVSQRTPD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:      "VSQRTPDMasked256load",
 +              auxType:   auxSymOff,
 +              argLen:    3,
 +              symEffect: SymRead,
 +              asm:       x86.AVSQRTPD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:      "VSQRTPDMasked512load",
 +              auxType:   auxSymOff,
 +              argLen:    3,
 +              symEffect: SymRead,
 +              asm:       x86.AVSQRTPD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:      "VSQRTPS512load",
 +              auxType:   auxSymOff,
 +              argLen:    2,
 +              symEffect: SymRead,
 +              asm:       x86.AVSQRTPS,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:      "VSQRTPSMasked128load",
 +              auxType:   auxSymOff,
 +              argLen:    3,
 +              symEffect: SymRead,
 +              asm:       x86.AVSQRTPS,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:      "VSQRTPSMasked256load",
 +              auxType:   auxSymOff,
 +              argLen:    3,
 +              symEffect: SymRead,
 +              asm:       x86.AVSQRTPS,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:      "VSQRTPSMasked512load",
 +              auxType:   auxSymOff,
 +              argLen:    3,
 +              symEffect: SymRead,
 +              asm:       x86.AVSQRTPS,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:      "VSUBPD512load",
 +              auxType:   auxSymOff,
 +              argLen:    3,
 +              symEffect: SymRead,
 +              asm:       x86.AVSUBPD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
 +                              {0, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:      "VSUBPDMasked128load",
 +              auxType:   auxSymOff,
 +              argLen:    4,
 +              symEffect: SymRead,
 +              asm:       x86.AVSUBPD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {1, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
 +                              {0, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:      "VSUBPDMasked256load",
 +              auxType:   auxSymOff,
 +              argLen:    4,
 +              symEffect: SymRead,
 +              asm:       x86.AVSUBPD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {1, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
 +                              {0, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:      "VSUBPDMasked512load",
 +              auxType:   auxSymOff,
 +              argLen:    4,
 +              symEffect: SymRead,
 +              asm:       x86.AVSUBPD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {1, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
 +                              {0, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:      "VSUBPS512load",
 +              auxType:   auxSymOff,
 +              argLen:    3,
 +              symEffect: SymRead,
 +              asm:       x86.AVSUBPS,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
 +                              {0, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:      "VSUBPSMasked128load",
 +              auxType:   auxSymOff,
 +              argLen:    4,
 +              symEffect: SymRead,
 +              asm:       x86.AVSUBPS,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {1, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
 +                              {0, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:      "VSUBPSMasked256load",
 +              auxType:   auxSymOff,
 +              argLen:    4,
 +              symEffect: SymRead,
 +              asm:       x86.AVSUBPS,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {1, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
 +                              {0, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:      "VSUBPSMasked512load",
 +              auxType:   auxSymOff,
 +              argLen:    4,
 +              symEffect: SymRead,
 +              asm:       x86.AVSUBPS,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {1, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
 +                              {0, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:      "VCMPPD512load",
 +              auxType:   auxSymValAndOff,
 +              argLen:    3,
 +              symEffect: SymRead,
 +              asm:       x86.AVCMPPD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
 +                              {0, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                      },
 +              },
 +      },
 +      {
 +              name:      "VCMPPDMasked128load",
 +              auxType:   auxSymValAndOff,
 +              argLen:    4,
 +              symEffect: SymRead,
 +              asm:       x86.AVCMPPD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {1, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
 +                              {0, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                      },
 +              },
 +      },
 +      {
 +              name:      "VCMPPDMasked256load",
 +              auxType:   auxSymValAndOff,
 +              argLen:    4,
 +              symEffect: SymRead,
 +              asm:       x86.AVCMPPD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {1, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
 +                              {0, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                      },
 +              },
 +      },
 +      {
 +              name:      "VCMPPDMasked512load",
 +              auxType:   auxSymValAndOff,
 +              argLen:    4,
 +              symEffect: SymRead,
 +              asm:       x86.AVCMPPD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {1, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
 +                              {0, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                      },
 +              },
 +      },
 +      {
 +              name:      "VCMPPS512load",
 +              auxType:   auxSymValAndOff,
 +              argLen:    3,
 +              symEffect: SymRead,
 +              asm:       x86.AVCMPPS,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
 +                              {0, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                      },
 +              },
 +      },
 +      {
 +              name:      "VCMPPSMasked128load",
 +              auxType:   auxSymValAndOff,
 +              argLen:    4,
 +              symEffect: SymRead,
 +              asm:       x86.AVCMPPS,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {1, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
 +                              {0, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                      },
 +              },
 +      },
 +      {
 +              name:      "VCMPPSMasked256load",
 +              auxType:   auxSymValAndOff,
 +              argLen:    4,
 +              symEffect: SymRead,
 +              asm:       x86.AVCMPPS,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {1, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
 +                              {0, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                      },
 +              },
 +      },
 +      {
 +              name:      "VCMPPSMasked512load",
 +              auxType:   auxSymValAndOff,
 +              argLen:    4,
 +              symEffect: SymRead,
 +              asm:       x86.AVCMPPS,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {1, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
 +                              {0, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                      },
 +              },
 +      },
 +      {
 +              name:      "VGF2P8AFFINEINVQB128load",
 +              auxType:   auxSymValAndOff,
 +              argLen:    3,
 +              symEffect: SymRead,
 +              asm:       x86.AVGF2P8AFFINEINVQB,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
 +                              {0, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:      "VGF2P8AFFINEINVQB256load",
 +              auxType:   auxSymValAndOff,
 +              argLen:    3,
 +              symEffect: SymRead,
 +              asm:       x86.AVGF2P8AFFINEINVQB,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
 +                              {0, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:      "VGF2P8AFFINEINVQB512load",
 +              auxType:   auxSymValAndOff,
 +              argLen:    3,
 +              symEffect: SymRead,
 +              asm:       x86.AVGF2P8AFFINEINVQB,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
 +                              {0, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:      "VGF2P8AFFINEINVQBMasked128load",
 +              auxType:   auxSymValAndOff,
 +              argLen:    4,
 +              symEffect: SymRead,
 +              asm:       x86.AVGF2P8AFFINEINVQB,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {1, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
 +                              {0, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:      "VGF2P8AFFINEINVQBMasked256load",
 +              auxType:   auxSymValAndOff,
 +              argLen:    4,
 +              symEffect: SymRead,
 +              asm:       x86.AVGF2P8AFFINEINVQB,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {1, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
 +                              {0, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:      "VGF2P8AFFINEINVQBMasked512load",
 +              auxType:   auxSymValAndOff,
 +              argLen:    4,
 +              symEffect: SymRead,
 +              asm:       x86.AVGF2P8AFFINEINVQB,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {1, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
 +                              {0, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:      "VGF2P8AFFINEQB128load",
 +              auxType:   auxSymValAndOff,
 +              argLen:    3,
 +              symEffect: SymRead,
 +              asm:       x86.AVGF2P8AFFINEQB,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
 +                              {0, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:      "VGF2P8AFFINEQB256load",
 +              auxType:   auxSymValAndOff,
 +              argLen:    3,
 +              symEffect: SymRead,
 +              asm:       x86.AVGF2P8AFFINEQB,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
 +                              {0, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:      "VGF2P8AFFINEQB512load",
 +              auxType:   auxSymValAndOff,
 +              argLen:    3,
 +              symEffect: SymRead,
 +              asm:       x86.AVGF2P8AFFINEQB,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
 +                              {0, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:      "VGF2P8AFFINEQBMasked128load",
 +              auxType:   auxSymValAndOff,
 +              argLen:    4,
 +              symEffect: SymRead,
 +              asm:       x86.AVGF2P8AFFINEQB,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {1, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
 +                              {0, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:      "VGF2P8AFFINEQBMasked256load",
 +              auxType:   auxSymValAndOff,
 +              argLen:    4,
 +              symEffect: SymRead,
 +              asm:       x86.AVGF2P8AFFINEQB,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {1, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
 +                              {0, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:      "VGF2P8AFFINEQBMasked512load",
 +              auxType:   auxSymValAndOff,
 +              argLen:    4,
 +              symEffect: SymRead,
 +              asm:       x86.AVGF2P8AFFINEQB,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {1, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
 +                              {0, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:      "VPCMPD512load",
 +              auxType:   auxSymValAndOff,
 +              argLen:    3,
 +              symEffect: SymRead,
 +              asm:       x86.AVPCMPD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
 +                              {0, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                      },
 +              },
 +      },
 +      {
 +              name:      "VPCMPDMasked128load",
 +              auxType:   auxSymValAndOff,
 +              argLen:    4,
 +              symEffect: SymRead,
 +              asm:       x86.AVPCMPD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {1, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
 +                              {0, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                      },
 +              },
 +      },
 +      {
 +              name:      "VPCMPDMasked256load",
 +              auxType:   auxSymValAndOff,
 +              argLen:    4,
 +              symEffect: SymRead,
 +              asm:       x86.AVPCMPD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {1, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
 +                              {0, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                      },
 +              },
 +      },
 +      {
 +              name:      "VPCMPDMasked512load",
 +              auxType:   auxSymValAndOff,
 +              argLen:    4,
 +              symEffect: SymRead,
 +              asm:       x86.AVPCMPD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {1, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
 +                              {0, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                      },
 +              },
 +      },
 +      {
 +              name:      "VPCMPQ512load",
 +              auxType:   auxSymValAndOff,
 +              argLen:    3,
 +              symEffect: SymRead,
 +              asm:       x86.AVPCMPQ,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
 +                              {0, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                      },
 +              },
 +      },
 +      {
 +              name:      "VPCMPQMasked128load",
 +              auxType:   auxSymValAndOff,
 +              argLen:    4,
 +              symEffect: SymRead,
 +              asm:       x86.AVPCMPQ,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {1, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
 +                              {0, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                      },
 +              },
 +      },
 +      {
 +              name:      "VPCMPQMasked256load",
 +              auxType:   auxSymValAndOff,
 +              argLen:    4,
 +              symEffect: SymRead,
 +              asm:       x86.AVPCMPQ,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {1, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
 +                              {0, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                      },
 +              },
 +      },
 +      {
 +              name:      "VPCMPQMasked512load",
 +              auxType:   auxSymValAndOff,
 +              argLen:    4,
 +              symEffect: SymRead,
 +              asm:       x86.AVPCMPQ,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {1, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
 +                              {0, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                      },
 +              },
 +      },
 +      {
 +              name:      "VPCMPUD512load",
 +              auxType:   auxSymValAndOff,
 +              argLen:    3,
 +              symEffect: SymRead,
 +              asm:       x86.AVPCMPUD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
 +                              {0, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                      },
 +              },
 +      },
 +      {
 +              name:      "VPCMPUDMasked128load",
 +              auxType:   auxSymValAndOff,
 +              argLen:    4,
 +              symEffect: SymRead,
 +              asm:       x86.AVPCMPUD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {1, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
 +                              {0, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                      },
 +              },
 +      },
 +      {
 +              name:      "VPCMPUDMasked256load",
 +              auxType:   auxSymValAndOff,
 +              argLen:    4,
 +              symEffect: SymRead,
 +              asm:       x86.AVPCMPUD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {1, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
 +                              {0, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                      },
 +              },
 +      },
 +      {
 +              name:      "VPCMPUDMasked512load",
 +              auxType:   auxSymValAndOff,
 +              argLen:    4,
 +              symEffect: SymRead,
 +              asm:       x86.AVPCMPUD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {1, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
 +                              {0, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                      },
 +              },
 +      },
 +      {
 +              name:      "VPCMPUQ512load",
 +              auxType:   auxSymValAndOff,
 +              argLen:    3,
 +              symEffect: SymRead,
 +              asm:       x86.AVPCMPUQ,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
 +                              {0, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                      },
 +              },
 +      },
 +      {
 +              name:      "VPCMPUQMasked128load",
 +              auxType:   auxSymValAndOff,
 +              argLen:    4,
 +              symEffect: SymRead,
 +              asm:       x86.AVPCMPUQ,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {1, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
 +                              {0, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                      },
 +              },
 +      },
 +      {
 +              name:      "VPCMPUQMasked256load",
 +              auxType:   auxSymValAndOff,
 +              argLen:    4,
 +              symEffect: SymRead,
 +              asm:       x86.AVPCMPUQ,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {1, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
 +                              {0, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                      },
 +              },
 +      },
 +      {
 +              name:      "VPCMPUQMasked512load",
 +              auxType:   auxSymValAndOff,
 +              argLen:    4,
 +              symEffect: SymRead,
 +              asm:       x86.AVPCMPUQ,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {1, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
 +                              {0, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                      },
 +              },
 +      },
 +      {
 +              name:      "VPROLD128load",
 +              auxType:   auxSymValAndOff,
 +              argLen:    2,
 +              symEffect: SymRead,
 +              asm:       x86.AVPROLD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:      "VPROLD256load",
 +              auxType:   auxSymValAndOff,
 +              argLen:    2,
 +              symEffect: SymRead,
 +              asm:       x86.AVPROLD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:      "VPROLD512load",
 +              auxType:   auxSymValAndOff,
 +              argLen:    2,
 +              symEffect: SymRead,
 +              asm:       x86.AVPROLD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:      "VPROLDMasked128load",
 +              auxType:   auxSymValAndOff,
 +              argLen:    3,
 +              symEffect: SymRead,
 +              asm:       x86.AVPROLD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:      "VPROLDMasked256load",
 +              auxType:   auxSymValAndOff,
 +              argLen:    3,
 +              symEffect: SymRead,
 +              asm:       x86.AVPROLD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:      "VPROLDMasked512load",
 +              auxType:   auxSymValAndOff,
 +              argLen:    3,
 +              symEffect: SymRead,
 +              asm:       x86.AVPROLD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:      "VPROLQ128load",
 +              auxType:   auxSymValAndOff,
 +              argLen:    2,
 +              symEffect: SymRead,
 +              asm:       x86.AVPROLQ,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:      "VPROLQ256load",
 +              auxType:   auxSymValAndOff,
 +              argLen:    2,
 +              symEffect: SymRead,
 +              asm:       x86.AVPROLQ,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:      "VPROLQ512load",
 +              auxType:   auxSymValAndOff,
 +              argLen:    2,
 +              symEffect: SymRead,
 +              asm:       x86.AVPROLQ,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:      "VPROLQMasked128load",
 +              auxType:   auxSymValAndOff,
 +              argLen:    3,
 +              symEffect: SymRead,
 +              asm:       x86.AVPROLQ,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:      "VPROLQMasked256load",
 +              auxType:   auxSymValAndOff,
 +              argLen:    3,
 +              symEffect: SymRead,
 +              asm:       x86.AVPROLQ,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:      "VPROLQMasked512load",
 +              auxType:   auxSymValAndOff,
 +              argLen:    3,
 +              symEffect: SymRead,
 +              asm:       x86.AVPROLQ,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:      "VPRORD128load",
 +              auxType:   auxSymValAndOff,
 +              argLen:    2,
 +              symEffect: SymRead,
 +              asm:       x86.AVPRORD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:      "VPRORD256load",
 +              auxType:   auxSymValAndOff,
 +              argLen:    2,
 +              symEffect: SymRead,
 +              asm:       x86.AVPRORD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:      "VPRORD512load",
 +              auxType:   auxSymValAndOff,
 +              argLen:    2,
 +              symEffect: SymRead,
 +              asm:       x86.AVPRORD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:      "VPRORDMasked128load",
 +              auxType:   auxSymValAndOff,
 +              argLen:    3,
 +              symEffect: SymRead,
 +              asm:       x86.AVPRORD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:      "VPRORDMasked256load",
 +              auxType:   auxSymValAndOff,
 +              argLen:    3,
 +              symEffect: SymRead,
 +              asm:       x86.AVPRORD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:      "VPRORDMasked512load",
 +              auxType:   auxSymValAndOff,
 +              argLen:    3,
 +              symEffect: SymRead,
 +              asm:       x86.AVPRORD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:      "VPRORQ128load",
 +              auxType:   auxSymValAndOff,
 +              argLen:    2,
 +              symEffect: SymRead,
 +              asm:       x86.AVPRORQ,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:      "VPRORQ256load",
 +              auxType:   auxSymValAndOff,
 +              argLen:    2,
 +              symEffect: SymRead,
 +              asm:       x86.AVPRORQ,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:      "VPRORQ512load",
 +              auxType:   auxSymValAndOff,
 +              argLen:    2,
 +              symEffect: SymRead,
 +              asm:       x86.AVPRORQ,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:      "VPRORQMasked128load",
 +              auxType:   auxSymValAndOff,
 +              argLen:    3,
 +              symEffect: SymRead,
 +              asm:       x86.AVPRORQ,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:      "VPRORQMasked256load",
 +              auxType:   auxSymValAndOff,
 +              argLen:    3,
 +              symEffect: SymRead,
 +              asm:       x86.AVPRORQ,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:      "VPRORQMasked512load",
 +              auxType:   auxSymValAndOff,
 +              argLen:    3,
 +              symEffect: SymRead,
 +              asm:       x86.AVPRORQ,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:      "VPSHLDD128load",
 +              auxType:   auxSymValAndOff,
 +              argLen:    3,
 +              symEffect: SymRead,
 +              asm:       x86.AVPSHLDD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
 +                              {0, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:      "VPSHLDD256load",
 +              auxType:   auxSymValAndOff,
 +              argLen:    3,
 +              symEffect: SymRead,
 +              asm:       x86.AVPSHLDD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
 +                              {0, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:      "VPSHLDD512load",
 +              auxType:   auxSymValAndOff,
 +              argLen:    3,
 +              symEffect: SymRead,
 +              asm:       x86.AVPSHLDD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
 +                              {0, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:      "VPSHLDDMasked128load",
 +              auxType:   auxSymValAndOff,
 +              argLen:    4,
 +              symEffect: SymRead,
 +              asm:       x86.AVPSHLDD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {1, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
 +                              {0, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:      "VPSHLDDMasked256load",
 +              auxType:   auxSymValAndOff,
 +              argLen:    4,
 +              symEffect: SymRead,
 +              asm:       x86.AVPSHLDD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {1, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
 +                              {0, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:      "VPSHLDDMasked512load",
 +              auxType:   auxSymValAndOff,
 +              argLen:    4,
 +              symEffect: SymRead,
 +              asm:       x86.AVPSHLDD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {1, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
 +                              {0, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:      "VPSHLDQ128load",
 +              auxType:   auxSymValAndOff,
 +              argLen:    3,
 +              symEffect: SymRead,
 +              asm:       x86.AVPSHLDQ,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
 +                              {0, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:      "VPSHLDQ256load",
 +              auxType:   auxSymValAndOff,
 +              argLen:    3,
 +              symEffect: SymRead,
 +              asm:       x86.AVPSHLDQ,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
 +                              {0, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:      "VPSHLDQ512load",
 +              auxType:   auxSymValAndOff,
 +              argLen:    3,
 +              symEffect: SymRead,
 +              asm:       x86.AVPSHLDQ,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
 +                              {0, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:      "VPSHLDQMasked128load",
 +              auxType:   auxSymValAndOff,
 +              argLen:    4,
 +              symEffect: SymRead,
 +              asm:       x86.AVPSHLDQ,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {1, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
 +                              {0, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:      "VPSHLDQMasked256load",
 +              auxType:   auxSymValAndOff,
 +              argLen:    4,
 +              symEffect: SymRead,
 +              asm:       x86.AVPSHLDQ,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {1, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
 +                              {0, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:      "VPSHLDQMasked512load",
 +              auxType:   auxSymValAndOff,
 +              argLen:    4,
 +              symEffect: SymRead,
 +              asm:       x86.AVPSHLDQ,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {1, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
 +                              {0, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:      "VPSHRDD128load",
 +              auxType:   auxSymValAndOff,
 +              argLen:    3,
 +              symEffect: SymRead,
 +              asm:       x86.AVPSHRDD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
 +                              {0, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:      "VPSHRDD256load",
 +              auxType:   auxSymValAndOff,
 +              argLen:    3,
 +              symEffect: SymRead,
 +              asm:       x86.AVPSHRDD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
 +                              {0, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:      "VPSHRDD512load",
 +              auxType:   auxSymValAndOff,
 +              argLen:    3,
 +              symEffect: SymRead,
 +              asm:       x86.AVPSHRDD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
 +                              {0, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:      "VPSHRDDMasked128load",
 +              auxType:   auxSymValAndOff,
 +              argLen:    4,
 +              symEffect: SymRead,
 +              asm:       x86.AVPSHRDD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {1, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
 +                              {0, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:      "VPSHRDDMasked256load",
 +              auxType:   auxSymValAndOff,
 +              argLen:    4,
 +              symEffect: SymRead,
 +              asm:       x86.AVPSHRDD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {1, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
 +                              {0, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:      "VPSHRDDMasked512load",
 +              auxType:   auxSymValAndOff,
 +              argLen:    4,
 +              symEffect: SymRead,
 +              asm:       x86.AVPSHRDD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {1, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
 +                              {0, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:      "VPSHRDQ128load",
 +              auxType:   auxSymValAndOff,
 +              argLen:    3,
 +              symEffect: SymRead,
 +              asm:       x86.AVPSHRDQ,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
 +                              {0, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:      "VPSHRDQ256load",
 +              auxType:   auxSymValAndOff,
 +              argLen:    3,
 +              symEffect: SymRead,
 +              asm:       x86.AVPSHRDQ,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
 +                              {0, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:      "VPSHRDQ512load",
 +              auxType:   auxSymValAndOff,
 +              argLen:    3,
 +              symEffect: SymRead,
 +              asm:       x86.AVPSHRDQ,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
 +                              {0, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:      "VPSHRDQMasked128load",
 +              auxType:   auxSymValAndOff,
 +              argLen:    4,
 +              symEffect: SymRead,
 +              asm:       x86.AVPSHRDQ,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {1, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
 +                              {0, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:      "VPSHRDQMasked256load",
 +              auxType:   auxSymValAndOff,
 +              argLen:    4,
 +              symEffect: SymRead,
 +              asm:       x86.AVPSHRDQ,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {1, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
 +                              {0, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:      "VPSHRDQMasked512load",
 +              auxType:   auxSymValAndOff,
 +              argLen:    4,
 +              symEffect: SymRead,
 +              asm:       x86.AVPSHRDQ,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {1, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
 +                              {0, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:      "VPSHUFD512load",
 +              auxType:   auxSymValAndOff,
 +              argLen:    2,
 +              symEffect: SymRead,
 +              asm:       x86.AVPSHUFD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:      "VPSHUFDMasked128load",
 +              auxType:   auxSymValAndOff,
 +              argLen:    3,
 +              symEffect: SymRead,
 +              asm:       x86.AVPSHUFD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:      "VPSHUFDMasked256load",
 +              auxType:   auxSymValAndOff,
 +              argLen:    3,
 +              symEffect: SymRead,
 +              asm:       x86.AVPSHUFD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:      "VPSHUFDMasked512load",
 +              auxType:   auxSymValAndOff,
 +              argLen:    3,
 +              symEffect: SymRead,
 +              asm:       x86.AVPSHUFD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:      "VPSLLD512constload",
 +              auxType:   auxSymValAndOff,
 +              argLen:    2,
 +              symEffect: SymRead,
 +              asm:       x86.AVPSLLD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:      "VPSLLDMasked128constload",
 +              auxType:   auxSymValAndOff,
 +              argLen:    3,
 +              symEffect: SymRead,
 +              asm:       x86.AVPSLLD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:      "VPSLLDMasked256constload",
 +              auxType:   auxSymValAndOff,
 +              argLen:    3,
 +              symEffect: SymRead,
 +              asm:       x86.AVPSLLD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:      "VPSLLDMasked512constload",
 +              auxType:   auxSymValAndOff,
 +              argLen:    3,
 +              symEffect: SymRead,
 +              asm:       x86.AVPSLLD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:      "VPSLLQ512constload",
 +              auxType:   auxSymValAndOff,
 +              argLen:    2,
 +              symEffect: SymRead,
 +              asm:       x86.AVPSLLQ,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:      "VPSLLQMasked128constload",
 +              auxType:   auxSymValAndOff,
 +              argLen:    3,
 +              symEffect: SymRead,
 +              asm:       x86.AVPSLLQ,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:      "VPSLLQMasked256constload",
 +              auxType:   auxSymValAndOff,
 +              argLen:    3,
 +              symEffect: SymRead,
 +              asm:       x86.AVPSLLQ,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:      "VPSLLQMasked512constload",
 +              auxType:   auxSymValAndOff,
 +              argLen:    3,
 +              symEffect: SymRead,
 +              asm:       x86.AVPSLLQ,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:      "VPSRAD512constload",
 +              auxType:   auxSymValAndOff,
 +              argLen:    2,
 +              symEffect: SymRead,
 +              asm:       x86.AVPSRAD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:      "VPSRADMasked128constload",
 +              auxType:   auxSymValAndOff,
 +              argLen:    3,
 +              symEffect: SymRead,
 +              asm:       x86.AVPSRAD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:      "VPSRADMasked256constload",
 +              auxType:   auxSymValAndOff,
 +              argLen:    3,
 +              symEffect: SymRead,
 +              asm:       x86.AVPSRAD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:      "VPSRADMasked512constload",
 +              auxType:   auxSymValAndOff,
 +              argLen:    3,
 +              symEffect: SymRead,
 +              asm:       x86.AVPSRAD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:      "VPSRAQ128constload",
 +              auxType:   auxSymValAndOff,
 +              argLen:    2,
 +              symEffect: SymRead,
 +              asm:       x86.AVPSRAQ,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:      "VPSRAQ256constload",
 +              auxType:   auxSymValAndOff,
 +              argLen:    2,
 +              symEffect: SymRead,
 +              asm:       x86.AVPSRAQ,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:      "VPSRAQ512constload",
 +              auxType:   auxSymValAndOff,
 +              argLen:    2,
 +              symEffect: SymRead,
 +              asm:       x86.AVPSRAQ,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:      "VPSRAQMasked128constload",
 +              auxType:   auxSymValAndOff,
 +              argLen:    3,
 +              symEffect: SymRead,
 +              asm:       x86.AVPSRAQ,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:      "VPSRAQMasked256constload",
 +              auxType:   auxSymValAndOff,
 +              argLen:    3,
 +              symEffect: SymRead,
 +              asm:       x86.AVPSRAQ,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:      "VPSRAQMasked512constload",
 +              auxType:   auxSymValAndOff,
 +              argLen:    3,
 +              symEffect: SymRead,
 +              asm:       x86.AVPSRAQ,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:      "VPSRLD512constload",
 +              auxType:   auxSymValAndOff,
 +              argLen:    2,
 +              symEffect: SymRead,
 +              asm:       x86.AVPSRLD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:      "VPSRLDMasked128constload",
 +              auxType:   auxSymValAndOff,
 +              argLen:    3,
 +              symEffect: SymRead,
 +              asm:       x86.AVPSRLD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:      "VPSRLDMasked256constload",
 +              auxType:   auxSymValAndOff,
 +              argLen:    3,
 +              symEffect: SymRead,
 +              asm:       x86.AVPSRLD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:      "VPSRLDMasked512constload",
 +              auxType:   auxSymValAndOff,
 +              argLen:    3,
 +              symEffect: SymRead,
 +              asm:       x86.AVPSRLD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:      "VPSRLQ512constload",
 +              auxType:   auxSymValAndOff,
 +              argLen:    2,
 +              symEffect: SymRead,
 +              asm:       x86.AVPSRLQ,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:      "VPSRLQMasked128constload",
 +              auxType:   auxSymValAndOff,
 +              argLen:    3,
 +              symEffect: SymRead,
 +              asm:       x86.AVPSRLQ,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:      "VPSRLQMasked256constload",
 +              auxType:   auxSymValAndOff,
 +              argLen:    3,
 +              symEffect: SymRead,
 +              asm:       x86.AVPSRLQ,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:      "VPSRLQMasked512constload",
 +              auxType:   auxSymValAndOff,
 +              argLen:    3,
 +              symEffect: SymRead,
 +              asm:       x86.AVPSRLQ,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VPTERNLOGD128load",
 +              auxType:      auxSymValAndOff,
 +              argLen:       4,
 +              resultInArg0: true,
 +              symEffect:    SymRead,
 +              asm:          x86.AVPTERNLOGD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {2, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VPTERNLOGD256load",
 +              auxType:      auxSymValAndOff,
 +              argLen:       4,
 +              resultInArg0: true,
 +              symEffect:    SymRead,
 +              asm:          x86.AVPTERNLOGD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {2, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VPTERNLOGD512load",
 +              auxType:      auxSymValAndOff,
 +              argLen:       4,
 +              resultInArg0: true,
 +              symEffect:    SymRead,
 +              asm:          x86.AVPTERNLOGD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {2, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VPTERNLOGQ128load",
 +              auxType:      auxSymValAndOff,
 +              argLen:       4,
 +              resultInArg0: true,
 +              symEffect:    SymRead,
 +              asm:          x86.AVPTERNLOGQ,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {2, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VPTERNLOGQ256load",
 +              auxType:      auxSymValAndOff,
 +              argLen:       4,
 +              resultInArg0: true,
 +              symEffect:    SymRead,
 +              asm:          x86.AVPTERNLOGQ,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {2, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VPTERNLOGQ512load",
 +              auxType:      auxSymValAndOff,
 +              argLen:       4,
 +              resultInArg0: true,
 +              symEffect:    SymRead,
 +              asm:          x86.AVPTERNLOGQ,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {2, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:      "VREDUCEPD128load",
 +              auxType:   auxSymValAndOff,
 +              argLen:    2,
 +              symEffect: SymRead,
 +              asm:       x86.AVREDUCEPD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:      "VREDUCEPD256load",
 +              auxType:   auxSymValAndOff,
 +              argLen:    2,
 +              symEffect: SymRead,
 +              asm:       x86.AVREDUCEPD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:      "VREDUCEPD512load",
 +              auxType:   auxSymValAndOff,
 +              argLen:    2,
 +              symEffect: SymRead,
 +              asm:       x86.AVREDUCEPD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:      "VREDUCEPDMasked128load",
 +              auxType:   auxSymValAndOff,
 +              argLen:    3,
 +              symEffect: SymRead,
 +              asm:       x86.AVREDUCEPD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:      "VREDUCEPDMasked256load",
 +              auxType:   auxSymValAndOff,
 +              argLen:    3,
 +              symEffect: SymRead,
 +              asm:       x86.AVREDUCEPD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:      "VREDUCEPDMasked512load",
 +              auxType:   auxSymValAndOff,
 +              argLen:    3,
 +              symEffect: SymRead,
 +              asm:       x86.AVREDUCEPD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:      "VREDUCEPS128load",
 +              auxType:   auxSymValAndOff,
 +              argLen:    2,
 +              symEffect: SymRead,
 +              asm:       x86.AVREDUCEPS,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:      "VREDUCEPS256load",
 +              auxType:   auxSymValAndOff,
 +              argLen:    2,
 +              symEffect: SymRead,
 +              asm:       x86.AVREDUCEPS,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:      "VREDUCEPS512load",
 +              auxType:   auxSymValAndOff,
 +              argLen:    2,
 +              symEffect: SymRead,
 +              asm:       x86.AVREDUCEPS,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:      "VREDUCEPSMasked128load",
 +              auxType:   auxSymValAndOff,
 +              argLen:    3,
 +              symEffect: SymRead,
 +              asm:       x86.AVREDUCEPS,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:      "VREDUCEPSMasked256load",
 +              auxType:   auxSymValAndOff,
 +              argLen:    3,
 +              symEffect: SymRead,
 +              asm:       x86.AVREDUCEPS,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:      "VREDUCEPSMasked512load",
 +              auxType:   auxSymValAndOff,
 +              argLen:    3,
 +              symEffect: SymRead,
 +              asm:       x86.AVREDUCEPS,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:      "VRNDSCALEPD128load",
 +              auxType:   auxSymValAndOff,
 +              argLen:    2,
 +              symEffect: SymRead,
 +              asm:       x86.AVRNDSCALEPD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:      "VRNDSCALEPD256load",
 +              auxType:   auxSymValAndOff,
 +              argLen:    2,
 +              symEffect: SymRead,
 +              asm:       x86.AVRNDSCALEPD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:      "VRNDSCALEPD512load",
 +              auxType:   auxSymValAndOff,
 +              argLen:    2,
 +              symEffect: SymRead,
 +              asm:       x86.AVRNDSCALEPD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:      "VRNDSCALEPDMasked128load",
 +              auxType:   auxSymValAndOff,
 +              argLen:    3,
 +              symEffect: SymRead,
 +              asm:       x86.AVRNDSCALEPD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:      "VRNDSCALEPDMasked256load",
 +              auxType:   auxSymValAndOff,
 +              argLen:    3,
 +              symEffect: SymRead,
 +              asm:       x86.AVRNDSCALEPD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:      "VRNDSCALEPDMasked512load",
 +              auxType:   auxSymValAndOff,
 +              argLen:    3,
 +              symEffect: SymRead,
 +              asm:       x86.AVRNDSCALEPD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:      "VRNDSCALEPS128load",
 +              auxType:   auxSymValAndOff,
 +              argLen:    2,
 +              symEffect: SymRead,
 +              asm:       x86.AVRNDSCALEPS,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:      "VRNDSCALEPS256load",
 +              auxType:   auxSymValAndOff,
 +              argLen:    2,
 +              symEffect: SymRead,
 +              asm:       x86.AVRNDSCALEPS,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:      "VRNDSCALEPS512load",
 +              auxType:   auxSymValAndOff,
 +              argLen:    2,
 +              symEffect: SymRead,
 +              asm:       x86.AVRNDSCALEPS,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:      "VRNDSCALEPSMasked128load",
 +              auxType:   auxSymValAndOff,
 +              argLen:    3,
 +              symEffect: SymRead,
 +              asm:       x86.AVRNDSCALEPS,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:      "VRNDSCALEPSMasked256load",
 +              auxType:   auxSymValAndOff,
 +              argLen:    3,
 +              symEffect: SymRead,
 +              asm:       x86.AVRNDSCALEPS,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:      "VRNDSCALEPSMasked512load",
 +              auxType:   auxSymValAndOff,
 +              argLen:    3,
 +              symEffect: SymRead,
 +              asm:       x86.AVRNDSCALEPS,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:      "VSHUFPD512load",
 +              auxType:   auxSymValAndOff,
 +              argLen:    3,
 +              symEffect: SymRead,
 +              asm:       x86.AVSHUFPD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
 +                              {0, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:      "VSHUFPS512load",
 +              auxType:   auxSymValAndOff,
 +              argLen:    3,
 +              symEffect: SymRead,
 +              asm:       x86.AVSHUFPS,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
 +                              {0, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VADDPDMasked128Merging",
 +              argLen:       4,
 +              resultInArg0: true,
 +              asm:          x86.AVADDPD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {2, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VADDPDMasked256Merging",
 +              argLen:       4,
 +              resultInArg0: true,
 +              asm:          x86.AVADDPD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {2, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VADDPDMasked512Merging",
 +              argLen:       4,
 +              resultInArg0: true,
 +              asm:          x86.AVADDPD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {2, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VADDPSMasked128Merging",
 +              argLen:       4,
 +              resultInArg0: true,
 +              asm:          x86.AVADDPS,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {2, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VADDPSMasked256Merging",
 +              argLen:       4,
 +              resultInArg0: true,
 +              asm:          x86.AVADDPS,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {2, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VADDPSMasked512Merging",
 +              argLen:       4,
 +              resultInArg0: true,
 +              asm:          x86.AVADDPS,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {2, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VBROADCASTSDMasked256Merging",
 +              argLen:       3,
 +              resultInArg0: true,
 +              asm:          x86.AVBROADCASTSD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VBROADCASTSDMasked512Merging",
 +              argLen:       3,
 +              resultInArg0: true,
 +              asm:          x86.AVBROADCASTSD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VBROADCASTSSMasked128Merging",
 +              argLen:       3,
 +              resultInArg0: true,
 +              asm:          x86.AVBROADCASTSS,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VBROADCASTSSMasked256Merging",
 +              argLen:       3,
 +              resultInArg0: true,
 +              asm:          x86.AVBROADCASTSS,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VBROADCASTSSMasked512Merging",
 +              argLen:       3,
 +              resultInArg0: true,
 +              asm:          x86.AVBROADCASTSS,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VCVTPS2UDQMasked128Merging",
 +              argLen:       3,
 +              resultInArg0: true,
 +              asm:          x86.AVCVTPS2UDQ,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VCVTPS2UDQMasked256Merging",
 +              argLen:       3,
 +              resultInArg0: true,
 +              asm:          x86.AVCVTPS2UDQ,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VCVTPS2UDQMasked512Merging",
 +              argLen:       3,
 +              resultInArg0: true,
 +              asm:          x86.AVCVTPS2UDQ,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VCVTTPS2DQMasked128Merging",
 +              argLen:       3,
 +              resultInArg0: true,
 +              asm:          x86.AVCVTTPS2DQ,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VCVTTPS2DQMasked256Merging",
 +              argLen:       3,
 +              resultInArg0: true,
 +              asm:          x86.AVCVTTPS2DQ,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VCVTTPS2DQMasked512Merging",
 +              argLen:       3,
 +              resultInArg0: true,
 +              asm:          x86.AVCVTTPS2DQ,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VDIVPDMasked128Merging",
 +              argLen:       4,
 +              resultInArg0: true,
 +              asm:          x86.AVDIVPD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {2, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VDIVPDMasked256Merging",
 +              argLen:       4,
 +              resultInArg0: true,
 +              asm:          x86.AVDIVPD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {2, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VDIVPDMasked512Merging",
 +              argLen:       4,
 +              resultInArg0: true,
 +              asm:          x86.AVDIVPD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {2, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VDIVPSMasked128Merging",
 +              argLen:       4,
 +              resultInArg0: true,
 +              asm:          x86.AVDIVPS,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {2, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VDIVPSMasked256Merging",
 +              argLen:       4,
 +              resultInArg0: true,
 +              asm:          x86.AVDIVPS,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {2, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VDIVPSMasked512Merging",
 +              argLen:       4,
 +              resultInArg0: true,
 +              asm:          x86.AVDIVPS,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {2, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VGF2P8MULBMasked128Merging",
 +              argLen:       4,
 +              resultInArg0: true,
 +              asm:          x86.AVGF2P8MULB,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {2, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VGF2P8MULBMasked256Merging",
 +              argLen:       4,
 +              resultInArg0: true,
 +              asm:          x86.AVGF2P8MULB,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {2, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VGF2P8MULBMasked512Merging",
 +              argLen:       4,
 +              resultInArg0: true,
 +              asm:          x86.AVGF2P8MULB,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {2, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VMAXPDMasked128Merging",
 +              argLen:       4,
 +              resultInArg0: true,
 +              asm:          x86.AVMAXPD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {2, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VMAXPDMasked256Merging",
 +              argLen:       4,
 +              resultInArg0: true,
 +              asm:          x86.AVMAXPD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {2, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VMAXPDMasked512Merging",
 +              argLen:       4,
 +              resultInArg0: true,
 +              asm:          x86.AVMAXPD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {2, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VMAXPSMasked128Merging",
 +              argLen:       4,
 +              resultInArg0: true,
 +              asm:          x86.AVMAXPS,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {2, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VMAXPSMasked256Merging",
 +              argLen:       4,
 +              resultInArg0: true,
 +              asm:          x86.AVMAXPS,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {2, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VMAXPSMasked512Merging",
 +              argLen:       4,
 +              resultInArg0: true,
 +              asm:          x86.AVMAXPS,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {2, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VMINPDMasked128Merging",
 +              argLen:       4,
 +              resultInArg0: true,
 +              asm:          x86.AVMINPD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {2, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VMINPDMasked256Merging",
 +              argLen:       4,
 +              resultInArg0: true,
 +              asm:          x86.AVMINPD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {2, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VMINPDMasked512Merging",
 +              argLen:       4,
 +              resultInArg0: true,
 +              asm:          x86.AVMINPD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {2, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VMINPSMasked128Merging",
 +              argLen:       4,
 +              resultInArg0: true,
 +              asm:          x86.AVMINPS,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {2, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VMINPSMasked256Merging",
 +              argLen:       4,
 +              resultInArg0: true,
 +              asm:          x86.AVMINPS,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {2, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VMINPSMasked512Merging",
 +              argLen:       4,
 +              resultInArg0: true,
 +              asm:          x86.AVMINPS,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {2, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VMULPDMasked128Merging",
 +              argLen:       4,
 +              resultInArg0: true,
 +              asm:          x86.AVMULPD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {2, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VMULPDMasked256Merging",
 +              argLen:       4,
 +              resultInArg0: true,
 +              asm:          x86.AVMULPD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {2, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VMULPDMasked512Merging",
 +              argLen:       4,
 +              resultInArg0: true,
 +              asm:          x86.AVMULPD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {2, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VMULPSMasked128Merging",
 +              argLen:       4,
 +              resultInArg0: true,
 +              asm:          x86.AVMULPS,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {2, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VMULPSMasked256Merging",
 +              argLen:       4,
 +              resultInArg0: true,
 +              asm:          x86.AVMULPS,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {2, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VMULPSMasked512Merging",
 +              argLen:       4,
 +              resultInArg0: true,
 +              asm:          x86.AVMULPS,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {2, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VPABSBMasked128Merging",
 +              argLen:       3,
 +              resultInArg0: true,
 +              asm:          x86.AVPABSB,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VPABSBMasked256Merging",
 +              argLen:       3,
 +              resultInArg0: true,
 +              asm:          x86.AVPABSB,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VPABSBMasked512Merging",
 +              argLen:       3,
 +              resultInArg0: true,
 +              asm:          x86.AVPABSB,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VPABSDMasked128Merging",
 +              argLen:       3,
 +              resultInArg0: true,
 +              asm:          x86.AVPABSD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VPABSDMasked256Merging",
 +              argLen:       3,
 +              resultInArg0: true,
 +              asm:          x86.AVPABSD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VPABSDMasked512Merging",
 +              argLen:       3,
 +              resultInArg0: true,
 +              asm:          x86.AVPABSD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VPABSQMasked128Merging",
 +              argLen:       3,
 +              resultInArg0: true,
 +              asm:          x86.AVPABSQ,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VPABSQMasked256Merging",
 +              argLen:       3,
 +              resultInArg0: true,
 +              asm:          x86.AVPABSQ,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VPABSQMasked512Merging",
 +              argLen:       3,
 +              resultInArg0: true,
 +              asm:          x86.AVPABSQ,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VPABSWMasked128Merging",
 +              argLen:       3,
 +              resultInArg0: true,
 +              asm:          x86.AVPABSW,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VPABSWMasked256Merging",
 +              argLen:       3,
 +              resultInArg0: true,
 +              asm:          x86.AVPABSW,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VPABSWMasked512Merging",
 +              argLen:       3,
 +              resultInArg0: true,
 +              asm:          x86.AVPABSW,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VPACKSSDWMasked128Merging",
 +              argLen:       4,
 +              resultInArg0: true,
 +              asm:          x86.AVPACKSSDW,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {2, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VPACKSSDWMasked256Merging",
 +              argLen:       4,
 +              resultInArg0: true,
 +              asm:          x86.AVPACKSSDW,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {2, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VPACKSSDWMasked512Merging",
 +              argLen:       4,
 +              resultInArg0: true,
 +              asm:          x86.AVPACKSSDW,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {2, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VPACKUSDWMasked128Merging",
 +              argLen:       4,
 +              resultInArg0: true,
 +              asm:          x86.AVPACKUSDW,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {2, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VPACKUSDWMasked256Merging",
 +              argLen:       4,
 +              resultInArg0: true,
 +              asm:          x86.AVPACKUSDW,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {2, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VPACKUSDWMasked512Merging",
 +              argLen:       4,
 +              resultInArg0: true,
 +              asm:          x86.AVPACKUSDW,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {2, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VPADDBMasked128Merging",
 +              argLen:       4,
 +              resultInArg0: true,
 +              asm:          x86.AVPADDB,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {2, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VPADDBMasked256Merging",
 +              argLen:       4,
 +              resultInArg0: true,
 +              asm:          x86.AVPADDB,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {2, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VPADDBMasked512Merging",
 +              argLen:       4,
 +              resultInArg0: true,
 +              asm:          x86.AVPADDB,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {2, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VPADDDMasked128Merging",
 +              argLen:       4,
 +              resultInArg0: true,
 +              asm:          x86.AVPADDD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {2, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VPADDDMasked256Merging",
 +              argLen:       4,
 +              resultInArg0: true,
 +              asm:          x86.AVPADDD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {2, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VPADDDMasked512Merging",
 +              argLen:       4,
 +              resultInArg0: true,
 +              asm:          x86.AVPADDD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {2, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VPADDQMasked128Merging",
 +              argLen:       4,
 +              resultInArg0: true,
 +              asm:          x86.AVPADDQ,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {2, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VPADDQMasked256Merging",
 +              argLen:       4,
 +              resultInArg0: true,
 +              asm:          x86.AVPADDQ,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {2, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VPADDQMasked512Merging",
 +              argLen:       4,
 +              resultInArg0: true,
 +              asm:          x86.AVPADDQ,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {2, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VPADDSBMasked128Merging",
 +              argLen:       4,
 +              resultInArg0: true,
 +              asm:          x86.AVPADDSB,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {2, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VPADDSBMasked256Merging",
 +              argLen:       4,
 +              resultInArg0: true,
 +              asm:          x86.AVPADDSB,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {2, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VPADDSBMasked512Merging",
 +              argLen:       4,
 +              resultInArg0: true,
 +              asm:          x86.AVPADDSB,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {2, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VPADDSWMasked128Merging",
 +              argLen:       4,
 +              resultInArg0: true,
 +              asm:          x86.AVPADDSW,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {2, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VPADDSWMasked256Merging",
 +              argLen:       4,
 +              resultInArg0: true,
 +              asm:          x86.AVPADDSW,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {2, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VPADDSWMasked512Merging",
 +              argLen:       4,
 +              resultInArg0: true,
 +              asm:          x86.AVPADDSW,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {2, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VPADDUSBMasked128Merging",
 +              argLen:       4,
 +              resultInArg0: true,
 +              asm:          x86.AVPADDUSB,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {2, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VPADDUSBMasked256Merging",
 +              argLen:       4,
 +              resultInArg0: true,
 +              asm:          x86.AVPADDUSB,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {2, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VPADDUSBMasked512Merging",
 +              argLen:       4,
 +              resultInArg0: true,
 +              asm:          x86.AVPADDUSB,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {2, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VPADDUSWMasked128Merging",
 +              argLen:       4,
 +              resultInArg0: true,
 +              asm:          x86.AVPADDUSW,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {2, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VPADDUSWMasked256Merging",
 +              argLen:       4,
 +              resultInArg0: true,
 +              asm:          x86.AVPADDUSW,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {2, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VPADDUSWMasked512Merging",
 +              argLen:       4,
 +              resultInArg0: true,
 +              asm:          x86.AVPADDUSW,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {2, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VPADDWMasked128Merging",
 +              argLen:       4,
 +              resultInArg0: true,
 +              asm:          x86.AVPADDW,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {2, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VPADDWMasked256Merging",
 +              argLen:       4,
 +              resultInArg0: true,
 +              asm:          x86.AVPADDW,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {2, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VPADDWMasked512Merging",
 +              argLen:       4,
 +              resultInArg0: true,
 +              asm:          x86.AVPADDW,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {2, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VPANDDMasked128Merging",
 +              argLen:       4,
 +              resultInArg0: true,
 +              asm:          x86.AVPANDD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {2, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VPANDDMasked256Merging",
 +              argLen:       4,
 +              resultInArg0: true,
 +              asm:          x86.AVPANDD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {2, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VPANDDMasked512Merging",
 +              argLen:       4,
 +              resultInArg0: true,
 +              asm:          x86.AVPANDD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {2, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VPANDQMasked128Merging",
 +              argLen:       4,
 +              resultInArg0: true,
 +              asm:          x86.AVPANDQ,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {2, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VPANDQMasked256Merging",
 +              argLen:       4,
 +              resultInArg0: true,
 +              asm:          x86.AVPANDQ,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {2, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VPANDQMasked512Merging",
 +              argLen:       4,
 +              resultInArg0: true,
 +              asm:          x86.AVPANDQ,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {2, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VPAVGBMasked128Merging",
 +              argLen:       4,
 +              resultInArg0: true,
 +              asm:          x86.AVPAVGB,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {2, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VPAVGBMasked256Merging",
 +              argLen:       4,
 +              resultInArg0: true,
 +              asm:          x86.AVPAVGB,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {2, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VPAVGBMasked512Merging",
 +              argLen:       4,
 +              resultInArg0: true,
 +              asm:          x86.AVPAVGB,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {2, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VPAVGWMasked128Merging",
 +              argLen:       4,
 +              resultInArg0: true,
 +              asm:          x86.AVPAVGW,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {2, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VPAVGWMasked256Merging",
 +              argLen:       4,
 +              resultInArg0: true,
 +              asm:          x86.AVPAVGW,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {2, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VPAVGWMasked512Merging",
 +              argLen:       4,
 +              resultInArg0: true,
 +              asm:          x86.AVPAVGW,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {2, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VPBROADCASTBMasked128Merging",
 +              argLen:       3,
 +              resultInArg0: true,
 +              asm:          x86.AVPBROADCASTB,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VPBROADCASTBMasked256Merging",
 +              argLen:       3,
 +              resultInArg0: true,
 +              asm:          x86.AVPBROADCASTB,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VPBROADCASTBMasked512Merging",
 +              argLen:       3,
 +              resultInArg0: true,
 +              asm:          x86.AVPBROADCASTB,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VPBROADCASTDMasked128Merging",
 +              argLen:       3,
 +              resultInArg0: true,
 +              asm:          x86.AVPBROADCASTD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VPBROADCASTDMasked256Merging",
 +              argLen:       3,
 +              resultInArg0: true,
 +              asm:          x86.AVPBROADCASTD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VPBROADCASTDMasked512Merging",
 +              argLen:       3,
 +              resultInArg0: true,
 +              asm:          x86.AVPBROADCASTD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VPBROADCASTQMasked128Merging",
 +              argLen:       3,
 +              resultInArg0: true,
 +              asm:          x86.AVPBROADCASTQ,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VPBROADCASTQMasked256Merging",
 +              argLen:       3,
 +              resultInArg0: true,
 +              asm:          x86.AVPBROADCASTQ,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VPBROADCASTQMasked512Merging",
 +              argLen:       3,
 +              resultInArg0: true,
 +              asm:          x86.AVPBROADCASTQ,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VPBROADCASTWMasked128Merging",
 +              argLen:       3,
 +              resultInArg0: true,
 +              asm:          x86.AVPBROADCASTW,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VPBROADCASTWMasked256Merging",
 +              argLen:       3,
 +              resultInArg0: true,
 +              asm:          x86.AVPBROADCASTW,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VPBROADCASTWMasked512Merging",
 +              argLen:       3,
 +              resultInArg0: true,
 +              asm:          x86.AVPBROADCASTW,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VPLZCNTDMasked128Merging",
 +              argLen:       3,
 +              resultInArg0: true,
 +              asm:          x86.AVPLZCNTD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VPLZCNTDMasked256Merging",
 +              argLen:       3,
 +              resultInArg0: true,
 +              asm:          x86.AVPLZCNTD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VPLZCNTDMasked512Merging",
 +              argLen:       3,
 +              resultInArg0: true,
 +              asm:          x86.AVPLZCNTD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VPLZCNTQMasked128Merging",
 +              argLen:       3,
 +              resultInArg0: true,
 +              asm:          x86.AVPLZCNTQ,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VPLZCNTQMasked256Merging",
 +              argLen:       3,
 +              resultInArg0: true,
 +              asm:          x86.AVPLZCNTQ,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VPLZCNTQMasked512Merging",
 +              argLen:       3,
 +              resultInArg0: true,
 +              asm:          x86.AVPLZCNTQ,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VPMADDUBSWMasked128Merging",
 +              argLen:       4,
 +              resultInArg0: true,
 +              asm:          x86.AVPMADDUBSW,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {2, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VPMADDUBSWMasked256Merging",
 +              argLen:       4,
 +              resultInArg0: true,
 +              asm:          x86.AVPMADDUBSW,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {2, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VPMADDUBSWMasked512Merging",
 +              argLen:       4,
 +              resultInArg0: true,
 +              asm:          x86.AVPMADDUBSW,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {2, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VPMADDWDMasked128Merging",
 +              argLen:       4,
 +              resultInArg0: true,
 +              asm:          x86.AVPMADDWD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {2, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VPMADDWDMasked256Merging",
 +              argLen:       4,
 +              resultInArg0: true,
 +              asm:          x86.AVPMADDWD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {2, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VPMADDWDMasked512Merging",
 +              argLen:       4,
 +              resultInArg0: true,
 +              asm:          x86.AVPMADDWD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {2, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VPMAXSBMasked128Merging",
 +              argLen:       4,
 +              resultInArg0: true,
 +              asm:          x86.AVPMAXSB,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {2, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VPMAXSBMasked256Merging",
 +              argLen:       4,
 +              resultInArg0: true,
 +              asm:          x86.AVPMAXSB,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {2, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VPMAXSBMasked512Merging",
 +              argLen:       4,
 +              resultInArg0: true,
 +              asm:          x86.AVPMAXSB,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {2, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VPMAXSDMasked128Merging",
 +              argLen:       4,
 +              resultInArg0: true,
 +              asm:          x86.AVPMAXSD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {2, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VPMAXSDMasked256Merging",
 +              argLen:       4,
 +              resultInArg0: true,
 +              asm:          x86.AVPMAXSD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {2, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VPMAXSDMasked512Merging",
 +              argLen:       4,
 +              resultInArg0: true,
 +              asm:          x86.AVPMAXSD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {2, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VPMAXSQMasked128Merging",
 +              argLen:       4,
 +              resultInArg0: true,
 +              asm:          x86.AVPMAXSQ,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {2, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VPMAXSQMasked256Merging",
 +              argLen:       4,
 +              resultInArg0: true,
 +              asm:          x86.AVPMAXSQ,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {2, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VPMAXSQMasked512Merging",
 +              argLen:       4,
 +              resultInArg0: true,
 +              asm:          x86.AVPMAXSQ,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {2, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VPMAXSWMasked128Merging",
 +              argLen:       4,
 +              resultInArg0: true,
 +              asm:          x86.AVPMAXSW,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {2, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VPMAXSWMasked256Merging",
 +              argLen:       4,
 +              resultInArg0: true,
 +              asm:          x86.AVPMAXSW,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {2, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VPMAXSWMasked512Merging",
 +              argLen:       4,
 +              resultInArg0: true,
 +              asm:          x86.AVPMAXSW,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {2, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VPMAXUBMasked128Merging",
 +              argLen:       4,
 +              resultInArg0: true,
 +              asm:          x86.AVPMAXUB,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {2, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VPMAXUBMasked256Merging",
 +              argLen:       4,
 +              resultInArg0: true,
 +              asm:          x86.AVPMAXUB,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {2, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VPMAXUBMasked512Merging",
 +              argLen:       4,
 +              resultInArg0: true,
 +              asm:          x86.AVPMAXUB,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {2, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VPMAXUDMasked128Merging",
 +              argLen:       4,
 +              resultInArg0: true,
 +              asm:          x86.AVPMAXUD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {2, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VPMAXUDMasked256Merging",
 +              argLen:       4,
 +              resultInArg0: true,
 +              asm:          x86.AVPMAXUD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {2, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VPMAXUDMasked512Merging",
 +              argLen:       4,
 +              resultInArg0: true,
 +              asm:          x86.AVPMAXUD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {2, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VPMAXUQMasked128Merging",
 +              argLen:       4,
 +              resultInArg0: true,
 +              asm:          x86.AVPMAXUQ,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {2, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VPMAXUQMasked256Merging",
 +              argLen:       4,
 +              resultInArg0: true,
 +              asm:          x86.AVPMAXUQ,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {2, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VPMAXUQMasked512Merging",
 +              argLen:       4,
 +              resultInArg0: true,
 +              asm:          x86.AVPMAXUQ,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {2, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VPMAXUWMasked128Merging",
 +              argLen:       4,
 +              resultInArg0: true,
 +              asm:          x86.AVPMAXUW,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {2, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VPMAXUWMasked256Merging",
 +              argLen:       4,
 +              resultInArg0: true,
 +              asm:          x86.AVPMAXUW,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {2, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VPMAXUWMasked512Merging",
 +              argLen:       4,
 +              resultInArg0: true,
 +              asm:          x86.AVPMAXUW,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {2, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VPMINSBMasked128Merging",
 +              argLen:       4,
 +              resultInArg0: true,
 +              asm:          x86.AVPMINSB,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {2, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VPMINSBMasked256Merging",
 +              argLen:       4,
 +              resultInArg0: true,
 +              asm:          x86.AVPMINSB,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {2, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VPMINSBMasked512Merging",
 +              argLen:       4,
 +              resultInArg0: true,
 +              asm:          x86.AVPMINSB,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {2, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VPMINSDMasked128Merging",
 +              argLen:       4,
 +              resultInArg0: true,
 +              asm:          x86.AVPMINSD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {2, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VPMINSDMasked256Merging",
 +              argLen:       4,
 +              resultInArg0: true,
 +              asm:          x86.AVPMINSD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {2, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VPMINSDMasked512Merging",
 +              argLen:       4,
 +              resultInArg0: true,
 +              asm:          x86.AVPMINSD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {2, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VPMINSQMasked128Merging",
 +              argLen:       4,
 +              resultInArg0: true,
 +              asm:          x86.AVPMINSQ,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {2, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VPMINSQMasked256Merging",
 +              argLen:       4,
 +              resultInArg0: true,
 +              asm:          x86.AVPMINSQ,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {2, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VPMINSQMasked512Merging",
 +              argLen:       4,
 +              resultInArg0: true,
 +              asm:          x86.AVPMINSQ,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {2, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VPMINSWMasked128Merging",
 +              argLen:       4,
 +              resultInArg0: true,
 +              asm:          x86.AVPMINSW,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {2, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VPMINSWMasked256Merging",
 +              argLen:       4,
 +              resultInArg0: true,
 +              asm:          x86.AVPMINSW,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {2, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VPMINSWMasked512Merging",
 +              argLen:       4,
 +              resultInArg0: true,
 +              asm:          x86.AVPMINSW,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {2, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VPMINUBMasked128Merging",
 +              argLen:       4,
 +              resultInArg0: true,
 +              asm:          x86.AVPMINUB,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {2, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VPMINUBMasked256Merging",
 +              argLen:       4,
 +              resultInArg0: true,
 +              asm:          x86.AVPMINUB,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {2, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VPMINUBMasked512Merging",
 +              argLen:       4,
 +              resultInArg0: true,
 +              asm:          x86.AVPMINUB,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {2, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VPMINUDMasked128Merging",
 +              argLen:       4,
 +              resultInArg0: true,
 +              asm:          x86.AVPMINUD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {2, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VPMINUDMasked256Merging",
 +              argLen:       4,
 +              resultInArg0: true,
 +              asm:          x86.AVPMINUD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {2, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VPMINUDMasked512Merging",
 +              argLen:       4,
 +              resultInArg0: true,
 +              asm:          x86.AVPMINUD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {2, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VPMINUQMasked128Merging",
 +              argLen:       4,
 +              resultInArg0: true,
 +              asm:          x86.AVPMINUQ,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {2, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VPMINUQMasked256Merging",
 +              argLen:       4,
 +              resultInArg0: true,
 +              asm:          x86.AVPMINUQ,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {2, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VPMINUQMasked512Merging",
 +              argLen:       4,
 +              resultInArg0: true,
 +              asm:          x86.AVPMINUQ,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {2, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VPMINUWMasked128Merging",
 +              argLen:       4,
 +              resultInArg0: true,
 +              asm:          x86.AVPMINUW,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {2, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VPMINUWMasked256Merging",
 +              argLen:       4,
 +              resultInArg0: true,
 +              asm:          x86.AVPMINUW,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {2, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VPMINUWMasked512Merging",
 +              argLen:       4,
 +              resultInArg0: true,
 +              asm:          x86.AVPMINUW,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {2, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VPMOVDBMasked128_128Merging",
 +              argLen:       3,
 +              resultInArg0: true,
 +              asm:          x86.AVPMOVDB,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VPMOVDBMasked128_256Merging",
 +              argLen:       3,
 +              resultInArg0: true,
 +              asm:          x86.AVPMOVDB,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VPMOVDBMasked128_512Merging",
 +              argLen:       3,
 +              resultInArg0: true,
 +              asm:          x86.AVPMOVDB,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VPMOVDWMasked128_128Merging",
 +              argLen:       3,
 +              resultInArg0: true,
 +              asm:          x86.AVPMOVDW,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VPMOVDWMasked128_256Merging",
 +              argLen:       3,
 +              resultInArg0: true,
 +              asm:          x86.AVPMOVDW,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VPMOVDWMasked256Merging",
 +              argLen:       3,
 +              resultInArg0: true,
 +              asm:          x86.AVPMOVDW,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VPMOVQBMasked128_128Merging",
 +              argLen:       3,
 +              resultInArg0: true,
 +              asm:          x86.AVPMOVQB,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VPMOVQBMasked128_256Merging",
 +              argLen:       3,
 +              resultInArg0: true,
 +              asm:          x86.AVPMOVQB,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VPMOVQBMasked128_512Merging",
 +              argLen:       3,
 +              resultInArg0: true,
 +              asm:          x86.AVPMOVQB,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VPMOVQDMasked128_128Merging",
 +              argLen:       3,
 +              resultInArg0: true,
 +              asm:          x86.AVPMOVQD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VPMOVQDMasked128_256Merging",
 +              argLen:       3,
 +              resultInArg0: true,
 +              asm:          x86.AVPMOVQD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VPMOVQDMasked256Merging",
 +              argLen:       3,
 +              resultInArg0: true,
 +              asm:          x86.AVPMOVQD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VPMOVQWMasked128_128Merging",
 +              argLen:       3,
 +              resultInArg0: true,
 +              asm:          x86.AVPMOVQW,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VPMOVQWMasked128_256Merging",
 +              argLen:       3,
 +              resultInArg0: true,
 +              asm:          x86.AVPMOVQW,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VPMOVQWMasked128_512Merging",
 +              argLen:       3,
 +              resultInArg0: true,
 +              asm:          x86.AVPMOVQW,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VPMOVSDBMasked128_128Merging",
 +              argLen:       3,
 +              resultInArg0: true,
 +              asm:          x86.AVPMOVSDB,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VPMOVSDBMasked128_256Merging",
 +              argLen:       3,
 +              resultInArg0: true,
 +              asm:          x86.AVPMOVSDB,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VPMOVSDBMasked128_512Merging",
 +              argLen:       3,
 +              resultInArg0: true,
 +              asm:          x86.AVPMOVSDB,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VPMOVSDWMasked128_128Merging",
 +              argLen:       3,
 +              resultInArg0: true,
 +              asm:          x86.AVPMOVSDW,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VPMOVSDWMasked128_256Merging",
 +              argLen:       3,
 +              resultInArg0: true,
 +              asm:          x86.AVPMOVSDW,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VPMOVSDWMasked256Merging",
 +              argLen:       3,
 +              resultInArg0: true,
 +              asm:          x86.AVPMOVSDW,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VPMOVSQBMasked128_128Merging",
 +              argLen:       3,
 +              resultInArg0: true,
 +              asm:          x86.AVPMOVSQB,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VPMOVSQBMasked128_256Merging",
 +              argLen:       3,
 +              resultInArg0: true,
 +              asm:          x86.AVPMOVSQB,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VPMOVSQBMasked128_512Merging",
 +              argLen:       3,
 +              resultInArg0: true,
 +              asm:          x86.AVPMOVSQB,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VPMOVSQDMasked128_128Merging",
 +              argLen:       3,
 +              resultInArg0: true,
 +              asm:          x86.AVPMOVSQD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VPMOVSQDMasked128_256Merging",
 +              argLen:       3,
 +              resultInArg0: true,
 +              asm:          x86.AVPMOVSQD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VPMOVSQDMasked256Merging",
 +              argLen:       3,
 +              resultInArg0: true,
 +              asm:          x86.AVPMOVSQD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VPMOVSQWMasked128_128Merging",
 +              argLen:       3,
 +              resultInArg0: true,
 +              asm:          x86.AVPMOVSQW,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VPMOVSQWMasked128_256Merging",
 +              argLen:       3,
 +              resultInArg0: true,
 +              asm:          x86.AVPMOVSQW,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VPMOVSQWMasked128_512Merging",
 +              argLen:       3,
 +              resultInArg0: true,
 +              asm:          x86.AVPMOVSQW,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VPMOVSWBMasked128_128Merging",
 +              argLen:       3,
 +              resultInArg0: true,
 +              asm:          x86.AVPMOVSWB,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VPMOVSWBMasked128_256Merging",
 +              argLen:       3,
 +              resultInArg0: true,
 +              asm:          x86.AVPMOVSWB,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VPMOVSWBMasked256Merging",
 +              argLen:       3,
 +              resultInArg0: true,
 +              asm:          x86.AVPMOVSWB,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VPMOVSXBDMasked128Merging",
 +              argLen:       3,
 +              resultInArg0: true,
 +              asm:          x86.AVPMOVSXBD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VPMOVSXBDMasked256Merging",
 +              argLen:       3,
 +              resultInArg0: true,
 +              asm:          x86.AVPMOVSXBD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VPMOVSXBDMasked512Merging",
 +              argLen:       3,
 +              resultInArg0: true,
 +              asm:          x86.AVPMOVSXBD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VPMOVSXBQMasked128Merging",
 +              argLen:       3,
 +              resultInArg0: true,
 +              asm:          x86.AVPMOVSXBQ,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VPMOVSXBQMasked256Merging",
 +              argLen:       3,
 +              resultInArg0: true,
 +              asm:          x86.AVPMOVSXBQ,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VPMOVSXBQMasked512Merging",
 +              argLen:       3,
 +              resultInArg0: true,
 +              asm:          x86.AVPMOVSXBQ,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VPMOVSXBWMasked128Merging",
 +              argLen:       3,
 +              resultInArg0: true,
 +              asm:          x86.AVPMOVSXBW,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VPMOVSXBWMasked256Merging",
 +              argLen:       3,
 +              resultInArg0: true,
 +              asm:          x86.AVPMOVSXBW,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VPMOVSXBWMasked512Merging",
 +              argLen:       3,
 +              resultInArg0: true,
 +              asm:          x86.AVPMOVSXBW,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VPMOVSXDQMasked128Merging",
 +              argLen:       3,
 +              resultInArg0: true,
 +              asm:          x86.AVPMOVSXDQ,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VPMOVSXDQMasked256Merging",
 +              argLen:       3,
 +              resultInArg0: true,
 +              asm:          x86.AVPMOVSXDQ,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VPMOVSXDQMasked512Merging",
 +              argLen:       3,
 +              resultInArg0: true,
 +              asm:          x86.AVPMOVSXDQ,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VPMOVSXWDMasked128Merging",
 +              argLen:       3,
 +              resultInArg0: true,
 +              asm:          x86.AVPMOVSXWD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VPMOVSXWDMasked256Merging",
 +              argLen:       3,
 +              resultInArg0: true,
 +              asm:          x86.AVPMOVSXWD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VPMOVSXWDMasked512Merging",
 +              argLen:       3,
 +              resultInArg0: true,
 +              asm:          x86.AVPMOVSXWD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VPMOVSXWQMasked128Merging",
 +              argLen:       3,
 +              resultInArg0: true,
 +              asm:          x86.AVPMOVSXWQ,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VPMOVSXWQMasked256Merging",
 +              argLen:       3,
 +              resultInArg0: true,
 +              asm:          x86.AVPMOVSXWQ,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VPMOVSXWQMasked512Merging",
 +              argLen:       3,
 +              resultInArg0: true,
 +              asm:          x86.AVPMOVSXWQ,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VPMOVUSDBMasked128_128Merging",
 +              argLen:       3,
 +              resultInArg0: true,
 +              asm:          x86.AVPMOVUSDB,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VPMOVUSDBMasked128_256Merging",
 +              argLen:       3,
 +              resultInArg0: true,
 +              asm:          x86.AVPMOVUSDB,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VPMOVUSDBMasked128_512Merging",
 +              argLen:       3,
 +              resultInArg0: true,
 +              asm:          x86.AVPMOVUSDB,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VPMOVUSDWMasked128_128Merging",
 +              argLen:       3,
 +              resultInArg0: true,
 +              asm:          x86.AVPMOVUSDW,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VPMOVUSDWMasked128_256Merging",
 +              argLen:       3,
 +              resultInArg0: true,
 +              asm:          x86.AVPMOVUSDW,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VPMOVUSDWMasked256Merging",
 +              argLen:       3,
 +              resultInArg0: true,
 +              asm:          x86.AVPMOVUSDW,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VPMOVUSQBMasked128_128Merging",
 +              argLen:       3,
 +              resultInArg0: true,
 +              asm:          x86.AVPMOVUSQB,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VPMOVUSQBMasked128_256Merging",
 +              argLen:       3,
 +              resultInArg0: true,
 +              asm:          x86.AVPMOVUSQB,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VPMOVUSQBMasked128_512Merging",
 +              argLen:       3,
 +              resultInArg0: true,
 +              asm:          x86.AVPMOVUSQB,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VPMOVUSQDMasked128_128Merging",
 +              argLen:       3,
 +              resultInArg0: true,
 +              asm:          x86.AVPMOVUSQD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VPMOVUSQDMasked128_256Merging",
 +              argLen:       3,
 +              resultInArg0: true,
 +              asm:          x86.AVPMOVUSQD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VPMOVUSQDMasked256Merging",
 +              argLen:       3,
 +              resultInArg0: true,
 +              asm:          x86.AVPMOVUSQD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VPMOVUSQWMasked128_128Merging",
 +              argLen:       3,
 +              resultInArg0: true,
 +              asm:          x86.AVPMOVUSQW,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VPMOVUSQWMasked128_256Merging",
 +              argLen:       3,
 +              resultInArg0: true,
 +              asm:          x86.AVPMOVUSQW,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VPMOVUSQWMasked128_512Merging",
 +              argLen:       3,
 +              resultInArg0: true,
 +              asm:          x86.AVPMOVUSQW,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VPMOVUSWBMasked128_128Merging",
 +              argLen:       3,
 +              resultInArg0: true,
 +              asm:          x86.AVPMOVUSWB,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VPMOVUSWBMasked128_256Merging",
 +              argLen:       3,
 +              resultInArg0: true,
 +              asm:          x86.AVPMOVUSWB,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VPMOVUSWBMasked256Merging",
 +              argLen:       3,
 +              resultInArg0: true,
 +              asm:          x86.AVPMOVUSWB,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VPMOVWBMasked128_128Merging",
 +              argLen:       3,
 +              resultInArg0: true,
 +              asm:          x86.AVPMOVWB,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VPMOVWBMasked128_256Merging",
 +              argLen:       3,
 +              resultInArg0: true,
 +              asm:          x86.AVPMOVWB,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VPMOVWBMasked256Merging",
 +              argLen:       3,
 +              resultInArg0: true,
 +              asm:          x86.AVPMOVWB,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VPMOVZXBDMasked128Merging",
 +              argLen:       3,
 +              resultInArg0: true,
 +              asm:          x86.AVPMOVZXBD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VPMOVZXBDMasked256Merging",
 +              argLen:       3,
 +              resultInArg0: true,
 +              asm:          x86.AVPMOVZXBD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VPMOVZXBDMasked512Merging",
 +              argLen:       3,
 +              resultInArg0: true,
 +              asm:          x86.AVPMOVZXBD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VPMOVZXBQMasked128Merging",
 +              argLen:       3,
 +              resultInArg0: true,
 +              asm:          x86.AVPMOVZXBQ,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VPMOVZXBQMasked256Merging",
 +              argLen:       3,
 +              resultInArg0: true,
 +              asm:          x86.AVPMOVZXBQ,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VPMOVZXBQMasked512Merging",
 +              argLen:       3,
 +              resultInArg0: true,
 +              asm:          x86.AVPMOVZXBQ,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VPMOVZXBWMasked128Merging",
 +              argLen:       3,
 +              resultInArg0: true,
 +              asm:          x86.AVPMOVZXBW,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VPMOVZXBWMasked256Merging",
 +              argLen:       3,
 +              resultInArg0: true,
 +              asm:          x86.AVPMOVZXBW,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VPMOVZXBWMasked512Merging",
 +              argLen:       3,
 +              resultInArg0: true,
 +              asm:          x86.AVPMOVZXBW,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VPMOVZXDQMasked128Merging",
 +              argLen:       3,
 +              resultInArg0: true,
 +              asm:          x86.AVPMOVZXDQ,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VPMOVZXDQMasked256Merging",
 +              argLen:       3,
 +              resultInArg0: true,
 +              asm:          x86.AVPMOVZXDQ,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VPMOVZXDQMasked512Merging",
 +              argLen:       3,
 +              resultInArg0: true,
 +              asm:          x86.AVPMOVZXDQ,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VPMOVZXWDMasked128Merging",
 +              argLen:       3,
 +              resultInArg0: true,
 +              asm:          x86.AVPMOVZXWD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VPMOVZXWDMasked256Merging",
 +              argLen:       3,
 +              resultInArg0: true,
 +              asm:          x86.AVPMOVZXWD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VPMOVZXWDMasked512Merging",
 +              argLen:       3,
 +              resultInArg0: true,
 +              asm:          x86.AVPMOVZXWD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VPMOVZXWQMasked128Merging",
 +              argLen:       3,
 +              resultInArg0: true,
 +              asm:          x86.AVPMOVZXWQ,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VPMOVZXWQMasked256Merging",
 +              argLen:       3,
 +              resultInArg0: true,
 +              asm:          x86.AVPMOVZXWQ,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VPMOVZXWQMasked512Merging",
 +              argLen:       3,
 +              resultInArg0: true,
 +              asm:          x86.AVPMOVZXWQ,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VPMULHUWMasked128Merging",
 +              argLen:       4,
 +              resultInArg0: true,
 +              asm:          x86.AVPMULHUW,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {2, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VPMULHUWMasked256Merging",
 +              argLen:       4,
 +              resultInArg0: true,
 +              asm:          x86.AVPMULHUW,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {2, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VPMULHUWMasked512Merging",
 +              argLen:       4,
 +              resultInArg0: true,
 +              asm:          x86.AVPMULHUW,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {2, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VPMULHWMasked128Merging",
 +              argLen:       4,
 +              resultInArg0: true,
 +              asm:          x86.AVPMULHW,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {2, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VPMULHWMasked256Merging",
 +              argLen:       4,
 +              resultInArg0: true,
 +              asm:          x86.AVPMULHW,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {2, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VPMULHWMasked512Merging",
 +              argLen:       4,
 +              resultInArg0: true,
 +              asm:          x86.AVPMULHW,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {2, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VPMULLDMasked128Merging",
 +              argLen:       4,
 +              resultInArg0: true,
 +              asm:          x86.AVPMULLD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {2, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VPMULLDMasked256Merging",
 +              argLen:       4,
 +              resultInArg0: true,
 +              asm:          x86.AVPMULLD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {2, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VPMULLDMasked512Merging",
 +              argLen:       4,
 +              resultInArg0: true,
 +              asm:          x86.AVPMULLD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {2, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VPMULLQMasked128Merging",
 +              argLen:       4,
 +              resultInArg0: true,
 +              asm:          x86.AVPMULLQ,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {2, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VPMULLQMasked256Merging",
 +              argLen:       4,
 +              resultInArg0: true,
 +              asm:          x86.AVPMULLQ,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {2, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VPMULLQMasked512Merging",
 +              argLen:       4,
 +              resultInArg0: true,
 +              asm:          x86.AVPMULLQ,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {2, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VPMULLWMasked128Merging",
 +              argLen:       4,
 +              resultInArg0: true,
 +              asm:          x86.AVPMULLW,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {2, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VPMULLWMasked256Merging",
 +              argLen:       4,
 +              resultInArg0: true,
 +              asm:          x86.AVPMULLW,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {2, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VPMULLWMasked512Merging",
 +              argLen:       4,
 +              resultInArg0: true,
 +              asm:          x86.AVPMULLW,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {2, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VPOPCNTBMasked128Merging",
 +              argLen:       3,
 +              resultInArg0: true,
 +              asm:          x86.AVPOPCNTB,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VPOPCNTBMasked256Merging",
 +              argLen:       3,
 +              resultInArg0: true,
 +              asm:          x86.AVPOPCNTB,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VPOPCNTBMasked512Merging",
 +              argLen:       3,
 +              resultInArg0: true,
 +              asm:          x86.AVPOPCNTB,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VPOPCNTDMasked128Merging",
 +              argLen:       3,
 +              resultInArg0: true,
 +              asm:          x86.AVPOPCNTD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VPOPCNTDMasked256Merging",
 +              argLen:       3,
 +              resultInArg0: true,
 +              asm:          x86.AVPOPCNTD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VPOPCNTDMasked512Merging",
 +              argLen:       3,
 +              resultInArg0: true,
 +              asm:          x86.AVPOPCNTD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VPOPCNTQMasked128Merging",
 +              argLen:       3,
 +              resultInArg0: true,
 +              asm:          x86.AVPOPCNTQ,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VPOPCNTQMasked256Merging",
 +              argLen:       3,
 +              resultInArg0: true,
 +              asm:          x86.AVPOPCNTQ,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VPOPCNTQMasked512Merging",
 +              argLen:       3,
 +              resultInArg0: true,
 +              asm:          x86.AVPOPCNTQ,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VPOPCNTWMasked128Merging",
 +              argLen:       3,
 +              resultInArg0: true,
 +              asm:          x86.AVPOPCNTW,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VPOPCNTWMasked256Merging",
 +              argLen:       3,
 +              resultInArg0: true,
 +              asm:          x86.AVPOPCNTW,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VPOPCNTWMasked512Merging",
 +              argLen:       3,
 +              resultInArg0: true,
 +              asm:          x86.AVPOPCNTW,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VPORDMasked128Merging",
 +              argLen:       4,
 +              resultInArg0: true,
 +              asm:          x86.AVPORD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {2, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VPORDMasked256Merging",
 +              argLen:       4,
 +              resultInArg0: true,
 +              asm:          x86.AVPORD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {2, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VPORDMasked512Merging",
 +              argLen:       4,
 +              resultInArg0: true,
 +              asm:          x86.AVPORD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {2, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VPORQMasked128Merging",
 +              argLen:       4,
 +              resultInArg0: true,
 +              asm:          x86.AVPORQ,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {2, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VPORQMasked256Merging",
 +              argLen:       4,
 +              resultInArg0: true,
 +              asm:          x86.AVPORQ,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {2, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VPORQMasked512Merging",
 +              argLen:       4,
 +              resultInArg0: true,
 +              asm:          x86.AVPORQ,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {2, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VPROLVDMasked128Merging",
 +              argLen:       4,
 +              resultInArg0: true,
 +              asm:          x86.AVPROLVD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {2, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VPROLVDMasked256Merging",
 +              argLen:       4,
 +              resultInArg0: true,
 +              asm:          x86.AVPROLVD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {2, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VPROLVDMasked512Merging",
 +              argLen:       4,
 +              resultInArg0: true,
 +              asm:          x86.AVPROLVD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {2, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VPROLVQMasked128Merging",
 +              argLen:       4,
 +              resultInArg0: true,
 +              asm:          x86.AVPROLVQ,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {2, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VPROLVQMasked256Merging",
 +              argLen:       4,
 +              resultInArg0: true,
 +              asm:          x86.AVPROLVQ,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {2, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VPROLVQMasked512Merging",
 +              argLen:       4,
 +              resultInArg0: true,
 +              asm:          x86.AVPROLVQ,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {2, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VPRORVDMasked128Merging",
 +              argLen:       4,
 +              resultInArg0: true,
 +              asm:          x86.AVPRORVD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {2, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VPRORVDMasked256Merging",
 +              argLen:       4,
 +              resultInArg0: true,
 +              asm:          x86.AVPRORVD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {2, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VPRORVDMasked512Merging",
 +              argLen:       4,
 +              resultInArg0: true,
 +              asm:          x86.AVPRORVD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {2, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VPRORVQMasked128Merging",
 +              argLen:       4,
 +              resultInArg0: true,
 +              asm:          x86.AVPRORVQ,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {2, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VPRORVQMasked256Merging",
 +              argLen:       4,
 +              resultInArg0: true,
 +              asm:          x86.AVPRORVQ,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {2, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VPRORVQMasked512Merging",
 +              argLen:       4,
 +              resultInArg0: true,
 +              asm:          x86.AVPRORVQ,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {2, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VPSHUFBMasked128Merging",
 +              argLen:       4,
 +              resultInArg0: true,
 +              asm:          x86.AVPSHUFB,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {2, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VPSHUFBMasked256Merging",
 +              argLen:       4,
 +              resultInArg0: true,
 +              asm:          x86.AVPSHUFB,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {2, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VPSHUFBMasked512Merging",
 +              argLen:       4,
 +              resultInArg0: true,
 +              asm:          x86.AVPSHUFB,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {2, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VPSLLVDMasked128Merging",
 +              argLen:       4,
 +              resultInArg0: true,
 +              asm:          x86.AVPSLLVD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {2, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VPSLLVDMasked256Merging",
 +              argLen:       4,
 +              resultInArg0: true,
 +              asm:          x86.AVPSLLVD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {2, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VPSLLVDMasked512Merging",
 +              argLen:       4,
 +              resultInArg0: true,
 +              asm:          x86.AVPSLLVD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {2, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VPSLLVQMasked128Merging",
 +              argLen:       4,
 +              resultInArg0: true,
 +              asm:          x86.AVPSLLVQ,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {2, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VPSLLVQMasked256Merging",
 +              argLen:       4,
 +              resultInArg0: true,
 +              asm:          x86.AVPSLLVQ,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {2, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VPSLLVQMasked512Merging",
 +              argLen:       4,
 +              resultInArg0: true,
 +              asm:          x86.AVPSLLVQ,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {2, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VPSLLVWMasked128Merging",
 +              argLen:       4,
 +              resultInArg0: true,
 +              asm:          x86.AVPSLLVW,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {2, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VPSLLVWMasked256Merging",
 +              argLen:       4,
 +              resultInArg0: true,
 +              asm:          x86.AVPSLLVW,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {2, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VPSLLVWMasked512Merging",
 +              argLen:       4,
 +              resultInArg0: true,
 +              asm:          x86.AVPSLLVW,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {2, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VPSRAVDMasked128Merging",
 +              argLen:       4,
 +              resultInArg0: true,
 +              asm:          x86.AVPSRAVD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {2, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VPSRAVDMasked256Merging",
 +              argLen:       4,
 +              resultInArg0: true,
 +              asm:          x86.AVPSRAVD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {2, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VPSRAVDMasked512Merging",
 +              argLen:       4,
 +              resultInArg0: true,
 +              asm:          x86.AVPSRAVD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {2, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VPSRAVQMasked128Merging",
 +              argLen:       4,
 +              resultInArg0: true,
 +              asm:          x86.AVPSRAVQ,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {2, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VPSRAVQMasked256Merging",
 +              argLen:       4,
 +              resultInArg0: true,
 +              asm:          x86.AVPSRAVQ,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {2, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VPSRAVQMasked512Merging",
 +              argLen:       4,
 +              resultInArg0: true,
 +              asm:          x86.AVPSRAVQ,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {2, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VPSRAVWMasked128Merging",
 +              argLen:       4,
 +              resultInArg0: true,
 +              asm:          x86.AVPSRAVW,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {2, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VPSRAVWMasked256Merging",
 +              argLen:       4,
 +              resultInArg0: true,
 +              asm:          x86.AVPSRAVW,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {2, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VPSRAVWMasked512Merging",
 +              argLen:       4,
 +              resultInArg0: true,
 +              asm:          x86.AVPSRAVW,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {2, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VPSRLVDMasked128Merging",
 +              argLen:       4,
 +              resultInArg0: true,
 +              asm:          x86.AVPSRLVD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {2, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VPSRLVDMasked256Merging",
 +              argLen:       4,
 +              resultInArg0: true,
 +              asm:          x86.AVPSRLVD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {2, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VPSRLVDMasked512Merging",
 +              argLen:       4,
 +              resultInArg0: true,
 +              asm:          x86.AVPSRLVD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {2, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VPSRLVQMasked128Merging",
 +              argLen:       4,
 +              resultInArg0: true,
 +              asm:          x86.AVPSRLVQ,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {2, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VPSRLVQMasked256Merging",
 +              argLen:       4,
 +              resultInArg0: true,
 +              asm:          x86.AVPSRLVQ,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {2, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VPSRLVQMasked512Merging",
 +              argLen:       4,
 +              resultInArg0: true,
 +              asm:          x86.AVPSRLVQ,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {2, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VPSRLVWMasked128Merging",
 +              argLen:       4,
 +              resultInArg0: true,
 +              asm:          x86.AVPSRLVW,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {2, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VPSRLVWMasked256Merging",
 +              argLen:       4,
 +              resultInArg0: true,
 +              asm:          x86.AVPSRLVW,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {2, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VPSRLVWMasked512Merging",
 +              argLen:       4,
 +              resultInArg0: true,
 +              asm:          x86.AVPSRLVW,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {2, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VPSUBBMasked128Merging",
 +              argLen:       4,
 +              resultInArg0: true,
 +              asm:          x86.AVPSUBB,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {2, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VPSUBBMasked256Merging",
 +              argLen:       4,
 +              resultInArg0: true,
 +              asm:          x86.AVPSUBB,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {2, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VPSUBBMasked512Merging",
 +              argLen:       4,
 +              resultInArg0: true,
 +              asm:          x86.AVPSUBB,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {2, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VPSUBDMasked128Merging",
 +              argLen:       4,
 +              resultInArg0: true,
 +              asm:          x86.AVPSUBD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {2, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VPSUBDMasked256Merging",
 +              argLen:       4,
 +              resultInArg0: true,
 +              asm:          x86.AVPSUBD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {2, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VPSUBDMasked512Merging",
 +              argLen:       4,
 +              resultInArg0: true,
 +              asm:          x86.AVPSUBD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {2, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VPSUBQMasked128Merging",
 +              argLen:       4,
 +              resultInArg0: true,
 +              asm:          x86.AVPSUBQ,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {2, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VPSUBQMasked256Merging",
 +              argLen:       4,
 +              resultInArg0: true,
 +              asm:          x86.AVPSUBQ,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {2, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VPSUBQMasked512Merging",
 +              argLen:       4,
 +              resultInArg0: true,
 +              asm:          x86.AVPSUBQ,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {2, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VPSUBSBMasked128Merging",
 +              argLen:       4,
 +              resultInArg0: true,
 +              asm:          x86.AVPSUBSB,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {2, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VPSUBSBMasked256Merging",
 +              argLen:       4,
 +              resultInArg0: true,
 +              asm:          x86.AVPSUBSB,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {2, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VPSUBSBMasked512Merging",
 +              argLen:       4,
 +              resultInArg0: true,
 +              asm:          x86.AVPSUBSB,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {2, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VPSUBSWMasked128Merging",
 +              argLen:       4,
 +              resultInArg0: true,
 +              asm:          x86.AVPSUBSW,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {2, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VPSUBSWMasked256Merging",
 +              argLen:       4,
 +              resultInArg0: true,
 +              asm:          x86.AVPSUBSW,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {2, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VPSUBSWMasked512Merging",
 +              argLen:       4,
 +              resultInArg0: true,
 +              asm:          x86.AVPSUBSW,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {2, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VPSUBUSBMasked128Merging",
 +              argLen:       4,
 +              resultInArg0: true,
 +              asm:          x86.AVPSUBUSB,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {2, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VPSUBUSBMasked256Merging",
 +              argLen:       4,
 +              resultInArg0: true,
 +              asm:          x86.AVPSUBUSB,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {2, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VPSUBUSBMasked512Merging",
 +              argLen:       4,
 +              resultInArg0: true,
 +              asm:          x86.AVPSUBUSB,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {2, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VPSUBUSWMasked128Merging",
 +              argLen:       4,
 +              resultInArg0: true,
 +              asm:          x86.AVPSUBUSW,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {2, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VPSUBUSWMasked256Merging",
 +              argLen:       4,
 +              resultInArg0: true,
 +              asm:          x86.AVPSUBUSW,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {2, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VPSUBUSWMasked512Merging",
 +              argLen:       4,
 +              resultInArg0: true,
 +              asm:          x86.AVPSUBUSW,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {2, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VPSUBWMasked128Merging",
 +              argLen:       4,
 +              resultInArg0: true,
 +              asm:          x86.AVPSUBW,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {2, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VPSUBWMasked256Merging",
 +              argLen:       4,
 +              resultInArg0: true,
 +              asm:          x86.AVPSUBW,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {2, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VPSUBWMasked512Merging",
 +              argLen:       4,
 +              resultInArg0: true,
 +              asm:          x86.AVPSUBW,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {2, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VPXORDMasked128Merging",
 +              argLen:       4,
 +              resultInArg0: true,
 +              asm:          x86.AVPXORD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {2, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VPXORDMasked256Merging",
 +              argLen:       4,
 +              resultInArg0: true,
 +              asm:          x86.AVPXORD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {2, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VPXORDMasked512Merging",
 +              argLen:       4,
 +              resultInArg0: true,
 +              asm:          x86.AVPXORD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {2, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VPXORQMasked128Merging",
 +              argLen:       4,
 +              resultInArg0: true,
 +              asm:          x86.AVPXORQ,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {2, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VPXORQMasked256Merging",
 +              argLen:       4,
 +              resultInArg0: true,
 +              asm:          x86.AVPXORQ,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {2, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VPXORQMasked512Merging",
 +              argLen:       4,
 +              resultInArg0: true,
 +              asm:          x86.AVPXORQ,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {2, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VRCP14PDMasked128Merging",
 +              argLen:       3,
 +              resultInArg0: true,
 +              asm:          x86.AVRCP14PD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VRCP14PDMasked256Merging",
 +              argLen:       3,
 +              resultInArg0: true,
 +              asm:          x86.AVRCP14PD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VRCP14PDMasked512Merging",
 +              argLen:       3,
 +              resultInArg0: true,
 +              asm:          x86.AVRCP14PD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VRCP14PSMasked128Merging",
 +              argLen:       3,
 +              resultInArg0: true,
 +              asm:          x86.AVRCP14PS,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VRCP14PSMasked256Merging",
 +              argLen:       3,
 +              resultInArg0: true,
 +              asm:          x86.AVRCP14PS,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VRCP14PSMasked512Merging",
 +              argLen:       3,
 +              resultInArg0: true,
 +              asm:          x86.AVRCP14PS,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VRSQRT14PDMasked128Merging",
 +              argLen:       3,
 +              resultInArg0: true,
 +              asm:          x86.AVRSQRT14PD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VRSQRT14PDMasked256Merging",
 +              argLen:       3,
 +              resultInArg0: true,
 +              asm:          x86.AVRSQRT14PD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VRSQRT14PDMasked512Merging",
 +              argLen:       3,
 +              resultInArg0: true,
 +              asm:          x86.AVRSQRT14PD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VRSQRT14PSMasked128Merging",
 +              argLen:       3,
 +              resultInArg0: true,
 +              asm:          x86.AVRSQRT14PS,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VRSQRT14PSMasked256Merging",
 +              argLen:       3,
 +              resultInArg0: true,
 +              asm:          x86.AVRSQRT14PS,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VRSQRT14PSMasked512Merging",
 +              argLen:       3,
 +              resultInArg0: true,
 +              asm:          x86.AVRSQRT14PS,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VSCALEFPDMasked128Merging",
 +              argLen:       4,
 +              resultInArg0: true,
 +              asm:          x86.AVSCALEFPD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {2, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VSCALEFPDMasked256Merging",
 +              argLen:       4,
 +              resultInArg0: true,
 +              asm:          x86.AVSCALEFPD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {2, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VSCALEFPDMasked512Merging",
 +              argLen:       4,
 +              resultInArg0: true,
 +              asm:          x86.AVSCALEFPD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {2, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VSCALEFPSMasked128Merging",
 +              argLen:       4,
 +              resultInArg0: true,
 +              asm:          x86.AVSCALEFPS,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {2, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VSCALEFPSMasked256Merging",
 +              argLen:       4,
 +              resultInArg0: true,
 +              asm:          x86.AVSCALEFPS,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {2, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VSCALEFPSMasked512Merging",
 +              argLen:       4,
 +              resultInArg0: true,
 +              asm:          x86.AVSCALEFPS,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {2, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VSQRTPDMasked128Merging",
 +              argLen:       3,
 +              resultInArg0: true,
 +              asm:          x86.AVSQRTPD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VSQRTPDMasked256Merging",
 +              argLen:       3,
 +              resultInArg0: true,
 +              asm:          x86.AVSQRTPD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VSQRTPDMasked512Merging",
 +              argLen:       3,
 +              resultInArg0: true,
 +              asm:          x86.AVSQRTPD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VSQRTPSMasked128Merging",
 +              argLen:       3,
 +              resultInArg0: true,
 +              asm:          x86.AVSQRTPS,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VSQRTPSMasked256Merging",
 +              argLen:       3,
 +              resultInArg0: true,
 +              asm:          x86.AVSQRTPS,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VSQRTPSMasked512Merging",
 +              argLen:       3,
 +              resultInArg0: true,
 +              asm:          x86.AVSQRTPS,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VSUBPDMasked128Merging",
 +              argLen:       4,
 +              resultInArg0: true,
 +              asm:          x86.AVSUBPD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {2, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VSUBPDMasked256Merging",
 +              argLen:       4,
 +              resultInArg0: true,
 +              asm:          x86.AVSUBPD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {2, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VSUBPDMasked512Merging",
 +              argLen:       4,
 +              resultInArg0: true,
 +              asm:          x86.AVSUBPD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {2, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VSUBPSMasked128Merging",
 +              argLen:       4,
 +              resultInArg0: true,
 +              asm:          x86.AVSUBPS,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {2, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VSUBPSMasked256Merging",
 +              argLen:       4,
 +              resultInArg0: true,
 +              asm:          x86.AVSUBPS,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {2, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VSUBPSMasked512Merging",
 +              argLen:       4,
 +              resultInArg0: true,
 +              asm:          x86.AVSUBPS,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {2, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VPALIGNRMasked128Merging",
 +              auxType:      auxUInt8,
 +              argLen:       4,
 +              resultInArg0: true,
 +              asm:          x86.AVPALIGNR,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {2, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VPALIGNRMasked256Merging",
 +              auxType:      auxUInt8,
 +              argLen:       4,
 +              resultInArg0: true,
 +              asm:          x86.AVPALIGNR,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {2, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VPALIGNRMasked512Merging",
 +              auxType:      auxUInt8,
 +              argLen:       4,
 +              resultInArg0: true,
 +              asm:          x86.AVPALIGNR,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {2, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VPROLDMasked128Merging",
 +              auxType:      auxUInt8,
 +              argLen:       3,
 +              resultInArg0: true,
 +              asm:          x86.AVPROLD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VPROLDMasked256Merging",
 +              auxType:      auxUInt8,
 +              argLen:       3,
 +              resultInArg0: true,
 +              asm:          x86.AVPROLD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VPROLDMasked512Merging",
 +              auxType:      auxUInt8,
 +              argLen:       3,
 +              resultInArg0: true,
 +              asm:          x86.AVPROLD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VPROLQMasked128Merging",
 +              auxType:      auxUInt8,
 +              argLen:       3,
 +              resultInArg0: true,
 +              asm:          x86.AVPROLQ,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VPROLQMasked256Merging",
 +              auxType:      auxUInt8,
 +              argLen:       3,
 +              resultInArg0: true,
 +              asm:          x86.AVPROLQ,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VPROLQMasked512Merging",
 +              auxType:      auxUInt8,
 +              argLen:       3,
 +              resultInArg0: true,
 +              asm:          x86.AVPROLQ,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VPRORDMasked128Merging",
 +              auxType:      auxUInt8,
 +              argLen:       3,
 +              resultInArg0: true,
 +              asm:          x86.AVPRORD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VPRORDMasked256Merging",
 +              auxType:      auxUInt8,
 +              argLen:       3,
 +              resultInArg0: true,
 +              asm:          x86.AVPRORD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VPRORDMasked512Merging",
 +              auxType:      auxUInt8,
 +              argLen:       3,
 +              resultInArg0: true,
 +              asm:          x86.AVPRORD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VPRORQMasked128Merging",
 +              auxType:      auxUInt8,
 +              argLen:       3,
 +              resultInArg0: true,
 +              asm:          x86.AVPRORQ,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VPRORQMasked256Merging",
 +              auxType:      auxUInt8,
 +              argLen:       3,
 +              resultInArg0: true,
 +              asm:          x86.AVPRORQ,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VPRORQMasked512Merging",
 +              auxType:      auxUInt8,
 +              argLen:       3,
 +              resultInArg0: true,
 +              asm:          x86.AVPRORQ,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VPSHLDDMasked128Merging",
 +              auxType:      auxUInt8,
 +              argLen:       4,
 +              resultInArg0: true,
 +              asm:          x86.AVPSHLDD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {2, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VPSHLDDMasked256Merging",
 +              auxType:      auxUInt8,
 +              argLen:       4,
 +              resultInArg0: true,
 +              asm:          x86.AVPSHLDD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {2, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VPSHLDDMasked512Merging",
 +              auxType:      auxUInt8,
 +              argLen:       4,
 +              resultInArg0: true,
 +              asm:          x86.AVPSHLDD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {2, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VPSHLDQMasked128Merging",
 +              auxType:      auxUInt8,
 +              argLen:       4,
 +              resultInArg0: true,
 +              asm:          x86.AVPSHLDQ,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {2, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VPSHLDQMasked256Merging",
 +              auxType:      auxUInt8,
 +              argLen:       4,
 +              resultInArg0: true,
 +              asm:          x86.AVPSHLDQ,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {2, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VPSHLDQMasked512Merging",
 +              auxType:      auxUInt8,
 +              argLen:       4,
 +              resultInArg0: true,
 +              asm:          x86.AVPSHLDQ,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {2, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VPSHLDWMasked128Merging",
 +              auxType:      auxUInt8,
 +              argLen:       4,
 +              resultInArg0: true,
 +              asm:          x86.AVPSHLDW,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {2, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VPSHLDWMasked256Merging",
 +              auxType:      auxUInt8,
 +              argLen:       4,
 +              resultInArg0: true,
 +              asm:          x86.AVPSHLDW,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {2, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VPSHLDWMasked512Merging",
 +              auxType:      auxUInt8,
 +              argLen:       4,
 +              resultInArg0: true,
 +              asm:          x86.AVPSHLDW,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {2, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VPSHRDDMasked128Merging",
 +              auxType:      auxUInt8,
 +              argLen:       4,
 +              resultInArg0: true,
 +              asm:          x86.AVPSHRDD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {2, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VPSHRDDMasked256Merging",
 +              auxType:      auxUInt8,
 +              argLen:       4,
 +              resultInArg0: true,
 +              asm:          x86.AVPSHRDD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {2, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VPSHRDDMasked512Merging",
 +              auxType:      auxUInt8,
 +              argLen:       4,
 +              resultInArg0: true,
 +              asm:          x86.AVPSHRDD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {2, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VPSHRDQMasked128Merging",
 +              auxType:      auxUInt8,
 +              argLen:       4,
 +              resultInArg0: true,
 +              asm:          x86.AVPSHRDQ,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {2, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VPSHRDQMasked256Merging",
 +              auxType:      auxUInt8,
 +              argLen:       4,
 +              resultInArg0: true,
 +              asm:          x86.AVPSHRDQ,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {2, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VPSHRDQMasked512Merging",
 +              auxType:      auxUInt8,
 +              argLen:       4,
 +              resultInArg0: true,
 +              asm:          x86.AVPSHRDQ,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {2, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VPSHRDWMasked128Merging",
 +              auxType:      auxUInt8,
 +              argLen:       4,
 +              resultInArg0: true,
 +              asm:          x86.AVPSHRDW,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {2, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VPSHRDWMasked256Merging",
 +              auxType:      auxUInt8,
 +              argLen:       4,
 +              resultInArg0: true,
 +              asm:          x86.AVPSHRDW,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {2, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VPSHRDWMasked512Merging",
 +              auxType:      auxUInt8,
 +              argLen:       4,
 +              resultInArg0: true,
 +              asm:          x86.AVPSHRDW,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {2, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VPSHUFDMasked128Merging",
 +              auxType:      auxUInt8,
 +              argLen:       3,
 +              resultInArg0: true,
 +              asm:          x86.AVPSHUFD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VPSHUFDMasked256Merging",
 +              auxType:      auxUInt8,
 +              argLen:       3,
 +              resultInArg0: true,
 +              asm:          x86.AVPSHUFD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VPSHUFDMasked512Merging",
 +              auxType:      auxUInt8,
 +              argLen:       3,
 +              resultInArg0: true,
 +              asm:          x86.AVPSHUFD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VPSHUFHWMasked128Merging",
 +              auxType:      auxUInt8,
 +              argLen:       3,
 +              resultInArg0: true,
 +              asm:          x86.AVPSHUFHW,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VPSHUFHWMasked256Merging",
 +              auxType:      auxUInt8,
 +              argLen:       3,
 +              resultInArg0: true,
 +              asm:          x86.AVPSHUFHW,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VPSHUFHWMasked512Merging",
 +              auxType:      auxUInt8,
 +              argLen:       3,
 +              resultInArg0: true,
 +              asm:          x86.AVPSHUFHW,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VPSLLDMasked128constMerging",
 +              auxType:      auxUInt8,
 +              argLen:       3,
 +              resultInArg0: true,
 +              asm:          x86.AVPSLLD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VPSLLDMasked256constMerging",
 +              auxType:      auxUInt8,
 +              argLen:       3,
 +              resultInArg0: true,
 +              asm:          x86.AVPSLLD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VPSLLDMasked512constMerging",
 +              auxType:      auxUInt8,
 +              argLen:       3,
 +              resultInArg0: true,
 +              asm:          x86.AVPSLLD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VPSLLQMasked128constMerging",
 +              auxType:      auxUInt8,
 +              argLen:       3,
 +              resultInArg0: true,
 +              asm:          x86.AVPSLLQ,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VPSLLQMasked256constMerging",
 +              auxType:      auxUInt8,
 +              argLen:       3,
 +              resultInArg0: true,
 +              asm:          x86.AVPSLLQ,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VPSLLQMasked512constMerging",
 +              auxType:      auxUInt8,
 +              argLen:       3,
 +              resultInArg0: true,
 +              asm:          x86.AVPSLLQ,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VPSLLWMasked128constMerging",
 +              auxType:      auxUInt8,
 +              argLen:       3,
 +              resultInArg0: true,
 +              asm:          x86.AVPSLLW,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VPSLLWMasked256constMerging",
 +              auxType:      auxUInt8,
 +              argLen:       3,
 +              resultInArg0: true,
 +              asm:          x86.AVPSLLW,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VPSLLWMasked512constMerging",
 +              auxType:      auxUInt8,
 +              argLen:       3,
 +              resultInArg0: true,
 +              asm:          x86.AVPSLLW,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VPSRADMasked128constMerging",
 +              auxType:      auxUInt8,
 +              argLen:       3,
 +              resultInArg0: true,
 +              asm:          x86.AVPSRAD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VPSRADMasked256constMerging",
 +              auxType:      auxUInt8,
 +              argLen:       3,
 +              resultInArg0: true,
 +              asm:          x86.AVPSRAD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VPSRADMasked512constMerging",
 +              auxType:      auxUInt8,
 +              argLen:       3,
 +              resultInArg0: true,
 +              asm:          x86.AVPSRAD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VPSRAQMasked128constMerging",
 +              auxType:      auxUInt8,
 +              argLen:       3,
 +              resultInArg0: true,
 +              asm:          x86.AVPSRAQ,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VPSRAQMasked256constMerging",
 +              auxType:      auxUInt8,
 +              argLen:       3,
 +              resultInArg0: true,
 +              asm:          x86.AVPSRAQ,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VPSRAQMasked512constMerging",
 +              auxType:      auxUInt8,
 +              argLen:       3,
 +              resultInArg0: true,
 +              asm:          x86.AVPSRAQ,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VPSRAWMasked128constMerging",
 +              auxType:      auxUInt8,
 +              argLen:       3,
 +              resultInArg0: true,
 +              asm:          x86.AVPSRAW,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VPSRAWMasked256constMerging",
 +              auxType:      auxUInt8,
 +              argLen:       3,
 +              resultInArg0: true,
 +              asm:          x86.AVPSRAW,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VPSRAWMasked512constMerging",
 +              auxType:      auxUInt8,
 +              argLen:       3,
 +              resultInArg0: true,
 +              asm:          x86.AVPSRAW,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VPSRLDMasked128constMerging",
 +              auxType:      auxUInt8,
 +              argLen:       3,
 +              resultInArg0: true,
 +              asm:          x86.AVPSRLD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VPSRLDMasked256constMerging",
 +              auxType:      auxUInt8,
 +              argLen:       3,
 +              resultInArg0: true,
 +              asm:          x86.AVPSRLD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VPSRLDMasked512constMerging",
 +              auxType:      auxUInt8,
 +              argLen:       3,
 +              resultInArg0: true,
 +              asm:          x86.AVPSRLD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VPSRLQMasked128constMerging",
 +              auxType:      auxUInt8,
 +              argLen:       3,
 +              resultInArg0: true,
 +              asm:          x86.AVPSRLQ,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VPSRLQMasked256constMerging",
 +              auxType:      auxUInt8,
 +              argLen:       3,
 +              resultInArg0: true,
 +              asm:          x86.AVPSRLQ,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VPSRLQMasked512constMerging",
 +              auxType:      auxUInt8,
 +              argLen:       3,
 +              resultInArg0: true,
 +              asm:          x86.AVPSRLQ,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VPSRLWMasked128constMerging",
 +              auxType:      auxUInt8,
 +              argLen:       3,
 +              resultInArg0: true,
 +              asm:          x86.AVPSRLW,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VPSRLWMasked256constMerging",
 +              auxType:      auxUInt8,
 +              argLen:       3,
 +              resultInArg0: true,
 +              asm:          x86.AVPSRLW,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VPSRLWMasked512constMerging",
 +              auxType:      auxUInt8,
 +              argLen:       3,
 +              resultInArg0: true,
 +              asm:          x86.AVPSRLW,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VREDUCEPDMasked128Merging",
 +              auxType:      auxUInt8,
 +              argLen:       3,
 +              resultInArg0: true,
 +              asm:          x86.AVREDUCEPD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VREDUCEPDMasked256Merging",
 +              auxType:      auxUInt8,
 +              argLen:       3,
 +              resultInArg0: true,
 +              asm:          x86.AVREDUCEPD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VREDUCEPDMasked512Merging",
 +              auxType:      auxUInt8,
 +              argLen:       3,
 +              resultInArg0: true,
 +              asm:          x86.AVREDUCEPD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VREDUCEPSMasked128Merging",
 +              auxType:      auxUInt8,
 +              argLen:       3,
 +              resultInArg0: true,
 +              asm:          x86.AVREDUCEPS,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VREDUCEPSMasked256Merging",
 +              auxType:      auxUInt8,
 +              argLen:       3,
 +              resultInArg0: true,
 +              asm:          x86.AVREDUCEPS,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VREDUCEPSMasked512Merging",
 +              auxType:      auxUInt8,
 +              argLen:       3,
 +              resultInArg0: true,
 +              asm:          x86.AVREDUCEPS,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VRNDSCALEPDMasked128Merging",
 +              auxType:      auxUInt8,
 +              argLen:       3,
 +              resultInArg0: true,
 +              asm:          x86.AVRNDSCALEPD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VRNDSCALEPDMasked256Merging",
 +              auxType:      auxUInt8,
 +              argLen:       3,
 +              resultInArg0: true,
 +              asm:          x86.AVRNDSCALEPD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VRNDSCALEPDMasked512Merging",
 +              auxType:      auxUInt8,
 +              argLen:       3,
 +              resultInArg0: true,
 +              asm:          x86.AVRNDSCALEPD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VRNDSCALEPSMasked128Merging",
 +              auxType:      auxUInt8,
 +              argLen:       3,
 +              resultInArg0: true,
 +              asm:          x86.AVRNDSCALEPS,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VRNDSCALEPSMasked256Merging",
 +              auxType:      auxUInt8,
 +              argLen:       3,
 +              resultInArg0: true,
 +              asm:          x86.AVRNDSCALEPS,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "VRNDSCALEPSMasked512Merging",
 +              auxType:      auxUInt8,
 +              argLen:       3,
 +              resultInArg0: true,
 +              asm:          x86.AVRNDSCALEPS,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
 +                              {0, 281472829161472},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                              {1, 281474976645120},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
 +                      },
 +              },
 +      },
 +
 +      {
 +              name:        "ADD",
 +              argLen:      2,
 +              commutative: true,
 +              asm:         arm.AADD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
 +                              {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:    "ADDconst",
 +              auxType: auxInt32,
 +              argLen:  1,
 +              asm:     arm.AADD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 30719}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:   "SUB",
 +              argLen: 2,
 +              asm:    arm.ASUB,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
 +                              {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:    "SUBconst",
 +              auxType: auxInt32,
 +              argLen:  1,
 +              asm:     arm.ASUB,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:   "RSB",
 +              argLen: 2,
 +              asm:    arm.ARSB,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
 +                              {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:    "RSBconst",
 +              auxType: auxInt32,
 +              argLen:  1,
 +              asm:     arm.ARSB,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:        "MUL",
 +              argLen:      2,
 +              commutative: true,
 +              asm:         arm.AMUL,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
 +                              {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:        "HMUL",
 +              argLen:      2,
 +              commutative: true,
 +              asm:         arm.AMULL,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
 +                              {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:        "HMULU",
 +              argLen:      2,
 +              commutative: true,
 +              asm:         arm.AMULLU,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
 +                              {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:         "CALLudiv",
 +              argLen:       2,
 +              clobberFlags: true,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 2}, // R1
 +                              {1, 1}, // R0
 +                      },
 +                      clobbers: 20492, // R2 R3 R12 R14
 +                      outputs: []outputInfo{
 +                              {0, 1}, // R0
 +                              {1, 2}, // R1
 +                      },
 +              },
 +      },
 +      {
 +              name:        "ADDS",
 +              argLen:      2,
 +              commutative: true,
 +              asm:         arm.AADD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
 +                              {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
 +                      },
 +                      outputs: []outputInfo{
 +                              {1, 0},
 +                              {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:    "ADDSconst",
 +              auxType: auxInt32,
 +              argLen:  1,
 +              asm:     arm.AADD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
 +                      },
 +                      outputs: []outputInfo{
 +                              {1, 0},
 +                              {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:        "ADC",
 +              argLen:      3,
 +              commutative: true,
 +              asm:         arm.AADC,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                              {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:    "ADCconst",
 +              auxType: auxInt32,
 +              argLen:  2,
 +              asm:     arm.AADC,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:        "ADCS",
 +              argLen:      3,
 +              commutative: true,
 +              asm:         arm.AADC,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                              {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                      },
 +                      outputs: []outputInfo{
 +                              {1, 0},
 +                              {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:   "SUBS",
 +              argLen: 2,
 +              asm:    arm.ASUB,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
 +                              {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
 +                      },
 +                      outputs: []outputInfo{
 +                              {1, 0},
 +                              {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:    "SUBSconst",
 +              auxType: auxInt32,
 +              argLen:  1,
 +              asm:     arm.ASUB,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
 +                      },
 +                      outputs: []outputInfo{
 +                              {1, 0},
 +                              {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:    "RSBSconst",
 +              auxType: auxInt32,
 +              argLen:  1,
 +              asm:     arm.ARSB,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
 +                      },
 +                      outputs: []outputInfo{
 +                              {1, 0},
 +                              {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:   "SBC",
 +              argLen: 3,
 +              asm:    arm.ASBC,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                              {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:    "SBCconst",
 +              auxType: auxInt32,
 +              argLen:  2,
 +              asm:     arm.ASBC,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:    "RSCconst",
 +              auxType: auxInt32,
 +              argLen:  2,
 +              asm:     arm.ARSC,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:        "MULLU",
 +              argLen:      2,
 +              commutative: true,
 +              asm:         arm.AMULLU,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
 +                              {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                              {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:   "MULA",
 +              argLen: 3,
 +              asm:    arm.AMULA,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                              {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                              {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:   "MULS",
 +              argLen: 3,
 +              asm:    arm.AMULS,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                              {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                              {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:        "ADDF",
 +              argLen:      2,
 +              commutative: true,
 +              asm:         arm.AADDF,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 +                              {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 +                      },
 +              },
 +      },
 +      {
 +              name:        "ADDD",
 +              argLen:      2,
 +              commutative: true,
 +              asm:         arm.AADDD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 +                              {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 +                      },
 +              },
 +      },
 +      {
 +              name:   "SUBF",
 +              argLen: 2,
 +              asm:    arm.ASUBF,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 +                              {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 +                      },
 +              },
 +      },
 +      {
 +              name:   "SUBD",
 +              argLen: 2,
 +              asm:    arm.ASUBD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 +                              {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 +                      },
 +              },
 +      },
 +      {
 +              name:        "MULF",
 +              argLen:      2,
 +              commutative: true,
 +              asm:         arm.AMULF,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 +                              {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 +                      },
 +              },
 +      },
 +      {
 +              name:        "MULD",
 +              argLen:      2,
 +              commutative: true,
 +              asm:         arm.AMULD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 +                              {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 +                      },
 +              },
 +      },
 +      {
 +              name:        "NMULF",
 +              argLen:      2,
 +              commutative: true,
 +              asm:         arm.ANMULF,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 +                              {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 +                      },
 +              },
 +      },
 +      {
 +              name:        "NMULD",
 +              argLen:      2,
 +              commutative: true,
 +              asm:         arm.ANMULD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 +                              {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 +                      },
 +              },
 +      },
 +      {
 +              name:   "DIVF",
 +              argLen: 2,
 +              asm:    arm.ADIVF,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 +                              {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 +                      },
 +              },
 +      },
 +      {
 +              name:   "DIVD",
 +              argLen: 2,
 +              asm:    arm.ADIVD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 +                              {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 +                      },
 +              },
 +      },
 +      {
 +              name:         "MULAF",
 +              argLen:       3,
 +              resultInArg0: true,
 +              asm:          arm.AMULAF,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 +                              {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 +                              {2, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 +                      },
 +              },
 +      },
 +      {
 +              name:         "MULAD",
 +              argLen:       3,
 +              resultInArg0: true,
 +              asm:          arm.AMULAD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 +                              {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 +                              {2, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 +                      },
 +              },
 +      },
 +      {
 +              name:         "MULSF",
 +              argLen:       3,
 +              resultInArg0: true,
 +              asm:          arm.AMULSF,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 +                              {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 +                              {2, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 +                      },
 +              },
 +      },
 +      {
 +              name:         "MULSD",
 +              argLen:       3,
 +              resultInArg0: true,
 +              asm:          arm.AMULSD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 +                              {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 +                              {2, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 +                      },
 +              },
 +      },
 +      {
 +              name:         "FMULAD",
 +              argLen:       3,
 +              resultInArg0: true,
 +              asm:          arm.AFMULAD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 +                              {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 +                              {2, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 +                      },
 +              },
 +      },
 +      {
 +              name:        "AND",
 +              argLen:      2,
 +              commutative: true,
 +              asm:         arm.AAND,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
 +                              {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:    "ANDconst",
 +              auxType: auxInt32,
 +              argLen:  1,
 +              asm:     arm.AAND,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:        "OR",
 +              argLen:      2,
 +              commutative: true,
 +              asm:         arm.AORR,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
 +                              {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:    "ORconst",
 +              auxType: auxInt32,
 +              argLen:  1,
 +              asm:     arm.AORR,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:        "XOR",
 +              argLen:      2,
 +              commutative: true,
 +              asm:         arm.AEOR,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
 +                              {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:    "XORconst",
 +              auxType: auxInt32,
 +              argLen:  1,
 +              asm:     arm.AEOR,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:   "BIC",
 +              argLen: 2,
 +              asm:    arm.ABIC,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
 +                              {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:    "BICconst",
 +              auxType: auxInt32,
 +              argLen:  1,
 +              asm:     arm.ABIC,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:    "BFX",
 +              auxType: auxInt32,
 +              argLen:  1,
 +              asm:     arm.ABFX,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:    "BFXU",
 +              auxType: auxInt32,
 +              argLen:  1,
 +              asm:     arm.ABFXU,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:   "MVN",
 +              argLen: 1,
 +              asm:    arm.AMVN,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:   "NEGF",
 +              argLen: 1,
 +              asm:    arm.ANEGF,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 +                      },
 +              },
 +      },
 +      {
 +              name:   "NEGD",
 +              argLen: 1,
 +              asm:    arm.ANEGD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 +                      },
 +              },
 +      },
 +      {
 +              name:   "SQRTD",
 +              argLen: 1,
 +              asm:    arm.ASQRTD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 +                      },
 +              },
 +      },
 +      {
 +              name:   "SQRTF",
 +              argLen: 1,
 +              asm:    arm.ASQRTF,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 +                      },
 +              },
 +      },
 +      {
 +              name:   "ABSD",
 +              argLen: 1,
 +              asm:    arm.AABSD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 +                      },
 +              },
 +      },
 +      {
 +              name:   "CLZ",
 +              argLen: 1,
 +              asm:    arm.ACLZ,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:   "REV",
 +              argLen: 1,
 +              asm:    arm.AREV,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:   "REV16",
 +              argLen: 1,
 +              asm:    arm.AREV16,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:   "RBIT",
 +              argLen: 1,
 +              asm:    arm.ARBIT,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:   "SLL",
 +              argLen: 2,
 +              asm:    arm.ASLL,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
 +                              {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:    "SLLconst",
 +              auxType: auxInt32,
 +              argLen:  1,
 +              asm:     arm.ASLL,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:   "SRL",
 +              argLen: 2,
 +              asm:    arm.ASRL,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
 +                              {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:    "SRLconst",
 +              auxType: auxInt32,
 +              argLen:  1,
 +              asm:     arm.ASRL,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:   "SRA",
 +              argLen: 2,
 +              asm:    arm.ASRA,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
 +                              {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:    "SRAconst",
 +              auxType: auxInt32,
 +              argLen:  1,
 +              asm:     arm.ASRA,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:   "SRR",
 +              argLen: 2,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
 +                              {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:    "SRRconst",
 +              auxType: auxInt32,
 +              argLen:  1,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:    "ADDshiftLL",
 +              auxType: auxInt32,
 +              argLen:  2,
 +              asm:     arm.AADD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
 +                              {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:    "ADDshiftRL",
 +              auxType: auxInt32,
 +              argLen:  2,
 +              asm:     arm.AADD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
 +                              {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:    "ADDshiftRA",
 +              auxType: auxInt32,
 +              argLen:  2,
 +              asm:     arm.AADD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
 +                              {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:    "SUBshiftLL",
 +              auxType: auxInt32,
 +              argLen:  2,
 +              asm:     arm.ASUB,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
 +                              {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:    "SUBshiftRL",
 +              auxType: auxInt32,
 +              argLen:  2,
 +              asm:     arm.ASUB,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
 +                              {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:    "SUBshiftRA",
 +              auxType: auxInt32,
 +              argLen:  2,
 +              asm:     arm.ASUB,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
 +                              {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:    "RSBshiftLL",
 +              auxType: auxInt32,
 +              argLen:  2,
 +              asm:     arm.ARSB,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
 +                              {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:    "RSBshiftRL",
 +              auxType: auxInt32,
 +              argLen:  2,
 +              asm:     arm.ARSB,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
 +                              {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:    "RSBshiftRA",
 +              auxType: auxInt32,
 +              argLen:  2,
 +              asm:     arm.ARSB,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
 +                              {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:    "ANDshiftLL",
 +              auxType: auxInt32,
 +              argLen:  2,
 +              asm:     arm.AAND,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
 +                              {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:    "ANDshiftRL",
 +              auxType: auxInt32,
 +              argLen:  2,
 +              asm:     arm.AAND,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
 +                              {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:    "ANDshiftRA",
 +              auxType: auxInt32,
 +              argLen:  2,
 +              asm:     arm.AAND,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
 +                              {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:    "ORshiftLL",
 +              auxType: auxInt32,
 +              argLen:  2,
 +              asm:     arm.AORR,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
 +                              {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:    "ORshiftRL",
 +              auxType: auxInt32,
 +              argLen:  2,
 +              asm:     arm.AORR,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
 +                              {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:    "ORshiftRA",
 +              auxType: auxInt32,
 +              argLen:  2,
 +              asm:     arm.AORR,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
 +                              {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:    "XORshiftLL",
 +              auxType: auxInt32,
 +              argLen:  2,
 +              asm:     arm.AEOR,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
 +                              {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:    "XORshiftRL",
 +              auxType: auxInt32,
 +              argLen:  2,
 +              asm:     arm.AEOR,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
 +                              {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:    "XORshiftRA",
 +              auxType: auxInt32,
 +              argLen:  2,
 +              asm:     arm.AEOR,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
 +                              {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:    "XORshiftRR",
 +              auxType: auxInt32,
 +              argLen:  2,
 +              asm:     arm.AEOR,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
 +                              {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:    "BICshiftLL",
 +              auxType: auxInt32,
 +              argLen:  2,
 +              asm:     arm.ABIC,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
 +                              {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:    "BICshiftRL",
 +              auxType: auxInt32,
 +              argLen:  2,
 +              asm:     arm.ABIC,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
 +                              {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:    "BICshiftRA",
 +              auxType: auxInt32,
 +              argLen:  2,
 +              asm:     arm.ABIC,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
 +                              {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:    "MVNshiftLL",
 +              auxType: auxInt32,
 +              argLen:  1,
 +              asm:     arm.AMVN,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:    "MVNshiftRL",
 +              auxType: auxInt32,
 +              argLen:  1,
 +              asm:     arm.AMVN,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:    "MVNshiftRA",
 +              auxType: auxInt32,
 +              argLen:  1,
 +              asm:     arm.AMVN,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:    "ADCshiftLL",
 +              auxType: auxInt32,
 +              argLen:  3,
 +              asm:     arm.AADC,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                              {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:    "ADCshiftRL",
 +              auxType: auxInt32,
 +              argLen:  3,
 +              asm:     arm.AADC,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                              {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:    "ADCshiftRA",
 +              auxType: auxInt32,
 +              argLen:  3,
 +              asm:     arm.AADC,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                              {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:    "SBCshiftLL",
 +              auxType: auxInt32,
 +              argLen:  3,
 +              asm:     arm.ASBC,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                              {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:    "SBCshiftRL",
 +              auxType: auxInt32,
 +              argLen:  3,
 +              asm:     arm.ASBC,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                              {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:    "SBCshiftRA",
 +              auxType: auxInt32,
 +              argLen:  3,
 +              asm:     arm.ASBC,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                              {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:    "RSCshiftLL",
 +              auxType: auxInt32,
 +              argLen:  3,
 +              asm:     arm.ARSC,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                              {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:    "RSCshiftRL",
 +              auxType: auxInt32,
 +              argLen:  3,
 +              asm:     arm.ARSC,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                              {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:    "RSCshiftRA",
 +              auxType: auxInt32,
 +              argLen:  3,
 +              asm:     arm.ARSC,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                              {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:    "ADDSshiftLL",
 +              auxType: auxInt32,
 +              argLen:  2,
 +              asm:     arm.AADD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
 +                              {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
 +                      },
 +                      outputs: []outputInfo{
 +                              {1, 0},
 +                              {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:    "ADDSshiftRL",
 +              auxType: auxInt32,
 +              argLen:  2,
 +              asm:     arm.AADD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
 +                              {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
 +                      },
 +                      outputs: []outputInfo{
 +                              {1, 0},
 +                              {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:    "ADDSshiftRA",
 +              auxType: auxInt32,
 +              argLen:  2,
 +              asm:     arm.AADD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
 +                              {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
 +                      },
 +                      outputs: []outputInfo{
 +                              {1, 0},
 +                              {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:    "SUBSshiftLL",
 +              auxType: auxInt32,
 +              argLen:  2,
 +              asm:     arm.ASUB,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
 +                              {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
 +                      },
 +                      outputs: []outputInfo{
 +                              {1, 0},
 +                              {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:    "SUBSshiftRL",
 +              auxType: auxInt32,
 +              argLen:  2,
 +              asm:     arm.ASUB,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
 +                              {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
 +                      },
 +                      outputs: []outputInfo{
 +                              {1, 0},
 +                              {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:    "SUBSshiftRA",
 +              auxType: auxInt32,
 +              argLen:  2,
 +              asm:     arm.ASUB,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
 +                              {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
 +                      },
 +                      outputs: []outputInfo{
 +                              {1, 0},
 +                              {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:    "RSBSshiftLL",
 +              auxType: auxInt32,
 +              argLen:  2,
 +              asm:     arm.ARSB,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
 +                              {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
 +                      },
 +                      outputs: []outputInfo{
 +                              {1, 0},
 +                              {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:    "RSBSshiftRL",
 +              auxType: auxInt32,
 +              argLen:  2,
 +              asm:     arm.ARSB,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
 +                              {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
 +                      },
 +                      outputs: []outputInfo{
 +                              {1, 0},
 +                              {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:    "RSBSshiftRA",
 +              auxType: auxInt32,
 +              argLen:  2,
 +              asm:     arm.ARSB,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
 +                              {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
 +                      },
 +                      outputs: []outputInfo{
 +                              {1, 0},
 +                              {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:   "ADDshiftLLreg",
 +              argLen: 3,
 +              asm:    arm.AADD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                              {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                              {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:   "ADDshiftRLreg",
 +              argLen: 3,
 +              asm:    arm.AADD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                              {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                              {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:   "ADDshiftRAreg",
 +              argLen: 3,
 +              asm:    arm.AADD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                              {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                              {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:   "SUBshiftLLreg",
 +              argLen: 3,
 +              asm:    arm.ASUB,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                              {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                              {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:   "SUBshiftRLreg",
 +              argLen: 3,
 +              asm:    arm.ASUB,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                              {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                              {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:   "SUBshiftRAreg",
 +              argLen: 3,
 +              asm:    arm.ASUB,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                              {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                              {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:   "RSBshiftLLreg",
 +              argLen: 3,
 +              asm:    arm.ARSB,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                              {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                              {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:   "RSBshiftRLreg",
 +              argLen: 3,
 +              asm:    arm.ARSB,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                              {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                              {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:   "RSBshiftRAreg",
 +              argLen: 3,
 +              asm:    arm.ARSB,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                              {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                              {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:   "ANDshiftLLreg",
 +              argLen: 3,
 +              asm:    arm.AAND,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                              {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                              {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:   "ANDshiftRLreg",
 +              argLen: 3,
 +              asm:    arm.AAND,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                              {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                              {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:   "ANDshiftRAreg",
 +              argLen: 3,
 +              asm:    arm.AAND,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                              {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                              {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:   "ORshiftLLreg",
 +              argLen: 3,
 +              asm:    arm.AORR,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                              {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                              {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:   "ORshiftRLreg",
 +              argLen: 3,
 +              asm:    arm.AORR,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                              {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                              {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:   "ORshiftRAreg",
 +              argLen: 3,
 +              asm:    arm.AORR,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                              {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                              {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:   "XORshiftLLreg",
 +              argLen: 3,
 +              asm:    arm.AEOR,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                              {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                              {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:   "XORshiftRLreg",
 +              argLen: 3,
 +              asm:    arm.AEOR,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                              {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                              {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:   "XORshiftRAreg",
 +              argLen: 3,
 +              asm:    arm.AEOR,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                              {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                              {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:   "BICshiftLLreg",
 +              argLen: 3,
 +              asm:    arm.ABIC,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                              {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                              {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:   "BICshiftRLreg",
 +              argLen: 3,
 +              asm:    arm.ABIC,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                              {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                              {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:   "BICshiftRAreg",
 +              argLen: 3,
 +              asm:    arm.ABIC,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                              {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                              {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:   "MVNshiftLLreg",
 +              argLen: 2,
 +              asm:    arm.AMVN,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
 +                              {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:   "MVNshiftRLreg",
 +              argLen: 2,
 +              asm:    arm.AMVN,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
 +                              {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:   "MVNshiftRAreg",
 +              argLen: 2,
 +              asm:    arm.AMVN,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
 +                              {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:   "ADCshiftLLreg",
 +              argLen: 4,
 +              asm:    arm.AADC,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                              {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                              {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:   "ADCshiftRLreg",
 +              argLen: 4,
 +              asm:    arm.AADC,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                              {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                              {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:   "ADCshiftRAreg",
 +              argLen: 4,
 +              asm:    arm.AADC,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                              {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                              {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:   "SBCshiftLLreg",
 +              argLen: 4,
 +              asm:    arm.ASBC,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                              {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                              {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:   "SBCshiftRLreg",
 +              argLen: 4,
 +              asm:    arm.ASBC,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                              {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                              {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:   "SBCshiftRAreg",
 +              argLen: 4,
 +              asm:    arm.ASBC,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                              {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                              {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:   "RSCshiftLLreg",
 +              argLen: 4,
 +              asm:    arm.ARSC,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                              {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                              {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:   "RSCshiftRLreg",
 +              argLen: 4,
 +              asm:    arm.ARSC,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                              {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                              {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:   "RSCshiftRAreg",
 +              argLen: 4,
 +              asm:    arm.ARSC,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                              {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                              {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:   "ADDSshiftLLreg",
 +              argLen: 3,
 +              asm:    arm.AADD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                              {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                              {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                      },
 +                      outputs: []outputInfo{
 +                              {1, 0},
 +                              {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:   "ADDSshiftRLreg",
 +              argLen: 3,
 +              asm:    arm.AADD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                              {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                              {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                      },
 +                      outputs: []outputInfo{
 +                              {1, 0},
 +                              {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:   "ADDSshiftRAreg",
 +              argLen: 3,
 +              asm:    arm.AADD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                              {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                              {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                      },
 +                      outputs: []outputInfo{
 +                              {1, 0},
 +                              {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:   "SUBSshiftLLreg",
 +              argLen: 3,
 +              asm:    arm.ASUB,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                              {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                              {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                      },
 +                      outputs: []outputInfo{
 +                              {1, 0},
 +                              {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:   "SUBSshiftRLreg",
 +              argLen: 3,
 +              asm:    arm.ASUB,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                              {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                              {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                      },
 +                      outputs: []outputInfo{
 +                              {1, 0},
 +                              {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:   "SUBSshiftRAreg",
 +              argLen: 3,
 +              asm:    arm.ASUB,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                              {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                              {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                      },
 +                      outputs: []outputInfo{
 +                              {1, 0},
 +                              {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:   "RSBSshiftLLreg",
 +              argLen: 3,
 +              asm:    arm.ARSB,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                              {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                              {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                      },
 +                      outputs: []outputInfo{
 +                              {1, 0},
 +                              {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:   "RSBSshiftRLreg",
 +              argLen: 3,
 +              asm:    arm.ARSB,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                              {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                              {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                      },
 +                      outputs: []outputInfo{
 +                              {1, 0},
 +                              {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:   "RSBSshiftRAreg",
 +              argLen: 3,
 +              asm:    arm.ARSB,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                              {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                              {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                      },
 +                      outputs: []outputInfo{
 +                              {1, 0},
 +                              {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:   "CMP",
 +              argLen: 2,
 +              asm:    arm.ACMP,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
 +                              {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:    "CMPconst",
 +              auxType: auxInt32,
 +              argLen:  1,
 +              asm:     arm.ACMP,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:        "CMN",
 +              argLen:      2,
 +              commutative: true,
 +              asm:         arm.ACMN,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
 +                              {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:    "CMNconst",
 +              auxType: auxInt32,
 +              argLen:  1,
 +              asm:     arm.ACMN,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:        "TST",
 +              argLen:      2,
 +              commutative: true,
 +              asm:         arm.ATST,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
 +                              {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:    "TSTconst",
 +              auxType: auxInt32,
 +              argLen:  1,
 +              asm:     arm.ATST,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:        "TEQ",
 +              argLen:      2,
 +              commutative: true,
 +              asm:         arm.ATEQ,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
 +                              {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:    "TEQconst",
 +              auxType: auxInt32,
 +              argLen:  1,
 +              asm:     arm.ATEQ,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:   "CMPF",
 +              argLen: 2,
 +              asm:    arm.ACMPF,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 +                              {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 +                      },
 +              },
 +      },
 +      {
 +              name:   "CMPD",
 +              argLen: 2,
 +              asm:    arm.ACMPD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 +                              {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 +                      },
 +              },
 +      },
 +      {
 +              name:    "CMPshiftLL",
 +              auxType: auxInt32,
 +              argLen:  2,
 +              asm:     arm.ACMP,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
 +                              {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:    "CMPshiftRL",
 +              auxType: auxInt32,
 +              argLen:  2,
 +              asm:     arm.ACMP,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
 +                              {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:    "CMPshiftRA",
 +              auxType: auxInt32,
 +              argLen:  2,
 +              asm:     arm.ACMP,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
 +                              {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:    "CMNshiftLL",
 +              auxType: auxInt32,
 +              argLen:  2,
 +              asm:     arm.ACMN,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
 +                              {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:    "CMNshiftRL",
 +              auxType: auxInt32,
 +              argLen:  2,
 +              asm:     arm.ACMN,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
 +                              {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:    "CMNshiftRA",
 +              auxType: auxInt32,
 +              argLen:  2,
 +              asm:     arm.ACMN,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
 +                              {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:    "TSTshiftLL",
 +              auxType: auxInt32,
 +              argLen:  2,
 +              asm:     arm.ATST,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
 +                              {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:    "TSTshiftRL",
 +              auxType: auxInt32,
 +              argLen:  2,
 +              asm:     arm.ATST,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
 +                              {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:    "TSTshiftRA",
 +              auxType: auxInt32,
 +              argLen:  2,
 +              asm:     arm.ATST,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
 +                              {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:    "TEQshiftLL",
 +              auxType: auxInt32,
 +              argLen:  2,
 +              asm:     arm.ATEQ,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
 +                              {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:    "TEQshiftRL",
 +              auxType: auxInt32,
 +              argLen:  2,
 +              asm:     arm.ATEQ,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
 +                              {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:    "TEQshiftRA",
 +              auxType: auxInt32,
 +              argLen:  2,
 +              asm:     arm.ATEQ,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
 +                              {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:   "CMPshiftLLreg",
 +              argLen: 3,
 +              asm:    arm.ACMP,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                              {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                              {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:   "CMPshiftRLreg",
 +              argLen: 3,
 +              asm:    arm.ACMP,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                              {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                              {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:   "CMPshiftRAreg",
 +              argLen: 3,
 +              asm:    arm.ACMP,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                              {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                              {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:   "CMNshiftLLreg",
 +              argLen: 3,
 +              asm:    arm.ACMN,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                              {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                              {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:   "CMNshiftRLreg",
 +              argLen: 3,
 +              asm:    arm.ACMN,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                              {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                              {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:   "CMNshiftRAreg",
 +              argLen: 3,
 +              asm:    arm.ACMN,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                              {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                              {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:   "TSTshiftLLreg",
 +              argLen: 3,
 +              asm:    arm.ATST,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                              {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                              {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:   "TSTshiftRLreg",
 +              argLen: 3,
 +              asm:    arm.ATST,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                              {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                              {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:   "TSTshiftRAreg",
 +              argLen: 3,
 +              asm:    arm.ATST,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                              {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                              {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:   "TEQshiftLLreg",
 +              argLen: 3,
 +              asm:    arm.ATEQ,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                              {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                              {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:   "TEQshiftRLreg",
 +              argLen: 3,
 +              asm:    arm.ATEQ,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                              {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                              {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:   "TEQshiftRAreg",
 +              argLen: 3,
 +              asm:    arm.ATEQ,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                              {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                              {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:   "CMPF0",
 +              argLen: 1,
 +              asm:    arm.ACMPF,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 +                      },
 +              },
 +      },
 +      {
 +              name:   "CMPD0",
 +              argLen: 1,
 +              asm:    arm.ACMPD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 +                      },
 +              },
 +      },
 +      {
 +              name:              "MOVWconst",
 +              auxType:           auxInt32,
 +              argLen:            0,
 +              rematerializeable: true,
 +              asm:               arm.AMOVW,
 +              reg: regInfo{
 +                      outputs: []outputInfo{
 +                              {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:              "MOVFconst",
 +              auxType:           auxFloat64,
 +              argLen:            0,
 +              rematerializeable: true,
 +              asm:               arm.AMOVF,
 +              reg: regInfo{
 +                      outputs: []outputInfo{
 +                              {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 +                      },
 +              },
 +      },
 +      {
 +              name:              "MOVDconst",
 +              auxType:           auxFloat64,
 +              argLen:            0,
 +              rematerializeable: true,
 +              asm:               arm.AMOVD,
 +              reg: regInfo{
 +                      outputs: []outputInfo{
 +                              {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 +                      },
 +              },
 +      },
 +      {
 +              name:              "MOVWaddr",
 +              auxType:           auxSymOff,
 +              argLen:            1,
 +              rematerializeable: true,
 +              symEffect:         SymAddr,
 +              asm:               arm.AMOVW,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 4294975488}, // SP SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:           "MOVBload",
 +              auxType:        auxSymOff,
 +              argLen:         2,
 +              faultOnNilArg0: true,
 +              symEffect:      SymRead,
 +              asm:            arm.AMOVB,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:           "MOVBUload",
 +              auxType:        auxSymOff,
 +              argLen:         2,
 +              faultOnNilArg0: true,
 +              symEffect:      SymRead,
 +              asm:            arm.AMOVBU,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:           "MOVHload",
 +              auxType:        auxSymOff,
 +              argLen:         2,
 +              faultOnNilArg0: true,
 +              symEffect:      SymRead,
 +              asm:            arm.AMOVH,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:           "MOVHUload",
 +              auxType:        auxSymOff,
 +              argLen:         2,
 +              faultOnNilArg0: true,
 +              symEffect:      SymRead,
 +              asm:            arm.AMOVHU,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:           "MOVWload",
 +              auxType:        auxSymOff,
 +              argLen:         2,
 +              faultOnNilArg0: true,
 +              symEffect:      SymRead,
 +              asm:            arm.AMOVW,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:           "MOVFload",
 +              auxType:        auxSymOff,
 +              argLen:         2,
 +              faultOnNilArg0: true,
 +              symEffect:      SymRead,
 +              asm:            arm.AMOVF,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 +                      },
 +              },
 +      },
 +      {
 +              name:           "MOVDload",
 +              auxType:        auxSymOff,
 +              argLen:         2,
 +              faultOnNilArg0: true,
 +              symEffect:      SymRead,
 +              asm:            arm.AMOVD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 +                      },
 +              },
 +      },
 +      {
 +              name:           "MOVBstore",
 +              auxType:        auxSymOff,
 +              argLen:         3,
 +              faultOnNilArg0: true,
 +              symEffect:      SymWrite,
 +              asm:            arm.AMOVB,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 22527},      // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
 +                              {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB
 +                      },
 +              },
 +      },
 +      {
 +              name:           "MOVHstore",
 +              auxType:        auxSymOff,
 +              argLen:         3,
 +              faultOnNilArg0: true,
 +              symEffect:      SymWrite,
 +              asm:            arm.AMOVH,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 22527},      // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
 +                              {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB
 +                      },
 +              },
 +      },
 +      {
 +              name:           "MOVWstore",
 +              auxType:        auxSymOff,
 +              argLen:         3,
 +              faultOnNilArg0: true,
 +              symEffect:      SymWrite,
 +              asm:            arm.AMOVW,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 22527},      // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
 +                              {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB
 +                      },
 +              },
 +      },
 +      {
 +              name:           "MOVFstore",
 +              auxType:        auxSymOff,
 +              argLen:         3,
 +              faultOnNilArg0: true,
 +              symEffect:      SymWrite,
 +              asm:            arm.AMOVF,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB
 +                              {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 +                      },
 +              },
 +      },
 +      {
 +              name:           "MOVDstore",
 +              auxType:        auxSymOff,
 +              argLen:         3,
 +              faultOnNilArg0: true,
 +              symEffect:      SymWrite,
 +              asm:            arm.AMOVD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB
 +                              {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 +                      },
 +              },
 +      },
 +      {
 +              name:   "MOVWloadidx",
 +              argLen: 3,
 +              asm:    arm.AMOVW,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 22527},      // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
 +                              {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:    "MOVWloadshiftLL",
 +              auxType: auxInt32,
 +              argLen:  3,
 +              asm:     arm.AMOVW,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 22527},      // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
 +                              {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:    "MOVWloadshiftRL",
 +              auxType: auxInt32,
 +              argLen:  3,
 +              asm:     arm.AMOVW,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 22527},      // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
 +                              {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:    "MOVWloadshiftRA",
 +              auxType: auxInt32,
 +              argLen:  3,
 +              asm:     arm.AMOVW,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 22527},      // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
 +                              {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:   "MOVBUloadidx",
 +              argLen: 3,
 +              asm:    arm.AMOVBU,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 22527},      // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
 +                              {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:   "MOVBloadidx",
 +              argLen: 3,
 +              asm:    arm.AMOVB,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 22527},      // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
 +                              {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:   "MOVHUloadidx",
 +              argLen: 3,
 +              asm:    arm.AMOVHU,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 22527},      // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
 +                              {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:   "MOVHloadidx",
 +              argLen: 3,
 +              asm:    arm.AMOVH,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 22527},      // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
 +                              {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:   "MOVWstoreidx",
 +              argLen: 4,
 +              asm:    arm.AMOVW,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 22527},      // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
 +                              {2, 22527},      // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
 +                              {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB
 +                      },
 +              },
 +      },
 +      {
 +              name:    "MOVWstoreshiftLL",
 +              auxType: auxInt32,
 +              argLen:  4,
 +              asm:     arm.AMOVW,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 22527},      // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
 +                              {2, 22527},      // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
 +                              {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB
 +                      },
 +              },
 +      },
 +      {
 +              name:    "MOVWstoreshiftRL",
 +              auxType: auxInt32,
 +              argLen:  4,
 +              asm:     arm.AMOVW,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 22527},      // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
 +                              {2, 22527},      // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
 +                              {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB
 +                      },
 +              },
 +      },
 +      {
 +              name:    "MOVWstoreshiftRA",
 +              auxType: auxInt32,
 +              argLen:  4,
 +              asm:     arm.AMOVW,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 22527},      // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
 +                              {2, 22527},      // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
 +                              {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB
 +                      },
 +              },
 +      },
 +      {
 +              name:   "MOVBstoreidx",
 +              argLen: 4,
 +              asm:    arm.AMOVB,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 22527},      // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
 +                              {2, 22527},      // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
 +                              {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB
 +                      },
 +              },
 +      },
 +      {
 +              name:   "MOVHstoreidx",
 +              argLen: 4,
 +              asm:    arm.AMOVH,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 22527},      // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
 +                              {2, 22527},      // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
 +                              {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB
 +                      },
 +              },
 +      },
 +      {
 +              name:   "MOVBreg",
 +              argLen: 1,
 +              asm:    arm.AMOVBS,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:   "MOVBUreg",
 +              argLen: 1,
 +              asm:    arm.AMOVBU,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:   "MOVHreg",
 +              argLen: 1,
 +              asm:    arm.AMOVHS,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:   "MOVHUreg",
 +              argLen: 1,
 +              asm:    arm.AMOVHU,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:   "MOVWreg",
 +              argLen: 1,
 +              asm:    arm.AMOVW,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:         "MOVWnop",
 +              argLen:       1,
 +              resultInArg0: true,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:   "MOVWF",
 +              argLen: 1,
 +              asm:    arm.AMOVWF,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                      },
 +                      clobbers: 2147483648, // F15
 +                      outputs: []outputInfo{
 +                              {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 +                      },
 +              },
 +      },
 +      {
 +              name:   "MOVWD",
 +              argLen: 1,
 +              asm:    arm.AMOVWD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                      },
 +                      clobbers: 2147483648, // F15
 +                      outputs: []outputInfo{
 +                              {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 +                      },
 +              },
 +      },
 +      {
 +              name:   "MOVWUF",
 +              argLen: 1,
 +              asm:    arm.AMOVWF,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                      },
 +                      clobbers: 2147483648, // F15
 +                      outputs: []outputInfo{
 +                              {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 +                      },
 +              },
 +      },
 +      {
 +              name:   "MOVWUD",
 +              argLen: 1,
 +              asm:    arm.AMOVWD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                      },
 +                      clobbers: 2147483648, // F15
 +                      outputs: []outputInfo{
 +                              {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 +                      },
 +              },
 +      },
 +      {
 +              name:   "MOVFW",
 +              argLen: 1,
 +              asm:    arm.AMOVFW,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 +                      },
 +                      clobbers: 2147483648, // F15
 +                      outputs: []outputInfo{
 +                              {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:   "MOVDW",
 +              argLen: 1,
 +              asm:    arm.AMOVDW,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 +                      },
 +                      clobbers: 2147483648, // F15
 +                      outputs: []outputInfo{
 +                              {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:   "MOVFWU",
 +              argLen: 1,
 +              asm:    arm.AMOVFW,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 +                      },
 +                      clobbers: 2147483648, // F15
 +                      outputs: []outputInfo{
 +                              {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:   "MOVDWU",
 +              argLen: 1,
 +              asm:    arm.AMOVDW,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 +                      },
 +                      clobbers: 2147483648, // F15
 +                      outputs: []outputInfo{
 +                              {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:   "MOVFD",
 +              argLen: 1,
 +              asm:    arm.AMOVFD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 +                      },
 +              },
 +      },
 +      {
 +              name:   "MOVDF",
 +              argLen: 1,
 +              asm:    arm.AMOVDF,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 +                      },
 +              },
 +      },
 +      {
 +              name:         "CMOVWHSconst",
 +              auxType:      auxInt32,
 +              argLen:       2,
 +              resultInArg0: true,
 +              asm:          arm.AMOVW,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:         "CMOVWLSconst",
 +              auxType:      auxInt32,
 +              argLen:       2,
 +              resultInArg0: true,
 +              asm:          arm.AMOVW,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:   "SRAcond",
 +              argLen: 3,
 +              asm:    arm.ASRA,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                              {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:         "CALLstatic",
 +              auxType:      auxCallOff,
 +              argLen:       1,
 +              clobberFlags: true,
 +              call:         true,
 +              reg: regInfo{
 +                      clobbers: 4294924287, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 +              },
 +      },
 +      {
 +              name:         "CALLtail",
 +              auxType:      auxCallOff,
 +              argLen:       1,
 +              clobberFlags: true,
 +              call:         true,
 +              tailCall:     true,
 +              reg: regInfo{
 +                      clobbers: 4294924287, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 +              },
 +      },
 +      {
 +              name:         "CALLclosure",
 +              auxType:      auxCallOff,
 +              argLen:       3,
 +              clobberFlags: true,
 +              call:         true,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 128},   // R7
 +                              {0, 29695}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 SP R14
 +                      },
 +                      clobbers: 4294924287, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 +              },
 +      },
 +      {
 +              name:         "CALLinter",
 +              auxType:      auxCallOff,
 +              argLen:       2,
 +              clobberFlags: true,
 +              call:         true,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                      },
 +                      clobbers: 4294924287, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 +              },
 +      },
 +      {
 +              name:           "LoweredNilCheck",
 +              argLen:         2,
 +              nilCheck:       true,
 +              faultOnNilArg0: true,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:   "Equal",
 +              argLen: 1,
 +              reg: regInfo{
 +                      outputs: []outputInfo{
 +                              {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:   "NotEqual",
 +              argLen: 1,
 +              reg: regInfo{
 +                      outputs: []outputInfo{
 +                              {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:   "LessThan",
 +              argLen: 1,
 +              reg: regInfo{
 +                      outputs: []outputInfo{
 +                              {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:   "LessEqual",
 +              argLen: 1,
 +              reg: regInfo{
 +                      outputs: []outputInfo{
 +                              {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:   "GreaterThan",
 +              argLen: 1,
 +              reg: regInfo{
 +                      outputs: []outputInfo{
 +                              {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:   "GreaterEqual",
 +              argLen: 1,
 +              reg: regInfo{
 +                      outputs: []outputInfo{
 +                              {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:   "LessThanU",
 +              argLen: 1,
 +              reg: regInfo{
 +                      outputs: []outputInfo{
 +                              {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:   "LessEqualU",
 +              argLen: 1,
 +              reg: regInfo{
 +                      outputs: []outputInfo{
 +                              {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:   "GreaterThanU",
 +              argLen: 1,
 +              reg: regInfo{
 +                      outputs: []outputInfo{
 +                              {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:   "GreaterEqualU",
 +              argLen: 1,
 +              reg: regInfo{
 +                      outputs: []outputInfo{
 +                              {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:           "DUFFZERO",
 +              auxType:        auxInt64,
 +              argLen:         3,
 +              faultOnNilArg0: true,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 2}, // R1
 +                              {1, 1}, // R0
 +                      },
 +                      clobbers: 20482, // R1 R12 R14
 +              },
 +      },
 +      {
 +              name:           "DUFFCOPY",
 +              auxType:        auxInt64,
 +              argLen:         3,
 +              faultOnNilArg0: true,
 +              faultOnNilArg1: true,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 4}, // R2
 +                              {1, 2}, // R1
 +                      },
 +                      clobbers: 20487, // R0 R1 R2 R12 R14
 +              },
 +      },
 +      {
 +              name:           "LoweredZero",
 +              auxType:        auxInt64,
 +              argLen:         4,
 +              clobberFlags:   true,
 +              faultOnNilArg0: true,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 2},     // R1
 +                              {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                              {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                      },
 +                      clobbers: 2, // R1
 +              },
 +      },
 +      {
 +              name:           "LoweredMove",
 +              auxType:        auxInt64,
 +              argLen:         4,
 +              clobberFlags:   true,
 +              faultOnNilArg0: true,
 +              faultOnNilArg1: true,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 4},     // R2
 +                              {1, 2},     // R1
 +                              {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                      },
 +                      clobbers: 6, // R1 R2
 +              },
 +      },
 +      {
 +              name:      "LoweredGetClosurePtr",
 +              argLen:    0,
 +              zeroWidth: true,
 +              reg: regInfo{
 +                      outputs: []outputInfo{
 +                              {0, 128}, // R7
 +                      },
 +              },
 +      },
 +      {
 +              name:              "LoweredGetCallerSP",
 +              argLen:            1,
 +              rematerializeable: true,
 +              reg: regInfo{
 +                      outputs: []outputInfo{
 +                              {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:              "LoweredGetCallerPC",
 +              argLen:            0,
 +              rematerializeable: true,
 +              reg: regInfo{
 +                      outputs: []outputInfo{
 +                              {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:    "LoweredPanicBoundsRR",
 +              auxType: auxInt64,
 +              argLen:  3,
 +              call:    true,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
 +                              {1, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
 +                      },
 +              },
 +      },
 +      {
 +              name:    "LoweredPanicBoundsRC",
 +              auxType: auxPanicBoundsC,
 +              argLen:  2,
 +              call:    true,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
 +                      },
 +              },
 +      },
 +      {
 +              name:    "LoweredPanicBoundsCR",
 +              auxType: auxPanicBoundsC,
 +              argLen:  2,
 +              call:    true,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
 +                      },
 +              },
 +      },
 +      {
 +              name:    "LoweredPanicBoundsCC",
 +              auxType: auxPanicBoundsCC,
 +              argLen:  1,
 +              call:    true,
 +              reg:     regInfo{},
 +      },
 +      {
 +              name:    "LoweredPanicExtendRR",
 +              auxType: auxInt64,
 +              argLen:  4,
 +              call:    true,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 15},    // R0 R1 R2 R3
 +                              {1, 15},    // R0 R1 R2 R3
 +                              {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:    "LoweredPanicExtendRC",
 +              auxType: auxPanicBoundsC,
 +              argLen:  3,
 +              call:    true,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 15}, // R0 R1 R2 R3
 +                              {1, 15}, // R0 R1 R2 R3
 +                      },
 +              },
 +      },
 +      {
 +              name:    "FlagConstant",
 +              auxType: auxFlagConstant,
 +              argLen:  0,
 +              reg:     regInfo{},
 +      },
 +      {
 +              name:   "InvertFlags",
 +              argLen: 1,
 +              reg:    regInfo{},
 +      },
 +      {
 +              name:         "LoweredWB",
 +              auxType:      auxInt64,
 +              argLen:       1,
 +              clobberFlags: true,
 +              reg: regInfo{
 +                      clobbers: 4294922240, // R12 R14 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 +                      outputs: []outputInfo{
 +                              {0, 256}, // R8
 +                      },
 +              },
 +      },
 +
 +      {
 +              name:        "ADCSflags",
 +              argLen:      3,
 +              commutative: true,
 +              asm:         arm64.AADCS,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 +                              {1, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 +                      },
 +                      outputs: []outputInfo{
 +                              {1, 0},
 +                              {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 +                      },
 +              },
 +      },
 +      {
 +              name:   "ADCzerocarry",
 +              argLen: 1,
 +              asm:    arm64.AADC,
 +              reg: regInfo{
 +                      outputs: []outputInfo{
 +                              {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 +                      },
 +              },
 +      },
 +      {
 +              name:        "ADD",
 +              argLen:      2,
 +              commutative: true,
 +              asm:         arm64.AADD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
 +                              {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 +                      },
 +              },
 +      },
 +      {
 +              name:    "ADDconst",
 +              auxType: auxInt64,
 +              argLen:  1,
 +              asm:     arm64.AADD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1476395007}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 +                      },
 +              },
 +      },
 +      {
 +              name:    "ADDSconstflags",
 +              auxType: auxInt64,
 +              argLen:  1,
 +              asm:     arm64.AADDS,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
 +                      },
 +                      outputs: []outputInfo{
 +                              {1, 0},
 +                              {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 +                      },
 +              },
 +      },
 +      {
 +              name:        "ADDSflags",
 +              argLen:      2,
 +              commutative: true,
 +              asm:         arm64.AADDS,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 +                              {1, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 +                      },
 +                      outputs: []outputInfo{
 +                              {1, 0},
 +                              {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 +                      },
 +              },
 +      },
 +      {
 +              name:   "SUB",
 +              argLen: 2,
 +              asm:    arm64.ASUB,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
 +                              {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 +                      },
 +              },
 +      },
 +      {
 +              name:    "SUBconst",
 +              auxType: auxInt64,
 +              argLen:  1,
 +              asm:     arm64.ASUB,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 +                      },
 +              },
 +      },
 +      {
 +              name:   "SBCSflags",
 +              argLen: 3,
 +              asm:    arm64.ASBCS,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 +                              {1, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 +                      },
 +                      outputs: []outputInfo{
 +                              {1, 0},
 +                              {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 +                      },
 +              },
 +      },
 +      {
 +              name:   "SUBSflags",
 +              argLen: 2,
 +              asm:    arm64.ASUBS,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 +                              {1, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 +                      },
 +                      outputs: []outputInfo{
 +                              {1, 0},
 +                              {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 +                      },
 +              },
 +      },
 +      {
 +              name:        "MUL",
 +              argLen:      2,
 +              commutative: true,
 +              asm:         arm64.AMUL,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
 +                              {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 +                      },
 +              },
 +      },
 +      {
 +              name:        "MULW",
 +              argLen:      2,
 +              commutative: true,
 +              asm:         arm64.AMULW,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
 +                              {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 +                      },
 +              },
 +      },
 +      {
 +              name:        "MNEG",
 +              argLen:      2,
 +              commutative: true,
 +              asm:         arm64.AMNEG,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
 +                              {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 +                      },
 +              },
 +      },
 +      {
 +              name:        "MNEGW",
 +              argLen:      2,
 +              commutative: true,
 +              asm:         arm64.AMNEGW,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
 +                              {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 +                      },
 +              },
 +      },
 +      {
 +              name:        "MULH",
 +              argLen:      2,
 +              commutative: true,
 +              asm:         arm64.ASMULH,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
 +                              {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 +                      },
 +              },
 +      },
 +      {
 +              name:        "UMULH",
 +              argLen:      2,
 +              commutative: true,
 +              asm:         arm64.AUMULH,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
 +                              {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 +                      },
 +              },
 +      },
 +      {
 +              name:        "MULL",
 +              argLen:      2,
 +              commutative: true,
 +              asm:         arm64.ASMULL,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
 +                              {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 +                      },
 +              },
 +      },
 +      {
 +              name:        "UMULL",
 +              argLen:      2,
 +              commutative: true,
 +              asm:         arm64.AUMULL,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
 +                              {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 +                      },
 +              },
 +      },
 +      {
 +              name:   "DIV",
 +              argLen: 2,
 +              asm:    arm64.ASDIV,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
 +                              {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 +                      },
 +              },
 +      },
 +      {
 +              name:   "UDIV",
 +              argLen: 2,
 +              asm:    arm64.AUDIV,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
 +                              {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 +                      },
 +              },
 +      },
 +      {
 +              name:   "DIVW",
 +              argLen: 2,
 +              asm:    arm64.ASDIVW,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
 +                              {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 +                      },
 +              },
 +      },
 +      {
 +              name:   "UDIVW",
 +              argLen: 2,
 +              asm:    arm64.AUDIVW,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
 +                              {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 +                      },
 +              },
 +      },
 +      {
 +              name:   "MOD",
 +              argLen: 2,
 +              asm:    arm64.AREM,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
 +                              {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 +                      },
 +              },
 +      },
 +      {
 +              name:   "UMOD",
 +              argLen: 2,
 +              asm:    arm64.AUREM,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
 +                              {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 +                      },
 +              },
 +      },
 +      {
 +              name:   "MODW",
 +              argLen: 2,
 +              asm:    arm64.AREMW,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
 +                              {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 +                      },
 +              },
 +      },
 +      {
 +              name:   "UMODW",
 +              argLen: 2,
 +              asm:    arm64.AUREMW,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
 +                              {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 +                      },
 +              },
 +      },
 +      {
 +              name:        "FADDS",
 +              argLen:      2,
 +              commutative: true,
 +              asm:         arm64.AFADDS,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                              {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +              },
 +      },
 +      {
 +              name:        "FADDD",
 +              argLen:      2,
 +              commutative: true,
 +              asm:         arm64.AFADDD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                              {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +              },
 +      },
 +      {
 +              name:   "FSUBS",
 +              argLen: 2,
 +              asm:    arm64.AFSUBS,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                              {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +              },
 +      },
 +      {
 +              name:   "FSUBD",
 +              argLen: 2,
 +              asm:    arm64.AFSUBD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                              {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +              },
 +      },
 +      {
 +              name:        "FMULS",
 +              argLen:      2,
 +              commutative: true,
 +              asm:         arm64.AFMULS,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                              {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +              },
 +      },
 +      {
 +              name:        "FMULD",
 +              argLen:      2,
 +              commutative: true,
 +              asm:         arm64.AFMULD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                              {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +              },
 +      },
 +      {
 +              name:        "FNMULS",
 +              argLen:      2,
 +              commutative: true,
 +              asm:         arm64.AFNMULS,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                              {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +              },
 +      },
 +      {
 +              name:        "FNMULD",
 +              argLen:      2,
 +              commutative: true,
 +              asm:         arm64.AFNMULD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                              {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +              },
 +      },
 +      {
 +              name:   "FDIVS",
 +              argLen: 2,
 +              asm:    arm64.AFDIVS,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                              {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +              },
 +      },
 +      {
 +              name:   "FDIVD",
 +              argLen: 2,
 +              asm:    arm64.AFDIVD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                              {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +              },
 +      },
 +      {
 +              name:        "AND",
 +              argLen:      2,
 +              commutative: true,
 +              asm:         arm64.AAND,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
 +                              {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 +                      },
 +              },
 +      },
 +      {
 +              name:    "ANDconst",
 +              auxType: auxInt64,
 +              argLen:  1,
 +              asm:     arm64.AAND,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 +                      },
 +              },
 +      },
 +      {
 +              name:        "OR",
 +              argLen:      2,
 +              commutative: true,
 +              asm:         arm64.AORR,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
 +                              {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 +                      },
 +              },
 +      },
 +      {
 +              name:    "ORconst",
 +              auxType: auxInt64,
 +              argLen:  1,
 +              asm:     arm64.AORR,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 +                      },
 +              },
 +      },
 +      {
 +              name:        "XOR",
 +              argLen:      2,
 +              commutative: true,
 +              asm:         arm64.AEOR,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
 +                              {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 +                      },
 +              },
 +      },
 +      {
 +              name:    "XORconst",
 +              auxType: auxInt64,
 +              argLen:  1,
 +              asm:     arm64.AEOR,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 +                      },
 +              },
 +      },
 +      {
 +              name:   "BIC",
 +              argLen: 2,
 +              asm:    arm64.ABIC,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
 +                              {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 +                      },
 +              },
 +      },
 +      {
 +              name:   "EON",
 +              argLen: 2,
 +              asm:    arm64.AEON,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
 +                              {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 +                      },
 +              },
 +      },
 +      {
 +              name:   "ORN",
 +              argLen: 2,
 +              asm:    arm64.AORN,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
 +                              {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 +                      },
 +              },
 +      },
 +      {
 +              name:   "MVN",
 +              argLen: 1,
 +              asm:    arm64.AMVN,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 +                      },
 +              },
 +      },
 +      {
 +              name:   "NEG",
 +              argLen: 1,
 +              asm:    arm64.ANEG,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 +                      },
 +              },
 +      },
 +      {
 +              name:   "NEGSflags",
 +              argLen: 1,
 +              asm:    arm64.ANEGS,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
 +                      },
 +                      outputs: []outputInfo{
 +                              {1, 0},
 +                              {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 +                      },
 +              },
 +      },
 +      {
 +              name:   "NGCzerocarry",
 +              argLen: 1,
 +              asm:    arm64.ANGC,
 +              reg: regInfo{
 +                      outputs: []outputInfo{
 +                              {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 +                      },
 +              },
 +      },
 +      {
 +              name:   "FABSD",
 +              argLen: 1,
 +              asm:    arm64.AFABSD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +              },
 +      },
 +      {
 +              name:   "FNEGS",
 +              argLen: 1,
 +              asm:    arm64.AFNEGS,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +              },
 +      },
 +      {
 +              name:   "FNEGD",
 +              argLen: 1,
 +              asm:    arm64.AFNEGD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +              },
 +      },
 +      {
 +              name:   "FSQRTD",
 +              argLen: 1,
 +              asm:    arm64.AFSQRTD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +              },
 +      },
 +      {
 +              name:   "FSQRTS",
 +              argLen: 1,
 +              asm:    arm64.AFSQRTS,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +              },
 +      },
 +      {
 +              name:   "FMIND",
 +              argLen: 2,
 +              asm:    arm64.AFMIND,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                              {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +              },
 +      },
 +      {
 +              name:   "FMINS",
 +              argLen: 2,
 +              asm:    arm64.AFMINS,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                              {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +              },
 +      },
 +      {
 +              name:   "FMAXD",
 +              argLen: 2,
 +              asm:    arm64.AFMAXD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                              {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +              },
 +      },
 +      {
 +              name:   "FMAXS",
 +              argLen: 2,
 +              asm:    arm64.AFMAXS,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                              {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +              },
 +      },
 +      {
 +              name:   "REV",
 +              argLen: 1,
 +              asm:    arm64.AREV,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 +                      },
 +              },
 +      },
 +      {
 +              name:   "REVW",
 +              argLen: 1,
 +              asm:    arm64.AREVW,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 +                      },
 +              },
 +      },
 +      {
 +              name:   "REV16",
 +              argLen: 1,
 +              asm:    arm64.AREV16,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 +                      },
 +              },
 +      },
 +      {
 +              name:   "REV16W",
 +              argLen: 1,
 +              asm:    arm64.AREV16W,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 +                      },
 +              },
 +      },
 +      {
 +              name:   "RBIT",
 +              argLen: 1,
 +              asm:    arm64.ARBIT,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 +                      },
 +              },
 +      },
 +      {
 +              name:   "RBITW",
 +              argLen: 1,
 +              asm:    arm64.ARBITW,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 +                      },
 +              },
 +      },
 +      {
 +              name:   "CLZ",
 +              argLen: 1,
 +              asm:    arm64.ACLZ,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 +                      },
 +              },
 +      },
 +      {
 +              name:   "CLZW",
 +              argLen: 1,
 +              asm:    arm64.ACLZW,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 +                      },
 +              },
 +      },
 +      {
 +              name:   "VCNT",
 +              argLen: 1,
 +              asm:    arm64.AVCNT,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +              },
 +      },
 +      {
 +              name:   "VUADDLV",
 +              argLen: 1,
 +              asm:    arm64.AVUADDLV,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "LoweredRound32F",
 +              argLen:       1,
 +              resultInArg0: true,
 +              zeroWidth:    true,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "LoweredRound64F",
 +              argLen:       1,
 +              resultInArg0: true,
 +              zeroWidth:    true,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +              },
 +      },
 +      {
 +              name:   "FMADDS",
 +              argLen: 3,
 +              asm:    arm64.AFMADDS,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                              {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                              {2, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +              },
 +      },
 +      {
 +              name:   "FMADDD",
 +              argLen: 3,
 +              asm:    arm64.AFMADDD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                              {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                              {2, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +              },
 +      },
 +      {
 +              name:   "FNMADDS",
 +              argLen: 3,
 +              asm:    arm64.AFNMADDS,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                              {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                              {2, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +              },
 +      },
 +      {
 +              name:   "FNMADDD",
 +              argLen: 3,
 +              asm:    arm64.AFNMADDD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                              {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                              {2, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +              },
 +      },
 +      {
 +              name:   "FMSUBS",
 +              argLen: 3,
 +              asm:    arm64.AFMSUBS,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                              {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                              {2, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +              },
 +      },
 +      {
 +              name:   "FMSUBD",
 +              argLen: 3,
 +              asm:    arm64.AFMSUBD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                              {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                              {2, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +              },
 +      },
 +      {
 +              name:   "FNMSUBS",
 +              argLen: 3,
 +              asm:    arm64.AFNMSUBS,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                              {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                              {2, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +              },
 +      },
 +      {
 +              name:   "FNMSUBD",
 +              argLen: 3,
 +              asm:    arm64.AFNMSUBD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                              {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                              {2, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +              },
 +      },
 +      {
 +              name:   "MADD",
 +              argLen: 3,
 +              asm:    arm64.AMADD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
 +                              {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
 +                              {2, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 +                      },
 +              },
 +      },
 +      {
 +              name:   "MADDW",
 +              argLen: 3,
 +              asm:    arm64.AMADDW,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
 +                              {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
 +                              {2, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 +                      },
 +              },
 +      },
 +      {
 +              name:   "MSUB",
 +              argLen: 3,
 +              asm:    arm64.AMSUB,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
 +                              {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
 +                              {2, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 +                      },
 +              },
 +      },
 +      {
 +              name:   "MSUBW",
 +              argLen: 3,
 +              asm:    arm64.AMSUBW,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
 +                              {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
 +                              {2, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 +                      },
 +              },
 +      },
 +      {
 +              name:   "SLL",
 +              argLen: 2,
 +              asm:    arm64.ALSL,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
 +                              {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 +                      },
 +              },
 +      },
 +      {
 +              name:    "SLLconst",
 +              auxType: auxInt64,
 +              argLen:  1,
 +              asm:     arm64.ALSL,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 +                      },
 +              },
 +      },
 +      {
 +              name:   "SRL",
 +              argLen: 2,
 +              asm:    arm64.ALSR,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
 +                              {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 +                      },
 +              },
 +      },
 +      {
 +              name:    "SRLconst",
 +              auxType: auxInt64,
 +              argLen:  1,
 +              asm:     arm64.ALSR,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 +                      },
 +              },
 +      },
 +      {
 +              name:   "SRA",
 +              argLen: 2,
 +              asm:    arm64.AASR,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
 +                              {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 +                      },
 +              },
 +      },
 +      {
 +              name:    "SRAconst",
 +              auxType: auxInt64,
 +              argLen:  1,
 +              asm:     arm64.AASR,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 +                      },
 +              },
 +      },
 +      {
 +              name:   "ROR",
 +              argLen: 2,
 +              asm:    arm64.AROR,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
 +                              {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 +                      },
 +              },
 +      },
 +      {
 +              name:   "RORW",
 +              argLen: 2,
 +              asm:    arm64.ARORW,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
 +                              {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 +                      },
 +              },
 +      },
 +      {
 +              name:    "RORconst",
 +              auxType: auxInt64,
 +              argLen:  1,
 +              asm:     arm64.AROR,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 +                      },
 +              },
 +      },
 +      {
 +              name:    "RORWconst",
 +              auxType: auxInt64,
 +              argLen:  1,
 +              asm:     arm64.ARORW,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 +                      },
 +              },
 +      },
 +      {
 +              name:    "EXTRconst",
 +              auxType: auxInt64,
 +              argLen:  2,
 +              asm:     arm64.AEXTR,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
 +                              {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 +                      },
 +              },
 +      },
 +      {
 +              name:    "EXTRWconst",
 +              auxType: auxInt64,
 +              argLen:  2,
 +              asm:     arm64.AEXTRW,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
 +                              {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 +                      },
 +              },
 +      },
 +      {
 +              name:   "CMP",
 +              argLen: 2,
 +              asm:    arm64.ACMP,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
 +                              {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
 +                      },
 +              },
 +      },
 +      {
 +              name:    "CMPconst",
 +              auxType: auxInt64,
 +              argLen:  1,
 +              asm:     arm64.ACMP,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
 +                      },
 +              },
 +      },
 +      {
 +              name:   "CMPW",
 +              argLen: 2,
 +              asm:    arm64.ACMPW,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
 +                              {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
 +                      },
 +              },
 +      },
 +      {
 +              name:    "CMPWconst",
 +              auxType: auxInt32,
 +              argLen:  1,
 +              asm:     arm64.ACMPW,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
 +                      },
 +              },
 +      },
 +      {
 +              name:        "CMN",
 +              argLen:      2,
 +              commutative: true,
 +              asm:         arm64.ACMN,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
 +                              {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
 +                      },
 +              },
 +      },
 +      {
 +              name:    "CMNconst",
 +              auxType: auxInt64,
 +              argLen:  1,
 +              asm:     arm64.ACMN,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
 +                      },
 +              },
 +      },
 +      {
 +              name:        "CMNW",
 +              argLen:      2,
 +              commutative: true,
 +              asm:         arm64.ACMNW,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
 +                              {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
 +                      },
 +              },
 +      },
 +      {
 +              name:    "CMNWconst",
 +              auxType: auxInt32,
 +              argLen:  1,
 +              asm:     arm64.ACMNW,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
 +                      },
 +              },
 +      },
 +      {
 +              name:        "TST",
 +              argLen:      2,
 +              commutative: true,
 +              asm:         arm64.ATST,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
 +                              {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
 +                      },
 +              },
 +      },
 +      {
 +              name:    "TSTconst",
 +              auxType: auxInt64,
 +              argLen:  1,
 +              asm:     arm64.ATST,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
 +                      },
 +              },
 +      },
 +      {
 +              name:        "TSTW",
 +              argLen:      2,
 +              commutative: true,
 +              asm:         arm64.ATSTW,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
 +                              {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
 +                      },
 +              },
 +      },
 +      {
 +              name:    "TSTWconst",
 +              auxType: auxInt32,
 +              argLen:  1,
 +              asm:     arm64.ATSTW,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
 +                      },
 +              },
 +      },
 +      {
 +              name:   "FCMPS",
 +              argLen: 2,
 +              asm:    arm64.AFCMPS,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                              {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +              },
 +      },
 +      {
 +              name:   "FCMPD",
 +              argLen: 2,
 +              asm:    arm64.AFCMPD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                              {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +              },
 +      },
 +      {
 +              name:   "FCMPS0",
 +              argLen: 1,
 +              asm:    arm64.AFCMPS,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +              },
 +      },
 +      {
 +              name:   "FCMPD0",
 +              argLen: 1,
 +              asm:    arm64.AFCMPD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +              },
 +      },
 +      {
 +              name:    "MVNshiftLL",
 +              auxType: auxInt64,
 +              argLen:  1,
 +              asm:     arm64.AMVN,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 +                      },
 +              },
 +      },
 +      {
 +              name:    "MVNshiftRL",
 +              auxType: auxInt64,
 +              argLen:  1,
 +              asm:     arm64.AMVN,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 +                      },
 +              },
 +      },
 +      {
 +              name:    "MVNshiftRA",
 +              auxType: auxInt64,
 +              argLen:  1,
 +              asm:     arm64.AMVN,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 +                      },
 +              },
 +      },
 +      {
 +              name:    "MVNshiftRO",
 +              auxType: auxInt64,
 +              argLen:  1,
 +              asm:     arm64.AMVN,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 +                      },
 +              },
 +      },
 +      {
 +              name:    "NEGshiftLL",
 +              auxType: auxInt64,
 +              argLen:  1,
 +              asm:     arm64.ANEG,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 +                      },
 +              },
 +      },
 +      {
 +              name:    "NEGshiftRL",
 +              auxType: auxInt64,
 +              argLen:  1,
 +              asm:     arm64.ANEG,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 +                      },
 +              },
 +      },
 +      {
 +              name:    "NEGshiftRA",
 +              auxType: auxInt64,
 +              argLen:  1,
 +              asm:     arm64.ANEG,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 +                      },
 +              },
 +      },
 +      {
 +              name:    "ADDshiftLL",
 +              auxType: auxInt64,
 +              argLen:  2,
 +              asm:     arm64.AADD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
 +                              {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 +                      },
 +              },
 +      },
 +      {
 +              name:    "ADDshiftRL",
 +              auxType: auxInt64,
 +              argLen:  2,
 +              asm:     arm64.AADD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
 +                              {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 +                      },
 +              },
 +      },
 +      {
 +              name:    "ADDshiftRA",
 +              auxType: auxInt64,
 +              argLen:  2,
 +              asm:     arm64.AADD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
 +                              {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 +                      },
 +              },
 +      },
 +      {
 +              name:    "SUBshiftLL",
 +              auxType: auxInt64,
 +              argLen:  2,
 +              asm:     arm64.ASUB,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
 +                              {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 +                      },
 +              },
 +      },
 +      {
 +              name:    "SUBshiftRL",
 +              auxType: auxInt64,
 +              argLen:  2,
 +              asm:     arm64.ASUB,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
 +                              {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 +                      },
 +              },
 +      },
 +      {
 +              name:    "SUBshiftRA",
 +              auxType: auxInt64,
 +              argLen:  2,
 +              asm:     arm64.ASUB,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
 +                              {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 +                      },
 +              },
 +      },
 +      {
 +              name:    "ANDshiftLL",
 +              auxType: auxInt64,
 +              argLen:  2,
 +              asm:     arm64.AAND,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
 +                              {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 +                      },
 +              },
 +      },
 +      {
 +              name:    "ANDshiftRL",
 +              auxType: auxInt64,
 +              argLen:  2,
 +              asm:     arm64.AAND,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
 +                              {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 +                      },
 +              },
 +      },
 +      {
 +              name:    "ANDshiftRA",
 +              auxType: auxInt64,
 +              argLen:  2,
 +              asm:     arm64.AAND,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
 +                              {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 +                      },
 +              },
 +      },
 +      {
 +              name:    "ANDshiftRO",
 +              auxType: auxInt64,
 +              argLen:  2,
 +              asm:     arm64.AAND,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
 +                              {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 +                      },
 +              },
 +      },
 +      {
 +              name:    "ORshiftLL",
 +              auxType: auxInt64,
 +              argLen:  2,
 +              asm:     arm64.AORR,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
 +                              {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 +                      },
 +              },
 +      },
 +      {
 +              name:    "ORshiftRL",
 +              auxType: auxInt64,
 +              argLen:  2,
 +              asm:     arm64.AORR,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
 +                              {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 +                      },
 +              },
 +      },
 +      {
 +              name:    "ORshiftRA",
 +              auxType: auxInt64,
 +              argLen:  2,
 +              asm:     arm64.AORR,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
 +                              {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 +                      },
 +              },
 +      },
 +      {
 +              name:    "ORshiftRO",
 +              auxType: auxInt64,
 +              argLen:  2,
 +              asm:     arm64.AORR,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
 +                              {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 +                      },
 +              },
 +      },
 +      {
 +              name:    "XORshiftLL",
 +              auxType: auxInt64,
 +              argLen:  2,
 +              asm:     arm64.AEOR,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
 +                              {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 +                      },
 +              },
 +      },
 +      {
 +              name:    "XORshiftRL",
 +              auxType: auxInt64,
 +              argLen:  2,
 +              asm:     arm64.AEOR,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
 +                              {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 +                      },
 +              },
 +      },
 +      {
 +              name:    "XORshiftRA",
 +              auxType: auxInt64,
 +              argLen:  2,
 +              asm:     arm64.AEOR,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
 +                              {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 +                      },
 +              },
 +      },
 +      {
 +              name:    "XORshiftRO",
 +              auxType: auxInt64,
 +              argLen:  2,
 +              asm:     arm64.AEOR,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
 +                              {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 +                      },
 +              },
 +      },
 +      {
 +              name:    "BICshiftLL",
 +              auxType: auxInt64,
 +              argLen:  2,
 +              asm:     arm64.ABIC,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
 +                              {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 +                      },
 +              },
 +      },
 +      {
 +              name:    "BICshiftRL",
 +              auxType: auxInt64,
 +              argLen:  2,
 +              asm:     arm64.ABIC,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
 +                              {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 +                      },
 +              },
 +      },
 +      {
 +              name:    "BICshiftRA",
 +              auxType: auxInt64,
 +              argLen:  2,
 +              asm:     arm64.ABIC,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
 +                              {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 +                      },
 +              },
 +      },
 +      {
 +              name:    "BICshiftRO",
 +              auxType: auxInt64,
 +              argLen:  2,
 +              asm:     arm64.ABIC,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
 +                              {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 +                      },
 +              },
 +      },
 +      {
 +              name:    "EONshiftLL",
 +              auxType: auxInt64,
 +              argLen:  2,
 +              asm:     arm64.AEON,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
 +                              {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 +                      },
 +              },
 +      },
 +      {
 +              name:    "EONshiftRL",
 +              auxType: auxInt64,
 +              argLen:  2,
 +              asm:     arm64.AEON,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
 +                              {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 +                      },
 +              },
 +      },
 +      {
 +              name:    "EONshiftRA",
 +              auxType: auxInt64,
 +              argLen:  2,
 +              asm:     arm64.AEON,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
 +                              {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 +                      },
 +              },
 +      },
 +      {
 +              name:    "EONshiftRO",
 +              auxType: auxInt64,
 +              argLen:  2,
 +              asm:     arm64.AEON,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
 +                              {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 +                      },
 +              },
 +      },
 +      {
 +              name:    "ORNshiftLL",
 +              auxType: auxInt64,
 +              argLen:  2,
 +              asm:     arm64.AORN,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
 +                              {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 +                      },
 +              },
 +      },
 +      {
 +              name:    "ORNshiftRL",
 +              auxType: auxInt64,
 +              argLen:  2,
 +              asm:     arm64.AORN,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
 +                              {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 +                      },
 +              },
 +      },
 +      {
 +              name:    "ORNshiftRA",
 +              auxType: auxInt64,
 +              argLen:  2,
 +              asm:     arm64.AORN,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
 +                              {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 +                      },
 +              },
 +      },
 +      {
 +              name:    "ORNshiftRO",
 +              auxType: auxInt64,
 +              argLen:  2,
 +              asm:     arm64.AORN,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
 +                              {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 +                      },
 +              },
 +      },
 +      {
 +              name:    "CMPshiftLL",
 +              auxType: auxInt64,
 +              argLen:  2,
 +              asm:     arm64.ACMP,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
 +                              {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
 +                      },
 +              },
 +      },
 +      {
 +              name:    "CMPshiftRL",
 +              auxType: auxInt64,
 +              argLen:  2,
 +              asm:     arm64.ACMP,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
 +                              {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
 +                      },
 +              },
 +      },
 +      {
 +              name:    "CMPshiftRA",
 +              auxType: auxInt64,
 +              argLen:  2,
 +              asm:     arm64.ACMP,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
 +                              {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
 +                      },
 +              },
 +      },
 +      {
 +              name:    "CMNshiftLL",
 +              auxType: auxInt64,
 +              argLen:  2,
 +              asm:     arm64.ACMN,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
 +                              {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
 +                      },
 +              },
 +      },
 +      {
 +              name:    "CMNshiftRL",
 +              auxType: auxInt64,
 +              argLen:  2,
 +              asm:     arm64.ACMN,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
 +                              {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
 +                      },
 +              },
 +      },
 +      {
 +              name:    "CMNshiftRA",
 +              auxType: auxInt64,
 +              argLen:  2,
 +              asm:     arm64.ACMN,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
 +                              {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
 +                      },
 +              },
 +      },
 +      {
 +              name:    "TSTshiftLL",
 +              auxType: auxInt64,
 +              argLen:  2,
 +              asm:     arm64.ATST,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
 +                              {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
 +                      },
 +              },
 +      },
 +      {
 +              name:    "TSTshiftRL",
 +              auxType: auxInt64,
 +              argLen:  2,
 +              asm:     arm64.ATST,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
 +                              {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
 +                      },
 +              },
 +      },
 +      {
 +              name:    "TSTshiftRA",
 +              auxType: auxInt64,
 +              argLen:  2,
 +              asm:     arm64.ATST,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
 +                              {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
 +                      },
 +              },
 +      },
 +      {
 +              name:    "TSTshiftRO",
 +              auxType: auxInt64,
 +              argLen:  2,
 +              asm:     arm64.ATST,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
 +                              {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
 +                      },
 +              },
 +      },
 +      {
 +              name:         "BFI",
 +              auxType:      auxARM64BitField,
 +              argLen:       2,
 +              resultInArg0: true,
 +              asm:          arm64.ABFI,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 +                              {1, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 +                      },
 +              },
 +      },
 +      {
 +              name:         "BFXIL",
 +              auxType:      auxARM64BitField,
 +              argLen:       2,
 +              resultInArg0: true,
 +              asm:          arm64.ABFXIL,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 +                              {1, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 +                      },
 +              },
 +      },
 +      {
 +              name:    "SBFIZ",
 +              auxType: auxARM64BitField,
 +              argLen:  1,
 +              asm:     arm64.ASBFIZ,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 +                      },
 +              },
 +      },
 +      {
 +              name:    "SBFX",
 +              auxType: auxARM64BitField,
 +              argLen:  1,
 +              asm:     arm64.ASBFX,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 +                      },
 +              },
 +      },
 +      {
 +              name:    "UBFIZ",
 +              auxType: auxARM64BitField,
 +              argLen:  1,
 +              asm:     arm64.AUBFIZ,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 +                      },
 +              },
 +      },
 +      {
 +              name:    "UBFX",
 +              auxType: auxARM64BitField,
 +              argLen:  1,
 +              asm:     arm64.AUBFX,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 +                      },
 +              },
 +      },
 +      {
 +              name:              "MOVDconst",
 +              auxType:           auxInt64,
 +              argLen:            0,
 +              rematerializeable: true,
 +              asm:               arm64.AMOVD,
 +              reg: regInfo{
 +                      outputs: []outputInfo{
 +                              {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 +                      },
 +              },
 +      },
 +      {
 +              name:              "FMOVSconst",
 +              auxType:           auxFloat64,
 +              argLen:            0,
 +              rematerializeable: true,
 +              asm:               arm64.AFMOVS,
 +              reg: regInfo{
 +                      outputs: []outputInfo{
 +                              {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +              },
 +      },
 +      {
 +              name:              "FMOVDconst",
 +              auxType:           auxFloat64,
 +              argLen:            0,
 +              rematerializeable: true,
 +              asm:               arm64.AFMOVD,
 +              reg: regInfo{
 +                      outputs: []outputInfo{
 +                              {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +              },
 +      },
 +      {
 +              name:              "MOVDaddr",
 +              auxType:           auxSymOff,
 +              argLen:            1,
 +              rematerializeable: true,
 +              symEffect:         SymAddr,
 +              asm:               arm64.AMOVD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 9223372037928517632}, // SP SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 +                      },
 +              },
 +      },
 +      {
 +              name:           "MOVBload",
 +              auxType:        auxSymOff,
 +              argLen:         2,
 +              faultOnNilArg0: true,
 +              symEffect:      SymRead,
 +              asm:            arm64.AMOVB,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 +                      },
 +              },
 +      },
 +      {
 +              name:           "MOVBUload",
 +              auxType:        auxSymOff,
 +              argLen:         2,
 +              faultOnNilArg0: true,
 +              symEffect:      SymRead,
 +              asm:            arm64.AMOVBU,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 +                      },
 +              },
 +      },
 +      {
 +              name:           "MOVHload",
 +              auxType:        auxSymOff,
 +              argLen:         2,
 +              faultOnNilArg0: true,
 +              symEffect:      SymRead,
 +              asm:            arm64.AMOVH,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 +                      },
 +              },
 +      },
 +      {
 +              name:           "MOVHUload",
 +              auxType:        auxSymOff,
 +              argLen:         2,
 +              faultOnNilArg0: true,
 +              symEffect:      SymRead,
 +              asm:            arm64.AMOVHU,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 +                      },
 +              },
 +      },
 +      {
 +              name:           "MOVWload",
 +              auxType:        auxSymOff,
 +              argLen:         2,
 +              faultOnNilArg0: true,
 +              symEffect:      SymRead,
 +              asm:            arm64.AMOVW,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 +                      },
 +              },
 +      },
 +      {
 +              name:           "MOVWUload",
 +              auxType:        auxSymOff,
 +              argLen:         2,
 +              faultOnNilArg0: true,
 +              symEffect:      SymRead,
 +              asm:            arm64.AMOVWU,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 +                      },
 +              },
 +      },
 +      {
 +              name:           "MOVDload",
 +              auxType:        auxSymOff,
 +              argLen:         2,
 +              faultOnNilArg0: true,
 +              symEffect:      SymRead,
 +              asm:            arm64.AMOVD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 +                      },
 +              },
 +      },
 +      {
 +              name:           "FMOVSload",
 +              auxType:        auxSymOff,
 +              argLen:         2,
 +              faultOnNilArg0: true,
 +              symEffect:      SymRead,
 +              asm:            arm64.AFMOVS,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +              },
 +      },
 +      {
 +              name:           "FMOVDload",
 +              auxType:        auxSymOff,
 +              argLen:         2,
 +              faultOnNilArg0: true,
 +              symEffect:      SymRead,
 +              asm:            arm64.AFMOVD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +              },
 +      },
 +      {
 +              name:           "LDP",
 +              auxType:        auxSymOff,
 +              argLen:         2,
 +              faultOnNilArg0: true,
 +              symEffect:      SymRead,
 +              asm:            arm64.ALDP,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
 +                              {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
 +                      },
 +              },
 +      },
 +      {
 +              name:           "LDPW",
 +              auxType:        auxSymOff,
 +              argLen:         2,
 +              faultOnNilArg0: true,
 +              symEffect:      SymRead,
 +              asm:            arm64.ALDPW,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
 +                              {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
 +                      },
 +              },
 +      },
 +      {
 +              name:           "LDPSW",
 +              auxType:        auxSymOff,
 +              argLen:         2,
 +              faultOnNilArg0: true,
 +              symEffect:      SymRead,
 +              asm:            arm64.ALDPSW,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
 +                              {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
 +                      },
 +              },
 +      },
 +      {
 +              name:           "FLDPD",
 +              auxType:        auxSymOff,
 +              argLen:         2,
 +              faultOnNilArg0: true,
 +              symEffect:      SymRead,
 +              asm:            arm64.AFLDPD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                              {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +              },
 +      },
 +      {
 +              name:           "FLDPS",
 +              auxType:        auxSymOff,
 +              argLen:         2,
 +              faultOnNilArg0: true,
 +              symEffect:      SymRead,
 +              asm:            arm64.AFLDPS,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                              {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +              },
 +      },
 +      {
 +              name:   "MOVDloadidx",
 +              argLen: 3,
 +              asm:    arm64.AMOVD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 402653183},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
 +                              {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 +                      },
 +              },
 +      },
 +      {
 +              name:   "MOVWloadidx",
 +              argLen: 3,
 +              asm:    arm64.AMOVW,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 402653183},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
 +                              {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 +                      },
 +              },
 +      },
 +      {
 +              name:   "MOVWUloadidx",
 +              argLen: 3,
 +              asm:    arm64.AMOVWU,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 402653183},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
 +                              {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 +                      },
 +              },
 +      },
 +      {
 +              name:   "MOVHloadidx",
 +              argLen: 3,
 +              asm:    arm64.AMOVH,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 402653183},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
 +                              {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 +                      },
 +              },
 +      },
 +      {
 +              name:   "MOVHUloadidx",
 +              argLen: 3,
 +              asm:    arm64.AMOVHU,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 402653183},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
 +                              {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 +                      },
 +              },
 +      },
 +      {
 +              name:   "MOVBloadidx",
 +              argLen: 3,
 +              asm:    arm64.AMOVB,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 402653183},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
 +                              {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 +                      },
 +              },
 +      },
 +      {
 +              name:   "MOVBUloadidx",
 +              argLen: 3,
 +              asm:    arm64.AMOVBU,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 402653183},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
 +                              {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 +                      },
 +              },
 +      },
 +      {
 +              name:   "FMOVSloadidx",
 +              argLen: 3,
 +              asm:    arm64.AFMOVS,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 402653183},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
 +                              {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +              },
 +      },
 +      {
 +              name:   "FMOVDloadidx",
 +              argLen: 3,
 +              asm:    arm64.AFMOVD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 402653183},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
 +                              {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +              },
 +      },
 +      {
 +              name:   "MOVHloadidx2",
 +              argLen: 3,
 +              asm:    arm64.AMOVH,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 402653183},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
 +                              {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 +                      },
 +              },
 +      },
 +      {
 +              name:   "MOVHUloadidx2",
 +              argLen: 3,
 +              asm:    arm64.AMOVHU,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 402653183},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
 +                              {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 +                      },
 +              },
 +      },
 +      {
 +              name:   "MOVWloadidx4",
 +              argLen: 3,
 +              asm:    arm64.AMOVW,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 402653183},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
 +                              {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 +                      },
 +              },
 +      },
 +      {
 +              name:   "MOVWUloadidx4",
 +              argLen: 3,
 +              asm:    arm64.AMOVWU,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 402653183},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
 +                              {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 +                      },
 +              },
 +      },
 +      {
 +              name:   "MOVDloadidx8",
 +              argLen: 3,
 +              asm:    arm64.AMOVD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 402653183},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
 +                              {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 +                      },
 +              },
 +      },
 +      {
 +              name:   "FMOVSloadidx4",
 +              argLen: 3,
 +              asm:    arm64.AFMOVS,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 402653183},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
 +                              {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +              },
 +      },
 +      {
 +              name:   "FMOVDloadidx8",
 +              argLen: 3,
 +              asm:    arm64.AFMOVD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 402653183},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
 +                              {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +              },
 +      },
 +      {
 +              name:           "MOVBstore",
 +              auxType:        auxSymOff,
 +              argLen:         3,
 +              faultOnNilArg0: true,
 +              symEffect:      SymWrite,
 +              asm:            arm64.AMOVB,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 939524095},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO
 +                              {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
 +                      },
 +              },
 +      },
 +      {
 +              name:           "MOVHstore",
 +              auxType:        auxSymOff,
 +              argLen:         3,
 +              faultOnNilArg0: true,
 +              symEffect:      SymWrite,
 +              asm:            arm64.AMOVH,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 939524095},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO
 +                              {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
 +                      },
 +              },
 +      },
 +      {
 +              name:           "MOVWstore",
 +              auxType:        auxSymOff,
 +              argLen:         3,
 +              faultOnNilArg0: true,
 +              symEffect:      SymWrite,
 +              asm:            arm64.AMOVW,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 939524095},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO
 +                              {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
 +                      },
 +              },
 +      },
 +      {
 +              name:           "MOVDstore",
 +              auxType:        auxSymOff,
 +              argLen:         3,
 +              faultOnNilArg0: true,
 +              symEffect:      SymWrite,
 +              asm:            arm64.AMOVD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 939524095},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO
 +                              {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
 +                      },
 +              },
 +      },
 +      {
 +              name:           "FMOVSstore",
 +              auxType:        auxSymOff,
 +              argLen:         3,
 +              faultOnNilArg0: true,
 +              symEffect:      SymWrite,
 +              asm:            arm64.AFMOVS,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
 +                              {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +              },
 +      },
 +      {
 +              name:           "FMOVDstore",
 +              auxType:        auxSymOff,
 +              argLen:         3,
 +              faultOnNilArg0: true,
 +              symEffect:      SymWrite,
 +              asm:            arm64.AFMOVD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
 +                              {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +              },
 +      },
 +      {
 +              name:           "STP",
 +              auxType:        auxSymOff,
 +              argLen:         4,
 +              faultOnNilArg0: true,
 +              symEffect:      SymWrite,
 +              asm:            arm64.ASTP,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 939524095},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO
 +                              {2, 939524095},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO
 +                              {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
 +                      },
 +              },
 +      },
 +      {
 +              name:           "STPW",
 +              auxType:        auxSymOff,
 +              argLen:         4,
 +              faultOnNilArg0: true,
 +              symEffect:      SymWrite,
 +              asm:            arm64.ASTPW,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 939524095},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO
 +                              {2, 939524095},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO
 +                              {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
 +                      },
 +              },
 +      },
 +      {
 +              name:           "FSTPD",
 +              auxType:        auxSymOff,
 +              argLen:         4,
 +              faultOnNilArg0: true,
 +              symEffect:      SymWrite,
 +              asm:            arm64.AFSTPD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
 +                              {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                              {2, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +              },
 +      },
 +      {
 +              name:           "FSTPS",
 +              auxType:        auxSymOff,
 +              argLen:         4,
 +              faultOnNilArg0: true,
 +              symEffect:      SymWrite,
 +              asm:            arm64.AFSTPS,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
 +                              {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                              {2, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +              },
 +      },
 +      {
 +              name:   "MOVBstoreidx",
 +              argLen: 4,
 +              asm:    arm64.AMOVB,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 939524095},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO
 +                              {2, 939524095},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO
 +                              {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
 +                      },
 +              },
 +      },
 +      {
 +              name:   "MOVHstoreidx",
 +              argLen: 4,
 +              asm:    arm64.AMOVH,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 939524095},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO
 +                              {2, 939524095},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO
 +                              {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
 +                      },
 +              },
 +      },
 +      {
 +              name:   "MOVWstoreidx",
 +              argLen: 4,
 +              asm:    arm64.AMOVW,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 939524095},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO
 +                              {2, 939524095},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO
 +                              {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
 +                      },
 +              },
 +      },
 +      {
 +              name:   "MOVDstoreidx",
 +              argLen: 4,
 +              asm:    arm64.AMOVD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 939524095},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO
 +                              {2, 939524095},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO
 +                              {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
 +                      },
 +              },
 +      },
 +      {
 +              name:   "FMOVSstoreidx",
 +              argLen: 4,
 +              asm:    arm64.AFMOVS,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 402653183},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
 +                              {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
 +                              {2, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +              },
 +      },
 +      {
 +              name:   "FMOVDstoreidx",
 +              argLen: 4,
 +              asm:    arm64.AFMOVD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 402653183},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
 +                              {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
 +                              {2, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +              },
 +      },
 +      {
 +              name:   "MOVHstoreidx2",
 +              argLen: 4,
 +              asm:    arm64.AMOVH,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 939524095},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO
 +                              {2, 939524095},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO
 +                              {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
 +                      },
 +              },
 +      },
 +      {
 +              name:   "MOVWstoreidx4",
 +              argLen: 4,
 +              asm:    arm64.AMOVW,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 939524095},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO
 +                              {2, 939524095},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO
 +                              {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
 +                      },
 +              },
 +      },
 +      {
 +              name:   "MOVDstoreidx8",
 +              argLen: 4,
 +              asm:    arm64.AMOVD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 939524095},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO
 +                              {2, 939524095},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO
 +                              {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
 +                      },
 +              },
 +      },
 +      {
 +              name:   "FMOVSstoreidx4",
 +              argLen: 4,
 +              asm:    arm64.AFMOVS,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 402653183},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
 +                              {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
 +                              {2, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +              },
 +      },
 +      {
 +              name:   "FMOVDstoreidx8",
 +              argLen: 4,
 +              asm:    arm64.AFMOVD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 402653183},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
 +                              {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
 +                              {2, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +              },
 +      },
 +      {
 +              name:   "FMOVDgpfp",
 +              argLen: 1,
 +              asm:    arm64.AFMOVD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +              },
 +      },
 +      {
 +              name:   "FMOVDfpgp",
 +              argLen: 1,
 +              asm:    arm64.AFMOVD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 +                      },
 +              },
 +      },
 +      {
 +              name:   "FMOVSgpfp",
 +              argLen: 1,
 +              asm:    arm64.AFMOVS,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +              },
 +      },
 +      {
 +              name:   "FMOVSfpgp",
 +              argLen: 1,
 +              asm:    arm64.AFMOVS,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 +                      },
 +              },
 +      },
 +      {
 +              name:   "MOVBreg",
 +              argLen: 1,
 +              asm:    arm64.AMOVB,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 +                      },
 +              },
 +      },
 +      {
 +              name:   "MOVBUreg",
 +              argLen: 1,
 +              asm:    arm64.AMOVBU,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 +                      },
 +              },
 +      },
 +      {
 +              name:   "MOVHreg",
 +              argLen: 1,
 +              asm:    arm64.AMOVH,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 +                      },
 +              },
 +      },
 +      {
 +              name:   "MOVHUreg",
 +              argLen: 1,
 +              asm:    arm64.AMOVHU,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 +                      },
 +              },
 +      },
 +      {
 +              name:   "MOVWreg",
 +              argLen: 1,
 +              asm:    arm64.AMOVW,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 +                      },
 +              },
 +      },
 +      {
 +              name:   "MOVWUreg",
 +              argLen: 1,
 +              asm:    arm64.AMOVWU,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 +                      },
 +              },
 +      },
 +      {
 +              name:   "MOVDreg",
 +              argLen: 1,
 +              asm:    arm64.AMOVD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 +                      },
 +              },
 +      },
 +      {
 +              name:         "MOVDnop",
 +              argLen:       1,
 +              resultInArg0: true,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 +                      },
 +              },
 +      },
 +      {
 +              name:   "SCVTFWS",
 +              argLen: 1,
 +              asm:    arm64.ASCVTFWS,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +              },
 +      },
 +      {
 +              name:   "SCVTFWD",
 +              argLen: 1,
 +              asm:    arm64.ASCVTFWD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +              },
 +      },
 +      {
 +              name:   "UCVTFWS",
 +              argLen: 1,
 +              asm:    arm64.AUCVTFWS,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +              },
 +      },
 +      {
 +              name:   "UCVTFWD",
 +              argLen: 1,
 +              asm:    arm64.AUCVTFWD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +              },
 +      },
 +      {
 +              name:   "SCVTFS",
 +              argLen: 1,
 +              asm:    arm64.ASCVTFS,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +              },
 +      },
 +      {
 +              name:   "SCVTFD",
 +              argLen: 1,
 +              asm:    arm64.ASCVTFD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +              },
 +      },
 +      {
 +              name:   "UCVTFS",
 +              argLen: 1,
 +              asm:    arm64.AUCVTFS,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +              },
 +      },
 +      {
 +              name:   "UCVTFD",
 +              argLen: 1,
 +              asm:    arm64.AUCVTFD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +              },
 +      },
 +      {
 +              name:   "FCVTZSSW",
 +              argLen: 1,
 +              asm:    arm64.AFCVTZSSW,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 +                      },
 +              },
 +      },
 +      {
 +              name:   "FCVTZSDW",
 +              argLen: 1,
 +              asm:    arm64.AFCVTZSDW,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 +                      },
 +              },
 +      },
 +      {
 +              name:   "FCVTZUSW",
 +              argLen: 1,
 +              asm:    arm64.AFCVTZUSW,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 +                      },
 +              },
 +      },
 +      {
 +              name:   "FCVTZUDW",
 +              argLen: 1,
 +              asm:    arm64.AFCVTZUDW,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 +                      },
 +              },
 +      },
 +      {
 +              name:   "FCVTZSS",
 +              argLen: 1,
 +              asm:    arm64.AFCVTZSS,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 +                      },
 +              },
 +      },
 +      {
 +              name:   "FCVTZSD",
 +              argLen: 1,
 +              asm:    arm64.AFCVTZSD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 +                      },
 +              },
 +      },
 +      {
 +              name:   "FCVTZUS",
 +              argLen: 1,
 +              asm:    arm64.AFCVTZUS,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 +                      },
 +              },
 +      },
 +      {
 +              name:   "FCVTZUD",
 +              argLen: 1,
 +              asm:    arm64.AFCVTZUD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 +                      },
 +              },
 +      },
 +      {
 +              name:   "FCVTSD",
 +              argLen: 1,
 +              asm:    arm64.AFCVTSD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +              },
 +      },
 +      {
 +              name:   "FCVTDS",
 +              argLen: 1,
 +              asm:    arm64.AFCVTDS,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +              },
 +      },
 +      {
 +              name:   "FRINTAD",
 +              argLen: 1,
 +              asm:    arm64.AFRINTAD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +              },
 +      },
 +      {
 +              name:   "FRINTMD",
 +              argLen: 1,
 +              asm:    arm64.AFRINTMD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +              },
 +      },
 +      {
 +              name:   "FRINTND",
 +              argLen: 1,
 +              asm:    arm64.AFRINTND,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +              },
 +      },
 +      {
 +              name:   "FRINTPD",
 +              argLen: 1,
 +              asm:    arm64.AFRINTPD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +              },
 +      },
 +      {
 +              name:   "FRINTZD",
 +              argLen: 1,
 +              asm:    arm64.AFRINTZD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +              },
 +      },
 +      {
 +              name:    "CSEL",
 +              auxType: auxCCop,
 +              argLen:  3,
 +              asm:     arm64.ACSEL,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 +                              {1, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 +                      },
 +              },
 +      },
 +      {
 +              name:    "CSEL0",
 +              auxType: auxCCop,
 +              argLen:  2,
 +              asm:     arm64.ACSEL,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 +                      },
 +              },
 +      },
 +      {
 +              name:    "CSINC",
 +              auxType: auxCCop,
 +              argLen:  3,
 +              asm:     arm64.ACSINC,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 +                              {1, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 +                      },
 +              },
 +      },
 +      {
 +              name:    "CSINV",
 +              auxType: auxCCop,
 +              argLen:  3,
 +              asm:     arm64.ACSINV,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 +                              {1, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 +                      },
 +              },
 +      },
 +      {
 +              name:    "CSNEG",
 +              auxType: auxCCop,
 +              argLen:  3,
 +              asm:     arm64.ACSNEG,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 +                              {1, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 +                      },
 +              },
 +      },
 +      {
 +              name:    "CSETM",
 +              auxType: auxCCop,
 +              argLen:  1,
 +              asm:     arm64.ACSETM,
 +              reg: regInfo{
 +                      outputs: []outputInfo{
 +                              {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 +                      },
 +              },
 +      },
 +      {
 +              name:    "CCMP",
 +              auxType: auxARM64ConditionalParams,
 +              argLen:  3,
 +              asm:     arm64.ACCMP,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
 +                              {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
 +                      },
 +              },
 +      },
 +      {
 +              name:    "CCMN",
 +              auxType: auxARM64ConditionalParams,
 +              argLen:  3,
 +              asm:     arm64.ACCMN,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
 +                              {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
 +                      },
 +              },
 +      },
 +      {
 +              name:    "CCMPconst",
 +              auxType: auxARM64ConditionalParams,
 +              argLen:  2,
 +              asm:     arm64.ACCMP,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
 +                      },
 +              },
 +      },
 +      {
 +              name:    "CCMNconst",
 +              auxType: auxARM64ConditionalParams,
 +              argLen:  2,
 +              asm:     arm64.ACCMN,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
 +                      },
 +              },
 +      },
 +      {
 +              name:    "CCMPW",
 +              auxType: auxARM64ConditionalParams,
 +              argLen:  3,
 +              asm:     arm64.ACCMPW,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
 +                              {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
 +                      },
 +              },
 +      },
 +      {
 +              name:    "CCMNW",
 +              auxType: auxARM64ConditionalParams,
 +              argLen:  3,
 +              asm:     arm64.ACCMNW,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
 +                              {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
 +                      },
 +              },
 +      },
 +      {
 +              name:    "CCMPWconst",
 +              auxType: auxARM64ConditionalParams,
 +              argLen:  2,
 +              asm:     arm64.ACCMPW,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
 +                      },
 +              },
 +      },
 +      {
 +              name:    "CCMNWconst",
 +              auxType: auxARM64ConditionalParams,
 +              argLen:  2,
 +              asm:     arm64.ACCMNW,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
 +                      },
 +              },
 +      },
 +      {
 +              name:         "CALLstatic",
 +              auxType:      auxCallOff,
 +              argLen:       -1,
 +              clobberFlags: true,
 +              call:         true,
 +              reg: regInfo{
 +                      clobbers: 9223372035109945343, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +              },
 +      },
 +      {
 +              name:         "CALLtail",
 +              auxType:      auxCallOff,
 +              argLen:       -1,
 +              clobberFlags: true,
 +              call:         true,
 +              tailCall:     true,
 +              reg: regInfo{
 +                      clobbers: 9223372035109945343, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +              },
 +      },
 +      {
 +              name:         "CALLclosure",
 +              auxType:      auxCallOff,
 +              argLen:       -1,
 +              clobberFlags: true,
 +              call:         true,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 33554432},   // R26
 +                              {0, 1409286143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 SP
 +                      },
 +                      clobbers: 9223372035109945343, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +              },
 +      },
 +      {
 +              name:         "CALLinter",
 +              auxType:      auxCallOff,
 +              argLen:       -1,
 +              clobberFlags: true,
 +              call:         true,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 +                      },
 +                      clobbers: 9223372035109945343, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +              },
 +      },
 +      {
 +              name:           "LoweredNilCheck",
 +              argLen:         2,
 +              nilCheck:       true,
 +              faultOnNilArg0: true,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
 +                      },
 +              },
 +      },
 +      {
 +              name:   "Equal",
 +              argLen: 1,
 +              reg: regInfo{
 +                      outputs: []outputInfo{
 +                              {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 +                      },
 +              },
 +      },
 +      {
 +              name:   "NotEqual",
 +              argLen: 1,
 +              reg: regInfo{
 +                      outputs: []outputInfo{
 +                              {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 +                      },
 +              },
 +      },
 +      {
 +              name:   "LessThan",
 +              argLen: 1,
 +              reg: regInfo{
 +                      outputs: []outputInfo{
 +                              {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 +                      },
 +              },
 +      },
 +      {
 +              name:   "LessEqual",
 +              argLen: 1,
 +              reg: regInfo{
 +                      outputs: []outputInfo{
 +                              {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 +                      },
 +              },
 +      },
 +      {
 +              name:   "GreaterThan",
 +              argLen: 1,
 +              reg: regInfo{
 +                      outputs: []outputInfo{
 +                              {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 +                      },
 +              },
 +      },
 +      {
 +              name:   "GreaterEqual",
 +              argLen: 1,
 +              reg: regInfo{
 +                      outputs: []outputInfo{
 +                              {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 +                      },
 +              },
 +      },
 +      {
 +              name:   "LessThanU",
 +              argLen: 1,
 +              reg: regInfo{
 +                      outputs: []outputInfo{
 +                              {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 +                      },
 +              },
 +      },
 +      {
 +              name:   "LessEqualU",
 +              argLen: 1,
 +              reg: regInfo{
 +                      outputs: []outputInfo{
 +                              {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 +                      },
 +              },
 +      },
 +      {
 +              name:   "GreaterThanU",
 +              argLen: 1,
 +              reg: regInfo{
 +                      outputs: []outputInfo{
 +                              {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 +                      },
 +              },
 +      },
 +      {
 +              name:   "GreaterEqualU",
 +              argLen: 1,
 +              reg: regInfo{
 +                      outputs: []outputInfo{
 +                              {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 +                      },
 +              },
 +      },
 +      {
 +              name:   "LessThanF",
 +              argLen: 1,
 +              reg: regInfo{
 +                      outputs: []outputInfo{
 +                              {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 +                      },
 +              },
 +      },
 +      {
 +              name:   "LessEqualF",
 +              argLen: 1,
 +              reg: regInfo{
 +                      outputs: []outputInfo{
 +                              {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 +                      },
 +              },
 +      },
 +      {
 +              name:   "GreaterThanF",
 +              argLen: 1,
 +              reg: regInfo{
 +                      outputs: []outputInfo{
 +                              {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 +                      },
 +              },
 +      },
 +      {
 +              name:   "GreaterEqualF",
 +              argLen: 1,
 +              reg: regInfo{
 +                      outputs: []outputInfo{
 +                              {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 +                      },
 +              },
 +      },
 +      {
 +              name:   "NotLessThanF",
 +              argLen: 1,
 +              reg: regInfo{
 +                      outputs: []outputInfo{
 +                              {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 +                      },
 +              },
 +      },
 +      {
 +              name:   "NotLessEqualF",
 +              argLen: 1,
 +              reg: regInfo{
 +                      outputs: []outputInfo{
 +                              {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 +                      },
 +              },
 +      },
 +      {
 +              name:   "NotGreaterThanF",
 +              argLen: 1,
 +              reg: regInfo{
 +                      outputs: []outputInfo{
 +                              {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 +                      },
 +              },
 +      },
 +      {
 +              name:   "NotGreaterEqualF",
 +              argLen: 1,
 +              reg: regInfo{
 +                      outputs: []outputInfo{
 +                              {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 +                      },
 +              },
 +      },
 +      {
 +              name:   "LessThanNoov",
 +              argLen: 1,
 +              reg: regInfo{
 +                      outputs: []outputInfo{
 +                              {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 +                      },
 +              },
 +      },
 +      {
 +              name:   "GreaterEqualNoov",
 +              argLen: 1,
 +              reg: regInfo{
 +                      outputs: []outputInfo{
 +                              {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 +                      },
 +              },
 +      },
 +      {
 +              name:           "LoweredZero",
 +              auxType:        auxInt64,
 +              argLen:         2,
 +              faultOnNilArg0: true,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 +                      },
 +              },
 +      },
 +      {
 +              name:           "LoweredZeroLoop",
 +              auxType:        auxInt64,
 +              argLen:         2,
 +              needIntTemp:    true,
 +              faultOnNilArg0: true,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 +                      },
 +                      clobbersArg0: true,
 +              },
 +      },
 +      {
 +              name:           "LoweredMove",
 +              auxType:        auxInt64,
 +              argLen:         3,
 +              faultOnNilArg0: true,
 +              faultOnNilArg1: true,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 318767103}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R26 R30
 +                              {1, 318767103}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R26 R30
 +                      },
 +                      clobbers: 422212481843200, // R25 F16 F17
 +              },
 +      },
 +      {
 +              name:           "LoweredMoveLoop",
 +              auxType:        auxInt64,
 +              argLen:         3,
 +              faultOnNilArg0: true,
 +              faultOnNilArg1: true,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 310378495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R26 R30
 +                              {1, 310378495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R26 R30
 +                      },
 +                      clobbers:     422212490231808, // R24 R25 F16 F17
 +                      clobbersArg0: true,
 +                      clobbersArg1: true,
 +              },
 +      },
 +      {
 +              name:      "LoweredGetClosurePtr",
 +              argLen:    0,
 +              zeroWidth: true,
 +              reg: regInfo{
 +                      outputs: []outputInfo{
 +                              {0, 33554432}, // R26
 +                      },
 +              },
 +      },
 +      {
 +              name:              "LoweredGetCallerSP",
 +              argLen:            1,
 +              rematerializeable: true,
 +              reg: regInfo{
 +                      outputs: []outputInfo{
 +                              {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 +                      },
 +              },
 +      },
 +      {
 +              name:              "LoweredGetCallerPC",
 +              argLen:            0,
 +              rematerializeable: true,
 +              reg: regInfo{
 +                      outputs: []outputInfo{
 +                              {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 +                      },
 +              },
 +      },
 +      {
 +              name:    "FlagConstant",
 +              auxType: auxFlagConstant,
 +              argLen:  0,
 +              reg:     regInfo{},
 +      },
 +      {
 +              name:   "InvertFlags",
 +              argLen: 1,
 +              reg:    regInfo{},
 +      },
 +      {
 +              name:           "LDAR",
 +              argLen:         2,
 +              faultOnNilArg0: true,
 +              asm:            arm64.ALDAR,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 +                      },
 +              },
 +      },
 +      {
 +              name:           "LDARB",
 +              argLen:         2,
 +              faultOnNilArg0: true,
 +              asm:            arm64.ALDARB,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 +                      },
 +              },
 +      },
 +      {
 +              name:           "LDARW",
 +              argLen:         2,
 +              faultOnNilArg0: true,
 +              asm:            arm64.ALDARW,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 +                      },
 +              },
 +      },
 +      {
 +              name:           "STLRB",
 +              argLen:         3,
 +              faultOnNilArg0: true,
 +              hasSideEffects: true,
 +              asm:            arm64.ASTLRB,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 939524095},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO
 +                              {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
 +                      },
 +              },
 +      },
 +      {
 +              name:           "STLR",
 +              argLen:         3,
 +              faultOnNilArg0: true,
 +              hasSideEffects: true,
 +              asm:            arm64.ASTLR,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 939524095},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO
 +                              {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
 +                      },
 +              },
 +      },
 +      {
 +              name:           "STLRW",
 +              argLen:         3,
 +              faultOnNilArg0: true,
 +              hasSideEffects: true,
 +              asm:            arm64.ASTLRW,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 939524095},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO
 +                              {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
 +                      },
 +              },
 +      },
 +      {
 +              name:            "LoweredAtomicExchange64",
 +              argLen:          3,
 +              resultNotInArgs: true,
 +              faultOnNilArg0:  true,
 +              hasSideEffects:  true,
 +              unsafePoint:     true,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 939524095},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO
 +                              {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 +                      },
 +              },
 +      },
 +      {
 +              name:            "LoweredAtomicExchange32",
 +              argLen:          3,
 +              resultNotInArgs: true,
 +              faultOnNilArg0:  true,
 +              hasSideEffects:  true,
 +              unsafePoint:     true,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 939524095},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO
 +                              {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 +                      },
 +              },
 +      },
 +      {
 +              name:            "LoweredAtomicExchange8",
 +              argLen:          3,
 +              resultNotInArgs: true,
 +              faultOnNilArg0:  true,
 +              hasSideEffects:  true,
 +              unsafePoint:     true,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 939524095},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO
 +                              {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 +                      },
 +              },
 +      },
 +      {
 +              name:            "LoweredAtomicExchange64Variant",
 +              argLen:          3,
 +              resultNotInArgs: true,
 +              faultOnNilArg0:  true,
 +              hasSideEffects:  true,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 939524095},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO
 +                              {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 +                      },
 +              },
 +      },
 +      {
 +              name:            "LoweredAtomicExchange32Variant",
 +              argLen:          3,
 +              resultNotInArgs: true,
 +              faultOnNilArg0:  true,
 +              hasSideEffects:  true,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 939524095},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO
 +                              {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 +                      },
 +              },
 +      },
 +      {
 +              name:            "LoweredAtomicExchange8Variant",
 +              argLen:          3,
 +              resultNotInArgs: true,
 +              faultOnNilArg0:  true,
 +              hasSideEffects:  true,
 +              unsafePoint:     true,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 939524095},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO
 +                              {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 +                      },
 +              },
 +      },
 +      {
 +              name:            "LoweredAtomicAdd64",
 +              argLen:          3,
 +              resultNotInArgs: true,
 +              faultOnNilArg0:  true,
 +              hasSideEffects:  true,
 +              unsafePoint:     true,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 939524095},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO
 +                              {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 +                      },
 +              },
 +      },
 +      {
 +              name:            "LoweredAtomicAdd32",
 +              argLen:          3,
 +              resultNotInArgs: true,
 +              faultOnNilArg0:  true,
 +              hasSideEffects:  true,
 +              unsafePoint:     true,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 939524095},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO
 +                              {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 +                      },
 +              },
 +      },
 +      {
 +              name:            "LoweredAtomicAdd64Variant",
 +              argLen:          3,
 +              resultNotInArgs: true,
 +              faultOnNilArg0:  true,
 +              hasSideEffects:  true,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 939524095},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO
 +                              {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 +                      },
 +              },
 +      },
 +      {
 +              name:            "LoweredAtomicAdd32Variant",
 +              argLen:          3,
 +              resultNotInArgs: true,
 +              faultOnNilArg0:  true,
 +              hasSideEffects:  true,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 939524095},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO
 +                              {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 +                      },
 +              },
 +      },
 +      {
 +              name:            "LoweredAtomicCas64",
 +              argLen:          4,
 +              resultNotInArgs: true,
 +              clobberFlags:    true,
 +              faultOnNilArg0:  true,
 +              hasSideEffects:  true,
 +              unsafePoint:     true,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 939524095},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO
 +                              {2, 939524095},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO
 +                              {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 +                      },
 +              },
 +      },
 +      {
 +              name:            "LoweredAtomicCas32",
 +              argLen:          4,
 +              resultNotInArgs: true,
 +              clobberFlags:    true,
 +              faultOnNilArg0:  true,
 +              hasSideEffects:  true,
 +              unsafePoint:     true,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 939524095},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO
 +                              {2, 939524095},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO
 +                              {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 +                      },
 +              },
 +      },
 +      {
 +              name:            "LoweredAtomicCas64Variant",
 +              argLen:          4,
 +              resultNotInArgs: true,
 +              clobberFlags:    true,
 +              faultOnNilArg0:  true,
 +              hasSideEffects:  true,
 +              unsafePoint:     true,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 939524095},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO
 +                              {2, 939524095},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO
 +                              {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 +                      },
 +              },
 +      },
 +      {
 +              name:            "LoweredAtomicCas32Variant",
 +              argLen:          4,
 +              resultNotInArgs: true,
 +              clobberFlags:    true,
 +              faultOnNilArg0:  true,
 +              hasSideEffects:  true,
 +              unsafePoint:     true,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 939524095},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO
 +                              {2, 939524095},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO
 +                              {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 +                      },
 +              },
 +      },
 +      {
 +              name:            "LoweredAtomicAnd8",
 +              argLen:          3,
 +              resultNotInArgs: true,
 +              needIntTemp:     true,
 +              faultOnNilArg0:  true,
 +              hasSideEffects:  true,
 +              unsafePoint:     true,
 +              asm:             arm64.AAND,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 939524095},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO
 +                              {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 +                      },
 +              },
 +      },
 +      {
 +              name:            "LoweredAtomicOr8",
 +              argLen:          3,
 +              resultNotInArgs: true,
 +              needIntTemp:     true,
 +              faultOnNilArg0:  true,
 +              hasSideEffects:  true,
 +              unsafePoint:     true,
 +              asm:             arm64.AORR,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 939524095},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO
 +                              {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 +                      },
 +              },
 +      },
 +      {
 +              name:            "LoweredAtomicAnd64",
 +              argLen:          3,
 +              resultNotInArgs: true,
 +              needIntTemp:     true,
 +              faultOnNilArg0:  true,
 +              hasSideEffects:  true,
 +              unsafePoint:     true,
 +              asm:             arm64.AAND,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 939524095},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO
 +                              {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 +                      },
 +              },
 +      },
 +      {
 +              name:            "LoweredAtomicOr64",
 +              argLen:          3,
 +              resultNotInArgs: true,
 +              needIntTemp:     true,
 +              faultOnNilArg0:  true,
 +              hasSideEffects:  true,
 +              unsafePoint:     true,
 +              asm:             arm64.AORR,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 939524095},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO
 +                              {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 +                      },
 +              },
 +      },
 +      {
 +              name:            "LoweredAtomicAnd32",
 +              argLen:          3,
 +              resultNotInArgs: true,
 +              needIntTemp:     true,
 +              faultOnNilArg0:  true,
 +              hasSideEffects:  true,
 +              unsafePoint:     true,
 +              asm:             arm64.AAND,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 939524095},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO
 +                              {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 +                      },
 +              },
 +      },
 +      {
 +              name:            "LoweredAtomicOr32",
 +              argLen:          3,
 +              resultNotInArgs: true,
 +              needIntTemp:     true,
 +              faultOnNilArg0:  true,
 +              hasSideEffects:  true,
 +              unsafePoint:     true,
 +              asm:             arm64.AORR,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 939524095},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO
 +                              {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 +                      },
 +              },
 +      },
 +      {
 +              name:            "LoweredAtomicAnd8Variant",
 +              argLen:          3,
 +              resultNotInArgs: true,
 +              faultOnNilArg0:  true,
 +              hasSideEffects:  true,
 +              unsafePoint:     true,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 939524095},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO
 +                              {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 +                      },
 +              },
 +      },
 +      {
 +              name:            "LoweredAtomicOr8Variant",
 +              argLen:          3,
 +              resultNotInArgs: true,
 +              faultOnNilArg0:  true,
 +              hasSideEffects:  true,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 939524095},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO
 +                              {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 +                      },
 +              },
 +      },
 +      {
 +              name:            "LoweredAtomicAnd64Variant",
 +              argLen:          3,
 +              resultNotInArgs: true,
 +              faultOnNilArg0:  true,
 +              hasSideEffects:  true,
 +              unsafePoint:     true,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 939524095},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO
 +                              {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 +                      },
 +              },
 +      },
 +      {
 +              name:            "LoweredAtomicOr64Variant",
 +              argLen:          3,
 +              resultNotInArgs: true,
 +              faultOnNilArg0:  true,
 +              hasSideEffects:  true,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 939524095},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO
 +                              {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 +                      },
 +              },
 +      },
 +      {
 +              name:            "LoweredAtomicAnd32Variant",
 +              argLen:          3,
 +              resultNotInArgs: true,
 +              faultOnNilArg0:  true,
 +              hasSideEffects:  true,
 +              unsafePoint:     true,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 939524095},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO
 +                              {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 +                      },
 +              },
 +      },
 +      {
 +              name:            "LoweredAtomicOr32Variant",
 +              argLen:          3,
 +              resultNotInArgs: true,
 +              faultOnNilArg0:  true,
 +              hasSideEffects:  true,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 939524095},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO
 +                              {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
 +                      },
 +              },
 +      },
 +      {
 +              name:         "LoweredWB",
 +              auxType:      auxInt64,
 +              argLen:       1,
 +              clobberFlags: true,
 +              reg: regInfo{
 +                      clobbers: 9223372034975924224, // R16 R17 R30 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      outputs: []outputInfo{
 +                              {0, 16777216}, // R25
 +                      },
 +              },
 +      },
 +      {
 +              name:    "LoweredPanicBoundsRR",
 +              auxType: auxInt64,
 +              argLen:  3,
 +              call:    true,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
 +                              {1, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
 +                      },
 +              },
 +      },
 +      {
 +              name:    "LoweredPanicBoundsRC",
 +              auxType: auxPanicBoundsC,
 +              argLen:  2,
 +              call:    true,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
 +                      },
 +              },
 +      },
 +      {
 +              name:    "LoweredPanicBoundsCR",
 +              auxType: auxPanicBoundsC,
 +              argLen:  2,
 +              call:    true,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
 +                      },
 +              },
 +      },
 +      {
 +              name:    "LoweredPanicBoundsCC",
 +              auxType: auxPanicBoundsCC,
 +              argLen:  1,
 +              call:    true,
 +              reg:     regInfo{},
 +      },
 +      {
 +              name:           "PRFM",
 +              auxType:        auxInt64,
 +              argLen:         2,
 +              hasSideEffects: true,
 +              asm:            arm64.APRFM,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
 +                      },
 +              },
 +      },
 +      {
 +              name:           "DMB",
 +              auxType:        auxInt64,
 +              argLen:         1,
 +              hasSideEffects: true,
 +              asm:            arm64.ADMB,
 +              reg:            regInfo{},
 +      },
 +      {
 +              name:      "ZERO",
 +              argLen:    0,
 +              zeroWidth: true,
 +              fixedReg:  true,
 +              reg:       regInfo{},
 +      },
 +
 +      {
 +              name:   "NEGV",
 +              argLen: 1,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
 +                      },
 +              },
 +      },
 +      {
 +              name:   "NEGF",
 +              argLen: 1,
 +              asm:    loong64.ANEGF,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +              },
 +      },
 +      {
 +              name:   "NEGD",
 +              argLen: 1,
 +              asm:    loong64.ANEGD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +              },
 +      },
 +      {
 +              name:   "SQRTD",
 +              argLen: 1,
 +              asm:    loong64.ASQRTD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +              },
 +      },
 +      {
 +              name:   "SQRTF",
 +              argLen: 1,
 +              asm:    loong64.ASQRTF,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +              },
 +      },
 +      {
 +              name:   "ABSD",
 +              argLen: 1,
 +              asm:    loong64.AABSD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +              },
 +      },
 +      {
 +              name:   "CLZW",
 +              argLen: 1,
 +              asm:    loong64.ACLZW,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
 +                      },
 +              },
 +      },
 +      {
 +              name:   "CLZV",
 +              argLen: 1,
 +              asm:    loong64.ACLZV,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
 +                      },
 +              },
 +      },
 +      {
 +              name:   "CTZW",
 +              argLen: 1,
 +              asm:    loong64.ACTZW,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
 +                      },
 +              },
 +      },
 +      {
 +              name:   "CTZV",
 +              argLen: 1,
 +              asm:    loong64.ACTZV,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
 +                      },
 +              },
 +      },
 +      {
 +              name:   "REVB2H",
 +              argLen: 1,
 +              asm:    loong64.AREVB2H,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
 +                      },
 +              },
 +      },
 +      {
 +              name:   "REVB2W",
 +              argLen: 1,
 +              asm:    loong64.AREVB2W,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
 +                      },
 +              },
 +      },
 +      {
 +              name:   "REVB4H",
 +              argLen: 1,
 +              asm:    loong64.AREVB4H,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
 +                      },
 +              },
 +      },
 +      {
 +              name:   "REVBV",
 +              argLen: 1,
 +              asm:    loong64.AREVBV,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
 +                      },
 +              },
 +      },
 +      {
 +              name:   "BITREV4B",
 +              argLen: 1,
 +              asm:    loong64.ABITREV4B,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
 +                      },
 +              },
 +      },
 +      {
 +              name:   "BITREVW",
 +              argLen: 1,
 +              asm:    loong64.ABITREVW,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
 +                      },
 +              },
 +      },
 +      {
 +              name:   "BITREVV",
 +              argLen: 1,
 +              asm:    loong64.ABITREVV,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
 +                      },
 +              },
 +      },
 +      {
 +              name:   "VPCNT64",
 +              argLen: 1,
 +              asm:    loong64.AVPCNTV,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +              },
 +      },
 +      {
 +              name:   "VPCNT32",
 +              argLen: 1,
 +              asm:    loong64.AVPCNTW,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +              },
 +      },
 +      {
 +              name:   "VPCNT16",
 +              argLen: 1,
 +              asm:    loong64.AVPCNTH,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +              },
 +      },
 +      {
 +              name:        "ADDV",
 +              argLen:      2,
 +              commutative: true,
 +              asm:         loong64.AADDVU,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
 +                              {1, 1073741817}, // ZERO R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
 +                      },
 +              },
 +      },
 +      {
 +              name:    "ADDVconst",
 +              auxType: auxInt64,
 +              argLen:  1,
 +              asm:     loong64.AADDVU,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1073741820}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
 +                      },
 +              },
 +      },
 +      {
 +              name:    "ADDV16const",
 +              auxType: auxInt64,
 +              argLen:  1,
 +              asm:     loong64.AADDV16,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1073741820}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
 +                      },
 +              },
 +      },
 +      {
 +              name:   "SUBV",
 +              argLen: 2,
 +              asm:    loong64.ASUBVU,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
 +                              {1, 1073741817}, // ZERO R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
 +                      },
 +              },
 +      },
 +      {
 +              name:    "SUBVconst",
 +              auxType: auxInt64,
 +              argLen:  1,
 +              asm:     loong64.ASUBVU,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
 +                      },
 +              },
 +      },
 +      {
 +              name:        "MULV",
 +              argLen:      2,
 +              commutative: true,
 +              asm:         loong64.AMULV,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
 +                              {1, 1073741817}, // ZERO R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
 +                      },
 +              },
 +      },
 +      {
 +              name:        "MULHV",
 +              argLen:      2,
 +              commutative: true,
 +              asm:         loong64.AMULHV,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
 +                              {1, 1073741817}, // ZERO R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
 +                      },
 +              },
 +      },
 +      {
 +              name:        "MULHVU",
 +              argLen:      2,
 +              commutative: true,
 +              asm:         loong64.AMULHVU,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
 +                              {1, 1073741817}, // ZERO R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
 +                      },
 +              },
 +      },
 +      {
 +              name:        "MULH",
 +              argLen:      2,
 +              commutative: true,
 +              asm:         loong64.AMULH,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
 +                              {1, 1073741817}, // ZERO R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
 +                      },
 +              },
 +      },
 +      {
 +              name:        "MULHU",
 +              argLen:      2,
 +              commutative: true,
 +              asm:         loong64.AMULHU,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
 +                              {1, 1073741817}, // ZERO R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
 +                      },
 +              },
 +      },
 +      {
 +              name:   "DIVV",
 +              argLen: 2,
 +              asm:    loong64.ADIVV,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
 +                              {1, 1073741817}, // ZERO R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
 +                      },
 +              },
 +      },
 +      {
 +              name:   "DIVVU",
 +              argLen: 2,
 +              asm:    loong64.ADIVVU,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
 +                              {1, 1073741817}, // ZERO R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
 +                      },
 +              },
 +      },
 +      {
 +              name:   "REMV",
 +              argLen: 2,
 +              asm:    loong64.AREMV,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
 +                              {1, 1073741817}, // ZERO R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
 +                      },
 +              },
 +      },
 +      {
 +              name:   "REMVU",
 +              argLen: 2,
 +              asm:    loong64.AREMVU,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
 +                              {1, 1073741817}, // ZERO R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
 +                      },
 +              },
 +      },
 +      {
 +              name:        "ADDF",
 +              argLen:      2,
 +              commutative: true,
 +              asm:         loong64.AADDF,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                              {1, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +              },
 +      },
 +      {
 +              name:        "ADDD",
 +              argLen:      2,
 +              commutative: true,
 +              asm:         loong64.AADDD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                              {1, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +              },
 +      },
 +      {
 +              name:   "SUBF",
 +              argLen: 2,
 +              asm:    loong64.ASUBF,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                              {1, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +              },
 +      },
 +      {
 +              name:   "SUBD",
 +              argLen: 2,
 +              asm:    loong64.ASUBD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                              {1, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +              },
 +      },
 +      {
 +              name:        "MULF",
 +              argLen:      2,
 +              commutative: true,
 +              asm:         loong64.AMULF,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                              {1, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +              },
 +      },
 +      {
 +              name:        "MULD",
 +              argLen:      2,
 +              commutative: true,
 +              asm:         loong64.AMULD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                              {1, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +              },
 +      },
 +      {
 +              name:   "DIVF",
 +              argLen: 2,
 +              asm:    loong64.ADIVF,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                              {1, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +              },
 +      },
 +      {
 +              name:   "DIVD",
 +              argLen: 2,
 +              asm:    loong64.ADIVD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                              {1, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +              },
 +      },
 +      {
 +              name:        "AND",
 +              argLen:      2,
 +              commutative: true,
 +              asm:         loong64.AAND,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
 +                              {1, 1073741817}, // ZERO R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
 +                      },
 +              },
 +      },
 +      {
 +              name:    "ANDconst",
 +              auxType: auxInt64,
 +              argLen:  1,
 +              asm:     loong64.AAND,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
 +                      },
 +              },
 +      },
 +      {
 +              name:        "OR",
 +              argLen:      2,
 +              commutative: true,
 +              asm:         loong64.AOR,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
 +                              {1, 1073741817}, // ZERO R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
 +                      },
 +              },
 +      },
 +      {
 +              name:    "ORconst",
 +              auxType: auxInt64,
 +              argLen:  1,
 +              asm:     loong64.AOR,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
 +                      },
 +              },
 +      },
 +      {
 +              name:        "XOR",
 +              argLen:      2,
 +              commutative: true,
 +              asm:         loong64.AXOR,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
 +                              {1, 1073741817}, // ZERO R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
 +                      },
 +              },
 +      },
 +      {
 +              name:    "XORconst",
 +              auxType: auxInt64,
 +              argLen:  1,
 +              asm:     loong64.AXOR,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
 +                      },
 +              },
 +      },
 +      {
 +              name:        "NOR",
 +              argLen:      2,
 +              commutative: true,
 +              asm:         loong64.ANOR,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
 +                              {1, 1073741817}, // ZERO R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
 +                      },
 +              },
 +      },
 +      {
 +              name:    "NORconst",
 +              auxType: auxInt64,
 +              argLen:  1,
 +              asm:     loong64.ANOR,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
 +                      },
 +              },
 +      },
 +      {
 +              name:   "ANDN",
 +              argLen: 2,
 +              asm:    loong64.AANDN,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
 +                              {1, 1073741817}, // ZERO R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
 +                      },
 +              },
 +      },
 +      {
 +              name:   "ORN",
 +              argLen: 2,
 +              asm:    loong64.AORN,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
 +                              {1, 1073741817}, // ZERO R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
 +                      },
 +              },
 +      },
 +      {
 +              name:        "FMADDF",
 +              argLen:      3,
 +              commutative: true,
 +              asm:         loong64.AFMADDF,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                              {1, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                              {2, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +              },
 +      },
 +      {
 +              name:        "FMADDD",
 +              argLen:      3,
 +              commutative: true,
 +              asm:         loong64.AFMADDD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                              {1, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                              {2, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +              },
 +      },
 +      {
 +              name:        "FMSUBF",
 +              argLen:      3,
 +              commutative: true,
 +              asm:         loong64.AFMSUBF,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                              {1, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                              {2, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +              },
 +      },
 +      {
 +              name:        "FMSUBD",
 +              argLen:      3,
 +              commutative: true,
 +              asm:         loong64.AFMSUBD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                              {1, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                              {2, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +              },
 +      },
 +      {
 +              name:        "FNMADDF",
 +              argLen:      3,
 +              commutative: true,
 +              asm:         loong64.AFNMADDF,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                              {1, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                              {2, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +              },
 +      },
 +      {
 +              name:        "FNMADDD",
 +              argLen:      3,
 +              commutative: true,
 +              asm:         loong64.AFNMADDD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                              {1, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                              {2, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +              },
 +      },
 +      {
 +              name:        "FNMSUBF",
 +              argLen:      3,
 +              commutative: true,
 +              asm:         loong64.AFNMSUBF,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                              {1, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                              {2, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +              },
 +      },
 +      {
 +              name:        "FNMSUBD",
 +              argLen:      3,
 +              commutative: true,
 +              asm:         loong64.AFNMSUBD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                              {1, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                              {2, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +              },
 +      },
 +      {
 +              name:            "FMINF",
 +              argLen:          2,
 +              commutative:     true,
 +              resultNotInArgs: true,
 +              asm:             loong64.AFMINF,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                              {1, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +              },
 +      },
 +      {
 +              name:            "FMIND",
 +              argLen:          2,
 +              commutative:     true,
 +              resultNotInArgs: true,
 +              asm:             loong64.AFMIND,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                              {1, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +              },
 +      },
 +      {
 +              name:            "FMAXF",
 +              argLen:          2,
 +              commutative:     true,
 +              resultNotInArgs: true,
 +              asm:             loong64.AFMAXF,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                              {1, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +              },
 +      },
 +      {
 +              name:            "FMAXD",
 +              argLen:          2,
 +              commutative:     true,
 +              resultNotInArgs: true,
 +              asm:             loong64.AFMAXD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                              {1, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +              },
 +      },
 +      {
 +              name:   "MASKEQZ",
 +              argLen: 2,
 +              asm:    loong64.AMASKEQZ,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
 +                              {1, 1073741817}, // ZERO R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
 +                      },
 +              },
 +      },
 +      {
 +              name:   "MASKNEZ",
 +              argLen: 2,
 +              asm:    loong64.AMASKNEZ,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
 +                              {1, 1073741817}, // ZERO R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
 +                      },
 +              },
 +      },
 +      {
 +              name:   "FCOPYSGD",
 +              argLen: 2,
 +              asm:    loong64.AFCOPYSGD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                              {1, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +              },
 +      },
 +      {
 +              name:   "SLL",
 +              argLen: 2,
 +              asm:    loong64.ASLL,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
 +                              {1, 1073741817}, // ZERO R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
 +                      },
 +              },
 +      },
 +      {
 +              name:   "SLLV",
 +              argLen: 2,
 +              asm:    loong64.ASLLV,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
 +                              {1, 1073741817}, // ZERO R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
 +                      },
 +              },
 +      },
 +      {
 +              name:    "SLLconst",
 +              auxType: auxInt64,
 +              argLen:  1,
 +              asm:     loong64.ASLL,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
 +                      },
 +              },
 +      },
 +      {
 +              name:    "SLLVconst",
 +              auxType: auxInt64,
 +              argLen:  1,
 +              asm:     loong64.ASLLV,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
 +                      },
 +              },
 +      },
 +      {
 +              name:   "SRL",
 +              argLen: 2,
 +              asm:    loong64.ASRL,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
 +                              {1, 1073741817}, // ZERO R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
 +                      },
 +              },
 +      },
 +      {
 +              name:   "SRLV",
 +              argLen: 2,
 +              asm:    loong64.ASRLV,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
 +                              {1, 1073741817}, // ZERO R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
 +                      },
 +              },
 +      },
 +      {
 +              name:    "SRLconst",
 +              auxType: auxInt64,
 +              argLen:  1,
 +              asm:     loong64.ASRL,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
 +                      },
 +              },
 +      },
 +      {
 +              name:    "SRLVconst",
 +              auxType: auxInt64,
 +              argLen:  1,
 +              asm:     loong64.ASRLV,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
 +                      },
 +              },
 +      },
 +      {
 +              name:   "SRA",
 +              argLen: 2,
 +              asm:    loong64.ASRA,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
 +                              {1, 1073741817}, // ZERO R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
 +                      },
 +              },
 +      },
 +      {
 +              name:   "SRAV",
 +              argLen: 2,
 +              asm:    loong64.ASRAV,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
 +                              {1, 1073741817}, // ZERO R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
 +                      },
 +              },
 +      },
 +      {
 +              name:    "SRAconst",
 +              auxType: auxInt64,
 +              argLen:  1,
 +              asm:     loong64.ASRA,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
 +                      },
 +              },
 +      },
 +      {
 +              name:    "SRAVconst",
 +              auxType: auxInt64,
 +              argLen:  1,
 +              asm:     loong64.ASRAV,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
 +                      },
 +              },
 +      },
 +      {
 +              name:   "ROTR",
 +              argLen: 2,
 +              asm:    loong64.AROTR,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
 +                              {1, 1073741817}, // ZERO R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
 +                      },
 +              },
 +      },
 +      {
 +              name:   "ROTRV",
 +              argLen: 2,
 +              asm:    loong64.AROTRV,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
 +                              {1, 1073741817}, // ZERO R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
 +                      },
 +              },
 +      },
 +      {
 +              name:    "ROTRconst",
 +              auxType: auxInt64,
 +              argLen:  1,
 +              asm:     loong64.AROTR,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
 +                      },
 +              },
 +      },
 +      {
 +              name:    "ROTRVconst",
 +              auxType: auxInt64,
 +              argLen:  1,
 +              asm:     loong64.AROTRV,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
 +                      },
 +              },
 +      },
 +      {
 +              name:   "SGT",
 +              argLen: 2,
 +              asm:    loong64.ASGT,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
 +                              {1, 1073741817}, // ZERO R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
 +                      },
 +              },
 +      },
 +      {
 +              name:    "SGTconst",
 +              auxType: auxInt64,
 +              argLen:  1,
 +              asm:     loong64.ASGT,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
 +                      },
 +              },
 +      },
 +      {
 +              name:   "SGTU",
 +              argLen: 2,
 +              asm:    loong64.ASGTU,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
 +                              {1, 1073741817}, // ZERO R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
 +                      },
 +              },
 +      },
 +      {
 +              name:    "SGTUconst",
 +              auxType: auxInt64,
 +              argLen:  1,
 +              asm:     loong64.ASGTU,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
 +                      },
 +              },
 +      },
 +      {
 +              name:   "CMPEQF",
 +              argLen: 2,
 +              asm:    loong64.ACMPEQF,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                              {1, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +              },
 +      },
 +      {
 +              name:   "CMPEQD",
 +              argLen: 2,
 +              asm:    loong64.ACMPEQD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                              {1, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +              },
 +      },
 +      {
 +              name:   "CMPGEF",
 +              argLen: 2,
 +              asm:    loong64.ACMPGEF,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                              {1, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +              },
 +      },
 +      {
 +              name:   "CMPGED",
 +              argLen: 2,
 +              asm:    loong64.ACMPGED,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                              {1, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +              },
 +      },
 +      {
 +              name:   "CMPGTF",
 +              argLen: 2,
 +              asm:    loong64.ACMPGTF,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                              {1, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +              },
 +      },
 +      {
 +              name:   "CMPGTD",
 +              argLen: 2,
 +              asm:    loong64.ACMPGTD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                              {1, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +              },
 +      },
 +      {
 +              name:    "BSTRPICKW",
 +              auxType: auxInt64,
 +              argLen:  1,
 +              asm:     loong64.ABSTRPICKW,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
 +                      },
 +              },
 +      },
 +      {
 +              name:    "BSTRPICKV",
 +              auxType: auxInt64,
 +              argLen:  1,
 +              asm:     loong64.ABSTRPICKV,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
 +                      },
 +              },
 +      },
 +      {
 +              name:              "MOVVconst",
 +              auxType:           auxInt64,
 +              argLen:            0,
 +              rematerializeable: true,
 +              asm:               loong64.AMOVV,
 +              reg: regInfo{
 +                      outputs: []outputInfo{
 +                              {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
 +                      },
 +              },
 +      },
 +      {
 +              name:              "MOVFconst",
 +              auxType:           auxFloat64,
 +              argLen:            0,
 +              rematerializeable: true,
 +              asm:               loong64.AMOVF,
 +              reg: regInfo{
 +                      outputs: []outputInfo{
 +                              {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +              },
 +      },
 +      {
 +              name:              "MOVDconst",
 +              auxType:           auxFloat64,
 +              argLen:            0,
 +              rematerializeable: true,
 +              asm:               loong64.AMOVD,
 +              reg: regInfo{
 +                      outputs: []outputInfo{
 +                              {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +              },
 +      },
 +      {
 +              name:              "MOVVaddr",
 +              auxType:           auxSymOff,
 +              argLen:            1,
 +              rematerializeable: true,
 +              symEffect:         SymAddr,
 +              asm:               loong64.AMOVV,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 4611686018427387908}, // SP SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
 +                      },
 +              },
 +      },
 +      {
 +              name:           "MOVBload",
 +              auxType:        auxSymOff,
 +              argLen:         2,
 +              faultOnNilArg0: true,
 +              symEffect:      SymRead,
 +              asm:            loong64.AMOVB,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
 +                      },
 +              },
 +      },
 +      {
 +              name:           "MOVBUload",
 +              auxType:        auxSymOff,
 +              argLen:         2,
 +              faultOnNilArg0: true,
 +              symEffect:      SymRead,
 +              asm:            loong64.AMOVBU,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
 +                      },
 +              },
 +      },
 +      {
 +              name:           "MOVHload",
 +              auxType:        auxSymOff,
 +              argLen:         2,
 +              faultOnNilArg0: true,
 +              symEffect:      SymRead,
 +              asm:            loong64.AMOVH,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
 +                      },
 +              },
 +      },
 +      {
 +              name:           "MOVHUload",
 +              auxType:        auxSymOff,
 +              argLen:         2,
 +              faultOnNilArg0: true,
 +              symEffect:      SymRead,
 +              asm:            loong64.AMOVHU,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
 +                      },
 +              },
 +      },
 +      {
 +              name:           "MOVWload",
 +              auxType:        auxSymOff,
 +              argLen:         2,
 +              faultOnNilArg0: true,
 +              symEffect:      SymRead,
 +              asm:            loong64.AMOVW,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
 +                      },
 +              },
 +      },
 +      {
 +              name:           "MOVWUload",
 +              auxType:        auxSymOff,
 +              argLen:         2,
 +              faultOnNilArg0: true,
 +              symEffect:      SymRead,
 +              asm:            loong64.AMOVWU,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
 +                      },
 +              },
 +      },
 +      {
 +              name:           "MOVVload",
 +              auxType:        auxSymOff,
 +              argLen:         2,
 +              faultOnNilArg0: true,
 +              symEffect:      SymRead,
 +              asm:            loong64.AMOVV,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
 +                      },
 +              },
 +      },
 +      {
 +              name:           "MOVFload",
 +              auxType:        auxSymOff,
 +              argLen:         2,
 +              faultOnNilArg0: true,
 +              symEffect:      SymRead,
 +              asm:            loong64.AMOVF,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +              },
 +      },
 +      {
 +              name:           "MOVDload",
 +              auxType:        auxSymOff,
 +              argLen:         2,
 +              faultOnNilArg0: true,
 +              symEffect:      SymRead,
 +              asm:            loong64.AMOVD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +              },
 +      },
 +      {
 +              name:   "MOVVloadidx",
 +              argLen: 3,
 +              asm:    loong64.AMOVV,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 1073741816},          // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
 +                              {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
 +                      },
 +              },
 +      },
 +      {
 +              name:   "MOVWloadidx",
 +              argLen: 3,
 +              asm:    loong64.AMOVW,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 1073741816},          // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
 +                              {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
 +                      },
 +              },
 +      },
 +      {
 +              name:   "MOVWUloadidx",
 +              argLen: 3,
 +              asm:    loong64.AMOVWU,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 1073741816},          // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
 +                              {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
 +                      },
 +              },
 +      },
 +      {
 +              name:   "MOVHloadidx",
 +              argLen: 3,
 +              asm:    loong64.AMOVH,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 1073741816},          // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
 +                              {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
 +                      },
 +              },
 +      },
 +      {
 +              name:   "MOVHUloadidx",
 +              argLen: 3,
 +              asm:    loong64.AMOVHU,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 1073741816},          // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
 +                              {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
 +                      },
 +              },
 +      },
 +      {
 +              name:   "MOVBloadidx",
 +              argLen: 3,
 +              asm:    loong64.AMOVB,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 1073741816},          // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
 +                              {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
 +                      },
 +              },
 +      },
 +      {
 +              name:   "MOVBUloadidx",
 +              argLen: 3,
 +              asm:    loong64.AMOVBU,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 1073741816},          // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
 +                              {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
 +                      },
 +              },
 +      },
 +      {
 +              name:   "MOVFloadidx",
 +              argLen: 3,
 +              asm:    loong64.AMOVF,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 1073741816},          // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
 +                              {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +              },
 +      },
 +      {
 +              name:   "MOVDloadidx",
 +              argLen: 3,
 +              asm:    loong64.AMOVD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 1073741816},          // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
 +                              {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +              },
 +      },
 +      {
 +              name:           "MOVBstore",
 +              auxType:        auxSymOff,
 +              argLen:         3,
 +              faultOnNilArg0: true,
 +              symEffect:      SymWrite,
 +              asm:            loong64.AMOVB,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 1073741817},          // ZERO R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
 +                              {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
 +                      },
 +              },
 +      },
 +      {
 +              name:           "MOVHstore",
 +              auxType:        auxSymOff,
 +              argLen:         3,
 +              faultOnNilArg0: true,
 +              symEffect:      SymWrite,
 +              asm:            loong64.AMOVH,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 1073741817},          // ZERO R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
 +                              {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
 +                      },
 +              },
 +      },
 +      {
 +              name:           "MOVWstore",
 +              auxType:        auxSymOff,
 +              argLen:         3,
 +              faultOnNilArg0: true,
 +              symEffect:      SymWrite,
 +              asm:            loong64.AMOVW,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 1073741817},          // ZERO R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
 +                              {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
 +                      },
 +              },
 +      },
 +      {
 +              name:           "MOVVstore",
 +              auxType:        auxSymOff,
 +              argLen:         3,
 +              faultOnNilArg0: true,
 +              symEffect:      SymWrite,
 +              asm:            loong64.AMOVV,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 1073741817},          // ZERO R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
 +                              {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
 +                      },
 +              },
 +      },
 +      {
 +              name:           "MOVFstore",
 +              auxType:        auxSymOff,
 +              argLen:         3,
 +              faultOnNilArg0: true,
 +              symEffect:      SymWrite,
 +              asm:            loong64.AMOVF,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
 +                              {1, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +              },
 +      },
 +      {
 +              name:           "MOVDstore",
 +              auxType:        auxSymOff,
 +              argLen:         3,
 +              faultOnNilArg0: true,
 +              symEffect:      SymWrite,
 +              asm:            loong64.AMOVD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
 +                              {1, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +              },
 +      },
 +      {
 +              name:   "MOVBstoreidx",
 +              argLen: 4,
 +              asm:    loong64.AMOVB,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 1073741816},          // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
 +                              {2, 1073741817},          // ZERO R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
 +                              {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
 +                      },
 +              },
 +      },
 +      {
 +              name:   "MOVHstoreidx",
 +              argLen: 4,
 +              asm:    loong64.AMOVH,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 1073741816},          // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
 +                              {2, 1073741817},          // ZERO R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
 +                              {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
 +                      },
 +              },
 +      },
 +      {
 +              name:   "MOVWstoreidx",
 +              argLen: 4,
 +              asm:    loong64.AMOVW,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 1073741816},          // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
 +                              {2, 1073741817},          // ZERO R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
 +                              {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
 +                      },
 +              },
 +      },
 +      {
 +              name:   "MOVVstoreidx",
 +              argLen: 4,
 +              asm:    loong64.AMOVV,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 1073741816},          // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
 +                              {2, 1073741817},          // ZERO R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
 +                              {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
 +                      },
 +              },
 +      },
 +      {
 +              name:   "MOVFstoreidx",
 +              argLen: 4,
 +              asm:    loong64.AMOVF,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 1073741816},          // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
 +                              {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
 +                              {2, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +              },
 +      },
 +      {
 +              name:   "MOVDstoreidx",
 +              argLen: 4,
 +              asm:    loong64.AMOVD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 1073741816},          // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
 +                              {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
 +                              {2, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +              },
 +      },
 +      {
 +              name:   "MOVWfpgp",
 +              argLen: 1,
 +              asm:    loong64.AMOVW,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
 +                      },
 +              },
 +      },
 +      {
 +              name:   "MOVWgpfp",
 +              argLen: 1,
 +              asm:    loong64.AMOVW,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +              },
 +      },
 +      {
 +              name:   "MOVVfpgp",
 +              argLen: 1,
 +              asm:    loong64.AMOVV,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
 +                      },
 +              },
 +      },
 +      {
 +              name:   "MOVVgpfp",
 +              argLen: 1,
 +              asm:    loong64.AMOVV,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +              },
 +      },
 +      {
 +              name:   "MOVBreg",
 +              argLen: 1,
 +              asm:    loong64.AMOVB,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
 +                      },
 +              },
 +      },
 +      {
 +              name:   "MOVBUreg",
 +              argLen: 1,
 +              asm:    loong64.AMOVBU,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
 +                      },
 +              },
 +      },
 +      {
 +              name:   "MOVHreg",
 +              argLen: 1,
 +              asm:    loong64.AMOVH,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
 +                      },
 +              },
 +      },
 +      {
 +              name:   "MOVHUreg",
 +              argLen: 1,
 +              asm:    loong64.AMOVHU,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
 +                      },
 +              },
 +      },
 +      {
 +              name:   "MOVWreg",
 +              argLen: 1,
 +              asm:    loong64.AMOVW,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
 +                      },
 +              },
 +      },
 +      {
 +              name:   "MOVWUreg",
 +              argLen: 1,
 +              asm:    loong64.AMOVWU,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
 +                      },
 +              },
 +      },
 +      {
 +              name:   "MOVVreg",
 +              argLen: 1,
 +              asm:    loong64.AMOVV,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "MOVVnop",
 +              argLen:       1,
 +              resultInArg0: true,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
 +                      },
 +              },
 +      },
 +      {
 +              name:   "MOVWF",
 +              argLen: 1,
 +              asm:    loong64.AMOVWF,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +              },
 +      },
 +      {
 +              name:   "MOVWD",
 +              argLen: 1,
 +              asm:    loong64.AMOVWD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +              },
 +      },
 +      {
 +              name:   "MOVVF",
 +              argLen: 1,
 +              asm:    loong64.AMOVVF,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +              },
 +      },
 +      {
 +              name:   "MOVVD",
 +              argLen: 1,
 +              asm:    loong64.AMOVVD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +              },
 +      },
 +      {
 +              name:   "TRUNCFW",
 +              argLen: 1,
 +              asm:    loong64.ATRUNCFW,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +              },
 +      },
 +      {
 +              name:   "TRUNCDW",
 +              argLen: 1,
 +              asm:    loong64.ATRUNCDW,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +              },
 +      },
 +      {
 +              name:   "TRUNCFV",
 +              argLen: 1,
 +              asm:    loong64.ATRUNCFV,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +              },
 +      },
 +      {
 +              name:   "TRUNCDV",
 +              argLen: 1,
 +              asm:    loong64.ATRUNCDV,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +              },
 +      },
 +      {
 +              name:   "MOVFD",
 +              argLen: 1,
 +              asm:    loong64.AMOVFD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +              },
 +      },
 +      {
 +              name:   "MOVDF",
 +              argLen: 1,
 +              asm:    loong64.AMOVDF,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "LoweredRound32F",
 +              argLen:       1,
 +              resultInArg0: true,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "LoweredRound64F",
 +              argLen:       1,
 +              resultInArg0: true,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "CALLstatic",
 +              auxType:      auxCallOff,
 +              argLen:       -1,
 +              clobberFlags: true,
 +              call:         true,
 +              reg: regInfo{
 +                      clobbers: 4611686018427387896, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +              },
 +      },
 +      {
 +              name:         "CALLtail",
 +              auxType:      auxCallOff,
 +              argLen:       -1,
 +              clobberFlags: true,
 +              call:         true,
 +              tailCall:     true,
 +              reg: regInfo{
 +                      clobbers: 4611686018427387896, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +              },
 +      },
 +      {
 +              name:         "CALLclosure",
 +              auxType:      auxCallOff,
 +              argLen:       -1,
 +              clobberFlags: true,
 +              call:         true,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 268435456},  // R29
 +                              {0, 1071644668}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
 +                      },
 +                      clobbers: 4611686018427387896, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +              },
 +      },
 +      {
 +              name:         "CALLinter",
 +              auxType:      auxCallOff,
 +              argLen:       -1,
 +              clobberFlags: true,
 +              call:         true,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
 +                      },
 +                      clobbers: 4611686018427387896, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +              },
 +      },
 +      {
 +              name:           "LoweredZero",
 +              auxType:        auxInt64,
 +              argLen:         2,
 +              faultOnNilArg0: true,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
 +                      },
 +              },
 +      },
 +      {
 +              name:           "LoweredZeroLoop",
 +              auxType:        auxInt64,
 +              argLen:         2,
 +              needIntTemp:    true,
 +              faultOnNilArg0: true,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
 +                      },
++                      clobbers:     2305843009213693952, // F31
 +                      clobbersArg0: true,
 +              },
 +      },
 +      {
 +              name:           "LoweredMove",
 +              auxType:        auxInt64,
 +              argLen:         3,
 +              faultOnNilArg0: true,
 +              faultOnNilArg1: true,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1071120376}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R21 R23 R24 R25 R26 R27 R28 R29 R31
 +                              {1, 1071120376}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R21 R23 R24 R25 R26 R27 R28 R29 R31
 +                      },
 +                      clobbers: 524288, // R20
 +              },
 +      },
 +      {
 +              name:           "LoweredMoveLoop",
 +              auxType:        auxInt64,
 +              argLen:         3,
 +              faultOnNilArg0: true,
 +              faultOnNilArg1: true,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1070071800}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R23 R24 R25 R26 R27 R28 R29 R31
 +                              {1, 1070071800}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R23 R24 R25 R26 R27 R28 R29 R31
 +                      },
 +                      clobbers:     1572864, // R20 R21
 +                      clobbersArg0: true,
 +                      clobbersArg1: true,
 +              },
 +      },
 +      {
 +              name:           "LoweredAtomicLoad8",
 +              argLen:         2,
 +              faultOnNilArg0: true,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
 +                      },
 +              },
 +      },
 +      {
 +              name:           "LoweredAtomicLoad32",
 +              argLen:         2,
 +              faultOnNilArg0: true,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
 +                      },
 +              },
 +      },
 +      {
 +              name:           "LoweredAtomicLoad64",
 +              argLen:         2,
 +              faultOnNilArg0: true,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
 +                      },
 +              },
 +      },
 +      {
 +              name:           "LoweredAtomicStore8",
 +              argLen:         3,
 +              faultOnNilArg0: true,
 +              hasSideEffects: true,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 1073741816},          // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
 +                              {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
 +                      },
 +              },
 +      },
 +      {
 +              name:           "LoweredAtomicStore32",
 +              argLen:         3,
 +              faultOnNilArg0: true,
 +              hasSideEffects: true,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 1073741816},          // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
 +                              {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
 +                      },
 +              },
 +      },
 +      {
 +              name:           "LoweredAtomicStore64",
 +              argLen:         3,
 +              faultOnNilArg0: true,
 +              hasSideEffects: true,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 1073741816},          // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
 +                              {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
 +                      },
 +              },
 +      },
 +      {
 +              name:           "LoweredAtomicStore8Variant",
 +              argLen:         3,
 +              faultOnNilArg0: true,
 +              hasSideEffects: true,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 1073741816},          // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
 +                              {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
 +                      },
 +              },
 +      },
 +      {
 +              name:           "LoweredAtomicStore32Variant",
 +              argLen:         3,
 +              faultOnNilArg0: true,
 +              hasSideEffects: true,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 1073741816},          // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
 +                              {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
 +                      },
 +              },
 +      },
 +      {
 +              name:           "LoweredAtomicStore64Variant",
 +              argLen:         3,
 +              faultOnNilArg0: true,
 +              hasSideEffects: true,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 1073741816},          // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
 +                              {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
 +                      },
 +              },
 +      },
 +      {
 +              name:            "LoweredAtomicExchange32",
 +              argLen:          3,
 +              resultNotInArgs: true,
 +              faultOnNilArg0:  true,
 +              hasSideEffects:  true,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 1073741816},          // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
 +                              {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
 +                      },
 +              },
 +      },
 +      {
 +              name:            "LoweredAtomicExchange64",
 +              argLen:          3,
 +              resultNotInArgs: true,
 +              faultOnNilArg0:  true,
 +              hasSideEffects:  true,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 1073741816},          // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
 +                              {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
 +                      },
 +              },
 +      },
 +      {
 +              name:            "LoweredAtomicExchange8Variant",
 +              argLen:          3,
 +              resultNotInArgs: true,
 +              faultOnNilArg0:  true,
 +              hasSideEffects:  true,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 1073741816},          // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
 +                              {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
 +                      },
 +              },
 +      },
 +      {
 +              name:            "LoweredAtomicAdd32",
 +              argLen:          3,
 +              resultNotInArgs: true,
 +              faultOnNilArg0:  true,
 +              hasSideEffects:  true,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 1073741816},          // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
 +                              {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
 +                      },
 +              },
 +      },
 +      {
 +              name:            "LoweredAtomicAdd64",
 +              argLen:          3,
 +              resultNotInArgs: true,
 +              faultOnNilArg0:  true,
 +              hasSideEffects:  true,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 1073741816},          // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
 +                              {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
 +                      },
 +              },
 +      },
 +      {
 +              name:            "LoweredAtomicCas32",
 +              argLen:          4,
 +              resultNotInArgs: true,
 +              faultOnNilArg0:  true,
 +              hasSideEffects:  true,
 +              unsafePoint:     true,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 1073741816},          // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
 +                              {2, 1073741816},          // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
 +                              {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
 +                      },
 +              },
 +      },
 +      {
 +              name:            "LoweredAtomicCas64",
 +              argLen:          4,
 +              resultNotInArgs: true,
 +              faultOnNilArg0:  true,
 +              hasSideEffects:  true,
 +              unsafePoint:     true,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 1073741816},          // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
 +                              {2, 1073741816},          // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
 +                              {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
 +                      },
 +              },
 +      },
 +      {
 +              name:            "LoweredAtomicCas64Variant",
 +              argLen:          4,
 +              resultNotInArgs: true,
 +              faultOnNilArg0:  true,
 +              hasSideEffects:  true,
 +              unsafePoint:     true,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 1073741816},          // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
 +                              {2, 1073741816},          // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
 +                              {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
 +                      },
 +              },
 +      },
 +      {
 +              name:            "LoweredAtomicCas32Variant",
 +              argLen:          4,
 +              resultNotInArgs: true,
 +              faultOnNilArg0:  true,
 +              hasSideEffects:  true,
 +              unsafePoint:     true,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 1073741816},          // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
 +                              {2, 1073741816},          // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
 +                              {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
 +                      },
 +              },
 +      },
 +      {
 +              name:            "LoweredAtomicAnd32",
 +              argLen:          3,
 +              resultNotInArgs: true,
 +              faultOnNilArg0:  true,
 +              hasSideEffects:  true,
 +              asm:             loong64.AAMANDDBW,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 1073741816},          // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
 +                              {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
 +                      },
 +              },
 +      },
 +      {
 +              name:            "LoweredAtomicOr32",
 +              argLen:          3,
 +              resultNotInArgs: true,
 +              faultOnNilArg0:  true,
 +              hasSideEffects:  true,
 +              asm:             loong64.AAMORDBW,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 1073741816},          // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
 +                              {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
 +                      },
 +              },
 +      },
 +      {
 +              name:            "LoweredAtomicAnd32value",
 +              argLen:          3,
 +              resultNotInArgs: true,
 +              faultOnNilArg0:  true,
 +              hasSideEffects:  true,
 +              asm:             loong64.AAMANDDBW,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 1073741816},          // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
 +                              {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
 +                      },
 +              },
 +      },
 +      {
 +              name:            "LoweredAtomicAnd64value",
 +              argLen:          3,
 +              resultNotInArgs: true,
 +              faultOnNilArg0:  true,
 +              hasSideEffects:  true,
 +              asm:             loong64.AAMANDDBV,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 1073741816},          // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
 +                              {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
 +                      },
 +              },
 +      },
 +      {
 +              name:            "LoweredAtomicOr32value",
 +              argLen:          3,
 +              resultNotInArgs: true,
 +              faultOnNilArg0:  true,
 +              hasSideEffects:  true,
 +              asm:             loong64.AAMORDBW,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 1073741816},          // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
 +                              {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
 +                      },
 +              },
 +      },
 +      {
 +              name:            "LoweredAtomicOr64value",
 +              argLen:          3,
 +              resultNotInArgs: true,
 +              faultOnNilArg0:  true,
 +              hasSideEffects:  true,
 +              asm:             loong64.AAMORDBV,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 1073741816},          // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
 +                              {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
 +                      },
 +              },
 +      },
 +      {
 +              name:           "LoweredNilCheck",
 +              argLen:         2,
 +              nilCheck:       true,
 +              faultOnNilArg0: true,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
 +                      },
 +              },
 +      },
 +      {
 +              name:   "FPFlagTrue",
 +              argLen: 1,
 +              reg: regInfo{
 +                      outputs: []outputInfo{
 +                              {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
 +                      },
 +              },
 +      },
 +      {
 +              name:   "FPFlagFalse",
 +              argLen: 1,
 +              reg: regInfo{
 +                      outputs: []outputInfo{
 +                              {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
 +                      },
 +              },
 +      },
 +      {
 +              name:      "LoweredGetClosurePtr",
 +              argLen:    0,
 +              zeroWidth: true,
 +              reg: regInfo{
 +                      outputs: []outputInfo{
 +                              {0, 268435456}, // R29
 +                      },
 +              },
 +      },
 +      {
 +              name:              "LoweredGetCallerSP",
 +              argLen:            1,
 +              rematerializeable: true,
 +              reg: regInfo{
 +                      outputs: []outputInfo{
 +                              {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
 +                      },
 +              },
 +      },
 +      {
 +              name:              "LoweredGetCallerPC",
 +              argLen:            0,
 +              rematerializeable: true,
 +              reg: regInfo{
 +                      outputs: []outputInfo{
 +                              {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "LoweredWB",
 +              auxType:      auxInt64,
 +              argLen:       1,
 +              clobberFlags: true,
 +              reg: regInfo{
 +                      clobbers: 4611686017353646082, // R1 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      outputs: []outputInfo{
 +                              {0, 268435456}, // R29
 +                      },
 +              },
 +      },
 +      {
 +              name:           "LoweredPubBarrier",
 +              argLen:         1,
 +              hasSideEffects: true,
 +              asm:            loong64.ADBAR,
 +              reg:            regInfo{},
 +      },
 +      {
 +              name:    "LoweredPanicBoundsRR",
 +              auxType: auxInt64,
 +              argLen:  3,
 +              call:    true,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 524280}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19
 +                              {1, 524280}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19
 +                      },
 +              },
 +      },
 +      {
 +              name:    "LoweredPanicBoundsRC",
 +              auxType: auxPanicBoundsC,
 +              argLen:  2,
 +              call:    true,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 524280}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19
 +                      },
 +              },
 +      },
 +      {
 +              name:    "LoweredPanicBoundsCR",
 +              auxType: auxPanicBoundsC,
 +              argLen:  2,
 +              call:    true,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 524280}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19
 +                      },
 +              },
 +      },
 +      {
 +              name:    "LoweredPanicBoundsCC",
 +              auxType: auxPanicBoundsCC,
 +              argLen:  1,
 +              call:    true,
 +              reg:     regInfo{},
 +      },
 +      {
 +              name:           "PRELD",
 +              auxType:        auxInt64,
 +              argLen:         2,
 +              hasSideEffects: true,
 +              asm:            loong64.APRELD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1073741820}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
 +                      },
 +              },
 +      },
 +      {
 +              name:           "PRELDX",
 +              auxType:        auxInt64,
 +              argLen:         2,
 +              hasSideEffects: true,
 +              asm:            loong64.APRELDX,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1073741820}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
 +                      },
 +              },
 +      },
 +      {
 +              name:    "ADDshiftLLV",
 +              auxType: auxInt64,
 +              argLen:  2,
 +              asm:     loong64.AALSLV,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
 +                              {1, 1073741817}, // ZERO R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
 +                      },
 +              },
 +      },
 +      {
 +              name:      "ZERO",
 +              argLen:    0,
 +              zeroWidth: true,
 +              fixedReg:  true,
 +              reg:       regInfo{},
 +      },
 +
 +      {
 +              name:        "ADD",
 +              argLen:      2,
 +              commutative: true,
 +              asm:         mips.AADDU,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
 +                              {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
 +                      },
 +              },
 +      },
 +      {
 +              name:    "ADDconst",
 +              auxType: auxInt32,
 +              argLen:  1,
 +              asm:     mips.AADDU,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 536870910}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
 +                      },
 +              },
 +      },
 +      {
 +              name:   "SUB",
 +              argLen: 2,
 +              asm:    mips.ASUBU,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
 +                              {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
 +                      },
 +              },
 +      },
 +      {
 +              name:    "SUBconst",
 +              auxType: auxInt32,
 +              argLen:  1,
 +              asm:     mips.ASUBU,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
 +                      },
 +              },
 +      },
 +      {
 +              name:        "MUL",
 +              argLen:      2,
 +              commutative: true,
 +              asm:         mips.AMUL,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
 +                              {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
 +                      },
 +                      clobbers: 105553116266496, // HI LO
 +                      outputs: []outputInfo{
 +                              {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
 +                      },
 +              },
 +      },
 +      {
 +              name:        "MULT",
 +              argLen:      2,
 +              commutative: true,
 +              asm:         mips.AMUL,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
 +                              {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 35184372088832}, // HI
 +                              {1, 70368744177664}, // LO
 +                      },
 +              },
 +      },
 +      {
 +              name:        "MULTU",
 +              argLen:      2,
 +              commutative: true,
 +              asm:         mips.AMULU,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
 +                              {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 35184372088832}, // HI
 +                              {1, 70368744177664}, // LO
 +                      },
 +              },
 +      },
 +      {
 +              name:   "DIV",
 +              argLen: 2,
 +              asm:    mips.ADIV,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
 +                              {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 35184372088832}, // HI
 +                              {1, 70368744177664}, // LO
 +                      },
 +              },
 +      },
 +      {
 +              name:   "DIVU",
 +              argLen: 2,
 +              asm:    mips.ADIVU,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
 +                              {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 35184372088832}, // HI
 +                              {1, 70368744177664}, // LO
 +                      },
 +              },
 +      },
 +      {
 +              name:        "ADDF",
 +              argLen:      2,
 +              commutative: true,
 +              asm:         mips.AADDF,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
 +                              {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
 +                      },
 +              },
 +      },
 +      {
 +              name:        "ADDD",
 +              argLen:      2,
 +              commutative: true,
 +              asm:         mips.AADDD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
 +                              {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
 +                      },
 +              },
 +      },
 +      {
 +              name:   "SUBF",
 +              argLen: 2,
 +              asm:    mips.ASUBF,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
 +                              {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
 +                      },
 +              },
 +      },
 +      {
 +              name:   "SUBD",
 +              argLen: 2,
 +              asm:    mips.ASUBD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
 +                              {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
 +                      },
 +              },
 +      },
 +      {
 +              name:        "MULF",
 +              argLen:      2,
 +              commutative: true,
 +              asm:         mips.AMULF,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
 +                              {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
 +                      },
 +              },
 +      },
 +      {
 +              name:        "MULD",
 +              argLen:      2,
 +              commutative: true,
 +              asm:         mips.AMULD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
 +                              {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
 +                      },
 +              },
 +      },
 +      {
 +              name:   "DIVF",
 +              argLen: 2,
 +              asm:    mips.ADIVF,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
 +                              {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
 +                      },
 +              },
 +      },
 +      {
 +              name:   "DIVD",
 +              argLen: 2,
 +              asm:    mips.ADIVD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
 +                              {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
 +                      },
 +              },
 +      },
 +      {
 +              name:        "AND",
 +              argLen:      2,
 +              commutative: true,
 +              asm:         mips.AAND,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
 +                              {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
 +                      },
 +              },
 +      },
 +      {
 +              name:    "ANDconst",
 +              auxType: auxInt32,
 +              argLen:  1,
 +              asm:     mips.AAND,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
 +                      },
 +              },
 +      },
 +      {
 +              name:        "OR",
 +              argLen:      2,
 +              commutative: true,
 +              asm:         mips.AOR,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
 +                              {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
 +                      },
 +              },
 +      },
 +      {
 +              name:    "ORconst",
 +              auxType: auxInt32,
 +              argLen:  1,
 +              asm:     mips.AOR,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
 +                      },
 +              },
 +      },
 +      {
 +              name:        "XOR",
 +              argLen:      2,
 +              commutative: true,
 +              asm:         mips.AXOR,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
 +                              {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
 +                      },
 +              },
 +      },
 +      {
 +              name:    "XORconst",
 +              auxType: auxInt32,
 +              argLen:  1,
 +              asm:     mips.AXOR,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
 +                      },
 +              },
 +      },
 +      {
 +              name:        "NOR",
 +              argLen:      2,
 +              commutative: true,
 +              asm:         mips.ANOR,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
 +                              {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
 +                      },
 +              },
 +      },
 +      {
 +              name:    "NORconst",
 +              auxType: auxInt32,
 +              argLen:  1,
 +              asm:     mips.ANOR,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
 +                      },
 +              },
 +      },
 +      {
 +              name:   "NEG",
 +              argLen: 1,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
 +                      },
 +              },
 +      },
 +      {
 +              name:   "NEGF",
 +              argLen: 1,
 +              asm:    mips.ANEGF,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
 +                      },
 +              },
 +      },
 +      {
 +              name:   "NEGD",
 +              argLen: 1,
 +              asm:    mips.ANEGD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
 +                      },
 +              },
 +      },
 +      {
 +              name:   "ABSD",
 +              argLen: 1,
 +              asm:    mips.AABSD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
 +                      },
 +              },
 +      },
 +      {
 +              name:   "SQRTD",
 +              argLen: 1,
 +              asm:    mips.ASQRTD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
 +                      },
 +              },
 +      },
 +      {
 +              name:   "SQRTF",
 +              argLen: 1,
 +              asm:    mips.ASQRTF,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
 +                      },
 +              },
 +      },
 +      {
 +              name:   "SLL",
 +              argLen: 2,
 +              asm:    mips.ASLL,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
 +                              {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
 +                      },
 +              },
 +      },
 +      {
 +              name:    "SLLconst",
 +              auxType: auxInt32,
 +              argLen:  1,
 +              asm:     mips.ASLL,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
 +                      },
 +              },
 +      },
 +      {
 +              name:   "SRL",
 +              argLen: 2,
 +              asm:    mips.ASRL,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
 +                              {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
 +                      },
 +              },
 +      },
 +      {
 +              name:    "SRLconst",
 +              auxType: auxInt32,
 +              argLen:  1,
 +              asm:     mips.ASRL,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
 +                      },
 +              },
 +      },
 +      {
 +              name:   "SRA",
 +              argLen: 2,
 +              asm:    mips.ASRA,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
 +                              {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
 +                      },
 +              },
 +      },
 +      {
 +              name:    "SRAconst",
 +              auxType: auxInt32,
 +              argLen:  1,
 +              asm:     mips.ASRA,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
 +                      },
 +              },
 +      },
 +      {
 +              name:   "CLZ",
 +              argLen: 1,
 +              asm:    mips.ACLZ,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
 +                      },
 +              },
 +      },
 +      {
 +              name:   "SGT",
 +              argLen: 2,
 +              asm:    mips.ASGT,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
 +                              {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
 +                      },
 +              },
 +      },
 +      {
 +              name:    "SGTconst",
 +              auxType: auxInt32,
 +              argLen:  1,
 +              asm:     mips.ASGT,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
 +                      },
 +              },
 +      },
 +      {
 +              name:   "SGTzero",
 +              argLen: 1,
 +              asm:    mips.ASGT,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
 +                      },
 +              },
 +      },
 +      {
 +              name:   "SGTU",
 +              argLen: 2,
 +              asm:    mips.ASGTU,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
 +                              {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
 +                      },
 +              },
 +      },
 +      {
 +              name:    "SGTUconst",
 +              auxType: auxInt32,
 +              argLen:  1,
 +              asm:     mips.ASGTU,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
 +                      },
 +              },
 +      },
 +      {
 +              name:   "SGTUzero",
 +              argLen: 1,
 +              asm:    mips.ASGTU,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
 +                      },
 +              },
 +      },
 +      {
 +              name:   "CMPEQF",
 +              argLen: 2,
 +              asm:    mips.ACMPEQF,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
 +                              {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
 +                      },
 +              },
 +      },
 +      {
 +              name:   "CMPEQD",
 +              argLen: 2,
 +              asm:    mips.ACMPEQD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
 +                              {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
 +                      },
 +              },
 +      },
 +      {
 +              name:   "CMPGEF",
 +              argLen: 2,
 +              asm:    mips.ACMPGEF,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
 +                              {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
 +                      },
 +              },
 +      },
 +      {
 +              name:   "CMPGED",
 +              argLen: 2,
 +              asm:    mips.ACMPGED,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
 +                              {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
 +                      },
 +              },
 +      },
 +      {
 +              name:   "CMPGTF",
 +              argLen: 2,
 +              asm:    mips.ACMPGTF,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
 +                              {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
 +                      },
 +              },
 +      },
 +      {
 +              name:   "CMPGTD",
 +              argLen: 2,
 +              asm:    mips.ACMPGTD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
 +                              {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
 +                      },
 +              },
 +      },
 +      {
 +              name:              "MOVWconst",
 +              auxType:           auxInt32,
 +              argLen:            0,
 +              rematerializeable: true,
 +              asm:               mips.AMOVW,
 +              reg: regInfo{
 +                      outputs: []outputInfo{
 +                              {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
 +                      },
 +              },
 +      },
 +      {
 +              name:              "MOVFconst",
 +              auxType:           auxFloat32,
 +              argLen:            0,
 +              rematerializeable: true,
 +              asm:               mips.AMOVF,
 +              reg: regInfo{
 +                      outputs: []outputInfo{
 +                              {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
 +                      },
 +              },
 +      },
 +      {
 +              name:              "MOVDconst",
 +              auxType:           auxFloat64,
 +              argLen:            0,
 +              rematerializeable: true,
 +              asm:               mips.AMOVD,
 +              reg: regInfo{
 +                      outputs: []outputInfo{
 +                              {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
 +                      },
 +              },
 +      },
 +      {
 +              name:              "MOVWaddr",
 +              auxType:           auxSymOff,
 +              argLen:            1,
 +              rematerializeable: true,
 +              symEffect:         SymAddr,
 +              asm:               mips.AMOVW,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 140737555464192}, // SP SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
 +                      },
 +              },
 +      },
 +      {
 +              name:           "MOVBload",
 +              auxType:        auxSymOff,
 +              argLen:         2,
 +              faultOnNilArg0: true,
 +              symEffect:      SymRead,
 +              asm:            mips.AMOVB,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
 +                      },
 +              },
 +      },
 +      {
 +              name:           "MOVBUload",
 +              auxType:        auxSymOff,
 +              argLen:         2,
 +              faultOnNilArg0: true,
 +              symEffect:      SymRead,
 +              asm:            mips.AMOVBU,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
 +                      },
 +              },
 +      },
 +      {
 +              name:           "MOVHload",
 +              auxType:        auxSymOff,
 +              argLen:         2,
 +              faultOnNilArg0: true,
 +              symEffect:      SymRead,
 +              asm:            mips.AMOVH,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
 +                      },
 +              },
 +      },
 +      {
 +              name:           "MOVHUload",
 +              auxType:        auxSymOff,
 +              argLen:         2,
 +              faultOnNilArg0: true,
 +              symEffect:      SymRead,
 +              asm:            mips.AMOVHU,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
 +                      },
 +              },
 +      },
 +      {
 +              name:           "MOVWload",
 +              auxType:        auxSymOff,
 +              argLen:         2,
 +              faultOnNilArg0: true,
 +              symEffect:      SymRead,
 +              asm:            mips.AMOVW,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
 +                      },
 +              },
 +      },
 +      {
 +              name:           "MOVFload",
 +              auxType:        auxSymOff,
 +              argLen:         2,
 +              faultOnNilArg0: true,
 +              symEffect:      SymRead,
 +              asm:            mips.AMOVF,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
 +                      },
 +              },
 +      },
 +      {
 +              name:           "MOVDload",
 +              auxType:        auxSymOff,
 +              argLen:         2,
 +              faultOnNilArg0: true,
 +              symEffect:      SymRead,
 +              asm:            mips.AMOVD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
 +                      },
 +              },
 +      },
 +      {
 +              name:           "MOVBstore",
 +              auxType:        auxSymOff,
 +              argLen:         3,
 +              faultOnNilArg0: true,
 +              symEffect:      SymWrite,
 +              asm:            mips.AMOVB,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 469762046},       // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
 +                              {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB
 +                      },
 +              },
 +      },
 +      {
 +              name:           "MOVHstore",
 +              auxType:        auxSymOff,
 +              argLen:         3,
 +              faultOnNilArg0: true,
 +              symEffect:      SymWrite,
 +              asm:            mips.AMOVH,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 469762046},       // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
 +                              {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB
 +                      },
 +              },
 +      },
 +      {
 +              name:           "MOVWstore",
 +              auxType:        auxSymOff,
 +              argLen:         3,
 +              faultOnNilArg0: true,
 +              symEffect:      SymWrite,
 +              asm:            mips.AMOVW,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 469762046},       // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
 +                              {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB
 +                      },
 +              },
 +      },
 +      {
 +              name:           "MOVFstore",
 +              auxType:        auxSymOff,
 +              argLen:         3,
 +              faultOnNilArg0: true,
 +              symEffect:      SymWrite,
 +              asm:            mips.AMOVF,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 35183835217920},  // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
 +                              {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB
 +                      },
 +              },
 +      },
 +      {
 +              name:           "MOVDstore",
 +              auxType:        auxSymOff,
 +              argLen:         3,
 +              faultOnNilArg0: true,
 +              symEffect:      SymWrite,
 +              asm:            mips.AMOVD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 35183835217920},  // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
 +                              {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB
 +                      },
 +              },
 +      },
 +      {
 +              name:           "MOVBstorezero",
 +              auxType:        auxSymOff,
 +              argLen:         2,
 +              faultOnNilArg0: true,
 +              symEffect:      SymWrite,
 +              asm:            mips.AMOVB,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB
 +                      },
 +              },
 +      },
 +      {
 +              name:           "MOVHstorezero",
 +              auxType:        auxSymOff,
 +              argLen:         2,
 +              faultOnNilArg0: true,
 +              symEffect:      SymWrite,
 +              asm:            mips.AMOVH,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB
 +                      },
 +              },
 +      },
 +      {
 +              name:           "MOVWstorezero",
 +              auxType:        auxSymOff,
 +              argLen:         2,
 +              faultOnNilArg0: true,
 +              symEffect:      SymWrite,
 +              asm:            mips.AMOVW,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB
 +                      },
 +              },
 +      },
 +      {
 +              name:   "MOVWfpgp",
 +              argLen: 1,
 +              asm:    mips.AMOVW,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
 +                      },
 +              },
 +      },
 +      {
 +              name:   "MOVWgpfp",
 +              argLen: 1,
 +              asm:    mips.AMOVW,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
 +                      },
 +              },
 +      },
 +      {
 +              name:   "MOVBreg",
 +              argLen: 1,
 +              asm:    mips.AMOVB,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
 +                      },
 +              },
 +      },
 +      {
 +              name:   "MOVBUreg",
 +              argLen: 1,
 +              asm:    mips.AMOVBU,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
 +                      },
 +              },
 +      },
 +      {
 +              name:   "MOVHreg",
 +              argLen: 1,
 +              asm:    mips.AMOVH,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
 +                      },
 +              },
 +      },
 +      {
 +              name:   "MOVHUreg",
 +              argLen: 1,
 +              asm:    mips.AMOVHU,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
 +                      },
 +              },
 +      },
 +      {
 +              name:   "MOVWreg",
 +              argLen: 1,
 +              asm:    mips.AMOVW,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "MOVWnop",
 +              argLen:       1,
 +              resultInArg0: true,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "CMOVZ",
 +              argLen:       3,
 +              resultInArg0: true,
 +              asm:          mips.ACMOVZ,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
 +                              {1, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
 +                              {2, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "CMOVZzero",
 +              argLen:       2,
 +              resultInArg0: true,
 +              asm:          mips.ACMOVZ,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
 +                              {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
 +                      },
 +              },
 +      },
 +      {
 +              name:   "MOVWF",
 +              argLen: 1,
 +              asm:    mips.AMOVWF,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
 +                      },
 +              },
 +      },
 +      {
 +              name:   "MOVWD",
 +              argLen: 1,
 +              asm:    mips.AMOVWD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
 +                      },
 +              },
 +      },
 +      {
 +              name:   "TRUNCFW",
 +              argLen: 1,
 +              asm:    mips.ATRUNCFW,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
 +                      },
 +              },
 +      },
 +      {
 +              name:   "TRUNCDW",
 +              argLen: 1,
 +              asm:    mips.ATRUNCDW,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
 +                      },
 +              },
 +      },
 +      {
 +              name:   "MOVFD",
 +              argLen: 1,
 +              asm:    mips.AMOVFD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
 +                      },
 +              },
 +      },
 +      {
 +              name:   "MOVDF",
 +              argLen: 1,
 +              asm:    mips.AMOVDF,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
 +                      },
 +              },
 +      },
 +      {
 +              name:         "CALLstatic",
 +              auxType:      auxCallOff,
 +              argLen:       1,
 +              clobberFlags: true,
 +              call:         true,
 +              reg: regInfo{
 +                      clobbers: 140737421246462, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 HI LO
 +              },
 +      },
 +      {
 +              name:         "CALLtail",
 +              auxType:      auxCallOff,
 +              argLen:       1,
 +              clobberFlags: true,
 +              call:         true,
 +              tailCall:     true,
 +              reg: regInfo{
 +                      clobbers: 140737421246462, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 HI LO
 +              },
 +      },
 +      {
 +              name:         "CALLclosure",
 +              auxType:      auxCallOff,
 +              argLen:       3,
 +              clobberFlags: true,
 +              call:         true,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 4194304},   // R22
 +                              {0, 402653182}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP R31
 +                      },
 +                      clobbers: 140737421246462, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 HI LO
 +              },
 +      },
 +      {
 +              name:         "CALLinter",
 +              auxType:      auxCallOff,
 +              argLen:       2,
 +              clobberFlags: true,
 +              call:         true,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
 +                      },
 +                      clobbers: 140737421246462, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 HI LO
 +              },
 +      },
 +      {
 +              name:           "LoweredAtomicLoad8",
 +              argLen:         2,
 +              faultOnNilArg0: true,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
 +                      },
 +              },
 +      },
 +      {
 +              name:           "LoweredAtomicLoad32",
 +              argLen:         2,
 +              faultOnNilArg0: true,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
 +                      },
 +              },
 +      },
 +      {
 +              name:           "LoweredAtomicStore8",
 +              argLen:         3,
 +              faultOnNilArg0: true,
 +              hasSideEffects: true,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 469762046},       // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
 +                              {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB
 +                      },
 +              },
 +      },
 +      {
 +              name:           "LoweredAtomicStore32",
 +              argLen:         3,
 +              faultOnNilArg0: true,
 +              hasSideEffects: true,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 469762046},       // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
 +                              {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB
 +                      },
 +              },
 +      },
 +      {
 +              name:           "LoweredAtomicStorezero",
 +              argLen:         2,
 +              faultOnNilArg0: true,
 +              hasSideEffects: true,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB
 +                      },
 +              },
 +      },
 +      {
 +              name:            "LoweredAtomicExchange",
 +              argLen:          3,
 +              resultNotInArgs: true,
 +              faultOnNilArg0:  true,
 +              hasSideEffects:  true,
 +              unsafePoint:     true,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 469762046},       // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
 +                              {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
 +                      },
 +              },
 +      },
 +      {
 +              name:            "LoweredAtomicAdd",
 +              argLen:          3,
 +              resultNotInArgs: true,
 +              faultOnNilArg0:  true,
 +              hasSideEffects:  true,
 +              unsafePoint:     true,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 469762046},       // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
 +                              {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
 +                      },
 +              },
 +      },
 +      {
 +              name:            "LoweredAtomicAddconst",
 +              auxType:         auxInt32,
 +              argLen:          2,
 +              resultNotInArgs: true,
 +              faultOnNilArg0:  true,
 +              hasSideEffects:  true,
 +              unsafePoint:     true,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
 +                      },
 +              },
 +      },
 +      {
 +              name:            "LoweredAtomicCas",
 +              argLen:          4,
 +              resultNotInArgs: true,
 +              faultOnNilArg0:  true,
 +              hasSideEffects:  true,
 +              unsafePoint:     true,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 469762046},       // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
 +                              {2, 469762046},       // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
 +                              {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
 +                      },
 +              },
 +      },
 +      {
 +              name:           "LoweredAtomicAnd",
 +              argLen:         3,
 +              faultOnNilArg0: true,
 +              hasSideEffects: true,
 +              unsafePoint:    true,
 +              asm:            mips.AAND,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 469762046},       // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
 +                              {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB
 +                      },
 +              },
 +      },
 +      {
 +              name:           "LoweredAtomicOr",
 +              argLen:         3,
 +              faultOnNilArg0: true,
 +              hasSideEffects: true,
 +              unsafePoint:    true,
 +              asm:            mips.AOR,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 469762046},       // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
 +                              {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB
 +                      },
 +              },
 +      },
 +      {
 +              name:           "LoweredZero",
 +              auxType:        auxInt32,
 +              argLen:         3,
 +              faultOnNilArg0: true,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 2},         // R1
 +                              {1, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
 +                      },
 +                      clobbers: 2, // R1
 +              },
 +      },
 +      {
 +              name:           "LoweredMove",
 +              auxType:        auxInt32,
 +              argLen:         4,
 +              faultOnNilArg0: true,
 +              faultOnNilArg1: true,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 4},         // R2
 +                              {1, 2},         // R1
 +                              {2, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
 +                      },
 +                      clobbers: 6, // R1 R2
 +              },
 +      },
 +      {
 +              name:           "LoweredNilCheck",
 +              argLen:         2,
 +              nilCheck:       true,
 +              faultOnNilArg0: true,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
 +                      },
 +              },
 +      },
 +      {
 +              name:   "FPFlagTrue",
 +              argLen: 1,
 +              reg: regInfo{
 +                      outputs: []outputInfo{
 +                              {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
 +                      },
 +              },
 +      },
 +      {
 +              name:   "FPFlagFalse",
 +              argLen: 1,
 +              reg: regInfo{
 +                      outputs: []outputInfo{
 +                              {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
 +                      },
 +              },
 +      },
 +      {
 +              name:      "LoweredGetClosurePtr",
 +              argLen:    0,
 +              zeroWidth: true,
 +              reg: regInfo{
 +                      outputs: []outputInfo{
 +                              {0, 4194304}, // R22
 +                      },
 +              },
 +      },
 +      {
 +              name:              "LoweredGetCallerSP",
 +              argLen:            1,
 +              rematerializeable: true,
 +              reg: regInfo{
 +                      outputs: []outputInfo{
 +                              {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
 +                      },
 +              },
 +      },
 +      {
 +              name:              "LoweredGetCallerPC",
 +              argLen:            0,
 +              rematerializeable: true,
 +              reg: regInfo{
 +                      outputs: []outputInfo{
 +                              {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "LoweredWB",
 +              auxType:      auxInt64,
 +              argLen:       1,
 +              clobberFlags: true,
 +              reg: regInfo{
 +                      clobbers: 140737219919872, // R31 F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 HI LO
 +                      outputs: []outputInfo{
 +                              {0, 16777216}, // R25
 +                      },
 +              },
 +      },
 +      {
 +              name:           "LoweredPubBarrier",
 +              argLen:         1,
 +              hasSideEffects: true,
 +              asm:            mips.ASYNC,
 +              reg:            regInfo{},
 +      },
 +      {
 +              name:    "LoweredPanicBoundsRR",
 +              auxType: auxInt64,
 +              argLen:  3,
 +              call:    true,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 131070}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16
 +                              {1, 131070}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16
 +                      },
 +              },
 +      },
 +      {
 +              name:    "LoweredPanicBoundsRC",
 +              auxType: auxPanicBoundsC,
 +              argLen:  2,
 +              call:    true,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 131070}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16
 +                      },
 +              },
 +      },
 +      {
 +              name:    "LoweredPanicBoundsCR",
 +              auxType: auxPanicBoundsC,
 +              argLen:  2,
 +              call:    true,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 131070}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16
 +                      },
 +              },
 +      },
 +      {
 +              name:    "LoweredPanicBoundsCC",
 +              auxType: auxPanicBoundsCC,
 +              argLen:  1,
 +              call:    true,
 +              reg:     regInfo{},
 +      },
 +      {
 +              name:    "LoweredPanicExtendRR",
 +              auxType: auxInt64,
 +              argLen:  4,
 +              call:    true,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 30},     // R1 R2 R3 R4
 +                              {1, 30},     // R1 R2 R3 R4
 +                              {2, 131070}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16
 +                      },
 +              },
 +      },
 +      {
 +              name:    "LoweredPanicExtendRC",
 +              auxType: auxPanicBoundsC,
 +              argLen:  3,
 +              call:    true,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 30}, // R1 R2 R3 R4
 +                              {1, 30}, // R1 R2 R3 R4
 +                      },
 +              },
 +      },
 +
 +      {
 +              name:        "ADDV",
 +              argLen:      2,
 +              commutative: true,
 +              asm:         mips.AADDVU,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
 +                              {1, 234881023}, // ZERO R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
 +                      },
 +              },
 +      },
 +      {
 +              name:    "ADDVconst",
 +              auxType: auxInt64,
 +              argLen:  1,
 +              asm:     mips.AADDVU,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 268435454}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
 +                      },
 +              },
 +      },
 +      {
 +              name:   "SUBV",
 +              argLen: 2,
 +              asm:    mips.ASUBVU,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
 +                              {1, 234881023}, // ZERO R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
 +                      },
 +              },
 +      },
 +      {
 +              name:    "SUBVconst",
 +              auxType: auxInt64,
 +              argLen:  1,
 +              asm:     mips.ASUBVU,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
 +                      },
 +              },
 +      },
 +      {
 +              name:        "MULV",
 +              argLen:      2,
 +              commutative: true,
 +              asm:         mips.AMULV,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
 +                              {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1152921504606846976}, // HI
 +                              {1, 2305843009213693952}, // LO
 +                      },
 +              },
 +      },
 +      {
 +              name:        "MULVU",
 +              argLen:      2,
 +              commutative: true,
 +              asm:         mips.AMULVU,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
 +                              {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1152921504606846976}, // HI
 +                              {1, 2305843009213693952}, // LO
 +                      },
 +              },
 +      },
 +      {
 +              name:   "DIVV",
 +              argLen: 2,
 +              asm:    mips.ADIVV,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
 +                              {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1152921504606846976}, // HI
 +                              {1, 2305843009213693952}, // LO
 +                      },
 +              },
 +      },
 +      {
 +              name:   "DIVVU",
 +              argLen: 2,
 +              asm:    mips.ADIVVU,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
 +                              {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1152921504606846976}, // HI
 +                              {1, 2305843009213693952}, // LO
 +                      },
 +              },
 +      },
 +      {
 +              name:        "ADDF",
 +              argLen:      2,
 +              commutative: true,
 +              asm:         mips.AADDF,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                              {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +              },
 +      },
 +      {
 +              name:        "ADDD",
 +              argLen:      2,
 +              commutative: true,
 +              asm:         mips.AADDD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                              {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +              },
 +      },
 +      {
 +              name:   "SUBF",
 +              argLen: 2,
 +              asm:    mips.ASUBF,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                              {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +              },
 +      },
 +      {
 +              name:   "SUBD",
 +              argLen: 2,
 +              asm:    mips.ASUBD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                              {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +              },
 +      },
 +      {
 +              name:        "MULF",
 +              argLen:      2,
 +              commutative: true,
 +              asm:         mips.AMULF,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                              {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +              },
 +      },
 +      {
 +              name:        "MULD",
 +              argLen:      2,
 +              commutative: true,
 +              asm:         mips.AMULD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                              {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +              },
 +      },
 +      {
 +              name:   "DIVF",
 +              argLen: 2,
 +              asm:    mips.ADIVF,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                              {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +              },
 +      },
 +      {
 +              name:   "DIVD",
 +              argLen: 2,
 +              asm:    mips.ADIVD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                              {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +              },
 +      },
 +      {
 +              name:        "AND",
 +              argLen:      2,
 +              commutative: true,
 +              asm:         mips.AAND,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
 +                              {1, 234881023}, // ZERO R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
 +                      },
 +              },
 +      },
 +      {
 +              name:    "ANDconst",
 +              auxType: auxInt64,
 +              argLen:  1,
 +              asm:     mips.AAND,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
 +                      },
 +              },
 +      },
 +      {
 +              name:        "OR",
 +              argLen:      2,
 +              commutative: true,
 +              asm:         mips.AOR,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
 +                              {1, 234881023}, // ZERO R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
 +                      },
 +              },
 +      },
 +      {
 +              name:    "ORconst",
 +              auxType: auxInt64,
 +              argLen:  1,
 +              asm:     mips.AOR,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
 +                      },
 +              },
 +      },
 +      {
 +              name:        "XOR",
 +              argLen:      2,
 +              commutative: true,
 +              asm:         mips.AXOR,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
 +                              {1, 234881023}, // ZERO R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
 +                      },
 +              },
 +      },
 +      {
 +              name:    "XORconst",
 +              auxType: auxInt64,
 +              argLen:  1,
 +              asm:     mips.AXOR,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
 +                      },
 +              },
 +      },
 +      {
 +              name:        "NOR",
 +              argLen:      2,
 +              commutative: true,
 +              asm:         mips.ANOR,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
 +                              {1, 234881023}, // ZERO R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
 +                      },
 +              },
 +      },
 +      {
 +              name:    "NORconst",
 +              auxType: auxInt64,
 +              argLen:  1,
 +              asm:     mips.ANOR,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
 +                      },
 +              },
 +      },
 +      {
 +              name:   "NEGV",
 +              argLen: 1,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
 +                      },
 +              },
 +      },
 +      {
 +              name:   "NEGF",
 +              argLen: 1,
 +              asm:    mips.ANEGF,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +              },
 +      },
 +      {
 +              name:   "NEGD",
 +              argLen: 1,
 +              asm:    mips.ANEGD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +              },
 +      },
 +      {
 +              name:   "ABSD",
 +              argLen: 1,
 +              asm:    mips.AABSD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +              },
 +      },
 +      {
 +              name:   "SQRTD",
 +              argLen: 1,
 +              asm:    mips.ASQRTD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +              },
 +      },
 +      {
 +              name:   "SQRTF",
 +              argLen: 1,
 +              asm:    mips.ASQRTF,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +              },
 +      },
 +      {
 +              name:   "SLLV",
 +              argLen: 2,
 +              asm:    mips.ASLLV,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
 +                              {1, 234881023}, // ZERO R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
 +                      },
 +              },
 +      },
 +      {
 +              name:    "SLLVconst",
 +              auxType: auxInt64,
 +              argLen:  1,
 +              asm:     mips.ASLLV,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
 +                      },
 +              },
 +      },
 +      {
 +              name:   "SRLV",
 +              argLen: 2,
 +              asm:    mips.ASRLV,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
 +                              {1, 234881023}, // ZERO R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
 +                      },
 +              },
 +      },
 +      {
 +              name:    "SRLVconst",
 +              auxType: auxInt64,
 +              argLen:  1,
 +              asm:     mips.ASRLV,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
 +                      },
 +              },
 +      },
 +      {
 +              name:   "SRAV",
 +              argLen: 2,
 +              asm:    mips.ASRAV,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
 +                              {1, 234881023}, // ZERO R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
 +                      },
 +              },
 +      },
 +      {
 +              name:    "SRAVconst",
 +              auxType: auxInt64,
 +              argLen:  1,
 +              asm:     mips.ASRAV,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
 +                      },
 +              },
 +      },
 +      {
 +              name:   "SGT",
 +              argLen: 2,
 +              asm:    mips.ASGT,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
 +                              {1, 234881023}, // ZERO R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
 +                      },
 +              },
 +      },
 +      {
 +              name:    "SGTconst",
 +              auxType: auxInt64,
 +              argLen:  1,
 +              asm:     mips.ASGT,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
 +                      },
 +              },
 +      },
 +      {
 +              name:   "SGTU",
 +              argLen: 2,
 +              asm:    mips.ASGTU,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
 +                              {1, 234881023}, // ZERO R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
 +                      },
 +              },
 +      },
 +      {
 +              name:    "SGTUconst",
 +              auxType: auxInt64,
 +              argLen:  1,
 +              asm:     mips.ASGTU,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
 +                      },
 +              },
 +      },
 +      {
 +              name:   "CMPEQF",
 +              argLen: 2,
 +              asm:    mips.ACMPEQF,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                              {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +              },
 +      },
 +      {
 +              name:   "CMPEQD",
 +              argLen: 2,
 +              asm:    mips.ACMPEQD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                              {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +              },
 +      },
 +      {
 +              name:   "CMPGEF",
 +              argLen: 2,
 +              asm:    mips.ACMPGEF,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                              {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +              },
 +      },
 +      {
 +              name:   "CMPGED",
 +              argLen: 2,
 +              asm:    mips.ACMPGED,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                              {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +              },
 +      },
 +      {
 +              name:   "CMPGTF",
 +              argLen: 2,
 +              asm:    mips.ACMPGTF,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                              {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +              },
 +      },
 +      {
 +              name:   "CMPGTD",
 +              argLen: 2,
 +              asm:    mips.ACMPGTD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                              {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +              },
 +      },
 +      {
 +              name:              "MOVVconst",
 +              auxType:           auxInt64,
 +              argLen:            0,
 +              rematerializeable: true,
 +              asm:               mips.AMOVV,
 +              reg: regInfo{
 +                      outputs: []outputInfo{
 +                              {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
 +                      },
 +              },
 +      },
 +      {
 +              name:              "MOVFconst",
 +              auxType:           auxFloat64,
 +              argLen:            0,
 +              rematerializeable: true,
 +              asm:               mips.AMOVF,
 +              reg: regInfo{
 +                      outputs: []outputInfo{
 +                              {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +              },
 +      },
 +      {
 +              name:              "MOVDconst",
 +              auxType:           auxFloat64,
 +              argLen:            0,
 +              rematerializeable: true,
 +              asm:               mips.AMOVD,
 +              reg: regInfo{
 +                      outputs: []outputInfo{
 +                              {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +              },
 +      },
 +      {
 +              name:              "MOVVaddr",
 +              auxType:           auxSymOff,
 +              argLen:            1,
 +              rematerializeable: true,
 +              symEffect:         SymAddr,
 +              asm:               mips.AMOVV,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 4611686018460942336}, // SP SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
 +                      },
 +              },
 +      },
 +      {
 +              name:           "MOVBload",
 +              auxType:        auxSymOff,
 +              argLen:         2,
 +              faultOnNilArg0: true,
 +              symEffect:      SymRead,
 +              asm:            mips.AMOVB,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
 +                      },
 +              },
 +      },
 +      {
 +              name:           "MOVBUload",
 +              auxType:        auxSymOff,
 +              argLen:         2,
 +              faultOnNilArg0: true,
 +              symEffect:      SymRead,
 +              asm:            mips.AMOVBU,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
 +                      },
 +              },
 +      },
 +      {
 +              name:           "MOVHload",
 +              auxType:        auxSymOff,
 +              argLen:         2,
 +              faultOnNilArg0: true,
 +              symEffect:      SymRead,
 +              asm:            mips.AMOVH,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
 +                      },
 +              },
 +      },
 +      {
 +              name:           "MOVHUload",
 +              auxType:        auxSymOff,
 +              argLen:         2,
 +              faultOnNilArg0: true,
 +              symEffect:      SymRead,
 +              asm:            mips.AMOVHU,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
 +                      },
 +              },
 +      },
 +      {
 +              name:           "MOVWload",
 +              auxType:        auxSymOff,
 +              argLen:         2,
 +              faultOnNilArg0: true,
 +              symEffect:      SymRead,
 +              asm:            mips.AMOVW,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
 +                      },
 +              },
 +      },
 +      {
 +              name:           "MOVWUload",
 +              auxType:        auxSymOff,
 +              argLen:         2,
 +              faultOnNilArg0: true,
 +              symEffect:      SymRead,
 +              asm:            mips.AMOVWU,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
 +                      },
 +              },
 +      },
 +      {
 +              name:           "MOVVload",
 +              auxType:        auxSymOff,
 +              argLen:         2,
 +              faultOnNilArg0: true,
 +              symEffect:      SymRead,
 +              asm:            mips.AMOVV,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
 +                      },
 +              },
 +      },
 +      {
 +              name:           "MOVFload",
 +              auxType:        auxSymOff,
 +              argLen:         2,
 +              faultOnNilArg0: true,
 +              symEffect:      SymRead,
 +              asm:            mips.AMOVF,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +              },
 +      },
 +      {
 +              name:           "MOVDload",
 +              auxType:        auxSymOff,
 +              argLen:         2,
 +              faultOnNilArg0: true,
 +              symEffect:      SymRead,
 +              asm:            mips.AMOVD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +              },
 +      },
 +      {
 +              name:           "MOVBstore",
 +              auxType:        auxSymOff,
 +              argLen:         3,
 +              faultOnNilArg0: true,
 +              symEffect:      SymWrite,
 +              asm:            mips.AMOVB,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 234881023},           // ZERO R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
 +                              {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB
 +                      },
 +              },
 +      },
 +      {
 +              name:           "MOVHstore",
 +              auxType:        auxSymOff,
 +              argLen:         3,
 +              faultOnNilArg0: true,
 +              symEffect:      SymWrite,
 +              asm:            mips.AMOVH,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 234881023},           // ZERO R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
 +                              {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB
 +                      },
 +              },
 +      },
 +      {
 +              name:           "MOVWstore",
 +              auxType:        auxSymOff,
 +              argLen:         3,
 +              faultOnNilArg0: true,
 +              symEffect:      SymWrite,
 +              asm:            mips.AMOVW,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 234881023},           // ZERO R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
 +                              {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB
 +                      },
 +              },
 +      },
 +      {
 +              name:           "MOVVstore",
 +              auxType:        auxSymOff,
 +              argLen:         3,
 +              faultOnNilArg0: true,
 +              symEffect:      SymWrite,
 +              asm:            mips.AMOVV,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 234881023},           // ZERO R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
 +                              {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB
 +                      },
 +              },
 +      },
 +      {
 +              name:           "MOVFstore",
 +              auxType:        auxSymOff,
 +              argLen:         3,
 +              faultOnNilArg0: true,
 +              symEffect:      SymWrite,
 +              asm:            mips.AMOVF,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB
 +                              {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +              },
 +      },
 +      {
 +              name:           "MOVDstore",
 +              auxType:        auxSymOff,
 +              argLen:         3,
 +              faultOnNilArg0: true,
 +              symEffect:      SymWrite,
 +              asm:            mips.AMOVD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB
 +                              {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +              },
 +      },
 +      {
 +              name:      "ZERO",
 +              argLen:    0,
 +              zeroWidth: true,
 +              fixedReg:  true,
 +              reg:       regInfo{},
 +      },
 +      {
 +              name:   "MOVWfpgp",
 +              argLen: 1,
 +              asm:    mips.AMOVW,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
 +                      },
 +              },
 +      },
 +      {
 +              name:   "MOVWgpfp",
 +              argLen: 1,
 +              asm:    mips.AMOVW,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +              },
 +      },
 +      {
 +              name:   "MOVVfpgp",
 +              argLen: 1,
 +              asm:    mips.AMOVV,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
 +                      },
 +              },
 +      },
 +      {
 +              name:   "MOVVgpfp",
 +              argLen: 1,
 +              asm:    mips.AMOVV,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +              },
 +      },
 +      {
 +              name:   "MOVBreg",
 +              argLen: 1,
 +              asm:    mips.AMOVB,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
 +                      },
 +              },
 +      },
 +      {
 +              name:   "MOVBUreg",
 +              argLen: 1,
 +              asm:    mips.AMOVBU,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
 +                      },
 +              },
 +      },
 +      {
 +              name:   "MOVHreg",
 +              argLen: 1,
 +              asm:    mips.AMOVH,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
 +                      },
 +              },
 +      },
 +      {
 +              name:   "MOVHUreg",
 +              argLen: 1,
 +              asm:    mips.AMOVHU,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
 +                      },
 +              },
 +      },
 +      {
 +              name:   "MOVWreg",
 +              argLen: 1,
 +              asm:    mips.AMOVW,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
 +                      },
 +              },
 +      },
 +      {
 +              name:   "MOVWUreg",
 +              argLen: 1,
 +              asm:    mips.AMOVWU,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
 +                      },
 +              },
 +      },
 +      {
 +              name:   "MOVVreg",
 +              argLen: 1,
 +              asm:    mips.AMOVV,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "MOVVnop",
 +              argLen:       1,
 +              resultInArg0: true,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
 +                      },
 +              },
 +      },
 +      {
 +              name:   "MOVWF",
 +              argLen: 1,
 +              asm:    mips.AMOVWF,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +              },
 +      },
 +      {
 +              name:   "MOVWD",
 +              argLen: 1,
 +              asm:    mips.AMOVWD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +              },
 +      },
 +      {
 +              name:   "MOVVF",
 +              argLen: 1,
 +              asm:    mips.AMOVVF,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +              },
 +      },
 +      {
 +              name:   "MOVVD",
 +              argLen: 1,
 +              asm:    mips.AMOVVD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +              },
 +      },
 +      {
 +              name:   "TRUNCFW",
 +              argLen: 1,
 +              asm:    mips.ATRUNCFW,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +              },
 +      },
 +      {
 +              name:   "TRUNCDW",
 +              argLen: 1,
 +              asm:    mips.ATRUNCDW,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +              },
 +      },
 +      {
 +              name:   "TRUNCFV",
 +              argLen: 1,
 +              asm:    mips.ATRUNCFV,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +              },
 +      },
 +      {
 +              name:   "TRUNCDV",
 +              argLen: 1,
 +              asm:    mips.ATRUNCDV,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +              },
 +      },
 +      {
 +              name:   "MOVFD",
 +              argLen: 1,
 +              asm:    mips.AMOVFD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +              },
 +      },
 +      {
 +              name:   "MOVDF",
 +              argLen: 1,
 +              asm:    mips.AMOVDF,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "CALLstatic",
 +              auxType:      auxCallOff,
 +              argLen:       1,
 +              clobberFlags: true,
 +              call:         true,
 +              reg: regInfo{
 +                      clobbers: 4611686018393833470, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 HI LO
 +              },
 +      },
 +      {
 +              name:         "CALLtail",
 +              auxType:      auxCallOff,
 +              argLen:       1,
 +              clobberFlags: true,
 +              call:         true,
 +              tailCall:     true,
 +              reg: regInfo{
 +                      clobbers: 4611686018393833470, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 HI LO
 +              },
 +      },
 +      {
 +              name:         "CALLclosure",
 +              auxType:      auxCallOff,
 +              argLen:       3,
 +              clobberFlags: true,
 +              call:         true,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 4194304},   // R22
 +                              {0, 201326590}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP R31
 +                      },
 +                      clobbers: 4611686018393833470, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 HI LO
 +              },
 +      },
 +      {
 +              name:         "CALLinter",
 +              auxType:      auxCallOff,
 +              argLen:       2,
 +              clobberFlags: true,
 +              call:         true,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
 +                      },
 +                      clobbers: 4611686018393833470, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 HI LO
 +              },
 +      },
 +      {
 +              name:           "DUFFZERO",
 +              auxType:        auxInt64,
 +              argLen:         2,
 +              faultOnNilArg0: true,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
 +                      },
 +                      clobbers: 134217730, // R1 R31
 +              },
 +      },
 +      {
 +              name:           "DUFFCOPY",
 +              auxType:        auxInt64,
 +              argLen:         3,
 +              faultOnNilArg0: true,
 +              faultOnNilArg1: true,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 4}, // R2
 +                              {1, 2}, // R1
 +                      },
 +                      clobbers: 134217734, // R1 R2 R31
 +              },
 +      },
 +      {
 +              name:           "LoweredZero",
 +              auxType:        auxInt64,
 +              argLen:         3,
 +              clobberFlags:   true,
 +              faultOnNilArg0: true,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 2},         // R1
 +                              {1, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
 +                      },
 +                      clobbers: 2, // R1
 +              },
 +      },
 +      {
 +              name:           "LoweredMove",
 +              auxType:        auxInt64,
 +              argLen:         4,
 +              clobberFlags:   true,
 +              faultOnNilArg0: true,
 +              faultOnNilArg1: true,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 4},         // R2
 +                              {1, 2},         // R1
 +                              {2, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
 +                      },
 +                      clobbers: 6, // R1 R2
 +              },
 +      },
 +      {
 +              name:           "LoweredAtomicAnd32",
 +              argLen:         3,
 +              faultOnNilArg0: true,
 +              hasSideEffects: true,
 +              unsafePoint:    true,
 +              asm:            mips.AAND,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 234881023},           // ZERO R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
 +                              {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB
 +                      },
 +              },
 +      },
 +      {
 +              name:           "LoweredAtomicOr32",
 +              argLen:         3,
 +              faultOnNilArg0: true,
 +              hasSideEffects: true,
 +              unsafePoint:    true,
 +              asm:            mips.AOR,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 234881023},           // ZERO R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
 +                              {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB
 +                      },
 +              },
 +      },
 +      {
 +              name:           "LoweredAtomicLoad8",
 +              argLen:         2,
 +              faultOnNilArg0: true,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
 +                      },
 +              },
 +      },
 +      {
 +              name:           "LoweredAtomicLoad32",
 +              argLen:         2,
 +              faultOnNilArg0: true,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
 +                      },
 +              },
 +      },
 +      {
 +              name:           "LoweredAtomicLoad64",
 +              argLen:         2,
 +              faultOnNilArg0: true,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
 +                      },
 +              },
 +      },
 +      {
 +              name:           "LoweredAtomicStore8",
 +              argLen:         3,
 +              faultOnNilArg0: true,
 +              hasSideEffects: true,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 234881023},           // ZERO R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
 +                              {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB
 +                      },
 +              },
 +      },
 +      {
 +              name:           "LoweredAtomicStore32",
 +              argLen:         3,
 +              faultOnNilArg0: true,
 +              hasSideEffects: true,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 234881023},           // ZERO R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
 +                              {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB
 +                      },
 +              },
 +      },
 +      {
 +              name:           "LoweredAtomicStore64",
 +              argLen:         3,
 +              faultOnNilArg0: true,
 +              hasSideEffects: true,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 234881023},           // ZERO R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
 +                              {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB
 +                      },
 +              },
 +      },
 +      {
 +              name:           "LoweredAtomicStorezero32",
 +              argLen:         2,
 +              faultOnNilArg0: true,
 +              hasSideEffects: true,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB
 +                      },
 +              },
 +      },
 +      {
 +              name:           "LoweredAtomicStorezero64",
 +              argLen:         2,
 +              faultOnNilArg0: true,
 +              hasSideEffects: true,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB
 +                      },
 +              },
 +      },
 +      {
 +              name:            "LoweredAtomicExchange32",
 +              argLen:          3,
 +              resultNotInArgs: true,
 +              faultOnNilArg0:  true,
 +              hasSideEffects:  true,
 +              unsafePoint:     true,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 234881022},           // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
 +                              {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
 +                      },
 +              },
 +      },
 +      {
 +              name:            "LoweredAtomicExchange64",
 +              argLen:          3,
 +              resultNotInArgs: true,
 +              faultOnNilArg0:  true,
 +              hasSideEffects:  true,
 +              unsafePoint:     true,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 234881022},           // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
 +                              {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
 +                      },
 +              },
 +      },
 +      {
 +              name:            "LoweredAtomicAdd32",
 +              argLen:          3,
 +              resultNotInArgs: true,
 +              faultOnNilArg0:  true,
 +              hasSideEffects:  true,
 +              unsafePoint:     true,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 234881022},           // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
 +                              {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
 +                      },
 +              },
 +      },
 +      {
 +              name:            "LoweredAtomicAdd64",
 +              argLen:          3,
 +              resultNotInArgs: true,
 +              faultOnNilArg0:  true,
 +              hasSideEffects:  true,
 +              unsafePoint:     true,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 234881022},           // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
 +                              {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
 +                      },
 +              },
 +      },
 +      {
 +              name:            "LoweredAtomicAddconst32",
 +              auxType:         auxInt32,
 +              argLen:          2,
 +              resultNotInArgs: true,
 +              faultOnNilArg0:  true,
 +              hasSideEffects:  true,
 +              unsafePoint:     true,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
 +                      },
 +              },
 +      },
 +      {
 +              name:            "LoweredAtomicAddconst64",
 +              auxType:         auxInt64,
 +              argLen:          2,
 +              resultNotInArgs: true,
 +              faultOnNilArg0:  true,
 +              hasSideEffects:  true,
 +              unsafePoint:     true,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
 +                      },
 +              },
 +      },
 +      {
 +              name:            "LoweredAtomicCas32",
 +              argLen:          4,
 +              resultNotInArgs: true,
 +              faultOnNilArg0:  true,
 +              hasSideEffects:  true,
 +              unsafePoint:     true,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 234881022},           // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
 +                              {2, 234881022},           // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
 +                              {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
 +                      },
 +              },
 +      },
 +      {
 +              name:            "LoweredAtomicCas64",
 +              argLen:          4,
 +              resultNotInArgs: true,
 +              faultOnNilArg0:  true,
 +              hasSideEffects:  true,
 +              unsafePoint:     true,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 234881022},           // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
 +                              {2, 234881022},           // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
 +                              {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
 +                      },
 +              },
 +      },
 +      {
 +              name:           "LoweredNilCheck",
 +              argLen:         2,
 +              nilCheck:       true,
 +              faultOnNilArg0: true,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
 +                      },
 +              },
 +      },
 +      {
 +              name:   "FPFlagTrue",
 +              argLen: 1,
 +              reg: regInfo{
 +                      outputs: []outputInfo{
 +                              {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
 +                      },
 +              },
 +      },
 +      {
 +              name:   "FPFlagFalse",
 +              argLen: 1,
 +              reg: regInfo{
 +                      outputs: []outputInfo{
 +                              {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
 +                      },
 +              },
 +      },
 +      {
 +              name:      "LoweredGetClosurePtr",
 +              argLen:    0,
 +              zeroWidth: true,
 +              reg: regInfo{
 +                      outputs: []outputInfo{
 +                              {0, 4194304}, // R22
 +                      },
 +              },
 +      },
 +      {
 +              name:              "LoweredGetCallerSP",
 +              argLen:            1,
 +              rematerializeable: true,
 +              reg: regInfo{
 +                      outputs: []outputInfo{
 +                              {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
 +                      },
 +              },
 +      },
 +      {
 +              name:              "LoweredGetCallerPC",
 +              argLen:            0,
 +              rematerializeable: true,
 +              reg: regInfo{
 +                      outputs: []outputInfo{
 +                              {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "LoweredWB",
 +              auxType:      auxInt64,
 +              argLen:       1,
 +              clobberFlags: true,
 +              reg: regInfo{
 +                      clobbers: 4611686018293170176, // R31 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 HI LO
 +                      outputs: []outputInfo{
 +                              {0, 16777216}, // R25
 +                      },
 +              },
 +      },
 +      {
 +              name:           "LoweredPubBarrier",
 +              argLen:         1,
 +              hasSideEffects: true,
 +              asm:            mips.ASYNC,
 +              reg:            regInfo{},
 +      },
 +      {
 +              name:    "LoweredPanicBoundsRR",
 +              auxType: auxInt64,
 +              argLen:  3,
 +              call:    true,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 131070}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16
 +                              {1, 131070}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16
 +                      },
 +              },
 +      },
 +      {
 +              name:    "LoweredPanicBoundsRC",
 +              auxType: auxPanicBoundsC,
 +              argLen:  2,
 +              call:    true,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 131070}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16
 +                      },
 +              },
 +      },
 +      {
 +              name:    "LoweredPanicBoundsCR",
 +              auxType: auxPanicBoundsC,
 +              argLen:  2,
 +              call:    true,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 131070}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16
 +                      },
 +              },
 +      },
 +      {
 +              name:    "LoweredPanicBoundsCC",
 +              auxType: auxPanicBoundsCC,
 +              argLen:  1,
 +              call:    true,
 +              reg:     regInfo{},
 +      },
 +
 +      {
 +              name:        "ADD",
 +              argLen:      2,
 +              commutative: true,
 +              asm:         ppc64.AADD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                              {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +              },
 +      },
 +      {
 +              name:        "ADDCC",
 +              argLen:      2,
 +              commutative: true,
 +              asm:         ppc64.AADDCC,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                              {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +              },
 +      },
 +      {
 +              name:    "ADDconst",
 +              auxType: auxInt64,
 +              argLen:  1,
 +              asm:     ppc64.AADD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +              },
 +      },
 +      {
 +              name:    "ADDCCconst",
 +              auxType: auxInt64,
 +              argLen:  1,
 +              asm:     ppc64.AADDCCC,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +                      clobbers: 9223372036854775808, // XER
 +                      outputs: []outputInfo{
 +                              {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +              },
 +      },
 +      {
 +              name:        "FADD",
 +              argLen:      2,
 +              commutative: true,
 +              asm:         ppc64.AFADD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
 +                              {1, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
 +                      },
 +              },
 +      },
 +      {
 +              name:        "FADDS",
 +              argLen:      2,
 +              commutative: true,
 +              asm:         ppc64.AFADDS,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
 +                              {1, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
 +                      },
 +              },
 +      },
 +      {
 +              name:   "SUB",
 +              argLen: 2,
 +              asm:    ppc64.ASUB,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                              {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +              },
 +      },
 +      {
 +              name:   "SUBCC",
 +              argLen: 2,
 +              asm:    ppc64.ASUBCC,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                              {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +              },
 +      },
 +      {
 +              name:    "SUBFCconst",
 +              auxType: auxInt64,
 +              argLen:  1,
 +              asm:     ppc64.ASUBC,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +                      clobbers: 9223372036854775808, // XER
 +                      outputs: []outputInfo{
 +                              {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +              },
 +      },
 +      {
 +              name:   "FSUB",
 +              argLen: 2,
 +              asm:    ppc64.AFSUB,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
 +                              {1, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
 +                      },
 +              },
 +      },
 +      {
 +              name:   "FSUBS",
 +              argLen: 2,
 +              asm:    ppc64.AFSUBS,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
 +                              {1, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
 +                      },
 +              },
 +      },
 +      {
 +              name:   "XSMINJDP",
 +              argLen: 2,
 +              asm:    ppc64.AXSMINJDP,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
 +                              {1, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
 +                      },
 +              },
 +      },
 +      {
 +              name:   "XSMAXJDP",
 +              argLen: 2,
 +              asm:    ppc64.AXSMAXJDP,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
 +                              {1, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
 +                      },
 +              },
 +      },
 +      {
 +              name:        "MULLD",
 +              argLen:      2,
 +              commutative: true,
 +              asm:         ppc64.AMULLD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                              {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +              },
 +      },
 +      {
 +              name:        "MULLW",
 +              argLen:      2,
 +              commutative: true,
 +              asm:         ppc64.AMULLW,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                              {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +              },
 +      },
 +      {
 +              name:    "MULLDconst",
 +              auxType: auxInt32,
 +              argLen:  1,
 +              asm:     ppc64.AMULLD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +              },
 +      },
 +      {
 +              name:    "MULLWconst",
 +              auxType: auxInt32,
 +              argLen:  1,
 +              asm:     ppc64.AMULLW,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +              },
 +      },
 +      {
 +              name:   "MADDLD",
 +              argLen: 3,
 +              asm:    ppc64.AMADDLD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                              {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                              {2, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +              },
 +      },
 +      {
 +              name:        "MULHD",
 +              argLen:      2,
 +              commutative: true,
 +              asm:         ppc64.AMULHD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                              {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +              },
 +      },
 +      {
 +              name:        "MULHW",
 +              argLen:      2,
 +              commutative: true,
 +              asm:         ppc64.AMULHW,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                              {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +              },
 +      },
 +      {
 +              name:        "MULHDU",
 +              argLen:      2,
 +              commutative: true,
 +              asm:         ppc64.AMULHDU,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                              {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +              },
 +      },
 +      {
 +              name:        "MULHDUCC",
 +              argLen:      2,
 +              commutative: true,
 +              asm:         ppc64.AMULHDUCC,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                              {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +              },
 +      },
 +      {
 +              name:        "MULHWU",
 +              argLen:      2,
 +              commutative: true,
 +              asm:         ppc64.AMULHWU,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                              {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +              },
 +      },
 +      {
 +              name:        "FMUL",
 +              argLen:      2,
 +              commutative: true,
 +              asm:         ppc64.AFMUL,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
 +                              {1, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
 +                      },
 +              },
 +      },
 +      {
 +              name:        "FMULS",
 +              argLen:      2,
 +              commutative: true,
 +              asm:         ppc64.AFMULS,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
 +                              {1, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
 +                      },
 +              },
 +      },
 +      {
 +              name:   "FMADD",
 +              argLen: 3,
 +              asm:    ppc64.AFMADD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
 +                              {1, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
 +                              {2, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
 +                      },
 +              },
 +      },
 +      {
 +              name:   "FMADDS",
 +              argLen: 3,
 +              asm:    ppc64.AFMADDS,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
 +                              {1, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
 +                              {2, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
 +                      },
 +              },
 +      },
 +      {
 +              name:   "FMSUB",
 +              argLen: 3,
 +              asm:    ppc64.AFMSUB,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
 +                              {1, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
 +                              {2, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
 +                      },
 +              },
 +      },
 +      {
 +              name:   "FMSUBS",
 +              argLen: 3,
 +              asm:    ppc64.AFMSUBS,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
 +                              {1, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
 +                              {2, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
 +                      },
 +              },
 +      },
 +      {
 +              name:   "SRAD",
 +              argLen: 2,
 +              asm:    ppc64.ASRAD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                              {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +                      clobbers: 9223372036854775808, // XER
 +                      outputs: []outputInfo{
 +                              {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +              },
 +      },
 +      {
 +              name:   "SRAW",
 +              argLen: 2,
 +              asm:    ppc64.ASRAW,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                              {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +                      clobbers: 9223372036854775808, // XER
 +                      outputs: []outputInfo{
 +                              {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +              },
 +      },
 +      {
 +              name:   "SRD",
 +              argLen: 2,
 +              asm:    ppc64.ASRD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                              {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +              },
 +      },
 +      {
 +              name:   "SRW",
 +              argLen: 2,
 +              asm:    ppc64.ASRW,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                              {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +              },
 +      },
 +      {
 +              name:   "SLD",
 +              argLen: 2,
 +              asm:    ppc64.ASLD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                              {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +              },
 +      },
 +      {
 +              name:   "SLW",
 +              argLen: 2,
 +              asm:    ppc64.ASLW,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                              {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +              },
 +      },
 +      {
 +              name:   "ROTL",
 +              argLen: 2,
 +              asm:    ppc64.AROTL,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                              {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +              },
 +      },
 +      {
 +              name:   "ROTLW",
 +              argLen: 2,
 +              asm:    ppc64.AROTLW,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                              {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +              },
 +      },
 +      {
 +              name:    "CLRLSLWI",
 +              auxType: auxInt32,
 +              argLen:  1,
 +              asm:     ppc64.ACLRLSLWI,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +              },
 +      },
 +      {
 +              name:    "CLRLSLDI",
 +              auxType: auxInt32,
 +              argLen:  1,
 +              asm:     ppc64.ACLRLSLDI,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +              },
 +      },
 +      {
 +              name:        "ADDC",
 +              argLen:      2,
 +              commutative: true,
 +              asm:         ppc64.AADDC,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                              {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +                      clobbers: 9223372036854775808, // XER
 +                      outputs: []outputInfo{
 +                              {1, 9223372036854775808}, // XER
 +                              {0, 1073733624},          // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +              },
 +      },
 +      {
 +              name:   "SUBC",
 +              argLen: 2,
 +              asm:    ppc64.ASUBC,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                              {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +                      clobbers: 9223372036854775808, // XER
 +                      outputs: []outputInfo{
 +                              {1, 9223372036854775808}, // XER
 +                              {0, 1073733624},          // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +              },
 +      },
 +      {
 +              name:    "ADDCconst",
 +              auxType: auxInt64,
 +              argLen:  1,
 +              asm:     ppc64.AADDC,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +                      outputs: []outputInfo{
 +                              {1, 9223372036854775808}, // XER
 +                              {0, 1073733624},          // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +              },
 +      },
 +      {
 +              name:    "SUBCconst",
 +              auxType: auxInt64,
 +              argLen:  1,
 +              asm:     ppc64.ASUBC,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +                      outputs: []outputInfo{
 +                              {1, 9223372036854775808}, // XER
 +                              {0, 1073733624},          // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +              },
 +      },
 +      {
 +              name:        "ADDE",
 +              argLen:      3,
 +              commutative: true,
 +              asm:         ppc64.AADDE,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {2, 9223372036854775808}, // XER
 +                              {0, 1073733630},          // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                              {1, 1073733630},          // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +                      clobbers: 9223372036854775808, // XER
 +                      outputs: []outputInfo{
 +                              {1, 9223372036854775808}, // XER
 +                              {0, 1073733624},          // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +              },
 +      },
 +      {
 +              name:   "ADDZE",
 +              argLen: 2,
 +              asm:    ppc64.AADDZE,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 9223372036854775808}, // XER
 +                              {0, 1073733630},          // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +                      clobbers: 9223372036854775808, // XER
 +                      outputs: []outputInfo{
 +                              {1, 9223372036854775808}, // XER
 +                              {0, 1073733624},          // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +              },
 +      },
 +      {
 +              name:   "SUBE",
 +              argLen: 3,
 +              asm:    ppc64.ASUBE,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {2, 9223372036854775808}, // XER
 +                              {0, 1073733630},          // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                              {1, 1073733630},          // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +                      clobbers: 9223372036854775808, // XER
 +                      outputs: []outputInfo{
 +                              {1, 9223372036854775808}, // XER
 +                              {0, 1073733624},          // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +              },
 +      },
 +      {
 +              name:   "ADDZEzero",
 +              argLen: 1,
 +              asm:    ppc64.AADDZE,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 9223372036854775808}, // XER
 +                      },
 +                      clobbers: 9223372036854775808, // XER
 +                      outputs: []outputInfo{
 +                              {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +              },
 +      },
 +      {
 +              name:   "SUBZEzero",
 +              argLen: 1,
 +              asm:    ppc64.ASUBZE,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 9223372036854775808}, // XER
 +                      },
 +                      clobbers: 9223372036854775808, // XER
 +                      outputs: []outputInfo{
 +                              {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +              },
 +      },
 +      {
 +              name:    "SRADconst",
 +              auxType: auxInt64,
 +              argLen:  1,
 +              asm:     ppc64.ASRAD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +                      clobbers: 9223372036854775808, // XER
 +                      outputs: []outputInfo{
 +                              {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +              },
 +      },
 +      {
 +              name:    "SRAWconst",
 +              auxType: auxInt64,
 +              argLen:  1,
 +              asm:     ppc64.ASRAW,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +                      clobbers: 9223372036854775808, // XER
 +                      outputs: []outputInfo{
 +                              {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +              },
 +      },
 +      {
 +              name:    "SRDconst",
 +              auxType: auxInt64,
 +              argLen:  1,
 +              asm:     ppc64.ASRD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +              },
 +      },
 +      {
 +              name:    "SRWconst",
 +              auxType: auxInt64,
 +              argLen:  1,
 +              asm:     ppc64.ASRW,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +              },
 +      },
 +      {
 +              name:    "SLDconst",
 +              auxType: auxInt64,
 +              argLen:  1,
 +              asm:     ppc64.ASLD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +              },
 +      },
 +      {
 +              name:    "SLWconst",
 +              auxType: auxInt64,
 +              argLen:  1,
 +              asm:     ppc64.ASLW,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +              },
 +      },
 +      {
 +              name:    "ROTLconst",
 +              auxType: auxInt64,
 +              argLen:  1,
 +              asm:     ppc64.AROTL,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +              },
 +      },
 +      {
 +              name:    "ROTLWconst",
 +              auxType: auxInt64,
 +              argLen:  1,
 +              asm:     ppc64.AROTLW,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +              },
 +      },
 +      {
 +              name:    "EXTSWSLconst",
 +              auxType: auxInt64,
 +              argLen:  1,
 +              asm:     ppc64.AEXTSWSLI,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +              },
 +      },
 +      {
 +              name:    "RLWINM",
 +              auxType: auxInt64,
 +              argLen:  1,
 +              asm:     ppc64.ARLWNM,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +              },
 +      },
 +      {
 +              name:    "RLWNM",
 +              auxType: auxInt64,
 +              argLen:  2,
 +              asm:     ppc64.ARLWNM,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                              {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +              },
 +      },
 +      {
 +              name:         "RLWMI",
 +              auxType:      auxInt64,
 +              argLen:       2,
 +              resultInArg0: true,
 +              asm:          ppc64.ARLWMI,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                              {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +              },
 +      },
 +      {
 +              name:    "RLDICL",
 +              auxType: auxInt64,
 +              argLen:  1,
 +              asm:     ppc64.ARLDICL,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +              },
 +      },
 +      {
 +              name:    "RLDICLCC",
 +              auxType: auxInt64,
 +              argLen:  1,
 +              asm:     ppc64.ARLDICLCC,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +              },
 +      },
 +      {
 +              name:    "RLDICR",
 +              auxType: auxInt64,
 +              argLen:  1,
 +              asm:     ppc64.ARLDICR,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +              },
 +      },
 +      {
 +              name:   "CNTLZD",
 +              argLen: 1,
 +              asm:    ppc64.ACNTLZD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +              },
 +      },
 +      {
 +              name:   "CNTLZDCC",
 +              argLen: 1,
 +              asm:    ppc64.ACNTLZDCC,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +              },
 +      },
 +      {
 +              name:   "CNTLZW",
 +              argLen: 1,
 +              asm:    ppc64.ACNTLZW,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +              },
 +      },
 +      {
 +              name:   "CNTTZD",
 +              argLen: 1,
 +              asm:    ppc64.ACNTTZD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +              },
 +      },
 +      {
 +              name:   "CNTTZW",
 +              argLen: 1,
 +              asm:    ppc64.ACNTTZW,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +              },
 +      },
 +      {
 +              name:   "POPCNTD",
 +              argLen: 1,
 +              asm:    ppc64.APOPCNTD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +              },
 +      },
 +      {
 +              name:   "POPCNTW",
 +              argLen: 1,
 +              asm:    ppc64.APOPCNTW,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +              },
 +      },
 +      {
 +              name:   "POPCNTB",
 +              argLen: 1,
 +              asm:    ppc64.APOPCNTB,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +              },
 +      },
 +      {
 +              name:   "FDIV",
 +              argLen: 2,
 +              asm:    ppc64.AFDIV,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
 +                              {1, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
 +                      },
 +              },
 +      },
 +      {
 +              name:   "FDIVS",
 +              argLen: 2,
 +              asm:    ppc64.AFDIVS,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
 +                              {1, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
 +                      },
 +              },
 +      },
 +      {
 +              name:   "DIVD",
 +              argLen: 2,
 +              asm:    ppc64.ADIVD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                              {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +              },
 +      },
 +      {
 +              name:   "DIVW",
 +              argLen: 2,
 +              asm:    ppc64.ADIVW,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                              {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +              },
 +      },
 +      {
 +              name:   "DIVDU",
 +              argLen: 2,
 +              asm:    ppc64.ADIVDU,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                              {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +              },
 +      },
 +      {
 +              name:   "DIVWU",
 +              argLen: 2,
 +              asm:    ppc64.ADIVWU,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                              {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +              },
 +      },
 +      {
 +              name:   "MODUD",
 +              argLen: 2,
 +              asm:    ppc64.AMODUD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                              {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +              },
 +      },
 +      {
 +              name:   "MODSD",
 +              argLen: 2,
 +              asm:    ppc64.AMODSD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                              {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +              },
 +      },
 +      {
 +              name:   "MODUW",
 +              argLen: 2,
 +              asm:    ppc64.AMODUW,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                              {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +              },
 +      },
 +      {
 +              name:   "MODSW",
 +              argLen: 2,
 +              asm:    ppc64.AMODSW,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                              {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +              },
 +      },
 +      {
 +              name:   "FCTIDZ",
 +              argLen: 1,
 +              asm:    ppc64.AFCTIDZ,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
 +                      },
 +              },
 +      },
 +      {
 +              name:   "FCTIWZ",
 +              argLen: 1,
 +              asm:    ppc64.AFCTIWZ,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
 +                      },
 +              },
 +      },
 +      {
 +              name:   "FCFID",
 +              argLen: 1,
 +              asm:    ppc64.AFCFID,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
 +                      },
 +              },
 +      },
 +      {
 +              name:   "FCFIDS",
 +              argLen: 1,
 +              asm:    ppc64.AFCFIDS,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
 +                      },
 +              },
 +      },
 +      {
 +              name:   "FRSP",
 +              argLen: 1,
 +              asm:    ppc64.AFRSP,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
 +                      },
 +              },
 +      },
 +      {
 +              name:   "MFVSRD",
 +              argLen: 1,
 +              asm:    ppc64.AMFVSRD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +              },
 +      },
 +      {
 +              name:   "MTVSRD",
 +              argLen: 1,
 +              asm:    ppc64.AMTVSRD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
 +                      },
 +              },
 +      },
 +      {
 +              name:        "AND",
 +              argLen:      2,
 +              commutative: true,
 +              asm:         ppc64.AAND,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                              {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +              },
 +      },
 +      {
 +              name:   "ANDN",
 +              argLen: 2,
 +              asm:    ppc64.AANDN,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                              {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +              },
 +      },
 +      {
 +              name:   "ANDNCC",
 +              argLen: 2,
 +              asm:    ppc64.AANDNCC,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                              {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +              },
 +      },
 +      {
 +              name:        "ANDCC",
 +              argLen:      2,
 +              commutative: true,
 +              asm:         ppc64.AANDCC,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                              {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +              },
 +      },
 +      {
 +              name:        "OR",
 +              argLen:      2,
 +              commutative: true,
 +              asm:         ppc64.AOR,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                              {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +              },
 +      },
 +      {
 +              name:   "ORN",
 +              argLen: 2,
 +              asm:    ppc64.AORN,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                              {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +              },
 +      },
 +      {
 +              name:        "ORCC",
 +              argLen:      2,
 +              commutative: true,
 +              asm:         ppc64.AORCC,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                              {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +              },
 +      },
 +      {
 +              name:        "NOR",
 +              argLen:      2,
 +              commutative: true,
 +              asm:         ppc64.ANOR,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                              {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +              },
 +      },
 +      {
 +              name:        "NORCC",
 +              argLen:      2,
 +              commutative: true,
 +              asm:         ppc64.ANORCC,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                              {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +              },
 +      },
 +      {
 +              name:        "XOR",
 +              argLen:      2,
 +              commutative: true,
 +              asm:         ppc64.AXOR,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                              {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +              },
 +      },
 +      {
 +              name:        "XORCC",
 +              argLen:      2,
 +              commutative: true,
 +              asm:         ppc64.AXORCC,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                              {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +              },
 +      },
 +      {
 +              name:        "EQV",
 +              argLen:      2,
 +              commutative: true,
 +              asm:         ppc64.AEQV,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                              {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +              },
 +      },
 +      {
 +              name:   "NEG",
 +              argLen: 1,
 +              asm:    ppc64.ANEG,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +              },
 +      },
 +      {
 +              name:   "NEGCC",
 +              argLen: 1,
 +              asm:    ppc64.ANEGCC,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +              },
 +      },
 +      {
 +              name:   "BRD",
 +              argLen: 1,
 +              asm:    ppc64.ABRD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +              },
 +      },
 +      {
 +              name:   "BRW",
 +              argLen: 1,
 +              asm:    ppc64.ABRW,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +              },
 +      },
 +      {
 +              name:   "BRH",
 +              argLen: 1,
 +              asm:    ppc64.ABRH,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +              },
 +      },
 +      {
 +              name:   "FNEG",
 +              argLen: 1,
 +              asm:    ppc64.AFNEG,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
 +                      },
 +              },
 +      },
 +      {
 +              name:   "FSQRT",
 +              argLen: 1,
 +              asm:    ppc64.AFSQRT,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
 +                      },
 +              },
 +      },
 +      {
 +              name:   "FSQRTS",
 +              argLen: 1,
 +              asm:    ppc64.AFSQRTS,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
 +                      },
 +              },
 +      },
 +      {
 +              name:   "FFLOOR",
 +              argLen: 1,
 +              asm:    ppc64.AFRIM,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
 +                      },
 +              },
 +      },
 +      {
 +              name:   "FCEIL",
 +              argLen: 1,
 +              asm:    ppc64.AFRIP,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
 +                      },
 +              },
 +      },
 +      {
 +              name:   "FTRUNC",
 +              argLen: 1,
 +              asm:    ppc64.AFRIZ,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
 +                      },
 +              },
 +      },
 +      {
 +              name:   "FROUND",
 +              argLen: 1,
 +              asm:    ppc64.AFRIN,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
 +                      },
 +              },
 +      },
 +      {
 +              name:   "FABS",
 +              argLen: 1,
 +              asm:    ppc64.AFABS,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
 +                      },
 +              },
 +      },
 +      {
 +              name:   "FNABS",
 +              argLen: 1,
 +              asm:    ppc64.AFNABS,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
 +                      },
 +              },
 +      },
 +      {
 +              name:   "FCPSGN",
 +              argLen: 2,
 +              asm:    ppc64.AFCPSGN,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
 +                              {1, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
 +                      },
 +              },
 +      },
 +      {
 +              name:    "ORconst",
 +              auxType: auxInt64,
 +              argLen:  1,
 +              asm:     ppc64.AOR,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +              },
 +      },
 +      {
 +              name:    "XORconst",
 +              auxType: auxInt64,
 +              argLen:  1,
 +              asm:     ppc64.AXOR,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +              },
 +      },
 +      {
 +              name:    "ANDCCconst",
 +              auxType: auxInt64,
 +              argLen:  1,
 +              asm:     ppc64.AANDCC,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +              },
 +      },
 +      {
 +              name:         "ANDconst",
 +              auxType:      auxInt64,
 +              argLen:       1,
 +              clobberFlags: true,
 +              asm:          ppc64.AANDCC,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +              },
 +      },
 +      {
 +              name:   "MOVBreg",
 +              argLen: 1,
 +              asm:    ppc64.AMOVB,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +              },
 +      },
 +      {
 +              name:   "MOVBZreg",
 +              argLen: 1,
 +              asm:    ppc64.AMOVBZ,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +              },
 +      },
 +      {
 +              name:   "MOVHreg",
 +              argLen: 1,
 +              asm:    ppc64.AMOVH,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +              },
 +      },
 +      {
 +              name:   "MOVHZreg",
 +              argLen: 1,
 +              asm:    ppc64.AMOVHZ,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +              },
 +      },
 +      {
 +              name:   "MOVWreg",
 +              argLen: 1,
 +              asm:    ppc64.AMOVW,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +              },
 +      },
 +      {
 +              name:   "MOVWZreg",
 +              argLen: 1,
 +              asm:    ppc64.AMOVWZ,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +              },
 +      },
 +      {
 +              name:           "MOVBZload",
 +              auxType:        auxSymOff,
 +              argLen:         2,
 +              faultOnNilArg0: true,
 +              symEffect:      SymRead,
 +              asm:            ppc64.AMOVBZ,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +              },
 +      },
 +      {
 +              name:           "MOVHload",
 +              auxType:        auxSymOff,
 +              argLen:         2,
 +              faultOnNilArg0: true,
 +              symEffect:      SymRead,
 +              asm:            ppc64.AMOVH,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +              },
 +      },
 +      {
 +              name:           "MOVHZload",
 +              auxType:        auxSymOff,
 +              argLen:         2,
 +              faultOnNilArg0: true,
 +              symEffect:      SymRead,
 +              asm:            ppc64.AMOVHZ,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +              },
 +      },
 +      {
 +              name:           "MOVWload",
 +              auxType:        auxSymOff,
 +              argLen:         2,
 +              faultOnNilArg0: true,
 +              symEffect:      SymRead,
 +              asm:            ppc64.AMOVW,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +              },
 +      },
 +      {
 +              name:           "MOVWZload",
 +              auxType:        auxSymOff,
 +              argLen:         2,
 +              faultOnNilArg0: true,
 +              symEffect:      SymRead,
 +              asm:            ppc64.AMOVWZ,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +              },
 +      },
 +      {
 +              name:           "MOVDload",
 +              auxType:        auxSymOff,
 +              argLen:         2,
 +              faultOnNilArg0: true,
 +              symEffect:      SymRead,
 +              asm:            ppc64.AMOVD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +              },
 +      },
 +      {
 +              name:           "MOVDBRload",
 +              argLen:         2,
 +              faultOnNilArg0: true,
 +              asm:            ppc64.AMOVDBR,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +              },
 +      },
 +      {
 +              name:           "MOVWBRload",
 +              argLen:         2,
 +              faultOnNilArg0: true,
 +              asm:            ppc64.AMOVWBR,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +              },
 +      },
 +      {
 +              name:           "MOVHBRload",
 +              argLen:         2,
 +              faultOnNilArg0: true,
 +              asm:            ppc64.AMOVHBR,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +              },
 +      },
 +      {
 +              name:   "MOVBZloadidx",
 +              argLen: 3,
 +              asm:    ppc64.AMOVBZ,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                              {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +              },
 +      },
 +      {
 +              name:   "MOVHloadidx",
 +              argLen: 3,
 +              asm:    ppc64.AMOVH,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                              {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +              },
 +      },
 +      {
 +              name:   "MOVHZloadidx",
 +              argLen: 3,
 +              asm:    ppc64.AMOVHZ,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                              {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +              },
 +      },
 +      {
 +              name:   "MOVWloadidx",
 +              argLen: 3,
 +              asm:    ppc64.AMOVW,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                              {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +              },
 +      },
 +      {
 +              name:   "MOVWZloadidx",
 +              argLen: 3,
 +              asm:    ppc64.AMOVWZ,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                              {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +              },
 +      },
 +      {
 +              name:   "MOVDloadidx",
 +              argLen: 3,
 +              asm:    ppc64.AMOVD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                              {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +              },
 +      },
 +      {
 +              name:   "MOVHBRloadidx",
 +              argLen: 3,
 +              asm:    ppc64.AMOVHBR,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                              {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +              },
 +      },
 +      {
 +              name:   "MOVWBRloadidx",
 +              argLen: 3,
 +              asm:    ppc64.AMOVWBR,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                              {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +              },
 +      },
 +      {
 +              name:   "MOVDBRloadidx",
 +              argLen: 3,
 +              asm:    ppc64.AMOVDBR,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                              {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +              },
 +      },
 +      {
 +              name:   "FMOVDloadidx",
 +              argLen: 3,
 +              asm:    ppc64.AFMOVD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                              {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
 +                      },
 +              },
 +      },
 +      {
 +              name:   "FMOVSloadidx",
 +              argLen: 3,
 +              asm:    ppc64.AFMOVS,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                              {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
 +                      },
 +              },
 +      },
 +      {
 +              name:           "DCBT",
 +              auxType:        auxInt64,
 +              argLen:         2,
 +              hasSideEffects: true,
 +              asm:            ppc64.ADCBT,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +              },
 +      },
 +      {
 +              name:           "MOVDBRstore",
 +              argLen:         3,
 +              faultOnNilArg0: true,
 +              asm:            ppc64.AMOVDBR,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                              {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +              },
 +      },
 +      {
 +              name:           "MOVWBRstore",
 +              argLen:         3,
 +              faultOnNilArg0: true,
 +              asm:            ppc64.AMOVWBR,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                              {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +              },
 +      },
 +      {
 +              name:           "MOVHBRstore",
 +              argLen:         3,
 +              faultOnNilArg0: true,
 +              asm:            ppc64.AMOVHBR,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                              {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +              },
 +      },
 +      {
 +              name:           "FMOVDload",
 +              auxType:        auxSymOff,
 +              argLen:         2,
 +              faultOnNilArg0: true,
 +              symEffect:      SymRead,
 +              asm:            ppc64.AFMOVD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
 +                      },
 +              },
 +      },
 +      {
 +              name:           "FMOVSload",
 +              auxType:        auxSymOff,
 +              argLen:         2,
 +              faultOnNilArg0: true,
 +              symEffect:      SymRead,
 +              asm:            ppc64.AFMOVS,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
 +                      },
 +              },
 +      },
 +      {
 +              name:           "MOVBstore",
 +              auxType:        auxSymOff,
 +              argLen:         3,
 +              faultOnNilArg0: true,
 +              symEffect:      SymWrite,
 +              asm:            ppc64.AMOVB,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                              {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +              },
 +      },
 +      {
 +              name:           "MOVHstore",
 +              auxType:        auxSymOff,
 +              argLen:         3,
 +              faultOnNilArg0: true,
 +              symEffect:      SymWrite,
 +              asm:            ppc64.AMOVH,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                              {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +              },
 +      },
 +      {
 +              name:           "MOVWstore",
 +              auxType:        auxSymOff,
 +              argLen:         3,
 +              faultOnNilArg0: true,
 +              symEffect:      SymWrite,
 +              asm:            ppc64.AMOVW,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                              {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +              },
 +      },
 +      {
 +              name:           "MOVDstore",
 +              auxType:        auxSymOff,
 +              argLen:         3,
 +              faultOnNilArg0: true,
 +              symEffect:      SymWrite,
 +              asm:            ppc64.AMOVD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                              {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +              },
 +      },
 +      {
 +              name:           "FMOVDstore",
 +              auxType:        auxSymOff,
 +              argLen:         3,
 +              faultOnNilArg0: true,
 +              symEffect:      SymWrite,
 +              asm:            ppc64.AFMOVD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1073733630},          // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                              {1, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
 +                      },
 +              },
 +      },
 +      {
 +              name:           "FMOVSstore",
 +              auxType:        auxSymOff,
 +              argLen:         3,
 +              faultOnNilArg0: true,
 +              symEffect:      SymWrite,
 +              asm:            ppc64.AFMOVS,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1073733630},          // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                              {1, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
 +                      },
 +              },
 +      },
 +      {
 +              name:   "MOVBstoreidx",
 +              argLen: 4,
 +              asm:    ppc64.AMOVB,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                              {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                              {2, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +              },
 +      },
 +      {
 +              name:   "MOVHstoreidx",
 +              argLen: 4,
 +              asm:    ppc64.AMOVH,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                              {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                              {2, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +              },
 +      },
 +      {
 +              name:   "MOVWstoreidx",
 +              argLen: 4,
 +              asm:    ppc64.AMOVW,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                              {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                              {2, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +              },
 +      },
 +      {
 +              name:   "MOVDstoreidx",
 +              argLen: 4,
 +              asm:    ppc64.AMOVD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                              {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                              {2, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +              },
 +      },
 +      {
 +              name:   "FMOVDstoreidx",
 +              argLen: 4,
 +              asm:    ppc64.AFMOVD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1073733630},          // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                              {1, 1073733630},          // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                              {2, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
 +                      },
 +              },
 +      },
 +      {
 +              name:   "FMOVSstoreidx",
 +              argLen: 4,
 +              asm:    ppc64.AFMOVS,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1073733630},          // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                              {1, 1073733630},          // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                              {2, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
 +                      },
 +              },
 +      },
 +      {
 +              name:   "MOVHBRstoreidx",
 +              argLen: 4,
 +              asm:    ppc64.AMOVHBR,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                              {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                              {2, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +              },
 +      },
 +      {
 +              name:   "MOVWBRstoreidx",
 +              argLen: 4,
 +              asm:    ppc64.AMOVWBR,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                              {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                              {2, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +              },
 +      },
 +      {
 +              name:   "MOVDBRstoreidx",
 +              argLen: 4,
 +              asm:    ppc64.AMOVDBR,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                              {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                              {2, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +              },
 +      },
 +      {
 +              name:           "MOVBstorezero",
 +              auxType:        auxSymOff,
 +              argLen:         2,
 +              faultOnNilArg0: true,
 +              symEffect:      SymWrite,
 +              asm:            ppc64.AMOVB,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +              },
 +      },
 +      {
 +              name:           "MOVHstorezero",
 +              auxType:        auxSymOff,
 +              argLen:         2,
 +              faultOnNilArg0: true,
 +              symEffect:      SymWrite,
 +              asm:            ppc64.AMOVH,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +              },
 +      },
 +      {
 +              name:           "MOVWstorezero",
 +              auxType:        auxSymOff,
 +              argLen:         2,
 +              faultOnNilArg0: true,
 +              symEffect:      SymWrite,
 +              asm:            ppc64.AMOVW,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +              },
 +      },
 +      {
 +              name:           "MOVDstorezero",
 +              auxType:        auxSymOff,
 +              argLen:         2,
 +              faultOnNilArg0: true,
 +              symEffect:      SymWrite,
 +              asm:            ppc64.AMOVD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +              },
 +      },
 +      {
 +              name:              "MOVDaddr",
 +              auxType:           auxSymOff,
 +              argLen:            1,
 +              rematerializeable: true,
 +              symEffect:         SymAddr,
 +              asm:               ppc64.AMOVD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +              },
 +      },
 +      {
 +              name:              "MOVDconst",
 +              auxType:           auxInt64,
 +              argLen:            0,
 +              rematerializeable: true,
 +              asm:               ppc64.AMOVD,
 +              reg: regInfo{
 +                      outputs: []outputInfo{
 +                              {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +              },
 +      },
 +      {
 +              name:              "FMOVDconst",
 +              auxType:           auxFloat64,
 +              argLen:            0,
 +              rematerializeable: true,
 +              asm:               ppc64.AFMOVD,
 +              reg: regInfo{
 +                      outputs: []outputInfo{
 +                              {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
 +                      },
 +              },
 +      },
 +      {
 +              name:              "FMOVSconst",
 +              auxType:           auxFloat32,
 +              argLen:            0,
 +              rematerializeable: true,
 +              asm:               ppc64.AFMOVS,
 +              reg: regInfo{
 +                      outputs: []outputInfo{
 +                              {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
 +                      },
 +              },
 +      },
 +      {
 +              name:   "FCMPU",
 +              argLen: 2,
 +              asm:    ppc64.AFCMPU,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
 +                              {1, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
 +                      },
 +              },
 +      },
 +      {
 +              name:   "CMP",
 +              argLen: 2,
 +              asm:    ppc64.ACMP,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                              {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +              },
 +      },
 +      {
 +              name:   "CMPU",
 +              argLen: 2,
 +              asm:    ppc64.ACMPU,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                              {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +              },
 +      },
 +      {
 +              name:   "CMPW",
 +              argLen: 2,
 +              asm:    ppc64.ACMPW,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                              {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +              },
 +      },
 +      {
 +              name:   "CMPWU",
 +              argLen: 2,
 +              asm:    ppc64.ACMPWU,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                              {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +              },
 +      },
 +      {
 +              name:    "CMPconst",
 +              auxType: auxInt64,
 +              argLen:  1,
 +              asm:     ppc64.ACMP,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +              },
 +      },
 +      {
 +              name:    "CMPUconst",
 +              auxType: auxInt64,
 +              argLen:  1,
 +              asm:     ppc64.ACMPU,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +              },
 +      },
 +      {
 +              name:    "CMPWconst",
 +              auxType: auxInt32,
 +              argLen:  1,
 +              asm:     ppc64.ACMPW,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +              },
 +      },
 +      {
 +              name:    "CMPWUconst",
 +              auxType: auxInt32,
 +              argLen:  1,
 +              asm:     ppc64.ACMPWU,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +              },
 +      },
 +      {
 +              name:    "ISEL",
 +              auxType: auxInt32,
 +              argLen:  3,
 +              asm:     ppc64.AISEL,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                              {1, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +              },
 +      },
 +      {
 +              name:    "ISELZ",
 +              auxType: auxInt32,
 +              argLen:  2,
 +              asm:     ppc64.AISEL,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +              },
 +      },
 +      {
 +              name:    "SETBC",
 +              auxType: auxInt32,
 +              argLen:  1,
 +              asm:     ppc64.ASETBC,
 +              reg: regInfo{
 +                      outputs: []outputInfo{
 +                              {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +              },
 +      },
 +      {
 +              name:    "SETBCR",
 +              auxType: auxInt32,
 +              argLen:  1,
 +              asm:     ppc64.ASETBCR,
 +              reg: regInfo{
 +                      outputs: []outputInfo{
 +                              {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +              },
 +      },
 +      {
 +              name:   "Equal",
 +              argLen: 1,
 +              reg: regInfo{
 +                      outputs: []outputInfo{
 +                              {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +              },
 +      },
 +      {
 +              name:   "NotEqual",
 +              argLen: 1,
 +              reg: regInfo{
 +                      outputs: []outputInfo{
 +                              {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +              },
 +      },
 +      {
 +              name:   "LessThan",
 +              argLen: 1,
 +              reg: regInfo{
 +                      outputs: []outputInfo{
 +                              {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +              },
 +      },
 +      {
 +              name:   "FLessThan",
 +              argLen: 1,
 +              reg: regInfo{
 +                      outputs: []outputInfo{
 +                              {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +              },
 +      },
 +      {
 +              name:   "LessEqual",
 +              argLen: 1,
 +              reg: regInfo{
 +                      outputs: []outputInfo{
 +                              {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +              },
 +      },
 +      {
 +              name:   "FLessEqual",
 +              argLen: 1,
 +              reg: regInfo{
 +                      outputs: []outputInfo{
 +                              {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +              },
 +      },
 +      {
 +              name:   "GreaterThan",
 +              argLen: 1,
 +              reg: regInfo{
 +                      outputs: []outputInfo{
 +                              {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +              },
 +      },
 +      {
 +              name:   "FGreaterThan",
 +              argLen: 1,
 +              reg: regInfo{
 +                      outputs: []outputInfo{
 +                              {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +              },
 +      },
 +      {
 +              name:   "GreaterEqual",
 +              argLen: 1,
 +              reg: regInfo{
 +                      outputs: []outputInfo{
 +                              {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +              },
 +      },
 +      {
 +              name:   "FGreaterEqual",
 +              argLen: 1,
 +              reg: regInfo{
 +                      outputs: []outputInfo{
 +                              {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +              },
 +      },
 +      {
 +              name:      "LoweredGetClosurePtr",
 +              argLen:    0,
 +              zeroWidth: true,
 +              reg: regInfo{
 +                      outputs: []outputInfo{
 +                              {0, 2048}, // R11
 +                      },
 +              },
 +      },
 +      {
 +              name:              "LoweredGetCallerSP",
 +              argLen:            1,
 +              rematerializeable: true,
 +              reg: regInfo{
 +                      outputs: []outputInfo{
 +                              {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +              },
 +      },
 +      {
 +              name:              "LoweredGetCallerPC",
 +              argLen:            0,
 +              rematerializeable: true,
 +              reg: regInfo{
 +                      outputs: []outputInfo{
 +                              {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +              },
 +      },
 +      {
 +              name:           "LoweredNilCheck",
 +              argLen:         2,
 +              clobberFlags:   true,
 +              nilCheck:       true,
 +              faultOnNilArg0: true,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +                      clobbers: 2147483648, // R31
 +              },
 +      },
 +      {
 +              name:         "LoweredRound32F",
 +              argLen:       1,
 +              resultInArg0: true,
 +              zeroWidth:    true,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
 +                      },
 +              },
 +      },
 +      {
 +              name:         "LoweredRound64F",
 +              argLen:       1,
 +              resultInArg0: true,
 +              zeroWidth:    true,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
 +                      },
 +              },
 +      },
 +      {
 +              name:         "CALLstatic",
 +              auxType:      auxCallOff,
 +              argLen:       -1,
 +              clobberFlags: true,
 +              call:         true,
 +              reg: regInfo{
 +                      clobbers: 18446744071562059768, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 g F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 XER
 +              },
 +      },
 +      {
 +              name:         "CALLtail",
 +              auxType:      auxCallOff,
 +              argLen:       -1,
 +              clobberFlags: true,
 +              call:         true,
 +              tailCall:     true,
 +              reg: regInfo{
 +                      clobbers: 18446744071562059768, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 g F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 XER
 +              },
 +      },
 +      {
 +              name:         "CALLclosure",
 +              auxType:      auxCallOff,
 +              argLen:       -1,
 +              clobberFlags: true,
 +              call:         true,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 4096}, // R12
 +                              {1, 2048}, // R11
 +                      },
 +                      clobbers: 18446744071562059768, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 g F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 XER
 +              },
 +      },
 +      {
 +              name:         "CALLinter",
 +              auxType:      auxCallOff,
 +              argLen:       -1,
 +              clobberFlags: true,
 +              call:         true,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 4096}, // R12
 +                      },
 +                      clobbers: 18446744071562059768, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 g F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 XER
 +              },
 +      },
 +      {
 +              name:           "LoweredZero",
 +              auxType:        auxInt64,
 +              argLen:         2,
 +              clobberFlags:   true,
 +              faultOnNilArg0: true,
 +              unsafePoint:    true,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1048576}, // R20
 +                      },
 +                      clobbers: 1048576, // R20
 +              },
 +      },
 +      {
 +              name:           "LoweredZeroShort",
 +              auxType:        auxInt64,
 +              argLen:         2,
 +              faultOnNilArg0: true,
 +              unsafePoint:    true,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +              },
 +      },
 +      {
 +              name:           "LoweredQuadZeroShort",
 +              auxType:        auxInt64,
 +              argLen:         2,
 +              faultOnNilArg0: true,
 +              unsafePoint:    true,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +              },
 +      },
 +      {
 +              name:           "LoweredQuadZero",
 +              auxType:        auxInt64,
 +              argLen:         2,
 +              clobberFlags:   true,
 +              faultOnNilArg0: true,
 +              unsafePoint:    true,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1048576}, // R20
 +                      },
 +                      clobbers: 1048576, // R20
 +              },
 +      },
 +      {
 +              name:           "LoweredMove",
 +              auxType:        auxInt64,
 +              argLen:         3,
 +              clobberFlags:   true,
 +              faultOnNilArg0: true,
 +              faultOnNilArg1: true,
 +              unsafePoint:    true,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1048576}, // R20
 +                              {1, 2097152}, // R21
 +                      },
 +                      clobbers: 3145728, // R20 R21
 +              },
 +      },
 +      {
 +              name:           "LoweredMoveShort",
 +              auxType:        auxInt64,
 +              argLen:         3,
 +              faultOnNilArg0: true,
 +              faultOnNilArg1: true,
 +              unsafePoint:    true,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                              {1, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +              },
 +      },
 +      {
 +              name:           "LoweredQuadMove",
 +              auxType:        auxInt64,
 +              argLen:         3,
 +              clobberFlags:   true,
 +              faultOnNilArg0: true,
 +              faultOnNilArg1: true,
 +              unsafePoint:    true,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1048576}, // R20
 +                              {1, 2097152}, // R21
 +                      },
 +                      clobbers: 3145728, // R20 R21
 +              },
 +      },
 +      {
 +              name:           "LoweredQuadMoveShort",
 +              auxType:        auxInt64,
 +              argLen:         3,
 +              faultOnNilArg0: true,
 +              faultOnNilArg1: true,
 +              unsafePoint:    true,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                              {1, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +              },
 +      },
 +      {
 +              name:           "LoweredAtomicStore8",
 +              auxType:        auxInt64,
 +              argLen:         3,
 +              faultOnNilArg0: true,
 +              hasSideEffects: true,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                              {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +              },
 +      },
 +      {
 +              name:           "LoweredAtomicStore32",
 +              auxType:        auxInt64,
 +              argLen:         3,
 +              faultOnNilArg0: true,
 +              hasSideEffects: true,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                              {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +              },
 +      },
 +      {
 +              name:           "LoweredAtomicStore64",
 +              auxType:        auxInt64,
 +              argLen:         3,
 +              faultOnNilArg0: true,
 +              hasSideEffects: true,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                              {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +              },
 +      },
 +      {
 +              name:           "LoweredAtomicLoad8",
 +              auxType:        auxInt64,
 +              argLen:         2,
 +              clobberFlags:   true,
 +              faultOnNilArg0: true,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +              },
 +      },
 +      {
 +              name:           "LoweredAtomicLoad32",
 +              auxType:        auxInt64,
 +              argLen:         2,
 +              clobberFlags:   true,
 +              faultOnNilArg0: true,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +              },
 +      },
 +      {
 +              name:           "LoweredAtomicLoad64",
 +              auxType:        auxInt64,
 +              argLen:         2,
 +              clobberFlags:   true,
 +              faultOnNilArg0: true,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +              },
 +      },
 +      {
 +              name:           "LoweredAtomicLoadPtr",
 +              auxType:        auxInt64,
 +              argLen:         2,
 +              clobberFlags:   true,
 +              faultOnNilArg0: true,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +              },
 +      },
 +      {
 +              name:            "LoweredAtomicAdd32",
 +              argLen:          3,
 +              resultNotInArgs: true,
 +              clobberFlags:    true,
 +              faultOnNilArg0:  true,
 +              hasSideEffects:  true,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                              {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +              },
 +      },
 +      {
 +              name:            "LoweredAtomicAdd64",
 +              argLen:          3,
 +              resultNotInArgs: true,
 +              clobberFlags:    true,
 +              faultOnNilArg0:  true,
 +              hasSideEffects:  true,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                              {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +              },
 +      },
 +      {
 +              name:            "LoweredAtomicExchange8",
 +              argLen:          3,
 +              resultNotInArgs: true,
 +              clobberFlags:    true,
 +              faultOnNilArg0:  true,
 +              hasSideEffects:  true,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                              {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +              },
 +      },
 +      {
 +              name:            "LoweredAtomicExchange32",
 +              argLen:          3,
 +              resultNotInArgs: true,
 +              clobberFlags:    true,
 +              faultOnNilArg0:  true,
 +              hasSideEffects:  true,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                              {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +              },
 +      },
 +      {
 +              name:            "LoweredAtomicExchange64",
 +              argLen:          3,
 +              resultNotInArgs: true,
 +              clobberFlags:    true,
 +              faultOnNilArg0:  true,
 +              hasSideEffects:  true,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                              {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +              },
 +      },
 +      {
 +              name:            "LoweredAtomicCas64",
 +              auxType:         auxInt64,
 +              argLen:          4,
 +              resultNotInArgs: true,
 +              clobberFlags:    true,
 +              faultOnNilArg0:  true,
 +              hasSideEffects:  true,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                              {2, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                              {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +              },
 +      },
 +      {
 +              name:            "LoweredAtomicCas32",
 +              auxType:         auxInt64,
 +              argLen:          4,
 +              resultNotInArgs: true,
 +              clobberFlags:    true,
 +              faultOnNilArg0:  true,
 +              hasSideEffects:  true,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                              {2, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                              {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +              },
 +      },
 +      {
 +              name:           "LoweredAtomicAnd8",
 +              argLen:         3,
 +              faultOnNilArg0: true,
 +              hasSideEffects: true,
 +              asm:            ppc64.AAND,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                              {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +              },
 +      },
 +      {
 +              name:           "LoweredAtomicAnd32",
 +              argLen:         3,
 +              faultOnNilArg0: true,
 +              hasSideEffects: true,
 +              asm:            ppc64.AAND,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                              {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +              },
 +      },
 +      {
 +              name:           "LoweredAtomicOr8",
 +              argLen:         3,
 +              faultOnNilArg0: true,
 +              hasSideEffects: true,
 +              asm:            ppc64.AOR,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                              {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +              },
 +      },
 +      {
 +              name:           "LoweredAtomicOr32",
 +              argLen:         3,
 +              faultOnNilArg0: true,
 +              hasSideEffects: true,
 +              asm:            ppc64.AOR,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                              {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
 +                      },
 +              },
 +      },
 +      {
 +              name:         "LoweredWB",
 +              auxType:      auxInt64,
 +              argLen:       1,
 +              clobberFlags: true,
 +              reg: regInfo{
 +                      clobbers: 18446744072632408064, // R11 R12 R18 R19 R22 R23 R24 R25 R26 R27 R28 R29 R31 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 XER
 +                      outputs: []outputInfo{
 +                              {0, 536870912}, // R29
 +                      },
 +              },
 +      },
 +      {
 +              name:           "LoweredPubBarrier",
 +              argLen:         1,
 +              hasSideEffects: true,
 +              asm:            ppc64.ALWSYNC,
 +              reg:            regInfo{},
 +      },
 +      {
 +              name:    "LoweredPanicBoundsRR",
 +              auxType: auxInt64,
 +              argLen:  3,
 +              call:    true,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1016}, // R3 R4 R5 R6 R7 R8 R9
 +                              {1, 1016}, // R3 R4 R5 R6 R7 R8 R9
 +                      },
 +              },
 +      },
 +      {
 +              name:    "LoweredPanicBoundsRC",
 +              auxType: auxPanicBoundsC,
 +              argLen:  2,
 +              call:    true,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1016}, // R3 R4 R5 R6 R7 R8 R9
 +                      },
 +              },
 +      },
 +      {
 +              name:    "LoweredPanicBoundsCR",
 +              auxType: auxPanicBoundsC,
 +              argLen:  2,
 +              call:    true,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1016}, // R3 R4 R5 R6 R7 R8 R9
 +                      },
 +              },
 +      },
 +      {
 +              name:    "LoweredPanicBoundsCC",
 +              auxType: auxPanicBoundsCC,
 +              argLen:  1,
 +              call:    true,
 +              reg:     regInfo{},
 +      },
 +      {
 +              name:   "InvertFlags",
 +              argLen: 1,
 +              reg:    regInfo{},
 +      },
 +      {
 +              name:   "FlagEQ",
 +              argLen: 0,
 +              reg:    regInfo{},
 +      },
 +      {
 +              name:   "FlagLT",
 +              argLen: 0,
 +              reg:    regInfo{},
 +      },
 +      {
 +              name:   "FlagGT",
 +              argLen: 0,
 +              reg:    regInfo{},
 +      },
 +
 +      {
 +              name:        "ADD",
 +              argLen:      2,
 +              commutative: true,
 +              asm:         riscv.AADD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                              {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                      },
 +              },
 +      },
 +      {
 +              name:    "ADDI",
 +              auxType: auxInt64,
 +              argLen:  1,
 +              asm:     riscv.AADDI,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                      },
 +              },
 +      },
 +      {
 +              name:    "ADDIW",
 +              auxType: auxInt64,
 +              argLen:  1,
 +              asm:     riscv.AADDIW,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                      },
 +              },
 +      },
 +      {
 +              name:   "NEG",
 +              argLen: 1,
 +              asm:    riscv.ANEG,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                      },
 +              },
 +      },
 +      {
 +              name:   "NEGW",
 +              argLen: 1,
 +              asm:    riscv.ANEGW,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                      },
 +              },
 +      },
 +      {
 +              name:   "SUB",
 +              argLen: 2,
 +              asm:    riscv.ASUB,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                              {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                      },
 +              },
 +      },
 +      {
 +              name:   "SUBW",
 +              argLen: 2,
 +              asm:    riscv.ASUBW,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                              {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                      },
 +              },
 +      },
 +      {
 +              name:        "MUL",
 +              argLen:      2,
 +              commutative: true,
 +              asm:         riscv.AMUL,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                              {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                      },
 +              },
 +      },
 +      {
 +              name:        "MULW",
 +              argLen:      2,
 +              commutative: true,
 +              asm:         riscv.AMULW,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                              {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                      },
 +              },
 +      },
 +      {
 +              name:        "MULH",
 +              argLen:      2,
 +              commutative: true,
 +              asm:         riscv.AMULH,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                              {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                      },
 +              },
 +      },
 +      {
 +              name:        "MULHU",
 +              argLen:      2,
 +              commutative: true,
 +              asm:         riscv.AMULHU,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                              {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                      },
 +              },
 +      },
 +      {
 +              name:            "LoweredMuluhilo",
 +              argLen:          2,
 +              resultNotInArgs: true,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                              {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                              {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                      },
 +              },
 +      },
 +      {
 +              name:            "LoweredMuluover",
 +              argLen:          2,
 +              resultNotInArgs: true,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                              {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                              {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                      },
 +              },
 +      },
 +      {
 +              name:   "DIV",
 +              argLen: 2,
 +              asm:    riscv.ADIV,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                              {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                      },
 +              },
 +      },
 +      {
 +              name:   "DIVU",
 +              argLen: 2,
 +              asm:    riscv.ADIVU,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                              {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                      },
 +              },
 +      },
 +      {
 +              name:   "DIVW",
 +              argLen: 2,
 +              asm:    riscv.ADIVW,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                              {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                      },
 +              },
 +      },
 +      {
 +              name:   "DIVUW",
 +              argLen: 2,
 +              asm:    riscv.ADIVUW,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                              {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                      },
 +              },
 +      },
 +      {
 +              name:   "REM",
 +              argLen: 2,
 +              asm:    riscv.AREM,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                              {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                      },
 +              },
 +      },
 +      {
 +              name:   "REMU",
 +              argLen: 2,
 +              asm:    riscv.AREMU,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                              {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                      },
 +              },
 +      },
 +      {
 +              name:   "REMW",
 +              argLen: 2,
 +              asm:    riscv.AREMW,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                              {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                      },
 +              },
 +      },
 +      {
 +              name:   "REMUW",
 +              argLen: 2,
 +              asm:    riscv.AREMUW,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                              {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                      },
 +              },
 +      },
 +      {
 +              name:              "MOVaddr",
 +              auxType:           auxSymOff,
 +              argLen:            1,
 +              rematerializeable: true,
 +              symEffect:         SymAddr,
 +              asm:               riscv.AMOV,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                      },
 +              },
 +      },
 +      {
 +              name:              "MOVDconst",
 +              auxType:           auxInt64,
 +              argLen:            0,
 +              rematerializeable: true,
 +              asm:               riscv.AMOV,
 +              reg: regInfo{
 +                      outputs: []outputInfo{
 +                              {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                      },
 +              },
 +      },
 +      {
 +              name:              "FMOVDconst",
 +              auxType:           auxFloat64,
 +              argLen:            0,
 +              rematerializeable: true,
 +              asm:               riscv.AMOVD,
 +              reg: regInfo{
 +                      outputs: []outputInfo{
 +                              {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +              },
 +      },
 +      {
 +              name:              "FMOVFconst",
 +              auxType:           auxFloat32,
 +              argLen:            0,
 +              rematerializeable: true,
 +              asm:               riscv.AMOVF,
 +              reg: regInfo{
 +                      outputs: []outputInfo{
 +                              {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +              },
 +      },
 +      {
 +              name:           "MOVBload",
 +              auxType:        auxSymOff,
 +              argLen:         2,
 +              faultOnNilArg0: true,
 +              symEffect:      SymRead,
 +              asm:            riscv.AMOVB,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                      },
 +              },
 +      },
 +      {
 +              name:           "MOVHload",
 +              auxType:        auxSymOff,
 +              argLen:         2,
 +              faultOnNilArg0: true,
 +              symEffect:      SymRead,
 +              asm:            riscv.AMOVH,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                      },
 +              },
 +      },
 +      {
 +              name:           "MOVWload",
 +              auxType:        auxSymOff,
 +              argLen:         2,
 +              faultOnNilArg0: true,
 +              symEffect:      SymRead,
 +              asm:            riscv.AMOVW,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                      },
 +              },
 +      },
 +      {
 +              name:           "MOVDload",
 +              auxType:        auxSymOff,
 +              argLen:         2,
 +              faultOnNilArg0: true,
 +              symEffect:      SymRead,
 +              asm:            riscv.AMOV,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                      },
 +              },
 +      },
 +      {
 +              name:           "MOVBUload",
 +              auxType:        auxSymOff,
 +              argLen:         2,
 +              faultOnNilArg0: true,
 +              symEffect:      SymRead,
 +              asm:            riscv.AMOVBU,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                      },
 +              },
 +      },
 +      {
 +              name:           "MOVHUload",
 +              auxType:        auxSymOff,
 +              argLen:         2,
 +              faultOnNilArg0: true,
 +              symEffect:      SymRead,
 +              asm:            riscv.AMOVHU,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                      },
 +              },
 +      },
 +      {
 +              name:           "MOVWUload",
 +              auxType:        auxSymOff,
 +              argLen:         2,
 +              faultOnNilArg0: true,
 +              symEffect:      SymRead,
 +              asm:            riscv.AMOVWU,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                      },
 +              },
 +      },
 +      {
 +              name:           "MOVBstore",
 +              auxType:        auxSymOff,
 +              argLen:         3,
 +              faultOnNilArg0: true,
 +              symEffect:      SymWrite,
 +              asm:            riscv.AMOVB,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 1006632946},          // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                              {0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB
 +                      },
 +              },
 +      },
 +      {
 +              name:           "MOVHstore",
 +              auxType:        auxSymOff,
 +              argLen:         3,
 +              faultOnNilArg0: true,
 +              symEffect:      SymWrite,
 +              asm:            riscv.AMOVH,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 1006632946},          // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                              {0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB
 +                      },
 +              },
 +      },
 +      {
 +              name:           "MOVWstore",
 +              auxType:        auxSymOff,
 +              argLen:         3,
 +              faultOnNilArg0: true,
 +              symEffect:      SymWrite,
 +              asm:            riscv.AMOVW,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 1006632946},          // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                              {0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB
 +                      },
 +              },
 +      },
 +      {
 +              name:           "MOVDstore",
 +              auxType:        auxSymOff,
 +              argLen:         3,
 +              faultOnNilArg0: true,
 +              symEffect:      SymWrite,
 +              asm:            riscv.AMOV,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 1006632946},          // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                              {0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB
 +                      },
 +              },
 +      },
 +      {
 +              name:           "MOVBstorezero",
 +              auxType:        auxSymOff,
 +              argLen:         2,
 +              faultOnNilArg0: true,
 +              symEffect:      SymWrite,
 +              asm:            riscv.AMOVB,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB
 +                      },
 +              },
 +      },
 +      {
 +              name:           "MOVHstorezero",
 +              auxType:        auxSymOff,
 +              argLen:         2,
 +              faultOnNilArg0: true,
 +              symEffect:      SymWrite,
 +              asm:            riscv.AMOVH,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB
 +                      },
 +              },
 +      },
 +      {
 +              name:           "MOVWstorezero",
 +              auxType:        auxSymOff,
 +              argLen:         2,
 +              faultOnNilArg0: true,
 +              symEffect:      SymWrite,
 +              asm:            riscv.AMOVW,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB
 +                      },
 +              },
 +      },
 +      {
 +              name:           "MOVDstorezero",
 +              auxType:        auxSymOff,
 +              argLen:         2,
 +              faultOnNilArg0: true,
 +              symEffect:      SymWrite,
 +              asm:            riscv.AMOV,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB
 +                      },
 +              },
 +      },
 +      {
 +              name:   "MOVBreg",
 +              argLen: 1,
 +              asm:    riscv.AMOVB,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                      },
 +              },
 +      },
 +      {
 +              name:   "MOVHreg",
 +              argLen: 1,
 +              asm:    riscv.AMOVH,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                      },
 +              },
 +      },
 +      {
 +              name:   "MOVWreg",
 +              argLen: 1,
 +              asm:    riscv.AMOVW,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                      },
 +              },
 +      },
 +      {
 +              name:   "MOVDreg",
 +              argLen: 1,
 +              asm:    riscv.AMOV,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                      },
 +              },
 +      },
 +      {
 +              name:   "MOVBUreg",
 +              argLen: 1,
 +              asm:    riscv.AMOVBU,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                      },
 +              },
 +      },
 +      {
 +              name:   "MOVHUreg",
 +              argLen: 1,
 +              asm:    riscv.AMOVHU,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                      },
 +              },
 +      },
 +      {
 +              name:   "MOVWUreg",
 +              argLen: 1,
 +              asm:    riscv.AMOVWU,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                      },
 +              },
 +      },
 +      {
 +              name:         "MOVDnop",
 +              argLen:       1,
 +              resultInArg0: true,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                      },
 +              },
 +      },
 +      {
 +              name:   "SLL",
 +              argLen: 2,
 +              asm:    riscv.ASLL,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                              {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                      },
 +              },
 +      },
 +      {
 +              name:   "SLLW",
 +              argLen: 2,
 +              asm:    riscv.ASLLW,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                              {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                      },
 +              },
 +      },
 +      {
 +              name:   "SRA",
 +              argLen: 2,
 +              asm:    riscv.ASRA,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                              {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                      },
 +              },
 +      },
 +      {
 +              name:   "SRAW",
 +              argLen: 2,
 +              asm:    riscv.ASRAW,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                              {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                      },
 +              },
 +      },
 +      {
 +              name:   "SRL",
 +              argLen: 2,
 +              asm:    riscv.ASRL,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                              {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                      },
 +              },
 +      },
 +      {
 +              name:   "SRLW",
 +              argLen: 2,
 +              asm:    riscv.ASRLW,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                              {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                      },
 +              },
 +      },
 +      {
 +              name:    "SLLI",
 +              auxType: auxInt64,
 +              argLen:  1,
 +              asm:     riscv.ASLLI,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                      },
 +              },
 +      },
 +      {
 +              name:    "SLLIW",
 +              auxType: auxInt64,
 +              argLen:  1,
 +              asm:     riscv.ASLLIW,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                      },
 +              },
 +      },
 +      {
 +              name:    "SRAI",
 +              auxType: auxInt64,
 +              argLen:  1,
 +              asm:     riscv.ASRAI,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                      },
 +              },
 +      },
 +      {
 +              name:    "SRAIW",
 +              auxType: auxInt64,
 +              argLen:  1,
 +              asm:     riscv.ASRAIW,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                      },
 +              },
 +      },
 +      {
 +              name:    "SRLI",
 +              auxType: auxInt64,
 +              argLen:  1,
 +              asm:     riscv.ASRLI,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                      },
 +              },
 +      },
 +      {
 +              name:    "SRLIW",
 +              auxType: auxInt64,
 +              argLen:  1,
 +              asm:     riscv.ASRLIW,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                      },
 +              },
 +      },
 +      {
 +              name:   "SH1ADD",
 +              argLen: 2,
 +              asm:    riscv.ASH1ADD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                              {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                      },
 +              },
 +      },
 +      {
 +              name:   "SH2ADD",
 +              argLen: 2,
 +              asm:    riscv.ASH2ADD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                              {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                      },
 +              },
 +      },
 +      {
 +              name:   "SH3ADD",
 +              argLen: 2,
 +              asm:    riscv.ASH3ADD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                              {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                      },
 +              },
 +      },
 +      {
 +              name:        "AND",
 +              argLen:      2,
 +              commutative: true,
 +              asm:         riscv.AAND,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                              {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                      },
 +              },
 +      },
 +      {
 +              name:   "ANDN",
 +              argLen: 2,
 +              asm:    riscv.AANDN,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                              {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                      },
 +              },
 +      },
 +      {
 +              name:    "ANDI",
 +              auxType: auxInt64,
 +              argLen:  1,
 +              asm:     riscv.AANDI,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                      },
 +              },
 +      },
 +      {
 +              name:   "CLZ",
 +              argLen: 1,
 +              asm:    riscv.ACLZ,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                      },
 +              },
 +      },
 +      {
 +              name:   "CLZW",
 +              argLen: 1,
 +              asm:    riscv.ACLZW,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                      },
 +              },
 +      },
 +      {
 +              name:   "CPOP",
 +              argLen: 1,
 +              asm:    riscv.ACPOP,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                      },
 +              },
 +      },
 +      {
 +              name:   "CPOPW",
 +              argLen: 1,
 +              asm:    riscv.ACPOPW,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                      },
 +              },
 +      },
 +      {
 +              name:   "CTZ",
 +              argLen: 1,
 +              asm:    riscv.ACTZ,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                      },
 +              },
 +      },
 +      {
 +              name:   "CTZW",
 +              argLen: 1,
 +              asm:    riscv.ACTZW,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                      },
 +              },
 +      },
 +      {
 +              name:   "NOT",
 +              argLen: 1,
 +              asm:    riscv.ANOT,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                      },
 +              },
 +      },
 +      {
 +              name:        "OR",
 +              argLen:      2,
 +              commutative: true,
 +              asm:         riscv.AOR,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                              {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                      },
 +              },
 +      },
 +      {
 +              name:   "ORN",
 +              argLen: 2,
 +              asm:    riscv.AORN,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                              {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                      },
 +              },
 +      },
 +      {
 +              name:    "ORI",
 +              auxType: auxInt64,
 +              argLen:  1,
 +              asm:     riscv.AORI,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                      },
 +              },
 +      },
 +      {
 +              name:   "REV8",
 +              argLen: 1,
 +              asm:    riscv.AREV8,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                      },
 +              },
 +      },
 +      {
 +              name:   "ROL",
 +              argLen: 2,
 +              asm:    riscv.AROL,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                              {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                      },
 +              },
 +      },
 +      {
 +              name:   "ROLW",
 +              argLen: 2,
 +              asm:    riscv.AROLW,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                              {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                      },
 +              },
 +      },
 +      {
 +              name:   "ROR",
 +              argLen: 2,
 +              asm:    riscv.AROR,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                              {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                      },
 +              },
 +      },
 +      {
 +              name:    "RORI",
 +              auxType: auxInt64,
 +              argLen:  1,
 +              asm:     riscv.ARORI,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                      },
 +              },
 +      },
 +      {
 +              name:    "RORIW",
 +              auxType: auxInt64,
 +              argLen:  1,
 +              asm:     riscv.ARORIW,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                      },
 +              },
 +      },
 +      {
 +              name:   "RORW",
 +              argLen: 2,
 +              asm:    riscv.ARORW,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                              {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                      },
 +              },
 +      },
 +      {
 +              name:        "XNOR",
 +              argLen:      2,
 +              commutative: true,
 +              asm:         riscv.AXNOR,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                              {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                      },
 +              },
 +      },
 +      {
 +              name:        "XOR",
 +              argLen:      2,
 +              commutative: true,
 +              asm:         riscv.AXOR,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                              {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                      },
 +              },
 +      },
 +      {
 +              name:    "XORI",
 +              auxType: auxInt64,
 +              argLen:  1,
 +              asm:     riscv.AXORI,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                      },
 +              },
 +      },
 +      {
 +              name:        "MIN",
 +              argLen:      2,
 +              commutative: true,
 +              asm:         riscv.AMIN,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                              {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                      },
 +              },
 +      },
 +      {
 +              name:        "MAX",
 +              argLen:      2,
 +              commutative: true,
 +              asm:         riscv.AMAX,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                              {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                      },
 +              },
 +      },
 +      {
 +              name:        "MINU",
 +              argLen:      2,
 +              commutative: true,
 +              asm:         riscv.AMINU,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                              {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                      },
 +              },
 +      },
 +      {
 +              name:        "MAXU",
 +              argLen:      2,
 +              commutative: true,
 +              asm:         riscv.AMAXU,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                              {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                      },
 +              },
 +      },
 +      {
 +              name:   "SEQZ",
 +              argLen: 1,
 +              asm:    riscv.ASEQZ,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                      },
 +              },
 +      },
 +      {
 +              name:   "SNEZ",
 +              argLen: 1,
 +              asm:    riscv.ASNEZ,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                      },
 +              },
 +      },
 +      {
 +              name:   "SLT",
 +              argLen: 2,
 +              asm:    riscv.ASLT,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                              {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                      },
 +              },
 +      },
 +      {
 +              name:    "SLTI",
 +              auxType: auxInt64,
 +              argLen:  1,
 +              asm:     riscv.ASLTI,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                      },
 +              },
 +      },
 +      {
 +              name:   "SLTU",
 +              argLen: 2,
 +              asm:    riscv.ASLTU,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                              {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                      },
 +              },
 +      },
 +      {
 +              name:    "SLTIU",
 +              auxType: auxInt64,
 +              argLen:  1,
 +              asm:     riscv.ASLTIU,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                      },
 +              },
 +      },
 +      {
 +              name:         "LoweredRound32F",
 +              argLen:       1,
 +              resultInArg0: true,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +              },
 +      },
 +      {
 +              name:         "LoweredRound64F",
 +              argLen:       1,
 +              resultInArg0: true,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +              },
 +      },
 +      {
 +              name:    "CALLstatic",
 +              auxType: auxCallOff,
 +              argLen:  -1,
 +              call:    true,
 +              reg: regInfo{
 +                      clobbers: 9223372035781033968, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +              },
 +      },
 +      {
 +              name:     "CALLtail",
 +              auxType:  auxCallOff,
 +              argLen:   -1,
 +              call:     true,
 +              tailCall: true,
 +              reg: regInfo{
 +                      clobbers: 9223372035781033968, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +              },
 +      },
 +      {
 +              name:    "CALLclosure",
 +              auxType: auxCallOff,
 +              argLen:  -1,
 +              call:    true,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 33554432},   // X26
 +                              {0, 1006632946}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                      },
 +                      clobbers: 9223372035781033968, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +              },
 +      },
 +      {
 +              name:    "CALLinter",
 +              auxType: auxCallOff,
 +              argLen:  -1,
 +              call:    true,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                      },
 +                      clobbers: 9223372035781033968, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +              },
 +      },
 +      {
 +              name:           "LoweredZero",
 +              auxType:        auxSymValAndOff,
 +              argLen:         2,
 +              faultOnNilArg0: true,
 +              symEffect:      SymWrite,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                      },
 +              },
 +      },
 +      {
 +              name:           "LoweredZeroLoop",
 +              auxType:        auxSymValAndOff,
 +              argLen:         2,
 +              needIntTemp:    true,
 +              faultOnNilArg0: true,
 +              symEffect:      SymWrite,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                      },
 +                      clobbersArg0: true,
 +              },
 +      },
 +      {
 +              name:           "LoweredMove",
 +              auxType:        auxSymValAndOff,
 +              argLen:         3,
 +              faultOnNilArg0: true,
 +              faultOnNilArg1: true,
 +              symEffect:      SymWrite,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1006632928}, // X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                              {1, 1006632928}, // X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                      },
 +                      clobbers: 16, // X5
 +              },
 +      },
 +      {
 +              name:           "LoweredMoveLoop",
 +              auxType:        auxSymValAndOff,
 +              argLen:         3,
 +              faultOnNilArg0: true,
 +              faultOnNilArg1: true,
 +              symEffect:      SymWrite,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1006632896}, // X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                              {1, 1006632896}, // X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                      },
 +                      clobbers:     48, // X5 X6
 +                      clobbersArg0: true,
 +                      clobbersArg1: true,
 +              },
 +      },
 +      {
 +              name:           "LoweredAtomicLoad8",
 +              argLen:         2,
 +              faultOnNilArg0: true,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                      },
 +              },
 +      },
 +      {
 +              name:           "LoweredAtomicLoad32",
 +              argLen:         2,
 +              faultOnNilArg0: true,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                      },
 +              },
 +      },
 +      {
 +              name:           "LoweredAtomicLoad64",
 +              argLen:         2,
 +              faultOnNilArg0: true,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                      },
 +              },
 +      },
 +      {
 +              name:           "LoweredAtomicStore8",
 +              argLen:         3,
 +              faultOnNilArg0: true,
 +              hasSideEffects: true,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 1006632946},          // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                              {0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB
 +                      },
 +              },
 +      },
 +      {
 +              name:           "LoweredAtomicStore32",
 +              argLen:         3,
 +              faultOnNilArg0: true,
 +              hasSideEffects: true,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 1006632946},          // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                              {0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB
 +                      },
 +              },
 +      },
 +      {
 +              name:           "LoweredAtomicStore64",
 +              argLen:         3,
 +              faultOnNilArg0: true,
 +              hasSideEffects: true,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 1006632946},          // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                              {0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB
 +                      },
 +              },
 +      },
 +      {
 +              name:            "LoweredAtomicExchange32",
 +              argLen:          3,
 +              resultNotInArgs: true,
 +              faultOnNilArg0:  true,
 +              hasSideEffects:  true,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 1073741808},          // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30
 +                              {0, 9223372037928517618}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30 SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                      },
 +              },
 +      },
 +      {
 +              name:            "LoweredAtomicExchange64",
 +              argLen:          3,
 +              resultNotInArgs: true,
 +              faultOnNilArg0:  true,
 +              hasSideEffects:  true,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 1073741808},          // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30
 +                              {0, 9223372037928517618}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30 SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                      },
 +              },
 +      },
 +      {
 +              name:            "LoweredAtomicAdd32",
 +              argLen:          3,
 +              resultNotInArgs: true,
 +              faultOnNilArg0:  true,
 +              hasSideEffects:  true,
 +              unsafePoint:     true,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 1073741808},          // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30
 +                              {0, 9223372037928517618}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30 SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                      },
 +              },
 +      },
 +      {
 +              name:            "LoweredAtomicAdd64",
 +              argLen:          3,
 +              resultNotInArgs: true,
 +              faultOnNilArg0:  true,
 +              hasSideEffects:  true,
 +              unsafePoint:     true,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 1073741808},          // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30
 +                              {0, 9223372037928517618}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30 SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                      },
 +              },
 +      },
 +      {
 +              name:            "LoweredAtomicCas32",
 +              argLen:          4,
 +              resultNotInArgs: true,
 +              faultOnNilArg0:  true,
 +              hasSideEffects:  true,
 +              unsafePoint:     true,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 1073741808},          // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30
 +                              {2, 1073741808},          // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30
 +                              {0, 9223372037928517618}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30 SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                      },
 +              },
 +      },
 +      {
 +              name:            "LoweredAtomicCas64",
 +              argLen:          4,
 +              resultNotInArgs: true,
 +              faultOnNilArg0:  true,
 +              hasSideEffects:  true,
 +              unsafePoint:     true,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 1073741808},          // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30
 +                              {2, 1073741808},          // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30
 +                              {0, 9223372037928517618}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30 SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                      },
 +              },
 +      },
 +      {
 +              name:           "LoweredAtomicAnd32",
 +              argLen:         3,
 +              faultOnNilArg0: true,
 +              hasSideEffects: true,
 +              asm:            riscv.AAMOANDW,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 1073741808},          // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30
 +                              {0, 9223372037928517618}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30 SB
 +                      },
 +              },
 +      },
 +      {
 +              name:           "LoweredAtomicOr32",
 +              argLen:         3,
 +              faultOnNilArg0: true,
 +              hasSideEffects: true,
 +              asm:            riscv.AAMOORW,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 1073741808},          // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30
 +                              {0, 9223372037928517618}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30 SB
 +                      },
 +              },
 +      },
 +      {
 +              name:           "LoweredNilCheck",
 +              argLen:         2,
 +              nilCheck:       true,
 +              faultOnNilArg0: true,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1006632946}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                      },
 +              },
 +      },
 +      {
 +              name:   "LoweredGetClosurePtr",
 +              argLen: 0,
 +              reg: regInfo{
 +                      outputs: []outputInfo{
 +                              {0, 33554432}, // X26
 +                      },
 +              },
 +      },
 +      {
 +              name:              "LoweredGetCallerSP",
 +              argLen:            1,
 +              rematerializeable: true,
 +              reg: regInfo{
 +                      outputs: []outputInfo{
 +                              {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                      },
 +              },
 +      },
 +      {
 +              name:              "LoweredGetCallerPC",
 +              argLen:            0,
 +              rematerializeable: true,
 +              reg: regInfo{
 +                      outputs: []outputInfo{
 +                              {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                      },
 +              },
 +      },
 +      {
 +              name:         "LoweredWB",
 +              auxType:      auxInt64,
 +              argLen:       1,
 +              clobberFlags: true,
 +              reg: regInfo{
 +                      clobbers: 9223372034707292160, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      outputs: []outputInfo{
 +                              {0, 8388608}, // X24
 +                      },
 +              },
 +      },
 +      {
 +              name:           "LoweredPubBarrier",
 +              argLen:         1,
 +              hasSideEffects: true,
 +              asm:            riscv.AFENCE,
 +              reg:            regInfo{},
 +      },
 +      {
 +              name:    "LoweredPanicBoundsRR",
 +              auxType: auxInt64,
 +              argLen:  3,
 +              call:    true,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1048560}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20
 +                              {1, 1048560}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20
 +                      },
 +              },
 +      },
 +      {
 +              name:    "LoweredPanicBoundsRC",
 +              auxType: auxPanicBoundsC,
 +              argLen:  2,
 +              call:    true,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1048560}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20
 +                      },
 +              },
 +      },
 +      {
 +              name:    "LoweredPanicBoundsCR",
 +              auxType: auxPanicBoundsC,
 +              argLen:  2,
 +              call:    true,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1048560}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20
 +                      },
 +              },
 +      },
 +      {
 +              name:    "LoweredPanicBoundsCC",
 +              auxType: auxPanicBoundsCC,
 +              argLen:  1,
 +              call:    true,
 +              reg:     regInfo{},
 +      },
 +      {
 +              name:        "FADDS",
 +              argLen:      2,
 +              commutative: true,
 +              asm:         riscv.AFADDS,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                              {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +              },
 +      },
 +      {
 +              name:   "FSUBS",
 +              argLen: 2,
 +              asm:    riscv.AFSUBS,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                              {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +              },
 +      },
 +      {
 +              name:        "FMULS",
 +              argLen:      2,
 +              commutative: true,
 +              asm:         riscv.AFMULS,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                              {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +              },
 +      },
 +      {
 +              name:   "FDIVS",
 +              argLen: 2,
 +              asm:    riscv.AFDIVS,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                              {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +              },
 +      },
 +      {
 +              name:        "FMADDS",
 +              argLen:      3,
 +              commutative: true,
 +              asm:         riscv.AFMADDS,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                              {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                              {2, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +              },
 +      },
 +      {
 +              name:        "FMSUBS",
 +              argLen:      3,
 +              commutative: true,
 +              asm:         riscv.AFMSUBS,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                              {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                              {2, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +              },
 +      },
 +      {
 +              name:        "FNMADDS",
 +              argLen:      3,
 +              commutative: true,
 +              asm:         riscv.AFNMADDS,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                              {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                              {2, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +              },
 +      },
 +      {
 +              name:        "FNMSUBS",
 +              argLen:      3,
 +              commutative: true,
 +              asm:         riscv.AFNMSUBS,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                              {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                              {2, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +              },
 +      },
 +      {
 +              name:   "FSQRTS",
 +              argLen: 1,
 +              asm:    riscv.AFSQRTS,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +              },
 +      },
 +      {
 +              name:   "FNEGS",
 +              argLen: 1,
 +              asm:    riscv.AFNEGS,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +              },
 +      },
 +      {
 +              name:   "FMVSX",
 +              argLen: 1,
 +              asm:    riscv.AFMVSX,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +              },
 +      },
 +      {
 +              name:   "FMVXS",
 +              argLen: 1,
 +              asm:    riscv.AFMVXS,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                      },
 +              },
 +      },
 +      {
 +              name:   "FCVTSW",
 +              argLen: 1,
 +              asm:    riscv.AFCVTSW,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +              },
 +      },
 +      {
 +              name:   "FCVTSL",
 +              argLen: 1,
 +              asm:    riscv.AFCVTSL,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +              },
 +      },
 +      {
 +              name:   "FCVTWS",
 +              argLen: 1,
 +              asm:    riscv.AFCVTWS,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                      },
 +              },
 +      },
 +      {
 +              name:   "FCVTLS",
 +              argLen: 1,
 +              asm:    riscv.AFCVTLS,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                      },
 +              },
 +      },
 +      {
 +              name:           "FMOVWload",
 +              auxType:        auxSymOff,
 +              argLen:         2,
 +              faultOnNilArg0: true,
 +              symEffect:      SymRead,
 +              asm:            riscv.AMOVF,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +              },
 +      },
 +      {
 +              name:           "FMOVWstore",
 +              auxType:        auxSymOff,
 +              argLen:         3,
 +              faultOnNilArg0: true,
 +              symEffect:      SymWrite,
 +              asm:            riscv.AMOVF,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB
 +                              {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +              },
 +      },
 +      {
 +              name:        "FEQS",
 +              argLen:      2,
 +              commutative: true,
 +              asm:         riscv.AFEQS,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                              {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                      },
 +              },
 +      },
 +      {
 +              name:        "FNES",
 +              argLen:      2,
 +              commutative: true,
 +              asm:         riscv.AFNES,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                              {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                      },
 +              },
 +      },
 +      {
 +              name:   "FLTS",
 +              argLen: 2,
 +              asm:    riscv.AFLTS,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                              {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                      },
 +              },
 +      },
 +      {
 +              name:   "FLES",
 +              argLen: 2,
 +              asm:    riscv.AFLES,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                              {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                      },
 +              },
 +      },
 +      {
 +              name:            "LoweredFMAXS",
 +              argLen:          2,
 +              commutative:     true,
 +              resultNotInArgs: true,
 +              asm:             riscv.AFMAXS,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                              {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +              },
 +      },
 +      {
 +              name:            "LoweredFMINS",
 +              argLen:          2,
 +              commutative:     true,
 +              resultNotInArgs: true,
 +              asm:             riscv.AFMINS,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                              {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +              },
 +      },
 +      {
 +              name:        "FADDD",
 +              argLen:      2,
 +              commutative: true,
 +              asm:         riscv.AFADDD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                              {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +              },
 +      },
 +      {
 +              name:   "FSUBD",
 +              argLen: 2,
 +              asm:    riscv.AFSUBD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                              {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +              },
 +      },
 +      {
 +              name:        "FMULD",
 +              argLen:      2,
 +              commutative: true,
 +              asm:         riscv.AFMULD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                              {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +              },
 +      },
 +      {
 +              name:   "FDIVD",
 +              argLen: 2,
 +              asm:    riscv.AFDIVD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                              {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +              },
 +      },
 +      {
 +              name:        "FMADDD",
 +              argLen:      3,
 +              commutative: true,
 +              asm:         riscv.AFMADDD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                              {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                              {2, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +              },
 +      },
 +      {
 +              name:        "FMSUBD",
 +              argLen:      3,
 +              commutative: true,
 +              asm:         riscv.AFMSUBD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                              {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                              {2, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +              },
 +      },
 +      {
 +              name:        "FNMADDD",
 +              argLen:      3,
 +              commutative: true,
 +              asm:         riscv.AFNMADDD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                              {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                              {2, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +              },
 +      },
 +      {
 +              name:        "FNMSUBD",
 +              argLen:      3,
 +              commutative: true,
 +              asm:         riscv.AFNMSUBD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                              {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                              {2, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +              },
 +      },
 +      {
 +              name:   "FSQRTD",
 +              argLen: 1,
 +              asm:    riscv.AFSQRTD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +              },
 +      },
 +      {
 +              name:   "FNEGD",
 +              argLen: 1,
 +              asm:    riscv.AFNEGD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +              },
 +      },
 +      {
 +              name:   "FABSD",
 +              argLen: 1,
 +              asm:    riscv.AFABSD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +              },
 +      },
 +      {
 +              name:   "FSGNJD",
 +              argLen: 2,
 +              asm:    riscv.AFSGNJD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                              {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +              },
 +      },
 +      {
 +              name:   "FMVDX",
 +              argLen: 1,
 +              asm:    riscv.AFMVDX,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +              },
 +      },
 +      {
 +              name:   "FMVXD",
 +              argLen: 1,
 +              asm:    riscv.AFMVXD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                      },
 +              },
 +      },
 +      {
 +              name:   "FCVTDW",
 +              argLen: 1,
 +              asm:    riscv.AFCVTDW,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +              },
 +      },
 +      {
 +              name:   "FCVTDL",
 +              argLen: 1,
 +              asm:    riscv.AFCVTDL,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +              },
 +      },
 +      {
 +              name:   "FCVTWD",
 +              argLen: 1,
 +              asm:    riscv.AFCVTWD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                      },
 +              },
 +      },
 +      {
 +              name:   "FCVTLD",
 +              argLen: 1,
 +              asm:    riscv.AFCVTLD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                      },
 +              },
 +      },
 +      {
 +              name:   "FCVTDS",
 +              argLen: 1,
 +              asm:    riscv.AFCVTDS,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +              },
 +      },
 +      {
 +              name:   "FCVTSD",
 +              argLen: 1,
 +              asm:    riscv.AFCVTSD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +              },
 +      },
 +      {
 +              name:           "FMOVDload",
 +              auxType:        auxSymOff,
 +              argLen:         2,
 +              faultOnNilArg0: true,
 +              symEffect:      SymRead,
 +              asm:            riscv.AMOVD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +              },
 +      },
 +      {
 +              name:           "FMOVDstore",
 +              auxType:        auxSymOff,
 +              argLen:         3,
 +              faultOnNilArg0: true,
 +              symEffect:      SymWrite,
 +              asm:            riscv.AMOVD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB
 +                              {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +              },
 +      },
 +      {
 +              name:        "FEQD",
 +              argLen:      2,
 +              commutative: true,
 +              asm:         riscv.AFEQD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                              {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                      },
 +              },
 +      },
 +      {
 +              name:        "FNED",
 +              argLen:      2,
 +              commutative: true,
 +              asm:         riscv.AFNED,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                              {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                      },
 +              },
 +      },
 +      {
 +              name:   "FLTD",
 +              argLen: 2,
 +              asm:    riscv.AFLTD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                              {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                      },
 +              },
 +      },
 +      {
 +              name:   "FLED",
 +              argLen: 2,
 +              asm:    riscv.AFLED,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                              {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                      },
 +              },
 +      },
 +      {
 +              name:            "LoweredFMIND",
 +              argLen:          2,
 +              commutative:     true,
 +              resultNotInArgs: true,
 +              asm:             riscv.AFMIND,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                              {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +              },
 +      },
 +      {
 +              name:            "LoweredFMAXD",
 +              argLen:          2,
 +              commutative:     true,
 +              resultNotInArgs: true,
 +              asm:             riscv.AFMAXD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                              {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +              },
 +      },
 +      {
 +              name:   "FCLASSS",
 +              argLen: 1,
 +              asm:    riscv.AFCLASSS,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                      },
 +              },
 +      },
 +      {
 +              name:   "FCLASSD",
 +              argLen: 1,
 +              asm:    riscv.AFCLASSD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
 +                      },
 +              },
 +      },
 +
 +      {
 +              name:         "FADDS",
 +              argLen:       2,
 +              commutative:  true,
 +              resultInArg0: true,
 +              asm:          s390x.AFADDS,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 +                              {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 +                      },
 +              },
 +      },
 +      {
 +              name:         "FADD",
 +              argLen:       2,
 +              commutative:  true,
 +              resultInArg0: true,
 +              asm:          s390x.AFADD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 +                              {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 +                      },
 +              },
 +      },
 +      {
 +              name:         "FSUBS",
 +              argLen:       2,
 +              resultInArg0: true,
 +              asm:          s390x.AFSUBS,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 +                              {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 +                      },
 +              },
 +      },
 +      {
 +              name:         "FSUB",
 +              argLen:       2,
 +              resultInArg0: true,
 +              asm:          s390x.AFSUB,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 +                              {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 +                      },
 +              },
 +      },
 +      {
 +              name:         "FMULS",
 +              argLen:       2,
 +              commutative:  true,
 +              resultInArg0: true,
 +              asm:          s390x.AFMULS,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 +                              {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 +                      },
 +              },
 +      },
 +      {
 +              name:         "FMUL",
 +              argLen:       2,
 +              commutative:  true,
 +              resultInArg0: true,
 +              asm:          s390x.AFMUL,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 +                              {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 +                      },
 +              },
 +      },
 +      {
 +              name:         "FDIVS",
 +              argLen:       2,
 +              resultInArg0: true,
 +              asm:          s390x.AFDIVS,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 +                              {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 +                      },
 +              },
 +      },
 +      {
 +              name:         "FDIV",
 +              argLen:       2,
 +              resultInArg0: true,
 +              asm:          s390x.AFDIV,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 +                              {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 +                      },
 +              },
 +      },
 +      {
 +              name:         "FNEGS",
 +              argLen:       1,
 +              clobberFlags: true,
 +              asm:          s390x.AFNEGS,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 +                      },
 +              },
 +      },
 +      {
 +              name:         "FNEG",
 +              argLen:       1,
 +              clobberFlags: true,
 +              asm:          s390x.AFNEG,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 +                      },
 +              },
 +      },
 +      {
 +              name:         "FMADDS",
 +              argLen:       3,
 +              resultInArg0: true,
 +              asm:          s390x.AFMADDS,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 +                              {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 +                              {2, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 +                      },
 +              },
 +      },
 +      {
 +              name:         "FMADD",
 +              argLen:       3,
 +              resultInArg0: true,
 +              asm:          s390x.AFMADD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 +                              {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 +                              {2, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 +                      },
 +              },
 +      },
 +      {
 +              name:         "FMSUBS",
 +              argLen:       3,
 +              resultInArg0: true,
 +              asm:          s390x.AFMSUBS,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 +                              {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 +                              {2, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 +                      },
 +              },
 +      },
 +      {
 +              name:         "FMSUB",
 +              argLen:       3,
 +              resultInArg0: true,
 +              asm:          s390x.AFMSUB,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 +                              {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 +                              {2, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 +                      },
 +              },
 +      },
 +      {
 +              name:   "LPDFR",
 +              argLen: 1,
 +              asm:    s390x.ALPDFR,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 +                      },
 +              },
 +      },
 +      {
 +              name:   "LNDFR",
 +              argLen: 1,
 +              asm:    s390x.ALNDFR,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 +                      },
 +              },
 +      },
 +      {
 +              name:   "CPSDR",
 +              argLen: 2,
 +              asm:    s390x.ACPSDR,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 +                              {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 +                      },
 +              },
 +      },
 +      {
 +              name:   "WFMAXDB",
 +              argLen: 2,
 +              asm:    s390x.AWFMAXDB,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 +                              {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 +                      },
 +              },
 +      },
 +      {
 +              name:   "WFMAXSB",
 +              argLen: 2,
 +              asm:    s390x.AWFMAXSB,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 +                              {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 +                      },
 +              },
 +      },
 +      {
 +              name:   "WFMINDB",
 +              argLen: 2,
 +              asm:    s390x.AWFMINDB,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 +                              {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 +                      },
 +              },
 +      },
 +      {
 +              name:   "WFMINSB",
 +              argLen: 2,
 +              asm:    s390x.AWFMINSB,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 +                              {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 +                      },
 +              },
 +      },
 +      {
 +              name:    "FIDBR",
 +              auxType: auxInt8,
 +              argLen:  1,
 +              asm:     s390x.AFIDBR,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 +                      },
 +              },
 +      },
 +      {
 +              name:           "FMOVSload",
 +              auxType:        auxSymOff,
 +              argLen:         2,
 +              faultOnNilArg0: true,
 +              symEffect:      SymRead,
 +              asm:            s390x.AFMOVS,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 +                      },
 +              },
 +      },
 +      {
 +              name:           "FMOVDload",
 +              auxType:        auxSymOff,
 +              argLen:         2,
 +              faultOnNilArg0: true,
 +              symEffect:      SymRead,
 +              asm:            s390x.AFMOVD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 +                      },
 +              },
 +      },
 +      {
 +              name:              "FMOVSconst",
 +              auxType:           auxFloat32,
 +              argLen:            0,
 +              rematerializeable: true,
 +              asm:               s390x.AFMOVS,
 +              reg: regInfo{
 +                      outputs: []outputInfo{
 +                              {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 +                      },
 +              },
 +      },
 +      {
 +              name:              "FMOVDconst",
 +              auxType:           auxFloat64,
 +              argLen:            0,
 +              rematerializeable: true,
 +              asm:               s390x.AFMOVD,
 +              reg: regInfo{
 +                      outputs: []outputInfo{
 +                              {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 +                      },
 +              },
 +      },
 +      {
 +              name:      "FMOVSloadidx",
 +              auxType:   auxSymOff,
 +              argLen:    3,
 +              symEffect: SymRead,
 +              asm:       s390x.AFMOVS,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
 +                              {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 +                      },
 +              },
 +      },
 +      {
 +              name:      "FMOVDloadidx",
 +              auxType:   auxSymOff,
 +              argLen:    3,
 +              symEffect: SymRead,
 +              asm:       s390x.AFMOVD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
 +                              {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 +                      },
 +              },
 +      },
 +      {
 +              name:           "FMOVSstore",
 +              auxType:        auxSymOff,
 +              argLen:         3,
 +              faultOnNilArg0: true,
 +              symEffect:      SymWrite,
 +              asm:            s390x.AFMOVS,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB
 +                              {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 +                      },
 +              },
 +      },
 +      {
 +              name:           "FMOVDstore",
 +              auxType:        auxSymOff,
 +              argLen:         3,
 +              faultOnNilArg0: true,
 +              symEffect:      SymWrite,
 +              asm:            s390x.AFMOVD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB
 +                              {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 +                      },
 +              },
 +      },
 +      {
 +              name:      "FMOVSstoreidx",
 +              auxType:   auxSymOff,
 +              argLen:    4,
 +              symEffect: SymWrite,
 +              asm:       s390x.AFMOVS,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 56318},      // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
 +                              {1, 56318},      // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
 +                              {2, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 +                      },
 +              },
 +      },
 +      {
 +              name:      "FMOVDstoreidx",
 +              auxType:   auxSymOff,
 +              argLen:    4,
 +              symEffect: SymWrite,
 +              asm:       s390x.AFMOVD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 56318},      // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
 +                              {1, 56318},      // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
 +                              {2, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 +                      },
 +              },
 +      },
 +      {
 +              name:         "ADD",
 +              argLen:       2,
 +              commutative:  true,
 +              clobberFlags: true,
 +              asm:          s390x.AADD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                              {0, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:         "ADDW",
 +              argLen:       2,
 +              commutative:  true,
 +              clobberFlags: true,
 +              asm:          s390x.AADDW,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                              {0, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:         "ADDconst",
 +              auxType:      auxInt32,
 +              argLen:       1,
 +              clobberFlags: true,
 +              asm:          s390x.AADD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:         "ADDWconst",
 +              auxType:      auxInt32,
 +              argLen:       1,
 +              clobberFlags: true,
 +              asm:          s390x.AADDW,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:           "ADDload",
 +              auxType:        auxSymOff,
 +              argLen:         3,
 +              resultInArg0:   true,
 +              clobberFlags:   true,
 +              faultOnNilArg1: true,
 +              symEffect:      SymRead,
 +              asm:            s390x.AADD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                              {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:           "ADDWload",
 +              auxType:        auxSymOff,
 +              argLen:         3,
 +              resultInArg0:   true,
 +              clobberFlags:   true,
 +              faultOnNilArg1: true,
 +              symEffect:      SymRead,
 +              asm:            s390x.AADDW,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                              {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:         "SUB",
 +              argLen:       2,
 +              clobberFlags: true,
 +              asm:          s390x.ASUB,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                              {1, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:         "SUBW",
 +              argLen:       2,
 +              clobberFlags: true,
 +              asm:          s390x.ASUBW,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                              {1, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:         "SUBconst",
 +              auxType:      auxInt32,
 +              argLen:       1,
 +              resultInArg0: true,
 +              clobberFlags: true,
 +              asm:          s390x.ASUB,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:         "SUBWconst",
 +              auxType:      auxInt32,
 +              argLen:       1,
 +              resultInArg0: true,
 +              clobberFlags: true,
 +              asm:          s390x.ASUBW,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:           "SUBload",
 +              auxType:        auxSymOff,
 +              argLen:         3,
 +              resultInArg0:   true,
 +              clobberFlags:   true,
 +              faultOnNilArg1: true,
 +              symEffect:      SymRead,
 +              asm:            s390x.ASUB,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                              {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:           "SUBWload",
 +              auxType:        auxSymOff,
 +              argLen:         3,
 +              resultInArg0:   true,
 +              clobberFlags:   true,
 +              faultOnNilArg1: true,
 +              symEffect:      SymRead,
 +              asm:            s390x.ASUBW,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                              {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:         "MULLD",
 +              argLen:       2,
 +              commutative:  true,
 +              resultInArg0: true,
 +              clobberFlags: true,
 +              asm:          s390x.AMULLD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                              {1, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:         "MULLW",
 +              argLen:       2,
 +              commutative:  true,
 +              resultInArg0: true,
 +              clobberFlags: true,
 +              asm:          s390x.AMULLW,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                              {1, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:         "MULLDconst",
 +              auxType:      auxInt32,
 +              argLen:       1,
 +              resultInArg0: true,
 +              clobberFlags: true,
 +              asm:          s390x.AMULLD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:         "MULLWconst",
 +              auxType:      auxInt32,
 +              argLen:       1,
 +              resultInArg0: true,
 +              clobberFlags: true,
 +              asm:          s390x.AMULLW,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:           "MULLDload",
 +              auxType:        auxSymOff,
 +              argLen:         3,
 +              resultInArg0:   true,
 +              clobberFlags:   true,
 +              faultOnNilArg1: true,
 +              symEffect:      SymRead,
 +              asm:            s390x.AMULLD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                              {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:           "MULLWload",
 +              auxType:        auxSymOff,
 +              argLen:         3,
 +              resultInArg0:   true,
 +              clobberFlags:   true,
 +              faultOnNilArg1: true,
 +              symEffect:      SymRead,
 +              asm:            s390x.AMULLW,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                              {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:         "MULHD",
 +              argLen:       2,
 +              commutative:  true,
 +              resultInArg0: true,
 +              clobberFlags: true,
 +              asm:          s390x.AMULHD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                              {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                      },
 +                      clobbers: 2048, // R11
 +                      outputs: []outputInfo{
 +                              {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:         "MULHDU",
 +              argLen:       2,
 +              commutative:  true,
 +              resultInArg0: true,
 +              clobberFlags: true,
 +              asm:          s390x.AMULHDU,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                              {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                      },
 +                      clobbers: 2048, // R11
 +                      outputs: []outputInfo{
 +                              {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:         "DIVD",
 +              argLen:       2,
 +              resultInArg0: true,
 +              clobberFlags: true,
 +              asm:          s390x.ADIVD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                              {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                      },
 +                      clobbers: 2048, // R11
 +                      outputs: []outputInfo{
 +                              {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:         "DIVW",
 +              argLen:       2,
 +              resultInArg0: true,
 +              clobberFlags: true,
 +              asm:          s390x.ADIVW,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                              {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                      },
 +                      clobbers: 2048, // R11
 +                      outputs: []outputInfo{
 +                              {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:         "DIVDU",
 +              argLen:       2,
 +              resultInArg0: true,
 +              clobberFlags: true,
 +              asm:          s390x.ADIVDU,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                              {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                      },
 +                      clobbers: 2048, // R11
 +                      outputs: []outputInfo{
 +                              {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:         "DIVWU",
 +              argLen:       2,
 +              resultInArg0: true,
 +              clobberFlags: true,
 +              asm:          s390x.ADIVWU,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                              {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                      },
 +                      clobbers: 2048, // R11
 +                      outputs: []outputInfo{
 +                              {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:         "MODD",
 +              argLen:       2,
 +              resultInArg0: true,
 +              clobberFlags: true,
 +              asm:          s390x.AMODD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                              {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                      },
 +                      clobbers: 2048, // R11
 +                      outputs: []outputInfo{
 +                              {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:         "MODW",
 +              argLen:       2,
 +              resultInArg0: true,
 +              clobberFlags: true,
 +              asm:          s390x.AMODW,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                              {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                      },
 +                      clobbers: 2048, // R11
 +                      outputs: []outputInfo{
 +                              {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:         "MODDU",
 +              argLen:       2,
 +              resultInArg0: true,
 +              clobberFlags: true,
 +              asm:          s390x.AMODDU,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                              {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                      },
 +                      clobbers: 2048, // R11
 +                      outputs: []outputInfo{
 +                              {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:         "MODWU",
 +              argLen:       2,
 +              resultInArg0: true,
 +              clobberFlags: true,
 +              asm:          s390x.AMODWU,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                              {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                      },
 +                      clobbers: 2048, // R11
 +                      outputs: []outputInfo{
 +                              {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:         "AND",
 +              argLen:       2,
 +              commutative:  true,
 +              clobberFlags: true,
 +              asm:          s390x.AAND,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                              {1, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:         "ANDW",
 +              argLen:       2,
 +              commutative:  true,
 +              clobberFlags: true,
 +              asm:          s390x.AANDW,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                              {1, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:         "ANDconst",
 +              auxType:      auxInt64,
 +              argLen:       1,
 +              resultInArg0: true,
 +              clobberFlags: true,
 +              asm:          s390x.AAND,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:         "ANDWconst",
 +              auxType:      auxInt32,
 +              argLen:       1,
 +              resultInArg0: true,
 +              clobberFlags: true,
 +              asm:          s390x.AANDW,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:           "ANDload",
 +              auxType:        auxSymOff,
 +              argLen:         3,
 +              resultInArg0:   true,
 +              clobberFlags:   true,
 +              faultOnNilArg1: true,
 +              symEffect:      SymRead,
 +              asm:            s390x.AAND,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                              {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:           "ANDWload",
 +              auxType:        auxSymOff,
 +              argLen:         3,
 +              resultInArg0:   true,
 +              clobberFlags:   true,
 +              faultOnNilArg1: true,
 +              symEffect:      SymRead,
 +              asm:            s390x.AANDW,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                              {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:         "OR",
 +              argLen:       2,
 +              commutative:  true,
 +              clobberFlags: true,
 +              asm:          s390x.AOR,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                              {1, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:         "ORW",
 +              argLen:       2,
 +              commutative:  true,
 +              clobberFlags: true,
 +              asm:          s390x.AORW,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                              {1, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:         "ORconst",
 +              auxType:      auxInt64,
 +              argLen:       1,
 +              resultInArg0: true,
 +              clobberFlags: true,
 +              asm:          s390x.AOR,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:         "ORWconst",
 +              auxType:      auxInt32,
 +              argLen:       1,
 +              resultInArg0: true,
 +              clobberFlags: true,
 +              asm:          s390x.AORW,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:           "ORload",
 +              auxType:        auxSymOff,
 +              argLen:         3,
 +              resultInArg0:   true,
 +              clobberFlags:   true,
 +              faultOnNilArg1: true,
 +              symEffect:      SymRead,
 +              asm:            s390x.AOR,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                              {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:           "ORWload",
 +              auxType:        auxSymOff,
 +              argLen:         3,
 +              resultInArg0:   true,
 +              clobberFlags:   true,
 +              faultOnNilArg1: true,
 +              symEffect:      SymRead,
 +              asm:            s390x.AORW,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                              {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:         "XOR",
 +              argLen:       2,
 +              commutative:  true,
 +              clobberFlags: true,
 +              asm:          s390x.AXOR,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                              {1, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:         "XORW",
 +              argLen:       2,
 +              commutative:  true,
 +              clobberFlags: true,
 +              asm:          s390x.AXORW,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                              {1, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:         "XORconst",
 +              auxType:      auxInt64,
 +              argLen:       1,
 +              resultInArg0: true,
 +              clobberFlags: true,
 +              asm:          s390x.AXOR,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:         "XORWconst",
 +              auxType:      auxInt32,
 +              argLen:       1,
 +              resultInArg0: true,
 +              clobberFlags: true,
 +              asm:          s390x.AXORW,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:           "XORload",
 +              auxType:        auxSymOff,
 +              argLen:         3,
 +              resultInArg0:   true,
 +              clobberFlags:   true,
 +              faultOnNilArg1: true,
 +              symEffect:      SymRead,
 +              asm:            s390x.AXOR,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                              {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:           "XORWload",
 +              auxType:        auxSymOff,
 +              argLen:         3,
 +              resultInArg0:   true,
 +              clobberFlags:   true,
 +              faultOnNilArg1: true,
 +              symEffect:      SymRead,
 +              asm:            s390x.AXORW,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                              {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:        "ADDC",
 +              argLen:      2,
 +              commutative: true,
 +              asm:         s390x.AADDC,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                              {1, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:    "ADDCconst",
 +              auxType: auxInt16,
 +              argLen:  1,
 +              asm:     s390x.AADDC,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:         "ADDE",
 +              argLen:       3,
 +              commutative:  true,
 +              resultInArg0: true,
 +              asm:          s390x.AADDE,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                              {1, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:   "SUBC",
 +              argLen: 2,
 +              asm:    s390x.ASUBC,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                              {1, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:         "SUBE",
 +              argLen:       3,
 +              resultInArg0: true,
 +              asm:          s390x.ASUBE,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                              {1, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:   "CMP",
 +              argLen: 2,
 +              asm:    s390x.ACMP,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
 +                              {1, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
 +                      },
 +              },
 +      },
 +      {
 +              name:   "CMPW",
 +              argLen: 2,
 +              asm:    s390x.ACMPW,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
 +                              {1, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
 +                      },
 +              },
 +      },
 +      {
 +              name:   "CMPU",
 +              argLen: 2,
 +              asm:    s390x.ACMPU,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
 +                              {1, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
 +                      },
 +              },
 +      },
 +      {
 +              name:   "CMPWU",
 +              argLen: 2,
 +              asm:    s390x.ACMPWU,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
 +                              {1, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
 +                      },
 +              },
 +      },
 +      {
 +              name:    "CMPconst",
 +              auxType: auxInt32,
 +              argLen:  1,
 +              asm:     s390x.ACMP,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
 +                      },
 +              },
 +      },
 +      {
 +              name:    "CMPWconst",
 +              auxType: auxInt32,
 +              argLen:  1,
 +              asm:     s390x.ACMPW,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
 +                      },
 +              },
 +      },
 +      {
 +              name:    "CMPUconst",
 +              auxType: auxInt32,
 +              argLen:  1,
 +              asm:     s390x.ACMPU,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
 +                      },
 +              },
 +      },
 +      {
 +              name:    "CMPWUconst",
 +              auxType: auxInt32,
 +              argLen:  1,
 +              asm:     s390x.ACMPWU,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
 +                      },
 +              },
 +      },
 +      {
 +              name:   "FCMPS",
 +              argLen: 2,
 +              asm:    s390x.ACEBR,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 +                              {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 +                      },
 +              },
 +      },
 +      {
 +              name:   "FCMP",
 +              argLen: 2,
 +              asm:    s390x.AFCMPU,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 +                              {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 +                      },
 +              },
 +      },
 +      {
 +              name:   "LTDBR",
 +              argLen: 1,
 +              asm:    s390x.ALTDBR,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 +                      },
 +              },
 +      },
 +      {
 +              name:   "LTEBR",
 +              argLen: 1,
 +              asm:    s390x.ALTEBR,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 +                      },
 +              },
 +      },
 +      {
 +              name:   "SLD",
 +              argLen: 2,
 +              asm:    s390x.ASLD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 23550}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                              {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:   "SLW",
 +              argLen: 2,
 +              asm:    s390x.ASLW,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 23550}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                              {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:    "SLDconst",
 +              auxType: auxUInt8,
 +              argLen:  1,
 +              asm:     s390x.ASLD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:    "SLWconst",
 +              auxType: auxUInt8,
 +              argLen:  1,
 +              asm:     s390x.ASLW,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:   "SRD",
 +              argLen: 2,
 +              asm:    s390x.ASRD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 23550}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                              {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:   "SRW",
 +              argLen: 2,
 +              asm:    s390x.ASRW,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 23550}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                              {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:    "SRDconst",
 +              auxType: auxUInt8,
 +              argLen:  1,
 +              asm:     s390x.ASRD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:    "SRWconst",
 +              auxType: auxUInt8,
 +              argLen:  1,
 +              asm:     s390x.ASRW,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:         "SRAD",
 +              argLen:       2,
 +              clobberFlags: true,
 +              asm:          s390x.ASRAD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 23550}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                              {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:         "SRAW",
 +              argLen:       2,
 +              clobberFlags: true,
 +              asm:          s390x.ASRAW,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 23550}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                              {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:         "SRADconst",
 +              auxType:      auxUInt8,
 +              argLen:       1,
 +              clobberFlags: true,
 +              asm:          s390x.ASRAD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:         "SRAWconst",
 +              auxType:      auxUInt8,
 +              argLen:       1,
 +              clobberFlags: true,
 +              asm:          s390x.ASRAW,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:   "RLLG",
 +              argLen: 2,
 +              asm:    s390x.ARLLG,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 23550}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                              {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:   "RLL",
 +              argLen: 2,
 +              asm:    s390x.ARLL,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 23550}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                              {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:    "RLLconst",
 +              auxType: auxUInt8,
 +              argLen:  1,
 +              asm:     s390x.ARLL,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:         "RXSBG",
 +              auxType:      auxS390XRotateParams,
 +              argLen:       2,
 +              resultInArg0: true,
 +              clobberFlags: true,
 +              asm:          s390x.ARXSBG,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                              {1, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:         "RISBGZ",
 +              auxType:      auxS390XRotateParams,
 +              argLen:       1,
 +              clobberFlags: true,
 +              asm:          s390x.ARISBGZ,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:         "NEG",
 +              argLen:       1,
 +              clobberFlags: true,
 +              asm:          s390x.ANEG,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:         "NEGW",
 +              argLen:       1,
 +              clobberFlags: true,
 +              asm:          s390x.ANEGW,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:         "NOT",
 +              argLen:       1,
 +              resultInArg0: true,
 +              clobberFlags: true,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:         "NOTW",
 +              argLen:       1,
 +              resultInArg0: true,
 +              clobberFlags: true,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:   "FSQRT",
 +              argLen: 1,
 +              asm:    s390x.AFSQRT,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 +                      },
 +              },
 +      },
 +      {
 +              name:   "FSQRTS",
 +              argLen: 1,
 +              asm:    s390x.AFSQRTS,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 +                      },
 +              },
 +      },
 +      {
 +              name:         "LOCGR",
 +              auxType:      auxS390XCCMask,
 +              argLen:       3,
 +              resultInArg0: true,
 +              asm:          s390x.ALOCGR,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                              {1, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:   "MOVBreg",
 +              argLen: 1,
 +              asm:    s390x.AMOVB,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:   "MOVBZreg",
 +              argLen: 1,
 +              asm:    s390x.AMOVBZ,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:   "MOVHreg",
 +              argLen: 1,
 +              asm:    s390x.AMOVH,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:   "MOVHZreg",
 +              argLen: 1,
 +              asm:    s390x.AMOVHZ,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:   "MOVWreg",
 +              argLen: 1,
 +              asm:    s390x.AMOVW,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:   "MOVWZreg",
 +              argLen: 1,
 +              asm:    s390x.AMOVWZ,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:              "MOVDconst",
 +              auxType:           auxInt64,
 +              argLen:            0,
 +              rematerializeable: true,
 +              asm:               s390x.AMOVD,
 +              reg: regInfo{
 +                      outputs: []outputInfo{
 +                              {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:   "LDGR",
 +              argLen: 1,
 +              asm:    s390x.ALDGR,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 +                      },
 +              },
 +      },
 +      {
 +              name:   "LGDR",
 +              argLen: 1,
 +              asm:    s390x.ALGDR,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:         "CFDBRA",
 +              argLen:       1,
 +              clobberFlags: true,
 +              asm:          s390x.ACFDBRA,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:         "CGDBRA",
 +              argLen:       1,
 +              clobberFlags: true,
 +              asm:          s390x.ACGDBRA,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:         "CFEBRA",
 +              argLen:       1,
 +              clobberFlags: true,
 +              asm:          s390x.ACFEBRA,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:         "CGEBRA",
 +              argLen:       1,
 +              clobberFlags: true,
 +              asm:          s390x.ACGEBRA,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:         "CEFBRA",
 +              argLen:       1,
 +              clobberFlags: true,
 +              asm:          s390x.ACEFBRA,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 +                      },
 +              },
 +      },
 +      {
 +              name:         "CDFBRA",
 +              argLen:       1,
 +              clobberFlags: true,
 +              asm:          s390x.ACDFBRA,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 +                      },
 +              },
 +      },
 +      {
 +              name:         "CEGBRA",
 +              argLen:       1,
 +              clobberFlags: true,
 +              asm:          s390x.ACEGBRA,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 +                      },
 +              },
 +      },
 +      {
 +              name:         "CDGBRA",
 +              argLen:       1,
 +              clobberFlags: true,
 +              asm:          s390x.ACDGBRA,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 +                      },
 +              },
 +      },
 +      {
 +              name:         "CLFEBR",
 +              argLen:       1,
 +              clobberFlags: true,
 +              asm:          s390x.ACLFEBR,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:         "CLFDBR",
 +              argLen:       1,
 +              clobberFlags: true,
 +              asm:          s390x.ACLFDBR,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:         "CLGEBR",
 +              argLen:       1,
 +              clobberFlags: true,
 +              asm:          s390x.ACLGEBR,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:         "CLGDBR",
 +              argLen:       1,
 +              clobberFlags: true,
 +              asm:          s390x.ACLGDBR,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:         "CELFBR",
 +              argLen:       1,
 +              clobberFlags: true,
 +              asm:          s390x.ACELFBR,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 +                      },
 +              },
 +      },
 +      {
 +              name:         "CDLFBR",
 +              argLen:       1,
 +              clobberFlags: true,
 +              asm:          s390x.ACDLFBR,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 +                      },
 +              },
 +      },
 +      {
 +              name:         "CELGBR",
 +              argLen:       1,
 +              clobberFlags: true,
 +              asm:          s390x.ACELGBR,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 +                      },
 +              },
 +      },
 +      {
 +              name:         "CDLGBR",
 +              argLen:       1,
 +              clobberFlags: true,
 +              asm:          s390x.ACDLGBR,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 +                      },
 +              },
 +      },
 +      {
 +              name:   "LEDBR",
 +              argLen: 1,
 +              asm:    s390x.ALEDBR,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 +                      },
 +              },
 +      },
 +      {
 +              name:   "LDEBR",
 +              argLen: 1,
 +              asm:    s390x.ALDEBR,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 +                      },
 +              },
 +      },
 +      {
 +              name:              "MOVDaddr",
 +              auxType:           auxSymOff,
 +              argLen:            1,
 +              rematerializeable: true,
 +              symEffect:         SymAddr,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 4295000064}, // SP SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:      "MOVDaddridx",
 +              auxType:   auxSymOff,
 +              argLen:    2,
 +              symEffect: SymAddr,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 4295000064}, // SP SB
 +                              {1, 56318},      // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:           "MOVBZload",
 +              auxType:        auxSymOff,
 +              argLen:         2,
 +              faultOnNilArg0: true,
 +              symEffect:      SymRead,
 +              asm:            s390x.AMOVBZ,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:           "MOVBload",
 +              auxType:        auxSymOff,
 +              argLen:         2,
 +              faultOnNilArg0: true,
 +              symEffect:      SymRead,
 +              asm:            s390x.AMOVB,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:           "MOVHZload",
 +              auxType:        auxSymOff,
 +              argLen:         2,
 +              faultOnNilArg0: true,
 +              symEffect:      SymRead,
 +              asm:            s390x.AMOVHZ,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:           "MOVHload",
 +              auxType:        auxSymOff,
 +              argLen:         2,
 +              faultOnNilArg0: true,
 +              symEffect:      SymRead,
 +              asm:            s390x.AMOVH,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:           "MOVWZload",
 +              auxType:        auxSymOff,
 +              argLen:         2,
 +              faultOnNilArg0: true,
 +              symEffect:      SymRead,
 +              asm:            s390x.AMOVWZ,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:           "MOVWload",
 +              auxType:        auxSymOff,
 +              argLen:         2,
 +              faultOnNilArg0: true,
 +              symEffect:      SymRead,
 +              asm:            s390x.AMOVW,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:           "MOVDload",
 +              auxType:        auxSymOff,
 +              argLen:         2,
 +              faultOnNilArg0: true,
 +              symEffect:      SymRead,
 +              asm:            s390x.AMOVD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:   "MOVWBR",
 +              argLen: 1,
 +              asm:    s390x.AMOVWBR,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:   "MOVDBR",
 +              argLen: 1,
 +              asm:    s390x.AMOVDBR,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:           "MOVHBRload",
 +              auxType:        auxSymOff,
 +              argLen:         2,
 +              faultOnNilArg0: true,
 +              symEffect:      SymRead,
 +              asm:            s390x.AMOVHBR,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:           "MOVWBRload",
 +              auxType:        auxSymOff,
 +              argLen:         2,
 +              faultOnNilArg0: true,
 +              symEffect:      SymRead,
 +              asm:            s390x.AMOVWBR,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:           "MOVDBRload",
 +              auxType:        auxSymOff,
 +              argLen:         2,
 +              faultOnNilArg0: true,
 +              symEffect:      SymRead,
 +              asm:            s390x.AMOVDBR,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:           "MOVBstore",
 +              auxType:        auxSymOff,
 +              argLen:         3,
 +              faultOnNilArg0: true,
 +              symEffect:      SymWrite,
 +              asm:            s390x.AMOVB,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB
 +                              {1, 56319},      // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
 +                      },
 +              },
 +      },
 +      {
 +              name:           "MOVHstore",
 +              auxType:        auxSymOff,
 +              argLen:         3,
 +              faultOnNilArg0: true,
 +              symEffect:      SymWrite,
 +              asm:            s390x.AMOVH,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB
 +                              {1, 56319},      // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
 +                      },
 +              },
 +      },
 +      {
 +              name:           "MOVWstore",
 +              auxType:        auxSymOff,
 +              argLen:         3,
 +              faultOnNilArg0: true,
 +              symEffect:      SymWrite,
 +              asm:            s390x.AMOVW,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB
 +                              {1, 56319},      // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
 +                      },
 +              },
 +      },
 +      {
 +              name:           "MOVDstore",
 +              auxType:        auxSymOff,
 +              argLen:         3,
 +              faultOnNilArg0: true,
 +              symEffect:      SymWrite,
 +              asm:            s390x.AMOVD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB
 +                              {1, 56319},      // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
 +                      },
 +              },
 +      },
 +      {
 +              name:           "MOVHBRstore",
 +              auxType:        auxSymOff,
 +              argLen:         3,
 +              faultOnNilArg0: true,
 +              symEffect:      SymWrite,
 +              asm:            s390x.AMOVHBR,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
 +                              {1, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
 +                      },
 +              },
 +      },
 +      {
 +              name:           "MOVWBRstore",
 +              auxType:        auxSymOff,
 +              argLen:         3,
 +              faultOnNilArg0: true,
 +              symEffect:      SymWrite,
 +              asm:            s390x.AMOVWBR,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
 +                              {1, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
 +                      },
 +              },
 +      },
 +      {
 +              name:           "MOVDBRstore",
 +              auxType:        auxSymOff,
 +              argLen:         3,
 +              faultOnNilArg0: true,
 +              symEffect:      SymWrite,
 +              asm:            s390x.AMOVDBR,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
 +                              {1, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
 +                      },
 +              },
 +      },
 +      {
 +              name:           "MVC",
 +              auxType:        auxSymValAndOff,
 +              argLen:         3,
 +              clobberFlags:   true,
 +              faultOnNilArg0: true,
 +              faultOnNilArg1: true,
 +              symEffect:      SymNone,
 +              asm:            s390x.AMVC,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
 +                              {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
 +                      },
 +              },
 +      },
 +      {
 +              name:        "MOVBZloadidx",
 +              auxType:     auxSymOff,
 +              argLen:      3,
 +              commutative: true,
 +              symEffect:   SymRead,
 +              asm:         s390x.AMOVBZ,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 56318},      // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
 +                              {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:        "MOVBloadidx",
 +              auxType:     auxSymOff,
 +              argLen:      3,
 +              commutative: true,
 +              symEffect:   SymRead,
 +              asm:         s390x.AMOVB,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 56318},      // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
 +                              {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:        "MOVHZloadidx",
 +              auxType:     auxSymOff,
 +              argLen:      3,
 +              commutative: true,
 +              symEffect:   SymRead,
 +              asm:         s390x.AMOVHZ,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 56318},      // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
 +                              {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:        "MOVHloadidx",
 +              auxType:     auxSymOff,
 +              argLen:      3,
 +              commutative: true,
 +              symEffect:   SymRead,
 +              asm:         s390x.AMOVH,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 56318},      // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
 +                              {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:        "MOVWZloadidx",
 +              auxType:     auxSymOff,
 +              argLen:      3,
 +              commutative: true,
 +              symEffect:   SymRead,
 +              asm:         s390x.AMOVWZ,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 56318},      // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
 +                              {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:        "MOVWloadidx",
 +              auxType:     auxSymOff,
 +              argLen:      3,
 +              commutative: true,
 +              symEffect:   SymRead,
 +              asm:         s390x.AMOVW,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 56318},      // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
 +                              {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:        "MOVDloadidx",
 +              auxType:     auxSymOff,
 +              argLen:      3,
 +              commutative: true,
 +              symEffect:   SymRead,
 +              asm:         s390x.AMOVD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 56318},      // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
 +                              {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:        "MOVHBRloadidx",
 +              auxType:     auxSymOff,
 +              argLen:      3,
 +              commutative: true,
 +              symEffect:   SymRead,
 +              asm:         s390x.AMOVHBR,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 56318},      // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
 +                              {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:        "MOVWBRloadidx",
 +              auxType:     auxSymOff,
 +              argLen:      3,
 +              commutative: true,
 +              symEffect:   SymRead,
 +              asm:         s390x.AMOVWBR,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 56318},      // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
 +                              {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:        "MOVDBRloadidx",
 +              auxType:     auxSymOff,
 +              argLen:      3,
 +              commutative: true,
 +              symEffect:   SymRead,
 +              asm:         s390x.AMOVDBR,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 56318},      // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
 +                              {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:        "MOVBstoreidx",
 +              auxType:     auxSymOff,
 +              argLen:      4,
 +              commutative: true,
 +              symEffect:   SymWrite,
 +              asm:         s390x.AMOVB,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
 +                              {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
 +                              {2, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
 +                      },
 +              },
 +      },
 +      {
 +              name:        "MOVHstoreidx",
 +              auxType:     auxSymOff,
 +              argLen:      4,
 +              commutative: true,
 +              symEffect:   SymWrite,
 +              asm:         s390x.AMOVH,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
 +                              {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
 +                              {2, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
 +                      },
 +              },
 +      },
 +      {
 +              name:        "MOVWstoreidx",
 +              auxType:     auxSymOff,
 +              argLen:      4,
 +              commutative: true,
 +              symEffect:   SymWrite,
 +              asm:         s390x.AMOVW,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
 +                              {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
 +                              {2, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
 +                      },
 +              },
 +      },
 +      {
 +              name:        "MOVDstoreidx",
 +              auxType:     auxSymOff,
 +              argLen:      4,
 +              commutative: true,
 +              symEffect:   SymWrite,
 +              asm:         s390x.AMOVD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
 +                              {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
 +                              {2, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
 +                      },
 +              },
 +      },
 +      {
 +              name:        "MOVHBRstoreidx",
 +              auxType:     auxSymOff,
 +              argLen:      4,
 +              commutative: true,
 +              symEffect:   SymWrite,
 +              asm:         s390x.AMOVHBR,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
 +                              {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
 +                              {2, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
 +                      },
 +              },
 +      },
 +      {
 +              name:        "MOVWBRstoreidx",
 +              auxType:     auxSymOff,
 +              argLen:      4,
 +              commutative: true,
 +              symEffect:   SymWrite,
 +              asm:         s390x.AMOVWBR,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
 +                              {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
 +                              {2, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
 +                      },
 +              },
 +      },
 +      {
 +              name:        "MOVDBRstoreidx",
 +              auxType:     auxSymOff,
 +              argLen:      4,
 +              commutative: true,
 +              symEffect:   SymWrite,
 +              asm:         s390x.AMOVDBR,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
 +                              {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
 +                              {2, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
 +                      },
 +              },
 +      },
 +      {
 +              name:           "MOVBstoreconst",
 +              auxType:        auxSymValAndOff,
 +              argLen:         2,
 +              faultOnNilArg0: true,
 +              symEffect:      SymWrite,
 +              asm:            s390x.AMOVB,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB
 +                      },
 +              },
 +      },
 +      {
 +              name:           "MOVHstoreconst",
 +              auxType:        auxSymValAndOff,
 +              argLen:         2,
 +              faultOnNilArg0: true,
 +              symEffect:      SymWrite,
 +              asm:            s390x.AMOVH,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB
 +                      },
 +              },
 +      },
 +      {
 +              name:           "MOVWstoreconst",
 +              auxType:        auxSymValAndOff,
 +              argLen:         2,
 +              faultOnNilArg0: true,
 +              symEffect:      SymWrite,
 +              asm:            s390x.AMOVW,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB
 +                      },
 +              },
 +      },
 +      {
 +              name:           "MOVDstoreconst",
 +              auxType:        auxSymValAndOff,
 +              argLen:         2,
 +              faultOnNilArg0: true,
 +              symEffect:      SymWrite,
 +              asm:            s390x.AMOVD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB
 +                      },
 +              },
 +      },
 +      {
 +              name:           "CLEAR",
 +              auxType:        auxSymValAndOff,
 +              argLen:         2,
 +              clobberFlags:   true,
 +              faultOnNilArg0: true,
 +              symEffect:      SymWrite,
 +              asm:            s390x.ACLEAR,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 23550}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:         "CALLstatic",
 +              auxType:      auxCallOff,
 +              argLen:       1,
 +              clobberFlags: true,
 +              call:         true,
 +              reg: regInfo{
 +                      clobbers: 4294933503, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 g R14 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 +              },
 +      },
 +      {
 +              name:         "CALLtail",
 +              auxType:      auxCallOff,
 +              argLen:       1,
 +              clobberFlags: true,
 +              call:         true,
 +              tailCall:     true,
 +              reg: regInfo{
 +                      clobbers: 4294933503, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 g R14 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 +              },
 +      },
 +      {
 +              name:         "CALLclosure",
 +              auxType:      auxCallOff,
 +              argLen:       3,
 +              clobberFlags: true,
 +              call:         true,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 4096},  // R12
 +                              {0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
 +                      },
 +                      clobbers: 4294933503, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 g R14 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 +              },
 +      },
 +      {
 +              name:         "CALLinter",
 +              auxType:      auxCallOff,
 +              argLen:       2,
 +              clobberFlags: true,
 +              call:         true,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 23550}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                      },
 +                      clobbers: 4294933503, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 g R14 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 +              },
 +      },
 +      {
 +              name:   "InvertFlags",
 +              argLen: 1,
 +              reg:    regInfo{},
 +      },
 +      {
 +              name:   "LoweredGetG",
 +              argLen: 1,
 +              reg: regInfo{
 +                      outputs: []outputInfo{
 +                              {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:      "LoweredGetClosurePtr",
 +              argLen:    0,
 +              zeroWidth: true,
 +              reg: regInfo{
 +                      outputs: []outputInfo{
 +                              {0, 4096}, // R12
 +                      },
 +              },
 +      },
 +      {
 +              name:              "LoweredGetCallerSP",
 +              argLen:            1,
 +              rematerializeable: true,
 +              reg: regInfo{
 +                      outputs: []outputInfo{
 +                              {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:              "LoweredGetCallerPC",
 +              argLen:            0,
 +              rematerializeable: true,
 +              reg: regInfo{
 +                      outputs: []outputInfo{
 +                              {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:           "LoweredNilCheck",
 +              argLen:         2,
 +              clobberFlags:   true,
 +              nilCheck:       true,
 +              faultOnNilArg0: true,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
 +                      },
 +              },
 +      },
 +      {
 +              name:         "LoweredRound32F",
 +              argLen:       1,
 +              resultInArg0: true,
 +              zeroWidth:    true,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 +                      },
 +              },
 +      },
 +      {
 +              name:         "LoweredRound64F",
 +              argLen:       1,
 +              resultInArg0: true,
 +              zeroWidth:    true,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 +                      },
 +              },
 +      },
 +      {
 +              name:         "LoweredWB",
 +              auxType:      auxInt64,
 +              argLen:       1,
 +              clobberFlags: true,
 +              reg: regInfo{
 +                      clobbers: 4294918146, // R1 R14 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 +                      outputs: []outputInfo{
 +                              {0, 512}, // R9
 +                      },
 +              },
 +      },
 +      {
 +              name:    "LoweredPanicBoundsRR",
 +              auxType: auxInt64,
 +              argLen:  3,
 +              call:    true,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 7167}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12
 +                              {1, 7167}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12
 +                      },
 +              },
 +      },
 +      {
 +              name:    "LoweredPanicBoundsRC",
 +              auxType: auxPanicBoundsC,
 +              argLen:  2,
 +              call:    true,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 7167}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12
 +                      },
 +              },
 +      },
 +      {
 +              name:    "LoweredPanicBoundsCR",
 +              auxType: auxPanicBoundsC,
 +              argLen:  2,
 +              call:    true,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 7167}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12
 +                      },
 +              },
 +      },
 +      {
 +              name:    "LoweredPanicBoundsCC",
 +              auxType: auxPanicBoundsCC,
 +              argLen:  1,
 +              call:    true,
 +              reg:     regInfo{},
 +      },
 +      {
 +              name:   "FlagEQ",
 +              argLen: 0,
 +              reg:    regInfo{},
 +      },
 +      {
 +              name:   "FlagLT",
 +              argLen: 0,
 +              reg:    regInfo{},
 +      },
 +      {
 +              name:   "FlagGT",
 +              argLen: 0,
 +              reg:    regInfo{},
 +      },
 +      {
 +              name:   "FlagOV",
 +              argLen: 0,
 +              reg:    regInfo{},
 +      },
 +      {
 +              name:   "SYNC",
 +              argLen: 1,
 +              asm:    s390x.ASYNC,
 +              reg:    regInfo{},
 +      },
 +      {
 +              name:           "MOVBZatomicload",
 +              auxType:        auxSymOff,
 +              argLen:         2,
 +              faultOnNilArg0: true,
 +              symEffect:      SymRead,
 +              asm:            s390x.AMOVBZ,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:           "MOVWZatomicload",
 +              auxType:        auxSymOff,
 +              argLen:         2,
 +              faultOnNilArg0: true,
 +              symEffect:      SymRead,
 +              asm:            s390x.AMOVWZ,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:           "MOVDatomicload",
 +              auxType:        auxSymOff,
 +              argLen:         2,
 +              faultOnNilArg0: true,
 +              symEffect:      SymRead,
 +              asm:            s390x.AMOVD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:           "MOVBatomicstore",
 +              auxType:        auxSymOff,
 +              argLen:         3,
 +              clobberFlags:   true,
 +              faultOnNilArg0: true,
 +              hasSideEffects: true,
 +              symEffect:      SymWrite,
 +              asm:            s390x.AMOVB,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB
 +                              {1, 56319},      // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
 +                      },
 +              },
 +      },
 +      {
 +              name:           "MOVWatomicstore",
 +              auxType:        auxSymOff,
 +              argLen:         3,
 +              clobberFlags:   true,
 +              faultOnNilArg0: true,
 +              hasSideEffects: true,
 +              symEffect:      SymWrite,
 +              asm:            s390x.AMOVW,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB
 +                              {1, 56319},      // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
 +                      },
 +              },
 +      },
 +      {
 +              name:           "MOVDatomicstore",
 +              auxType:        auxSymOff,
 +              argLen:         3,
 +              clobberFlags:   true,
 +              faultOnNilArg0: true,
 +              hasSideEffects: true,
 +              symEffect:      SymWrite,
 +              asm:            s390x.AMOVD,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB
 +                              {1, 56319},      // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
 +                      },
 +              },
 +      },
 +      {
 +              name:           "LAA",
 +              auxType:        auxSymOff,
 +              argLen:         3,
 +              clobberFlags:   true,
 +              faultOnNilArg0: true,
 +              hasSideEffects: true,
 +              symEffect:      SymRdWr,
 +              asm:            s390x.ALAA,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB
 +                              {1, 56319},      // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:           "LAAG",
 +              auxType:        auxSymOff,
 +              argLen:         3,
 +              clobberFlags:   true,
 +              faultOnNilArg0: true,
 +              hasSideEffects: true,
 +              symEffect:      SymRdWr,
 +              asm:            s390x.ALAAG,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB
 +                              {1, 56319},      // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:   "AddTupleFirst32",
 +              argLen: 2,
 +              reg:    regInfo{},
 +      },
 +      {
 +              name:   "AddTupleFirst64",
 +              argLen: 2,
 +              reg:    regInfo{},
 +      },
 +      {
 +              name:           "LAN",
 +              argLen:         3,
 +              clobberFlags:   true,
 +              hasSideEffects: true,
 +              asm:            s390x.ALAN,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB
 +                              {1, 56319},      // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
 +                      },
 +              },
 +      },
 +      {
 +              name:           "LANfloor",
 +              argLen:         3,
 +              clobberFlags:   true,
 +              hasSideEffects: true,
 +              asm:            s390x.ALAN,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 2},     // R1
 +                              {1, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
 +                      },
 +                      clobbers: 2, // R1
 +              },
 +      },
 +      {
 +              name:           "LAO",
 +              argLen:         3,
 +              clobberFlags:   true,
 +              hasSideEffects: true,
 +              asm:            s390x.ALAO,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB
 +                              {1, 56319},      // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
 +                      },
 +              },
 +      },
 +      {
 +              name:           "LAOfloor",
 +              argLen:         3,
 +              clobberFlags:   true,
 +              hasSideEffects: true,
 +              asm:            s390x.ALAO,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 2},     // R1
 +                              {1, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
 +                      },
 +                      clobbers: 2, // R1
 +              },
 +      },
 +      {
 +              name:           "LoweredAtomicCas32",
 +              auxType:        auxSymOff,
 +              argLen:         4,
 +              clobberFlags:   true,
 +              faultOnNilArg0: true,
 +              hasSideEffects: true,
 +              symEffect:      SymRdWr,
 +              asm:            s390x.ACS,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 1},     // R0
 +                              {0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
 +                              {2, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
 +                      },
 +                      clobbers: 1, // R0
 +                      outputs: []outputInfo{
 +                              {1, 0},
 +                              {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:           "LoweredAtomicCas64",
 +              auxType:        auxSymOff,
 +              argLen:         4,
 +              clobberFlags:   true,
 +              faultOnNilArg0: true,
 +              hasSideEffects: true,
 +              symEffect:      SymRdWr,
 +              asm:            s390x.ACSG,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 1},     // R0
 +                              {0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
 +                              {2, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
 +                      },
 +                      clobbers: 1, // R0
 +                      outputs: []outputInfo{
 +                              {1, 0},
 +                              {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:           "LoweredAtomicExchange32",
 +              auxType:        auxSymOff,
 +              argLen:         3,
 +              clobberFlags:   true,
 +              faultOnNilArg0: true,
 +              hasSideEffects: true,
 +              symEffect:      SymRdWr,
 +              asm:            s390x.ACS,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
 +                              {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
 +                      },
 +                      outputs: []outputInfo{
 +                              {1, 0},
 +                              {0, 1}, // R0
 +                      },
 +              },
 +      },
 +      {
 +              name:           "LoweredAtomicExchange64",
 +              auxType:        auxSymOff,
 +              argLen:         3,
 +              clobberFlags:   true,
 +              faultOnNilArg0: true,
 +              hasSideEffects: true,
 +              symEffect:      SymRdWr,
 +              asm:            s390x.ACSG,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
 +                              {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
 +                      },
 +                      outputs: []outputInfo{
 +                              {1, 0},
 +                              {0, 1}, // R0
 +                      },
 +              },
 +      },
 +      {
 +              name:         "FLOGR",
 +              argLen:       1,
 +              clobberFlags: true,
 +              asm:          s390x.AFLOGR,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                      },
 +                      clobbers: 2, // R1
 +                      outputs: []outputInfo{
 +                              {0, 1}, // R0
 +                      },
 +              },
 +      },
 +      {
 +              name:         "POPCNT",
 +              argLen:       1,
 +              clobberFlags: true,
 +              asm:          s390x.APOPCNT,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                      },
 +              },
 +      },
 +      {
 +              name:   "MLGR",
 +              argLen: 2,
 +              asm:    s390x.AMLGR,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 8},     // R3
 +                              {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 4}, // R2
 +                              {1, 8}, // R3
 +                      },
 +              },
 +      },
 +      {
 +              name:   "SumBytes2",
 +              argLen: 1,
 +              reg:    regInfo{},
 +      },
 +      {
 +              name:   "SumBytes4",
 +              argLen: 1,
 +              reg:    regInfo{},
 +      },
 +      {
 +              name:   "SumBytes8",
 +              argLen: 1,
 +              reg:    regInfo{},
 +      },
 +      {
 +              name:           "STMG2",
 +              auxType:        auxSymOff,
 +              argLen:         4,
 +              clobberFlags:   true,
 +              faultOnNilArg0: true,
 +              symEffect:      SymWrite,
 +              asm:            s390x.ASTMG,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 2},     // R1
 +                              {2, 4},     // R2
 +                              {0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
 +                      },
 +              },
 +      },
 +      {
 +              name:           "STMG3",
 +              auxType:        auxSymOff,
 +              argLen:         5,
 +              clobberFlags:   true,
 +              faultOnNilArg0: true,
 +              symEffect:      SymWrite,
 +              asm:            s390x.ASTMG,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 2},     // R1
 +                              {2, 4},     // R2
 +                              {3, 8},     // R3
 +                              {0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
 +                      },
 +              },
 +      },
 +      {
 +              name:           "STMG4",
 +              auxType:        auxSymOff,
 +              argLen:         6,
 +              clobberFlags:   true,
 +              faultOnNilArg0: true,
 +              symEffect:      SymWrite,
 +              asm:            s390x.ASTMG,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 2},     // R1
 +                              {2, 4},     // R2
 +                              {3, 8},     // R3
 +                              {4, 16},    // R4
 +                              {0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
 +                      },
 +              },
 +      },
 +      {
 +              name:           "STM2",
 +              auxType:        auxSymOff,
 +              argLen:         4,
 +              clobberFlags:   true,
 +              faultOnNilArg0: true,
 +              symEffect:      SymWrite,
 +              asm:            s390x.ASTMY,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 2},     // R1
 +                              {2, 4},     // R2
 +                              {0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
 +                      },
 +              },
 +      },
 +      {
 +              name:           "STM3",
 +              auxType:        auxSymOff,
 +              argLen:         5,
 +              clobberFlags:   true,
 +              faultOnNilArg0: true,
 +              symEffect:      SymWrite,
 +              asm:            s390x.ASTMY,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 2},     // R1
 +                              {2, 4},     // R2
 +                              {3, 8},     // R3
 +                              {0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
 +                      },
 +              },
 +      },
 +      {
 +              name:           "STM4",
 +              auxType:        auxSymOff,
 +              argLen:         6,
 +              clobberFlags:   true,
 +              faultOnNilArg0: true,
 +              symEffect:      SymWrite,
 +              asm:            s390x.ASTMY,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 2},     // R1
 +                              {2, 4},     // R2
 +                              {3, 8},     // R3
 +                              {4, 16},    // R4
 +                              {0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
 +                      },
 +              },
 +      },
 +      {
 +              name:           "LoweredMove",
 +              auxType:        auxInt64,
 +              argLen:         4,
 +              clobberFlags:   true,
 +              faultOnNilArg0: true,
 +              faultOnNilArg1: true,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 2},     // R1
 +                              {1, 4},     // R2
 +                              {2, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
 +                      },
 +                      clobbers: 6, // R1 R2
 +              },
 +      },
 +      {
 +              name:           "LoweredZero",
 +              auxType:        auxInt64,
 +              argLen:         3,
 +              clobberFlags:   true,
 +              faultOnNilArg0: true,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 2},     // R1
 +                              {1, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
 +                      },
 +                      clobbers: 2, // R1
 +              },
 +      },
 +
 +      {
 +              name:    "LoweredStaticCall",
 +              auxType: auxCallOff,
 +              argLen:  1,
 +              call:    true,
 +              reg: regInfo{
 +                      clobbers: 844424930131967, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 g
 +              },
 +      },
 +      {
 +              name:     "LoweredTailCall",
 +              auxType:  auxCallOff,
 +              argLen:   1,
 +              call:     true,
 +              tailCall: true,
 +              reg: regInfo{
 +                      clobbers: 844424930131967, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 g
 +              },
 +      },
 +      {
 +              name:    "LoweredClosureCall",
 +              auxType: auxCallOff,
 +              argLen:  3,
 +              call:    true,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
 +                              {1, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
 +                      },
 +                      clobbers: 844424930131967, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 g
 +              },
 +      },
 +      {
 +              name:    "LoweredInterCall",
 +              auxType: auxCallOff,
 +              argLen:  2,
 +              call:    true,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
 +                      },
 +                      clobbers: 844424930131967, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 g
 +              },
 +      },
 +      {
 +              name:              "LoweredAddr",
 +              auxType:           auxSymOff,
 +              argLen:            1,
 +              rematerializeable: true,
 +              symEffect:         SymAddr,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
 +                      },
 +              },
 +      },
 +      {
 +              name:    "LoweredMove",
 +              auxType: auxInt64,
 +              argLen:  3,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
 +                              {1, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
 +                      },
 +              },
 +      },
 +      {
 +              name:    "LoweredZero",
 +              auxType: auxInt64,
 +              argLen:  2,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
 +                      },
 +              },
 +      },
 +      {
 +              name:   "LoweredGetClosurePtr",
 +              argLen: 0,
 +              reg: regInfo{
 +                      outputs: []outputInfo{
 +                              {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
 +                      },
 +              },
 +      },
 +      {
 +              name:              "LoweredGetCallerPC",
 +              argLen:            0,
 +              rematerializeable: true,
 +              reg: regInfo{
 +                      outputs: []outputInfo{
 +                              {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
 +                      },
 +              },
 +      },
 +      {
 +              name:              "LoweredGetCallerSP",
 +              argLen:            1,
 +              rematerializeable: true,
 +              reg: regInfo{
 +                      outputs: []outputInfo{
 +                              {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
 +                      },
 +              },
 +      },
 +      {
 +              name:           "LoweredNilCheck",
 +              argLen:         2,
 +              nilCheck:       true,
 +              faultOnNilArg0: true,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
 +                      },
 +              },
 +      },
 +      {
 +              name:    "LoweredWB",
 +              auxType: auxInt64,
 +              argLen:  1,
 +              reg: regInfo{
 +                      clobbers: 844424930131967, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 g
 +                      outputs: []outputInfo{
 +                              {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
 +                      },
 +              },
 +      },
 +      {
 +              name:   "LoweredConvert",
 +              argLen: 2,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
 +                      },
 +              },
 +      },
 +      {
 +              name:   "Select",
 +              argLen: 3,
 +              asm:    wasm.ASelect,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
 +                              {1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
 +                              {2, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
 +                      },
 +              },
 +      },
 +      {
 +              name:    "I64Load8U",
 +              auxType: auxInt64,
 +              argLen:  2,
 +              asm:     wasm.AI64Load8U,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1407374883618815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
 +                      },
 +              },
 +      },
 +      {
 +              name:    "I64Load8S",
 +              auxType: auxInt64,
 +              argLen:  2,
 +              asm:     wasm.AI64Load8S,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1407374883618815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
 +                      },
 +              },
 +      },
 +      {
 +              name:    "I64Load16U",
 +              auxType: auxInt64,
 +              argLen:  2,
 +              asm:     wasm.AI64Load16U,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1407374883618815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
 +                      },
 +              },
 +      },
 +      {
 +              name:    "I64Load16S",
 +              auxType: auxInt64,
 +              argLen:  2,
 +              asm:     wasm.AI64Load16S,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1407374883618815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
 +                      },
 +              },
 +      },
 +      {
 +              name:    "I64Load32U",
 +              auxType: auxInt64,
 +              argLen:  2,
 +              asm:     wasm.AI64Load32U,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1407374883618815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
 +                      },
 +              },
 +      },
 +      {
 +              name:    "I64Load32S",
 +              auxType: auxInt64,
 +              argLen:  2,
 +              asm:     wasm.AI64Load32S,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1407374883618815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
 +                      },
 +              },
 +      },
 +      {
 +              name:    "I64Load",
 +              auxType: auxInt64,
 +              argLen:  2,
 +              asm:     wasm.AI64Load,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1407374883618815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
 +                      },
 +              },
 +      },
 +      {
 +              name:    "I64Store8",
 +              auxType: auxInt64,
 +              argLen:  3,
 +              asm:     wasm.AI64Store8,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 281474976776191},  // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
 +                              {0, 1407374883618815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP SB
 +                      },
 +              },
 +      },
 +      {
 +              name:    "I64Store16",
 +              auxType: auxInt64,
 +              argLen:  3,
 +              asm:     wasm.AI64Store16,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 281474976776191},  // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
 +                              {0, 1407374883618815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP SB
 +                      },
 +              },
 +      },
 +      {
 +              name:    "I64Store32",
 +              auxType: auxInt64,
 +              argLen:  3,
 +              asm:     wasm.AI64Store32,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 281474976776191},  // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
 +                              {0, 1407374883618815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP SB
 +                      },
 +              },
 +      },
 +      {
 +              name:    "I64Store",
 +              auxType: auxInt64,
 +              argLen:  3,
 +              asm:     wasm.AI64Store,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 281474976776191},  // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
 +                              {0, 1407374883618815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP SB
 +                      },
 +              },
 +      },
 +      {
 +              name:    "F32Load",
 +              auxType: auxInt64,
 +              argLen:  2,
 +              asm:     wasm.AF32Load,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1407374883618815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 +                      },
 +              },
 +      },
 +      {
 +              name:    "F64Load",
 +              auxType: auxInt64,
 +              argLen:  2,
 +              asm:     wasm.AF64Load,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 1407374883618815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP SB
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +              },
 +      },
 +      {
 +              name:    "F32Store",
 +              auxType: auxInt64,
 +              argLen:  3,
 +              asm:     wasm.AF32Store,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 4294901760},       // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 +                              {0, 1407374883618815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP SB
 +                      },
 +              },
 +      },
 +      {
 +              name:    "F64Store",
 +              auxType: auxInt64,
 +              argLen:  3,
 +              asm:     wasm.AF64Store,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {1, 281470681743360},  // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                              {0, 1407374883618815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP SB
 +                      },
 +              },
 +      },
 +      {
 +              name:              "I64Const",
 +              auxType:           auxInt64,
 +              argLen:            0,
 +              rematerializeable: true,
 +              reg: regInfo{
 +                      outputs: []outputInfo{
 +                              {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
 +                      },
 +              },
 +      },
 +      {
 +              name:              "F32Const",
 +              auxType:           auxFloat32,
 +              argLen:            0,
 +              rematerializeable: true,
 +              reg: regInfo{
 +                      outputs: []outputInfo{
 +                              {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 +                      },
 +              },
 +      },
 +      {
 +              name:              "F64Const",
 +              auxType:           auxFloat64,
 +              argLen:            0,
 +              rematerializeable: true,
 +              reg: regInfo{
 +                      outputs: []outputInfo{
 +                              {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +              },
 +      },
 +      {
 +              name:   "I64Eqz",
 +              argLen: 1,
 +              asm:    wasm.AI64Eqz,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
 +                      },
 +              },
 +      },
 +      {
 +              name:   "I64Eq",
 +              argLen: 2,
 +              asm:    wasm.AI64Eq,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
 +                              {1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
 +                      },
 +              },
 +      },
 +      {
 +              name:   "I64Ne",
 +              argLen: 2,
 +              asm:    wasm.AI64Ne,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
 +                              {1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
 +                      },
 +              },
 +      },
 +      {
 +              name:   "I64LtS",
 +              argLen: 2,
 +              asm:    wasm.AI64LtS,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
 +                              {1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
 +                      },
 +              },
 +      },
 +      {
 +              name:   "I64LtU",
 +              argLen: 2,
 +              asm:    wasm.AI64LtU,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
 +                              {1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
 +                      },
 +              },
 +      },
 +      {
 +              name:   "I64GtS",
 +              argLen: 2,
 +              asm:    wasm.AI64GtS,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
 +                              {1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
 +                      },
 +              },
 +      },
 +      {
 +              name:   "I64GtU",
 +              argLen: 2,
 +              asm:    wasm.AI64GtU,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
 +                              {1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
 +                      },
 +              },
 +      },
 +      {
 +              name:   "I64LeS",
 +              argLen: 2,
 +              asm:    wasm.AI64LeS,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
 +                              {1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
 +                      },
 +              },
 +      },
 +      {
 +              name:   "I64LeU",
 +              argLen: 2,
 +              asm:    wasm.AI64LeU,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
 +                              {1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
 +                      },
 +              },
 +      },
 +      {
 +              name:   "I64GeS",
 +              argLen: 2,
 +              asm:    wasm.AI64GeS,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
 +                              {1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
 +                      },
 +              },
 +      },
 +      {
 +              name:   "I64GeU",
 +              argLen: 2,
 +              asm:    wasm.AI64GeU,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
 +                              {1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
 +                      },
 +              },
 +      },
 +      {
 +              name:   "F32Eq",
 +              argLen: 2,
 +              asm:    wasm.AF32Eq,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 +                              {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
 +                      },
 +              },
 +      },
 +      {
 +              name:   "F32Ne",
 +              argLen: 2,
 +              asm:    wasm.AF32Ne,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 +                              {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
 +                      },
 +              },
 +      },
 +      {
 +              name:   "F32Lt",
 +              argLen: 2,
 +              asm:    wasm.AF32Lt,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 +                              {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
 +                      },
 +              },
 +      },
 +      {
 +              name:   "F32Gt",
 +              argLen: 2,
 +              asm:    wasm.AF32Gt,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 +                              {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
 +                      },
 +              },
 +      },
 +      {
 +              name:   "F32Le",
 +              argLen: 2,
 +              asm:    wasm.AF32Le,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 +                              {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
 +                      },
 +              },
 +      },
 +      {
 +              name:   "F32Ge",
 +              argLen: 2,
 +              asm:    wasm.AF32Ge,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 +                              {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
 +                      },
 +              },
 +      },
 +      {
 +              name:   "F64Eq",
 +              argLen: 2,
 +              asm:    wasm.AF64Eq,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                              {1, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
 +                      },
 +              },
 +      },
 +      {
 +              name:   "F64Ne",
 +              argLen: 2,
 +              asm:    wasm.AF64Ne,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                              {1, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
 +                      },
 +              },
 +      },
 +      {
 +              name:   "F64Lt",
 +              argLen: 2,
 +              asm:    wasm.AF64Lt,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                              {1, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
 +                      },
 +              },
 +      },
 +      {
 +              name:   "F64Gt",
 +              argLen: 2,
 +              asm:    wasm.AF64Gt,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                              {1, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
 +                      },
 +              },
 +      },
 +      {
 +              name:   "F64Le",
 +              argLen: 2,
 +              asm:    wasm.AF64Le,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                              {1, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
 +                      },
 +              },
 +      },
 +      {
 +              name:   "F64Ge",
 +              argLen: 2,
 +              asm:    wasm.AF64Ge,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                              {1, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
 +                      },
 +              },
 +      },
 +      {
 +              name:   "I64Add",
 +              argLen: 2,
 +              asm:    wasm.AI64Add,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
 +                              {1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
 +                      },
 +              },
 +      },
 +      {
 +              name:    "I64AddConst",
 +              auxType: auxInt64,
 +              argLen:  1,
 +              asm:     wasm.AI64Add,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
 +                      },
 +              },
 +      },
 +      {
 +              name:   "I64Sub",
 +              argLen: 2,
 +              asm:    wasm.AI64Sub,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
 +                              {1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
 +                      },
 +              },
 +      },
 +      {
 +              name:   "I64Mul",
 +              argLen: 2,
 +              asm:    wasm.AI64Mul,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
 +                              {1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
 +                      },
 +              },
 +      },
 +      {
 +              name:   "I64DivS",
 +              argLen: 2,
 +              asm:    wasm.AI64DivS,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
 +                              {1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
 +                      },
 +              },
 +      },
 +      {
 +              name:   "I64DivU",
 +              argLen: 2,
 +              asm:    wasm.AI64DivU,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
 +                              {1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
 +                      },
 +              },
 +      },
 +      {
 +              name:   "I64RemS",
 +              argLen: 2,
 +              asm:    wasm.AI64RemS,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
 +                              {1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
 +                      },
 +              },
 +      },
 +      {
 +              name:   "I64RemU",
 +              argLen: 2,
 +              asm:    wasm.AI64RemU,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
 +                              {1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
 +                      },
 +              },
 +      },
 +      {
 +              name:   "I64And",
 +              argLen: 2,
 +              asm:    wasm.AI64And,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
 +                              {1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
 +                      },
 +              },
 +      },
 +      {
 +              name:   "I64Or",
 +              argLen: 2,
 +              asm:    wasm.AI64Or,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
 +                              {1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
 +                      },
 +              },
 +      },
 +      {
 +              name:   "I64Xor",
 +              argLen: 2,
 +              asm:    wasm.AI64Xor,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
 +                              {1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
 +                      },
 +              },
 +      },
 +      {
 +              name:   "I64Shl",
 +              argLen: 2,
 +              asm:    wasm.AI64Shl,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
 +                              {1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
 +                      },
 +              },
 +      },
 +      {
 +              name:   "I64ShrS",
 +              argLen: 2,
 +              asm:    wasm.AI64ShrS,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
 +                              {1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
 +                      },
 +              },
 +      },
 +      {
 +              name:   "I64ShrU",
 +              argLen: 2,
 +              asm:    wasm.AI64ShrU,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
 +                              {1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
 +                      },
 +              },
 +      },
 +      {
 +              name:   "F32Neg",
 +              argLen: 1,
 +              asm:    wasm.AF32Neg,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 +                      },
 +              },
 +      },
 +      {
 +              name:   "F32Add",
 +              argLen: 2,
 +              asm:    wasm.AF32Add,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 +                              {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 +                      },
 +              },
 +      },
 +      {
 +              name:   "F32Sub",
 +              argLen: 2,
 +              asm:    wasm.AF32Sub,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 +                              {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 +                      },
 +              },
 +      },
 +      {
 +              name:   "F32Mul",
 +              argLen: 2,
 +              asm:    wasm.AF32Mul,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 +                              {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 +                      },
 +              },
 +      },
 +      {
 +              name:   "F32Div",
 +              argLen: 2,
 +              asm:    wasm.AF32Div,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 +                              {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 +                      },
 +              },
 +      },
 +      {
 +              name:   "F64Neg",
 +              argLen: 1,
 +              asm:    wasm.AF64Neg,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +              },
 +      },
 +      {
 +              name:   "F64Add",
 +              argLen: 2,
 +              asm:    wasm.AF64Add,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                              {1, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +              },
 +      },
 +      {
 +              name:   "F64Sub",
 +              argLen: 2,
 +              asm:    wasm.AF64Sub,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                              {1, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +              },
 +      },
 +      {
 +              name:   "F64Mul",
 +              argLen: 2,
 +              asm:    wasm.AF64Mul,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                              {1, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +              },
 +      },
 +      {
 +              name:   "F64Div",
 +              argLen: 2,
 +              asm:    wasm.AF64Div,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                              {1, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +              },
 +      },
 +      {
 +              name:   "I64TruncSatF64S",
 +              argLen: 1,
 +              asm:    wasm.AI64TruncSatF64S,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
 +                      },
 +              },
 +      },
 +      {
 +              name:   "I64TruncSatF64U",
 +              argLen: 1,
 +              asm:    wasm.AI64TruncSatF64U,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
 +                      },
 +              },
 +      },
 +      {
 +              name:   "I64TruncSatF32S",
 +              argLen: 1,
 +              asm:    wasm.AI64TruncSatF32S,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
 +                      },
 +              },
 +      },
 +      {
 +              name:   "I64TruncSatF32U",
 +              argLen: 1,
 +              asm:    wasm.AI64TruncSatF32U,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
 +                      },
 +              },
 +      },
 +      {
 +              name:   "F32ConvertI64S",
 +              argLen: 1,
 +              asm:    wasm.AF32ConvertI64S,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 +                      },
 +              },
 +      },
 +      {
 +              name:   "F32ConvertI64U",
 +              argLen: 1,
 +              asm:    wasm.AF32ConvertI64U,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 +                      },
 +              },
 +      },
 +      {
 +              name:   "F64ConvertI64S",
 +              argLen: 1,
 +              asm:    wasm.AF64ConvertI64S,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +              },
 +      },
 +      {
 +              name:   "F64ConvertI64U",
 +              argLen: 1,
 +              asm:    wasm.AF64ConvertI64U,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +              },
 +      },
 +      {
 +              name:   "F32DemoteF64",
 +              argLen: 1,
 +              asm:    wasm.AF32DemoteF64,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 +                      },
 +              },
 +      },
 +      {
 +              name:   "F64PromoteF32",
 +              argLen: 1,
 +              asm:    wasm.AF64PromoteF32,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +              },
 +      },
 +      {
 +              name:   "I64Extend8S",
 +              argLen: 1,
 +              asm:    wasm.AI64Extend8S,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
 +                      },
 +              },
 +      },
 +      {
 +              name:   "I64Extend16S",
 +              argLen: 1,
 +              asm:    wasm.AI64Extend16S,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
 +                      },
 +              },
 +      },
 +      {
 +              name:   "I64Extend32S",
 +              argLen: 1,
 +              asm:    wasm.AI64Extend32S,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
 +                      },
 +              },
 +      },
 +      {
 +              name:   "F32Sqrt",
 +              argLen: 1,
 +              asm:    wasm.AF32Sqrt,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 +                      },
 +              },
 +      },
 +      {
 +              name:   "F32Trunc",
 +              argLen: 1,
 +              asm:    wasm.AF32Trunc,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 +                      },
 +              },
 +      },
 +      {
 +              name:   "F32Ceil",
 +              argLen: 1,
 +              asm:    wasm.AF32Ceil,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 +                      },
 +              },
 +      },
 +      {
 +              name:   "F32Floor",
 +              argLen: 1,
 +              asm:    wasm.AF32Floor,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 +                      },
 +              },
 +      },
 +      {
 +              name:   "F32Nearest",
 +              argLen: 1,
 +              asm:    wasm.AF32Nearest,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 +                      },
 +              },
 +      },
 +      {
 +              name:   "F32Abs",
 +              argLen: 1,
 +              asm:    wasm.AF32Abs,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 +                      },
 +              },
 +      },
 +      {
 +              name:   "F32Copysign",
 +              argLen: 2,
 +              asm:    wasm.AF32Copysign,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 +                              {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
 +                      },
 +              },
 +      },
 +      {
 +              name:   "F64Sqrt",
 +              argLen: 1,
 +              asm:    wasm.AF64Sqrt,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +              },
 +      },
 +      {
 +              name:   "F64Trunc",
 +              argLen: 1,
 +              asm:    wasm.AF64Trunc,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +              },
 +      },
 +      {
 +              name:   "F64Ceil",
 +              argLen: 1,
 +              asm:    wasm.AF64Ceil,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +              },
 +      },
 +      {
 +              name:   "F64Floor",
 +              argLen: 1,
 +              asm:    wasm.AF64Floor,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +              },
 +      },
 +      {
 +              name:   "F64Nearest",
 +              argLen: 1,
 +              asm:    wasm.AF64Nearest,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +              },
 +      },
 +      {
 +              name:   "F64Abs",
 +              argLen: 1,
 +              asm:    wasm.AF64Abs,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +              },
 +      },
 +      {
 +              name:   "F64Copysign",
 +              argLen: 2,
 +              asm:    wasm.AF64Copysign,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                              {1, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
 +                      },
 +              },
 +      },
 +      {
 +              name:   "I64Ctz",
 +              argLen: 1,
 +              asm:    wasm.AI64Ctz,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
 +                      },
 +              },
 +      },
 +      {
 +              name:   "I64Clz",
 +              argLen: 1,
 +              asm:    wasm.AI64Clz,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
 +                      },
 +              },
 +      },
 +      {
 +              name:   "I32Rotl",
 +              argLen: 2,
 +              asm:    wasm.AI32Rotl,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
 +                              {1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
 +                      },
 +              },
 +      },
 +      {
 +              name:   "I64Rotl",
 +              argLen: 2,
 +              asm:    wasm.AI64Rotl,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
 +                              {1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
 +                      },
 +              },
 +      },
 +      {
 +              name:   "I64Popcnt",
 +              argLen: 1,
 +              asm:    wasm.AI64Popcnt,
 +              reg: regInfo{
 +                      inputs: []inputInfo{
 +                              {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
 +                      },
 +                      outputs: []outputInfo{
 +                              {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
 +                      },
 +              },
 +      },
 +
 +      {
 +              name:    "Last",
 +              argLen:  -1,
 +              generic: true,
 +      },
 +      {
 +              name:        "Add8",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "Add16",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "Add32",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "Add64",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:    "AddPtr",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:        "Add32F",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "Add64F",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:    "Sub8",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "Sub16",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "Sub32",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "Sub64",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "SubPtr",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "Sub32F",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "Sub64F",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:        "Mul8",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "Mul16",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "Mul32",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "Mul64",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "Mul32F",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "Mul64F",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:    "Div32F",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "Div64F",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:        "Hmul32",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "Hmul32u",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "Hmul64",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "Hmul64u",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "Mul32uhilo",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "Mul64uhilo",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "Mul32uover",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "Mul64uover",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:    "Avg32u",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "Avg64u",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "Div8",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "Div8u",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "Div16",
 +              auxType: auxBool,
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "Div16u",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "Div32",
 +              auxType: auxBool,
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "Div32u",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "Div64",
 +              auxType: auxBool,
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "Div64u",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "Div128u",
 +              argLen:  3,
 +              generic: true,
 +      },
 +      {
 +              name:    "Mod8",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "Mod8u",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "Mod16",
 +              auxType: auxBool,
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "Mod16u",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "Mod32",
 +              auxType: auxBool,
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "Mod32u",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "Mod64",
 +              auxType: auxBool,
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "Mod64u",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:        "And8",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "And16",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "And32",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "And64",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "Or8",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "Or16",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "Or32",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "Or64",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "Xor8",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "Xor16",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "Xor32",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "Xor64",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:    "Lsh8x8",
 +              auxType: auxBool,
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "Lsh8x16",
 +              auxType: auxBool,
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "Lsh8x32",
 +              auxType: auxBool,
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "Lsh8x64",
 +              auxType: auxBool,
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "Lsh16x8",
 +              auxType: auxBool,
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "Lsh16x16",
 +              auxType: auxBool,
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "Lsh16x32",
 +              auxType: auxBool,
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "Lsh16x64",
 +              auxType: auxBool,
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "Lsh32x8",
 +              auxType: auxBool,
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "Lsh32x16",
 +              auxType: auxBool,
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "Lsh32x32",
 +              auxType: auxBool,
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "Lsh32x64",
 +              auxType: auxBool,
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "Lsh64x8",
 +              auxType: auxBool,
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "Lsh64x16",
 +              auxType: auxBool,
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "Lsh64x32",
 +              auxType: auxBool,
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "Lsh64x64",
 +              auxType: auxBool,
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "Rsh8x8",
 +              auxType: auxBool,
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "Rsh8x16",
 +              auxType: auxBool,
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "Rsh8x32",
 +              auxType: auxBool,
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "Rsh8x64",
 +              auxType: auxBool,
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "Rsh16x8",
 +              auxType: auxBool,
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "Rsh16x16",
 +              auxType: auxBool,
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "Rsh16x32",
 +              auxType: auxBool,
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "Rsh16x64",
 +              auxType: auxBool,
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "Rsh32x8",
 +              auxType: auxBool,
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "Rsh32x16",
 +              auxType: auxBool,
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "Rsh32x32",
 +              auxType: auxBool,
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "Rsh32x64",
 +              auxType: auxBool,
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "Rsh64x8",
 +              auxType: auxBool,
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "Rsh64x16",
 +              auxType: auxBool,
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "Rsh64x32",
 +              auxType: auxBool,
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "Rsh64x64",
 +              auxType: auxBool,
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "Rsh8Ux8",
 +              auxType: auxBool,
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "Rsh8Ux16",
 +              auxType: auxBool,
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "Rsh8Ux32",
 +              auxType: auxBool,
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "Rsh8Ux64",
 +              auxType: auxBool,
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "Rsh16Ux8",
 +              auxType: auxBool,
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "Rsh16Ux16",
 +              auxType: auxBool,
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "Rsh16Ux32",
 +              auxType: auxBool,
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "Rsh16Ux64",
 +              auxType: auxBool,
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "Rsh32Ux8",
 +              auxType: auxBool,
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "Rsh32Ux16",
 +              auxType: auxBool,
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "Rsh32Ux32",
 +              auxType: auxBool,
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "Rsh32Ux64",
 +              auxType: auxBool,
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "Rsh64Ux8",
 +              auxType: auxBool,
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "Rsh64Ux16",
 +              auxType: auxBool,
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "Rsh64Ux32",
 +              auxType: auxBool,
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "Rsh64Ux64",
 +              auxType: auxBool,
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:        "Eq8",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "Eq16",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "Eq32",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "Eq64",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "EqPtr",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:    "EqInter",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "EqSlice",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:        "Eq32F",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "Eq64F",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "Neq8",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "Neq16",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "Neq32",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "Neq64",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "NeqPtr",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:    "NeqInter",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "NeqSlice",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:        "Neq32F",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "Neq64F",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:    "Less8",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "Less8U",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "Less16",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "Less16U",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "Less32",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "Less32U",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "Less64",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "Less64U",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "Less32F",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "Less64F",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "Leq8",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "Leq8U",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "Leq16",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "Leq16U",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "Leq32",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "Leq32U",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "Leq64",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "Leq64U",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "Leq32F",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "Leq64F",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "CondSelect",
 +              argLen:  3,
 +              generic: true,
 +      },
 +      {
 +              name:        "AndB",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "OrB",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "EqB",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "NeqB",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:    "Not",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "Neg8",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "Neg16",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "Neg32",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "Neg64",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "Neg32F",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "Neg64F",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "Com8",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "Com16",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "Com32",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "Com64",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "Ctz8",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "Ctz16",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "Ctz32",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "Ctz64",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "Ctz64On32",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "Ctz8NonZero",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "Ctz16NonZero",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "Ctz32NonZero",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "Ctz64NonZero",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "BitLen8",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "BitLen16",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "BitLen32",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "BitLen64",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "Bswap16",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "Bswap32",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "Bswap64",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "BitRev8",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "BitRev16",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "BitRev32",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "BitRev64",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "PopCount8",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "PopCount16",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "PopCount32",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "PopCount64",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "RotateLeft64",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "RotateLeft32",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "RotateLeft16",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "RotateLeft8",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "Sqrt",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "Sqrt32",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "Floor",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "Ceil",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "Trunc",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "Round",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "RoundToEven",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "Abs",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "Copysign",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "Min64",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "Max64",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "Min64u",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "Max64u",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "Min64F",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "Min32F",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "Max64F",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "Max32F",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "FMA",
 +              argLen:  3,
 +              generic: true,
 +      },
 +      {
 +              name:      "Phi",
 +              argLen:    -1,
 +              zeroWidth: true,
 +              generic:   true,
 +      },
 +      {
 +              name:    "Copy",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:         "Convert",
 +              argLen:       2,
 +              resultInArg0: true,
 +              zeroWidth:    true,
 +              generic:      true,
 +      },
 +      {
 +              name:    "ConstBool",
 +              auxType: auxBool,
 +              argLen:  0,
 +              generic: true,
 +      },
 +      {
 +              name:    "ConstString",
 +              auxType: auxString,
 +              argLen:  0,
 +              generic: true,
 +      },
 +      {
 +              name:    "ConstNil",
 +              argLen:  0,
 +              generic: true,
 +      },
 +      {
 +              name:    "Const8",
 +              auxType: auxInt8,
 +              argLen:  0,
 +              generic: true,
 +      },
 +      {
 +              name:    "Const16",
 +              auxType: auxInt16,
 +              argLen:  0,
 +              generic: true,
 +      },
 +      {
 +              name:    "Const32",
 +              auxType: auxInt32,
 +              argLen:  0,
 +              generic: true,
 +      },
 +      {
 +              name:    "Const64",
 +              auxType: auxInt64,
 +              argLen:  0,
 +              generic: true,
 +      },
 +      {
 +              name:    "Const32F",
 +              auxType: auxFloat32,
 +              argLen:  0,
 +              generic: true,
 +      },
 +      {
 +              name:    "Const64F",
 +              auxType: auxFloat64,
 +              argLen:  0,
 +              generic: true,
 +      },
 +      {
 +              name:    "ConstInterface",
 +              argLen:  0,
 +              generic: true,
 +      },
 +      {
 +              name:    "ConstSlice",
 +              argLen:  0,
 +              generic: true,
 +      },
 +      {
 +              name:      "InitMem",
 +              argLen:    0,
 +              zeroWidth: true,
 +              generic:   true,
 +      },
 +      {
 +              name:      "Arg",
 +              auxType:   auxSymOff,
 +              argLen:    0,
 +              zeroWidth: true,
 +              symEffect: SymRead,
 +              generic:   true,
 +      },
 +      {
 +              name:      "ArgIntReg",
 +              auxType:   auxNameOffsetInt8,
 +              argLen:    0,
 +              zeroWidth: true,
 +              generic:   true,
 +      },
 +      {
 +              name:      "ArgFloatReg",
 +              auxType:   auxNameOffsetInt8,
 +              argLen:    0,
 +              zeroWidth: true,
 +              generic:   true,
 +      },
 +      {
 +              name:      "Addr",
 +              auxType:   auxSym,
 +              argLen:    1,
 +              symEffect: SymAddr,
 +              generic:   true,
 +      },
 +      {
 +              name:      "LocalAddr",
 +              auxType:   auxSym,
 +              argLen:    2,
 +              symEffect: SymAddr,
 +              generic:   true,
 +      },
 +      {
 +              name:      "SP",
 +              argLen:    0,
 +              zeroWidth: true,
 +              fixedReg:  true,
 +              generic:   true,
 +      },
 +      {
 +              name:      "SB",
 +              argLen:    0,
 +              zeroWidth: true,
 +              fixedReg:  true,
 +              generic:   true,
 +      },
 +      {
 +              name:      "SPanchored",
 +              argLen:    2,
 +              zeroWidth: true,
 +              generic:   true,
 +      },
 +      {
 +              name:    "Load",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "Dereference",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "Store",
 +              auxType: auxTyp,
 +              argLen:  3,
 +              generic: true,
 +      },
 +      {
 +              name:    "LoadMasked8",
 +              argLen:  3,
 +              generic: true,
 +      },
 +      {
 +              name:    "LoadMasked16",
 +              argLen:  3,
 +              generic: true,
 +      },
 +      {
 +              name:    "LoadMasked32",
 +              argLen:  3,
 +              generic: true,
 +      },
 +      {
 +              name:    "LoadMasked64",
 +              argLen:  3,
 +              generic: true,
 +      },
 +      {
 +              name:    "StoreMasked8",
 +              auxType: auxTyp,
 +              argLen:  4,
 +              generic: true,
 +      },
 +      {
 +              name:    "StoreMasked16",
 +              auxType: auxTyp,
 +              argLen:  4,
 +              generic: true,
 +      },
 +      {
 +              name:    "StoreMasked32",
 +              auxType: auxTyp,
 +              argLen:  4,
 +              generic: true,
 +      },
 +      {
 +              name:    "StoreMasked64",
 +              auxType: auxTyp,
 +              argLen:  4,
 +              generic: true,
 +      },
 +      {
 +              name:    "Move",
 +              auxType: auxTypSize,
 +              argLen:  3,
 +              generic: true,
 +      },
 +      {
 +              name:    "Zero",
 +              auxType: auxTypSize,
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "StoreWB",
 +              auxType: auxTyp,
 +              argLen:  3,
 +              generic: true,
 +      },
 +      {
 +              name:    "MoveWB",
 +              auxType: auxTypSize,
 +              argLen:  3,
 +              generic: true,
 +      },
 +      {
 +              name:    "ZeroWB",
 +              auxType: auxTypSize,
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "WBend",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "WB",
 +              auxType: auxInt64,
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:      "HasCPUFeature",
 +              auxType:   auxSym,
 +              argLen:    0,
 +              symEffect: SymNone,
 +              generic:   true,
 +      },
 +      {
 +              name:    "PanicBounds",
 +              auxType: auxInt64,
 +              argLen:  3,
 +              call:    true,
 +              generic: true,
 +      },
 +      {
 +              name:    "PanicExtend",
 +              auxType: auxInt64,
 +              argLen:  4,
 +              call:    true,
 +              generic: true,
 +      },
 +      {
 +              name:    "ClosureCall",
 +              auxType: auxCallOff,
 +              argLen:  -1,
 +              call:    true,
 +              generic: true,
 +      },
 +      {
 +              name:    "StaticCall",
 +              auxType: auxCallOff,
 +              argLen:  -1,
 +              call:    true,
 +              generic: true,
 +      },
 +      {
 +              name:    "InterCall",
 +              auxType: auxCallOff,
 +              argLen:  -1,
 +              call:    true,
 +              generic: true,
 +      },
 +      {
 +              name:    "TailCall",
 +              auxType: auxCallOff,
 +              argLen:  -1,
 +              call:    true,
 +              generic: true,
 +      },
 +      {
 +              name:    "ClosureLECall",
 +              auxType: auxCallOff,
 +              argLen:  -1,
 +              call:    true,
 +              generic: true,
 +      },
 +      {
 +              name:    "StaticLECall",
 +              auxType: auxCallOff,
 +              argLen:  -1,
 +              call:    true,
 +              generic: true,
 +      },
 +      {
 +              name:    "InterLECall",
 +              auxType: auxCallOff,
 +              argLen:  -1,
 +              call:    true,
 +              generic: true,
 +      },
 +      {
 +              name:    "TailLECall",
 +              auxType: auxCallOff,
 +              argLen:  -1,
 +              call:    true,
 +              generic: true,
 +      },
 +      {
 +              name:    "SignExt8to16",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "SignExt8to32",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "SignExt8to64",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "SignExt16to32",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "SignExt16to64",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "SignExt32to64",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "ZeroExt8to16",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "ZeroExt8to32",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "ZeroExt8to64",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "ZeroExt16to32",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "ZeroExt16to64",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "ZeroExt32to64",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "Trunc16to8",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "Trunc32to8",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "Trunc32to16",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "Trunc64to8",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "Trunc64to16",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "Trunc64to32",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "Cvt32to32F",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "Cvt32to64F",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "Cvt64to32F",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "Cvt64to64F",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "Cvt32Fto32",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "Cvt32Fto64",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "Cvt64Fto32",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "Cvt64Fto64",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "Cvt32Fto64F",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "Cvt64Fto32F",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "CvtBoolToUint8",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "Round32F",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "Round64F",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "IsNonNil",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "IsInBounds",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "IsSliceInBounds",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:     "NilCheck",
 +              argLen:   2,
 +              nilCheck: true,
 +              generic:  true,
 +      },
 +      {
 +              name:      "GetG",
 +              argLen:    1,
 +              zeroWidth: true,
 +              generic:   true,
 +      },
 +      {
 +              name:    "GetClosurePtr",
 +              argLen:  0,
 +              generic: true,
 +      },
 +      {
 +              name:    "GetCallerPC",
 +              argLen:  0,
 +              generic: true,
 +      },
 +      {
 +              name:    "GetCallerSP",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "PtrIndex",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "OffPtr",
 +              auxType: auxInt64,
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "SliceMake",
 +              argLen:  3,
 +              generic: true,
 +      },
 +      {
 +              name:    "SlicePtr",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "SliceLen",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "SliceCap",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "SlicePtrUnchecked",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "ComplexMake",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "ComplexReal",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "ComplexImag",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "StringMake",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "StringPtr",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "StringLen",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "IMake",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "ITab",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "IData",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "StructMake",
 +              argLen:  -1,
 +              generic: true,
 +      },
 +      {
 +              name:    "StructSelect",
 +              auxType: auxInt64,
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "ArrayMake0",
 +              argLen:  0,
 +              generic: true,
 +      },
 +      {
 +              name:    "ArrayMake1",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "ArraySelect",
 +              auxType: auxInt64,
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "StoreReg",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "LoadReg",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:      "FwdRef",
 +              auxType:   auxSym,
 +              argLen:    0,
 +              symEffect: SymNone,
 +              generic:   true,
 +      },
 +      {
 +              name:    "Unknown",
 +              argLen:  0,
 +              generic: true,
 +      },
 +      {
 +              name:      "VarDef",
 +              auxType:   auxSym,
 +              argLen:    1,
 +              zeroWidth: true,
 +              symEffect: SymNone,
 +              generic:   true,
 +      },
 +      {
 +              name:      "VarLive",
 +              auxType:   auxSym,
 +              argLen:    1,
 +              zeroWidth: true,
 +              symEffect: SymRead,
 +              generic:   true,
 +      },
 +      {
 +              name:      "KeepAlive",
 +              argLen:    2,
 +              zeroWidth: true,
 +              generic:   true,
 +      },
 +      {
 +              name:    "InlMark",
 +              auxType: auxInt32,
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "Int64Make",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "Int64Hi",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "Int64Lo",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:        "Add32carry",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "Add32withcarry",
 +              argLen:      3,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "Add32carrywithcarry",
 +              argLen:      3,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:    "Sub32carry",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "Sub32withcarry",
 +              argLen:  3,
 +              generic: true,
 +      },
 +      {
 +              name:        "Add64carry",
 +              argLen:      3,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:    "Sub64borrow",
 +              argLen:  3,
 +              generic: true,
 +      },
 +      {
 +              name:    "Signmask",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "Zeromask",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "Slicemask",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "SpectreIndex",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "SpectreSliceIndex",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "Cvt32Uto32F",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "Cvt32Uto64F",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "Cvt32Fto32U",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "Cvt64Fto32U",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "Cvt64Uto32F",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "Cvt64Uto64F",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "Cvt32Fto64U",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "Cvt64Fto64U",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:      "Select0",
 +              argLen:    1,
 +              zeroWidth: true,
 +              generic:   true,
 +      },
 +      {
 +              name:      "Select1",
 +              argLen:    1,
 +              zeroWidth: true,
 +              generic:   true,
 +      },
 +      {
 +              name:    "MakeTuple",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "SelectN",
 +              auxType: auxInt64,
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "SelectNAddr",
 +              auxType: auxInt64,
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "MakeResult",
 +              argLen:  -1,
 +              generic: true,
 +      },
 +      {
 +              name:    "AtomicLoad8",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "AtomicLoad32",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "AtomicLoad64",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "AtomicLoadPtr",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "AtomicLoadAcq32",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "AtomicLoadAcq64",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:           "AtomicStore8",
 +              argLen:         3,
 +              hasSideEffects: true,
 +              generic:        true,
 +      },
 +      {
 +              name:           "AtomicStore32",
 +              argLen:         3,
 +              hasSideEffects: true,
 +              generic:        true,
 +      },
 +      {
 +              name:           "AtomicStore64",
 +              argLen:         3,
 +              hasSideEffects: true,
 +              generic:        true,
 +      },
 +      {
 +              name:           "AtomicStorePtrNoWB",
 +              argLen:         3,
 +              hasSideEffects: true,
 +              generic:        true,
 +      },
 +      {
 +              name:           "AtomicStoreRel32",
 +              argLen:         3,
 +              hasSideEffects: true,
 +              generic:        true,
 +      },
 +      {
 +              name:           "AtomicStoreRel64",
 +              argLen:         3,
 +              hasSideEffects: true,
 +              generic:        true,
 +      },
 +      {
 +              name:           "AtomicExchange8",
 +              argLen:         3,
 +              hasSideEffects: true,
 +              generic:        true,
 +      },
 +      {
 +              name:           "AtomicExchange32",
 +              argLen:         3,
 +              hasSideEffects: true,
 +              generic:        true,
 +      },
 +      {
 +              name:           "AtomicExchange64",
 +              argLen:         3,
 +              hasSideEffects: true,
 +              generic:        true,
 +      },
 +      {
 +              name:           "AtomicAdd32",
 +              argLen:         3,
 +              hasSideEffects: true,
 +              generic:        true,
 +      },
 +      {
 +              name:           "AtomicAdd64",
 +              argLen:         3,
 +              hasSideEffects: true,
 +              generic:        true,
 +      },
 +      {
 +              name:           "AtomicCompareAndSwap32",
 +              argLen:         4,
 +              hasSideEffects: true,
 +              generic:        true,
 +      },
 +      {
 +              name:           "AtomicCompareAndSwap64",
 +              argLen:         4,
 +              hasSideEffects: true,
 +              generic:        true,
 +      },
 +      {
 +              name:           "AtomicCompareAndSwapRel32",
 +              argLen:         4,
 +              hasSideEffects: true,
 +              generic:        true,
 +      },
 +      {
 +              name:           "AtomicAnd8",
 +              argLen:         3,
 +              hasSideEffects: true,
 +              generic:        true,
 +      },
 +      {
 +              name:           "AtomicOr8",
 +              argLen:         3,
 +              hasSideEffects: true,
 +              generic:        true,
 +      },
 +      {
 +              name:           "AtomicAnd32",
 +              argLen:         3,
 +              hasSideEffects: true,
 +              generic:        true,
 +      },
 +      {
 +              name:           "AtomicOr32",
 +              argLen:         3,
 +              hasSideEffects: true,
 +              generic:        true,
 +      },
 +      {
 +              name:           "AtomicAnd64value",
 +              argLen:         3,
 +              hasSideEffects: true,
 +              generic:        true,
 +      },
 +      {
 +              name:           "AtomicAnd32value",
 +              argLen:         3,
 +              hasSideEffects: true,
 +              generic:        true,
 +      },
 +      {
 +              name:           "AtomicAnd8value",
 +              argLen:         3,
 +              hasSideEffects: true,
 +              generic:        true,
 +      },
 +      {
 +              name:           "AtomicOr64value",
 +              argLen:         3,
 +              hasSideEffects: true,
 +              generic:        true,
 +      },
 +      {
 +              name:           "AtomicOr32value",
 +              argLen:         3,
 +              hasSideEffects: true,
 +              generic:        true,
 +      },
 +      {
 +              name:           "AtomicOr8value",
 +              argLen:         3,
 +              hasSideEffects: true,
 +              generic:        true,
 +      },
 +      {
 +              name:           "AtomicStore8Variant",
 +              argLen:         3,
 +              hasSideEffects: true,
 +              generic:        true,
 +      },
 +      {
 +              name:           "AtomicStore32Variant",
 +              argLen:         3,
 +              hasSideEffects: true,
 +              generic:        true,
 +      },
 +      {
 +              name:           "AtomicStore64Variant",
 +              argLen:         3,
 +              hasSideEffects: true,
 +              generic:        true,
 +      },
 +      {
 +              name:           "AtomicAdd32Variant",
 +              argLen:         3,
 +              hasSideEffects: true,
 +              generic:        true,
 +      },
 +      {
 +              name:           "AtomicAdd64Variant",
 +              argLen:         3,
 +              hasSideEffects: true,
 +              generic:        true,
 +      },
 +      {
 +              name:           "AtomicExchange8Variant",
 +              argLen:         3,
 +              hasSideEffects: true,
 +              generic:        true,
 +      },
 +      {
 +              name:           "AtomicExchange32Variant",
 +              argLen:         3,
 +              hasSideEffects: true,
 +              generic:        true,
 +      },
 +      {
 +              name:           "AtomicExchange64Variant",
 +              argLen:         3,
 +              hasSideEffects: true,
 +              generic:        true,
 +      },
 +      {
 +              name:           "AtomicCompareAndSwap32Variant",
 +              argLen:         4,
 +              hasSideEffects: true,
 +              generic:        true,
 +      },
 +      {
 +              name:           "AtomicCompareAndSwap64Variant",
 +              argLen:         4,
 +              hasSideEffects: true,
 +              generic:        true,
 +      },
 +      {
 +              name:           "AtomicAnd64valueVariant",
 +              argLen:         3,
 +              hasSideEffects: true,
 +              generic:        true,
 +      },
 +      {
 +              name:           "AtomicOr64valueVariant",
 +              argLen:         3,
 +              hasSideEffects: true,
 +              generic:        true,
 +      },
 +      {
 +              name:           "AtomicAnd32valueVariant",
 +              argLen:         3,
 +              hasSideEffects: true,
 +              generic:        true,
 +      },
 +      {
 +              name:           "AtomicOr32valueVariant",
 +              argLen:         3,
 +              hasSideEffects: true,
 +              generic:        true,
 +      },
 +      {
 +              name:           "AtomicAnd8valueVariant",
 +              argLen:         3,
 +              hasSideEffects: true,
 +              generic:        true,
 +      },
 +      {
 +              name:           "AtomicOr8valueVariant",
 +              argLen:         3,
 +              hasSideEffects: true,
 +              generic:        true,
 +      },
 +      {
 +              name:           "PubBarrier",
 +              argLen:         1,
 +              hasSideEffects: true,
 +              generic:        true,
 +      },
 +      {
 +              name:      "Clobber",
 +              auxType:   auxSymOff,
 +              argLen:    0,
 +              symEffect: SymNone,
 +              generic:   true,
 +      },
 +      {
 +              name:    "ClobberReg",
 +              argLen:  0,
 +              generic: true,
 +      },
 +      {
 +              name:           "PrefetchCache",
 +              argLen:         2,
 +              hasSideEffects: true,
 +              generic:        true,
 +      },
 +      {
 +              name:           "PrefetchCacheStreamed",
 +              argLen:         2,
 +              hasSideEffects: true,
 +              generic:        true,
 +      },
 +      {
 +              name:    "ZeroSIMD",
 +              argLen:  0,
 +              generic: true,
 +      },
 +      {
 +              name:    "Cvt16toMask8x16",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "Cvt32toMask8x32",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "Cvt64toMask8x64",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "Cvt8toMask16x8",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "Cvt16toMask16x16",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "Cvt32toMask16x32",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "Cvt8toMask32x4",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "Cvt8toMask32x8",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "Cvt16toMask32x16",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "Cvt8toMask64x2",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "Cvt8toMask64x4",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "Cvt8toMask64x8",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "CvtMask8x16to16",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "CvtMask8x32to32",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "CvtMask8x64to64",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "CvtMask16x8to8",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "CvtMask16x16to16",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "CvtMask16x32to32",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "CvtMask32x4to8",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "CvtMask32x8to8",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "CvtMask32x16to16",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "CvtMask64x2to8",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "CvtMask64x4to8",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "CvtMask64x8to8",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "IsZeroVec",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "AESDecryptLastRoundUint8x16",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "AESDecryptLastRoundUint8x32",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "AESDecryptLastRoundUint8x64",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "AESDecryptOneRoundUint8x16",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "AESDecryptOneRoundUint8x32",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "AESDecryptOneRoundUint8x64",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "AESEncryptLastRoundUint8x16",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "AESEncryptLastRoundUint8x32",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "AESEncryptLastRoundUint8x64",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "AESEncryptOneRoundUint8x16",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "AESEncryptOneRoundUint8x32",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "AESEncryptOneRoundUint8x64",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "AESInvMixColumnsUint32x4",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "AbsInt8x16",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "AbsInt8x32",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "AbsInt8x64",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "AbsInt16x8",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "AbsInt16x16",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "AbsInt16x32",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "AbsInt32x4",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "AbsInt32x8",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "AbsInt32x16",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "AbsInt64x2",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "AbsInt64x4",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "AbsInt64x8",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:        "AddFloat32x4",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "AddFloat32x8",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "AddFloat32x16",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "AddFloat64x2",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "AddFloat64x4",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "AddFloat64x8",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "AddInt8x16",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "AddInt8x32",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "AddInt8x64",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "AddInt16x8",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "AddInt16x16",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "AddInt16x32",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "AddInt32x4",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "AddInt32x8",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "AddInt32x16",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "AddInt64x2",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "AddInt64x4",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "AddInt64x8",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:    "AddPairsFloat32x4",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "AddPairsFloat32x8",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "AddPairsFloat64x2",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "AddPairsFloat64x4",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "AddPairsInt16x8",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "AddPairsInt16x16",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "AddPairsInt32x4",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "AddPairsInt32x8",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "AddPairsSaturatedInt16x8",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "AddPairsSaturatedInt16x16",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "AddPairsUint16x8",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "AddPairsUint16x16",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "AddPairsUint32x4",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "AddPairsUint32x8",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:        "AddSaturatedInt8x16",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "AddSaturatedInt8x32",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "AddSaturatedInt8x64",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "AddSaturatedInt16x8",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "AddSaturatedInt16x16",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "AddSaturatedInt16x32",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "AddSaturatedUint8x16",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "AddSaturatedUint8x32",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "AddSaturatedUint8x64",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "AddSaturatedUint16x8",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "AddSaturatedUint16x16",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "AddSaturatedUint16x32",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:    "AddSubFloat32x4",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "AddSubFloat32x8",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "AddSubFloat64x2",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "AddSubFloat64x4",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:        "AddUint8x16",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "AddUint8x32",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "AddUint8x64",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "AddUint16x8",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "AddUint16x16",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "AddUint16x32",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "AddUint32x4",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "AddUint32x8",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "AddUint32x16",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "AddUint64x2",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "AddUint64x4",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "AddUint64x8",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "AndInt8x16",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "AndInt8x32",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "AndInt8x64",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "AndInt16x8",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "AndInt16x16",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "AndInt16x32",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "AndInt32x4",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "AndInt32x8",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "AndInt32x16",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "AndInt64x2",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "AndInt64x4",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "AndInt64x8",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:    "AndNotInt8x16",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "AndNotInt8x32",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "AndNotInt8x64",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "AndNotInt16x8",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "AndNotInt16x16",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "AndNotInt16x32",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "AndNotInt32x4",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "AndNotInt32x8",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "AndNotInt32x16",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "AndNotInt64x2",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "AndNotInt64x4",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "AndNotInt64x8",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "AndNotUint8x16",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "AndNotUint8x32",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "AndNotUint8x64",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "AndNotUint16x8",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "AndNotUint16x16",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "AndNotUint16x32",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "AndNotUint32x4",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "AndNotUint32x8",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "AndNotUint32x16",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "AndNotUint64x2",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "AndNotUint64x4",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "AndNotUint64x8",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:        "AndUint8x16",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "AndUint8x32",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "AndUint8x64",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "AndUint16x8",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "AndUint16x16",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "AndUint16x32",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "AndUint32x4",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "AndUint32x8",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "AndUint32x16",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "AndUint64x2",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "AndUint64x4",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "AndUint64x8",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "AverageUint8x16",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "AverageUint8x32",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "AverageUint8x64",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "AverageUint16x8",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "AverageUint16x16",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "AverageUint16x32",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:    "Broadcast128Float32x4",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "Broadcast128Float64x2",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "Broadcast128Int8x16",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "Broadcast128Int16x8",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "Broadcast128Int32x4",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "Broadcast128Int64x2",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "Broadcast128Uint8x16",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "Broadcast128Uint16x8",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "Broadcast128Uint32x4",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "Broadcast128Uint64x2",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "Broadcast256Float32x4",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "Broadcast256Float64x2",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "Broadcast256Int8x16",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "Broadcast256Int16x8",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "Broadcast256Int32x4",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "Broadcast256Int64x2",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "Broadcast256Uint8x16",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "Broadcast256Uint16x8",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "Broadcast256Uint32x4",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "Broadcast256Uint64x2",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "Broadcast512Float32x4",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "Broadcast512Float64x2",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "Broadcast512Int8x16",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "Broadcast512Int16x8",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "Broadcast512Int32x4",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "Broadcast512Int64x2",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "Broadcast512Uint8x16",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "Broadcast512Uint16x8",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "Broadcast512Uint32x4",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "Broadcast512Uint64x2",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "CeilFloat32x4",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "CeilFloat32x8",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "CeilFloat64x2",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "CeilFloat64x4",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "CompressFloat32x4",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "CompressFloat32x8",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "CompressFloat32x16",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "CompressFloat64x2",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "CompressFloat64x4",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "CompressFloat64x8",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "CompressInt8x16",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "CompressInt8x32",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "CompressInt8x64",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "CompressInt16x8",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "CompressInt16x16",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "CompressInt16x32",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "CompressInt32x4",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "CompressInt32x8",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "CompressInt32x16",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "CompressInt64x2",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "CompressInt64x4",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "CompressInt64x8",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "CompressUint8x16",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "CompressUint8x32",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "CompressUint8x64",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "CompressUint16x8",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "CompressUint16x16",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "CompressUint16x32",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "CompressUint32x4",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "CompressUint32x8",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "CompressUint32x16",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "CompressUint64x2",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "CompressUint64x4",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "CompressUint64x8",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "ConvertToInt8Int16x8",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "ConvertToInt8Int16x16",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "ConvertToInt8Int16x32",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "ConvertToInt8Int32x4",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "ConvertToInt8Int32x8",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "ConvertToInt8Int32x16",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "ConvertToInt8Int64x2",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "ConvertToInt8Int64x4",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "ConvertToInt8Int64x8",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "ConvertToInt8SaturatedInt16x8",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "ConvertToInt8SaturatedInt16x16",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "ConvertToInt8SaturatedInt16x32",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "ConvertToInt8SaturatedInt32x4",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "ConvertToInt8SaturatedInt32x8",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "ConvertToInt8SaturatedInt32x16",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "ConvertToInt8SaturatedInt64x2",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "ConvertToInt8SaturatedInt64x4",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "ConvertToInt8SaturatedInt64x8",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "ConvertToInt16Int8x16",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "ConvertToInt16Int8x32",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "ConvertToInt16Int32x4",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "ConvertToInt16Int32x8",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "ConvertToInt16Int32x16",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "ConvertToInt16Int64x2",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "ConvertToInt16Int64x4",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "ConvertToInt16Int64x8",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "ConvertToInt16SaturatedInt32x4",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "ConvertToInt16SaturatedInt32x8",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "ConvertToInt16SaturatedInt32x16",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "ConvertToInt16SaturatedInt64x2",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "ConvertToInt16SaturatedInt64x4",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "ConvertToInt16SaturatedInt64x8",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "ConvertToInt16SaturatedPackedInt32x4",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "ConvertToInt16SaturatedPackedInt32x8",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "ConvertToInt16SaturatedPackedInt32x16",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "ConvertToInt16x8Int8x16",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "ConvertToInt32Float32x4",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "ConvertToInt32Float32x8",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "ConvertToInt32Float32x16",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "ConvertToInt32Int8x16",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "ConvertToInt32Int16x8",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "ConvertToInt32Int16x16",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "ConvertToInt32Int64x2",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "ConvertToInt32Int64x4",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "ConvertToInt32Int64x8",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "ConvertToInt32SaturatedInt64x2",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "ConvertToInt32SaturatedInt64x4",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "ConvertToInt32SaturatedInt64x8",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "ConvertToInt32x4Int8x16",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "ConvertToInt32x4Int16x8",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "ConvertToInt32x8Int8x16",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "ConvertToInt64Int16x8",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "ConvertToInt64Int32x4",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "ConvertToInt64Int32x8",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "ConvertToInt64x2Int8x16",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "ConvertToInt64x2Int16x8",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "ConvertToInt64x2Int32x4",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "ConvertToInt64x4Int8x16",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "ConvertToInt64x8Int8x16",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "ConvertToUint8SaturatedUint16x8",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "ConvertToUint8SaturatedUint16x16",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "ConvertToUint8SaturatedUint16x32",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "ConvertToUint8SaturatedUint32x4",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "ConvertToUint8SaturatedUint32x8",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "ConvertToUint8SaturatedUint32x16",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "ConvertToUint8SaturatedUint64x2",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "ConvertToUint8SaturatedUint64x4",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "ConvertToUint8SaturatedUint64x8",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "ConvertToUint8Uint16x8",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "ConvertToUint8Uint16x16",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "ConvertToUint8Uint16x32",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "ConvertToUint8Uint32x4",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "ConvertToUint8Uint32x8",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "ConvertToUint8Uint32x16",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "ConvertToUint8Uint64x2",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "ConvertToUint8Uint64x4",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "ConvertToUint8Uint64x8",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "ConvertToUint16SaturatedPackedUint32x4",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "ConvertToUint16SaturatedPackedUint32x8",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "ConvertToUint16SaturatedPackedUint32x16",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "ConvertToUint16SaturatedUint32x4",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "ConvertToUint16SaturatedUint32x8",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "ConvertToUint16SaturatedUint32x16",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "ConvertToUint16SaturatedUint64x2",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "ConvertToUint16SaturatedUint64x4",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "ConvertToUint16SaturatedUint64x8",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "ConvertToUint16Uint8x16",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "ConvertToUint16Uint8x32",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "ConvertToUint16Uint32x4",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "ConvertToUint16Uint32x8",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "ConvertToUint16Uint32x16",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "ConvertToUint16Uint64x2",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "ConvertToUint16Uint64x4",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "ConvertToUint16Uint64x8",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "ConvertToUint16x8Uint8x16",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "ConvertToUint32Float32x4",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "ConvertToUint32Float32x8",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "ConvertToUint32Float32x16",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "ConvertToUint32SaturatedUint64x2",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "ConvertToUint32SaturatedUint64x4",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "ConvertToUint32SaturatedUint64x8",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "ConvertToUint32Uint8x16",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "ConvertToUint32Uint16x8",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "ConvertToUint32Uint16x16",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "ConvertToUint32Uint64x2",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "ConvertToUint32Uint64x4",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "ConvertToUint32Uint64x8",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "ConvertToUint32x4Uint8x16",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "ConvertToUint32x4Uint16x8",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "ConvertToUint32x8Uint8x16",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "ConvertToUint64Uint16x8",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "ConvertToUint64Uint32x4",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "ConvertToUint64Uint32x8",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "ConvertToUint64x2Uint8x16",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "ConvertToUint64x2Uint16x8",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "ConvertToUint64x2Uint32x4",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "ConvertToUint64x4Int16x8",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "ConvertToUint64x4Uint8x16",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "ConvertToUint64x4Uint16x8",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "ConvertToUint64x8Uint8x16",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "CopySignInt8x16",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "CopySignInt8x32",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "CopySignInt16x8",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "CopySignInt16x16",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "CopySignInt32x4",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "CopySignInt32x8",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "DivFloat32x4",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "DivFloat32x8",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "DivFloat32x16",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "DivFloat64x2",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "DivFloat64x4",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "DivFloat64x8",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "DotProductPairsInt16x8",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "DotProductPairsInt16x16",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "DotProductPairsInt16x32",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "DotProductPairsSaturatedUint8x16",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "DotProductPairsSaturatedUint8x32",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "DotProductPairsSaturatedUint8x64",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "DotProductQuadrupleInt32x4",
 +              argLen:  3,
 +              generic: true,
 +      },
 +      {
 +              name:    "DotProductQuadrupleInt32x8",
 +              argLen:  3,
 +              generic: true,
 +      },
 +      {
 +              name:    "DotProductQuadrupleInt32x16",
 +              argLen:  3,
 +              generic: true,
 +      },
 +      {
 +              name:    "DotProductQuadrupleSaturatedInt32x4",
 +              argLen:  3,
 +              generic: true,
 +      },
 +      {
 +              name:    "DotProductQuadrupleSaturatedInt32x8",
 +              argLen:  3,
 +              generic: true,
 +      },
 +      {
 +              name:    "DotProductQuadrupleSaturatedInt32x16",
 +              argLen:  3,
 +              generic: true,
 +      },
 +      {
 +              name:        "EqualFloat32x4",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "EqualFloat32x8",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "EqualFloat32x16",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "EqualFloat64x2",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "EqualFloat64x4",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "EqualFloat64x8",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "EqualInt8x16",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "EqualInt8x32",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "EqualInt8x64",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "EqualInt16x8",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "EqualInt16x16",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "EqualInt16x32",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "EqualInt32x4",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "EqualInt32x8",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "EqualInt32x16",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "EqualInt64x2",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "EqualInt64x4",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "EqualInt64x8",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "EqualUint8x16",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "EqualUint8x32",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "EqualUint8x64",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "EqualUint16x8",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "EqualUint16x16",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "EqualUint16x32",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "EqualUint32x4",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "EqualUint32x8",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "EqualUint32x16",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "EqualUint64x2",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "EqualUint64x4",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "EqualUint64x8",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:    "ExpandFloat32x4",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "ExpandFloat32x8",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "ExpandFloat32x16",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "ExpandFloat64x2",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "ExpandFloat64x4",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "ExpandFloat64x8",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "ExpandInt8x16",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "ExpandInt8x32",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "ExpandInt8x64",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "ExpandInt16x8",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "ExpandInt16x16",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "ExpandInt16x32",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "ExpandInt32x4",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "ExpandInt32x8",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "ExpandInt32x16",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "ExpandInt64x2",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "ExpandInt64x4",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "ExpandInt64x8",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "ExpandUint8x16",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "ExpandUint8x32",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "ExpandUint8x64",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "ExpandUint16x8",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "ExpandUint16x16",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "ExpandUint16x32",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "ExpandUint32x4",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "ExpandUint32x8",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "ExpandUint32x16",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "ExpandUint64x2",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "ExpandUint64x4",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "ExpandUint64x8",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "FloorFloat32x4",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "FloorFloat32x8",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "FloorFloat64x2",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "FloorFloat64x4",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "GaloisFieldMulUint8x16",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "GaloisFieldMulUint8x32",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "GaloisFieldMulUint8x64",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "GetHiFloat32x8",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "GetHiFloat32x16",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "GetHiFloat64x4",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "GetHiFloat64x8",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "GetHiInt8x32",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "GetHiInt8x64",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "GetHiInt16x16",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "GetHiInt16x32",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "GetHiInt32x8",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "GetHiInt32x16",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "GetHiInt64x4",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "GetHiInt64x8",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "GetHiUint8x32",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "GetHiUint8x64",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "GetHiUint16x16",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "GetHiUint16x32",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "GetHiUint32x8",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "GetHiUint32x16",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "GetHiUint64x4",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "GetHiUint64x8",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "GetLoFloat32x8",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "GetLoFloat32x16",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "GetLoFloat64x4",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "GetLoFloat64x8",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "GetLoInt8x32",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "GetLoInt8x64",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "GetLoInt16x16",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "GetLoInt16x32",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "GetLoInt32x8",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "GetLoInt32x16",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "GetLoInt64x4",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "GetLoInt64x8",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "GetLoUint8x32",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "GetLoUint8x64",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "GetLoUint16x16",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "GetLoUint16x32",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "GetLoUint32x8",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "GetLoUint32x16",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "GetLoUint64x4",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "GetLoUint64x8",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "GreaterEqualFloat32x4",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "GreaterEqualFloat32x8",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "GreaterEqualFloat32x16",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "GreaterEqualFloat64x2",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "GreaterEqualFloat64x4",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "GreaterEqualFloat64x8",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "GreaterEqualInt8x64",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "GreaterEqualInt16x32",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "GreaterEqualInt32x16",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "GreaterEqualInt64x8",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "GreaterEqualUint8x64",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "GreaterEqualUint16x32",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "GreaterEqualUint32x16",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "GreaterEqualUint64x8",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "GreaterFloat32x4",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "GreaterFloat32x8",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "GreaterFloat32x16",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "GreaterFloat64x2",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "GreaterFloat64x4",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "GreaterFloat64x8",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "GreaterInt8x16",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "GreaterInt8x32",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "GreaterInt8x64",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "GreaterInt16x8",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "GreaterInt16x16",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "GreaterInt16x32",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "GreaterInt32x4",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "GreaterInt32x8",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "GreaterInt32x16",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "GreaterInt64x2",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "GreaterInt64x4",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "GreaterInt64x8",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "GreaterUint8x64",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "GreaterUint16x32",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "GreaterUint32x16",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "GreaterUint64x8",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "InterleaveHiGroupedInt16x16",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "InterleaveHiGroupedInt16x32",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "InterleaveHiGroupedInt32x8",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "InterleaveHiGroupedInt32x16",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "InterleaveHiGroupedInt64x4",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "InterleaveHiGroupedInt64x8",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "InterleaveHiGroupedUint16x16",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "InterleaveHiGroupedUint16x32",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "InterleaveHiGroupedUint32x8",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "InterleaveHiGroupedUint32x16",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "InterleaveHiGroupedUint64x4",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "InterleaveHiGroupedUint64x8",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "InterleaveHiInt16x8",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "InterleaveHiInt32x4",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "InterleaveHiInt64x2",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "InterleaveHiUint16x8",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "InterleaveHiUint32x4",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "InterleaveHiUint64x2",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "InterleaveLoGroupedInt16x16",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "InterleaveLoGroupedInt16x32",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "InterleaveLoGroupedInt32x8",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "InterleaveLoGroupedInt32x16",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "InterleaveLoGroupedInt64x4",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "InterleaveLoGroupedInt64x8",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "InterleaveLoGroupedUint16x16",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "InterleaveLoGroupedUint16x32",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "InterleaveLoGroupedUint32x8",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "InterleaveLoGroupedUint32x16",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "InterleaveLoGroupedUint64x4",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "InterleaveLoGroupedUint64x8",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "InterleaveLoInt16x8",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "InterleaveLoInt32x4",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "InterleaveLoInt64x2",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "InterleaveLoUint16x8",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "InterleaveLoUint32x4",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "InterleaveLoUint64x2",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:        "IsNanFloat32x4",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "IsNanFloat32x8",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "IsNanFloat32x16",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "IsNanFloat64x2",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "IsNanFloat64x4",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "IsNanFloat64x8",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:    "LeadingZerosInt32x4",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "LeadingZerosInt32x8",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "LeadingZerosInt32x16",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "LeadingZerosInt64x2",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "LeadingZerosInt64x4",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "LeadingZerosInt64x8",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "LeadingZerosUint32x4",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "LeadingZerosUint32x8",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "LeadingZerosUint32x16",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "LeadingZerosUint64x2",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "LeadingZerosUint64x4",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "LeadingZerosUint64x8",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "LessEqualFloat32x4",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "LessEqualFloat32x8",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "LessEqualFloat32x16",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "LessEqualFloat64x2",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "LessEqualFloat64x4",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "LessEqualFloat64x8",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "LessEqualInt8x64",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "LessEqualInt16x32",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "LessEqualInt32x16",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "LessEqualInt64x8",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "LessEqualUint8x64",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "LessEqualUint16x32",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "LessEqualUint32x16",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "LessEqualUint64x8",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "LessFloat32x4",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "LessFloat32x8",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "LessFloat32x16",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "LessFloat64x2",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "LessFloat64x4",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "LessFloat64x8",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "LessInt8x64",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "LessInt16x32",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "LessInt32x16",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "LessInt64x8",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "LessUint8x64",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "LessUint16x32",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "LessUint32x16",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "LessUint64x8",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:        "MaxFloat32x4",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "MaxFloat32x8",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "MaxFloat32x16",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "MaxFloat64x2",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "MaxFloat64x4",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "MaxFloat64x8",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "MaxInt8x16",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "MaxInt8x32",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "MaxInt8x64",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "MaxInt16x8",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "MaxInt16x16",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "MaxInt16x32",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "MaxInt32x4",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "MaxInt32x8",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "MaxInt32x16",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "MaxInt64x2",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "MaxInt64x4",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "MaxInt64x8",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "MaxUint8x16",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "MaxUint8x32",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "MaxUint8x64",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "MaxUint16x8",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "MaxUint16x16",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "MaxUint16x32",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "MaxUint32x4",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "MaxUint32x8",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "MaxUint32x16",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "MaxUint64x2",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "MaxUint64x4",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "MaxUint64x8",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "MinFloat32x4",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "MinFloat32x8",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "MinFloat32x16",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "MinFloat64x2",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "MinFloat64x4",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "MinFloat64x8",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "MinInt8x16",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "MinInt8x32",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "MinInt8x64",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "MinInt16x8",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "MinInt16x16",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "MinInt16x32",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "MinInt32x4",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "MinInt32x8",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "MinInt32x16",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "MinInt64x2",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "MinInt64x4",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "MinInt64x8",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "MinUint8x16",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "MinUint8x32",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "MinUint8x64",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "MinUint16x8",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "MinUint16x16",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "MinUint16x32",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "MinUint32x4",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "MinUint32x8",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "MinUint32x16",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "MinUint64x2",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "MinUint64x4",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "MinUint64x8",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:    "MulAddFloat32x4",
 +              argLen:  3,
 +              generic: true,
 +      },
 +      {
 +              name:    "MulAddFloat32x8",
 +              argLen:  3,
 +              generic: true,
 +      },
 +      {
 +              name:    "MulAddFloat32x16",
 +              argLen:  3,
 +              generic: true,
 +      },
 +      {
 +              name:    "MulAddFloat64x2",
 +              argLen:  3,
 +              generic: true,
 +      },
 +      {
 +              name:    "MulAddFloat64x4",
 +              argLen:  3,
 +              generic: true,
 +      },
 +      {
 +              name:    "MulAddFloat64x8",
 +              argLen:  3,
 +              generic: true,
 +      },
 +      {
 +              name:    "MulAddSubFloat32x4",
 +              argLen:  3,
 +              generic: true,
 +      },
 +      {
 +              name:    "MulAddSubFloat32x8",
 +              argLen:  3,
 +              generic: true,
 +      },
 +      {
 +              name:    "MulAddSubFloat32x16",
 +              argLen:  3,
 +              generic: true,
 +      },
 +      {
 +              name:    "MulAddSubFloat64x2",
 +              argLen:  3,
 +              generic: true,
 +      },
 +      {
 +              name:    "MulAddSubFloat64x4",
 +              argLen:  3,
 +              generic: true,
 +      },
 +      {
 +              name:    "MulAddSubFloat64x8",
 +              argLen:  3,
 +              generic: true,
 +      },
 +      {
 +              name:        "MulEvenWidenInt32x4",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "MulEvenWidenInt32x8",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "MulEvenWidenUint32x4",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "MulEvenWidenUint32x8",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "MulFloat32x4",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "MulFloat32x8",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "MulFloat32x16",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "MulFloat64x2",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "MulFloat64x4",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "MulFloat64x8",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "MulHighInt16x8",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "MulHighInt16x16",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "MulHighInt16x32",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "MulHighUint16x8",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "MulHighUint16x16",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "MulHighUint16x32",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "MulInt16x8",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "MulInt16x16",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "MulInt16x32",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "MulInt32x4",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "MulInt32x8",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "MulInt32x16",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "MulInt64x2",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "MulInt64x4",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "MulInt64x8",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:    "MulSubAddFloat32x4",
 +              argLen:  3,
 +              generic: true,
 +      },
 +      {
 +              name:    "MulSubAddFloat32x8",
 +              argLen:  3,
 +              generic: true,
 +      },
 +      {
 +              name:    "MulSubAddFloat32x16",
 +              argLen:  3,
 +              generic: true,
 +      },
 +      {
 +              name:    "MulSubAddFloat64x2",
 +              argLen:  3,
 +              generic: true,
 +      },
 +      {
 +              name:    "MulSubAddFloat64x4",
 +              argLen:  3,
 +              generic: true,
 +      },
 +      {
 +              name:    "MulSubAddFloat64x8",
 +              argLen:  3,
 +              generic: true,
 +      },
 +      {
 +              name:        "MulUint16x8",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "MulUint16x16",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "MulUint16x32",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "MulUint32x4",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "MulUint32x8",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "MulUint32x16",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "MulUint64x2",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "MulUint64x4",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "MulUint64x8",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "NotEqualFloat32x4",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "NotEqualFloat32x8",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "NotEqualFloat32x16",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "NotEqualFloat64x2",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "NotEqualFloat64x4",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "NotEqualFloat64x8",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "NotEqualInt8x64",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "NotEqualInt16x32",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "NotEqualInt32x16",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "NotEqualInt64x8",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "NotEqualUint8x64",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "NotEqualUint16x32",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "NotEqualUint32x16",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "NotEqualUint64x8",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:    "OnesCountInt8x16",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "OnesCountInt8x32",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "OnesCountInt8x64",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "OnesCountInt16x8",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "OnesCountInt16x16",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "OnesCountInt16x32",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "OnesCountInt32x4",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "OnesCountInt32x8",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "OnesCountInt32x16",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "OnesCountInt64x2",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "OnesCountInt64x4",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "OnesCountInt64x8",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "OnesCountUint8x16",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "OnesCountUint8x32",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "OnesCountUint8x64",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "OnesCountUint16x8",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "OnesCountUint16x16",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "OnesCountUint16x32",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "OnesCountUint32x4",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "OnesCountUint32x8",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "OnesCountUint32x16",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "OnesCountUint64x2",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "OnesCountUint64x4",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "OnesCountUint64x8",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:        "OrInt8x16",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "OrInt8x32",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "OrInt8x64",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "OrInt16x8",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "OrInt16x16",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "OrInt16x32",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "OrInt32x4",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "OrInt32x8",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "OrInt32x16",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "OrInt64x2",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "OrInt64x4",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "OrInt64x8",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "OrUint8x16",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "OrUint8x32",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "OrUint8x64",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "OrUint16x8",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "OrUint16x16",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "OrUint16x32",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "OrUint32x4",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "OrUint32x8",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "OrUint32x16",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "OrUint64x2",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "OrUint64x4",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:        "OrUint64x8",
 +              argLen:      2,
 +              commutative: true,
 +              generic:     true,
 +      },
 +      {
 +              name:    "Permute2Float32x4",
 +              argLen:  3,
 +              generic: true,
 +      },
 +      {
 +              name:    "Permute2Float32x8",
 +              argLen:  3,
 +              generic: true,
 +      },
 +      {
 +              name:    "Permute2Float32x16",
 +              argLen:  3,
 +              generic: true,
 +      },
 +      {
 +              name:    "Permute2Float64x2",
 +              argLen:  3,
 +              generic: true,
 +      },
 +      {
 +              name:    "Permute2Float64x4",
 +              argLen:  3,
 +              generic: true,
 +      },
 +      {
 +              name:    "Permute2Float64x8",
 +              argLen:  3,
 +              generic: true,
 +      },
 +      {
 +              name:    "Permute2Int8x16",
 +              argLen:  3,
 +              generic: true,
 +      },
 +      {
 +              name:    "Permute2Int8x32",
 +              argLen:  3,
 +              generic: true,
 +      },
 +      {
 +              name:    "Permute2Int8x64",
 +              argLen:  3,
 +              generic: true,
 +      },
 +      {
 +              name:    "Permute2Int16x8",
 +              argLen:  3,
 +              generic: true,
 +      },
 +      {
 +              name:    "Permute2Int16x16",
 +              argLen:  3,
 +              generic: true,
 +      },
 +      {
 +              name:    "Permute2Int16x32",
 +              argLen:  3,
 +              generic: true,
 +      },
 +      {
 +              name:    "Permute2Int32x4",
 +              argLen:  3,
 +              generic: true,
 +      },
 +      {
 +              name:    "Permute2Int32x8",
 +              argLen:  3,
 +              generic: true,
 +      },
 +      {
 +              name:    "Permute2Int32x16",
 +              argLen:  3,
 +              generic: true,
 +      },
 +      {
 +              name:    "Permute2Int64x2",
 +              argLen:  3,
 +              generic: true,
 +      },
 +      {
 +              name:    "Permute2Int64x4",
 +              argLen:  3,
 +              generic: true,
 +      },
 +      {
 +              name:    "Permute2Int64x8",
 +              argLen:  3,
 +              generic: true,
 +      },
 +      {
 +              name:    "Permute2Uint8x16",
 +              argLen:  3,
 +              generic: true,
 +      },
 +      {
 +              name:    "Permute2Uint8x32",
 +              argLen:  3,
 +              generic: true,
 +      },
 +      {
 +              name:    "Permute2Uint8x64",
 +              argLen:  3,
 +              generic: true,
 +      },
 +      {
 +              name:    "Permute2Uint16x8",
 +              argLen:  3,
 +              generic: true,
 +      },
 +      {
 +              name:    "Permute2Uint16x16",
 +              argLen:  3,
 +              generic: true,
 +      },
 +      {
 +              name:    "Permute2Uint16x32",
 +              argLen:  3,
 +              generic: true,
 +      },
 +      {
 +              name:    "Permute2Uint32x4",
 +              argLen:  3,
 +              generic: true,
 +      },
 +      {
 +              name:    "Permute2Uint32x8",
 +              argLen:  3,
 +              generic: true,
 +      },
 +      {
 +              name:    "Permute2Uint32x16",
 +              argLen:  3,
 +              generic: true,
 +      },
 +      {
 +              name:    "Permute2Uint64x2",
 +              argLen:  3,
 +              generic: true,
 +      },
 +      {
 +              name:    "Permute2Uint64x4",
 +              argLen:  3,
 +              generic: true,
 +      },
 +      {
 +              name:    "Permute2Uint64x8",
 +              argLen:  3,
 +              generic: true,
 +      },
 +      {
 +              name:    "PermuteFloat32x8",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "PermuteFloat32x16",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "PermuteFloat64x4",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "PermuteFloat64x8",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "PermuteGroupedInt8x32",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "PermuteGroupedInt8x64",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "PermuteGroupedUint8x32",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "PermuteGroupedUint8x64",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "PermuteInt8x16",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "PermuteInt8x32",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "PermuteInt8x64",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "PermuteInt16x8",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "PermuteInt16x16",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "PermuteInt16x32",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "PermuteInt32x8",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "PermuteInt32x16",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "PermuteInt64x4",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "PermuteInt64x8",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "PermuteUint8x16",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "PermuteUint8x32",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "PermuteUint8x64",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "PermuteUint16x8",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "PermuteUint16x16",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "PermuteUint16x32",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "PermuteUint32x8",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "PermuteUint32x16",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "PermuteUint64x4",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "PermuteUint64x8",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "ReciprocalFloat32x4",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "ReciprocalFloat32x8",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "ReciprocalFloat32x16",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "ReciprocalFloat64x2",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "ReciprocalFloat64x4",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "ReciprocalFloat64x8",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "ReciprocalSqrtFloat32x4",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "ReciprocalSqrtFloat32x8",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "ReciprocalSqrtFloat32x16",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "ReciprocalSqrtFloat64x2",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "ReciprocalSqrtFloat64x4",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "ReciprocalSqrtFloat64x8",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "RotateLeftInt32x4",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "RotateLeftInt32x8",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "RotateLeftInt32x16",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "RotateLeftInt64x2",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "RotateLeftInt64x4",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "RotateLeftInt64x8",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "RotateLeftUint32x4",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "RotateLeftUint32x8",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "RotateLeftUint32x16",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "RotateLeftUint64x2",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "RotateLeftUint64x4",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "RotateLeftUint64x8",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "RotateRightInt32x4",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "RotateRightInt32x8",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "RotateRightInt32x16",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "RotateRightInt64x2",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "RotateRightInt64x4",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "RotateRightInt64x8",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "RotateRightUint32x4",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "RotateRightUint32x8",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "RotateRightUint32x16",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "RotateRightUint64x2",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "RotateRightUint64x4",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "RotateRightUint64x8",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "RoundToEvenFloat32x4",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "RoundToEvenFloat32x8",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "RoundToEvenFloat64x2",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "RoundToEvenFloat64x4",
 +              argLen:  1,
 +              generic: true,
 +      },
 +      {
 +              name:    "SHA1Message1Uint32x4",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "SHA1Message2Uint32x4",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "SHA1NextEUint32x4",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "SHA256Message1Uint32x4",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "SHA256Message2Uint32x4",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "SHA256TwoRoundsUint32x4",
 +              argLen:  3,
 +              generic: true,
 +      },
 +      {
 +              name:    "ScaleFloat32x4",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "ScaleFloat32x8",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "ScaleFloat32x16",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "ScaleFloat64x2",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "ScaleFloat64x4",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "ScaleFloat64x8",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "SetHiFloat32x8",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "SetHiFloat32x16",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "SetHiFloat64x4",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "SetHiFloat64x8",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "SetHiInt8x32",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "SetHiInt8x64",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "SetHiInt16x16",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "SetHiInt16x32",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "SetHiInt32x8",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "SetHiInt32x16",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "SetHiInt64x4",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "SetHiInt64x8",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "SetHiUint8x32",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "SetHiUint8x64",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "SetHiUint16x16",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "SetHiUint16x32",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "SetHiUint32x8",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "SetHiUint32x16",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "SetHiUint64x4",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "SetHiUint64x8",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "SetLoFloat32x8",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "SetLoFloat32x16",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "SetLoFloat64x4",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "SetLoFloat64x8",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "SetLoInt8x32",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "SetLoInt8x64",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "SetLoInt16x16",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "SetLoInt16x32",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "SetLoInt32x8",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "SetLoInt32x16",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "SetLoInt64x4",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "SetLoInt64x8",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "SetLoUint8x32",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "SetLoUint8x64",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "SetLoUint16x16",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "SetLoUint16x32",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "SetLoUint32x8",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "SetLoUint32x16",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "SetLoUint64x4",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "SetLoUint64x8",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "ShiftAllLeftInt16x8",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "ShiftAllLeftInt16x16",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "ShiftAllLeftInt16x32",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "ShiftAllLeftInt32x4",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "ShiftAllLeftInt32x8",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "ShiftAllLeftInt32x16",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "ShiftAllLeftInt64x2",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "ShiftAllLeftInt64x4",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "ShiftAllLeftInt64x8",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "ShiftAllLeftUint16x8",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "ShiftAllLeftUint16x16",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "ShiftAllLeftUint16x32",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "ShiftAllLeftUint32x4",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "ShiftAllLeftUint32x8",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "ShiftAllLeftUint32x16",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "ShiftAllLeftUint64x2",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "ShiftAllLeftUint64x4",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "ShiftAllLeftUint64x8",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "ShiftAllRightInt16x8",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "ShiftAllRightInt16x16",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "ShiftAllRightInt16x32",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "ShiftAllRightInt32x4",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "ShiftAllRightInt32x8",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "ShiftAllRightInt32x16",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "ShiftAllRightInt64x2",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "ShiftAllRightInt64x4",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "ShiftAllRightInt64x8",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "ShiftAllRightUint16x8",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "ShiftAllRightUint16x16",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "ShiftAllRightUint16x32",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "ShiftAllRightUint32x4",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "ShiftAllRightUint32x8",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "ShiftAllRightUint32x16",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "ShiftAllRightUint64x2",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "ShiftAllRightUint64x4",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "ShiftAllRightUint64x8",
 +              argLen:  2,
 +              generic: true,
 +      },
 +      {
 +              name:    "ShiftLeftConcatInt16x8",
 +              argLen:  3,
 +              generic: true,
 +      },
 +      {
 +              name:    "ShiftLeftConcatInt16x16",
 +              argLen:  3,
 +              generic: true,
 +      },
 +      {
 +              name:    "ShiftLeftConcatInt16x32",
 +              argLen:  3,
                generic: true,
        },
        {

diff --cc src/cmd/compile/internal/ssa/regalloc.go
Simple merge

diff --cc src/cmd/compile/internal/ssa/rewritegeneric.go
Simple merge

diff --cc src/cmd/compile/internal/ssagen/ssa.go
Simple merge

diff --cc src/cmd/compile/internal/typecheck/_builtin/runtime.go
Simple merge

diff --cc src/cmd/compile/internal/typecheck/builtin.go
index eea7fd7d05065082451952686bfe9c1b18108bfa,ee892856dd93df06c8bc8f216a3f1824449f94e4..537de2cbe90a84d5545c2c41815c72b60d310186
--- 1/src/cmd/compile/internal/typecheck/builtin.go
--- 2/src/cmd/compile/internal/typecheck/builtin.go
+++ b/src/cmd/compile/internal/typecheck/builtin.go
@@@ -214,30 -219,29 +219,30 @@@ var runtimeDecls = [...]struct 
        {"racefuncexit", funcTag, 9},
        {"raceread", funcTag, 33},
        {"racewrite", funcTag, 33},
-       {"racereadrange", funcTag, 149},
-       {"racewriterange", funcTag, 149},
-       {"msanread", funcTag, 149},
-       {"msanwrite", funcTag, 149},
-       {"msanmove", funcTag, 150},
-       {"asanread", funcTag, 149},
-       {"asanwrite", funcTag, 149},
-       {"checkptrAlignment", funcTag, 151},
-       {"checkptrArithmetic", funcTag, 153},
-       {"libfuzzerTraceCmp1", funcTag, 154},
-       {"libfuzzerTraceCmp2", funcTag, 155},
-       {"libfuzzerTraceCmp4", funcTag, 156},
-       {"libfuzzerTraceCmp8", funcTag, 157},
-       {"libfuzzerTraceConstCmp1", funcTag, 154},
-       {"libfuzzerTraceConstCmp2", funcTag, 155},
-       {"libfuzzerTraceConstCmp4", funcTag, 156},
-       {"libfuzzerTraceConstCmp8", funcTag, 157},
-       {"libfuzzerHookStrCmp", funcTag, 158},
-       {"libfuzzerHookEqualFold", funcTag, 158},
-       {"addCovMeta", funcTag, 160},
+       {"racereadrange", funcTag, 154},
+       {"racewriterange", funcTag, 154},
+       {"msanread", funcTag, 154},
+       {"msanwrite", funcTag, 154},
+       {"msanmove", funcTag, 155},
+       {"asanread", funcTag, 154},
+       {"asanwrite", funcTag, 154},
+       {"checkptrAlignment", funcTag, 156},
+       {"checkptrArithmetic", funcTag, 158},
+       {"libfuzzerTraceCmp1", funcTag, 159},
+       {"libfuzzerTraceCmp2", funcTag, 160},
+       {"libfuzzerTraceCmp4", funcTag, 161},
+       {"libfuzzerTraceCmp8", funcTag, 162},
+       {"libfuzzerTraceConstCmp1", funcTag, 159},
+       {"libfuzzerTraceConstCmp2", funcTag, 160},
+       {"libfuzzerTraceConstCmp4", funcTag, 161},
+       {"libfuzzerTraceConstCmp8", funcTag, 162},
+       {"libfuzzerHookStrCmp", funcTag, 163},
+       {"libfuzzerHookEqualFold", funcTag, 163},
+       {"addCovMeta", funcTag, 165},
 +      {"x86HasAVX", varTag, 6},
 +      {"x86HasFMA", varTag, 6},
        {"x86HasPOPCNT", varTag, 6},
        {"x86HasSSE41", varTag, 6},
 -      {"x86HasFMA", varTag, 6},
        {"armHasVFPv4", varTag, 6},
        {"arm64HasATOMICS", varTag, 6},
        {"loong64HasLAMCAS", varTag, 6},

diff --cc src/cmd/compile/internal/types/type.go
Simple merge

diff --cc src/cmd/internal/obj/x86/obj6.go
Simple merge

diff --cc src/go/build/deps_test.go
Simple merge

diff --cc src/internal/buildcfg/exp.go
index 9dcac008813279accc2a2e2552d3863af0c1e332,f1a1d8632ef50729d7b450a1895b3425ce9f6d6f..da6aac914783887289980011e9d779bccb5aa56e
--- 1/src/internal/buildcfg/exp.go
--- 2/src/internal/buildcfg/exp.go
+++ b/src/internal/buildcfg/exp.go
@@@ -81,10 -81,8 +81,9 @@@ func ParseGOEXPERIMENT(goos, goarch, go
        baseline := goexperiment.Flags{
                RegabiWrappers:        regabiSupported,
                RegabiArgs:            regabiSupported,
 +              SIMD:                  goarch == "amd64", // TODO remove this (default to false) when dev.simd is merged
                Dwarf5:                dwarf5Supported,
                RandomizedHeapBase64:  true,
-               RuntimeFree:           true,
                SizeSpecializedMalloc: true,
                GreenTeaGC:            true,
        }

diff --cc src/internal/goexperiment/flags.go
Simple merge

diff --cc src/runtime/asm_amd64.s
Simple merge

diff --cc src/runtime/export_test.go
Simple merge

diff --cc src/runtime/panic.go
Simple merge

diff --cc src/runtime/proc.go
Simple merge