[dev.simd] cmd/compile, simd: add shift operations

This CL is generated by CL 683475.

Change-Id: I9e3ac6aff6f711cb26ff85e4c8729d9e2cc38e7d
Reviewed-on: https://go-review.googlesource.com/c/go/+/683715
LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com>
Reviewed-by: David Chase <drchase@google.com>

diff --git a/src/cmd/compile/internal/amd64/simdssa.go b/src/cmd/compile/internal/amd64/simdssa.go
index 5297680357844bcf4ba14774eb1fd79acefab034..6c1d365bfa7f9bd068bfb16a0fefb083ea3e566d 100644 (file)
--- a/src/cmd/compile/internal/amd64/simdssa.go
+++ b/src/cmd/compile/internal/amd64/simdssa.go
@@ -247,6 +247,18 @@ func ssaGenSIMDValue(s *ssagen.State, v *ssa.Value) bool {
                ssa.OpAMD64VPHSUBW256,
                ssa.OpAMD64VPHSUBD128,
                ssa.OpAMD64VPHSUBD256,
+               ssa.OpAMD64VPROLVD128,
+               ssa.OpAMD64VPROLVD256,
+               ssa.OpAMD64VPROLVD512,
+               ssa.OpAMD64VPROLVQ128,
+               ssa.OpAMD64VPROLVQ256,
+               ssa.OpAMD64VPROLVQ512,
+               ssa.OpAMD64VPRORVD128,
+               ssa.OpAMD64VPRORVD256,
+               ssa.OpAMD64VPRORVD512,
+               ssa.OpAMD64VPRORVQ128,
+               ssa.OpAMD64VPRORVQ256,
+               ssa.OpAMD64VPRORVQ512,
                ssa.OpAMD64VPADDSB128,
                ssa.OpAMD64VPADDSB256,
                ssa.OpAMD64VPADDSB512,
@@ -266,6 +278,33 @@ func ssaGenSIMDValue(s *ssagen.State, v *ssa.Value) bool {
                ssa.OpAMD64VPMADDUBSW128,
                ssa.OpAMD64VPMADDUBSW256,
                ssa.OpAMD64VPMADDUBSW512,
+               ssa.OpAMD64VPSLLVW128,
+               ssa.OpAMD64VPSLLVW256,
+               ssa.OpAMD64VPSLLVW512,
+               ssa.OpAMD64VPSLLVD128,
+               ssa.OpAMD64VPSLLVD256,
+               ssa.OpAMD64VPSLLVD512,
+               ssa.OpAMD64VPSLLVQ128,
+               ssa.OpAMD64VPSLLVQ256,
+               ssa.OpAMD64VPSLLVQ512,
+               ssa.OpAMD64VPSRLVW128,
+               ssa.OpAMD64VPSRLVW256,
+               ssa.OpAMD64VPSRLVW512,
+               ssa.OpAMD64VPSRLVD128,
+               ssa.OpAMD64VPSRLVD256,
+               ssa.OpAMD64VPSRLVD512,
+               ssa.OpAMD64VPSRLVQ128,
+               ssa.OpAMD64VPSRLVQ256,
+               ssa.OpAMD64VPSRLVQ512,
+               ssa.OpAMD64VPSRAVW128,
+               ssa.OpAMD64VPSRAVW256,
+               ssa.OpAMD64VPSRAVW512,
+               ssa.OpAMD64VPSRAVD128,
+               ssa.OpAMD64VPSRAVD256,
+               ssa.OpAMD64VPSRAVD512,
+               ssa.OpAMD64VPSRAVQ128,
+               ssa.OpAMD64VPSRAVQ256,
+               ssa.OpAMD64VPSRAVQ512,
                ssa.OpAMD64VPSIGNB128,
                ssa.OpAMD64VPSIGNB256,
                ssa.OpAMD64VPSIGNW128,
@@ -464,6 +503,18 @@ func ssaGenSIMDValue(s *ssagen.State, v *ssa.Value) bool {
                ssa.OpAMD64VPMADDWDMasked128,
                ssa.OpAMD64VPMADDWDMasked256,
                ssa.OpAMD64VPMADDWDMasked512,
+               ssa.OpAMD64VPROLVDMasked128,
+               ssa.OpAMD64VPROLVDMasked256,
+               ssa.OpAMD64VPROLVDMasked512,
+               ssa.OpAMD64VPROLVQMasked128,
+               ssa.OpAMD64VPROLVQMasked256,
+               ssa.OpAMD64VPROLVQMasked512,
+               ssa.OpAMD64VPRORVDMasked128,
+               ssa.OpAMD64VPRORVDMasked256,
+               ssa.OpAMD64VPRORVDMasked512,
+               ssa.OpAMD64VPRORVQMasked128,
+               ssa.OpAMD64VPRORVQMasked256,
+               ssa.OpAMD64VPRORVQMasked512,
                ssa.OpAMD64VPADDSBMasked128,
                ssa.OpAMD64VPADDSBMasked256,
                ssa.OpAMD64VPADDSBMasked512,
@@ -479,6 +530,33 @@ func ssaGenSIMDValue(s *ssagen.State, v *ssa.Value) bool {
                ssa.OpAMD64VPMADDUBSWMasked128,
                ssa.OpAMD64VPMADDUBSWMasked256,
                ssa.OpAMD64VPMADDUBSWMasked512,
+               ssa.OpAMD64VPSLLVWMasked128,
+               ssa.OpAMD64VPSLLVWMasked256,
+               ssa.OpAMD64VPSLLVWMasked512,
+               ssa.OpAMD64VPSLLVDMasked128,
+               ssa.OpAMD64VPSLLVDMasked256,
+               ssa.OpAMD64VPSLLVDMasked512,
+               ssa.OpAMD64VPSLLVQMasked128,
+               ssa.OpAMD64VPSLLVQMasked256,
+               ssa.OpAMD64VPSLLVQMasked512,
+               ssa.OpAMD64VPSRLVWMasked128,
+               ssa.OpAMD64VPSRLVWMasked256,
+               ssa.OpAMD64VPSRLVWMasked512,
+               ssa.OpAMD64VPSRLVDMasked128,
+               ssa.OpAMD64VPSRLVDMasked256,
+               ssa.OpAMD64VPSRLVDMasked512,
+               ssa.OpAMD64VPSRLVQMasked128,
+               ssa.OpAMD64VPSRLVQMasked256,
+               ssa.OpAMD64VPSRLVQMasked512,
+               ssa.OpAMD64VPSRAVWMasked128,
+               ssa.OpAMD64VPSRAVWMasked256,
+               ssa.OpAMD64VPSRAVWMasked512,
+               ssa.OpAMD64VPSRAVDMasked128,
+               ssa.OpAMD64VPSRAVDMasked256,
+               ssa.OpAMD64VPSRAVDMasked512,
+               ssa.OpAMD64VPSRAVQMasked128,
+               ssa.OpAMD64VPSRAVQMasked256,
+               ssa.OpAMD64VPSRAVQMasked512,
                ssa.OpAMD64VSUBPSMasked128,
                ssa.OpAMD64VSUBPSMasked256,
                ssa.OpAMD64VSUBPSMasked512,
@@ -570,7 +648,19 @@ func ssaGenSIMDValue(s *ssagen.State, v *ssa.Value) bool {
                ssa.OpAMD64VREDUCEPS512,
                ssa.OpAMD64VREDUCEPD128,
                ssa.OpAMD64VREDUCEPD256,
-               ssa.OpAMD64VREDUCEPD512:
+               ssa.OpAMD64VREDUCEPD512,
+               ssa.OpAMD64VPROLD128,
+               ssa.OpAMD64VPROLD256,
+               ssa.OpAMD64VPROLD512,
+               ssa.OpAMD64VPROLQ128,
+               ssa.OpAMD64VPROLQ256,
+               ssa.OpAMD64VPROLQ512,
+               ssa.OpAMD64VPRORD128,
+               ssa.OpAMD64VPRORD256,
+               ssa.OpAMD64VPRORD512,
+               ssa.OpAMD64VPRORQ128,
+               ssa.OpAMD64VPRORQ256,
+               ssa.OpAMD64VPRORQ512:
                p = simdFp11Imm8(s, v)
 
        case ssa.OpAMD64VRNDSCALEPSMasked128,
@@ -584,14 +674,44 @@ func ssaGenSIMDValue(s *ssagen.State, v *ssa.Value) bool {
                ssa.OpAMD64VREDUCEPSMasked512,
                ssa.OpAMD64VREDUCEPDMasked128,
                ssa.OpAMD64VREDUCEPDMasked256,
-               ssa.OpAMD64VREDUCEPDMasked512:
+               ssa.OpAMD64VREDUCEPDMasked512,
+               ssa.OpAMD64VPROLDMasked128,
+               ssa.OpAMD64VPROLDMasked256,
+               ssa.OpAMD64VPROLDMasked512,
+               ssa.OpAMD64VPROLQMasked128,
+               ssa.OpAMD64VPROLQMasked256,
+               ssa.OpAMD64VPROLQMasked512,
+               ssa.OpAMD64VPRORDMasked128,
+               ssa.OpAMD64VPRORDMasked256,
+               ssa.OpAMD64VPRORDMasked512,
+               ssa.OpAMD64VPRORQMasked128,
+               ssa.OpAMD64VPRORQMasked256,
+               ssa.OpAMD64VPRORQMasked512:
                p = simdFpkfpImm8(s, v)
 
        case ssa.OpAMD64VDPPD128,
                ssa.OpAMD64VCMPPS128,
                ssa.OpAMD64VCMPPS256,
                ssa.OpAMD64VCMPPD128,
-               ssa.OpAMD64VCMPPD256:
+               ssa.OpAMD64VCMPPD256,
+               ssa.OpAMD64VPSHLDW128,
+               ssa.OpAMD64VPSHLDW256,
+               ssa.OpAMD64VPSHLDW512,
+               ssa.OpAMD64VPSHLDD128,
+               ssa.OpAMD64VPSHLDD256,
+               ssa.OpAMD64VPSHLDD512,
+               ssa.OpAMD64VPSHLDQ128,
+               ssa.OpAMD64VPSHLDQ256,
+               ssa.OpAMD64VPSHLDQ512,
+               ssa.OpAMD64VPSHRDW128,
+               ssa.OpAMD64VPSHRDW256,
+               ssa.OpAMD64VPSHRDW512,
+               ssa.OpAMD64VPSHRDD128,
+               ssa.OpAMD64VPSHRDD256,
+               ssa.OpAMD64VPSHRDD512,
+               ssa.OpAMD64VPSHRDQ128,
+               ssa.OpAMD64VPSHRDQ256,
+               ssa.OpAMD64VPSHRDQ512:
                p = simdFp21Imm8(s, v)
 
        case ssa.OpAMD64VCMPPS512,
@@ -681,6 +801,24 @@ func ssaGenSIMDValue(s *ssagen.State, v *ssa.Value) bool {
                ssa.OpAMD64VPDPBUSDS128,
                ssa.OpAMD64VPDPBUSDS256,
                ssa.OpAMD64VPDPBUSDS512,
+               ssa.OpAMD64VPSHLDVW128,
+               ssa.OpAMD64VPSHLDVW256,
+               ssa.OpAMD64VPSHLDVW512,
+               ssa.OpAMD64VPSHLDVD128,
+               ssa.OpAMD64VPSHLDVD256,
+               ssa.OpAMD64VPSHLDVD512,
+               ssa.OpAMD64VPSHLDVQ128,
+               ssa.OpAMD64VPSHLDVQ256,
+               ssa.OpAMD64VPSHLDVQ512,
+               ssa.OpAMD64VPSHRDVW128,
+               ssa.OpAMD64VPSHRDVW256,
+               ssa.OpAMD64VPSHRDVW512,
+               ssa.OpAMD64VPSHRDVD128,
+               ssa.OpAMD64VPSHRDVD256,
+               ssa.OpAMD64VPSHRDVD512,
+               ssa.OpAMD64VPSHRDVQ128,
+               ssa.OpAMD64VPSHRDVQ256,
+               ssa.OpAMD64VPSHRDVQ512,
                ssa.OpAMD64VPDPBUSD128,
                ssa.OpAMD64VPDPBUSD256,
                ssa.OpAMD64VPDPBUSD512:
@@ -713,11 +851,63 @@ func ssaGenSIMDValue(s *ssagen.State, v *ssa.Value) bool {
                ssa.OpAMD64VPDPBUSDSMasked128,
                ssa.OpAMD64VPDPBUSDSMasked256,
                ssa.OpAMD64VPDPBUSDSMasked512,
+               ssa.OpAMD64VPSHLDVWMasked128,
+               ssa.OpAMD64VPSHLDVWMasked256,
+               ssa.OpAMD64VPSHLDVWMasked512,
+               ssa.OpAMD64VPSHLDVDMasked128,
+               ssa.OpAMD64VPSHLDVDMasked256,
+               ssa.OpAMD64VPSHLDVDMasked512,
+               ssa.OpAMD64VPSHLDVQMasked128,
+               ssa.OpAMD64VPSHLDVQMasked256,
+               ssa.OpAMD64VPSHLDVQMasked512,
+               ssa.OpAMD64VPSHRDVWMasked128,
+               ssa.OpAMD64VPSHRDVWMasked256,
+               ssa.OpAMD64VPSHRDVWMasked512,
+               ssa.OpAMD64VPSHRDVDMasked128,
+               ssa.OpAMD64VPSHRDVDMasked256,
+               ssa.OpAMD64VPSHRDVDMasked512,
+               ssa.OpAMD64VPSHRDVQMasked128,
+               ssa.OpAMD64VPSHRDVQMasked256,
+               ssa.OpAMD64VPSHRDVQMasked512,
                ssa.OpAMD64VPDPBUSDMasked128,
                ssa.OpAMD64VPDPBUSDMasked256,
                ssa.OpAMD64VPDPBUSDMasked512:
                p = simdFp3kfpResultInArg0(s, v)
 
+       case ssa.OpAMD64VPSLLW128,
+               ssa.OpAMD64VPSLLW256,
+               ssa.OpAMD64VPSLLD128,
+               ssa.OpAMD64VPSLLD256,
+               ssa.OpAMD64VPSLLQ128,
+               ssa.OpAMD64VPSLLQ256,
+               ssa.OpAMD64VPSLLQ512,
+               ssa.OpAMD64VPSRLW128,
+               ssa.OpAMD64VPSRLW256,
+               ssa.OpAMD64VPSRLD128,
+               ssa.OpAMD64VPSRLD256,
+               ssa.OpAMD64VPSRLQ128,
+               ssa.OpAMD64VPSRLQ256,
+               ssa.OpAMD64VPSRLQ512,
+               ssa.OpAMD64VPSRAW128,
+               ssa.OpAMD64VPSRAW256,
+               ssa.OpAMD64VPSRAD128,
+               ssa.OpAMD64VPSRAD256,
+               ssa.OpAMD64VPSRAQ128,
+               ssa.OpAMD64VPSRAQ256,
+               ssa.OpAMD64VPSRAQ512:
+               p = simdFpXfp(s, v)
+
+       case ssa.OpAMD64VPSLLQMasked128,
+               ssa.OpAMD64VPSLLQMasked256,
+               ssa.OpAMD64VPSLLQMasked512,
+               ssa.OpAMD64VPSRLQMasked128,
+               ssa.OpAMD64VPSRLQMasked256,
+               ssa.OpAMD64VPSRLQMasked512,
+               ssa.OpAMD64VPSRAQMasked128,
+               ssa.OpAMD64VPSRAQMasked256,
+               ssa.OpAMD64VPSRAQMasked512:
+               p = simdFpXkfp(s, v)
+
        case ssa.OpAMD64VPINSRB128,
                ssa.OpAMD64VPINSRW128,
                ssa.OpAMD64VPINSRD128,
@@ -730,6 +920,26 @@ func ssaGenSIMDValue(s *ssagen.State, v *ssa.Value) bool {
                ssa.OpAMD64VPEXTRQ128:
                p = simdFpgpImm8(s, v)
 
+       case ssa.OpAMD64VPSHLDWMasked128,
+               ssa.OpAMD64VPSHLDWMasked256,
+               ssa.OpAMD64VPSHLDWMasked512,
+               ssa.OpAMD64VPSHLDDMasked128,
+               ssa.OpAMD64VPSHLDDMasked256,
+               ssa.OpAMD64VPSHLDDMasked512,
+               ssa.OpAMD64VPSHLDQMasked128,
+               ssa.OpAMD64VPSHLDQMasked256,
+               ssa.OpAMD64VPSHLDQMasked512,
+               ssa.OpAMD64VPSHRDWMasked128,
+               ssa.OpAMD64VPSHRDWMasked256,
+               ssa.OpAMD64VPSHRDWMasked512,
+               ssa.OpAMD64VPSHRDDMasked128,
+               ssa.OpAMD64VPSHRDDMasked256,
+               ssa.OpAMD64VPSHRDDMasked512,
+               ssa.OpAMD64VPSHRDQMasked128,
+               ssa.OpAMD64VPSHRDQMasked256,
+               ssa.OpAMD64VPSHRDQMasked512:
+               p = simdFp2kfpImm8(s, v)
+
        default:
                // Unknown reg shape
                return false
@@ -968,6 +1178,30 @@ func ssaGenSIMDValue(s *ssagen.State, v *ssa.Value) bool {
                ssa.OpAMD64VPOPCNTQMasked128,
                ssa.OpAMD64VPOPCNTQMasked256,
                ssa.OpAMD64VPOPCNTQMasked512,
+               ssa.OpAMD64VPROLDMasked128,
+               ssa.OpAMD64VPROLDMasked256,
+               ssa.OpAMD64VPROLDMasked512,
+               ssa.OpAMD64VPROLQMasked128,
+               ssa.OpAMD64VPROLQMasked256,
+               ssa.OpAMD64VPROLQMasked512,
+               ssa.OpAMD64VPRORDMasked128,
+               ssa.OpAMD64VPRORDMasked256,
+               ssa.OpAMD64VPRORDMasked512,
+               ssa.OpAMD64VPRORQMasked128,
+               ssa.OpAMD64VPRORQMasked256,
+               ssa.OpAMD64VPRORQMasked512,
+               ssa.OpAMD64VPROLVDMasked128,
+               ssa.OpAMD64VPROLVDMasked256,
+               ssa.OpAMD64VPROLVDMasked512,
+               ssa.OpAMD64VPROLVQMasked128,
+               ssa.OpAMD64VPROLVQMasked256,
+               ssa.OpAMD64VPROLVQMasked512,
+               ssa.OpAMD64VPRORVDMasked128,
+               ssa.OpAMD64VPRORVDMasked256,
+               ssa.OpAMD64VPRORVDMasked512,
+               ssa.OpAMD64VPRORVQMasked128,
+               ssa.OpAMD64VPRORVQMasked256,
+               ssa.OpAMD64VPRORVQMasked512,
                ssa.OpAMD64VPADDSBMasked128,
                ssa.OpAMD64VPADDSBMasked256,
                ssa.OpAMD64VPADDSBMasked512,
@@ -989,6 +1223,78 @@ func ssaGenSIMDValue(s *ssagen.State, v *ssa.Value) bool {
                ssa.OpAMD64VPDPBUSDSMasked128,
                ssa.OpAMD64VPDPBUSDSMasked256,
                ssa.OpAMD64VPDPBUSDSMasked512,
+               ssa.OpAMD64VPSLLQMasked128,
+               ssa.OpAMD64VPSLLQMasked256,
+               ssa.OpAMD64VPSLLQMasked512,
+               ssa.OpAMD64VPSHLDWMasked128,
+               ssa.OpAMD64VPSHLDWMasked256,
+               ssa.OpAMD64VPSHLDWMasked512,
+               ssa.OpAMD64VPSHLDDMasked128,
+               ssa.OpAMD64VPSHLDDMasked256,
+               ssa.OpAMD64VPSHLDDMasked512,
+               ssa.OpAMD64VPSHLDQMasked128,
+               ssa.OpAMD64VPSHLDQMasked256,
+               ssa.OpAMD64VPSHLDQMasked512,
+               ssa.OpAMD64VPSRLQMasked128,
+               ssa.OpAMD64VPSRLQMasked256,
+               ssa.OpAMD64VPSRLQMasked512,
+               ssa.OpAMD64VPSHRDWMasked128,
+               ssa.OpAMD64VPSHRDWMasked256,
+               ssa.OpAMD64VPSHRDWMasked512,
+               ssa.OpAMD64VPSHRDDMasked128,
+               ssa.OpAMD64VPSHRDDMasked256,
+               ssa.OpAMD64VPSHRDDMasked512,
+               ssa.OpAMD64VPSHRDQMasked128,
+               ssa.OpAMD64VPSHRDQMasked256,
+               ssa.OpAMD64VPSHRDQMasked512,
+               ssa.OpAMD64VPSRAQMasked128,
+               ssa.OpAMD64VPSRAQMasked256,
+               ssa.OpAMD64VPSRAQMasked512,
+               ssa.OpAMD64VPSLLVWMasked128,
+               ssa.OpAMD64VPSLLVWMasked256,
+               ssa.OpAMD64VPSLLVWMasked512,
+               ssa.OpAMD64VPSLLVDMasked128,
+               ssa.OpAMD64VPSLLVDMasked256,
+               ssa.OpAMD64VPSLLVDMasked512,
+               ssa.OpAMD64VPSLLVQMasked128,
+               ssa.OpAMD64VPSLLVQMasked256,
+               ssa.OpAMD64VPSLLVQMasked512,
+               ssa.OpAMD64VPSHLDVWMasked128,
+               ssa.OpAMD64VPSHLDVWMasked256,
+               ssa.OpAMD64VPSHLDVWMasked512,
+               ssa.OpAMD64VPSHLDVDMasked128,
+               ssa.OpAMD64VPSHLDVDMasked256,
+               ssa.OpAMD64VPSHLDVDMasked512,
+               ssa.OpAMD64VPSHLDVQMasked128,
+               ssa.OpAMD64VPSHLDVQMasked256,
+               ssa.OpAMD64VPSHLDVQMasked512,
+               ssa.OpAMD64VPSRLVWMasked128,
+               ssa.OpAMD64VPSRLVWMasked256,
+               ssa.OpAMD64VPSRLVWMasked512,
+               ssa.OpAMD64VPSRLVDMasked128,
+               ssa.OpAMD64VPSRLVDMasked256,
+               ssa.OpAMD64VPSRLVDMasked512,
+               ssa.OpAMD64VPSRLVQMasked128,
+               ssa.OpAMD64VPSRLVQMasked256,
+               ssa.OpAMD64VPSRLVQMasked512,
+               ssa.OpAMD64VPSHRDVWMasked128,
+               ssa.OpAMD64VPSHRDVWMasked256,
+               ssa.OpAMD64VPSHRDVWMasked512,
+               ssa.OpAMD64VPSHRDVDMasked128,
+               ssa.OpAMD64VPSHRDVDMasked256,
+               ssa.OpAMD64VPSHRDVDMasked512,
+               ssa.OpAMD64VPSHRDVQMasked128,
+               ssa.OpAMD64VPSHRDVQMasked256,
+               ssa.OpAMD64VPSHRDVQMasked512,
+               ssa.OpAMD64VPSRAVWMasked128,
+               ssa.OpAMD64VPSRAVWMasked256,
+               ssa.OpAMD64VPSRAVWMasked512,
+               ssa.OpAMD64VPSRAVDMasked128,
+               ssa.OpAMD64VPSRAVDMasked256,
+               ssa.OpAMD64VPSRAVDMasked512,
+               ssa.OpAMD64VPSRAVQMasked128,
+               ssa.OpAMD64VPSRAVQMasked256,
+               ssa.OpAMD64VPSRAVQMasked512,
                ssa.OpAMD64VSQRTPSMasked128,
                ssa.OpAMD64VSQRTPSMasked256,
                ssa.OpAMD64VSQRTPSMasked512,

diff --git a/src/cmd/compile/internal/ssa/_gen/simdAMD64.rules b/src/cmd/compile/internal/ssa/_gen/simdAMD64.rules
index b21d58b4a44a2187a2315d2c7fc75f3333418a61..968ded213133a23260973bebbc05bc8b13f190fd 100644 (file)
--- a/src/cmd/compile/internal/ssa/_gen/simdAMD64.rules
+++ b/src/cmd/compile/internal/ssa/_gen/simdAMD64.rules
@@ -904,6 +904,54 @@
 (MaskedPopCountUint64x2 x mask) => (VPOPCNTQMasked128 x (VPMOVVec64x2ToM <types.TypeMask> mask))
 (MaskedPopCountUint64x4 x mask) => (VPOPCNTQMasked256 x (VPMOVVec64x4ToM <types.TypeMask> mask))
 (MaskedPopCountUint64x8 x mask) => (VPOPCNTQMasked512 x (VPMOVVec64x8ToM <types.TypeMask> mask))
+(MaskedRotateAllLeftInt32x4 [a] x mask) => (VPROLDMasked128 [a] x (VPMOVVec32x4ToM <types.TypeMask> mask))
+(MaskedRotateAllLeftInt32x8 [a] x mask) => (VPROLDMasked256 [a] x (VPMOVVec32x8ToM <types.TypeMask> mask))
+(MaskedRotateAllLeftInt32x16 [a] x mask) => (VPROLDMasked512 [a] x (VPMOVVec32x16ToM <types.TypeMask> mask))
+(MaskedRotateAllLeftInt64x2 [a] x mask) => (VPROLQMasked128 [a] x (VPMOVVec64x2ToM <types.TypeMask> mask))
+(MaskedRotateAllLeftInt64x4 [a] x mask) => (VPROLQMasked256 [a] x (VPMOVVec64x4ToM <types.TypeMask> mask))
+(MaskedRotateAllLeftInt64x8 [a] x mask) => (VPROLQMasked512 [a] x (VPMOVVec64x8ToM <types.TypeMask> mask))
+(MaskedRotateAllLeftUint32x4 [a] x mask) => (VPROLDMasked128 [a] x (VPMOVVec32x4ToM <types.TypeMask> mask))
+(MaskedRotateAllLeftUint32x8 [a] x mask) => (VPROLDMasked256 [a] x (VPMOVVec32x8ToM <types.TypeMask> mask))
+(MaskedRotateAllLeftUint32x16 [a] x mask) => (VPROLDMasked512 [a] x (VPMOVVec32x16ToM <types.TypeMask> mask))
+(MaskedRotateAllLeftUint64x2 [a] x mask) => (VPROLQMasked128 [a] x (VPMOVVec64x2ToM <types.TypeMask> mask))
+(MaskedRotateAllLeftUint64x4 [a] x mask) => (VPROLQMasked256 [a] x (VPMOVVec64x4ToM <types.TypeMask> mask))
+(MaskedRotateAllLeftUint64x8 [a] x mask) => (VPROLQMasked512 [a] x (VPMOVVec64x8ToM <types.TypeMask> mask))
+(MaskedRotateAllRightInt32x4 [a] x mask) => (VPRORDMasked128 [a] x (VPMOVVec32x4ToM <types.TypeMask> mask))
+(MaskedRotateAllRightInt32x8 [a] x mask) => (VPRORDMasked256 [a] x (VPMOVVec32x8ToM <types.TypeMask> mask))
+(MaskedRotateAllRightInt32x16 [a] x mask) => (VPRORDMasked512 [a] x (VPMOVVec32x16ToM <types.TypeMask> mask))
+(MaskedRotateAllRightInt64x2 [a] x mask) => (VPRORQMasked128 [a] x (VPMOVVec64x2ToM <types.TypeMask> mask))
+(MaskedRotateAllRightInt64x4 [a] x mask) => (VPRORQMasked256 [a] x (VPMOVVec64x4ToM <types.TypeMask> mask))
+(MaskedRotateAllRightInt64x8 [a] x mask) => (VPRORQMasked512 [a] x (VPMOVVec64x8ToM <types.TypeMask> mask))
+(MaskedRotateAllRightUint32x4 [a] x mask) => (VPRORDMasked128 [a] x (VPMOVVec32x4ToM <types.TypeMask> mask))
+(MaskedRotateAllRightUint32x8 [a] x mask) => (VPRORDMasked256 [a] x (VPMOVVec32x8ToM <types.TypeMask> mask))
+(MaskedRotateAllRightUint32x16 [a] x mask) => (VPRORDMasked512 [a] x (VPMOVVec32x16ToM <types.TypeMask> mask))
+(MaskedRotateAllRightUint64x2 [a] x mask) => (VPRORQMasked128 [a] x (VPMOVVec64x2ToM <types.TypeMask> mask))
+(MaskedRotateAllRightUint64x4 [a] x mask) => (VPRORQMasked256 [a] x (VPMOVVec64x4ToM <types.TypeMask> mask))
+(MaskedRotateAllRightUint64x8 [a] x mask) => (VPRORQMasked512 [a] x (VPMOVVec64x8ToM <types.TypeMask> mask))
+(MaskedRotateLeftInt32x4 x y mask) => (VPROLVDMasked128 x y (VPMOVVec32x4ToM <types.TypeMask> mask))
+(MaskedRotateLeftInt32x8 x y mask) => (VPROLVDMasked256 x y (VPMOVVec32x8ToM <types.TypeMask> mask))
+(MaskedRotateLeftInt32x16 x y mask) => (VPROLVDMasked512 x y (VPMOVVec32x16ToM <types.TypeMask> mask))
+(MaskedRotateLeftInt64x2 x y mask) => (VPROLVQMasked128 x y (VPMOVVec64x2ToM <types.TypeMask> mask))
+(MaskedRotateLeftInt64x4 x y mask) => (VPROLVQMasked256 x y (VPMOVVec64x4ToM <types.TypeMask> mask))
+(MaskedRotateLeftInt64x8 x y mask) => (VPROLVQMasked512 x y (VPMOVVec64x8ToM <types.TypeMask> mask))
+(MaskedRotateLeftUint32x4 x y mask) => (VPROLVDMasked128 x y (VPMOVVec32x4ToM <types.TypeMask> mask))
+(MaskedRotateLeftUint32x8 x y mask) => (VPROLVDMasked256 x y (VPMOVVec32x8ToM <types.TypeMask> mask))
+(MaskedRotateLeftUint32x16 x y mask) => (VPROLVDMasked512 x y (VPMOVVec32x16ToM <types.TypeMask> mask))
+(MaskedRotateLeftUint64x2 x y mask) => (VPROLVQMasked128 x y (VPMOVVec64x2ToM <types.TypeMask> mask))
+(MaskedRotateLeftUint64x4 x y mask) => (VPROLVQMasked256 x y (VPMOVVec64x4ToM <types.TypeMask> mask))
+(MaskedRotateLeftUint64x8 x y mask) => (VPROLVQMasked512 x y (VPMOVVec64x8ToM <types.TypeMask> mask))
+(MaskedRotateRightInt32x4 x y mask) => (VPRORVDMasked128 x y (VPMOVVec32x4ToM <types.TypeMask> mask))
+(MaskedRotateRightInt32x8 x y mask) => (VPRORVDMasked256 x y (VPMOVVec32x8ToM <types.TypeMask> mask))
+(MaskedRotateRightInt32x16 x y mask) => (VPRORVDMasked512 x y (VPMOVVec32x16ToM <types.TypeMask> mask))
+(MaskedRotateRightInt64x2 x y mask) => (VPRORVQMasked128 x y (VPMOVVec64x2ToM <types.TypeMask> mask))
+(MaskedRotateRightInt64x4 x y mask) => (VPRORVQMasked256 x y (VPMOVVec64x4ToM <types.TypeMask> mask))
+(MaskedRotateRightInt64x8 x y mask) => (VPRORVQMasked512 x y (VPMOVVec64x8ToM <types.TypeMask> mask))
+(MaskedRotateRightUint32x4 x y mask) => (VPRORVDMasked128 x y (VPMOVVec32x4ToM <types.TypeMask> mask))
+(MaskedRotateRightUint32x8 x y mask) => (VPRORVDMasked256 x y (VPMOVVec32x8ToM <types.TypeMask> mask))
+(MaskedRotateRightUint32x16 x y mask) => (VPRORVDMasked512 x y (VPMOVVec32x16ToM <types.TypeMask> mask))
+(MaskedRotateRightUint64x2 x y mask) => (VPRORVQMasked128 x y (VPMOVVec64x2ToM <types.TypeMask> mask))
+(MaskedRotateRightUint64x4 x y mask) => (VPRORVQMasked256 x y (VPMOVVec64x4ToM <types.TypeMask> mask))
+(MaskedRotateRightUint64x8 x y mask) => (VPRORVQMasked512 x y (VPMOVVec64x8ToM <types.TypeMask> mask))
 (MaskedRoundSuppressExceptionWithPrecisionFloat32x4 [a] x mask) => (VRNDSCALEPSMasked128 [a+8] x (VPMOVVec32x4ToM <types.TypeMask> mask))
 (MaskedRoundSuppressExceptionWithPrecisionFloat32x8 [a] x mask) => (VRNDSCALEPSMasked256 [a+8] x (VPMOVVec32x8ToM <types.TypeMask> mask))
 (MaskedRoundSuppressExceptionWithPrecisionFloat32x16 [a] x mask) => (VRNDSCALEPSMasked512 [a+8] x (VPMOVVec32x16ToM <types.TypeMask> mask))
@@ -952,6 +1000,147 @@
 (MaskedSaturatedUnsignedSignedQuadDotProdAccumulateUint32x4 x y z mask) => (VPDPBUSDSMasked128 x y z (VPMOVVec32x4ToM <types.TypeMask> mask))
 (MaskedSaturatedUnsignedSignedQuadDotProdAccumulateUint32x8 x y z mask) => (VPDPBUSDSMasked256 x y z (VPMOVVec32x8ToM <types.TypeMask> mask))
 (MaskedSaturatedUnsignedSignedQuadDotProdAccumulateUint32x16 x y z mask) => (VPDPBUSDSMasked512 x y z (VPMOVVec32x16ToM <types.TypeMask> mask))
+(MaskedShiftAllLeftInt64x2 x y mask) => (VPSLLQMasked128 x y (VPMOVVec64x2ToM <types.TypeMask> mask))
+(MaskedShiftAllLeftInt64x4 x y mask) => (VPSLLQMasked256 x y (VPMOVVec64x4ToM <types.TypeMask> mask))
+(MaskedShiftAllLeftInt64x8 x y mask) => (VPSLLQMasked512 x y (VPMOVVec64x8ToM <types.TypeMask> mask))
+(MaskedShiftAllLeftUint64x2 x y mask) => (VPSLLQMasked128 x y (VPMOVVec64x2ToM <types.TypeMask> mask))
+(MaskedShiftAllLeftUint64x4 x y mask) => (VPSLLQMasked256 x y (VPMOVVec64x4ToM <types.TypeMask> mask))
+(MaskedShiftAllLeftUint64x8 x y mask) => (VPSLLQMasked512 x y (VPMOVVec64x8ToM <types.TypeMask> mask))
+(MaskedShiftAllLeftAndFillUpperFromInt16x8 [a] x y mask) => (VPSHLDWMasked128 [a] x y (VPMOVVec16x8ToM <types.TypeMask> mask))
+(MaskedShiftAllLeftAndFillUpperFromInt16x16 [a] x y mask) => (VPSHLDWMasked256 [a] x y (VPMOVVec16x16ToM <types.TypeMask> mask))
+(MaskedShiftAllLeftAndFillUpperFromInt16x32 [a] x y mask) => (VPSHLDWMasked512 [a] x y (VPMOVVec16x32ToM <types.TypeMask> mask))
+(MaskedShiftAllLeftAndFillUpperFromInt32x4 [a] x y mask) => (VPSHLDDMasked128 [a] x y (VPMOVVec32x4ToM <types.TypeMask> mask))
+(MaskedShiftAllLeftAndFillUpperFromInt32x8 [a] x y mask) => (VPSHLDDMasked256 [a] x y (VPMOVVec32x8ToM <types.TypeMask> mask))
+(MaskedShiftAllLeftAndFillUpperFromInt32x16 [a] x y mask) => (VPSHLDDMasked512 [a] x y (VPMOVVec32x16ToM <types.TypeMask> mask))
+(MaskedShiftAllLeftAndFillUpperFromInt64x2 [a] x y mask) => (VPSHLDQMasked128 [a] x y (VPMOVVec64x2ToM <types.TypeMask> mask))
+(MaskedShiftAllLeftAndFillUpperFromInt64x4 [a] x y mask) => (VPSHLDQMasked256 [a] x y (VPMOVVec64x4ToM <types.TypeMask> mask))
+(MaskedShiftAllLeftAndFillUpperFromInt64x8 [a] x y mask) => (VPSHLDQMasked512 [a] x y (VPMOVVec64x8ToM <types.TypeMask> mask))
+(MaskedShiftAllLeftAndFillUpperFromUint16x8 [a] x y mask) => (VPSHLDWMasked128 [a] x y (VPMOVVec16x8ToM <types.TypeMask> mask))
+(MaskedShiftAllLeftAndFillUpperFromUint16x16 [a] x y mask) => (VPSHLDWMasked256 [a] x y (VPMOVVec16x16ToM <types.TypeMask> mask))
+(MaskedShiftAllLeftAndFillUpperFromUint16x32 [a] x y mask) => (VPSHLDWMasked512 [a] x y (VPMOVVec16x32ToM <types.TypeMask> mask))
+(MaskedShiftAllLeftAndFillUpperFromUint32x4 [a] x y mask) => (VPSHLDDMasked128 [a] x y (VPMOVVec32x4ToM <types.TypeMask> mask))
+(MaskedShiftAllLeftAndFillUpperFromUint32x8 [a] x y mask) => (VPSHLDDMasked256 [a] x y (VPMOVVec32x8ToM <types.TypeMask> mask))
+(MaskedShiftAllLeftAndFillUpperFromUint32x16 [a] x y mask) => (VPSHLDDMasked512 [a] x y (VPMOVVec32x16ToM <types.TypeMask> mask))
+(MaskedShiftAllLeftAndFillUpperFromUint64x2 [a] x y mask) => (VPSHLDQMasked128 [a] x y (VPMOVVec64x2ToM <types.TypeMask> mask))
+(MaskedShiftAllLeftAndFillUpperFromUint64x4 [a] x y mask) => (VPSHLDQMasked256 [a] x y (VPMOVVec64x4ToM <types.TypeMask> mask))
+(MaskedShiftAllLeftAndFillUpperFromUint64x8 [a] x y mask) => (VPSHLDQMasked512 [a] x y (VPMOVVec64x8ToM <types.TypeMask> mask))
+(MaskedShiftAllRightInt64x2 x y mask) => (VPSRLQMasked128 x y (VPMOVVec64x2ToM <types.TypeMask> mask))
+(MaskedShiftAllRightInt64x4 x y mask) => (VPSRLQMasked256 x y (VPMOVVec64x4ToM <types.TypeMask> mask))
+(MaskedShiftAllRightInt64x8 x y mask) => (VPSRLQMasked512 x y (VPMOVVec64x8ToM <types.TypeMask> mask))
+(MaskedShiftAllRightUint64x2 x y mask) => (VPSRLQMasked128 x y (VPMOVVec64x2ToM <types.TypeMask> mask))
+(MaskedShiftAllRightUint64x4 x y mask) => (VPSRLQMasked256 x y (VPMOVVec64x4ToM <types.TypeMask> mask))
+(MaskedShiftAllRightUint64x8 x y mask) => (VPSRLQMasked512 x y (VPMOVVec64x8ToM <types.TypeMask> mask))
+(MaskedShiftAllRightAndFillUpperFromInt16x8 [a] x y mask) => (VPSHRDWMasked128 [a] x y (VPMOVVec16x8ToM <types.TypeMask> mask))
+(MaskedShiftAllRightAndFillUpperFromInt16x16 [a] x y mask) => (VPSHRDWMasked256 [a] x y (VPMOVVec16x16ToM <types.TypeMask> mask))
+(MaskedShiftAllRightAndFillUpperFromInt16x32 [a] x y mask) => (VPSHRDWMasked512 [a] x y (VPMOVVec16x32ToM <types.TypeMask> mask))
+(MaskedShiftAllRightAndFillUpperFromInt32x4 [a] x y mask) => (VPSHRDDMasked128 [a] x y (VPMOVVec32x4ToM <types.TypeMask> mask))
+(MaskedShiftAllRightAndFillUpperFromInt32x8 [a] x y mask) => (VPSHRDDMasked256 [a] x y (VPMOVVec32x8ToM <types.TypeMask> mask))
+(MaskedShiftAllRightAndFillUpperFromInt32x16 [a] x y mask) => (VPSHRDDMasked512 [a] x y (VPMOVVec32x16ToM <types.TypeMask> mask))
+(MaskedShiftAllRightAndFillUpperFromInt64x2 [a] x y mask) => (VPSHRDQMasked128 [a] x y (VPMOVVec64x2ToM <types.TypeMask> mask))
+(MaskedShiftAllRightAndFillUpperFromInt64x4 [a] x y mask) => (VPSHRDQMasked256 [a] x y (VPMOVVec64x4ToM <types.TypeMask> mask))
+(MaskedShiftAllRightAndFillUpperFromInt64x8 [a] x y mask) => (VPSHRDQMasked512 [a] x y (VPMOVVec64x8ToM <types.TypeMask> mask))
+(MaskedShiftAllRightAndFillUpperFromUint16x8 [a] x y mask) => (VPSHRDWMasked128 [a] x y (VPMOVVec16x8ToM <types.TypeMask> mask))
+(MaskedShiftAllRightAndFillUpperFromUint16x16 [a] x y mask) => (VPSHRDWMasked256 [a] x y (VPMOVVec16x16ToM <types.TypeMask> mask))
+(MaskedShiftAllRightAndFillUpperFromUint16x32 [a] x y mask) => (VPSHRDWMasked512 [a] x y (VPMOVVec16x32ToM <types.TypeMask> mask))
+(MaskedShiftAllRightAndFillUpperFromUint32x4 [a] x y mask) => (VPSHRDDMasked128 [a] x y (VPMOVVec32x4ToM <types.TypeMask> mask))
+(MaskedShiftAllRightAndFillUpperFromUint32x8 [a] x y mask) => (VPSHRDDMasked256 [a] x y (VPMOVVec32x8ToM <types.TypeMask> mask))
+(MaskedShiftAllRightAndFillUpperFromUint32x16 [a] x y mask) => (VPSHRDDMasked512 [a] x y (VPMOVVec32x16ToM <types.TypeMask> mask))
+(MaskedShiftAllRightAndFillUpperFromUint64x2 [a] x y mask) => (VPSHRDQMasked128 [a] x y (VPMOVVec64x2ToM <types.TypeMask> mask))
+(MaskedShiftAllRightAndFillUpperFromUint64x4 [a] x y mask) => (VPSHRDQMasked256 [a] x y (VPMOVVec64x4ToM <types.TypeMask> mask))
+(MaskedShiftAllRightAndFillUpperFromUint64x8 [a] x y mask) => (VPSHRDQMasked512 [a] x y (VPMOVVec64x8ToM <types.TypeMask> mask))
+(MaskedShiftAllRightSignExtendedInt64x2 x y mask) => (VPSRAQMasked128 x y (VPMOVVec64x2ToM <types.TypeMask> mask))
+(MaskedShiftAllRightSignExtendedInt64x4 x y mask) => (VPSRAQMasked256 x y (VPMOVVec64x4ToM <types.TypeMask> mask))
+(MaskedShiftAllRightSignExtendedInt64x8 x y mask) => (VPSRAQMasked512 x y (VPMOVVec64x8ToM <types.TypeMask> mask))
+(MaskedShiftLeftInt16x8 x y mask) => (VPSLLVWMasked128 x y (VPMOVVec16x8ToM <types.TypeMask> mask))
+(MaskedShiftLeftInt16x16 x y mask) => (VPSLLVWMasked256 x y (VPMOVVec16x16ToM <types.TypeMask> mask))
+(MaskedShiftLeftInt16x32 x y mask) => (VPSLLVWMasked512 x y (VPMOVVec16x32ToM <types.TypeMask> mask))
+(MaskedShiftLeftInt32x4 x y mask) => (VPSLLVDMasked128 x y (VPMOVVec32x4ToM <types.TypeMask> mask))
+(MaskedShiftLeftInt32x8 x y mask) => (VPSLLVDMasked256 x y (VPMOVVec32x8ToM <types.TypeMask> mask))
+(MaskedShiftLeftInt32x16 x y mask) => (VPSLLVDMasked512 x y (VPMOVVec32x16ToM <types.TypeMask> mask))
+(MaskedShiftLeftInt64x2 x y mask) => (VPSLLVQMasked128 x y (VPMOVVec64x2ToM <types.TypeMask> mask))
+(MaskedShiftLeftInt64x4 x y mask) => (VPSLLVQMasked256 x y (VPMOVVec64x4ToM <types.TypeMask> mask))
+(MaskedShiftLeftInt64x8 x y mask) => (VPSLLVQMasked512 x y (VPMOVVec64x8ToM <types.TypeMask> mask))
+(MaskedShiftLeftUint16x8 x y mask) => (VPSLLVWMasked128 x y (VPMOVVec16x8ToM <types.TypeMask> mask))
+(MaskedShiftLeftUint16x16 x y mask) => (VPSLLVWMasked256 x y (VPMOVVec16x16ToM <types.TypeMask> mask))
+(MaskedShiftLeftUint16x32 x y mask) => (VPSLLVWMasked512 x y (VPMOVVec16x32ToM <types.TypeMask> mask))
+(MaskedShiftLeftUint32x4 x y mask) => (VPSLLVDMasked128 x y (VPMOVVec32x4ToM <types.TypeMask> mask))
+(MaskedShiftLeftUint32x8 x y mask) => (VPSLLVDMasked256 x y (VPMOVVec32x8ToM <types.TypeMask> mask))
+(MaskedShiftLeftUint32x16 x y mask) => (VPSLLVDMasked512 x y (VPMOVVec32x16ToM <types.TypeMask> mask))
+(MaskedShiftLeftUint64x2 x y mask) => (VPSLLVQMasked128 x y (VPMOVVec64x2ToM <types.TypeMask> mask))
+(MaskedShiftLeftUint64x4 x y mask) => (VPSLLVQMasked256 x y (VPMOVVec64x4ToM <types.TypeMask> mask))
+(MaskedShiftLeftUint64x8 x y mask) => (VPSLLVQMasked512 x y (VPMOVVec64x8ToM <types.TypeMask> mask))
+(MaskedShiftLeftAndFillUpperFromInt16x8 x y z mask) => (VPSHLDVWMasked128 x y z (VPMOVVec16x8ToM <types.TypeMask> mask))
+(MaskedShiftLeftAndFillUpperFromInt16x16 x y z mask) => (VPSHLDVWMasked256 x y z (VPMOVVec16x16ToM <types.TypeMask> mask))
+(MaskedShiftLeftAndFillUpperFromInt16x32 x y z mask) => (VPSHLDVWMasked512 x y z (VPMOVVec16x32ToM <types.TypeMask> mask))
+(MaskedShiftLeftAndFillUpperFromInt32x4 x y z mask) => (VPSHLDVDMasked128 x y z (VPMOVVec32x4ToM <types.TypeMask> mask))
+(MaskedShiftLeftAndFillUpperFromInt32x8 x y z mask) => (VPSHLDVDMasked256 x y z (VPMOVVec32x8ToM <types.TypeMask> mask))
+(MaskedShiftLeftAndFillUpperFromInt32x16 x y z mask) => (VPSHLDVDMasked512 x y z (VPMOVVec32x16ToM <types.TypeMask> mask))
+(MaskedShiftLeftAndFillUpperFromInt64x2 x y z mask) => (VPSHLDVQMasked128 x y z (VPMOVVec64x2ToM <types.TypeMask> mask))
+(MaskedShiftLeftAndFillUpperFromInt64x4 x y z mask) => (VPSHLDVQMasked256 x y z (VPMOVVec64x4ToM <types.TypeMask> mask))
+(MaskedShiftLeftAndFillUpperFromInt64x8 x y z mask) => (VPSHLDVQMasked512 x y z (VPMOVVec64x8ToM <types.TypeMask> mask))
+(MaskedShiftLeftAndFillUpperFromUint16x8 x y z mask) => (VPSHLDVWMasked128 x y z (VPMOVVec16x8ToM <types.TypeMask> mask))
+(MaskedShiftLeftAndFillUpperFromUint16x16 x y z mask) => (VPSHLDVWMasked256 x y z (VPMOVVec16x16ToM <types.TypeMask> mask))
+(MaskedShiftLeftAndFillUpperFromUint16x32 x y z mask) => (VPSHLDVWMasked512 x y z (VPMOVVec16x32ToM <types.TypeMask> mask))
+(MaskedShiftLeftAndFillUpperFromUint32x4 x y z mask) => (VPSHLDVDMasked128 x y z (VPMOVVec32x4ToM <types.TypeMask> mask))
+(MaskedShiftLeftAndFillUpperFromUint32x8 x y z mask) => (VPSHLDVDMasked256 x y z (VPMOVVec32x8ToM <types.TypeMask> mask))
+(MaskedShiftLeftAndFillUpperFromUint32x16 x y z mask) => (VPSHLDVDMasked512 x y z (VPMOVVec32x16ToM <types.TypeMask> mask))
+(MaskedShiftLeftAndFillUpperFromUint64x2 x y z mask) => (VPSHLDVQMasked128 x y z (VPMOVVec64x2ToM <types.TypeMask> mask))
+(MaskedShiftLeftAndFillUpperFromUint64x4 x y z mask) => (VPSHLDVQMasked256 x y z (VPMOVVec64x4ToM <types.TypeMask> mask))
+(MaskedShiftLeftAndFillUpperFromUint64x8 x y z mask) => (VPSHLDVQMasked512 x y z (VPMOVVec64x8ToM <types.TypeMask> mask))
+(MaskedShiftRightInt16x8 x y mask) => (VPSRLVWMasked128 x y (VPMOVVec16x8ToM <types.TypeMask> mask))
+(MaskedShiftRightInt16x16 x y mask) => (VPSRLVWMasked256 x y (VPMOVVec16x16ToM <types.TypeMask> mask))
+(MaskedShiftRightInt16x32 x y mask) => (VPSRLVWMasked512 x y (VPMOVVec16x32ToM <types.TypeMask> mask))
+(MaskedShiftRightInt32x4 x y mask) => (VPSRLVDMasked128 x y (VPMOVVec32x4ToM <types.TypeMask> mask))
+(MaskedShiftRightInt32x8 x y mask) => (VPSRLVDMasked256 x y (VPMOVVec32x8ToM <types.TypeMask> mask))
+(MaskedShiftRightInt32x16 x y mask) => (VPSRLVDMasked512 x y (VPMOVVec32x16ToM <types.TypeMask> mask))
+(MaskedShiftRightInt64x2 x y mask) => (VPSRLVQMasked128 x y (VPMOVVec64x2ToM <types.TypeMask> mask))
+(MaskedShiftRightInt64x4 x y mask) => (VPSRLVQMasked256 x y (VPMOVVec64x4ToM <types.TypeMask> mask))
+(MaskedShiftRightInt64x8 x y mask) => (VPSRLVQMasked512 x y (VPMOVVec64x8ToM <types.TypeMask> mask))
+(MaskedShiftRightUint16x8 x y mask) => (VPSRLVWMasked128 x y (VPMOVVec16x8ToM <types.TypeMask> mask))
+(MaskedShiftRightUint16x16 x y mask) => (VPSRLVWMasked256 x y (VPMOVVec16x16ToM <types.TypeMask> mask))
+(MaskedShiftRightUint16x32 x y mask) => (VPSRLVWMasked512 x y (VPMOVVec16x32ToM <types.TypeMask> mask))
+(MaskedShiftRightUint32x4 x y mask) => (VPSRLVDMasked128 x y (VPMOVVec32x4ToM <types.TypeMask> mask))
+(MaskedShiftRightUint32x8 x y mask) => (VPSRLVDMasked256 x y (VPMOVVec32x8ToM <types.TypeMask> mask))
+(MaskedShiftRightUint32x16 x y mask) => (VPSRLVDMasked512 x y (VPMOVVec32x16ToM <types.TypeMask> mask))
+(MaskedShiftRightUint64x2 x y mask) => (VPSRLVQMasked128 x y (VPMOVVec64x2ToM <types.TypeMask> mask))
+(MaskedShiftRightUint64x4 x y mask) => (VPSRLVQMasked256 x y (VPMOVVec64x4ToM <types.TypeMask> mask))
+(MaskedShiftRightUint64x8 x y mask) => (VPSRLVQMasked512 x y (VPMOVVec64x8ToM <types.TypeMask> mask))
+(MaskedShiftRightAndFillUpperFromInt16x8 x y z mask) => (VPSHRDVWMasked128 x y z (VPMOVVec16x8ToM <types.TypeMask> mask))
+(MaskedShiftRightAndFillUpperFromInt16x16 x y z mask) => (VPSHRDVWMasked256 x y z (VPMOVVec16x16ToM <types.TypeMask> mask))
+(MaskedShiftRightAndFillUpperFromInt16x32 x y z mask) => (VPSHRDVWMasked512 x y z (VPMOVVec16x32ToM <types.TypeMask> mask))
+(MaskedShiftRightAndFillUpperFromInt32x4 x y z mask) => (VPSHRDVDMasked128 x y z (VPMOVVec32x4ToM <types.TypeMask> mask))
+(MaskedShiftRightAndFillUpperFromInt32x8 x y z mask) => (VPSHRDVDMasked256 x y z (VPMOVVec32x8ToM <types.TypeMask> mask))
+(MaskedShiftRightAndFillUpperFromInt32x16 x y z mask) => (VPSHRDVDMasked512 x y z (VPMOVVec32x16ToM <types.TypeMask> mask))
+(MaskedShiftRightAndFillUpperFromInt64x2 x y z mask) => (VPSHRDVQMasked128 x y z (VPMOVVec64x2ToM <types.TypeMask> mask))
+(MaskedShiftRightAndFillUpperFromInt64x4 x y z mask) => (VPSHRDVQMasked256 x y z (VPMOVVec64x4ToM <types.TypeMask> mask))
+(MaskedShiftRightAndFillUpperFromInt64x8 x y z mask) => (VPSHRDVQMasked512 x y z (VPMOVVec64x8ToM <types.TypeMask> mask))
+(MaskedShiftRightAndFillUpperFromUint16x8 x y z mask) => (VPSHRDVWMasked128 x y z (VPMOVVec16x8ToM <types.TypeMask> mask))
+(MaskedShiftRightAndFillUpperFromUint16x16 x y z mask) => (VPSHRDVWMasked256 x y z (VPMOVVec16x16ToM <types.TypeMask> mask))
+(MaskedShiftRightAndFillUpperFromUint16x32 x y z mask) => (VPSHRDVWMasked512 x y z (VPMOVVec16x32ToM <types.TypeMask> mask))
+(MaskedShiftRightAndFillUpperFromUint32x4 x y z mask) => (VPSHRDVDMasked128 x y z (VPMOVVec32x4ToM <types.TypeMask> mask))
+(MaskedShiftRightAndFillUpperFromUint32x8 x y z mask) => (VPSHRDVDMasked256 x y z (VPMOVVec32x8ToM <types.TypeMask> mask))
+(MaskedShiftRightAndFillUpperFromUint32x16 x y z mask) => (VPSHRDVDMasked512 x y z (VPMOVVec32x16ToM <types.TypeMask> mask))
+(MaskedShiftRightAndFillUpperFromUint64x2 x y z mask) => (VPSHRDVQMasked128 x y z (VPMOVVec64x2ToM <types.TypeMask> mask))
+(MaskedShiftRightAndFillUpperFromUint64x4 x y z mask) => (VPSHRDVQMasked256 x y z (VPMOVVec64x4ToM <types.TypeMask> mask))
+(MaskedShiftRightAndFillUpperFromUint64x8 x y z mask) => (VPSHRDVQMasked512 x y z (VPMOVVec64x8ToM <types.TypeMask> mask))
+(MaskedShiftRightSignExtendedInt16x8 x y mask) => (VPSRAVWMasked128 x y (VPMOVVec16x8ToM <types.TypeMask> mask))
+(MaskedShiftRightSignExtendedInt16x16 x y mask) => (VPSRAVWMasked256 x y (VPMOVVec16x16ToM <types.TypeMask> mask))
+(MaskedShiftRightSignExtendedInt16x32 x y mask) => (VPSRAVWMasked512 x y (VPMOVVec16x32ToM <types.TypeMask> mask))
+(MaskedShiftRightSignExtendedInt32x4 x y mask) => (VPSRAVDMasked128 x y (VPMOVVec32x4ToM <types.TypeMask> mask))
+(MaskedShiftRightSignExtendedInt32x8 x y mask) => (VPSRAVDMasked256 x y (VPMOVVec32x8ToM <types.TypeMask> mask))
+(MaskedShiftRightSignExtendedInt32x16 x y mask) => (VPSRAVDMasked512 x y (VPMOVVec32x16ToM <types.TypeMask> mask))
+(MaskedShiftRightSignExtendedInt64x2 x y mask) => (VPSRAVQMasked128 x y (VPMOVVec64x2ToM <types.TypeMask> mask))
+(MaskedShiftRightSignExtendedInt64x4 x y mask) => (VPSRAVQMasked256 x y (VPMOVVec64x4ToM <types.TypeMask> mask))
+(MaskedShiftRightSignExtendedInt64x8 x y mask) => (VPSRAVQMasked512 x y (VPMOVVec64x8ToM <types.TypeMask> mask))
+(MaskedShiftRightSignExtendedUint16x8 x y mask) => (VPSRAVWMasked128 x y (VPMOVVec16x8ToM <types.TypeMask> mask))
+(MaskedShiftRightSignExtendedUint16x16 x y mask) => (VPSRAVWMasked256 x y (VPMOVVec16x16ToM <types.TypeMask> mask))
+(MaskedShiftRightSignExtendedUint16x32 x y mask) => (VPSRAVWMasked512 x y (VPMOVVec16x32ToM <types.TypeMask> mask))
+(MaskedShiftRightSignExtendedUint32x4 x y mask) => (VPSRAVDMasked128 x y (VPMOVVec32x4ToM <types.TypeMask> mask))
+(MaskedShiftRightSignExtendedUint32x8 x y mask) => (VPSRAVDMasked256 x y (VPMOVVec32x8ToM <types.TypeMask> mask))
+(MaskedShiftRightSignExtendedUint32x16 x y mask) => (VPSRAVDMasked512 x y (VPMOVVec32x16ToM <types.TypeMask> mask))
+(MaskedShiftRightSignExtendedUint64x2 x y mask) => (VPSRAVQMasked128 x y (VPMOVVec64x2ToM <types.TypeMask> mask))
+(MaskedShiftRightSignExtendedUint64x4 x y mask) => (VPSRAVQMasked256 x y (VPMOVVec64x4ToM <types.TypeMask> mask))
+(MaskedShiftRightSignExtendedUint64x8 x y mask) => (VPSRAVQMasked512 x y (VPMOVVec64x8ToM <types.TypeMask> mask))
 (MaskedSqrtFloat32x4 x mask) => (VSQRTPSMasked128 x (VPMOVVec32x4ToM <types.TypeMask> mask))
 (MaskedSqrtFloat32x8 x mask) => (VSQRTPSMasked256 x (VPMOVVec32x8ToM <types.TypeMask> mask))
 (MaskedSqrtFloat32x16 x mask) => (VSQRTPSMasked512 x (VPMOVVec32x16ToM <types.TypeMask> mask))
@@ -1231,6 +1420,54 @@
 (PopCountUint64x2 ...) => (VPOPCNTQ128 ...)
 (PopCountUint64x4 ...) => (VPOPCNTQ256 ...)
 (PopCountUint64x8 ...) => (VPOPCNTQ512 ...)
+(RotateAllLeftInt32x4 [a] x) => (VPROLD128 [a] x)
+(RotateAllLeftInt32x8 [a] x) => (VPROLD256 [a] x)
+(RotateAllLeftInt32x16 [a] x) => (VPROLD512 [a] x)
+(RotateAllLeftInt64x2 [a] x) => (VPROLQ128 [a] x)
+(RotateAllLeftInt64x4 [a] x) => (VPROLQ256 [a] x)
+(RotateAllLeftInt64x8 [a] x) => (VPROLQ512 [a] x)
+(RotateAllLeftUint32x4 [a] x) => (VPROLD128 [a] x)
+(RotateAllLeftUint32x8 [a] x) => (VPROLD256 [a] x)
+(RotateAllLeftUint32x16 [a] x) => (VPROLD512 [a] x)
+(RotateAllLeftUint64x2 [a] x) => (VPROLQ128 [a] x)
+(RotateAllLeftUint64x4 [a] x) => (VPROLQ256 [a] x)
+(RotateAllLeftUint64x8 [a] x) => (VPROLQ512 [a] x)
+(RotateAllRightInt32x4 [a] x) => (VPRORD128 [a] x)
+(RotateAllRightInt32x8 [a] x) => (VPRORD256 [a] x)
+(RotateAllRightInt32x16 [a] x) => (VPRORD512 [a] x)
+(RotateAllRightInt64x2 [a] x) => (VPRORQ128 [a] x)
+(RotateAllRightInt64x4 [a] x) => (VPRORQ256 [a] x)
+(RotateAllRightInt64x8 [a] x) => (VPRORQ512 [a] x)
+(RotateAllRightUint32x4 [a] x) => (VPRORD128 [a] x)
+(RotateAllRightUint32x8 [a] x) => (VPRORD256 [a] x)
+(RotateAllRightUint32x16 [a] x) => (VPRORD512 [a] x)
+(RotateAllRightUint64x2 [a] x) => (VPRORQ128 [a] x)
+(RotateAllRightUint64x4 [a] x) => (VPRORQ256 [a] x)
+(RotateAllRightUint64x8 [a] x) => (VPRORQ512 [a] x)
+(RotateLeftInt32x4 ...) => (VPROLVD128 ...)
+(RotateLeftInt32x8 ...) => (VPROLVD256 ...)
+(RotateLeftInt32x16 ...) => (VPROLVD512 ...)
+(RotateLeftInt64x2 ...) => (VPROLVQ128 ...)
+(RotateLeftInt64x4 ...) => (VPROLVQ256 ...)
+(RotateLeftInt64x8 ...) => (VPROLVQ512 ...)
+(RotateLeftUint32x4 ...) => (VPROLVD128 ...)
+(RotateLeftUint32x8 ...) => (VPROLVD256 ...)
+(RotateLeftUint32x16 ...) => (VPROLVD512 ...)
+(RotateLeftUint64x2 ...) => (VPROLVQ128 ...)
+(RotateLeftUint64x4 ...) => (VPROLVQ256 ...)
+(RotateLeftUint64x8 ...) => (VPROLVQ512 ...)
+(RotateRightInt32x4 ...) => (VPRORVD128 ...)
+(RotateRightInt32x8 ...) => (VPRORVD256 ...)
+(RotateRightInt32x16 ...) => (VPRORVD512 ...)
+(RotateRightInt64x2 ...) => (VPRORVQ128 ...)
+(RotateRightInt64x4 ...) => (VPRORVQ256 ...)
+(RotateRightInt64x8 ...) => (VPRORVQ512 ...)
+(RotateRightUint32x4 ...) => (VPRORVD128 ...)
+(RotateRightUint32x8 ...) => (VPRORVD256 ...)
+(RotateRightUint32x16 ...) => (VPRORVD512 ...)
+(RotateRightUint64x2 ...) => (VPRORVQ128 ...)
+(RotateRightUint64x4 ...) => (VPRORVQ256 ...)
+(RotateRightUint64x8 ...) => (VPRORVQ512 ...)
 (RoundFloat32x4 x) => (VROUNDPS128 [0] x)
 (RoundFloat32x8 x) => (VROUNDPS256 [0] x)
 (RoundFloat64x2 x) => (VROUNDPD128 [0] x)
@@ -1295,6 +1532,167 @@
 (SetElemUint16x8 [a] x y) => (VPINSRW128 [a] x y)
 (SetElemUint32x4 [a] x y) => (VPINSRD128 [a] x y)
 (SetElemUint64x2 [a] x y) => (VPINSRQ128 [a] x y)
+(ShiftAllLeftInt16x8 ...) => (VPSLLW128 ...)
+(ShiftAllLeftInt16x16 ...) => (VPSLLW256 ...)
+(ShiftAllLeftInt32x4 ...) => (VPSLLD128 ...)
+(ShiftAllLeftInt32x8 ...) => (VPSLLD256 ...)
+(ShiftAllLeftInt64x2 ...) => (VPSLLQ128 ...)
+(ShiftAllLeftInt64x4 ...) => (VPSLLQ256 ...)
+(ShiftAllLeftInt64x8 ...) => (VPSLLQ512 ...)
+(ShiftAllLeftUint16x8 ...) => (VPSLLW128 ...)
+(ShiftAllLeftUint16x16 ...) => (VPSLLW256 ...)
+(ShiftAllLeftUint32x4 ...) => (VPSLLD128 ...)
+(ShiftAllLeftUint32x8 ...) => (VPSLLD256 ...)
+(ShiftAllLeftUint64x2 ...) => (VPSLLQ128 ...)
+(ShiftAllLeftUint64x4 ...) => (VPSLLQ256 ...)
+(ShiftAllLeftUint64x8 ...) => (VPSLLQ512 ...)
+(ShiftAllLeftAndFillUpperFromInt16x8 [a] x y) => (VPSHLDW128 [a] x y)
+(ShiftAllLeftAndFillUpperFromInt16x16 [a] x y) => (VPSHLDW256 [a] x y)
+(ShiftAllLeftAndFillUpperFromInt16x32 [a] x y) => (VPSHLDW512 [a] x y)
+(ShiftAllLeftAndFillUpperFromInt32x4 [a] x y) => (VPSHLDD128 [a] x y)
+(ShiftAllLeftAndFillUpperFromInt32x8 [a] x y) => (VPSHLDD256 [a] x y)
+(ShiftAllLeftAndFillUpperFromInt32x16 [a] x y) => (VPSHLDD512 [a] x y)
+(ShiftAllLeftAndFillUpperFromInt64x2 [a] x y) => (VPSHLDQ128 [a] x y)
+(ShiftAllLeftAndFillUpperFromInt64x4 [a] x y) => (VPSHLDQ256 [a] x y)
+(ShiftAllLeftAndFillUpperFromInt64x8 [a] x y) => (VPSHLDQ512 [a] x y)
+(ShiftAllLeftAndFillUpperFromUint16x8 [a] x y) => (VPSHLDW128 [a] x y)
+(ShiftAllLeftAndFillUpperFromUint16x16 [a] x y) => (VPSHLDW256 [a] x y)
+(ShiftAllLeftAndFillUpperFromUint16x32 [a] x y) => (VPSHLDW512 [a] x y)
+(ShiftAllLeftAndFillUpperFromUint32x4 [a] x y) => (VPSHLDD128 [a] x y)
+(ShiftAllLeftAndFillUpperFromUint32x8 [a] x y) => (VPSHLDD256 [a] x y)
+(ShiftAllLeftAndFillUpperFromUint32x16 [a] x y) => (VPSHLDD512 [a] x y)
+(ShiftAllLeftAndFillUpperFromUint64x2 [a] x y) => (VPSHLDQ128 [a] x y)
+(ShiftAllLeftAndFillUpperFromUint64x4 [a] x y) => (VPSHLDQ256 [a] x y)
+(ShiftAllLeftAndFillUpperFromUint64x8 [a] x y) => (VPSHLDQ512 [a] x y)
+(ShiftAllRightInt16x8 ...) => (VPSRLW128 ...)
+(ShiftAllRightInt16x16 ...) => (VPSRLW256 ...)
+(ShiftAllRightInt32x4 ...) => (VPSRLD128 ...)
+(ShiftAllRightInt32x8 ...) => (VPSRLD256 ...)
+(ShiftAllRightInt64x2 ...) => (VPSRLQ128 ...)
+(ShiftAllRightInt64x4 ...) => (VPSRLQ256 ...)
+(ShiftAllRightInt64x8 ...) => (VPSRLQ512 ...)
+(ShiftAllRightUint16x8 ...) => (VPSRLW128 ...)
+(ShiftAllRightUint16x16 ...) => (VPSRLW256 ...)
+(ShiftAllRightUint32x4 ...) => (VPSRLD128 ...)
+(ShiftAllRightUint32x8 ...) => (VPSRLD256 ...)
+(ShiftAllRightUint64x2 ...) => (VPSRLQ128 ...)
+(ShiftAllRightUint64x4 ...) => (VPSRLQ256 ...)
+(ShiftAllRightUint64x8 ...) => (VPSRLQ512 ...)
+(ShiftAllRightAndFillUpperFromInt16x8 [a] x y) => (VPSHRDW128 [a] x y)
+(ShiftAllRightAndFillUpperFromInt16x16 [a] x y) => (VPSHRDW256 [a] x y)
+(ShiftAllRightAndFillUpperFromInt16x32 [a] x y) => (VPSHRDW512 [a] x y)
+(ShiftAllRightAndFillUpperFromInt32x4 [a] x y) => (VPSHRDD128 [a] x y)
+(ShiftAllRightAndFillUpperFromInt32x8 [a] x y) => (VPSHRDD256 [a] x y)
+(ShiftAllRightAndFillUpperFromInt32x16 [a] x y) => (VPSHRDD512 [a] x y)
+(ShiftAllRightAndFillUpperFromInt64x2 [a] x y) => (VPSHRDQ128 [a] x y)
+(ShiftAllRightAndFillUpperFromInt64x4 [a] x y) => (VPSHRDQ256 [a] x y)
+(ShiftAllRightAndFillUpperFromInt64x8 [a] x y) => (VPSHRDQ512 [a] x y)
+(ShiftAllRightAndFillUpperFromUint16x8 [a] x y) => (VPSHRDW128 [a] x y)
+(ShiftAllRightAndFillUpperFromUint16x16 [a] x y) => (VPSHRDW256 [a] x y)
+(ShiftAllRightAndFillUpperFromUint16x32 [a] x y) => (VPSHRDW512 [a] x y)
+(ShiftAllRightAndFillUpperFromUint32x4 [a] x y) => (VPSHRDD128 [a] x y)
+(ShiftAllRightAndFillUpperFromUint32x8 [a] x y) => (VPSHRDD256 [a] x y)
+(ShiftAllRightAndFillUpperFromUint32x16 [a] x y) => (VPSHRDD512 [a] x y)
+(ShiftAllRightAndFillUpperFromUint64x2 [a] x y) => (VPSHRDQ128 [a] x y)
+(ShiftAllRightAndFillUpperFromUint64x4 [a] x y) => (VPSHRDQ256 [a] x y)
+(ShiftAllRightAndFillUpperFromUint64x8 [a] x y) => (VPSHRDQ512 [a] x y)
+(ShiftAllRightSignExtendedInt16x8 ...) => (VPSRAW128 ...)
+(ShiftAllRightSignExtendedInt16x16 ...) => (VPSRAW256 ...)
+(ShiftAllRightSignExtendedInt32x4 ...) => (VPSRAD128 ...)
+(ShiftAllRightSignExtendedInt32x8 ...) => (VPSRAD256 ...)
+(ShiftAllRightSignExtendedInt64x2 ...) => (VPSRAQ128 ...)
+(ShiftAllRightSignExtendedInt64x4 ...) => (VPSRAQ256 ...)
+(ShiftAllRightSignExtendedInt64x8 ...) => (VPSRAQ512 ...)
+(ShiftLeftInt16x8 ...) => (VPSLLVW128 ...)
+(ShiftLeftInt16x16 ...) => (VPSLLVW256 ...)
+(ShiftLeftInt16x32 ...) => (VPSLLVW512 ...)
+(ShiftLeftInt32x4 ...) => (VPSLLVD128 ...)
+(ShiftLeftInt32x8 ...) => (VPSLLVD256 ...)
+(ShiftLeftInt32x16 ...) => (VPSLLVD512 ...)
+(ShiftLeftInt64x2 ...) => (VPSLLVQ128 ...)
+(ShiftLeftInt64x4 ...) => (VPSLLVQ256 ...)
+(ShiftLeftInt64x8 ...) => (VPSLLVQ512 ...)
+(ShiftLeftUint16x8 ...) => (VPSLLVW128 ...)
+(ShiftLeftUint16x16 ...) => (VPSLLVW256 ...)
+(ShiftLeftUint16x32 ...) => (VPSLLVW512 ...)
+(ShiftLeftUint32x4 ...) => (VPSLLVD128 ...)
+(ShiftLeftUint32x8 ...) => (VPSLLVD256 ...)
+(ShiftLeftUint32x16 ...) => (VPSLLVD512 ...)
+(ShiftLeftUint64x2 ...) => (VPSLLVQ128 ...)
+(ShiftLeftUint64x4 ...) => (VPSLLVQ256 ...)
+(ShiftLeftUint64x8 ...) => (VPSLLVQ512 ...)
+(ShiftLeftAndFillUpperFromInt16x8 ...) => (VPSHLDVW128 ...)
+(ShiftLeftAndFillUpperFromInt16x16 ...) => (VPSHLDVW256 ...)
+(ShiftLeftAndFillUpperFromInt16x32 ...) => (VPSHLDVW512 ...)
+(ShiftLeftAndFillUpperFromInt32x4 ...) => (VPSHLDVD128 ...)
+(ShiftLeftAndFillUpperFromInt32x8 ...) => (VPSHLDVD256 ...)
+(ShiftLeftAndFillUpperFromInt32x16 ...) => (VPSHLDVD512 ...)
+(ShiftLeftAndFillUpperFromInt64x2 ...) => (VPSHLDVQ128 ...)
+(ShiftLeftAndFillUpperFromInt64x4 ...) => (VPSHLDVQ256 ...)
+(ShiftLeftAndFillUpperFromInt64x8 ...) => (VPSHLDVQ512 ...)
+(ShiftLeftAndFillUpperFromUint16x8 ...) => (VPSHLDVW128 ...)
+(ShiftLeftAndFillUpperFromUint16x16 ...) => (VPSHLDVW256 ...)
+(ShiftLeftAndFillUpperFromUint16x32 ...) => (VPSHLDVW512 ...)
+(ShiftLeftAndFillUpperFromUint32x4 ...) => (VPSHLDVD128 ...)
+(ShiftLeftAndFillUpperFromUint32x8 ...) => (VPSHLDVD256 ...)
+(ShiftLeftAndFillUpperFromUint32x16 ...) => (VPSHLDVD512 ...)
+(ShiftLeftAndFillUpperFromUint64x2 ...) => (VPSHLDVQ128 ...)
+(ShiftLeftAndFillUpperFromUint64x4 ...) => (VPSHLDVQ256 ...)
+(ShiftLeftAndFillUpperFromUint64x8 ...) => (VPSHLDVQ512 ...)
+(ShiftRightInt16x8 ...) => (VPSRLVW128 ...)
+(ShiftRightInt16x16 ...) => (VPSRLVW256 ...)
+(ShiftRightInt16x32 ...) => (VPSRLVW512 ...)
+(ShiftRightInt32x4 ...) => (VPSRLVD128 ...)
+(ShiftRightInt32x8 ...) => (VPSRLVD256 ...)
+(ShiftRightInt32x16 ...) => (VPSRLVD512 ...)
+(ShiftRightInt64x2 ...) => (VPSRLVQ128 ...)
+(ShiftRightInt64x4 ...) => (VPSRLVQ256 ...)
+(ShiftRightInt64x8 ...) => (VPSRLVQ512 ...)
+(ShiftRightUint16x8 ...) => (VPSRLVW128 ...)
+(ShiftRightUint16x16 ...) => (VPSRLVW256 ...)
+(ShiftRightUint16x32 ...) => (VPSRLVW512 ...)
+(ShiftRightUint32x4 ...) => (VPSRLVD128 ...)
+(ShiftRightUint32x8 ...) => (VPSRLVD256 ...)
+(ShiftRightUint32x16 ...) => (VPSRLVD512 ...)
+(ShiftRightUint64x2 ...) => (VPSRLVQ128 ...)
+(ShiftRightUint64x4 ...) => (VPSRLVQ256 ...)
+(ShiftRightUint64x8 ...) => (VPSRLVQ512 ...)
+(ShiftRightAndFillUpperFromInt16x8 ...) => (VPSHRDVW128 ...)
+(ShiftRightAndFillUpperFromInt16x16 ...) => (VPSHRDVW256 ...)
+(ShiftRightAndFillUpperFromInt16x32 ...) => (VPSHRDVW512 ...)
+(ShiftRightAndFillUpperFromInt32x4 ...) => (VPSHRDVD128 ...)
+(ShiftRightAndFillUpperFromInt32x8 ...) => (VPSHRDVD256 ...)
+(ShiftRightAndFillUpperFromInt32x16 ...) => (VPSHRDVD512 ...)
+(ShiftRightAndFillUpperFromInt64x2 ...) => (VPSHRDVQ128 ...)
+(ShiftRightAndFillUpperFromInt64x4 ...) => (VPSHRDVQ256 ...)
+(ShiftRightAndFillUpperFromInt64x8 ...) => (VPSHRDVQ512 ...)
+(ShiftRightAndFillUpperFromUint16x8 ...) => (VPSHRDVW128 ...)
+(ShiftRightAndFillUpperFromUint16x16 ...) => (VPSHRDVW256 ...)
+(ShiftRightAndFillUpperFromUint16x32 ...) => (VPSHRDVW512 ...)
+(ShiftRightAndFillUpperFromUint32x4 ...) => (VPSHRDVD128 ...)
+(ShiftRightAndFillUpperFromUint32x8 ...) => (VPSHRDVD256 ...)
+(ShiftRightAndFillUpperFromUint32x16 ...) => (VPSHRDVD512 ...)
+(ShiftRightAndFillUpperFromUint64x2 ...) => (VPSHRDVQ128 ...)
+(ShiftRightAndFillUpperFromUint64x4 ...) => (VPSHRDVQ256 ...)
+(ShiftRightAndFillUpperFromUint64x8 ...) => (VPSHRDVQ512 ...)
+(ShiftRightSignExtendedInt16x8 ...) => (VPSRAVW128 ...)
+(ShiftRightSignExtendedInt16x16 ...) => (VPSRAVW256 ...)
+(ShiftRightSignExtendedInt16x32 ...) => (VPSRAVW512 ...)
+(ShiftRightSignExtendedInt32x4 ...) => (VPSRAVD128 ...)
+(ShiftRightSignExtendedInt32x8 ...) => (VPSRAVD256 ...)
+(ShiftRightSignExtendedInt32x16 ...) => (VPSRAVD512 ...)
+(ShiftRightSignExtendedInt64x2 ...) => (VPSRAVQ128 ...)
+(ShiftRightSignExtendedInt64x4 ...) => (VPSRAVQ256 ...)
+(ShiftRightSignExtendedInt64x8 ...) => (VPSRAVQ512 ...)
+(ShiftRightSignExtendedUint16x8 ...) => (VPSRAVW128 ...)
+(ShiftRightSignExtendedUint16x16 ...) => (VPSRAVW256 ...)
+(ShiftRightSignExtendedUint16x32 ...) => (VPSRAVW512 ...)
+(ShiftRightSignExtendedUint32x4 ...) => (VPSRAVD128 ...)
+(ShiftRightSignExtendedUint32x8 ...) => (VPSRAVD256 ...)
+(ShiftRightSignExtendedUint32x16 ...) => (VPSRAVD512 ...)
+(ShiftRightSignExtendedUint64x2 ...) => (VPSRAVQ128 ...)
+(ShiftRightSignExtendedUint64x4 ...) => (VPSRAVQ256 ...)
+(ShiftRightSignExtendedUint64x8 ...) => (VPSRAVQ512 ...)
 (SignInt8x16 ...) => (VPSIGNB128 ...)
 (SignInt8x32 ...) => (VPSIGNB256 ...)
 (SignInt16x8 ...) => (VPSIGNW128 ...)

diff --git a/src/cmd/compile/internal/ssa/_gen/simdAMD64ops.go b/src/cmd/compile/internal/ssa/_gen/simdAMD64ops.go
index 93b136230d077868b3fd713693036fac6168513c..cbddbe0ff6ef7d51fe79f011d57eabaefdf479eb 100644 (file)
--- a/src/cmd/compile/internal/ssa/_gen/simdAMD64ops.go
+++ b/src/cmd/compile/internal/ssa/_gen/simdAMD64ops.go
@@ -233,6 +233,11 @@ func simdAMD64Ops(fp11, fp21, fp2k, fpkfp, fp2kfp, fp2kk, fp31, fp3kfp, fpgpfp,
                {name: "VPOPCNTWMasked256", argLength: 2, reg: fpkfp, asm: "VPOPCNTW", commutative: false, typ: "Vec256", resultInArg0: false},
                {name: "VPADDSWMasked256", argLength: 3, reg: fp2kfp, asm: "VPADDSW", commutative: true, typ: "Vec256", resultInArg0: false},
                {name: "VPSUBSWMasked256", argLength: 3, reg: fp2kfp, asm: "VPSUBSW", commutative: false, typ: "Vec256", resultInArg0: false},
+               {name: "VPSLLVWMasked256", argLength: 3, reg: fp2kfp, asm: "VPSLLVW", commutative: false, typ: "Vec256", resultInArg0: false},
+               {name: "VPSHLDVWMasked256", argLength: 4, reg: fp3kfp, asm: "VPSHLDVW", commutative: false, typ: "Vec256", resultInArg0: true},
+               {name: "VPSRLVWMasked256", argLength: 3, reg: fp2kfp, asm: "VPSRLVW", commutative: false, typ: "Vec256", resultInArg0: false},
+               {name: "VPSHRDVWMasked256", argLength: 4, reg: fp3kfp, asm: "VPSHRDVW", commutative: false, typ: "Vec256", resultInArg0: true},
+               {name: "VPSRAVWMasked256", argLength: 3, reg: fp2kfp, asm: "VPSRAVW", commutative: false, typ: "Vec256", resultInArg0: false},
                {name: "VPSUBWMasked256", argLength: 3, reg: fp2kfp, asm: "VPSUBW", commutative: false, typ: "Vec256", resultInArg0: false},
                {name: "VPMAXSW256", argLength: 2, reg: fp21, asm: "VPMAXSW", commutative: true, typ: "Vec256", resultInArg0: false},
                {name: "VPMINSW256", argLength: 2, reg: fp21, asm: "VPMINSW", commutative: true, typ: "Vec256", resultInArg0: false},
@@ -246,6 +251,14 @@ func simdAMD64Ops(fp11, fp21, fp2k, fpkfp, fp2kfp, fp2kk, fp31, fp3kfp, fpgpfp,
                {name: "VPHADDSW256", argLength: 2, reg: fp21, asm: "VPHADDSW", commutative: false, typ: "Vec256", resultInArg0: false},
                {name: "VPHSUBSW256", argLength: 2, reg: fp21, asm: "VPHSUBSW", commutative: false, typ: "Vec256", resultInArg0: false},
                {name: "VPSUBSW256", argLength: 2, reg: fp21, asm: "VPSUBSW", commutative: false, typ: "Vec256", resultInArg0: false},
+               {name: "VPSLLW256", argLength: 2, reg: fp21, asm: "VPSLLW", commutative: false, typ: "Vec256", resultInArg0: false},
+               {name: "VPSRLW256", argLength: 2, reg: fp21, asm: "VPSRLW", commutative: false, typ: "Vec256", resultInArg0: false},
+               {name: "VPSRAW256", argLength: 2, reg: fp21, asm: "VPSRAW", commutative: false, typ: "Vec256", resultInArg0: false},
+               {name: "VPSLLVW256", argLength: 2, reg: fp21, asm: "VPSLLVW", commutative: false, typ: "Vec256", resultInArg0: false},
+               {name: "VPSHLDVW256", argLength: 3, reg: fp31, asm: "VPSHLDVW", commutative: false, typ: "Vec256", resultInArg0: true},
+               {name: "VPSRLVW256", argLength: 2, reg: fp21, asm: "VPSRLVW", commutative: false, typ: "Vec256", resultInArg0: false},
+               {name: "VPSHRDVW256", argLength: 3, reg: fp31, asm: "VPSHRDVW", commutative: false, typ: "Vec256", resultInArg0: true},
+               {name: "VPSRAVW256", argLength: 2, reg: fp21, asm: "VPSRAVW", commutative: false, typ: "Vec256", resultInArg0: false},
                {name: "VPSIGNW256", argLength: 2, reg: fp21, asm: "VPSIGNW", commutative: false, typ: "Vec256", resultInArg0: false},
                {name: "VPSUBW256", argLength: 2, reg: fp21, asm: "VPSUBW", commutative: false, typ: "Vec256", resultInArg0: false},
                {name: "VPABSW512", argLength: 1, reg: fp11, asm: "VPABSW", commutative: false, typ: "Vec512", resultInArg0: false},
@@ -260,6 +273,11 @@ func simdAMD64Ops(fp11, fp21, fp2k, fpkfp, fp2kfp, fp2kk, fp31, fp3kfp, fpgpfp,
                {name: "VPOPCNTWMasked512", argLength: 2, reg: fpkfp, asm: "VPOPCNTW", commutative: false, typ: "Vec512", resultInArg0: false},
                {name: "VPADDSWMasked512", argLength: 3, reg: fp2kfp, asm: "VPADDSW", commutative: true, typ: "Vec512", resultInArg0: false},
                {name: "VPSUBSWMasked512", argLength: 3, reg: fp2kfp, asm: "VPSUBSW", commutative: false, typ: "Vec512", resultInArg0: false},
+               {name: "VPSLLVWMasked512", argLength: 3, reg: fp2kfp, asm: "VPSLLVW", commutative: false, typ: "Vec512", resultInArg0: false},
+               {name: "VPSHLDVWMasked512", argLength: 4, reg: fp3kfp, asm: "VPSHLDVW", commutative: false, typ: "Vec512", resultInArg0: true},
+               {name: "VPSRLVWMasked512", argLength: 3, reg: fp2kfp, asm: "VPSRLVW", commutative: false, typ: "Vec512", resultInArg0: false},
+               {name: "VPSHRDVWMasked512", argLength: 4, reg: fp3kfp, asm: "VPSHRDVW", commutative: false, typ: "Vec512", resultInArg0: true},
+               {name: "VPSRAVWMasked512", argLength: 3, reg: fp2kfp, asm: "VPSRAVW", commutative: false, typ: "Vec512", resultInArg0: false},
                {name: "VPSUBWMasked512", argLength: 3, reg: fp2kfp, asm: "VPSUBW", commutative: false, typ: "Vec512", resultInArg0: false},
                {name: "VPMAXSW512", argLength: 2, reg: fp21, asm: "VPMAXSW", commutative: true, typ: "Vec512", resultInArg0: false},
                {name: "VPMINSW512", argLength: 2, reg: fp21, asm: "VPMINSW", commutative: true, typ: "Vec512", resultInArg0: false},
@@ -269,6 +287,11 @@ func simdAMD64Ops(fp11, fp21, fp2k, fpkfp, fp2kfp, fp2kk, fp31, fp3kfp, fpgpfp,
                {name: "VPOPCNTW512", argLength: 1, reg: fp11, asm: "VPOPCNTW", commutative: false, typ: "Vec512", resultInArg0: false},
                {name: "VPADDSW512", argLength: 2, reg: fp21, asm: "VPADDSW", commutative: true, typ: "Vec512", resultInArg0: false},
                {name: "VPSUBSW512", argLength: 2, reg: fp21, asm: "VPSUBSW", commutative: false, typ: "Vec512", resultInArg0: false},
+               {name: "VPSLLVW512", argLength: 2, reg: fp21, asm: "VPSLLVW", commutative: false, typ: "Vec512", resultInArg0: false},
+               {name: "VPSHLDVW512", argLength: 3, reg: fp31, asm: "VPSHLDVW", commutative: false, typ: "Vec512", resultInArg0: true},
+               {name: "VPSRLVW512", argLength: 2, reg: fp21, asm: "VPSRLVW", commutative: false, typ: "Vec512", resultInArg0: false},
+               {name: "VPSHRDVW512", argLength: 3, reg: fp31, asm: "VPSHRDVW", commutative: false, typ: "Vec512", resultInArg0: true},
+               {name: "VPSRAVW512", argLength: 2, reg: fp21, asm: "VPSRAVW", commutative: false, typ: "Vec512", resultInArg0: false},
                {name: "VPSUBW512", argLength: 2, reg: fp21, asm: "VPSUBW", commutative: false, typ: "Vec512", resultInArg0: false},
                {name: "VPABSW128", argLength: 1, reg: fp11, asm: "VPABSW", commutative: false, typ: "Vec128", resultInArg0: false},
                {name: "VPADDW128", argLength: 2, reg: fp21, asm: "VPADDW", commutative: true, typ: "Vec128", resultInArg0: false},
@@ -284,6 +307,11 @@ func simdAMD64Ops(fp11, fp21, fp2k, fpkfp, fp2kfp, fp2kk, fp31, fp3kfp, fpgpfp,
                {name: "VPOPCNTWMasked128", argLength: 2, reg: fpkfp, asm: "VPOPCNTW", commutative: false, typ: "Vec128", resultInArg0: false},
                {name: "VPADDSWMasked128", argLength: 3, reg: fp2kfp, asm: "VPADDSW", commutative: true, typ: "Vec128", resultInArg0: false},
                {name: "VPSUBSWMasked128", argLength: 3, reg: fp2kfp, asm: "VPSUBSW", commutative: false, typ: "Vec128", resultInArg0: false},
+               {name: "VPSLLVWMasked128", argLength: 3, reg: fp2kfp, asm: "VPSLLVW", commutative: false, typ: "Vec128", resultInArg0: false},
+               {name: "VPSHLDVWMasked128", argLength: 4, reg: fp3kfp, asm: "VPSHLDVW", commutative: false, typ: "Vec128", resultInArg0: true},
+               {name: "VPSRLVWMasked128", argLength: 3, reg: fp2kfp, asm: "VPSRLVW", commutative: false, typ: "Vec128", resultInArg0: false},
+               {name: "VPSHRDVWMasked128", argLength: 4, reg: fp3kfp, asm: "VPSHRDVW", commutative: false, typ: "Vec128", resultInArg0: true},
+               {name: "VPSRAVWMasked128", argLength: 3, reg: fp2kfp, asm: "VPSRAVW", commutative: false, typ: "Vec128", resultInArg0: false},
                {name: "VPSUBWMasked128", argLength: 3, reg: fp2kfp, asm: "VPSUBW", commutative: false, typ: "Vec128", resultInArg0: false},
                {name: "VPMAXSW128", argLength: 2, reg: fp21, asm: "VPMAXSW", commutative: true, typ: "Vec128", resultInArg0: false},
                {name: "VPMINSW128", argLength: 2, reg: fp21, asm: "VPMINSW", commutative: true, typ: "Vec128", resultInArg0: false},
@@ -297,6 +325,14 @@ func simdAMD64Ops(fp11, fp21, fp2k, fpkfp, fp2kfp, fp2kk, fp31, fp3kfp, fpgpfp,
                {name: "VPHADDSW128", argLength: 2, reg: fp21, asm: "VPHADDSW", commutative: false, typ: "Vec128", resultInArg0: false},
                {name: "VPHSUBSW128", argLength: 2, reg: fp21, asm: "VPHSUBSW", commutative: false, typ: "Vec128", resultInArg0: false},
                {name: "VPSUBSW128", argLength: 2, reg: fp21, asm: "VPSUBSW", commutative: false, typ: "Vec128", resultInArg0: false},
+               {name: "VPSLLW128", argLength: 2, reg: fp21, asm: "VPSLLW", commutative: false, typ: "Vec128", resultInArg0: false},
+               {name: "VPSRLW128", argLength: 2, reg: fp21, asm: "VPSRLW", commutative: false, typ: "Vec128", resultInArg0: false},
+               {name: "VPSRAW128", argLength: 2, reg: fp21, asm: "VPSRAW", commutative: false, typ: "Vec128", resultInArg0: false},
+               {name: "VPSLLVW128", argLength: 2, reg: fp21, asm: "VPSLLVW", commutative: false, typ: "Vec128", resultInArg0: false},
+               {name: "VPSHLDVW128", argLength: 3, reg: fp31, asm: "VPSHLDVW", commutative: false, typ: "Vec128", resultInArg0: true},
+               {name: "VPSRLVW128", argLength: 2, reg: fp21, asm: "VPSRLVW", commutative: false, typ: "Vec128", resultInArg0: false},
+               {name: "VPSHRDVW128", argLength: 3, reg: fp31, asm: "VPSHRDVW", commutative: false, typ: "Vec128", resultInArg0: true},
+               {name: "VPSRAVW128", argLength: 2, reg: fp21, asm: "VPSRAVW", commutative: false, typ: "Vec128", resultInArg0: false},
                {name: "VPSIGNW128", argLength: 2, reg: fp21, asm: "VPSIGNW", commutative: false, typ: "Vec128", resultInArg0: false},
                {name: "VPSUBW128", argLength: 2, reg: fp21, asm: "VPSUBW", commutative: false, typ: "Vec128", resultInArg0: false},
                {name: "VPABSD512", argLength: 1, reg: fp11, asm: "VPABSD", commutative: false, typ: "Vec512", resultInArg0: false},
@@ -313,8 +349,15 @@ func simdAMD64Ops(fp11, fp21, fp2k, fpkfp, fp2kfp, fp2kk, fp31, fp3kfp, fpgpfp,
                {name: "VPORDMasked512", argLength: 3, reg: fp2kfp, asm: "VPORD", commutative: true, typ: "Vec512", resultInArg0: false},
                {name: "VPDPWSSDMasked512", argLength: 4, reg: fp3kfp, asm: "VPDPWSSD", commutative: false, typ: "Vec512", resultInArg0: true},
                {name: "VPOPCNTDMasked512", argLength: 2, reg: fpkfp, asm: "VPOPCNTD", commutative: false, typ: "Vec512", resultInArg0: false},
+               {name: "VPROLVDMasked512", argLength: 3, reg: fp2kfp, asm: "VPROLVD", commutative: false, typ: "Vec512", resultInArg0: false},
+               {name: "VPRORVDMasked512", argLength: 3, reg: fp2kfp, asm: "VPRORVD", commutative: false, typ: "Vec512", resultInArg0: false},
                {name: "VPDPWSSDSMasked512", argLength: 4, reg: fp3kfp, asm: "VPDPWSSDS", commutative: false, typ: "Vec512", resultInArg0: true},
                {name: "VPDPBUSDSMasked512", argLength: 4, reg: fp3kfp, asm: "VPDPBUSDS", commutative: false, typ: "Vec512", resultInArg0: true},
+               {name: "VPSLLVDMasked512", argLength: 3, reg: fp2kfp, asm: "VPSLLVD", commutative: false, typ: "Vec512", resultInArg0: false},
+               {name: "VPSHLDVDMasked512", argLength: 4, reg: fp3kfp, asm: "VPSHLDVD", commutative: false, typ: "Vec512", resultInArg0: true},
+               {name: "VPSRLVDMasked512", argLength: 3, reg: fp2kfp, asm: "VPSRLVD", commutative: false, typ: "Vec512", resultInArg0: false},
+               {name: "VPSHRDVDMasked512", argLength: 4, reg: fp3kfp, asm: "VPSHRDVD", commutative: false, typ: "Vec512", resultInArg0: true},
+               {name: "VPSRAVDMasked512", argLength: 3, reg: fp2kfp, asm: "VPSRAVD", commutative: false, typ: "Vec512", resultInArg0: false},
                {name: "VPSUBDMasked512", argLength: 3, reg: fp2kfp, asm: "VPSUBD", commutative: false, typ: "Vec512", resultInArg0: false},
                {name: "VPDPBUSDMasked512", argLength: 4, reg: fp3kfp, asm: "VPDPBUSD", commutative: false, typ: "Vec512", resultInArg0: true},
                {name: "VPXORDMasked512", argLength: 3, reg: fp2kfp, asm: "VPXORD", commutative: true, typ: "Vec512", resultInArg0: false},
@@ -324,8 +367,15 @@ func simdAMD64Ops(fp11, fp21, fp2k, fpkfp, fp2kfp, fp2kk, fp31, fp3kfp, fpgpfp,
                {name: "VPORD512", argLength: 2, reg: fp21, asm: "VPORD", commutative: true, typ: "Vec512", resultInArg0: false},
                {name: "VPDPWSSD512", argLength: 3, reg: fp31, asm: "VPDPWSSD", commutative: false, typ: "Vec512", resultInArg0: true},
                {name: "VPOPCNTD512", argLength: 1, reg: fp11, asm: "VPOPCNTD", commutative: false, typ: "Vec512", resultInArg0: false},
+               {name: "VPROLVD512", argLength: 2, reg: fp21, asm: "VPROLVD", commutative: false, typ: "Vec512", resultInArg0: false},
+               {name: "VPRORVD512", argLength: 2, reg: fp21, asm: "VPRORVD", commutative: false, typ: "Vec512", resultInArg0: false},
                {name: "VPDPWSSDS512", argLength: 3, reg: fp31, asm: "VPDPWSSDS", commutative: false, typ: "Vec512", resultInArg0: true},
                {name: "VPDPBUSDS512", argLength: 3, reg: fp31, asm: "VPDPBUSDS", commutative: false, typ: "Vec512", resultInArg0: true},
+               {name: "VPSLLVD512", argLength: 2, reg: fp21, asm: "VPSLLVD", commutative: false, typ: "Vec512", resultInArg0: false},
+               {name: "VPSHLDVD512", argLength: 3, reg: fp31, asm: "VPSHLDVD", commutative: false, typ: "Vec512", resultInArg0: true},
+               {name: "VPSRLVD512", argLength: 2, reg: fp21, asm: "VPSRLVD", commutative: false, typ: "Vec512", resultInArg0: false},
+               {name: "VPSHRDVD512", argLength: 3, reg: fp31, asm: "VPSHRDVD", commutative: false, typ: "Vec512", resultInArg0: true},
+               {name: "VPSRAVD512", argLength: 2, reg: fp21, asm: "VPSRAVD", commutative: false, typ: "Vec512", resultInArg0: false},
                {name: "VPSUBD512", argLength: 2, reg: fp21, asm: "VPSUBD", commutative: false, typ: "Vec512", resultInArg0: false},
                {name: "VPDPBUSD512", argLength: 3, reg: fp31, asm: "VPDPBUSD", commutative: false, typ: "Vec512", resultInArg0: true},
                {name: "VPXORD512", argLength: 2, reg: fp21, asm: "VPXORD", commutative: true, typ: "Vec512", resultInArg0: false},
@@ -343,8 +393,15 @@ func simdAMD64Ops(fp11, fp21, fp2k, fpkfp, fp2kfp, fp2kk, fp31, fp3kfp, fpgpfp,
                {name: "VPORDMasked128", argLength: 3, reg: fp2kfp, asm: "VPORD", commutative: true, typ: "Vec128", resultInArg0: false},
                {name: "VPDPWSSDMasked128", argLength: 4, reg: fp3kfp, asm: "VPDPWSSD", commutative: false, typ: "Vec128", resultInArg0: true},
                {name: "VPOPCNTDMasked128", argLength: 2, reg: fpkfp, asm: "VPOPCNTD", commutative: false, typ: "Vec128", resultInArg0: false},
+               {name: "VPROLVDMasked128", argLength: 3, reg: fp2kfp, asm: "VPROLVD", commutative: false, typ: "Vec128", resultInArg0: false},
+               {name: "VPRORVDMasked128", argLength: 3, reg: fp2kfp, asm: "VPRORVD", commutative: false, typ: "Vec128", resultInArg0: false},
                {name: "VPDPWSSDSMasked128", argLength: 4, reg: fp3kfp, asm: "VPDPWSSDS", commutative: false, typ: "Vec128", resultInArg0: true},
                {name: "VPDPBUSDSMasked128", argLength: 4, reg: fp3kfp, asm: "VPDPBUSDS", commutative: false, typ: "Vec128", resultInArg0: true},
+               {name: "VPSLLVDMasked128", argLength: 3, reg: fp2kfp, asm: "VPSLLVD", commutative: false, typ: "Vec128", resultInArg0: false},
+               {name: "VPSHLDVDMasked128", argLength: 4, reg: fp3kfp, asm: "VPSHLDVD", commutative: false, typ: "Vec128", resultInArg0: true},
+               {name: "VPSRLVDMasked128", argLength: 3, reg: fp2kfp, asm: "VPSRLVD", commutative: false, typ: "Vec128", resultInArg0: false},
+               {name: "VPSHRDVDMasked128", argLength: 4, reg: fp3kfp, asm: "VPSHRDVD", commutative: false, typ: "Vec128", resultInArg0: true},
+               {name: "VPSRAVDMasked128", argLength: 3, reg: fp2kfp, asm: "VPSRAVD", commutative: false, typ: "Vec128", resultInArg0: false},
                {name: "VPSUBDMasked128", argLength: 3, reg: fp2kfp, asm: "VPSUBD", commutative: false, typ: "Vec128", resultInArg0: false},
                {name: "VPDPBUSDMasked128", argLength: 4, reg: fp3kfp, asm: "VPDPBUSD", commutative: false, typ: "Vec128", resultInArg0: true},
                {name: "VPXORDMasked128", argLength: 3, reg: fp2kfp, asm: "VPXORD", commutative: true, typ: "Vec128", resultInArg0: false},
@@ -356,8 +413,18 @@ func simdAMD64Ops(fp11, fp21, fp2k, fpkfp, fp2kfp, fp2kk, fp31, fp3kfp, fpgpfp,
                {name: "VPHADDD128", argLength: 2, reg: fp21, asm: "VPHADDD", commutative: false, typ: "Vec128", resultInArg0: false},
                {name: "VPHSUBD128", argLength: 2, reg: fp21, asm: "VPHSUBD", commutative: false, typ: "Vec128", resultInArg0: false},
                {name: "VPOPCNTD128", argLength: 1, reg: fp11, asm: "VPOPCNTD", commutative: false, typ: "Vec128", resultInArg0: false},
+               {name: "VPROLVD128", argLength: 2, reg: fp21, asm: "VPROLVD", commutative: false, typ: "Vec128", resultInArg0: false},
+               {name: "VPRORVD128", argLength: 2, reg: fp21, asm: "VPRORVD", commutative: false, typ: "Vec128", resultInArg0: false},
                {name: "VPDPWSSDS128", argLength: 3, reg: fp31, asm: "VPDPWSSDS", commutative: false, typ: "Vec128", resultInArg0: true},
                {name: "VPDPBUSDS128", argLength: 3, reg: fp31, asm: "VPDPBUSDS", commutative: false, typ: "Vec128", resultInArg0: true},
+               {name: "VPSLLD128", argLength: 2, reg: fp21, asm: "VPSLLD", commutative: false, typ: "Vec128", resultInArg0: false},
+               {name: "VPSRLD128", argLength: 2, reg: fp21, asm: "VPSRLD", commutative: false, typ: "Vec128", resultInArg0: false},
+               {name: "VPSRAD128", argLength: 2, reg: fp21, asm: "VPSRAD", commutative: false, typ: "Vec128", resultInArg0: false},
+               {name: "VPSLLVD128", argLength: 2, reg: fp21, asm: "VPSLLVD", commutative: false, typ: "Vec128", resultInArg0: false},
+               {name: "VPSHLDVD128", argLength: 3, reg: fp31, asm: "VPSHLDVD", commutative: false, typ: "Vec128", resultInArg0: true},
+               {name: "VPSRLVD128", argLength: 2, reg: fp21, asm: "VPSRLVD", commutative: false, typ: "Vec128", resultInArg0: false},
+               {name: "VPSHRDVD128", argLength: 3, reg: fp31, asm: "VPSHRDVD", commutative: false, typ: "Vec128", resultInArg0: true},
+               {name: "VPSRAVD128", argLength: 2, reg: fp21, asm: "VPSRAVD", commutative: false, typ: "Vec128", resultInArg0: false},
                {name: "VPSIGND128", argLength: 2, reg: fp21, asm: "VPSIGND", commutative: false, typ: "Vec128", resultInArg0: false},
                {name: "VPSUBD128", argLength: 2, reg: fp21, asm: "VPSUBD", commutative: false, typ: "Vec128", resultInArg0: false},
                {name: "VPDPBUSD128", argLength: 3, reg: fp31, asm: "VPDPBUSD", commutative: false, typ: "Vec128", resultInArg0: true},
@@ -375,8 +442,15 @@ func simdAMD64Ops(fp11, fp21, fp2k, fpkfp, fp2kfp, fp2kk, fp31, fp3kfp, fpgpfp,
                {name: "VPORDMasked256", argLength: 3, reg: fp2kfp, asm: "VPORD", commutative: true, typ: "Vec256", resultInArg0: false},
                {name: "VPDPWSSDMasked256", argLength: 4, reg: fp3kfp, asm: "VPDPWSSD", commutative: false, typ: "Vec256", resultInArg0: true},
                {name: "VPOPCNTDMasked256", argLength: 2, reg: fpkfp, asm: "VPOPCNTD", commutative: false, typ: "Vec256", resultInArg0: false},
+               {name: "VPROLVDMasked256", argLength: 3, reg: fp2kfp, asm: "VPROLVD", commutative: false, typ: "Vec256", resultInArg0: false},
+               {name: "VPRORVDMasked256", argLength: 3, reg: fp2kfp, asm: "VPRORVD", commutative: false, typ: "Vec256", resultInArg0: false},
                {name: "VPDPWSSDSMasked256", argLength: 4, reg: fp3kfp, asm: "VPDPWSSDS", commutative: false, typ: "Vec256", resultInArg0: true},
                {name: "VPDPBUSDSMasked256", argLength: 4, reg: fp3kfp, asm: "VPDPBUSDS", commutative: false, typ: "Vec256", resultInArg0: true},
+               {name: "VPSLLVDMasked256", argLength: 3, reg: fp2kfp, asm: "VPSLLVD", commutative: false, typ: "Vec256", resultInArg0: false},
+               {name: "VPSHLDVDMasked256", argLength: 4, reg: fp3kfp, asm: "VPSHLDVD", commutative: false, typ: "Vec256", resultInArg0: true},
+               {name: "VPSRLVDMasked256", argLength: 3, reg: fp2kfp, asm: "VPSRLVD", commutative: false, typ: "Vec256", resultInArg0: false},
+               {name: "VPSHRDVDMasked256", argLength: 4, reg: fp3kfp, asm: "VPSHRDVD", commutative: false, typ: "Vec256", resultInArg0: true},
+               {name: "VPSRAVDMasked256", argLength: 3, reg: fp2kfp, asm: "VPSRAVD", commutative: false, typ: "Vec256", resultInArg0: false},
                {name: "VPSUBDMasked256", argLength: 3, reg: fp2kfp, asm: "VPSUBD", commutative: false, typ: "Vec256", resultInArg0: false},
                {name: "VPDPBUSDMasked256", argLength: 4, reg: fp3kfp, asm: "VPDPBUSD", commutative: false, typ: "Vec256", resultInArg0: true},
                {name: "VPXORDMasked256", argLength: 3, reg: fp2kfp, asm: "VPXORD", commutative: true, typ: "Vec256", resultInArg0: false},
@@ -388,8 +462,18 @@ func simdAMD64Ops(fp11, fp21, fp2k, fpkfp, fp2kfp, fp2kk, fp31, fp3kfp, fpgpfp,
                {name: "VPHADDD256", argLength: 2, reg: fp21, asm: "VPHADDD", commutative: false, typ: "Vec256", resultInArg0: false},
                {name: "VPHSUBD256", argLength: 2, reg: fp21, asm: "VPHSUBD", commutative: false, typ: "Vec256", resultInArg0: false},
                {name: "VPOPCNTD256", argLength: 1, reg: fp11, asm: "VPOPCNTD", commutative: false, typ: "Vec256", resultInArg0: false},
+               {name: "VPROLVD256", argLength: 2, reg: fp21, asm: "VPROLVD", commutative: false, typ: "Vec256", resultInArg0: false},
+               {name: "VPRORVD256", argLength: 2, reg: fp21, asm: "VPRORVD", commutative: false, typ: "Vec256", resultInArg0: false},
                {name: "VPDPWSSDS256", argLength: 3, reg: fp31, asm: "VPDPWSSDS", commutative: false, typ: "Vec256", resultInArg0: true},
                {name: "VPDPBUSDS256", argLength: 3, reg: fp31, asm: "VPDPBUSDS", commutative: false, typ: "Vec256", resultInArg0: true},
+               {name: "VPSLLD256", argLength: 2, reg: fp21, asm: "VPSLLD", commutative: false, typ: "Vec256", resultInArg0: false},
+               {name: "VPSRLD256", argLength: 2, reg: fp21, asm: "VPSRLD", commutative: false, typ: "Vec256", resultInArg0: false},
+               {name: "VPSRAD256", argLength: 2, reg: fp21, asm: "VPSRAD", commutative: false, typ: "Vec256", resultInArg0: false},
+               {name: "VPSLLVD256", argLength: 2, reg: fp21, asm: "VPSLLVD", commutative: false, typ: "Vec256", resultInArg0: false},
+               {name: "VPSHLDVD256", argLength: 3, reg: fp31, asm: "VPSHLDVD", commutative: false, typ: "Vec256", resultInArg0: true},
+               {name: "VPSRLVD256", argLength: 2, reg: fp21, asm: "VPSRLVD", commutative: false, typ: "Vec256", resultInArg0: false},
+               {name: "VPSHRDVD256", argLength: 3, reg: fp31, asm: "VPSHRDVD", commutative: false, typ: "Vec256", resultInArg0: true},
+               {name: "VPSRAVD256", argLength: 2, reg: fp21, asm: "VPSRAVD", commutative: false, typ: "Vec256", resultInArg0: false},
                {name: "VPSIGND256", argLength: 2, reg: fp21, asm: "VPSIGND", commutative: false, typ: "Vec256", resultInArg0: false},
                {name: "VPSUBD256", argLength: 2, reg: fp21, asm: "VPSUBD", commutative: false, typ: "Vec256", resultInArg0: false},
                {name: "VPDPBUSD256", argLength: 3, reg: fp31, asm: "VPDPBUSD", commutative: false, typ: "Vec256", resultInArg0: true},
@@ -406,12 +490,32 @@ func simdAMD64Ops(fp11, fp21, fp2k, fpkfp, fp2kfp, fp2kk, fp31, fp3kfp, fpgpfp,
                {name: "VPMULLQMasked128", argLength: 3, reg: fp2kfp, asm: "VPMULLQ", commutative: true, typ: "Vec128", resultInArg0: false},
                {name: "VPORQMasked128", argLength: 3, reg: fp2kfp, asm: "VPORQ", commutative: true, typ: "Vec128", resultInArg0: false},
                {name: "VPOPCNTQMasked128", argLength: 2, reg: fpkfp, asm: "VPOPCNTQ", commutative: false, typ: "Vec128", resultInArg0: false},
+               {name: "VPROLVQMasked128", argLength: 3, reg: fp2kfp, asm: "VPROLVQ", commutative: false, typ: "Vec128", resultInArg0: false},
+               {name: "VPRORVQMasked128", argLength: 3, reg: fp2kfp, asm: "VPRORVQ", commutative: false, typ: "Vec128", resultInArg0: false},
+               {name: "VPSLLQMasked128", argLength: 3, reg: fp2kfp, asm: "VPSLLQ", commutative: false, typ: "Vec128", resultInArg0: false},
+               {name: "VPSRLQMasked128", argLength: 3, reg: fp2kfp, asm: "VPSRLQ", commutative: false, typ: "Vec128", resultInArg0: false},
+               {name: "VPSRAQMasked128", argLength: 3, reg: fp2kfp, asm: "VPSRAQ", commutative: false, typ: "Vec128", resultInArg0: false},
+               {name: "VPSLLVQMasked128", argLength: 3, reg: fp2kfp, asm: "VPSLLVQ", commutative: false, typ: "Vec128", resultInArg0: false},
+               {name: "VPSHLDVQMasked128", argLength: 4, reg: fp3kfp, asm: "VPSHLDVQ", commutative: false, typ: "Vec128", resultInArg0: true},
+               {name: "VPSRLVQMasked128", argLength: 3, reg: fp2kfp, asm: "VPSRLVQ", commutative: false, typ: "Vec128", resultInArg0: false},
+               {name: "VPSHRDVQMasked128", argLength: 4, reg: fp3kfp, asm: "VPSHRDVQ", commutative: false, typ: "Vec128", resultInArg0: true},
+               {name: "VPSRAVQMasked128", argLength: 3, reg: fp2kfp, asm: "VPSRAVQ", commutative: false, typ: "Vec128", resultInArg0: false},
                {name: "VPSUBQMasked128", argLength: 3, reg: fp2kfp, asm: "VPSUBQ", commutative: false, typ: "Vec128", resultInArg0: false},
                {name: "VPXORQMasked128", argLength: 3, reg: fp2kfp, asm: "VPXORQ", commutative: true, typ: "Vec128", resultInArg0: false},
                {name: "VPMAXSQ128", argLength: 2, reg: fp21, asm: "VPMAXSQ", commutative: true, typ: "Vec128", resultInArg0: false},
                {name: "VPMINSQ128", argLength: 2, reg: fp21, asm: "VPMINSQ", commutative: true, typ: "Vec128", resultInArg0: false},
                {name: "VPMULLQ128", argLength: 2, reg: fp21, asm: "VPMULLQ", commutative: true, typ: "Vec128", resultInArg0: false},
                {name: "VPOPCNTQ128", argLength: 1, reg: fp11, asm: "VPOPCNTQ", commutative: false, typ: "Vec128", resultInArg0: false},
+               {name: "VPROLVQ128", argLength: 2, reg: fp21, asm: "VPROLVQ", commutative: false, typ: "Vec128", resultInArg0: false},
+               {name: "VPRORVQ128", argLength: 2, reg: fp21, asm: "VPRORVQ", commutative: false, typ: "Vec128", resultInArg0: false},
+               {name: "VPSLLQ128", argLength: 2, reg: fp21, asm: "VPSLLQ", commutative: false, typ: "Vec128", resultInArg0: false},
+               {name: "VPSRLQ128", argLength: 2, reg: fp21, asm: "VPSRLQ", commutative: false, typ: "Vec128", resultInArg0: false},
+               {name: "VPSRAQ128", argLength: 2, reg: fp21, asm: "VPSRAQ", commutative: false, typ: "Vec128", resultInArg0: false},
+               {name: "VPSLLVQ128", argLength: 2, reg: fp21, asm: "VPSLLVQ", commutative: false, typ: "Vec128", resultInArg0: false},
+               {name: "VPSHLDVQ128", argLength: 3, reg: fp31, asm: "VPSHLDVQ", commutative: false, typ: "Vec128", resultInArg0: true},
+               {name: "VPSRLVQ128", argLength: 2, reg: fp21, asm: "VPSRLVQ", commutative: false, typ: "Vec128", resultInArg0: false},
+               {name: "VPSHRDVQ128", argLength: 3, reg: fp31, asm: "VPSHRDVQ", commutative: false, typ: "Vec128", resultInArg0: true},
+               {name: "VPSRAVQ128", argLength: 2, reg: fp21, asm: "VPSRAVQ", commutative: false, typ: "Vec128", resultInArg0: false},
                {name: "VPSUBQ128", argLength: 2, reg: fp21, asm: "VPSUBQ", commutative: false, typ: "Vec128", resultInArg0: false},
                {name: "VPABSQ256", argLength: 1, reg: fp11, asm: "VPABSQ", commutative: false, typ: "Vec256", resultInArg0: false},
                {name: "VPADDQ256", argLength: 2, reg: fp21, asm: "VPADDQ", commutative: true, typ: "Vec256", resultInArg0: false},
@@ -427,12 +531,32 @@ func simdAMD64Ops(fp11, fp21, fp2k, fpkfp, fp2kfp, fp2kk, fp31, fp3kfp, fpgpfp,
                {name: "VPMULLQMasked256", argLength: 3, reg: fp2kfp, asm: "VPMULLQ", commutative: true, typ: "Vec256", resultInArg0: false},
                {name: "VPORQMasked256", argLength: 3, reg: fp2kfp, asm: "VPORQ", commutative: true, typ: "Vec256", resultInArg0: false},
                {name: "VPOPCNTQMasked256", argLength: 2, reg: fpkfp, asm: "VPOPCNTQ", commutative: false, typ: "Vec256", resultInArg0: false},
+               {name: "VPROLVQMasked256", argLength: 3, reg: fp2kfp, asm: "VPROLVQ", commutative: false, typ: "Vec256", resultInArg0: false},
+               {name: "VPRORVQMasked256", argLength: 3, reg: fp2kfp, asm: "VPRORVQ", commutative: false, typ: "Vec256", resultInArg0: false},
+               {name: "VPSLLQMasked256", argLength: 3, reg: fp2kfp, asm: "VPSLLQ", commutative: false, typ: "Vec256", resultInArg0: false},
+               {name: "VPSRLQMasked256", argLength: 3, reg: fp2kfp, asm: "VPSRLQ", commutative: false, typ: "Vec256", resultInArg0: false},
+               {name: "VPSRAQMasked256", argLength: 3, reg: fp2kfp, asm: "VPSRAQ", commutative: false, typ: "Vec256", resultInArg0: false},
+               {name: "VPSLLVQMasked256", argLength: 3, reg: fp2kfp, asm: "VPSLLVQ", commutative: false, typ: "Vec256", resultInArg0: false},
+               {name: "VPSHLDVQMasked256", argLength: 4, reg: fp3kfp, asm: "VPSHLDVQ", commutative: false, typ: "Vec256", resultInArg0: true},
+               {name: "VPSRLVQMasked256", argLength: 3, reg: fp2kfp, asm: "VPSRLVQ", commutative: false, typ: "Vec256", resultInArg0: false},
+               {name: "VPSHRDVQMasked256", argLength: 4, reg: fp3kfp, asm: "VPSHRDVQ", commutative: false, typ: "Vec256", resultInArg0: true},
+               {name: "VPSRAVQMasked256", argLength: 3, reg: fp2kfp, asm: "VPSRAVQ", commutative: false, typ: "Vec256", resultInArg0: false},
                {name: "VPSUBQMasked256", argLength: 3, reg: fp2kfp, asm: "VPSUBQ", commutative: false, typ: "Vec256", resultInArg0: false},
                {name: "VPXORQMasked256", argLength: 3, reg: fp2kfp, asm: "VPXORQ", commutative: true, typ: "Vec256", resultInArg0: false},
                {name: "VPMAXSQ256", argLength: 2, reg: fp21, asm: "VPMAXSQ", commutative: true, typ: "Vec256", resultInArg0: false},
                {name: "VPMINSQ256", argLength: 2, reg: fp21, asm: "VPMINSQ", commutative: true, typ: "Vec256", resultInArg0: false},
                {name: "VPMULLQ256", argLength: 2, reg: fp21, asm: "VPMULLQ", commutative: true, typ: "Vec256", resultInArg0: false},
                {name: "VPOPCNTQ256", argLength: 1, reg: fp11, asm: "VPOPCNTQ", commutative: false, typ: "Vec256", resultInArg0: false},
+               {name: "VPROLVQ256", argLength: 2, reg: fp21, asm: "VPROLVQ", commutative: false, typ: "Vec256", resultInArg0: false},
+               {name: "VPRORVQ256", argLength: 2, reg: fp21, asm: "VPRORVQ", commutative: false, typ: "Vec256", resultInArg0: false},
+               {name: "VPSLLQ256", argLength: 2, reg: fp21, asm: "VPSLLQ", commutative: false, typ: "Vec256", resultInArg0: false},
+               {name: "VPSRLQ256", argLength: 2, reg: fp21, asm: "VPSRLQ", commutative: false, typ: "Vec256", resultInArg0: false},
+               {name: "VPSRAQ256", argLength: 2, reg: fp21, asm: "VPSRAQ", commutative: false, typ: "Vec256", resultInArg0: false},
+               {name: "VPSLLVQ256", argLength: 2, reg: fp21, asm: "VPSLLVQ", commutative: false, typ: "Vec256", resultInArg0: false},
+               {name: "VPSHLDVQ256", argLength: 3, reg: fp31, asm: "VPSHLDVQ", commutative: false, typ: "Vec256", resultInArg0: true},
+               {name: "VPSRLVQ256", argLength: 2, reg: fp21, asm: "VPSRLVQ", commutative: false, typ: "Vec256", resultInArg0: false},
+               {name: "VPSHRDVQ256", argLength: 3, reg: fp31, asm: "VPSHRDVQ", commutative: false, typ: "Vec256", resultInArg0: true},
+               {name: "VPSRAVQ256", argLength: 2, reg: fp21, asm: "VPSRAVQ", commutative: false, typ: "Vec256", resultInArg0: false},
                {name: "VPSUBQ256", argLength: 2, reg: fp21, asm: "VPSUBQ", commutative: false, typ: "Vec256", resultInArg0: false},
                {name: "VPABSQ512", argLength: 1, reg: fp11, asm: "VPABSQ", commutative: false, typ: "Vec512", resultInArg0: false},
                {name: "VPADDQ512", argLength: 2, reg: fp21, asm: "VPADDQ", commutative: true, typ: "Vec512", resultInArg0: false},
@@ -448,6 +572,16 @@ func simdAMD64Ops(fp11, fp21, fp2k, fpkfp, fp2kfp, fp2kk, fp31, fp3kfp, fpgpfp,
                {name: "VPMULLQMasked512", argLength: 3, reg: fp2kfp, asm: "VPMULLQ", commutative: true, typ: "Vec512", resultInArg0: false},
                {name: "VPORQMasked512", argLength: 3, reg: fp2kfp, asm: "VPORQ", commutative: true, typ: "Vec512", resultInArg0: false},
                {name: "VPOPCNTQMasked512", argLength: 2, reg: fpkfp, asm: "VPOPCNTQ", commutative: false, typ: "Vec512", resultInArg0: false},
+               {name: "VPROLVQMasked512", argLength: 3, reg: fp2kfp, asm: "VPROLVQ", commutative: false, typ: "Vec512", resultInArg0: false},
+               {name: "VPRORVQMasked512", argLength: 3, reg: fp2kfp, asm: "VPRORVQ", commutative: false, typ: "Vec512", resultInArg0: false},
+               {name: "VPSLLQMasked512", argLength: 3, reg: fp2kfp, asm: "VPSLLQ", commutative: false, typ: "Vec512", resultInArg0: false},
+               {name: "VPSRLQMasked512", argLength: 3, reg: fp2kfp, asm: "VPSRLQ", commutative: false, typ: "Vec512", resultInArg0: false},
+               {name: "VPSRAQMasked512", argLength: 3, reg: fp2kfp, asm: "VPSRAQ", commutative: false, typ: "Vec512", resultInArg0: false},
+               {name: "VPSLLVQMasked512", argLength: 3, reg: fp2kfp, asm: "VPSLLVQ", commutative: false, typ: "Vec512", resultInArg0: false},
+               {name: "VPSHLDVQMasked512", argLength: 4, reg: fp3kfp, asm: "VPSHLDVQ", commutative: false, typ: "Vec512", resultInArg0: true},
+               {name: "VPSRLVQMasked512", argLength: 3, reg: fp2kfp, asm: "VPSRLVQ", commutative: false, typ: "Vec512", resultInArg0: false},
+               {name: "VPSHRDVQMasked512", argLength: 4, reg: fp3kfp, asm: "VPSHRDVQ", commutative: false, typ: "Vec512", resultInArg0: true},
+               {name: "VPSRAVQMasked512", argLength: 3, reg: fp2kfp, asm: "VPSRAVQ", commutative: false, typ: "Vec512", resultInArg0: false},
                {name: "VPSUBQMasked512", argLength: 3, reg: fp2kfp, asm: "VPSUBQ", commutative: false, typ: "Vec512", resultInArg0: false},
                {name: "VPXORQMasked512", argLength: 3, reg: fp2kfp, asm: "VPXORQ", commutative: true, typ: "Vec512", resultInArg0: false},
                {name: "VPMAXSQ512", argLength: 2, reg: fp21, asm: "VPMAXSQ", commutative: true, typ: "Vec512", resultInArg0: false},
@@ -456,6 +590,16 @@ func simdAMD64Ops(fp11, fp21, fp2k, fpkfp, fp2kfp, fp2kk, fp31, fp3kfp, fpgpfp,
                {name: "VPMULLQ512", argLength: 2, reg: fp21, asm: "VPMULLQ", commutative: true, typ: "Vec512", resultInArg0: false},
                {name: "VPORQ512", argLength: 2, reg: fp21, asm: "VPORQ", commutative: true, typ: "Vec512", resultInArg0: false},
                {name: "VPOPCNTQ512", argLength: 1, reg: fp11, asm: "VPOPCNTQ", commutative: false, typ: "Vec512", resultInArg0: false},
+               {name: "VPROLVQ512", argLength: 2, reg: fp21, asm: "VPROLVQ", commutative: false, typ: "Vec512", resultInArg0: false},
+               {name: "VPRORVQ512", argLength: 2, reg: fp21, asm: "VPRORVQ", commutative: false, typ: "Vec512", resultInArg0: false},
+               {name: "VPSLLQ512", argLength: 2, reg: fp21, asm: "VPSLLQ", commutative: false, typ: "Vec512", resultInArg0: false},
+               {name: "VPSRLQ512", argLength: 2, reg: fp21, asm: "VPSRLQ", commutative: false, typ: "Vec512", resultInArg0: false},
+               {name: "VPSRAQ512", argLength: 2, reg: fp21, asm: "VPSRAQ", commutative: false, typ: "Vec512", resultInArg0: false},
+               {name: "VPSLLVQ512", argLength: 2, reg: fp21, asm: "VPSLLVQ", commutative: false, typ: "Vec512", resultInArg0: false},
+               {name: "VPSHLDVQ512", argLength: 3, reg: fp31, asm: "VPSHLDVQ", commutative: false, typ: "Vec512", resultInArg0: true},
+               {name: "VPSRLVQ512", argLength: 2, reg: fp21, asm: "VPSRLVQ", commutative: false, typ: "Vec512", resultInArg0: false},
+               {name: "VPSHRDVQ512", argLength: 3, reg: fp31, asm: "VPSHRDVQ", commutative: false, typ: "Vec512", resultInArg0: true},
+               {name: "VPSRAVQ512", argLength: 2, reg: fp21, asm: "VPSRAVQ", commutative: false, typ: "Vec512", resultInArg0: false},
                {name: "VPSUBQ512", argLength: 2, reg: fp21, asm: "VPSUBQ", commutative: false, typ: "Vec512", resultInArg0: false},
                {name: "VPXORQ512", argLength: 2, reg: fp21, asm: "VPXORQ", commutative: true, typ: "Vec512", resultInArg0: false},
                {name: "VPABSB128", argLength: 1, reg: fp11, asm: "VPABSB", commutative: false, typ: "Vec128", resultInArg0: false},
@@ -641,28 +785,88 @@ func simdAMD64Ops(fp11, fp21, fp2k, fpkfp, fp2kfp, fp2kk, fp31, fp3kfp, fpgpfp,
                {name: "VCMPPDMasked512", argLength: 3, reg: fp2kk, asm: "VCMPPD", aux: "Int8", commutative: true, typ: "Mask", resultInArg0: false},
                {name: "VPCMPW256", argLength: 2, reg: fp2k, asm: "VPCMPW", aux: "Int8", commutative: false, typ: "Mask", resultInArg0: false},
                {name: "VPCMPWMasked256", argLength: 3, reg: fp2kk, asm: "VPCMPW", aux: "Int8", commutative: true, typ: "Mask", resultInArg0: false},
+               {name: "VPSHLDWMasked256", argLength: 3, reg: fp2kfp, asm: "VPSHLDW", aux: "Int8", commutative: false, typ: "Vec256", resultInArg0: false},
+               {name: "VPSHRDWMasked256", argLength: 3, reg: fp2kfp, asm: "VPSHRDW", aux: "Int8", commutative: false, typ: "Vec256", resultInArg0: false},
+               {name: "VPSHLDW256", argLength: 2, reg: fp21, asm: "VPSHLDW", aux: "Int8", commutative: false, typ: "Vec256", resultInArg0: false},
+               {name: "VPSHRDW256", argLength: 2, reg: fp21, asm: "VPSHRDW", aux: "Int8", commutative: false, typ: "Vec256", resultInArg0: false},
                {name: "VPCMPW512", argLength: 2, reg: fp2k, asm: "VPCMPW", aux: "Int8", commutative: true, typ: "Mask", resultInArg0: false},
                {name: "VPCMPWMasked512", argLength: 3, reg: fp2kk, asm: "VPCMPW", aux: "Int8", commutative: true, typ: "Mask", resultInArg0: false},
+               {name: "VPSHLDWMasked512", argLength: 3, reg: fp2kfp, asm: "VPSHLDW", aux: "Int8", commutative: false, typ: "Vec512", resultInArg0: false},
+               {name: "VPSHRDWMasked512", argLength: 3, reg: fp2kfp, asm: "VPSHRDW", aux: "Int8", commutative: false, typ: "Vec512", resultInArg0: false},
+               {name: "VPSHLDW512", argLength: 2, reg: fp21, asm: "VPSHLDW", aux: "Int8", commutative: false, typ: "Vec512", resultInArg0: false},
+               {name: "VPSHRDW512", argLength: 2, reg: fp21, asm: "VPSHRDW", aux: "Int8", commutative: false, typ: "Vec512", resultInArg0: false},
                {name: "VPEXTRW128", argLength: 1, reg: fpgp, asm: "VPEXTRW", aux: "Int8", commutative: false, typ: "int16", resultInArg0: false},
                {name: "VPCMPW128", argLength: 2, reg: fp2k, asm: "VPCMPW", aux: "Int8", commutative: false, typ: "Mask", resultInArg0: false},
                {name: "VPCMPWMasked128", argLength: 3, reg: fp2kk, asm: "VPCMPW", aux: "Int8", commutative: true, typ: "Mask", resultInArg0: false},
+               {name: "VPSHLDWMasked128", argLength: 3, reg: fp2kfp, asm: "VPSHLDW", aux: "Int8", commutative: false, typ: "Vec128", resultInArg0: false},
+               {name: "VPSHRDWMasked128", argLength: 3, reg: fp2kfp, asm: "VPSHRDW", aux: "Int8", commutative: false, typ: "Vec128", resultInArg0: false},
                {name: "VPINSRW128", argLength: 2, reg: fpgpfp, asm: "VPINSRW", aux: "Int8", commutative: false, typ: "Vec128", resultInArg0: false},
+               {name: "VPSHLDW128", argLength: 2, reg: fp21, asm: "VPSHLDW", aux: "Int8", commutative: false, typ: "Vec128", resultInArg0: false},
+               {name: "VPSHRDW128", argLength: 2, reg: fp21, asm: "VPSHRDW", aux: "Int8", commutative: false, typ: "Vec128", resultInArg0: false},
                {name: "VPCMPD512", argLength: 2, reg: fp2k, asm: "VPCMPD", aux: "Int8", commutative: true, typ: "Mask", resultInArg0: false},
                {name: "VPCMPDMasked512", argLength: 3, reg: fp2kk, asm: "VPCMPD", aux: "Int8", commutative: true, typ: "Mask", resultInArg0: false},
+               {name: "VPROLDMasked512", argLength: 2, reg: fpkfp, asm: "VPROLD", aux: "Int8", commutative: false, typ: "Vec512", resultInArg0: false},
+               {name: "VPRORDMasked512", argLength: 2, reg: fpkfp, asm: "VPRORD", aux: "Int8", commutative: false, typ: "Vec512", resultInArg0: false},
+               {name: "VPSHLDDMasked512", argLength: 3, reg: fp2kfp, asm: "VPSHLDD", aux: "Int8", commutative: false, typ: "Vec512", resultInArg0: false},
+               {name: "VPSHRDDMasked512", argLength: 3, reg: fp2kfp, asm: "VPSHRDD", aux: "Int8", commutative: false, typ: "Vec512", resultInArg0: false},
+               {name: "VPROLD512", argLength: 1, reg: fp11, asm: "VPROLD", aux: "Int8", commutative: false, typ: "Vec512", resultInArg0: false},
+               {name: "VPRORD512", argLength: 1, reg: fp11, asm: "VPRORD", aux: "Int8", commutative: false, typ: "Vec512", resultInArg0: false},
+               {name: "VPSHLDD512", argLength: 2, reg: fp21, asm: "VPSHLDD", aux: "Int8", commutative: false, typ: "Vec512", resultInArg0: false},
+               {name: "VPSHRDD512", argLength: 2, reg: fp21, asm: "VPSHRDD", aux: "Int8", commutative: false, typ: "Vec512", resultInArg0: false},
                {name: "VPEXTRD128", argLength: 1, reg: fpgp, asm: "VPEXTRD", aux: "Int8", commutative: false, typ: "int32", resultInArg0: false},
                {name: "VPCMPD128", argLength: 2, reg: fp2k, asm: "VPCMPD", aux: "Int8", commutative: false, typ: "Mask", resultInArg0: false},
                {name: "VPCMPDMasked128", argLength: 3, reg: fp2kk, asm: "VPCMPD", aux: "Int8", commutative: true, typ: "Mask", resultInArg0: false},
+               {name: "VPROLDMasked128", argLength: 2, reg: fpkfp, asm: "VPROLD", aux: "Int8", commutative: false, typ: "Vec128", resultInArg0: false},
+               {name: "VPRORDMasked128", argLength: 2, reg: fpkfp, asm: "VPRORD", aux: "Int8", commutative: false, typ: "Vec128", resultInArg0: false},
+               {name: "VPSHLDDMasked128", argLength: 3, reg: fp2kfp, asm: "VPSHLDD", aux: "Int8", commutative: false, typ: "Vec128", resultInArg0: false},
+               {name: "VPSHRDDMasked128", argLength: 3, reg: fp2kfp, asm: "VPSHRDD", aux: "Int8", commutative: false, typ: "Vec128", resultInArg0: false},
+               {name: "VPROLD128", argLength: 1, reg: fp11, asm: "VPROLD", aux: "Int8", commutative: false, typ: "Vec128", resultInArg0: false},
+               {name: "VPRORD128", argLength: 1, reg: fp11, asm: "VPRORD", aux: "Int8", commutative: false, typ: "Vec128", resultInArg0: false},
                {name: "VPINSRD128", argLength: 2, reg: fpgpfp, asm: "VPINSRD", aux: "Int8", commutative: false, typ: "Vec128", resultInArg0: false},
+               {name: "VPSHLDD128", argLength: 2, reg: fp21, asm: "VPSHLDD", aux: "Int8", commutative: false, typ: "Vec128", resultInArg0: false},
+               {name: "VPSHRDD128", argLength: 2, reg: fp21, asm: "VPSHRDD", aux: "Int8", commutative: false, typ: "Vec128", resultInArg0: false},
                {name: "VPCMPD256", argLength: 2, reg: fp2k, asm: "VPCMPD", aux: "Int8", commutative: false, typ: "Mask", resultInArg0: false},
                {name: "VPCMPDMasked256", argLength: 3, reg: fp2kk, asm: "VPCMPD", aux: "Int8", commutative: true, typ: "Mask", resultInArg0: false},
+               {name: "VPROLDMasked256", argLength: 2, reg: fpkfp, asm: "VPROLD", aux: "Int8", commutative: false, typ: "Vec256", resultInArg0: false},
+               {name: "VPRORDMasked256", argLength: 2, reg: fpkfp, asm: "VPRORD", aux: "Int8", commutative: false, typ: "Vec256", resultInArg0: false},
+               {name: "VPSHLDDMasked256", argLength: 3, reg: fp2kfp, asm: "VPSHLDD", aux: "Int8", commutative: false, typ: "Vec256", resultInArg0: false},
+               {name: "VPSHRDDMasked256", argLength: 3, reg: fp2kfp, asm: "VPSHRDD", aux: "Int8", commutative: false, typ: "Vec256", resultInArg0: false},
+               {name: "VPROLD256", argLength: 1, reg: fp11, asm: "VPROLD", aux: "Int8", commutative: false, typ: "Vec256", resultInArg0: false},
+               {name: "VPRORD256", argLength: 1, reg: fp11, asm: "VPRORD", aux: "Int8", commutative: false, typ: "Vec256", resultInArg0: false},
+               {name: "VPSHLDD256", argLength: 2, reg: fp21, asm: "VPSHLDD", aux: "Int8", commutative: false, typ: "Vec256", resultInArg0: false},
+               {name: "VPSHRDD256", argLength: 2, reg: fp21, asm: "VPSHRDD", aux: "Int8", commutative: false, typ: "Vec256", resultInArg0: false},
                {name: "VPEXTRQ128", argLength: 1, reg: fpgp, asm: "VPEXTRQ", aux: "Int8", commutative: false, typ: "int64", resultInArg0: false},
                {name: "VPCMPQ128", argLength: 2, reg: fp2k, asm: "VPCMPQ", aux: "Int8", commutative: false, typ: "Mask", resultInArg0: false},
                {name: "VPCMPQMasked128", argLength: 3, reg: fp2kk, asm: "VPCMPQ", aux: "Int8", commutative: true, typ: "Mask", resultInArg0: false},
+               {name: "VPROLQMasked128", argLength: 2, reg: fpkfp, asm: "VPROLQ", aux: "Int8", commutative: false, typ: "Vec128", resultInArg0: false},
+               {name: "VPRORQMasked128", argLength: 2, reg: fpkfp, asm: "VPRORQ", aux: "Int8", commutative: false, typ: "Vec128", resultInArg0: false},
+               {name: "VPSHLDQMasked128", argLength: 3, reg: fp2kfp, asm: "VPSHLDQ", aux: "Int8", commutative: false, typ: "Vec128", resultInArg0: false},
+               {name: "VPSHRDQMasked128", argLength: 3, reg: fp2kfp, asm: "VPSHRDQ", aux: "Int8", commutative: false, typ: "Vec128", resultInArg0: false},
+               {name: "VPROLQ128", argLength: 1, reg: fp11, asm: "VPROLQ", aux: "Int8", commutative: false, typ: "Vec128", resultInArg0: false},
+               {name: "VPRORQ128", argLength: 1, reg: fp11, asm: "VPRORQ", aux: "Int8", commutative: false, typ: "Vec128", resultInArg0: false},
                {name: "VPINSRQ128", argLength: 2, reg: fpgpfp, asm: "VPINSRQ", aux: "Int8", commutative: false, typ: "Vec128", resultInArg0: false},
+               {name: "VPSHLDQ128", argLength: 2, reg: fp21, asm: "VPSHLDQ", aux: "Int8", commutative: false, typ: "Vec128", resultInArg0: false},
+               {name: "VPSHRDQ128", argLength: 2, reg: fp21, asm: "VPSHRDQ", aux: "Int8", commutative: false, typ: "Vec128", resultInArg0: false},
                {name: "VPCMPQ256", argLength: 2, reg: fp2k, asm: "VPCMPQ", aux: "Int8", commutative: false, typ: "Mask", resultInArg0: false},
                {name: "VPCMPQMasked256", argLength: 3, reg: fp2kk, asm: "VPCMPQ", aux: "Int8", commutative: true, typ: "Mask", resultInArg0: false},
+               {name: "VPROLQMasked256", argLength: 2, reg: fpkfp, asm: "VPROLQ", aux: "Int8", commutative: false, typ: "Vec256", resultInArg0: false},
+               {name: "VPRORQMasked256", argLength: 2, reg: fpkfp, asm: "VPRORQ", aux: "Int8", commutative: false, typ: "Vec256", resultInArg0: false},
+               {name: "VPSHLDQMasked256", argLength: 3, reg: fp2kfp, asm: "VPSHLDQ", aux: "Int8", commutative: false, typ: "Vec256", resultInArg0: false},
+               {name: "VPSHRDQMasked256", argLength: 3, reg: fp2kfp, asm: "VPSHRDQ", aux: "Int8", commutative: false, typ: "Vec256", resultInArg0: false},
+               {name: "VPROLQ256", argLength: 1, reg: fp11, asm: "VPROLQ", aux: "Int8", commutative: false, typ: "Vec256", resultInArg0: false},
+               {name: "VPRORQ256", argLength: 1, reg: fp11, asm: "VPRORQ", aux: "Int8", commutative: false, typ: "Vec256", resultInArg0: false},
+               {name: "VPSHLDQ256", argLength: 2, reg: fp21, asm: "VPSHLDQ", aux: "Int8", commutative: false, typ: "Vec256", resultInArg0: false},
+               {name: "VPSHRDQ256", argLength: 2, reg: fp21, asm: "VPSHRDQ", aux: "Int8", commutative: false, typ: "Vec256", resultInArg0: false},
                {name: "VPCMPQ512", argLength: 2, reg: fp2k, asm: "VPCMPQ", aux: "Int8", commutative: true, typ: "Mask", resultInArg0: false},
                {name: "VPCMPQMasked512", argLength: 3, reg: fp2kk, asm: "VPCMPQ", aux: "Int8", commutative: true, typ: "Mask", resultInArg0: false},
+               {name: "VPROLQMasked512", argLength: 2, reg: fpkfp, asm: "VPROLQ", aux: "Int8", commutative: false, typ: "Vec512", resultInArg0: false},
+               {name: "VPRORQMasked512", argLength: 2, reg: fpkfp, asm: "VPRORQ", aux: "Int8", commutative: false, typ: "Vec512", resultInArg0: false},
+               {name: "VPSHLDQMasked512", argLength: 3, reg: fp2kfp, asm: "VPSHLDQ", aux: "Int8", commutative: false, typ: "Vec512", resultInArg0: false},
+               {name: "VPSHRDQMasked512", argLength: 3, reg: fp2kfp, asm: "VPSHRDQ", aux: "Int8", commutative: false, typ: "Vec512", resultInArg0: false},
+               {name: "VPROLQ512", argLength: 1, reg: fp11, asm: "VPROLQ", aux: "Int8", commutative: false, typ: "Vec512", resultInArg0: false},
+               {name: "VPRORQ512", argLength: 1, reg: fp11, asm: "VPRORQ", aux: "Int8", commutative: false, typ: "Vec512", resultInArg0: false},
+               {name: "VPSHLDQ512", argLength: 2, reg: fp21, asm: "VPSHLDQ", aux: "Int8", commutative: false, typ: "Vec512", resultInArg0: false},
+               {name: "VPSHRDQ512", argLength: 2, reg: fp21, asm: "VPSHRDQ", aux: "Int8", commutative: false, typ: "Vec512", resultInArg0: false},
                {name: "VPEXTRB128", argLength: 1, reg: fpgp, asm: "VPEXTRB", aux: "Int8", commutative: false, typ: "int8", resultInArg0: false},
                {name: "VPCMPB128", argLength: 2, reg: fp2k, asm: "VPCMPB", aux: "Int8", commutative: false, typ: "Mask", resultInArg0: false},
                {name: "VPCMPBMasked128", argLength: 3, reg: fp2kk, asm: "VPCMPB", aux: "Int8", commutative: true, typ: "Mask", resultInArg0: false},

diff --git a/src/cmd/compile/internal/ssa/_gen/simdgenericOps.go b/src/cmd/compile/internal/ssa/_gen/simdgenericOps.go
index 1c33483f4242f045d110436a29c17f3ce5b44f8d..0f3d3f8214cd22ff142119db9fc1c622ee0fa0b7 100644 (file)
--- a/src/cmd/compile/internal/ssa/_gen/simdgenericOps.go
+++ b/src/cmd/compile/internal/ssa/_gen/simdgenericOps.go
@@ -345,6 +345,11 @@ func simdGenericOps() []opData {
                {name: "MaskedPopCountInt16x16", argLength: 2, commutative: false},
                {name: "MaskedSaturatedAddInt16x16", argLength: 3, commutative: true},
                {name: "MaskedSaturatedSubInt16x16", argLength: 3, commutative: false},
+               {name: "MaskedShiftLeftInt16x16", argLength: 3, commutative: false},
+               {name: "MaskedShiftLeftAndFillUpperFromInt16x16", argLength: 4, commutative: false},
+               {name: "MaskedShiftRightInt16x16", argLength: 3, commutative: false},
+               {name: "MaskedShiftRightAndFillUpperFromInt16x16", argLength: 4, commutative: false},
+               {name: "MaskedShiftRightSignExtendedInt16x16", argLength: 3, commutative: false},
                {name: "MaskedSubInt16x16", argLength: 3, commutative: false},
                {name: "MaxInt16x16", argLength: 2, commutative: true},
                {name: "MinInt16x16", argLength: 2, commutative: true},
@@ -360,6 +365,14 @@ func simdGenericOps() []opData {
                {name: "SaturatedPairwiseAddInt16x16", argLength: 2, commutative: false},
                {name: "SaturatedPairwiseSubInt16x16", argLength: 2, commutative: false},
                {name: "SaturatedSubInt16x16", argLength: 2, commutative: false},
+               {name: "ShiftAllLeftInt16x16", argLength: 2, commutative: false},
+               {name: "ShiftAllRightInt16x16", argLength: 2, commutative: false},
+               {name: "ShiftAllRightSignExtendedInt16x16", argLength: 2, commutative: false},
+               {name: "ShiftLeftInt16x16", argLength: 2, commutative: false},
+               {name: "ShiftLeftAndFillUpperFromInt16x16", argLength: 3, commutative: false},
+               {name: "ShiftRightInt16x16", argLength: 2, commutative: false},
+               {name: "ShiftRightAndFillUpperFromInt16x16", argLength: 3, commutative: false},
+               {name: "ShiftRightSignExtendedInt16x16", argLength: 2, commutative: false},
                {name: "SignInt16x16", argLength: 2, commutative: false},
                {name: "SubInt16x16", argLength: 2, commutative: false},
                {name: "XorInt16x16", argLength: 2, commutative: true},
@@ -386,6 +399,11 @@ func simdGenericOps() []opData {
                {name: "MaskedPopCountInt16x32", argLength: 2, commutative: false},
                {name: "MaskedSaturatedAddInt16x32", argLength: 3, commutative: true},
                {name: "MaskedSaturatedSubInt16x32", argLength: 3, commutative: false},
+               {name: "MaskedShiftLeftInt16x32", argLength: 3, commutative: false},
+               {name: "MaskedShiftLeftAndFillUpperFromInt16x32", argLength: 4, commutative: false},
+               {name: "MaskedShiftRightInt16x32", argLength: 3, commutative: false},
+               {name: "MaskedShiftRightAndFillUpperFromInt16x32", argLength: 4, commutative: false},
+               {name: "MaskedShiftRightSignExtendedInt16x32", argLength: 3, commutative: false},
                {name: "MaskedSubInt16x32", argLength: 3, commutative: false},
                {name: "MaxInt16x32", argLength: 2, commutative: true},
                {name: "MinInt16x32", argLength: 2, commutative: true},
@@ -396,6 +414,11 @@ func simdGenericOps() []opData {
                {name: "PopCountInt16x32", argLength: 1, commutative: false},
                {name: "SaturatedAddInt16x32", argLength: 2, commutative: true},
                {name: "SaturatedSubInt16x32", argLength: 2, commutative: false},
+               {name: "ShiftLeftInt16x32", argLength: 2, commutative: false},
+               {name: "ShiftLeftAndFillUpperFromInt16x32", argLength: 3, commutative: false},
+               {name: "ShiftRightInt16x32", argLength: 2, commutative: false},
+               {name: "ShiftRightAndFillUpperFromInt16x32", argLength: 3, commutative: false},
+               {name: "ShiftRightSignExtendedInt16x32", argLength: 2, commutative: false},
                {name: "SubInt16x32", argLength: 2, commutative: false},
                {name: "AbsoluteInt16x8", argLength: 1, commutative: false},
                {name: "AddInt16x8", argLength: 2, commutative: true},
@@ -422,6 +445,11 @@ func simdGenericOps() []opData {
                {name: "MaskedPopCountInt16x8", argLength: 2, commutative: false},
                {name: "MaskedSaturatedAddInt16x8", argLength: 3, commutative: true},
                {name: "MaskedSaturatedSubInt16x8", argLength: 3, commutative: false},
+               {name: "MaskedShiftLeftInt16x8", argLength: 3, commutative: false},
+               {name: "MaskedShiftLeftAndFillUpperFromInt16x8", argLength: 4, commutative: false},
+               {name: "MaskedShiftRightInt16x8", argLength: 3, commutative: false},
+               {name: "MaskedShiftRightAndFillUpperFromInt16x8", argLength: 4, commutative: false},
+               {name: "MaskedShiftRightSignExtendedInt16x8", argLength: 3, commutative: false},
                {name: "MaskedSubInt16x8", argLength: 3, commutative: false},
                {name: "MaxInt16x8", argLength: 2, commutative: true},
                {name: "MinInt16x8", argLength: 2, commutative: true},
@@ -437,6 +465,14 @@ func simdGenericOps() []opData {
                {name: "SaturatedPairwiseAddInt16x8", argLength: 2, commutative: false},
                {name: "SaturatedPairwiseSubInt16x8", argLength: 2, commutative: false},
                {name: "SaturatedSubInt16x8", argLength: 2, commutative: false},
+               {name: "ShiftAllLeftInt16x8", argLength: 2, commutative: false},
+               {name: "ShiftAllRightInt16x8", argLength: 2, commutative: false},
+               {name: "ShiftAllRightSignExtendedInt16x8", argLength: 2, commutative: false},
+               {name: "ShiftLeftInt16x8", argLength: 2, commutative: false},
+               {name: "ShiftLeftAndFillUpperFromInt16x8", argLength: 3, commutative: false},
+               {name: "ShiftRightInt16x8", argLength: 2, commutative: false},
+               {name: "ShiftRightAndFillUpperFromInt16x8", argLength: 3, commutative: false},
+               {name: "ShiftRightSignExtendedInt16x8", argLength: 2, commutative: false},
                {name: "SignInt16x8", argLength: 2, commutative: false},
                {name: "SubInt16x8", argLength: 2, commutative: false},
                {name: "XorInt16x8", argLength: 2, commutative: true},
@@ -465,8 +501,15 @@ func simdGenericOps() []opData {
                {name: "MaskedOrInt32x16", argLength: 3, commutative: true},
                {name: "MaskedPairDotProdAccumulateInt32x16", argLength: 4, commutative: false},
                {name: "MaskedPopCountInt32x16", argLength: 2, commutative: false},
+               {name: "MaskedRotateLeftInt32x16", argLength: 3, commutative: false},
+               {name: "MaskedRotateRightInt32x16", argLength: 3, commutative: false},
                {name: "MaskedSaturatedPairDotProdAccumulateInt32x16", argLength: 4, commutative: false},
                {name: "MaskedSaturatedUnsignedSignedQuadDotProdAccumulateInt32x16", argLength: 4, commutative: false},
+               {name: "MaskedShiftLeftInt32x16", argLength: 3, commutative: false},
+               {name: "MaskedShiftLeftAndFillUpperFromInt32x16", argLength: 4, commutative: false},
+               {name: "MaskedShiftRightInt32x16", argLength: 3, commutative: false},
+               {name: "MaskedShiftRightAndFillUpperFromInt32x16", argLength: 4, commutative: false},
+               {name: "MaskedShiftRightSignExtendedInt32x16", argLength: 3, commutative: false},
                {name: "MaskedSubInt32x16", argLength: 3, commutative: false},
                {name: "MaskedUnsignedSignedQuadDotProdAccumulateInt32x16", argLength: 4, commutative: false},
                {name: "MaskedXorInt32x16", argLength: 3, commutative: true},
@@ -477,8 +520,15 @@ func simdGenericOps() []opData {
                {name: "OrInt32x16", argLength: 2, commutative: true},
                {name: "PairDotProdAccumulateInt32x16", argLength: 3, commutative: false},
                {name: "PopCountInt32x16", argLength: 1, commutative: false},
+               {name: "RotateLeftInt32x16", argLength: 2, commutative: false},
+               {name: "RotateRightInt32x16", argLength: 2, commutative: false},
                {name: "SaturatedPairDotProdAccumulateInt32x16", argLength: 3, commutative: false},
                {name: "SaturatedUnsignedSignedQuadDotProdAccumulateInt32x16", argLength: 3, commutative: false},
+               {name: "ShiftLeftInt32x16", argLength: 2, commutative: false},
+               {name: "ShiftLeftAndFillUpperFromInt32x16", argLength: 3, commutative: false},
+               {name: "ShiftRightInt32x16", argLength: 2, commutative: false},
+               {name: "ShiftRightAndFillUpperFromInt32x16", argLength: 3, commutative: false},
+               {name: "ShiftRightSignExtendedInt32x16", argLength: 2, commutative: false},
                {name: "SubInt32x16", argLength: 2, commutative: false},
                {name: "UnsignedSignedQuadDotProdAccumulateInt32x16", argLength: 3, commutative: false},
                {name: "XorInt32x16", argLength: 2, commutative: true},
@@ -507,8 +557,15 @@ func simdGenericOps() []opData {
                {name: "MaskedOrInt32x4", argLength: 3, commutative: true},
                {name: "MaskedPairDotProdAccumulateInt32x4", argLength: 4, commutative: false},
                {name: "MaskedPopCountInt32x4", argLength: 2, commutative: false},
+               {name: "MaskedRotateLeftInt32x4", argLength: 3, commutative: false},
+               {name: "MaskedRotateRightInt32x4", argLength: 3, commutative: false},
                {name: "MaskedSaturatedPairDotProdAccumulateInt32x4", argLength: 4, commutative: false},
                {name: "MaskedSaturatedUnsignedSignedQuadDotProdAccumulateInt32x4", argLength: 4, commutative: false},
+               {name: "MaskedShiftLeftInt32x4", argLength: 3, commutative: false},
+               {name: "MaskedShiftLeftAndFillUpperFromInt32x4", argLength: 4, commutative: false},
+               {name: "MaskedShiftRightInt32x4", argLength: 3, commutative: false},
+               {name: "MaskedShiftRightAndFillUpperFromInt32x4", argLength: 4, commutative: false},
+               {name: "MaskedShiftRightSignExtendedInt32x4", argLength: 3, commutative: false},
                {name: "MaskedSubInt32x4", argLength: 3, commutative: false},
                {name: "MaskedUnsignedSignedQuadDotProdAccumulateInt32x4", argLength: 4, commutative: false},
                {name: "MaskedXorInt32x4", argLength: 3, commutative: true},
@@ -522,8 +579,18 @@ func simdGenericOps() []opData {
                {name: "PairwiseAddInt32x4", argLength: 2, commutative: false},
                {name: "PairwiseSubInt32x4", argLength: 2, commutative: false},
                {name: "PopCountInt32x4", argLength: 1, commutative: false},
+               {name: "RotateLeftInt32x4", argLength: 2, commutative: false},
+               {name: "RotateRightInt32x4", argLength: 2, commutative: false},
                {name: "SaturatedPairDotProdAccumulateInt32x4", argLength: 3, commutative: false},
                {name: "SaturatedUnsignedSignedQuadDotProdAccumulateInt32x4", argLength: 3, commutative: false},
+               {name: "ShiftAllLeftInt32x4", argLength: 2, commutative: false},
+               {name: "ShiftAllRightInt32x4", argLength: 2, commutative: false},
+               {name: "ShiftAllRightSignExtendedInt32x4", argLength: 2, commutative: false},
+               {name: "ShiftLeftInt32x4", argLength: 2, commutative: false},
+               {name: "ShiftLeftAndFillUpperFromInt32x4", argLength: 3, commutative: false},
+               {name: "ShiftRightInt32x4", argLength: 2, commutative: false},
+               {name: "ShiftRightAndFillUpperFromInt32x4", argLength: 3, commutative: false},
+               {name: "ShiftRightSignExtendedInt32x4", argLength: 2, commutative: false},
                {name: "SignInt32x4", argLength: 2, commutative: false},
                {name: "SubInt32x4", argLength: 2, commutative: false},
                {name: "UnsignedSignedQuadDotProdAccumulateInt32x4", argLength: 3, commutative: false},
@@ -553,8 +620,15 @@ func simdGenericOps() []opData {
                {name: "MaskedOrInt32x8", argLength: 3, commutative: true},
                {name: "MaskedPairDotProdAccumulateInt32x8", argLength: 4, commutative: false},
                {name: "MaskedPopCountInt32x8", argLength: 2, commutative: false},
+               {name: "MaskedRotateLeftInt32x8", argLength: 3, commutative: false},
+               {name: "MaskedRotateRightInt32x8", argLength: 3, commutative: false},
                {name: "MaskedSaturatedPairDotProdAccumulateInt32x8", argLength: 4, commutative: false},
                {name: "MaskedSaturatedUnsignedSignedQuadDotProdAccumulateInt32x8", argLength: 4, commutative: false},
+               {name: "MaskedShiftLeftInt32x8", argLength: 3, commutative: false},
+               {name: "MaskedShiftLeftAndFillUpperFromInt32x8", argLength: 4, commutative: false},
+               {name: "MaskedShiftRightInt32x8", argLength: 3, commutative: false},
+               {name: "MaskedShiftRightAndFillUpperFromInt32x8", argLength: 4, commutative: false},
+               {name: "MaskedShiftRightSignExtendedInt32x8", argLength: 3, commutative: false},
                {name: "MaskedSubInt32x8", argLength: 3, commutative: false},
                {name: "MaskedUnsignedSignedQuadDotProdAccumulateInt32x8", argLength: 4, commutative: false},
                {name: "MaskedXorInt32x8", argLength: 3, commutative: true},
@@ -568,8 +642,18 @@ func simdGenericOps() []opData {
                {name: "PairwiseAddInt32x8", argLength: 2, commutative: false},
                {name: "PairwiseSubInt32x8", argLength: 2, commutative: false},
                {name: "PopCountInt32x8", argLength: 1, commutative: false},
+               {name: "RotateLeftInt32x8", argLength: 2, commutative: false},
+               {name: "RotateRightInt32x8", argLength: 2, commutative: false},
                {name: "SaturatedPairDotProdAccumulateInt32x8", argLength: 3, commutative: false},
                {name: "SaturatedUnsignedSignedQuadDotProdAccumulateInt32x8", argLength: 3, commutative: false},
+               {name: "ShiftAllLeftInt32x8", argLength: 2, commutative: false},
+               {name: "ShiftAllRightInt32x8", argLength: 2, commutative: false},
+               {name: "ShiftAllRightSignExtendedInt32x8", argLength: 2, commutative: false},
+               {name: "ShiftLeftInt32x8", argLength: 2, commutative: false},
+               {name: "ShiftLeftAndFillUpperFromInt32x8", argLength: 3, commutative: false},
+               {name: "ShiftRightInt32x8", argLength: 2, commutative: false},
+               {name: "ShiftRightAndFillUpperFromInt32x8", argLength: 3, commutative: false},
+               {name: "ShiftRightSignExtendedInt32x8", argLength: 2, commutative: false},
                {name: "SignInt32x8", argLength: 2, commutative: false},
                {name: "SubInt32x8", argLength: 2, commutative: false},
                {name: "UnsignedSignedQuadDotProdAccumulateInt32x8", argLength: 3, commutative: false},
@@ -599,6 +683,16 @@ func simdGenericOps() []opData {
                {name: "MaskedNotEqualInt64x2", argLength: 3, commutative: true},
                {name: "MaskedOrInt64x2", argLength: 3, commutative: true},
                {name: "MaskedPopCountInt64x2", argLength: 2, commutative: false},
+               {name: "MaskedRotateLeftInt64x2", argLength: 3, commutative: false},
+               {name: "MaskedRotateRightInt64x2", argLength: 3, commutative: false},
+               {name: "MaskedShiftAllLeftInt64x2", argLength: 3, commutative: false},
+               {name: "MaskedShiftAllRightInt64x2", argLength: 3, commutative: false},
+               {name: "MaskedShiftAllRightSignExtendedInt64x2", argLength: 3, commutative: false},
+               {name: "MaskedShiftLeftInt64x2", argLength: 3, commutative: false},
+               {name: "MaskedShiftLeftAndFillUpperFromInt64x2", argLength: 4, commutative: false},
+               {name: "MaskedShiftRightInt64x2", argLength: 3, commutative: false},
+               {name: "MaskedShiftRightAndFillUpperFromInt64x2", argLength: 4, commutative: false},
+               {name: "MaskedShiftRightSignExtendedInt64x2", argLength: 3, commutative: false},
                {name: "MaskedSubInt64x2", argLength: 3, commutative: false},
                {name: "MaskedXorInt64x2", argLength: 3, commutative: true},
                {name: "MaxInt64x2", argLength: 2, commutative: true},
@@ -608,6 +702,16 @@ func simdGenericOps() []opData {
                {name: "NotEqualInt64x2", argLength: 2, commutative: true},
                {name: "OrInt64x2", argLength: 2, commutative: true},
                {name: "PopCountInt64x2", argLength: 1, commutative: false},
+               {name: "RotateLeftInt64x2", argLength: 2, commutative: false},
+               {name: "RotateRightInt64x2", argLength: 2, commutative: false},
+               {name: "ShiftAllLeftInt64x2", argLength: 2, commutative: false},
+               {name: "ShiftAllRightInt64x2", argLength: 2, commutative: false},
+               {name: "ShiftAllRightSignExtendedInt64x2", argLength: 2, commutative: false},
+               {name: "ShiftLeftInt64x2", argLength: 2, commutative: false},
+               {name: "ShiftLeftAndFillUpperFromInt64x2", argLength: 3, commutative: false},
+               {name: "ShiftRightInt64x2", argLength: 2, commutative: false},
+               {name: "ShiftRightAndFillUpperFromInt64x2", argLength: 3, commutative: false},
+               {name: "ShiftRightSignExtendedInt64x2", argLength: 2, commutative: false},
                {name: "SubInt64x2", argLength: 2, commutative: false},
                {name: "XorInt64x2", argLength: 2, commutative: true},
                {name: "AbsoluteInt64x4", argLength: 1, commutative: false},
@@ -635,6 +739,16 @@ func simdGenericOps() []opData {
                {name: "MaskedNotEqualInt64x4", argLength: 3, commutative: true},
                {name: "MaskedOrInt64x4", argLength: 3, commutative: true},
                {name: "MaskedPopCountInt64x4", argLength: 2, commutative: false},
+               {name: "MaskedRotateLeftInt64x4", argLength: 3, commutative: false},
+               {name: "MaskedRotateRightInt64x4", argLength: 3, commutative: false},
+               {name: "MaskedShiftAllLeftInt64x4", argLength: 3, commutative: false},
+               {name: "MaskedShiftAllRightInt64x4", argLength: 3, commutative: false},
+               {name: "MaskedShiftAllRightSignExtendedInt64x4", argLength: 3, commutative: false},
+               {name: "MaskedShiftLeftInt64x4", argLength: 3, commutative: false},
+               {name: "MaskedShiftLeftAndFillUpperFromInt64x4", argLength: 4, commutative: false},
+               {name: "MaskedShiftRightInt64x4", argLength: 3, commutative: false},
+               {name: "MaskedShiftRightAndFillUpperFromInt64x4", argLength: 4, commutative: false},
+               {name: "MaskedShiftRightSignExtendedInt64x4", argLength: 3, commutative: false},
                {name: "MaskedSubInt64x4", argLength: 3, commutative: false},
                {name: "MaskedXorInt64x4", argLength: 3, commutative: true},
                {name: "MaxInt64x4", argLength: 2, commutative: true},
@@ -644,6 +758,16 @@ func simdGenericOps() []opData {
                {name: "NotEqualInt64x4", argLength: 2, commutative: true},
                {name: "OrInt64x4", argLength: 2, commutative: true},
                {name: "PopCountInt64x4", argLength: 1, commutative: false},
+               {name: "RotateLeftInt64x4", argLength: 2, commutative: false},
+               {name: "RotateRightInt64x4", argLength: 2, commutative: false},
+               {name: "ShiftAllLeftInt64x4", argLength: 2, commutative: false},
+               {name: "ShiftAllRightInt64x4", argLength: 2, commutative: false},
+               {name: "ShiftAllRightSignExtendedInt64x4", argLength: 2, commutative: false},
+               {name: "ShiftLeftInt64x4", argLength: 2, commutative: false},
+               {name: "ShiftLeftAndFillUpperFromInt64x4", argLength: 3, commutative: false},
+               {name: "ShiftRightInt64x4", argLength: 2, commutative: false},
+               {name: "ShiftRightAndFillUpperFromInt64x4", argLength: 3, commutative: false},
+               {name: "ShiftRightSignExtendedInt64x4", argLength: 2, commutative: false},
                {name: "SubInt64x4", argLength: 2, commutative: false},
                {name: "XorInt64x4", argLength: 2, commutative: true},
                {name: "AbsoluteInt64x8", argLength: 1, commutative: false},
@@ -671,6 +795,16 @@ func simdGenericOps() []opData {
                {name: "MaskedNotEqualInt64x8", argLength: 3, commutative: true},
                {name: "MaskedOrInt64x8", argLength: 3, commutative: true},
                {name: "MaskedPopCountInt64x8", argLength: 2, commutative: false},
+               {name: "MaskedRotateLeftInt64x8", argLength: 3, commutative: false},
+               {name: "MaskedRotateRightInt64x8", argLength: 3, commutative: false},
+               {name: "MaskedShiftAllLeftInt64x8", argLength: 3, commutative: false},
+               {name: "MaskedShiftAllRightInt64x8", argLength: 3, commutative: false},
+               {name: "MaskedShiftAllRightSignExtendedInt64x8", argLength: 3, commutative: false},
+               {name: "MaskedShiftLeftInt64x8", argLength: 3, commutative: false},
+               {name: "MaskedShiftLeftAndFillUpperFromInt64x8", argLength: 4, commutative: false},
+               {name: "MaskedShiftRightInt64x8", argLength: 3, commutative: false},
+               {name: "MaskedShiftRightAndFillUpperFromInt64x8", argLength: 4, commutative: false},
+               {name: "MaskedShiftRightSignExtendedInt64x8", argLength: 3, commutative: false},
                {name: "MaskedSubInt64x8", argLength: 3, commutative: false},
                {name: "MaskedXorInt64x8", argLength: 3, commutative: true},
                {name: "MaxInt64x8", argLength: 2, commutative: true},
@@ -680,6 +814,16 @@ func simdGenericOps() []opData {
                {name: "NotEqualInt64x8", argLength: 2, commutative: true},
                {name: "OrInt64x8", argLength: 2, commutative: true},
                {name: "PopCountInt64x8", argLength: 1, commutative: false},
+               {name: "RotateLeftInt64x8", argLength: 2, commutative: false},
+               {name: "RotateRightInt64x8", argLength: 2, commutative: false},
+               {name: "ShiftAllLeftInt64x8", argLength: 2, commutative: false},
+               {name: "ShiftAllRightInt64x8", argLength: 2, commutative: false},
+               {name: "ShiftAllRightSignExtendedInt64x8", argLength: 2, commutative: false},
+               {name: "ShiftLeftInt64x8", argLength: 2, commutative: false},
+               {name: "ShiftLeftAndFillUpperFromInt64x8", argLength: 3, commutative: false},
+               {name: "ShiftRightInt64x8", argLength: 2, commutative: false},
+               {name: "ShiftRightAndFillUpperFromInt64x8", argLength: 3, commutative: false},
+               {name: "ShiftRightSignExtendedInt64x8", argLength: 2, commutative: false},
                {name: "SubInt64x8", argLength: 2, commutative: false},
                {name: "XorInt64x8", argLength: 2, commutative: true},
                {name: "AbsoluteInt8x16", argLength: 1, commutative: false},
@@ -799,6 +943,11 @@ func simdGenericOps() []opData {
                {name: "MaskedPopCountUint16x16", argLength: 2, commutative: false},
                {name: "MaskedSaturatedAddUint16x16", argLength: 3, commutative: true},
                {name: "MaskedSaturatedSubUint16x16", argLength: 3, commutative: false},
+               {name: "MaskedShiftLeftUint16x16", argLength: 3, commutative: false},
+               {name: "MaskedShiftLeftAndFillUpperFromUint16x16", argLength: 4, commutative: false},
+               {name: "MaskedShiftRightUint16x16", argLength: 3, commutative: false},
+               {name: "MaskedShiftRightAndFillUpperFromUint16x16", argLength: 4, commutative: false},
+               {name: "MaskedShiftRightSignExtendedUint16x16", argLength: 3, commutative: false},
                {name: "MaskedSubUint16x16", argLength: 3, commutative: false},
                {name: "MaxUint16x16", argLength: 2, commutative: true},
                {name: "MinUint16x16", argLength: 2, commutative: true},
@@ -810,6 +959,13 @@ func simdGenericOps() []opData {
                {name: "PopCountUint16x16", argLength: 1, commutative: false},
                {name: "SaturatedAddUint16x16", argLength: 2, commutative: true},
                {name: "SaturatedSubUint16x16", argLength: 2, commutative: false},
+               {name: "ShiftAllLeftUint16x16", argLength: 2, commutative: false},
+               {name: "ShiftAllRightUint16x16", argLength: 2, commutative: false},
+               {name: "ShiftLeftUint16x16", argLength: 2, commutative: false},
+               {name: "ShiftLeftAndFillUpperFromUint16x16", argLength: 3, commutative: false},
+               {name: "ShiftRightUint16x16", argLength: 2, commutative: false},
+               {name: "ShiftRightAndFillUpperFromUint16x16", argLength: 3, commutative: false},
+               {name: "ShiftRightSignExtendedUint16x16", argLength: 2, commutative: false},
                {name: "SubUint16x16", argLength: 2, commutative: false},
                {name: "XorUint16x16", argLength: 2, commutative: true},
                {name: "AddUint16x32", argLength: 2, commutative: true},
@@ -833,6 +989,11 @@ func simdGenericOps() []opData {
                {name: "MaskedPopCountUint16x32", argLength: 2, commutative: false},
                {name: "MaskedSaturatedAddUint16x32", argLength: 3, commutative: true},
                {name: "MaskedSaturatedSubUint16x32", argLength: 3, commutative: false},
+               {name: "MaskedShiftLeftUint16x32", argLength: 3, commutative: false},
+               {name: "MaskedShiftLeftAndFillUpperFromUint16x32", argLength: 4, commutative: false},
+               {name: "MaskedShiftRightUint16x32", argLength: 3, commutative: false},
+               {name: "MaskedShiftRightAndFillUpperFromUint16x32", argLength: 4, commutative: false},
+               {name: "MaskedShiftRightSignExtendedUint16x32", argLength: 3, commutative: false},
                {name: "MaskedSubUint16x32", argLength: 3, commutative: false},
                {name: "MaxUint16x32", argLength: 2, commutative: true},
                {name: "MinUint16x32", argLength: 2, commutative: true},
@@ -841,6 +1002,11 @@ func simdGenericOps() []opData {
                {name: "PopCountUint16x32", argLength: 1, commutative: false},
                {name: "SaturatedAddUint16x32", argLength: 2, commutative: true},
                {name: "SaturatedSubUint16x32", argLength: 2, commutative: false},
+               {name: "ShiftLeftUint16x32", argLength: 2, commutative: false},
+               {name: "ShiftLeftAndFillUpperFromUint16x32", argLength: 3, commutative: false},
+               {name: "ShiftRightUint16x32", argLength: 2, commutative: false},
+               {name: "ShiftRightAndFillUpperFromUint16x32", argLength: 3, commutative: false},
+               {name: "ShiftRightSignExtendedUint16x32", argLength: 2, commutative: false},
                {name: "SubUint16x32", argLength: 2, commutative: false},
                {name: "AddUint16x8", argLength: 2, commutative: true},
                {name: "AndUint16x8", argLength: 2, commutative: true},
@@ -865,6 +1031,11 @@ func simdGenericOps() []opData {
                {name: "MaskedPopCountUint16x8", argLength: 2, commutative: false},
                {name: "MaskedSaturatedAddUint16x8", argLength: 3, commutative: true},
                {name: "MaskedSaturatedSubUint16x8", argLength: 3, commutative: false},
+               {name: "MaskedShiftLeftUint16x8", argLength: 3, commutative: false},
+               {name: "MaskedShiftLeftAndFillUpperFromUint16x8", argLength: 4, commutative: false},
+               {name: "MaskedShiftRightUint16x8", argLength: 3, commutative: false},
+               {name: "MaskedShiftRightAndFillUpperFromUint16x8", argLength: 4, commutative: false},
+               {name: "MaskedShiftRightSignExtendedUint16x8", argLength: 3, commutative: false},
                {name: "MaskedSubUint16x8", argLength: 3, commutative: false},
                {name: "MaxUint16x8", argLength: 2, commutative: true},
                {name: "MinUint16x8", argLength: 2, commutative: true},
@@ -876,6 +1047,13 @@ func simdGenericOps() []opData {
                {name: "PopCountUint16x8", argLength: 1, commutative: false},
                {name: "SaturatedAddUint16x8", argLength: 2, commutative: true},
                {name: "SaturatedSubUint16x8", argLength: 2, commutative: false},
+               {name: "ShiftAllLeftUint16x8", argLength: 2, commutative: false},
+               {name: "ShiftAllRightUint16x8", argLength: 2, commutative: false},
+               {name: "ShiftLeftUint16x8", argLength: 2, commutative: false},
+               {name: "ShiftLeftAndFillUpperFromUint16x8", argLength: 3, commutative: false},
+               {name: "ShiftRightUint16x8", argLength: 2, commutative: false},
+               {name: "ShiftRightAndFillUpperFromUint16x8", argLength: 3, commutative: false},
+               {name: "ShiftRightSignExtendedUint16x8", argLength: 2, commutative: false},
                {name: "SubUint16x8", argLength: 2, commutative: false},
                {name: "XorUint16x8", argLength: 2, commutative: true},
                {name: "AddUint32x16", argLength: 2, commutative: true},
@@ -899,7 +1077,14 @@ func simdGenericOps() []opData {
                {name: "MaskedNotEqualUint32x16", argLength: 3, commutative: true},
                {name: "MaskedOrUint32x16", argLength: 3, commutative: true},
                {name: "MaskedPopCountUint32x16", argLength: 2, commutative: false},
+               {name: "MaskedRotateLeftUint32x16", argLength: 3, commutative: false},
+               {name: "MaskedRotateRightUint32x16", argLength: 3, commutative: false},
                {name: "MaskedSaturatedUnsignedSignedQuadDotProdAccumulateUint32x16", argLength: 4, commutative: false},
+               {name: "MaskedShiftLeftUint32x16", argLength: 3, commutative: false},
+               {name: "MaskedShiftLeftAndFillUpperFromUint32x16", argLength: 4, commutative: false},
+               {name: "MaskedShiftRightUint32x16", argLength: 3, commutative: false},
+               {name: "MaskedShiftRightAndFillUpperFromUint32x16", argLength: 4, commutative: false},
+               {name: "MaskedShiftRightSignExtendedUint32x16", argLength: 3, commutative: false},
                {name: "MaskedSubUint32x16", argLength: 3, commutative: false},
                {name: "MaskedUnsignedSignedQuadDotProdAccumulateUint32x16", argLength: 4, commutative: false},
                {name: "MaskedXorUint32x16", argLength: 3, commutative: true},
@@ -908,7 +1093,14 @@ func simdGenericOps() []opData {
                {name: "NotEqualUint32x16", argLength: 2, commutative: true},
                {name: "OrUint32x16", argLength: 2, commutative: true},
                {name: "PopCountUint32x16", argLength: 1, commutative: false},
+               {name: "RotateLeftUint32x16", argLength: 2, commutative: false},
+               {name: "RotateRightUint32x16", argLength: 2, commutative: false},
                {name: "SaturatedUnsignedSignedQuadDotProdAccumulateUint32x16", argLength: 3, commutative: false},
+               {name: "ShiftLeftUint32x16", argLength: 2, commutative: false},
+               {name: "ShiftLeftAndFillUpperFromUint32x16", argLength: 3, commutative: false},
+               {name: "ShiftRightUint32x16", argLength: 2, commutative: false},
+               {name: "ShiftRightAndFillUpperFromUint32x16", argLength: 3, commutative: false},
+               {name: "ShiftRightSignExtendedUint32x16", argLength: 2, commutative: false},
                {name: "SubUint32x16", argLength: 2, commutative: false},
                {name: "UnsignedSignedQuadDotProdAccumulateUint32x16", argLength: 3, commutative: false},
                {name: "XorUint32x16", argLength: 2, commutative: true},
@@ -933,7 +1125,14 @@ func simdGenericOps() []opData {
                {name: "MaskedNotEqualUint32x4", argLength: 3, commutative: true},
                {name: "MaskedOrUint32x4", argLength: 3, commutative: true},
                {name: "MaskedPopCountUint32x4", argLength: 2, commutative: false},
+               {name: "MaskedRotateLeftUint32x4", argLength: 3, commutative: false},
+               {name: "MaskedRotateRightUint32x4", argLength: 3, commutative: false},
                {name: "MaskedSaturatedUnsignedSignedQuadDotProdAccumulateUint32x4", argLength: 4, commutative: false},
+               {name: "MaskedShiftLeftUint32x4", argLength: 3, commutative: false},
+               {name: "MaskedShiftLeftAndFillUpperFromUint32x4", argLength: 4, commutative: false},
+               {name: "MaskedShiftRightUint32x4", argLength: 3, commutative: false},
+               {name: "MaskedShiftRightAndFillUpperFromUint32x4", argLength: 4, commutative: false},
+               {name: "MaskedShiftRightSignExtendedUint32x4", argLength: 3, commutative: false},
                {name: "MaskedSubUint32x4", argLength: 3, commutative: false},
                {name: "MaskedUnsignedSignedQuadDotProdAccumulateUint32x4", argLength: 4, commutative: false},
                {name: "MaskedXorUint32x4", argLength: 3, commutative: true},
@@ -945,7 +1144,16 @@ func simdGenericOps() []opData {
                {name: "PairwiseAddUint32x4", argLength: 2, commutative: false},
                {name: "PairwiseSubUint32x4", argLength: 2, commutative: false},
                {name: "PopCountUint32x4", argLength: 1, commutative: false},
+               {name: "RotateLeftUint32x4", argLength: 2, commutative: false},
+               {name: "RotateRightUint32x4", argLength: 2, commutative: false},
                {name: "SaturatedUnsignedSignedQuadDotProdAccumulateUint32x4", argLength: 3, commutative: false},
+               {name: "ShiftAllLeftUint32x4", argLength: 2, commutative: false},
+               {name: "ShiftAllRightUint32x4", argLength: 2, commutative: false},
+               {name: "ShiftLeftUint32x4", argLength: 2, commutative: false},
+               {name: "ShiftLeftAndFillUpperFromUint32x4", argLength: 3, commutative: false},
+               {name: "ShiftRightUint32x4", argLength: 2, commutative: false},
+               {name: "ShiftRightAndFillUpperFromUint32x4", argLength: 3, commutative: false},
+               {name: "ShiftRightSignExtendedUint32x4", argLength: 2, commutative: false},
                {name: "SubUint32x4", argLength: 2, commutative: false},
                {name: "UnsignedSignedQuadDotProdAccumulateUint32x4", argLength: 3, commutative: false},
                {name: "XorUint32x4", argLength: 2, commutative: true},
@@ -970,7 +1178,14 @@ func simdGenericOps() []opData {
                {name: "MaskedNotEqualUint32x8", argLength: 3, commutative: true},
                {name: "MaskedOrUint32x8", argLength: 3, commutative: true},
                {name: "MaskedPopCountUint32x8", argLength: 2, commutative: false},
+               {name: "MaskedRotateLeftUint32x8", argLength: 3, commutative: false},
+               {name: "MaskedRotateRightUint32x8", argLength: 3, commutative: false},
                {name: "MaskedSaturatedUnsignedSignedQuadDotProdAccumulateUint32x8", argLength: 4, commutative: false},
+               {name: "MaskedShiftLeftUint32x8", argLength: 3, commutative: false},
+               {name: "MaskedShiftLeftAndFillUpperFromUint32x8", argLength: 4, commutative: false},
+               {name: "MaskedShiftRightUint32x8", argLength: 3, commutative: false},
+               {name: "MaskedShiftRightAndFillUpperFromUint32x8", argLength: 4, commutative: false},
+               {name: "MaskedShiftRightSignExtendedUint32x8", argLength: 3, commutative: false},
                {name: "MaskedSubUint32x8", argLength: 3, commutative: false},
                {name: "MaskedUnsignedSignedQuadDotProdAccumulateUint32x8", argLength: 4, commutative: false},
                {name: "MaskedXorUint32x8", argLength: 3, commutative: true},
@@ -982,7 +1197,16 @@ func simdGenericOps() []opData {
                {name: "PairwiseAddUint32x8", argLength: 2, commutative: false},
                {name: "PairwiseSubUint32x8", argLength: 2, commutative: false},
                {name: "PopCountUint32x8", argLength: 1, commutative: false},
+               {name: "RotateLeftUint32x8", argLength: 2, commutative: false},
+               {name: "RotateRightUint32x8", argLength: 2, commutative: false},
                {name: "SaturatedUnsignedSignedQuadDotProdAccumulateUint32x8", argLength: 3, commutative: false},
+               {name: "ShiftAllLeftUint32x8", argLength: 2, commutative: false},
+               {name: "ShiftAllRightUint32x8", argLength: 2, commutative: false},
+               {name: "ShiftLeftUint32x8", argLength: 2, commutative: false},
+               {name: "ShiftLeftAndFillUpperFromUint32x8", argLength: 3, commutative: false},
+               {name: "ShiftRightUint32x8", argLength: 2, commutative: false},
+               {name: "ShiftRightAndFillUpperFromUint32x8", argLength: 3, commutative: false},
+               {name: "ShiftRightSignExtendedUint32x8", argLength: 2, commutative: false},
                {name: "SubUint32x8", argLength: 2, commutative: false},
                {name: "UnsignedSignedQuadDotProdAccumulateUint32x8", argLength: 3, commutative: false},
                {name: "XorUint32x8", argLength: 2, commutative: true},
@@ -1008,6 +1232,15 @@ func simdGenericOps() []opData {
                {name: "MaskedNotEqualUint64x2", argLength: 3, commutative: true},
                {name: "MaskedOrUint64x2", argLength: 3, commutative: true},
                {name: "MaskedPopCountUint64x2", argLength: 2, commutative: false},
+               {name: "MaskedRotateLeftUint64x2", argLength: 3, commutative: false},
+               {name: "MaskedRotateRightUint64x2", argLength: 3, commutative: false},
+               {name: "MaskedShiftAllLeftUint64x2", argLength: 3, commutative: false},
+               {name: "MaskedShiftAllRightUint64x2", argLength: 3, commutative: false},
+               {name: "MaskedShiftLeftUint64x2", argLength: 3, commutative: false},
+               {name: "MaskedShiftLeftAndFillUpperFromUint64x2", argLength: 4, commutative: false},
+               {name: "MaskedShiftRightUint64x2", argLength: 3, commutative: false},
+               {name: "MaskedShiftRightAndFillUpperFromUint64x2", argLength: 4, commutative: false},
+               {name: "MaskedShiftRightSignExtendedUint64x2", argLength: 3, commutative: false},
                {name: "MaskedSubUint64x2", argLength: 3, commutative: false},
                {name: "MaskedXorUint64x2", argLength: 3, commutative: true},
                {name: "MaxUint64x2", argLength: 2, commutative: true},
@@ -1016,6 +1249,15 @@ func simdGenericOps() []opData {
                {name: "NotEqualUint64x2", argLength: 2, commutative: true},
                {name: "OrUint64x2", argLength: 2, commutative: true},
                {name: "PopCountUint64x2", argLength: 1, commutative: false},
+               {name: "RotateLeftUint64x2", argLength: 2, commutative: false},
+               {name: "RotateRightUint64x2", argLength: 2, commutative: false},
+               {name: "ShiftAllLeftUint64x2", argLength: 2, commutative: false},
+               {name: "ShiftAllRightUint64x2", argLength: 2, commutative: false},
+               {name: "ShiftLeftUint64x2", argLength: 2, commutative: false},
+               {name: "ShiftLeftAndFillUpperFromUint64x2", argLength: 3, commutative: false},
+               {name: "ShiftRightUint64x2", argLength: 2, commutative: false},
+               {name: "ShiftRightAndFillUpperFromUint64x2", argLength: 3, commutative: false},
+               {name: "ShiftRightSignExtendedUint64x2", argLength: 2, commutative: false},
                {name: "SubUint64x2", argLength: 2, commutative: false},
                {name: "XorUint64x2", argLength: 2, commutative: true},
                {name: "AddUint64x4", argLength: 2, commutative: true},
@@ -1040,6 +1282,15 @@ func simdGenericOps() []opData {
                {name: "MaskedNotEqualUint64x4", argLength: 3, commutative: true},
                {name: "MaskedOrUint64x4", argLength: 3, commutative: true},
                {name: "MaskedPopCountUint64x4", argLength: 2, commutative: false},
+               {name: "MaskedRotateLeftUint64x4", argLength: 3, commutative: false},
+               {name: "MaskedRotateRightUint64x4", argLength: 3, commutative: false},
+               {name: "MaskedShiftAllLeftUint64x4", argLength: 3, commutative: false},
+               {name: "MaskedShiftAllRightUint64x4", argLength: 3, commutative: false},
+               {name: "MaskedShiftLeftUint64x4", argLength: 3, commutative: false},
+               {name: "MaskedShiftLeftAndFillUpperFromUint64x4", argLength: 4, commutative: false},
+               {name: "MaskedShiftRightUint64x4", argLength: 3, commutative: false},
+               {name: "MaskedShiftRightAndFillUpperFromUint64x4", argLength: 4, commutative: false},
+               {name: "MaskedShiftRightSignExtendedUint64x4", argLength: 3, commutative: false},
                {name: "MaskedSubUint64x4", argLength: 3, commutative: false},
                {name: "MaskedXorUint64x4", argLength: 3, commutative: true},
                {name: "MaxUint64x4", argLength: 2, commutative: true},
@@ -1048,6 +1299,15 @@ func simdGenericOps() []opData {
                {name: "NotEqualUint64x4", argLength: 2, commutative: true},
                {name: "OrUint64x4", argLength: 2, commutative: true},
                {name: "PopCountUint64x4", argLength: 1, commutative: false},
+               {name: "RotateLeftUint64x4", argLength: 2, commutative: false},
+               {name: "RotateRightUint64x4", argLength: 2, commutative: false},
+               {name: "ShiftAllLeftUint64x4", argLength: 2, commutative: false},
+               {name: "ShiftAllRightUint64x4", argLength: 2, commutative: false},
+               {name: "ShiftLeftUint64x4", argLength: 2, commutative: false},
+               {name: "ShiftLeftAndFillUpperFromUint64x4", argLength: 3, commutative: false},
+               {name: "ShiftRightUint64x4", argLength: 2, commutative: false},
+               {name: "ShiftRightAndFillUpperFromUint64x4", argLength: 3, commutative: false},
+               {name: "ShiftRightSignExtendedUint64x4", argLength: 2, commutative: false},
                {name: "SubUint64x4", argLength: 2, commutative: false},
                {name: "XorUint64x4", argLength: 2, commutative: true},
                {name: "AddUint64x8", argLength: 2, commutative: true},
@@ -1072,6 +1332,15 @@ func simdGenericOps() []opData {
                {name: "MaskedNotEqualUint64x8", argLength: 3, commutative: true},
                {name: "MaskedOrUint64x8", argLength: 3, commutative: true},
                {name: "MaskedPopCountUint64x8", argLength: 2, commutative: false},
+               {name: "MaskedRotateLeftUint64x8", argLength: 3, commutative: false},
+               {name: "MaskedRotateRightUint64x8", argLength: 3, commutative: false},
+               {name: "MaskedShiftAllLeftUint64x8", argLength: 3, commutative: false},
+               {name: "MaskedShiftAllRightUint64x8", argLength: 3, commutative: false},
+               {name: "MaskedShiftLeftUint64x8", argLength: 3, commutative: false},
+               {name: "MaskedShiftLeftAndFillUpperFromUint64x8", argLength: 4, commutative: false},
+               {name: "MaskedShiftRightUint64x8", argLength: 3, commutative: false},
+               {name: "MaskedShiftRightAndFillUpperFromUint64x8", argLength: 4, commutative: false},
+               {name: "MaskedShiftRightSignExtendedUint64x8", argLength: 3, commutative: false},
                {name: "MaskedSubUint64x8", argLength: 3, commutative: false},
                {name: "MaskedXorUint64x8", argLength: 3, commutative: true},
                {name: "MaxUint64x8", argLength: 2, commutative: true},
@@ -1080,6 +1349,15 @@ func simdGenericOps() []opData {
                {name: "NotEqualUint64x8", argLength: 2, commutative: true},
                {name: "OrUint64x8", argLength: 2, commutative: true},
                {name: "PopCountUint64x8", argLength: 1, commutative: false},
+               {name: "RotateLeftUint64x8", argLength: 2, commutative: false},
+               {name: "RotateRightUint64x8", argLength: 2, commutative: false},
+               {name: "ShiftAllLeftUint64x8", argLength: 2, commutative: false},
+               {name: "ShiftAllRightUint64x8", argLength: 2, commutative: false},
+               {name: "ShiftLeftUint64x8", argLength: 2, commutative: false},
+               {name: "ShiftLeftAndFillUpperFromUint64x8", argLength: 3, commutative: false},
+               {name: "ShiftRightUint64x8", argLength: 2, commutative: false},
+               {name: "ShiftRightAndFillUpperFromUint64x8", argLength: 3, commutative: false},
+               {name: "ShiftRightSignExtendedUint64x8", argLength: 2, commutative: false},
                {name: "SubUint64x8", argLength: 2, commutative: false},
                {name: "XorUint64x8", argLength: 2, commutative: true},
                {name: "AddUint8x16", argLength: 2, commutative: true},
@@ -1372,20 +1650,140 @@ func simdGenericOps() []opData {
                {name: "RoundWithPrecisionFloat64x8", argLength: 1, commutative: false, aux: "Int8"},
                {name: "TruncSuppressExceptionWithPrecisionFloat64x8", argLength: 1, commutative: false, aux: "Int8"},
                {name: "TruncWithPrecisionFloat64x8", argLength: 1, commutative: false, aux: "Int8"},
+               {name: "MaskedShiftAllLeftAndFillUpperFromInt16x16", argLength: 3, commutative: false, aux: "Int8"},
+               {name: "MaskedShiftAllRightAndFillUpperFromInt16x16", argLength: 3, commutative: false, aux: "Int8"},
+               {name: "ShiftAllLeftAndFillUpperFromInt16x16", argLength: 2, commutative: false, aux: "Int8"},
+               {name: "ShiftAllRightAndFillUpperFromInt16x16", argLength: 2, commutative: false, aux: "Int8"},
+               {name: "MaskedShiftAllLeftAndFillUpperFromInt16x32", argLength: 3, commutative: false, aux: "Int8"},
+               {name: "MaskedShiftAllRightAndFillUpperFromInt16x32", argLength: 3, commutative: false, aux: "Int8"},
+               {name: "ShiftAllLeftAndFillUpperFromInt16x32", argLength: 2, commutative: false, aux: "Int8"},
+               {name: "ShiftAllRightAndFillUpperFromInt16x32", argLength: 2, commutative: false, aux: "Int8"},
                {name: "GetElemInt16x8", argLength: 1, commutative: false, aux: "Int8"},
+               {name: "MaskedShiftAllLeftAndFillUpperFromInt16x8", argLength: 3, commutative: false, aux: "Int8"},
+               {name: "MaskedShiftAllRightAndFillUpperFromInt16x8", argLength: 3, commutative: false, aux: "Int8"},
                {name: "SetElemInt16x8", argLength: 2, commutative: false, aux: "Int8"},
+               {name: "ShiftAllLeftAndFillUpperFromInt16x8", argLength: 2, commutative: false, aux: "Int8"},
+               {name: "ShiftAllRightAndFillUpperFromInt16x8", argLength: 2, commutative: false, aux: "Int8"},
+               {name: "MaskedRotateAllLeftInt32x16", argLength: 2, commutative: false, aux: "Int8"},
+               {name: "MaskedRotateAllRightInt32x16", argLength: 2, commutative: false, aux: "Int8"},
+               {name: "MaskedShiftAllLeftAndFillUpperFromInt32x16", argLength: 3, commutative: false, aux: "Int8"},
+               {name: "MaskedShiftAllRightAndFillUpperFromInt32x16", argLength: 3, commutative: false, aux: "Int8"},
+               {name: "RotateAllLeftInt32x16", argLength: 1, commutative: false, aux: "Int8"},
+               {name: "RotateAllRightInt32x16", argLength: 1, commutative: false, aux: "Int8"},
+               {name: "ShiftAllLeftAndFillUpperFromInt32x16", argLength: 2, commutative: false, aux: "Int8"},
+               {name: "ShiftAllRightAndFillUpperFromInt32x16", argLength: 2, commutative: false, aux: "Int8"},
                {name: "GetElemInt32x4", argLength: 1, commutative: false, aux: "Int8"},
+               {name: "MaskedRotateAllLeftInt32x4", argLength: 2, commutative: false, aux: "Int8"},
+               {name: "MaskedRotateAllRightInt32x4", argLength: 2, commutative: false, aux: "Int8"},
+               {name: "MaskedShiftAllLeftAndFillUpperFromInt32x4", argLength: 3, commutative: false, aux: "Int8"},
+               {name: "MaskedShiftAllRightAndFillUpperFromInt32x4", argLength: 3, commutative: false, aux: "Int8"},
+               {name: "RotateAllLeftInt32x4", argLength: 1, commutative: false, aux: "Int8"},
+               {name: "RotateAllRightInt32x4", argLength: 1, commutative: false, aux: "Int8"},
                {name: "SetElemInt32x4", argLength: 2, commutative: false, aux: "Int8"},
+               {name: "ShiftAllLeftAndFillUpperFromInt32x4", argLength: 2, commutative: false, aux: "Int8"},
+               {name: "ShiftAllRightAndFillUpperFromInt32x4", argLength: 2, commutative: false, aux: "Int8"},
+               {name: "MaskedRotateAllLeftInt32x8", argLength: 2, commutative: false, aux: "Int8"},
+               {name: "MaskedRotateAllRightInt32x8", argLength: 2, commutative: false, aux: "Int8"},
+               {name: "MaskedShiftAllLeftAndFillUpperFromInt32x8", argLength: 3, commutative: false, aux: "Int8"},
+               {name: "MaskedShiftAllRightAndFillUpperFromInt32x8", argLength: 3, commutative: false, aux: "Int8"},
+               {name: "RotateAllLeftInt32x8", argLength: 1, commutative: false, aux: "Int8"},
+               {name: "RotateAllRightInt32x8", argLength: 1, commutative: false, aux: "Int8"},
+               {name: "ShiftAllLeftAndFillUpperFromInt32x8", argLength: 2, commutative: false, aux: "Int8"},
+               {name: "ShiftAllRightAndFillUpperFromInt32x8", argLength: 2, commutative: false, aux: "Int8"},
                {name: "GetElemInt64x2", argLength: 1, commutative: false, aux: "Int8"},
+               {name: "MaskedRotateAllLeftInt64x2", argLength: 2, commutative: false, aux: "Int8"},
+               {name: "MaskedRotateAllRightInt64x2", argLength: 2, commutative: false, aux: "Int8"},
+               {name: "MaskedShiftAllLeftAndFillUpperFromInt64x2", argLength: 3, commutative: false, aux: "Int8"},
+               {name: "MaskedShiftAllRightAndFillUpperFromInt64x2", argLength: 3, commutative: false, aux: "Int8"},
+               {name: "RotateAllLeftInt64x2", argLength: 1, commutative: false, aux: "Int8"},
+               {name: "RotateAllRightInt64x2", argLength: 1, commutative: false, aux: "Int8"},
                {name: "SetElemInt64x2", argLength: 2, commutative: false, aux: "Int8"},
+               {name: "ShiftAllLeftAndFillUpperFromInt64x2", argLength: 2, commutative: false, aux: "Int8"},
+               {name: "ShiftAllRightAndFillUpperFromInt64x2", argLength: 2, commutative: false, aux: "Int8"},
+               {name: "MaskedRotateAllLeftInt64x4", argLength: 2, commutative: false, aux: "Int8"},
+               {name: "MaskedRotateAllRightInt64x4", argLength: 2, commutative: false, aux: "Int8"},
+               {name: "MaskedShiftAllLeftAndFillUpperFromInt64x4", argLength: 3, commutative: false, aux: "Int8"},
+               {name: "MaskedShiftAllRightAndFillUpperFromInt64x4", argLength: 3, commutative: false, aux: "Int8"},
+               {name: "RotateAllLeftInt64x4", argLength: 1, commutative: false, aux: "Int8"},
+               {name: "RotateAllRightInt64x4", argLength: 1, commutative: false, aux: "Int8"},
+               {name: "ShiftAllLeftAndFillUpperFromInt64x4", argLength: 2, commutative: false, aux: "Int8"},
+               {name: "ShiftAllRightAndFillUpperFromInt64x4", argLength: 2, commutative: false, aux: "Int8"},
+               {name: "MaskedRotateAllLeftInt64x8", argLength: 2, commutative: false, aux: "Int8"},
+               {name: "MaskedRotateAllRightInt64x8", argLength: 2, commutative: false, aux: "Int8"},
+               {name: "MaskedShiftAllLeftAndFillUpperFromInt64x8", argLength: 3, commutative: false, aux: "Int8"},
+               {name: "MaskedShiftAllRightAndFillUpperFromInt64x8", argLength: 3, commutative: false, aux: "Int8"},
+               {name: "RotateAllLeftInt64x8", argLength: 1, commutative: false, aux: "Int8"},
+               {name: "RotateAllRightInt64x8", argLength: 1, commutative: false, aux: "Int8"},
+               {name: "ShiftAllLeftAndFillUpperFromInt64x8", argLength: 2, commutative: false, aux: "Int8"},
+               {name: "ShiftAllRightAndFillUpperFromInt64x8", argLength: 2, commutative: false, aux: "Int8"},
                {name: "GetElemInt8x16", argLength: 1, commutative: false, aux: "Int8"},
                {name: "SetElemInt8x16", argLength: 2, commutative: false, aux: "Int8"},
+               {name: "MaskedShiftAllLeftAndFillUpperFromUint16x16", argLength: 3, commutative: false, aux: "Int8"},
+               {name: "MaskedShiftAllRightAndFillUpperFromUint16x16", argLength: 3, commutative: false, aux: "Int8"},
+               {name: "ShiftAllLeftAndFillUpperFromUint16x16", argLength: 2, commutative: false, aux: "Int8"},
+               {name: "ShiftAllRightAndFillUpperFromUint16x16", argLength: 2, commutative: false, aux: "Int8"},
+               {name: "MaskedShiftAllLeftAndFillUpperFromUint16x32", argLength: 3, commutative: false, aux: "Int8"},
+               {name: "MaskedShiftAllRightAndFillUpperFromUint16x32", argLength: 3, commutative: false, aux: "Int8"},
+               {name: "ShiftAllLeftAndFillUpperFromUint16x32", argLength: 2, commutative: false, aux: "Int8"},
+               {name: "ShiftAllRightAndFillUpperFromUint16x32", argLength: 2, commutative: false, aux: "Int8"},
                {name: "GetElemUint16x8", argLength: 1, commutative: false, aux: "Int8"},
+               {name: "MaskedShiftAllLeftAndFillUpperFromUint16x8", argLength: 3, commutative: false, aux: "Int8"},
+               {name: "MaskedShiftAllRightAndFillUpperFromUint16x8", argLength: 3, commutative: false, aux: "Int8"},
                {name: "SetElemUint16x8", argLength: 2, commutative: false, aux: "Int8"},
+               {name: "ShiftAllLeftAndFillUpperFromUint16x8", argLength: 2, commutative: false, aux: "Int8"},
+               {name: "ShiftAllRightAndFillUpperFromUint16x8", argLength: 2, commutative: false, aux: "Int8"},
+               {name: "MaskedRotateAllLeftUint32x16", argLength: 2, commutative: false, aux: "Int8"},
+               {name: "MaskedRotateAllRightUint32x16", argLength: 2, commutative: false, aux: "Int8"},
+               {name: "MaskedShiftAllLeftAndFillUpperFromUint32x16", argLength: 3, commutative: false, aux: "Int8"},
+               {name: "MaskedShiftAllRightAndFillUpperFromUint32x16", argLength: 3, commutative: false, aux: "Int8"},
+               {name: "RotateAllLeftUint32x16", argLength: 1, commutative: false, aux: "Int8"},
+               {name: "RotateAllRightUint32x16", argLength: 1, commutative: false, aux: "Int8"},
+               {name: "ShiftAllLeftAndFillUpperFromUint32x16", argLength: 2, commutative: false, aux: "Int8"},
+               {name: "ShiftAllRightAndFillUpperFromUint32x16", argLength: 2, commutative: false, aux: "Int8"},
                {name: "GetElemUint32x4", argLength: 1, commutative: false, aux: "Int8"},
+               {name: "MaskedRotateAllLeftUint32x4", argLength: 2, commutative: false, aux: "Int8"},
+               {name: "MaskedRotateAllRightUint32x4", argLength: 2, commutative: false, aux: "Int8"},
+               {name: "MaskedShiftAllLeftAndFillUpperFromUint32x4", argLength: 3, commutative: false, aux: "Int8"},
+               {name: "MaskedShiftAllRightAndFillUpperFromUint32x4", argLength: 3, commutative: false, aux: "Int8"},
+               {name: "RotateAllLeftUint32x4", argLength: 1, commutative: false, aux: "Int8"},
+               {name: "RotateAllRightUint32x4", argLength: 1, commutative: false, aux: "Int8"},
                {name: "SetElemUint32x4", argLength: 2, commutative: false, aux: "Int8"},
+               {name: "ShiftAllLeftAndFillUpperFromUint32x4", argLength: 2, commutative: false, aux: "Int8"},
+               {name: "ShiftAllRightAndFillUpperFromUint32x4", argLength: 2, commutative: false, aux: "Int8"},
+               {name: "MaskedRotateAllLeftUint32x8", argLength: 2, commutative: false, aux: "Int8"},
+               {name: "MaskedRotateAllRightUint32x8", argLength: 2, commutative: false, aux: "Int8"},
+               {name: "MaskedShiftAllLeftAndFillUpperFromUint32x8", argLength: 3, commutative: false, aux: "Int8"},
+               {name: "MaskedShiftAllRightAndFillUpperFromUint32x8", argLength: 3, commutative: false, aux: "Int8"},
+               {name: "RotateAllLeftUint32x8", argLength: 1, commutative: false, aux: "Int8"},
+               {name: "RotateAllRightUint32x8", argLength: 1, commutative: false, aux: "Int8"},
+               {name: "ShiftAllLeftAndFillUpperFromUint32x8", argLength: 2, commutative: false, aux: "Int8"},
+               {name: "ShiftAllRightAndFillUpperFromUint32x8", argLength: 2, commutative: false, aux: "Int8"},
                {name: "GetElemUint64x2", argLength: 1, commutative: false, aux: "Int8"},
+               {name: "MaskedRotateAllLeftUint64x2", argLength: 2, commutative: false, aux: "Int8"},
+               {name: "MaskedRotateAllRightUint64x2", argLength: 2, commutative: false, aux: "Int8"},
+               {name: "MaskedShiftAllLeftAndFillUpperFromUint64x2", argLength: 3, commutative: false, aux: "Int8"},
+               {name: "MaskedShiftAllRightAndFillUpperFromUint64x2", argLength: 3, commutative: false, aux: "Int8"},
+               {name: "RotateAllLeftUint64x2", argLength: 1, commutative: false, aux: "Int8"},
+               {name: "RotateAllRightUint64x2", argLength: 1, commutative: false, aux: "Int8"},
                {name: "SetElemUint64x2", argLength: 2, commutative: false, aux: "Int8"},
+               {name: "ShiftAllLeftAndFillUpperFromUint64x2", argLength: 2, commutative: false, aux: "Int8"},
+               {name: "ShiftAllRightAndFillUpperFromUint64x2", argLength: 2, commutative: false, aux: "Int8"},
+               {name: "MaskedRotateAllLeftUint64x4", argLength: 2, commutative: false, aux: "Int8"},
+               {name: "MaskedRotateAllRightUint64x4", argLength: 2, commutative: false, aux: "Int8"},
+               {name: "MaskedShiftAllLeftAndFillUpperFromUint64x4", argLength: 3, commutative: false, aux: "Int8"},
+               {name: "MaskedShiftAllRightAndFillUpperFromUint64x4", argLength: 3, commutative: false, aux: "Int8"},
+               {name: "RotateAllLeftUint64x4", argLength: 1, commutative: false, aux: "Int8"},
+               {name: "RotateAllRightUint64x4", argLength: 1, commutative: false, aux: "Int8"},
+               {name: "ShiftAllLeftAndFillUpperFromUint64x4", argLength: 2, commutative: false, aux: "Int8"},
+               {name: "ShiftAllRightAndFillUpperFromUint64x4", argLength: 2, commutative: false, aux: "Int8"},
+               {name: "MaskedRotateAllLeftUint64x8", argLength: 2, commutative: false, aux: "Int8"},
+               {name: "MaskedRotateAllRightUint64x8", argLength: 2, commutative: false, aux: "Int8"},
+               {name: "MaskedShiftAllLeftAndFillUpperFromUint64x8", argLength: 3, commutative: false, aux: "Int8"},
+               {name: "MaskedShiftAllRightAndFillUpperFromUint64x8", argLength: 3, commutative: false, aux: "Int8"},
+               {name: "RotateAllLeftUint64x8", argLength: 1, commutative: false, aux: "Int8"},
+               {name: "RotateAllRightUint64x8", argLength: 1, commutative: false, aux: "Int8"},
+               {name: "ShiftAllLeftAndFillUpperFromUint64x8", argLength: 2, commutative: false, aux: "Int8"},
+               {name: "ShiftAllRightAndFillUpperFromUint64x8", argLength: 2, commutative: false, aux: "Int8"},
                {name: "GetElemUint8x16", argLength: 1, commutative: false, aux: "Int8"},
                {name: "SetElemUint8x16", argLength: 2, commutative: false, aux: "Int8"},
        }

diff --git a/src/cmd/compile/internal/ssa/opGen.go b/src/cmd/compile/internal/ssa/opGen.go
index 7a1126d433f93c19a622297e505f238f08ea090f..2bdbd5156e1984a40e4cc18d9c89e7f98541fb4c 100644 (file)
--- a/src/cmd/compile/internal/ssa/opGen.go
+++ b/src/cmd/compile/internal/ssa/opGen.go
@@ -1426,6 +1426,11 @@ const (
        OpAMD64VPOPCNTWMasked256
        OpAMD64VPADDSWMasked256
        OpAMD64VPSUBSWMasked256
+       OpAMD64VPSLLVWMasked256
+       OpAMD64VPSHLDVWMasked256
+       OpAMD64VPSRLVWMasked256
+       OpAMD64VPSHRDVWMasked256
+       OpAMD64VPSRAVWMasked256
        OpAMD64VPSUBWMasked256
        OpAMD64VPMAXSW256
        OpAMD64VPMINSW256
@@ -1439,6 +1444,14 @@ const (
        OpAMD64VPHADDSW256
        OpAMD64VPHSUBSW256
        OpAMD64VPSUBSW256
+       OpAMD64VPSLLW256
+       OpAMD64VPSRLW256
+       OpAMD64VPSRAW256
+       OpAMD64VPSLLVW256
+       OpAMD64VPSHLDVW256
+       OpAMD64VPSRLVW256
+       OpAMD64VPSHRDVW256
+       OpAMD64VPSRAVW256
        OpAMD64VPSIGNW256
        OpAMD64VPSUBW256
        OpAMD64VPABSW512
@@ -1453,6 +1466,11 @@ const (
        OpAMD64VPOPCNTWMasked512
        OpAMD64VPADDSWMasked512
        OpAMD64VPSUBSWMasked512
+       OpAMD64VPSLLVWMasked512
+       OpAMD64VPSHLDVWMasked512
+       OpAMD64VPSRLVWMasked512
+       OpAMD64VPSHRDVWMasked512
+       OpAMD64VPSRAVWMasked512
        OpAMD64VPSUBWMasked512
        OpAMD64VPMAXSW512
        OpAMD64VPMINSW512
@@ -1462,6 +1480,11 @@ const (
        OpAMD64VPOPCNTW512
        OpAMD64VPADDSW512
        OpAMD64VPSUBSW512
+       OpAMD64VPSLLVW512
+       OpAMD64VPSHLDVW512
+       OpAMD64VPSRLVW512
+       OpAMD64VPSHRDVW512
+       OpAMD64VPSRAVW512
        OpAMD64VPSUBW512
        OpAMD64VPABSW128
        OpAMD64VPADDW128
@@ -1477,6 +1500,11 @@ const (
        OpAMD64VPOPCNTWMasked128
        OpAMD64VPADDSWMasked128
        OpAMD64VPSUBSWMasked128
+       OpAMD64VPSLLVWMasked128
+       OpAMD64VPSHLDVWMasked128
+       OpAMD64VPSRLVWMasked128
+       OpAMD64VPSHRDVWMasked128
+       OpAMD64VPSRAVWMasked128
        OpAMD64VPSUBWMasked128
        OpAMD64VPMAXSW128
        OpAMD64VPMINSW128
@@ -1490,6 +1518,14 @@ const (
        OpAMD64VPHADDSW128
        OpAMD64VPHSUBSW128
        OpAMD64VPSUBSW128
+       OpAMD64VPSLLW128
+       OpAMD64VPSRLW128
+       OpAMD64VPSRAW128
+       OpAMD64VPSLLVW128
+       OpAMD64VPSHLDVW128
+       OpAMD64VPSRLVW128
+       OpAMD64VPSHRDVW128
+       OpAMD64VPSRAVW128
        OpAMD64VPSIGNW128
        OpAMD64VPSUBW128
        OpAMD64VPABSD512
@@ -1506,8 +1542,15 @@ const (
        OpAMD64VPORDMasked512
        OpAMD64VPDPWSSDMasked512
        OpAMD64VPOPCNTDMasked512
+       OpAMD64VPROLVDMasked512
+       OpAMD64VPRORVDMasked512
        OpAMD64VPDPWSSDSMasked512
        OpAMD64VPDPBUSDSMasked512
+       OpAMD64VPSLLVDMasked512
+       OpAMD64VPSHLDVDMasked512
+       OpAMD64VPSRLVDMasked512
+       OpAMD64VPSHRDVDMasked512
+       OpAMD64VPSRAVDMasked512
        OpAMD64VPSUBDMasked512
        OpAMD64VPDPBUSDMasked512
        OpAMD64VPXORDMasked512
@@ -1517,8 +1560,15 @@ const (
        OpAMD64VPORD512
        OpAMD64VPDPWSSD512
        OpAMD64VPOPCNTD512
+       OpAMD64VPROLVD512
+       OpAMD64VPRORVD512
        OpAMD64VPDPWSSDS512
        OpAMD64VPDPBUSDS512
+       OpAMD64VPSLLVD512
+       OpAMD64VPSHLDVD512
+       OpAMD64VPSRLVD512
+       OpAMD64VPSHRDVD512
+       OpAMD64VPSRAVD512
        OpAMD64VPSUBD512
        OpAMD64VPDPBUSD512
        OpAMD64VPXORD512
@@ -1536,8 +1586,15 @@ const (
        OpAMD64VPORDMasked128
        OpAMD64VPDPWSSDMasked128
        OpAMD64VPOPCNTDMasked128
+       OpAMD64VPROLVDMasked128
+       OpAMD64VPRORVDMasked128
        OpAMD64VPDPWSSDSMasked128
        OpAMD64VPDPBUSDSMasked128
+       OpAMD64VPSLLVDMasked128
+       OpAMD64VPSHLDVDMasked128
+       OpAMD64VPSRLVDMasked128
+       OpAMD64VPSHRDVDMasked128
+       OpAMD64VPSRAVDMasked128
        OpAMD64VPSUBDMasked128
        OpAMD64VPDPBUSDMasked128
        OpAMD64VPXORDMasked128
@@ -1549,8 +1606,18 @@ const (
        OpAMD64VPHADDD128
        OpAMD64VPHSUBD128
        OpAMD64VPOPCNTD128
+       OpAMD64VPROLVD128
+       OpAMD64VPRORVD128
        OpAMD64VPDPWSSDS128
        OpAMD64VPDPBUSDS128
+       OpAMD64VPSLLD128
+       OpAMD64VPSRLD128
+       OpAMD64VPSRAD128
+       OpAMD64VPSLLVD128
+       OpAMD64VPSHLDVD128
+       OpAMD64VPSRLVD128
+       OpAMD64VPSHRDVD128
+       OpAMD64VPSRAVD128
        OpAMD64VPSIGND128
        OpAMD64VPSUBD128
        OpAMD64VPDPBUSD128
@@ -1568,8 +1635,15 @@ const (
        OpAMD64VPORDMasked256
        OpAMD64VPDPWSSDMasked256
        OpAMD64VPOPCNTDMasked256
+       OpAMD64VPROLVDMasked256
+       OpAMD64VPRORVDMasked256
        OpAMD64VPDPWSSDSMasked256
        OpAMD64VPDPBUSDSMasked256
+       OpAMD64VPSLLVDMasked256
+       OpAMD64VPSHLDVDMasked256
+       OpAMD64VPSRLVDMasked256
+       OpAMD64VPSHRDVDMasked256
+       OpAMD64VPSRAVDMasked256
        OpAMD64VPSUBDMasked256
        OpAMD64VPDPBUSDMasked256
        OpAMD64VPXORDMasked256
@@ -1581,8 +1655,18 @@ const (
        OpAMD64VPHADDD256
        OpAMD64VPHSUBD256
        OpAMD64VPOPCNTD256
+       OpAMD64VPROLVD256
+       OpAMD64VPRORVD256
        OpAMD64VPDPWSSDS256
        OpAMD64VPDPBUSDS256
+       OpAMD64VPSLLD256
+       OpAMD64VPSRLD256
+       OpAMD64VPSRAD256
+       OpAMD64VPSLLVD256
+       OpAMD64VPSHLDVD256
+       OpAMD64VPSRLVD256
+       OpAMD64VPSHRDVD256
+       OpAMD64VPSRAVD256
        OpAMD64VPSIGND256
        OpAMD64VPSUBD256
        OpAMD64VPDPBUSD256
@@ -1599,12 +1683,32 @@ const (
        OpAMD64VPMULLQMasked128
        OpAMD64VPORQMasked128
        OpAMD64VPOPCNTQMasked128
+       OpAMD64VPROLVQMasked128
+       OpAMD64VPRORVQMasked128
+       OpAMD64VPSLLQMasked128
+       OpAMD64VPSRLQMasked128
+       OpAMD64VPSRAQMasked128
+       OpAMD64VPSLLVQMasked128
+       OpAMD64VPSHLDVQMasked128
+       OpAMD64VPSRLVQMasked128
+       OpAMD64VPSHRDVQMasked128
+       OpAMD64VPSRAVQMasked128
        OpAMD64VPSUBQMasked128
        OpAMD64VPXORQMasked128
        OpAMD64VPMAXSQ128
        OpAMD64VPMINSQ128
        OpAMD64VPMULLQ128
        OpAMD64VPOPCNTQ128
+       OpAMD64VPROLVQ128
+       OpAMD64VPRORVQ128
+       OpAMD64VPSLLQ128
+       OpAMD64VPSRLQ128
+       OpAMD64VPSRAQ128
+       OpAMD64VPSLLVQ128
+       OpAMD64VPSHLDVQ128
+       OpAMD64VPSRLVQ128
+       OpAMD64VPSHRDVQ128
+       OpAMD64VPSRAVQ128
        OpAMD64VPSUBQ128
        OpAMD64VPABSQ256
        OpAMD64VPADDQ256
@@ -1620,12 +1724,32 @@ const (
        OpAMD64VPMULLQMasked256
        OpAMD64VPORQMasked256
        OpAMD64VPOPCNTQMasked256
+       OpAMD64VPROLVQMasked256
+       OpAMD64VPRORVQMasked256
+       OpAMD64VPSLLQMasked256
+       OpAMD64VPSRLQMasked256
+       OpAMD64VPSRAQMasked256
+       OpAMD64VPSLLVQMasked256
+       OpAMD64VPSHLDVQMasked256
+       OpAMD64VPSRLVQMasked256
+       OpAMD64VPSHRDVQMasked256
+       OpAMD64VPSRAVQMasked256
        OpAMD64VPSUBQMasked256
        OpAMD64VPXORQMasked256
        OpAMD64VPMAXSQ256
        OpAMD64VPMINSQ256
        OpAMD64VPMULLQ256
        OpAMD64VPOPCNTQ256
+       OpAMD64VPROLVQ256
+       OpAMD64VPRORVQ256
+       OpAMD64VPSLLQ256
+       OpAMD64VPSRLQ256
+       OpAMD64VPSRAQ256
+       OpAMD64VPSLLVQ256
+       OpAMD64VPSHLDVQ256
+       OpAMD64VPSRLVQ256
+       OpAMD64VPSHRDVQ256
+       OpAMD64VPSRAVQ256
        OpAMD64VPSUBQ256
        OpAMD64VPABSQ512
        OpAMD64VPADDQ512
@@ -1641,6 +1765,16 @@ const (
        OpAMD64VPMULLQMasked512
        OpAMD64VPORQMasked512
        OpAMD64VPOPCNTQMasked512
+       OpAMD64VPROLVQMasked512
+       OpAMD64VPRORVQMasked512
+       OpAMD64VPSLLQMasked512
+       OpAMD64VPSRLQMasked512
+       OpAMD64VPSRAQMasked512
+       OpAMD64VPSLLVQMasked512
+       OpAMD64VPSHLDVQMasked512
+       OpAMD64VPSRLVQMasked512
+       OpAMD64VPSHRDVQMasked512
+       OpAMD64VPSRAVQMasked512
        OpAMD64VPSUBQMasked512
        OpAMD64VPXORQMasked512
        OpAMD64VPMAXSQ512
@@ -1649,6 +1783,16 @@ const (
        OpAMD64VPMULLQ512
        OpAMD64VPORQ512
        OpAMD64VPOPCNTQ512
+       OpAMD64VPROLVQ512
+       OpAMD64VPRORVQ512
+       OpAMD64VPSLLQ512
+       OpAMD64VPSRLQ512
+       OpAMD64VPSRAQ512
+       OpAMD64VPSLLVQ512
+       OpAMD64VPSHLDVQ512
+       OpAMD64VPSRLVQ512
+       OpAMD64VPSHRDVQ512
+       OpAMD64VPSRAVQ512
        OpAMD64VPSUBQ512
        OpAMD64VPXORQ512
        OpAMD64VPABSB128
@@ -1834,28 +1978,88 @@ const (
        OpAMD64VCMPPDMasked512
        OpAMD64VPCMPW256
        OpAMD64VPCMPWMasked256
+       OpAMD64VPSHLDWMasked256
+       OpAMD64VPSHRDWMasked256
+       OpAMD64VPSHLDW256
+       OpAMD64VPSHRDW256
        OpAMD64VPCMPW512
        OpAMD64VPCMPWMasked512
+       OpAMD64VPSHLDWMasked512
+       OpAMD64VPSHRDWMasked512
+       OpAMD64VPSHLDW512
+       OpAMD64VPSHRDW512
        OpAMD64VPEXTRW128
        OpAMD64VPCMPW128
        OpAMD64VPCMPWMasked128
+       OpAMD64VPSHLDWMasked128
+       OpAMD64VPSHRDWMasked128
        OpAMD64VPINSRW128
+       OpAMD64VPSHLDW128
+       OpAMD64VPSHRDW128
        OpAMD64VPCMPD512
        OpAMD64VPCMPDMasked512
+       OpAMD64VPROLDMasked512
+       OpAMD64VPRORDMasked512
+       OpAMD64VPSHLDDMasked512
+       OpAMD64VPSHRDDMasked512
+       OpAMD64VPROLD512
+       OpAMD64VPRORD512
+       OpAMD64VPSHLDD512
+       OpAMD64VPSHRDD512
        OpAMD64VPEXTRD128
        OpAMD64VPCMPD128
        OpAMD64VPCMPDMasked128
+       OpAMD64VPROLDMasked128
+       OpAMD64VPRORDMasked128
+       OpAMD64VPSHLDDMasked128
+       OpAMD64VPSHRDDMasked128
+       OpAMD64VPROLD128
+       OpAMD64VPRORD128
        OpAMD64VPINSRD128
+       OpAMD64VPSHLDD128
+       OpAMD64VPSHRDD128
        OpAMD64VPCMPD256
        OpAMD64VPCMPDMasked256
+       OpAMD64VPROLDMasked256
+       OpAMD64VPRORDMasked256
+       OpAMD64VPSHLDDMasked256
+       OpAMD64VPSHRDDMasked256
+       OpAMD64VPROLD256
+       OpAMD64VPRORD256
+       OpAMD64VPSHLDD256
+       OpAMD64VPSHRDD256
        OpAMD64VPEXTRQ128
        OpAMD64VPCMPQ128
        OpAMD64VPCMPQMasked128
+       OpAMD64VPROLQMasked128
+       OpAMD64VPRORQMasked128
+       OpAMD64VPSHLDQMasked128
+       OpAMD64VPSHRDQMasked128
+       OpAMD64VPROLQ128
+       OpAMD64VPRORQ128
        OpAMD64VPINSRQ128
+       OpAMD64VPSHLDQ128
+       OpAMD64VPSHRDQ128
        OpAMD64VPCMPQ256
        OpAMD64VPCMPQMasked256
+       OpAMD64VPROLQMasked256
+       OpAMD64VPRORQMasked256
+       OpAMD64VPSHLDQMasked256
+       OpAMD64VPSHRDQMasked256
+       OpAMD64VPROLQ256
+       OpAMD64VPRORQ256
+       OpAMD64VPSHLDQ256
+       OpAMD64VPSHRDQ256
        OpAMD64VPCMPQ512
        OpAMD64VPCMPQMasked512
+       OpAMD64VPROLQMasked512
+       OpAMD64VPRORQMasked512
+       OpAMD64VPSHLDQMasked512
+       OpAMD64VPSHRDQMasked512
+       OpAMD64VPROLQ512
+       OpAMD64VPRORQ512
+       OpAMD64VPSHLDQ512
+       OpAMD64VPSHRDQ512
        OpAMD64VPEXTRB128
        OpAMD64VPCMPB128
        OpAMD64VPCMPBMasked128
@@ -4456,6 +4660,11 @@ const (
        OpMaskedPopCountInt16x16
        OpMaskedSaturatedAddInt16x16
        OpMaskedSaturatedSubInt16x16
+       OpMaskedShiftLeftInt16x16
+       OpMaskedShiftLeftAndFillUpperFromInt16x16
+       OpMaskedShiftRightInt16x16
+       OpMaskedShiftRightAndFillUpperFromInt16x16
+       OpMaskedShiftRightSignExtendedInt16x16
        OpMaskedSubInt16x16
        OpMaxInt16x16
        OpMinInt16x16
@@ -4471,6 +4680,14 @@ const (
        OpSaturatedPairwiseAddInt16x16
        OpSaturatedPairwiseSubInt16x16
        OpSaturatedSubInt16x16
+       OpShiftAllLeftInt16x16
+       OpShiftAllRightInt16x16
+       OpShiftAllRightSignExtendedInt16x16
+       OpShiftLeftInt16x16
+       OpShiftLeftAndFillUpperFromInt16x16
+       OpShiftRightInt16x16
+       OpShiftRightAndFillUpperFromInt16x16
+       OpShiftRightSignExtendedInt16x16
        OpSignInt16x16
        OpSubInt16x16
        OpXorInt16x16
@@ -4497,6 +4714,11 @@ const (
        OpMaskedPopCountInt16x32
        OpMaskedSaturatedAddInt16x32
        OpMaskedSaturatedSubInt16x32
+       OpMaskedShiftLeftInt16x32
+       OpMaskedShiftLeftAndFillUpperFromInt16x32
+       OpMaskedShiftRightInt16x32
+       OpMaskedShiftRightAndFillUpperFromInt16x32
+       OpMaskedShiftRightSignExtendedInt16x32
        OpMaskedSubInt16x32
        OpMaxInt16x32
        OpMinInt16x32
@@ -4507,6 +4729,11 @@ const (
        OpPopCountInt16x32
        OpSaturatedAddInt16x32
        OpSaturatedSubInt16x32
+       OpShiftLeftInt16x32
+       OpShiftLeftAndFillUpperFromInt16x32
+       OpShiftRightInt16x32
+       OpShiftRightAndFillUpperFromInt16x32
+       OpShiftRightSignExtendedInt16x32
        OpSubInt16x32
        OpAbsoluteInt16x8
        OpAddInt16x8
@@ -4533,6 +4760,11 @@ const (
        OpMaskedPopCountInt16x8
        OpMaskedSaturatedAddInt16x8
        OpMaskedSaturatedSubInt16x8
+       OpMaskedShiftLeftInt16x8
+       OpMaskedShiftLeftAndFillUpperFromInt16x8
+       OpMaskedShiftRightInt16x8
+       OpMaskedShiftRightAndFillUpperFromInt16x8
+       OpMaskedShiftRightSignExtendedInt16x8
        OpMaskedSubInt16x8
        OpMaxInt16x8
        OpMinInt16x8
@@ -4548,6 +4780,14 @@ const (
        OpSaturatedPairwiseAddInt16x8
        OpSaturatedPairwiseSubInt16x8
        OpSaturatedSubInt16x8
+       OpShiftAllLeftInt16x8
+       OpShiftAllRightInt16x8
+       OpShiftAllRightSignExtendedInt16x8
+       OpShiftLeftInt16x8
+       OpShiftLeftAndFillUpperFromInt16x8
+       OpShiftRightInt16x8
+       OpShiftRightAndFillUpperFromInt16x8
+       OpShiftRightSignExtendedInt16x8
        OpSignInt16x8
        OpSubInt16x8
        OpXorInt16x8
@@ -4576,8 +4816,15 @@ const (
        OpMaskedOrInt32x16
        OpMaskedPairDotProdAccumulateInt32x16
        OpMaskedPopCountInt32x16
+       OpMaskedRotateLeftInt32x16
+       OpMaskedRotateRightInt32x16
        OpMaskedSaturatedPairDotProdAccumulateInt32x16
        OpMaskedSaturatedUnsignedSignedQuadDotProdAccumulateInt32x16
+       OpMaskedShiftLeftInt32x16
+       OpMaskedShiftLeftAndFillUpperFromInt32x16
+       OpMaskedShiftRightInt32x16
+       OpMaskedShiftRightAndFillUpperFromInt32x16
+       OpMaskedShiftRightSignExtendedInt32x16
        OpMaskedSubInt32x16
        OpMaskedUnsignedSignedQuadDotProdAccumulateInt32x16
        OpMaskedXorInt32x16
@@ -4588,8 +4835,15 @@ const (
        OpOrInt32x16
        OpPairDotProdAccumulateInt32x16
        OpPopCountInt32x16
+       OpRotateLeftInt32x16
+       OpRotateRightInt32x16
        OpSaturatedPairDotProdAccumulateInt32x16
        OpSaturatedUnsignedSignedQuadDotProdAccumulateInt32x16
+       OpShiftLeftInt32x16
+       OpShiftLeftAndFillUpperFromInt32x16
+       OpShiftRightInt32x16
+       OpShiftRightAndFillUpperFromInt32x16
+       OpShiftRightSignExtendedInt32x16
        OpSubInt32x16
        OpUnsignedSignedQuadDotProdAccumulateInt32x16
        OpXorInt32x16
@@ -4618,8 +4872,15 @@ const (
        OpMaskedOrInt32x4
        OpMaskedPairDotProdAccumulateInt32x4
        OpMaskedPopCountInt32x4
+       OpMaskedRotateLeftInt32x4
+       OpMaskedRotateRightInt32x4
        OpMaskedSaturatedPairDotProdAccumulateInt32x4
        OpMaskedSaturatedUnsignedSignedQuadDotProdAccumulateInt32x4
+       OpMaskedShiftLeftInt32x4
+       OpMaskedShiftLeftAndFillUpperFromInt32x4
+       OpMaskedShiftRightInt32x4
+       OpMaskedShiftRightAndFillUpperFromInt32x4
+       OpMaskedShiftRightSignExtendedInt32x4
        OpMaskedSubInt32x4
        OpMaskedUnsignedSignedQuadDotProdAccumulateInt32x4
        OpMaskedXorInt32x4
@@ -4633,8 +4894,18 @@ const (
        OpPairwiseAddInt32x4
        OpPairwiseSubInt32x4
        OpPopCountInt32x4
+       OpRotateLeftInt32x4
+       OpRotateRightInt32x4
        OpSaturatedPairDotProdAccumulateInt32x4
        OpSaturatedUnsignedSignedQuadDotProdAccumulateInt32x4
+       OpShiftAllLeftInt32x4
+       OpShiftAllRightInt32x4
+       OpShiftAllRightSignExtendedInt32x4
+       OpShiftLeftInt32x4
+       OpShiftLeftAndFillUpperFromInt32x4
+       OpShiftRightInt32x4
+       OpShiftRightAndFillUpperFromInt32x4
+       OpShiftRightSignExtendedInt32x4
        OpSignInt32x4
        OpSubInt32x4
        OpUnsignedSignedQuadDotProdAccumulateInt32x4
@@ -4664,8 +4935,15 @@ const (
        OpMaskedOrInt32x8
        OpMaskedPairDotProdAccumulateInt32x8
        OpMaskedPopCountInt32x8
+       OpMaskedRotateLeftInt32x8
+       OpMaskedRotateRightInt32x8
        OpMaskedSaturatedPairDotProdAccumulateInt32x8
        OpMaskedSaturatedUnsignedSignedQuadDotProdAccumulateInt32x8
+       OpMaskedShiftLeftInt32x8
+       OpMaskedShiftLeftAndFillUpperFromInt32x8
+       OpMaskedShiftRightInt32x8
+       OpMaskedShiftRightAndFillUpperFromInt32x8
+       OpMaskedShiftRightSignExtendedInt32x8
        OpMaskedSubInt32x8
        OpMaskedUnsignedSignedQuadDotProdAccumulateInt32x8
        OpMaskedXorInt32x8
@@ -4679,8 +4957,18 @@ const (
        OpPairwiseAddInt32x8
        OpPairwiseSubInt32x8
        OpPopCountInt32x8
+       OpRotateLeftInt32x8
+       OpRotateRightInt32x8
        OpSaturatedPairDotProdAccumulateInt32x8
        OpSaturatedUnsignedSignedQuadDotProdAccumulateInt32x8
+       OpShiftAllLeftInt32x8
+       OpShiftAllRightInt32x8
+       OpShiftAllRightSignExtendedInt32x8
+       OpShiftLeftInt32x8
+       OpShiftLeftAndFillUpperFromInt32x8
+       OpShiftRightInt32x8
+       OpShiftRightAndFillUpperFromInt32x8
+       OpShiftRightSignExtendedInt32x8
        OpSignInt32x8
        OpSubInt32x8
        OpUnsignedSignedQuadDotProdAccumulateInt32x8
@@ -4710,6 +4998,16 @@ const (
        OpMaskedNotEqualInt64x2
        OpMaskedOrInt64x2
        OpMaskedPopCountInt64x2
+       OpMaskedRotateLeftInt64x2
+       OpMaskedRotateRightInt64x2
+       OpMaskedShiftAllLeftInt64x2
+       OpMaskedShiftAllRightInt64x2
+       OpMaskedShiftAllRightSignExtendedInt64x2
+       OpMaskedShiftLeftInt64x2
+       OpMaskedShiftLeftAndFillUpperFromInt64x2
+       OpMaskedShiftRightInt64x2
+       OpMaskedShiftRightAndFillUpperFromInt64x2
+       OpMaskedShiftRightSignExtendedInt64x2
        OpMaskedSubInt64x2
        OpMaskedXorInt64x2
        OpMaxInt64x2
@@ -4719,6 +5017,16 @@ const (
        OpNotEqualInt64x2
        OpOrInt64x2
        OpPopCountInt64x2
+       OpRotateLeftInt64x2
+       OpRotateRightInt64x2
+       OpShiftAllLeftInt64x2
+       OpShiftAllRightInt64x2
+       OpShiftAllRightSignExtendedInt64x2
+       OpShiftLeftInt64x2
+       OpShiftLeftAndFillUpperFromInt64x2
+       OpShiftRightInt64x2
+       OpShiftRightAndFillUpperFromInt64x2
+       OpShiftRightSignExtendedInt64x2
        OpSubInt64x2
        OpXorInt64x2
        OpAbsoluteInt64x4
@@ -4746,6 +5054,16 @@ const (
        OpMaskedNotEqualInt64x4
        OpMaskedOrInt64x4
        OpMaskedPopCountInt64x4
+       OpMaskedRotateLeftInt64x4
+       OpMaskedRotateRightInt64x4
+       OpMaskedShiftAllLeftInt64x4
+       OpMaskedShiftAllRightInt64x4
+       OpMaskedShiftAllRightSignExtendedInt64x4
+       OpMaskedShiftLeftInt64x4
+       OpMaskedShiftLeftAndFillUpperFromInt64x4
+       OpMaskedShiftRightInt64x4
+       OpMaskedShiftRightAndFillUpperFromInt64x4
+       OpMaskedShiftRightSignExtendedInt64x4
        OpMaskedSubInt64x4
        OpMaskedXorInt64x4
        OpMaxInt64x4
@@ -4755,6 +5073,16 @@ const (
        OpNotEqualInt64x4
        OpOrInt64x4
        OpPopCountInt64x4
+       OpRotateLeftInt64x4
+       OpRotateRightInt64x4
+       OpShiftAllLeftInt64x4
+       OpShiftAllRightInt64x4
+       OpShiftAllRightSignExtendedInt64x4
+       OpShiftLeftInt64x4
+       OpShiftLeftAndFillUpperFromInt64x4
+       OpShiftRightInt64x4
+       OpShiftRightAndFillUpperFromInt64x4
+       OpShiftRightSignExtendedInt64x4
        OpSubInt64x4
        OpXorInt64x4
        OpAbsoluteInt64x8
@@ -4782,6 +5110,16 @@ const (
        OpMaskedNotEqualInt64x8
        OpMaskedOrInt64x8
        OpMaskedPopCountInt64x8
+       OpMaskedRotateLeftInt64x8
+       OpMaskedRotateRightInt64x8
+       OpMaskedShiftAllLeftInt64x8
+       OpMaskedShiftAllRightInt64x8
+       OpMaskedShiftAllRightSignExtendedInt64x8
+       OpMaskedShiftLeftInt64x8
+       OpMaskedShiftLeftAndFillUpperFromInt64x8
+       OpMaskedShiftRightInt64x8
+       OpMaskedShiftRightAndFillUpperFromInt64x8
+       OpMaskedShiftRightSignExtendedInt64x8
        OpMaskedSubInt64x8
        OpMaskedXorInt64x8
        OpMaxInt64x8
@@ -4791,6 +5129,16 @@ const (
        OpNotEqualInt64x8
        OpOrInt64x8
        OpPopCountInt64x8
+       OpRotateLeftInt64x8
+       OpRotateRightInt64x8
+       OpShiftAllLeftInt64x8
+       OpShiftAllRightInt64x8
+       OpShiftAllRightSignExtendedInt64x8
+       OpShiftLeftInt64x8
+       OpShiftLeftAndFillUpperFromInt64x8
+       OpShiftRightInt64x8
+       OpShiftRightAndFillUpperFromInt64x8
+       OpShiftRightSignExtendedInt64x8
        OpSubInt64x8
        OpXorInt64x8
        OpAbsoluteInt8x16
@@ -4910,6 +5258,11 @@ const (
        OpMaskedPopCountUint16x16
        OpMaskedSaturatedAddUint16x16
        OpMaskedSaturatedSubUint16x16
+       OpMaskedShiftLeftUint16x16
+       OpMaskedShiftLeftAndFillUpperFromUint16x16
+       OpMaskedShiftRightUint16x16
+       OpMaskedShiftRightAndFillUpperFromUint16x16
+       OpMaskedShiftRightSignExtendedUint16x16
        OpMaskedSubUint16x16
        OpMaxUint16x16
        OpMinUint16x16
@@ -4921,6 +5274,13 @@ const (
        OpPopCountUint16x16
        OpSaturatedAddUint16x16
        OpSaturatedSubUint16x16
+       OpShiftAllLeftUint16x16
+       OpShiftAllRightUint16x16
+       OpShiftLeftUint16x16
+       OpShiftLeftAndFillUpperFromUint16x16
+       OpShiftRightUint16x16
+       OpShiftRightAndFillUpperFromUint16x16
+       OpShiftRightSignExtendedUint16x16
        OpSubUint16x16
        OpXorUint16x16
        OpAddUint16x32
@@ -4944,6 +5304,11 @@ const (
        OpMaskedPopCountUint16x32
        OpMaskedSaturatedAddUint16x32
        OpMaskedSaturatedSubUint16x32
+       OpMaskedShiftLeftUint16x32
+       OpMaskedShiftLeftAndFillUpperFromUint16x32
+       OpMaskedShiftRightUint16x32
+       OpMaskedShiftRightAndFillUpperFromUint16x32
+       OpMaskedShiftRightSignExtendedUint16x32
        OpMaskedSubUint16x32
        OpMaxUint16x32
        OpMinUint16x32
@@ -4952,6 +5317,11 @@ const (
        OpPopCountUint16x32
        OpSaturatedAddUint16x32
        OpSaturatedSubUint16x32
+       OpShiftLeftUint16x32
+       OpShiftLeftAndFillUpperFromUint16x32
+       OpShiftRightUint16x32
+       OpShiftRightAndFillUpperFromUint16x32
+       OpShiftRightSignExtendedUint16x32
        OpSubUint16x32
        OpAddUint16x8
        OpAndUint16x8
@@ -4976,6 +5346,11 @@ const (
        OpMaskedPopCountUint16x8
        OpMaskedSaturatedAddUint16x8
        OpMaskedSaturatedSubUint16x8
+       OpMaskedShiftLeftUint16x8
+       OpMaskedShiftLeftAndFillUpperFromUint16x8
+       OpMaskedShiftRightUint16x8
+       OpMaskedShiftRightAndFillUpperFromUint16x8
+       OpMaskedShiftRightSignExtendedUint16x8
        OpMaskedSubUint16x8
        OpMaxUint16x8
        OpMinUint16x8
@@ -4987,6 +5362,13 @@ const (
        OpPopCountUint16x8
        OpSaturatedAddUint16x8
        OpSaturatedSubUint16x8
+       OpShiftAllLeftUint16x8
+       OpShiftAllRightUint16x8
+       OpShiftLeftUint16x8
+       OpShiftLeftAndFillUpperFromUint16x8
+       OpShiftRightUint16x8
+       OpShiftRightAndFillUpperFromUint16x8
+       OpShiftRightSignExtendedUint16x8
        OpSubUint16x8
        OpXorUint16x8
        OpAddUint32x16
@@ -5010,7 +5392,14 @@ const (
        OpMaskedNotEqualUint32x16
        OpMaskedOrUint32x16
        OpMaskedPopCountUint32x16
+       OpMaskedRotateLeftUint32x16
+       OpMaskedRotateRightUint32x16
        OpMaskedSaturatedUnsignedSignedQuadDotProdAccumulateUint32x16
+       OpMaskedShiftLeftUint32x16
+       OpMaskedShiftLeftAndFillUpperFromUint32x16
+       OpMaskedShiftRightUint32x16
+       OpMaskedShiftRightAndFillUpperFromUint32x16
+       OpMaskedShiftRightSignExtendedUint32x16
        OpMaskedSubUint32x16
        OpMaskedUnsignedSignedQuadDotProdAccumulateUint32x16
        OpMaskedXorUint32x16
@@ -5019,7 +5408,14 @@ const (
        OpNotEqualUint32x16
        OpOrUint32x16
        OpPopCountUint32x16
+       OpRotateLeftUint32x16
+       OpRotateRightUint32x16
        OpSaturatedUnsignedSignedQuadDotProdAccumulateUint32x16
+       OpShiftLeftUint32x16
+       OpShiftLeftAndFillUpperFromUint32x16
+       OpShiftRightUint32x16
+       OpShiftRightAndFillUpperFromUint32x16
+       OpShiftRightSignExtendedUint32x16
        OpSubUint32x16
        OpUnsignedSignedQuadDotProdAccumulateUint32x16
        OpXorUint32x16
@@ -5044,7 +5440,14 @@ const (
        OpMaskedNotEqualUint32x4
        OpMaskedOrUint32x4
        OpMaskedPopCountUint32x4
+       OpMaskedRotateLeftUint32x4
+       OpMaskedRotateRightUint32x4
        OpMaskedSaturatedUnsignedSignedQuadDotProdAccumulateUint32x4
+       OpMaskedShiftLeftUint32x4
+       OpMaskedShiftLeftAndFillUpperFromUint32x4
+       OpMaskedShiftRightUint32x4
+       OpMaskedShiftRightAndFillUpperFromUint32x4
+       OpMaskedShiftRightSignExtendedUint32x4
        OpMaskedSubUint32x4
        OpMaskedUnsignedSignedQuadDotProdAccumulateUint32x4
        OpMaskedXorUint32x4
@@ -5056,7 +5459,16 @@ const (
        OpPairwiseAddUint32x4
        OpPairwiseSubUint32x4
        OpPopCountUint32x4
+       OpRotateLeftUint32x4
+       OpRotateRightUint32x4
        OpSaturatedUnsignedSignedQuadDotProdAccumulateUint32x4
+       OpShiftAllLeftUint32x4
+       OpShiftAllRightUint32x4
+       OpShiftLeftUint32x4
+       OpShiftLeftAndFillUpperFromUint32x4
+       OpShiftRightUint32x4
+       OpShiftRightAndFillUpperFromUint32x4
+       OpShiftRightSignExtendedUint32x4
        OpSubUint32x4
        OpUnsignedSignedQuadDotProdAccumulateUint32x4
        OpXorUint32x4
@@ -5081,7 +5493,14 @@ const (
        OpMaskedNotEqualUint32x8
        OpMaskedOrUint32x8
        OpMaskedPopCountUint32x8
+       OpMaskedRotateLeftUint32x8
+       OpMaskedRotateRightUint32x8
        OpMaskedSaturatedUnsignedSignedQuadDotProdAccumulateUint32x8
+       OpMaskedShiftLeftUint32x8
+       OpMaskedShiftLeftAndFillUpperFromUint32x8
+       OpMaskedShiftRightUint32x8
+       OpMaskedShiftRightAndFillUpperFromUint32x8
+       OpMaskedShiftRightSignExtendedUint32x8
        OpMaskedSubUint32x8
        OpMaskedUnsignedSignedQuadDotProdAccumulateUint32x8
        OpMaskedXorUint32x8
@@ -5093,7 +5512,16 @@ const (
        OpPairwiseAddUint32x8
        OpPairwiseSubUint32x8
        OpPopCountUint32x8
+       OpRotateLeftUint32x8
+       OpRotateRightUint32x8
        OpSaturatedUnsignedSignedQuadDotProdAccumulateUint32x8
+       OpShiftAllLeftUint32x8
+       OpShiftAllRightUint32x8
+       OpShiftLeftUint32x8
+       OpShiftLeftAndFillUpperFromUint32x8
+       OpShiftRightUint32x8
+       OpShiftRightAndFillUpperFromUint32x8
+       OpShiftRightSignExtendedUint32x8
        OpSubUint32x8
        OpUnsignedSignedQuadDotProdAccumulateUint32x8
        OpXorUint32x8
@@ -5119,6 +5547,15 @@ const (
        OpMaskedNotEqualUint64x2
        OpMaskedOrUint64x2
        OpMaskedPopCountUint64x2
+       OpMaskedRotateLeftUint64x2
+       OpMaskedRotateRightUint64x2
+       OpMaskedShiftAllLeftUint64x2
+       OpMaskedShiftAllRightUint64x2
+       OpMaskedShiftLeftUint64x2
+       OpMaskedShiftLeftAndFillUpperFromUint64x2
+       OpMaskedShiftRightUint64x2
+       OpMaskedShiftRightAndFillUpperFromUint64x2
+       OpMaskedShiftRightSignExtendedUint64x2
        OpMaskedSubUint64x2
        OpMaskedXorUint64x2
        OpMaxUint64x2
@@ -5127,6 +5564,15 @@ const (
        OpNotEqualUint64x2
        OpOrUint64x2
        OpPopCountUint64x2
+       OpRotateLeftUint64x2
+       OpRotateRightUint64x2
+       OpShiftAllLeftUint64x2
+       OpShiftAllRightUint64x2
+       OpShiftLeftUint64x2
+       OpShiftLeftAndFillUpperFromUint64x2
+       OpShiftRightUint64x2
+       OpShiftRightAndFillUpperFromUint64x2
+       OpShiftRightSignExtendedUint64x2
        OpSubUint64x2
        OpXorUint64x2
        OpAddUint64x4
@@ -5151,6 +5597,15 @@ const (
        OpMaskedNotEqualUint64x4
        OpMaskedOrUint64x4
        OpMaskedPopCountUint64x4
+       OpMaskedRotateLeftUint64x4
+       OpMaskedRotateRightUint64x4
+       OpMaskedShiftAllLeftUint64x4
+       OpMaskedShiftAllRightUint64x4
+       OpMaskedShiftLeftUint64x4
+       OpMaskedShiftLeftAndFillUpperFromUint64x4
+       OpMaskedShiftRightUint64x4
+       OpMaskedShiftRightAndFillUpperFromUint64x4
+       OpMaskedShiftRightSignExtendedUint64x4
        OpMaskedSubUint64x4
        OpMaskedXorUint64x4
        OpMaxUint64x4
@@ -5159,6 +5614,15 @@ const (
        OpNotEqualUint64x4
        OpOrUint64x4
        OpPopCountUint64x4
+       OpRotateLeftUint64x4
+       OpRotateRightUint64x4
+       OpShiftAllLeftUint64x4
+       OpShiftAllRightUint64x4
+       OpShiftLeftUint64x4
+       OpShiftLeftAndFillUpperFromUint64x4
+       OpShiftRightUint64x4
+       OpShiftRightAndFillUpperFromUint64x4
+       OpShiftRightSignExtendedUint64x4
        OpSubUint64x4
        OpXorUint64x4
        OpAddUint64x8
@@ -5183,6 +5647,15 @@ const (
        OpMaskedNotEqualUint64x8
        OpMaskedOrUint64x8
        OpMaskedPopCountUint64x8
+       OpMaskedRotateLeftUint64x8
+       OpMaskedRotateRightUint64x8
+       OpMaskedShiftAllLeftUint64x8
+       OpMaskedShiftAllRightUint64x8
+       OpMaskedShiftLeftUint64x8
+       OpMaskedShiftLeftAndFillUpperFromUint64x8
+       OpMaskedShiftRightUint64x8
+       OpMaskedShiftRightAndFillUpperFromUint64x8
+       OpMaskedShiftRightSignExtendedUint64x8
        OpMaskedSubUint64x8
        OpMaskedXorUint64x8
        OpMaxUint64x8
@@ -5191,6 +5664,15 @@ const (
        OpNotEqualUint64x8
        OpOrUint64x8
        OpPopCountUint64x8
+       OpRotateLeftUint64x8
+       OpRotateRightUint64x8
+       OpShiftAllLeftUint64x8
+       OpShiftAllRightUint64x8
+       OpShiftLeftUint64x8
+       OpShiftLeftAndFillUpperFromUint64x8
+       OpShiftRightUint64x8
+       OpShiftRightAndFillUpperFromUint64x8
+       OpShiftRightSignExtendedUint64x8
        OpSubUint64x8
        OpXorUint64x8
        OpAddUint8x16
@@ -5483,20 +5965,140 @@ const (
        OpRoundWithPrecisionFloat64x8
        OpTruncSuppressExceptionWithPrecisionFloat64x8
        OpTruncWithPrecisionFloat64x8
+       OpMaskedShiftAllLeftAndFillUpperFromInt16x16
+       OpMaskedShiftAllRightAndFillUpperFromInt16x16
+       OpShiftAllLeftAndFillUpperFromInt16x16
+       OpShiftAllRightAndFillUpperFromInt16x16
+       OpMaskedShiftAllLeftAndFillUpperFromInt16x32
+       OpMaskedShiftAllRightAndFillUpperFromInt16x32
+       OpShiftAllLeftAndFillUpperFromInt16x32
+       OpShiftAllRightAndFillUpperFromInt16x32
        OpGetElemInt16x8
+       OpMaskedShiftAllLeftAndFillUpperFromInt16x8
+       OpMaskedShiftAllRightAndFillUpperFromInt16x8
        OpSetElemInt16x8
+       OpShiftAllLeftAndFillUpperFromInt16x8
+       OpShiftAllRightAndFillUpperFromInt16x8
+       OpMaskedRotateAllLeftInt32x16
+       OpMaskedRotateAllRightInt32x16
+       OpMaskedShiftAllLeftAndFillUpperFromInt32x16
+       OpMaskedShiftAllRightAndFillUpperFromInt32x16
+       OpRotateAllLeftInt32x16
+       OpRotateAllRightInt32x16
+       OpShiftAllLeftAndFillUpperFromInt32x16
+       OpShiftAllRightAndFillUpperFromInt32x16
        OpGetElemInt32x4
+       OpMaskedRotateAllLeftInt32x4
+       OpMaskedRotateAllRightInt32x4
+       OpMaskedShiftAllLeftAndFillUpperFromInt32x4
+       OpMaskedShiftAllRightAndFillUpperFromInt32x4
+       OpRotateAllLeftInt32x4
+       OpRotateAllRightInt32x4
        OpSetElemInt32x4
+       OpShiftAllLeftAndFillUpperFromInt32x4
+       OpShiftAllRightAndFillUpperFromInt32x4
+       OpMaskedRotateAllLeftInt32x8
+       OpMaskedRotateAllRightInt32x8
+       OpMaskedShiftAllLeftAndFillUpperFromInt32x8
+       OpMaskedShiftAllRightAndFillUpperFromInt32x8
+       OpRotateAllLeftInt32x8
+       OpRotateAllRightInt32x8
+       OpShiftAllLeftAndFillUpperFromInt32x8
+       OpShiftAllRightAndFillUpperFromInt32x8
        OpGetElemInt64x2
+       OpMaskedRotateAllLeftInt64x2
+       OpMaskedRotateAllRightInt64x2
+       OpMaskedShiftAllLeftAndFillUpperFromInt64x2
+       OpMaskedShiftAllRightAndFillUpperFromInt64x2
+       OpRotateAllLeftInt64x2
+       OpRotateAllRightInt64x2
        OpSetElemInt64x2
+       OpShiftAllLeftAndFillUpperFromInt64x2
+       OpShiftAllRightAndFillUpperFromInt64x2
+       OpMaskedRotateAllLeftInt64x4
+       OpMaskedRotateAllRightInt64x4
+       OpMaskedShiftAllLeftAndFillUpperFromInt64x4
+       OpMaskedShiftAllRightAndFillUpperFromInt64x4
+       OpRotateAllLeftInt64x4
+       OpRotateAllRightInt64x4
+       OpShiftAllLeftAndFillUpperFromInt64x4
+       OpShiftAllRightAndFillUpperFromInt64x4
+       OpMaskedRotateAllLeftInt64x8
+       OpMaskedRotateAllRightInt64x8
+       OpMaskedShiftAllLeftAndFillUpperFromInt64x8
+       OpMaskedShiftAllRightAndFillUpperFromInt64x8
+       OpRotateAllLeftInt64x8
+       OpRotateAllRightInt64x8
+       OpShiftAllLeftAndFillUpperFromInt64x8
+       OpShiftAllRightAndFillUpperFromInt64x8
        OpGetElemInt8x16
        OpSetElemInt8x16
+       OpMaskedShiftAllLeftAndFillUpperFromUint16x16
+       OpMaskedShiftAllRightAndFillUpperFromUint16x16
+       OpShiftAllLeftAndFillUpperFromUint16x16
+       OpShiftAllRightAndFillUpperFromUint16x16
+       OpMaskedShiftAllLeftAndFillUpperFromUint16x32
+       OpMaskedShiftAllRightAndFillUpperFromUint16x32
+       OpShiftAllLeftAndFillUpperFromUint16x32
+       OpShiftAllRightAndFillUpperFromUint16x32
        OpGetElemUint16x8
+       OpMaskedShiftAllLeftAndFillUpperFromUint16x8
+       OpMaskedShiftAllRightAndFillUpperFromUint16x8
        OpSetElemUint16x8
+       OpShiftAllLeftAndFillUpperFromUint16x8
+       OpShiftAllRightAndFillUpperFromUint16x8
+       OpMaskedRotateAllLeftUint32x16
+       OpMaskedRotateAllRightUint32x16
+       OpMaskedShiftAllLeftAndFillUpperFromUint32x16
+       OpMaskedShiftAllRightAndFillUpperFromUint32x16
+       OpRotateAllLeftUint32x16
+       OpRotateAllRightUint32x16
+       OpShiftAllLeftAndFillUpperFromUint32x16
+       OpShiftAllRightAndFillUpperFromUint32x16
        OpGetElemUint32x4
+       OpMaskedRotateAllLeftUint32x4
+       OpMaskedRotateAllRightUint32x4
+       OpMaskedShiftAllLeftAndFillUpperFromUint32x4
+       OpMaskedShiftAllRightAndFillUpperFromUint32x4
+       OpRotateAllLeftUint32x4
+       OpRotateAllRightUint32x4
        OpSetElemUint32x4
+       OpShiftAllLeftAndFillUpperFromUint32x4
+       OpShiftAllRightAndFillUpperFromUint32x4
+       OpMaskedRotateAllLeftUint32x8
+       OpMaskedRotateAllRightUint32x8
+       OpMaskedShiftAllLeftAndFillUpperFromUint32x8
+       OpMaskedShiftAllRightAndFillUpperFromUint32x8
+       OpRotateAllLeftUint32x8
+       OpRotateAllRightUint32x8
+       OpShiftAllLeftAndFillUpperFromUint32x8
+       OpShiftAllRightAndFillUpperFromUint32x8
        OpGetElemUint64x2
+       OpMaskedRotateAllLeftUint64x2
+       OpMaskedRotateAllRightUint64x2
+       OpMaskedShiftAllLeftAndFillUpperFromUint64x2
+       OpMaskedShiftAllRightAndFillUpperFromUint64x2
+       OpRotateAllLeftUint64x2
+       OpRotateAllRightUint64x2
        OpSetElemUint64x2
+       OpShiftAllLeftAndFillUpperFromUint64x2
+       OpShiftAllRightAndFillUpperFromUint64x2
+       OpMaskedRotateAllLeftUint64x4
+       OpMaskedRotateAllRightUint64x4
+       OpMaskedShiftAllLeftAndFillUpperFromUint64x4
+       OpMaskedShiftAllRightAndFillUpperFromUint64x4
+       OpRotateAllLeftUint64x4
+       OpRotateAllRightUint64x4
+       OpShiftAllLeftAndFillUpperFromUint64x4
+       OpShiftAllRightAndFillUpperFromUint64x4
+       OpMaskedRotateAllLeftUint64x8
+       OpMaskedRotateAllRightUint64x8
+       OpMaskedShiftAllLeftAndFillUpperFromUint64x8
+       OpMaskedShiftAllRightAndFillUpperFromUint64x8
+       OpRotateAllLeftUint64x8
+       OpRotateAllRightUint64x8
+       OpShiftAllLeftAndFillUpperFromUint64x8
+       OpShiftAllRightAndFillUpperFromUint64x8
        OpGetElemUint8x16
        OpSetElemUint8x16
 )
@@ -21551,6 +22153,85 @@ var opcodeTable = [...]opInfo{
                        },
                },
        },
+       {
+               name:   "VPSLLVWMasked256",
+               argLen: 3,
+               asm:    x86.AVPSLLVW,
+               reg: regInfo{
+                       inputs: []inputInfo{
+                               {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7
+                               {0, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {1, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                       },
+                       outputs: []outputInfo{
+                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                       },
+               },
+       },
+       {
+               name:         "VPSHLDVWMasked256",
+               argLen:       4,
+               resultInArg0: true,
+               asm:          x86.AVPSHLDVW,
+               reg: regInfo{
+                       inputs: []inputInfo{
+                               {3, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7
+                               {0, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {1, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {2, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                       },
+                       outputs: []outputInfo{
+                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                       },
+               },
+       },
+       {
+               name:   "VPSRLVWMasked256",
+               argLen: 3,
+               asm:    x86.AVPSRLVW,
+               reg: regInfo{
+                       inputs: []inputInfo{
+                               {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7
+                               {0, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {1, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                       },
+                       outputs: []outputInfo{
+                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                       },
+               },
+       },
+       {
+               name:         "VPSHRDVWMasked256",
+               argLen:       4,
+               resultInArg0: true,
+               asm:          x86.AVPSHRDVW,
+               reg: regInfo{
+                       inputs: []inputInfo{
+                               {3, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7
+                               {0, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {1, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {2, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                       },
+                       outputs: []outputInfo{
+                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                       },
+               },
+       },
+       {
+               name:   "VPSRAVWMasked256",
+               argLen: 3,
+               asm:    x86.AVPSRAVW,
+               reg: regInfo{
+                       inputs: []inputInfo{
+                               {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7
+                               {0, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {1, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                       },
+                       outputs: []outputInfo{
+                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                       },
+               },
+       },
        {
                name:   "VPSUBWMasked256",
                argLen: 3,
@@ -21738,6 +22419,122 @@ var opcodeTable = [...]opInfo{
                        },
                },
        },
+       {
+               name:   "VPSLLW256",
+               argLen: 2,
+               asm:    x86.AVPSLLW,
+               reg: regInfo{
+                       inputs: []inputInfo{
+                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                       },
+                       outputs: []outputInfo{
+                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                       },
+               },
+       },
+       {
+               name:   "VPSRLW256",
+               argLen: 2,
+               asm:    x86.AVPSRLW,
+               reg: regInfo{
+                       inputs: []inputInfo{
+                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                       },
+                       outputs: []outputInfo{
+                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                       },
+               },
+       },
+       {
+               name:   "VPSRAW256",
+               argLen: 2,
+               asm:    x86.AVPSRAW,
+               reg: regInfo{
+                       inputs: []inputInfo{
+                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                       },
+                       outputs: []outputInfo{
+                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                       },
+               },
+       },
+       {
+               name:   "VPSLLVW256",
+               argLen: 2,
+               asm:    x86.AVPSLLVW,
+               reg: regInfo{
+                       inputs: []inputInfo{
+                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                       },
+                       outputs: []outputInfo{
+                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                       },
+               },
+       },
+       {
+               name:         "VPSHLDVW256",
+               argLen:       3,
+               resultInArg0: true,
+               asm:          x86.AVPSHLDVW,
+               reg: regInfo{
+                       inputs: []inputInfo{
+                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                       },
+                       outputs: []outputInfo{
+                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                       },
+               },
+       },
+       {
+               name:   "VPSRLVW256",
+               argLen: 2,
+               asm:    x86.AVPSRLVW,
+               reg: regInfo{
+                       inputs: []inputInfo{
+                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                       },
+                       outputs: []outputInfo{
+                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                       },
+               },
+       },
+       {
+               name:         "VPSHRDVW256",
+               argLen:       3,
+               resultInArg0: true,
+               asm:          x86.AVPSHRDVW,
+               reg: regInfo{
+                       inputs: []inputInfo{
+                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                       },
+                       outputs: []outputInfo{
+                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                       },
+               },
+       },
+       {
+               name:   "VPSRAVW256",
+               argLen: 2,
+               asm:    x86.AVPSRAVW,
+               reg: regInfo{
+                       inputs: []inputInfo{
+                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                       },
+                       outputs: []outputInfo{
+                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                       },
+               },
+       },
        {
                name:   "VPSIGNW256",
                argLen: 2,
@@ -21948,6 +22745,85 @@ var opcodeTable = [...]opInfo{
                        },
                },
        },
+       {
+               name:   "VPSLLVWMasked512",
+               argLen: 3,
+               asm:    x86.AVPSLLVW,
+               reg: regInfo{
+                       inputs: []inputInfo{
+                               {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7
+                               {0, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {1, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                       },
+                       outputs: []outputInfo{
+                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                       },
+               },
+       },
+       {
+               name:         "VPSHLDVWMasked512",
+               argLen:       4,
+               resultInArg0: true,
+               asm:          x86.AVPSHLDVW,
+               reg: regInfo{
+                       inputs: []inputInfo{
+                               {3, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7
+                               {0, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {1, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {2, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                       },
+                       outputs: []outputInfo{
+                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                       },
+               },
+       },
+       {
+               name:   "VPSRLVWMasked512",
+               argLen: 3,
+               asm:    x86.AVPSRLVW,
+               reg: regInfo{
+                       inputs: []inputInfo{
+                               {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7
+                               {0, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {1, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                       },
+                       outputs: []outputInfo{
+                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                       },
+               },
+       },
+       {
+               name:         "VPSHRDVWMasked512",
+               argLen:       4,
+               resultInArg0: true,
+               asm:          x86.AVPSHRDVW,
+               reg: regInfo{
+                       inputs: []inputInfo{
+                               {3, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7
+                               {0, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {1, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {2, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                       },
+                       outputs: []outputInfo{
+                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                       },
+               },
+       },
+       {
+               name:   "VPSRAVWMasked512",
+               argLen: 3,
+               asm:    x86.AVPSRAVW,
+               reg: regInfo{
+                       inputs: []inputInfo{
+                               {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7
+                               {0, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {1, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                       },
+                       outputs: []outputInfo{
+                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                       },
+               },
+       },
        {
                name:   "VPSUBWMasked512",
                argLen: 3,
@@ -22079,6 +22955,80 @@ var opcodeTable = [...]opInfo{
                        },
                },
        },
+       {
+               name:   "VPSLLVW512",
+               argLen: 2,
+               asm:    x86.AVPSLLVW,
+               reg: regInfo{
+                       inputs: []inputInfo{
+                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                       },
+                       outputs: []outputInfo{
+                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                       },
+               },
+       },
+       {
+               name:         "VPSHLDVW512",
+               argLen:       3,
+               resultInArg0: true,
+               asm:          x86.AVPSHLDVW,
+               reg: regInfo{
+                       inputs: []inputInfo{
+                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                       },
+                       outputs: []outputInfo{
+                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                       },
+               },
+       },
+       {
+               name:   "VPSRLVW512",
+               argLen: 2,
+               asm:    x86.AVPSRLVW,
+               reg: regInfo{
+                       inputs: []inputInfo{
+                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                       },
+                       outputs: []outputInfo{
+                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                       },
+               },
+       },
+       {
+               name:         "VPSHRDVW512",
+               argLen:       3,
+               resultInArg0: true,
+               asm:          x86.AVPSHRDVW,
+               reg: regInfo{
+                       inputs: []inputInfo{
+                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                       },
+                       outputs: []outputInfo{
+                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                       },
+               },
+       },
+       {
+               name:   "VPSRAVW512",
+               argLen: 2,
+               asm:    x86.AVPSRAVW,
+               reg: regInfo{
+                       inputs: []inputInfo{
+                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                       },
+                       outputs: []outputInfo{
+                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                       },
+               },
+       },
        {
                name:   "VPSUBW512",
                argLen: 2,
@@ -22304,6 +23254,85 @@ var opcodeTable = [...]opInfo{
                        },
                },
        },
+       {
+               name:   "VPSLLVWMasked128",
+               argLen: 3,
+               asm:    x86.AVPSLLVW,
+               reg: regInfo{
+                       inputs: []inputInfo{
+                               {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7
+                               {0, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {1, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                       },
+                       outputs: []outputInfo{
+                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                       },
+               },
+       },
+       {
+               name:         "VPSHLDVWMasked128",
+               argLen:       4,
+               resultInArg0: true,
+               asm:          x86.AVPSHLDVW,
+               reg: regInfo{
+                       inputs: []inputInfo{
+                               {3, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7
+                               {0, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {1, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {2, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                       },
+                       outputs: []outputInfo{
+                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                       },
+               },
+       },
+       {
+               name:   "VPSRLVWMasked128",
+               argLen: 3,
+               asm:    x86.AVPSRLVW,
+               reg: regInfo{
+                       inputs: []inputInfo{
+                               {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7
+                               {0, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {1, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                       },
+                       outputs: []outputInfo{
+                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                       },
+               },
+       },
+       {
+               name:         "VPSHRDVWMasked128",
+               argLen:       4,
+               resultInArg0: true,
+               asm:          x86.AVPSHRDVW,
+               reg: regInfo{
+                       inputs: []inputInfo{
+                               {3, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7
+                               {0, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {1, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {2, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                       },
+                       outputs: []outputInfo{
+                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                       },
+               },
+       },
+       {
+               name:   "VPSRAVWMasked128",
+               argLen: 3,
+               asm:    x86.AVPSRAVW,
+               reg: regInfo{
+                       inputs: []inputInfo{
+                               {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7
+                               {0, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {1, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                       },
+                       outputs: []outputInfo{
+                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                       },
+               },
+       },
        {
                name:   "VPSUBWMasked128",
                argLen: 3,
@@ -22491,6 +23520,122 @@ var opcodeTable = [...]opInfo{
                        },
                },
        },
+       {
+               name:   "VPSLLW128",
+               argLen: 2,
+               asm:    x86.AVPSLLW,
+               reg: regInfo{
+                       inputs: []inputInfo{
+                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                       },
+                       outputs: []outputInfo{
+                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                       },
+               },
+       },
+       {
+               name:   "VPSRLW128",
+               argLen: 2,
+               asm:    x86.AVPSRLW,
+               reg: regInfo{
+                       inputs: []inputInfo{
+                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                       },
+                       outputs: []outputInfo{
+                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                       },
+               },
+       },
+       {
+               name:   "VPSRAW128",
+               argLen: 2,
+               asm:    x86.AVPSRAW,
+               reg: regInfo{
+                       inputs: []inputInfo{
+                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                       },
+                       outputs: []outputInfo{
+                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                       },
+               },
+       },
+       {
+               name:   "VPSLLVW128",
+               argLen: 2,
+               asm:    x86.AVPSLLVW,
+               reg: regInfo{
+                       inputs: []inputInfo{
+                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                       },
+                       outputs: []outputInfo{
+                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                       },
+               },
+       },
+       {
+               name:         "VPSHLDVW128",
+               argLen:       3,
+               resultInArg0: true,
+               asm:          x86.AVPSHLDVW,
+               reg: regInfo{
+                       inputs: []inputInfo{
+                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                       },
+                       outputs: []outputInfo{
+                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                       },
+               },
+       },
+       {
+               name:   "VPSRLVW128",
+               argLen: 2,
+               asm:    x86.AVPSRLVW,
+               reg: regInfo{
+                       inputs: []inputInfo{
+                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                       },
+                       outputs: []outputInfo{
+                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                       },
+               },
+       },
+       {
+               name:         "VPSHRDVW128",
+               argLen:       3,
+               resultInArg0: true,
+               asm:          x86.AVPSHRDVW,
+               reg: regInfo{
+                       inputs: []inputInfo{
+                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                       },
+                       outputs: []outputInfo{
+                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                       },
+               },
+       },
+       {
+               name:   "VPSRAVW128",
+               argLen: 2,
+               asm:    x86.AVPSRAVW,
+               reg: regInfo{
+                       inputs: []inputInfo{
+                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                       },
+                       outputs: []outputInfo{
+                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                       },
+               },
+       },
        {
                name:   "VPSIGNW128",
                argLen: 2,
@@ -22732,6 +23877,36 @@ var opcodeTable = [...]opInfo{
                        },
                },
        },
+       {
+               name:   "VPROLVDMasked512",
+               argLen: 3,
+               asm:    x86.AVPROLVD,
+               reg: regInfo{
+                       inputs: []inputInfo{
+                               {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7
+                               {0, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {1, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                       },
+                       outputs: []outputInfo{
+                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                       },
+               },
+       },
+       {
+               name:   "VPRORVDMasked512",
+               argLen: 3,
+               asm:    x86.AVPRORVD,
+               reg: regInfo{
+                       inputs: []inputInfo{
+                               {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7
+                               {0, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {1, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                       },
+                       outputs: []outputInfo{
+                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                       },
+               },
+       },
        {
                name:         "VPDPWSSDSMasked512",
                argLen:       4,
@@ -22766,6 +23941,85 @@ var opcodeTable = [...]opInfo{
                        },
                },
        },
+       {
+               name:   "VPSLLVDMasked512",
+               argLen: 3,
+               asm:    x86.AVPSLLVD,
+               reg: regInfo{
+                       inputs: []inputInfo{
+                               {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7
+                               {0, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {1, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                       },
+                       outputs: []outputInfo{
+                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                       },
+               },
+       },
+       {
+               name:         "VPSHLDVDMasked512",
+               argLen:       4,
+               resultInArg0: true,
+               asm:          x86.AVPSHLDVD,
+               reg: regInfo{
+                       inputs: []inputInfo{
+                               {3, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7
+                               {0, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {1, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {2, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                       },
+                       outputs: []outputInfo{
+                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                       },
+               },
+       },
+       {
+               name:   "VPSRLVDMasked512",
+               argLen: 3,
+               asm:    x86.AVPSRLVD,
+               reg: regInfo{
+                       inputs: []inputInfo{
+                               {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7
+                               {0, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {1, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                       },
+                       outputs: []outputInfo{
+                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                       },
+               },
+       },
+       {
+               name:         "VPSHRDVDMasked512",
+               argLen:       4,
+               resultInArg0: true,
+               asm:          x86.AVPSHRDVD,
+               reg: regInfo{
+                       inputs: []inputInfo{
+                               {3, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7
+                               {0, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {1, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {2, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                       },
+                       outputs: []outputInfo{
+                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                       },
+               },
+       },
+       {
+               name:   "VPSRAVDMasked512",
+               argLen: 3,
+               asm:    x86.AVPSRAVD,
+               reg: regInfo{
+                       inputs: []inputInfo{
+                               {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7
+                               {0, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {1, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                       },
+                       outputs: []outputInfo{
+                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                       },
+               },
+       },
        {
                name:   "VPSUBDMasked512",
                argLen: 3,
@@ -22903,6 +24157,34 @@ var opcodeTable = [...]opInfo{
                        },
                },
        },
+       {
+               name:   "VPROLVD512",
+               argLen: 2,
+               asm:    x86.AVPROLVD,
+               reg: regInfo{
+                       inputs: []inputInfo{
+                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                       },
+                       outputs: []outputInfo{
+                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                       },
+               },
+       },
+       {
+               name:   "VPRORVD512",
+               argLen: 2,
+               asm:    x86.AVPRORVD,
+               reg: regInfo{
+                       inputs: []inputInfo{
+                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                       },
+                       outputs: []outputInfo{
+                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                       },
+               },
+       },
        {
                name:         "VPDPWSSDS512",
                argLen:       3,
@@ -22935,6 +24217,80 @@ var opcodeTable = [...]opInfo{
                        },
                },
        },
+       {
+               name:   "VPSLLVD512",
+               argLen: 2,
+               asm:    x86.AVPSLLVD,
+               reg: regInfo{
+                       inputs: []inputInfo{
+                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                       },
+                       outputs: []outputInfo{
+                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                       },
+               },
+       },
+       {
+               name:         "VPSHLDVD512",
+               argLen:       3,
+               resultInArg0: true,
+               asm:          x86.AVPSHLDVD,
+               reg: regInfo{
+                       inputs: []inputInfo{
+                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                       },
+                       outputs: []outputInfo{
+                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                       },
+               },
+       },
+       {
+               name:   "VPSRLVD512",
+               argLen: 2,
+               asm:    x86.AVPSRLVD,
+               reg: regInfo{
+                       inputs: []inputInfo{
+                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                       },
+                       outputs: []outputInfo{
+                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                       },
+               },
+       },
+       {
+               name:         "VPSHRDVD512",
+               argLen:       3,
+               resultInArg0: true,
+               asm:          x86.AVPSHRDVD,
+               reg: regInfo{
+                       inputs: []inputInfo{
+                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                       },
+                       outputs: []outputInfo{
+                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                       },
+               },
+       },
+       {
+               name:   "VPSRAVD512",
+               argLen: 2,
+               asm:    x86.AVPSRAVD,
+               reg: regInfo{
+                       inputs: []inputInfo{
+                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                       },
+                       outputs: []outputInfo{
+                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                       },
+               },
+       },
        {
                name:   "VPSUBD512",
                argLen: 2,
@@ -23193,6 +24549,36 @@ var opcodeTable = [...]opInfo{
                        },
                },
        },
+       {
+               name:   "VPROLVDMasked128",
+               argLen: 3,
+               asm:    x86.AVPROLVD,
+               reg: regInfo{
+                       inputs: []inputInfo{
+                               {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7
+                               {0, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {1, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                       },
+                       outputs: []outputInfo{
+                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                       },
+               },
+       },
+       {
+               name:   "VPRORVDMasked128",
+               argLen: 3,
+               asm:    x86.AVPRORVD,
+               reg: regInfo{
+                       inputs: []inputInfo{
+                               {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7
+                               {0, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {1, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                       },
+                       outputs: []outputInfo{
+                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                       },
+               },
+       },
        {
                name:         "VPDPWSSDSMasked128",
                argLen:       4,
@@ -23227,6 +24613,85 @@ var opcodeTable = [...]opInfo{
                        },
                },
        },
+       {
+               name:   "VPSLLVDMasked128",
+               argLen: 3,
+               asm:    x86.AVPSLLVD,
+               reg: regInfo{
+                       inputs: []inputInfo{
+                               {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7
+                               {0, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {1, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                       },
+                       outputs: []outputInfo{
+                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                       },
+               },
+       },
+       {
+               name:         "VPSHLDVDMasked128",
+               argLen:       4,
+               resultInArg0: true,
+               asm:          x86.AVPSHLDVD,
+               reg: regInfo{
+                       inputs: []inputInfo{
+                               {3, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7
+                               {0, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {1, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {2, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                       },
+                       outputs: []outputInfo{
+                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                       },
+               },
+       },
+       {
+               name:   "VPSRLVDMasked128",
+               argLen: 3,
+               asm:    x86.AVPSRLVD,
+               reg: regInfo{
+                       inputs: []inputInfo{
+                               {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7
+                               {0, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {1, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                       },
+                       outputs: []outputInfo{
+                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                       },
+               },
+       },
+       {
+               name:         "VPSHRDVDMasked128",
+               argLen:       4,
+               resultInArg0: true,
+               asm:          x86.AVPSHRDVD,
+               reg: regInfo{
+                       inputs: []inputInfo{
+                               {3, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7
+                               {0, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {1, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {2, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                       },
+                       outputs: []outputInfo{
+                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                       },
+               },
+       },
+       {
+               name:   "VPSRAVDMasked128",
+               argLen: 3,
+               asm:    x86.AVPSRAVD,
+               reg: regInfo{
+                       inputs: []inputInfo{
+                               {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7
+                               {0, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {1, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                       },
+                       outputs: []outputInfo{
+                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                       },
+               },
+       },
        {
                name:   "VPSUBDMasked128",
                argLen: 3,
@@ -23392,6 +24857,34 @@ var opcodeTable = [...]opInfo{
                        },
                },
        },
+       {
+               name:   "VPROLVD128",
+               argLen: 2,
+               asm:    x86.AVPROLVD,
+               reg: regInfo{
+                       inputs: []inputInfo{
+                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                       },
+                       outputs: []outputInfo{
+                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                       },
+               },
+       },
+       {
+               name:   "VPRORVD128",
+               argLen: 2,
+               asm:    x86.AVPRORVD,
+               reg: regInfo{
+                       inputs: []inputInfo{
+                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                       },
+                       outputs: []outputInfo{
+                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                       },
+               },
+       },
        {
                name:         "VPDPWSSDS128",
                argLen:       3,
@@ -23424,6 +24917,122 @@ var opcodeTable = [...]opInfo{
                        },
                },
        },
+       {
+               name:   "VPSLLD128",
+               argLen: 2,
+               asm:    x86.AVPSLLD,
+               reg: regInfo{
+                       inputs: []inputInfo{
+                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                       },
+                       outputs: []outputInfo{
+                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                       },
+               },
+       },
+       {
+               name:   "VPSRLD128",
+               argLen: 2,
+               asm:    x86.AVPSRLD,
+               reg: regInfo{
+                       inputs: []inputInfo{
+                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                       },
+                       outputs: []outputInfo{
+                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                       },
+               },
+       },
+       {
+               name:   "VPSRAD128",
+               argLen: 2,
+               asm:    x86.AVPSRAD,
+               reg: regInfo{
+                       inputs: []inputInfo{
+                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                       },
+                       outputs: []outputInfo{
+                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                       },
+               },
+       },
+       {
+               name:   "VPSLLVD128",
+               argLen: 2,
+               asm:    x86.AVPSLLVD,
+               reg: regInfo{
+                       inputs: []inputInfo{
+                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                       },
+                       outputs: []outputInfo{
+                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                       },
+               },
+       },
+       {
+               name:         "VPSHLDVD128",
+               argLen:       3,
+               resultInArg0: true,
+               asm:          x86.AVPSHLDVD,
+               reg: regInfo{
+                       inputs: []inputInfo{
+                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                       },
+                       outputs: []outputInfo{
+                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                       },
+               },
+       },
+       {
+               name:   "VPSRLVD128",
+               argLen: 2,
+               asm:    x86.AVPSRLVD,
+               reg: regInfo{
+                       inputs: []inputInfo{
+                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                       },
+                       outputs: []outputInfo{
+                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                       },
+               },
+       },
+       {
+               name:         "VPSHRDVD128",
+               argLen:       3,
+               resultInArg0: true,
+               asm:          x86.AVPSHRDVD,
+               reg: regInfo{
+                       inputs: []inputInfo{
+                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                       },
+                       outputs: []outputInfo{
+                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                       },
+               },
+       },
+       {
+               name:   "VPSRAVD128",
+               argLen: 2,
+               asm:    x86.AVPSRAVD,
+               reg: regInfo{
+                       inputs: []inputInfo{
+                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                       },
+                       outputs: []outputInfo{
+                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                       },
+               },
+       },
        {
                name:   "VPSIGND128",
                argLen: 2,
@@ -23681,6 +25290,36 @@ var opcodeTable = [...]opInfo{
                        },
                },
        },
+       {
+               name:   "VPROLVDMasked256",
+               argLen: 3,
+               asm:    x86.AVPROLVD,
+               reg: regInfo{
+                       inputs: []inputInfo{
+                               {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7
+                               {0, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {1, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                       },
+                       outputs: []outputInfo{
+                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                       },
+               },
+       },
+       {
+               name:   "VPRORVDMasked256",
+               argLen: 3,
+               asm:    x86.AVPRORVD,
+               reg: regInfo{
+                       inputs: []inputInfo{
+                               {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7
+                               {0, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {1, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                       },
+                       outputs: []outputInfo{
+                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                       },
+               },
+       },
        {
                name:         "VPDPWSSDSMasked256",
                argLen:       4,
@@ -23715,6 +25354,85 @@ var opcodeTable = [...]opInfo{
                        },
                },
        },
+       {
+               name:   "VPSLLVDMasked256",
+               argLen: 3,
+               asm:    x86.AVPSLLVD,
+               reg: regInfo{
+                       inputs: []inputInfo{
+                               {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7
+                               {0, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {1, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                       },
+                       outputs: []outputInfo{
+                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                       },
+               },
+       },
+       {
+               name:         "VPSHLDVDMasked256",
+               argLen:       4,
+               resultInArg0: true,
+               asm:          x86.AVPSHLDVD,
+               reg: regInfo{
+                       inputs: []inputInfo{
+                               {3, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7
+                               {0, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {1, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {2, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                       },
+                       outputs: []outputInfo{
+                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                       },
+               },
+       },
+       {
+               name:   "VPSRLVDMasked256",
+               argLen: 3,
+               asm:    x86.AVPSRLVD,
+               reg: regInfo{
+                       inputs: []inputInfo{
+                               {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7
+                               {0, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {1, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                       },
+                       outputs: []outputInfo{
+                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                       },
+               },
+       },
+       {
+               name:         "VPSHRDVDMasked256",
+               argLen:       4,
+               resultInArg0: true,
+               asm:          x86.AVPSHRDVD,
+               reg: regInfo{
+                       inputs: []inputInfo{
+                               {3, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7
+                               {0, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {1, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {2, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                       },
+                       outputs: []outputInfo{
+                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                       },
+               },
+       },
+       {
+               name:   "VPSRAVDMasked256",
+               argLen: 3,
+               asm:    x86.AVPSRAVD,
+               reg: regInfo{
+                       inputs: []inputInfo{
+                               {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7
+                               {0, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {1, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                       },
+                       outputs: []outputInfo{
+                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                       },
+               },
+       },
        {
                name:   "VPSUBDMasked256",
                argLen: 3,
@@ -23880,6 +25598,34 @@ var opcodeTable = [...]opInfo{
                        },
                },
        },
+       {
+               name:   "VPROLVD256",
+               argLen: 2,
+               asm:    x86.AVPROLVD,
+               reg: regInfo{
+                       inputs: []inputInfo{
+                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                       },
+                       outputs: []outputInfo{
+                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                       },
+               },
+       },
+       {
+               name:   "VPRORVD256",
+               argLen: 2,
+               asm:    x86.AVPRORVD,
+               reg: regInfo{
+                       inputs: []inputInfo{
+                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                       },
+                       outputs: []outputInfo{
+                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                       },
+               },
+       },
        {
                name:         "VPDPWSSDS256",
                argLen:       3,
@@ -23912,6 +25658,122 @@ var opcodeTable = [...]opInfo{
                        },
                },
        },
+       {
+               name:   "VPSLLD256",
+               argLen: 2,
+               asm:    x86.AVPSLLD,
+               reg: regInfo{
+                       inputs: []inputInfo{
+                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                       },
+                       outputs: []outputInfo{
+                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                       },
+               },
+       },
+       {
+               name:   "VPSRLD256",
+               argLen: 2,
+               asm:    x86.AVPSRLD,
+               reg: regInfo{
+                       inputs: []inputInfo{
+                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                       },
+                       outputs: []outputInfo{
+                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                       },
+               },
+       },
+       {
+               name:   "VPSRAD256",
+               argLen: 2,
+               asm:    x86.AVPSRAD,
+               reg: regInfo{
+                       inputs: []inputInfo{
+                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                       },
+                       outputs: []outputInfo{
+                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                       },
+               },
+       },
+       {
+               name:   "VPSLLVD256",
+               argLen: 2,
+               asm:    x86.AVPSLLVD,
+               reg: regInfo{
+                       inputs: []inputInfo{
+                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                       },
+                       outputs: []outputInfo{
+                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                       },
+               },
+       },
+       {
+               name:         "VPSHLDVD256",
+               argLen:       3,
+               resultInArg0: true,
+               asm:          x86.AVPSHLDVD,
+               reg: regInfo{
+                       inputs: []inputInfo{
+                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                       },
+                       outputs: []outputInfo{
+                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                       },
+               },
+       },
+       {
+               name:   "VPSRLVD256",
+               argLen: 2,
+               asm:    x86.AVPSRLVD,
+               reg: regInfo{
+                       inputs: []inputInfo{
+                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                       },
+                       outputs: []outputInfo{
+                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                       },
+               },
+       },
+       {
+               name:         "VPSHRDVD256",
+               argLen:       3,
+               resultInArg0: true,
+               asm:          x86.AVPSHRDVD,
+               reg: regInfo{
+                       inputs: []inputInfo{
+                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                       },
+                       outputs: []outputInfo{
+                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                       },
+               },
+       },
+       {
+               name:   "VPSRAVD256",
+               argLen: 2,
+               asm:    x86.AVPSRAVD,
+               reg: regInfo{
+                       inputs: []inputInfo{
+                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                       },
+                       outputs: []outputInfo{
+                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                       },
+               },
+       },
        {
                name:   "VPSIGND256",
                argLen: 2,
@@ -24155,9 +26017,9 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:   "VPSUBQMasked128",
+               name:   "VPROLVQMasked128",
                argLen: 3,
-               asm:    x86.AVPSUBQ,
+               asm:    x86.AVPROLVQ,
                reg: regInfo{
                        inputs: []inputInfo{
                                {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7
@@ -24170,10 +26032,9 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:        "VPXORQMasked128",
-               argLen:      3,
-               commutative: true,
-               asm:         x86.AVPXORQ,
+               name:   "VPRORVQMasked128",
+               argLen: 3,
+               asm:    x86.AVPRORVQ,
                reg: regInfo{
                        inputs: []inputInfo{
                                {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7
@@ -24186,29 +26047,14 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:        "VPMAXSQ128",
-               argLen:      2,
-               commutative: true,
-               asm:         x86.AVPMAXSQ,
-               reg: regInfo{
-                       inputs: []inputInfo{
-                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
-                               {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
-                       },
-                       outputs: []outputInfo{
-                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
-                       },
-               },
-       },
-       {
-               name:        "VPMINSQ128",
-               argLen:      2,
-               commutative: true,
-               asm:         x86.AVPMINSQ,
+               name:   "VPSLLQMasked128",
+               argLen: 3,
+               asm:    x86.AVPSLLQ,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
-                               {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7
+                               {0, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {1, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
                        },
                        outputs: []outputInfo{
                                {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
@@ -24216,14 +26062,14 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:        "VPMULLQ128",
-               argLen:      2,
-               commutative: true,
-               asm:         x86.AVPMULLQ,
+               name:   "VPSRLQMasked128",
+               argLen: 3,
+               asm:    x86.AVPSRLQ,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
-                               {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7
+                               {0, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {1, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
                        },
                        outputs: []outputInfo{
                                {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
@@ -24231,12 +26077,14 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:   "VPOPCNTQ128",
-               argLen: 1,
-               asm:    x86.AVPOPCNTQ,
+               name:   "VPSRAQMasked128",
+               argLen: 3,
+               asm:    x86.AVPSRAQ,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7
+                               {0, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {1, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
                        },
                        outputs: []outputInfo{
                                {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
@@ -24244,13 +26092,14 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:   "VPSUBQ128",
-               argLen: 2,
-               asm:    x86.AVPSUBQ,
+               name:   "VPSLLVQMasked128",
+               argLen: 3,
+               asm:    x86.AVPSLLVQ,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
-                               {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7
+                               {0, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {1, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
                        },
                        outputs: []outputInfo{
                                {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
@@ -24258,12 +26107,16 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:   "VPABSQ256",
-               argLen: 1,
-               asm:    x86.AVPABSQ,
+               name:         "VPSHLDVQMasked128",
+               argLen:       4,
+               resultInArg0: true,
+               asm:          x86.AVPSHLDVQ,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {3, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7
+                               {0, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {1, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {2, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
                        },
                        outputs: []outputInfo{
                                {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
@@ -24271,14 +26124,14 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:        "VPADDQ256",
-               argLen:      2,
-               commutative: true,
-               asm:         x86.AVPADDQ,
+               name:   "VPSRLVQMasked128",
+               argLen: 3,
+               asm:    x86.AVPSRLVQ,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
-                               {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7
+                               {0, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {1, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
                        },
                        outputs: []outputInfo{
                                {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
@@ -24286,14 +26139,16 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:        "VPCMPEQQ256",
-               argLen:      2,
-               commutative: true,
-               asm:         x86.AVPCMPEQQ,
+               name:         "VPSHRDVQMasked128",
+               argLen:       4,
+               resultInArg0: true,
+               asm:          x86.AVPSHRDVQ,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
-                               {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {3, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7
+                               {0, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {1, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {2, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
                        },
                        outputs: []outputInfo{
                                {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
@@ -24301,13 +26156,14 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:   "VPCMPGTQ256",
-               argLen: 2,
-               asm:    x86.AVPCMPGTQ,
+               name:   "VPSRAVQMasked128",
+               argLen: 3,
+               asm:    x86.AVPSRAVQ,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
-                               {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7
+                               {0, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {1, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
                        },
                        outputs: []outputInfo{
                                {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
@@ -24315,13 +26171,14 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:   "VPABSQMasked256",
-               argLen: 2,
-               asm:    x86.AVPABSQ,
+               name:   "VPSUBQMasked128",
+               argLen: 3,
+               asm:    x86.AVPSUBQ,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {1, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7
+                               {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7
                                {0, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {1, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
                        },
                        outputs: []outputInfo{
                                {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
@@ -24329,10 +26186,10 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:        "VPADDQMasked256",
+               name:        "VPXORQMasked128",
                argLen:      3,
                commutative: true,
-               asm:         x86.AVPADDQ,
+               asm:         x86.AVPXORQ,
                reg: regInfo{
                        inputs: []inputInfo{
                                {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7
@@ -24345,15 +26202,14 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:        "VPANDQMasked256",
-               argLen:      3,
+               name:        "VPMAXSQ128",
+               argLen:      2,
                commutative: true,
-               asm:         x86.AVPANDQ,
+               asm:         x86.AVPMAXSQ,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7
-                               {0, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
-                               {1, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
                        },
                        outputs: []outputInfo{
                                {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
@@ -24361,14 +26217,14 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:   "VPANDNQMasked256",
-               argLen: 3,
-               asm:    x86.AVPANDNQ,
+               name:        "VPMINSQ128",
+               argLen:      2,
+               commutative: true,
+               asm:         x86.AVPMINSQ,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7
-                               {0, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
-                               {1, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
                        },
                        outputs: []outputInfo{
                                {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
@@ -24376,15 +26232,14 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:        "VPMAXSQMasked256",
-               argLen:      3,
+               name:        "VPMULLQ128",
+               argLen:      2,
                commutative: true,
-               asm:         x86.AVPMAXSQ,
+               asm:         x86.AVPMULLQ,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7
-                               {0, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
-                               {1, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
                        },
                        outputs: []outputInfo{
                                {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
@@ -24392,15 +26247,12 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:        "VPMINSQMasked256",
-               argLen:      3,
-               commutative: true,
-               asm:         x86.AVPMINSQ,
+               name:   "VPOPCNTQ128",
+               argLen: 1,
+               asm:    x86.AVPOPCNTQ,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7
-                               {0, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
-                               {1, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
                        },
                        outputs: []outputInfo{
                                {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
@@ -24408,15 +26260,13 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:        "VPMULDQMasked256",
-               argLen:      3,
-               commutative: true,
-               asm:         x86.AVPMULDQ,
+               name:   "VPROLVQ128",
+               argLen: 2,
+               asm:    x86.AVPROLVQ,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7
-                               {0, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
-                               {1, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
                        },
                        outputs: []outputInfo{
                                {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
@@ -24424,15 +26274,13 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:        "VPMULLQMasked256",
-               argLen:      3,
-               commutative: true,
-               asm:         x86.AVPMULLQ,
+               name:   "VPRORVQ128",
+               argLen: 2,
+               asm:    x86.AVPRORVQ,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7
-                               {0, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
-                               {1, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
                        },
                        outputs: []outputInfo{
                                {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
@@ -24440,15 +26288,13 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:        "VPORQMasked256",
-               argLen:      3,
-               commutative: true,
-               asm:         x86.AVPORQ,
+               name:   "VPSLLQ128",
+               argLen: 2,
+               asm:    x86.AVPSLLQ,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7
-                               {0, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
-                               {1, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
                        },
                        outputs: []outputInfo{
                                {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
@@ -24456,13 +26302,13 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:   "VPOPCNTQMasked256",
+               name:   "VPSRLQ128",
                argLen: 2,
-               asm:    x86.AVPOPCNTQ,
+               asm:    x86.AVPSRLQ,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {1, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7
-                               {0, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
                        },
                        outputs: []outputInfo{
                                {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
@@ -24470,14 +26316,13 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:   "VPSUBQMasked256",
-               argLen: 3,
-               asm:    x86.AVPSUBQ,
+               name:   "VPSRAQ128",
+               argLen: 2,
+               asm:    x86.AVPSRAQ,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7
-                               {0, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
-                               {1, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
                        },
                        outputs: []outputInfo{
                                {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
@@ -24485,15 +26330,13 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:        "VPXORQMasked256",
-               argLen:      3,
-               commutative: true,
-               asm:         x86.AVPXORQ,
+               name:   "VPSLLVQ128",
+               argLen: 2,
+               asm:    x86.AVPSLLVQ,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7
-                               {0, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
-                               {1, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
                        },
                        outputs: []outputInfo{
                                {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
@@ -24501,14 +26344,15 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:        "VPMAXSQ256",
-               argLen:      2,
-               commutative: true,
-               asm:         x86.AVPMAXSQ,
+               name:         "VPSHLDVQ128",
+               argLen:       3,
+               resultInArg0: true,
+               asm:          x86.AVPSHLDVQ,
                reg: regInfo{
                        inputs: []inputInfo{
                                {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
                                {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
                        },
                        outputs: []outputInfo{
                                {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
@@ -24516,10 +26360,9 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:        "VPMINSQ256",
-               argLen:      2,
-               commutative: true,
-               asm:         x86.AVPMINSQ,
+               name:   "VPSRLVQ128",
+               argLen: 2,
+               asm:    x86.AVPSRLVQ,
                reg: regInfo{
                        inputs: []inputInfo{
                                {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
@@ -24531,14 +26374,15 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:        "VPMULLQ256",
-               argLen:      2,
-               commutative: true,
-               asm:         x86.AVPMULLQ,
+               name:         "VPSHRDVQ128",
+               argLen:       3,
+               resultInArg0: true,
+               asm:          x86.AVPSHRDVQ,
                reg: regInfo{
                        inputs: []inputInfo{
                                {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
                                {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
                        },
                        outputs: []outputInfo{
                                {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
@@ -24546,12 +26390,13 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:   "VPOPCNTQ256",
-               argLen: 1,
-               asm:    x86.AVPOPCNTQ,
+               name:   "VPSRAVQ128",
+               argLen: 2,
+               asm:    x86.AVPSRAVQ,
                reg: regInfo{
                        inputs: []inputInfo{
                                {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
                        },
                        outputs: []outputInfo{
                                {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
@@ -24559,7 +26404,7 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:   "VPSUBQ256",
+               name:   "VPSUBQ128",
                argLen: 2,
                asm:    x86.AVPSUBQ,
                reg: regInfo{
@@ -24573,7 +26418,7 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:   "VPABSQ512",
+               name:   "VPABSQ256",
                argLen: 1,
                asm:    x86.AVPABSQ,
                reg: regInfo{
@@ -24586,7 +26431,7 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:        "VPADDQ512",
+               name:        "VPADDQ256",
                argLen:      2,
                commutative: true,
                asm:         x86.AVPADDQ,
@@ -24601,10 +26446,10 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:        "VPANDQ512",
+               name:        "VPCMPEQQ256",
                argLen:      2,
                commutative: true,
-               asm:         x86.AVPANDQ,
+               asm:         x86.AVPCMPEQQ,
                reg: regInfo{
                        inputs: []inputInfo{
                                {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
@@ -24616,9 +26461,9 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:   "VPANDNQ512",
+               name:   "VPCMPGTQ256",
                argLen: 2,
-               asm:    x86.AVPANDNQ,
+               asm:    x86.AVPCMPGTQ,
                reg: regInfo{
                        inputs: []inputInfo{
                                {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
@@ -24630,7 +26475,7 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:   "VPABSQMasked512",
+               name:   "VPABSQMasked256",
                argLen: 2,
                asm:    x86.AVPABSQ,
                reg: regInfo{
@@ -24644,7 +26489,7 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:        "VPADDQMasked512",
+               name:        "VPADDQMasked256",
                argLen:      3,
                commutative: true,
                asm:         x86.AVPADDQ,
@@ -24660,7 +26505,7 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:        "VPANDQMasked512",
+               name:        "VPANDQMasked256",
                argLen:      3,
                commutative: true,
                asm:         x86.AVPANDQ,
@@ -24676,7 +26521,7 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:   "VPANDNQMasked512",
+               name:   "VPANDNQMasked256",
                argLen: 3,
                asm:    x86.AVPANDNQ,
                reg: regInfo{
@@ -24691,7 +26536,7 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:        "VPMAXSQMasked512",
+               name:        "VPMAXSQMasked256",
                argLen:      3,
                commutative: true,
                asm:         x86.AVPMAXSQ,
@@ -24707,7 +26552,7 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:        "VPMINSQMasked512",
+               name:        "VPMINSQMasked256",
                argLen:      3,
                commutative: true,
                asm:         x86.AVPMINSQ,
@@ -24723,7 +26568,7 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:        "VPMULDQMasked512",
+               name:        "VPMULDQMasked256",
                argLen:      3,
                commutative: true,
                asm:         x86.AVPMULDQ,
@@ -24739,7 +26584,7 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:        "VPMULLQMasked512",
+               name:        "VPMULLQMasked256",
                argLen:      3,
                commutative: true,
                asm:         x86.AVPMULLQ,
@@ -24755,7 +26600,7 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:        "VPORQMasked512",
+               name:        "VPORQMasked256",
                argLen:      3,
                commutative: true,
                asm:         x86.AVPORQ,
@@ -24771,7 +26616,7 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:   "VPOPCNTQMasked512",
+               name:   "VPOPCNTQMasked256",
                argLen: 2,
                asm:    x86.AVPOPCNTQ,
                reg: regInfo{
@@ -24785,9 +26630,9 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:   "VPSUBQMasked512",
+               name:   "VPROLVQMasked256",
                argLen: 3,
-               asm:    x86.AVPSUBQ,
+               asm:    x86.AVPROLVQ,
                reg: regInfo{
                        inputs: []inputInfo{
                                {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7
@@ -24800,10 +26645,9 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:        "VPXORQMasked512",
-               argLen:      3,
-               commutative: true,
-               asm:         x86.AVPXORQ,
+               name:   "VPRORVQMasked256",
+               argLen: 3,
+               asm:    x86.AVPRORVQ,
                reg: regInfo{
                        inputs: []inputInfo{
                                {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7
@@ -24816,14 +26660,14 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:        "VPMAXSQ512",
-               argLen:      2,
-               commutative: true,
-               asm:         x86.AVPMAXSQ,
+               name:   "VPSLLQMasked256",
+               argLen: 3,
+               asm:    x86.AVPSLLQ,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
-                               {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7
+                               {0, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {1, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
                        },
                        outputs: []outputInfo{
                                {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
@@ -24831,14 +26675,14 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:        "VPMINSQ512",
-               argLen:      2,
-               commutative: true,
-               asm:         x86.AVPMINSQ,
+               name:   "VPSRLQMasked256",
+               argLen: 3,
+               asm:    x86.AVPSRLQ,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
-                               {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7
+                               {0, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {1, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
                        },
                        outputs: []outputInfo{
                                {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
@@ -24846,14 +26690,14 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:        "VPMULDQ512",
-               argLen:      2,
-               commutative: true,
-               asm:         x86.AVPMULDQ,
+               name:   "VPSRAQMasked256",
+               argLen: 3,
+               asm:    x86.AVPSRAQ,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
-                               {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7
+                               {0, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {1, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
                        },
                        outputs: []outputInfo{
                                {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
@@ -24861,14 +26705,14 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:        "VPMULLQ512",
-               argLen:      2,
-               commutative: true,
-               asm:         x86.AVPMULLQ,
+               name:   "VPSLLVQMasked256",
+               argLen: 3,
+               asm:    x86.AVPSLLVQ,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
-                               {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7
+                               {0, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {1, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
                        },
                        outputs: []outputInfo{
                                {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
@@ -24876,14 +26720,16 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:        "VPORQ512",
-               argLen:      2,
-               commutative: true,
-               asm:         x86.AVPORQ,
+               name:         "VPSHLDVQMasked256",
+               argLen:       4,
+               resultInArg0: true,
+               asm:          x86.AVPSHLDVQ,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
-                               {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {3, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7
+                               {0, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {1, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {2, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
                        },
                        outputs: []outputInfo{
                                {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
@@ -24891,12 +26737,14 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:   "VPOPCNTQ512",
-               argLen: 1,
-               asm:    x86.AVPOPCNTQ,
+               name:   "VPSRLVQMasked256",
+               argLen: 3,
+               asm:    x86.AVPSRLVQ,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7
+                               {0, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {1, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
                        },
                        outputs: []outputInfo{
                                {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
@@ -24904,13 +26752,16 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:   "VPSUBQ512",
-               argLen: 2,
-               asm:    x86.AVPSUBQ,
+               name:         "VPSHRDVQMasked256",
+               argLen:       4,
+               resultInArg0: true,
+               asm:          x86.AVPSHRDVQ,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
-                               {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {3, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7
+                               {0, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {1, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {2, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
                        },
                        outputs: []outputInfo{
                                {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
@@ -24918,14 +26769,14 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:        "VPXORQ512",
-               argLen:      2,
-               commutative: true,
-               asm:         x86.AVPXORQ,
+               name:   "VPSRAVQMasked256",
+               argLen: 3,
+               asm:    x86.AVPSRAVQ,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
-                               {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7
+                               {0, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {1, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
                        },
                        outputs: []outputInfo{
                                {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
@@ -24933,12 +26784,14 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:   "VPABSB128",
-               argLen: 1,
-               asm:    x86.AVPABSB,
+               name:   "VPSUBQMasked256",
+               argLen: 3,
+               asm:    x86.AVPSUBQ,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7
+                               {0, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {1, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
                        },
                        outputs: []outputInfo{
                                {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
@@ -24946,14 +26799,15 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:        "VPADDB128",
-               argLen:      2,
+               name:        "VPXORQMasked256",
+               argLen:      3,
                commutative: true,
-               asm:         x86.AVPADDB,
+               asm:         x86.AVPXORQ,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
-                               {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7
+                               {0, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {1, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
                        },
                        outputs: []outputInfo{
                                {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
@@ -24961,10 +26815,10 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:        "VPAND128",
+               name:        "VPMAXSQ256",
                argLen:      2,
                commutative: true,
-               asm:         x86.AVPAND,
+               asm:         x86.AVPMAXSQ,
                reg: regInfo{
                        inputs: []inputInfo{
                                {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
@@ -24976,9 +26830,10 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:   "VPANDN128",
-               argLen: 2,
-               asm:    x86.AVPANDN,
+               name:        "VPMINSQ256",
+               argLen:      2,
+               commutative: true,
+               asm:         x86.AVPMINSQ,
                reg: regInfo{
                        inputs: []inputInfo{
                                {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
@@ -24990,10 +26845,10 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:        "VPCMPEQB128",
+               name:        "VPMULLQ256",
                argLen:      2,
                commutative: true,
-               asm:         x86.AVPCMPEQB,
+               asm:         x86.AVPMULLQ,
                reg: regInfo{
                        inputs: []inputInfo{
                                {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
@@ -25005,13 +26860,12 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:   "VPCMPGTB128",
-               argLen: 2,
-               asm:    x86.AVPCMPGTB,
+               name:   "VPOPCNTQ256",
+               argLen: 1,
+               asm:    x86.AVPOPCNTQ,
                reg: regInfo{
                        inputs: []inputInfo{
                                {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
-                               {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
                        },
                        outputs: []outputInfo{
                                {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
@@ -25019,13 +26873,13 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:   "VPABSBMasked128",
+               name:   "VPROLVQ256",
                argLen: 2,
-               asm:    x86.AVPABSB,
+               asm:    x86.AVPROLVQ,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {1, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7
-                               {0, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
                        },
                        outputs: []outputInfo{
                                {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
@@ -25033,15 +26887,13 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:        "VPADDBMasked128",
-               argLen:      3,
-               commutative: true,
-               asm:         x86.AVPADDB,
+               name:   "VPRORVQ256",
+               argLen: 2,
+               asm:    x86.AVPRORVQ,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7
-                               {0, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
-                               {1, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
                        },
                        outputs: []outputInfo{
                                {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
@@ -25049,15 +26901,13 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:        "VPMAXSBMasked128",
-               argLen:      3,
-               commutative: true,
-               asm:         x86.AVPMAXSB,
+               name:   "VPSLLQ256",
+               argLen: 2,
+               asm:    x86.AVPSLLQ,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7
-                               {0, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
-                               {1, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
                        },
                        outputs: []outputInfo{
                                {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
@@ -25065,15 +26915,13 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:        "VPMINSBMasked128",
-               argLen:      3,
-               commutative: true,
-               asm:         x86.AVPMINSB,
+               name:   "VPSRLQ256",
+               argLen: 2,
+               asm:    x86.AVPSRLQ,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7
-                               {0, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
-                               {1, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
                        },
                        outputs: []outputInfo{
                                {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
@@ -25081,13 +26929,13 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:   "VPOPCNTBMasked128",
+               name:   "VPSRAQ256",
                argLen: 2,
-               asm:    x86.AVPOPCNTB,
+               asm:    x86.AVPSRAQ,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {1, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7
-                               {0, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
                        },
                        outputs: []outputInfo{
                                {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
@@ -25095,15 +26943,13 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:        "VPADDSBMasked128",
-               argLen:      3,
-               commutative: true,
-               asm:         x86.AVPADDSB,
+               name:   "VPSLLVQ256",
+               argLen: 2,
+               asm:    x86.AVPSLLVQ,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7
-                               {0, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
-                               {1, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
                        },
                        outputs: []outputInfo{
                                {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
@@ -25111,14 +26957,15 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:   "VPSUBSBMasked128",
-               argLen: 3,
-               asm:    x86.AVPSUBSB,
+               name:         "VPSHLDVQ256",
+               argLen:       3,
+               resultInArg0: true,
+               asm:          x86.AVPSHLDVQ,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7
-                               {0, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
-                               {1, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
                        },
                        outputs: []outputInfo{
                                {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
@@ -25126,14 +26973,13 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:   "VPSUBBMasked128",
-               argLen: 3,
-               asm:    x86.AVPSUBB,
+               name:   "VPSRLVQ256",
+               argLen: 2,
+               asm:    x86.AVPSRLVQ,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7
-                               {0, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
-                               {1, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
                        },
                        outputs: []outputInfo{
                                {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
@@ -25141,14 +26987,15 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:        "VPMAXSB128",
-               argLen:      2,
-               commutative: true,
-               asm:         x86.AVPMAXSB,
+               name:         "VPSHRDVQ256",
+               argLen:       3,
+               resultInArg0: true,
+               asm:          x86.AVPSHRDVQ,
                reg: regInfo{
                        inputs: []inputInfo{
                                {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
                                {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
                        },
                        outputs: []outputInfo{
                                {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
@@ -25156,10 +27003,9 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:        "VPMINSB128",
-               argLen:      2,
-               commutative: true,
-               asm:         x86.AVPMINSB,
+               name:   "VPSRAVQ256",
+               argLen: 2,
+               asm:    x86.AVPSRAVQ,
                reg: regInfo{
                        inputs: []inputInfo{
                                {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
@@ -25171,10 +27017,9 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:        "VPOR128",
-               argLen:      2,
-               commutative: true,
-               asm:         x86.AVPOR,
+               name:   "VPSUBQ256",
+               argLen: 2,
+               asm:    x86.AVPSUBQ,
                reg: regInfo{
                        inputs: []inputInfo{
                                {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
@@ -25186,9 +27031,9 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:   "VPOPCNTB128",
+               name:   "VPABSQ512",
                argLen: 1,
-               asm:    x86.AVPOPCNTB,
+               asm:    x86.AVPABSQ,
                reg: regInfo{
                        inputs: []inputInfo{
                                {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
@@ -25199,10 +27044,10 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:        "VPADDSB128",
+               name:        "VPADDQ512",
                argLen:      2,
                commutative: true,
-               asm:         x86.AVPADDSB,
+               asm:         x86.AVPADDQ,
                reg: regInfo{
                        inputs: []inputInfo{
                                {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
@@ -25214,9 +27059,10 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:   "VPSUBSB128",
-               argLen: 2,
-               asm:    x86.AVPSUBSB,
+               name:        "VPANDQ512",
+               argLen:      2,
+               commutative: true,
+               asm:         x86.AVPANDQ,
                reg: regInfo{
                        inputs: []inputInfo{
                                {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
@@ -25228,9 +27074,9 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:   "VPSIGNB128",
+               name:   "VPANDNQ512",
                argLen: 2,
-               asm:    x86.AVPSIGNB,
+               asm:    x86.AVPANDNQ,
                reg: regInfo{
                        inputs: []inputInfo{
                                {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
@@ -25242,13 +27088,13 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:   "VPSUBB128",
+               name:   "VPABSQMasked512",
                argLen: 2,
-               asm:    x86.AVPSUBB,
+               asm:    x86.AVPABSQ,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
-                               {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {1, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7
+                               {0, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
                        },
                        outputs: []outputInfo{
                                {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
@@ -25256,14 +27102,15 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:        "VPXOR128",
-               argLen:      2,
+               name:        "VPADDQMasked512",
+               argLen:      3,
                commutative: true,
-               asm:         x86.AVPXOR,
+               asm:         x86.AVPADDQ,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
-                               {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7
+                               {0, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {1, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
                        },
                        outputs: []outputInfo{
                                {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
@@ -25271,27 +27118,46 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:   "VPABSB256",
-               argLen: 1,
-               asm:    x86.AVPABSB,
+               name:        "VPANDQMasked512",
+               argLen:      3,
+               commutative: true,
+               asm:         x86.AVPANDQ,
                reg: regInfo{
                        inputs: []inputInfo{
+                               {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7
+                               {0, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {1, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                       },
+                       outputs: []outputInfo{
                                {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
                        },
+               },
+       },
+       {
+               name:   "VPANDNQMasked512",
+               argLen: 3,
+               asm:    x86.AVPANDNQ,
+               reg: regInfo{
+                       inputs: []inputInfo{
+                               {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7
+                               {0, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {1, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                       },
                        outputs: []outputInfo{
                                {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
                        },
                },
        },
        {
-               name:        "VPADDB256",
-               argLen:      2,
+               name:        "VPMAXSQMasked512",
+               argLen:      3,
                commutative: true,
-               asm:         x86.AVPADDB,
+               asm:         x86.AVPMAXSQ,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
-                               {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7
+                               {0, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {1, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
                        },
                        outputs: []outputInfo{
                                {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
@@ -25299,14 +27165,15 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:        "VPAND256",
-               argLen:      2,
+               name:        "VPMINSQMasked512",
+               argLen:      3,
                commutative: true,
-               asm:         x86.AVPAND,
+               asm:         x86.AVPMINSQ,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
-                               {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7
+                               {0, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {1, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
                        },
                        outputs: []outputInfo{
                                {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
@@ -25314,13 +27181,15 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:   "VPANDN256",
-               argLen: 2,
-               asm:    x86.AVPANDN,
+               name:        "VPMULDQMasked512",
+               argLen:      3,
+               commutative: true,
+               asm:         x86.AVPMULDQ,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
-                               {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7
+                               {0, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {1, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
                        },
                        outputs: []outputInfo{
                                {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
@@ -25328,14 +27197,15 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:        "VPCMPEQB256",
-               argLen:      2,
+               name:        "VPMULLQMasked512",
+               argLen:      3,
                commutative: true,
-               asm:         x86.AVPCMPEQB,
+               asm:         x86.AVPMULLQ,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
-                               {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7
+                               {0, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {1, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
                        },
                        outputs: []outputInfo{
                                {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
@@ -25343,13 +27213,15 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:   "VPCMPGTB256",
-               argLen: 2,
-               asm:    x86.AVPCMPGTB,
+               name:        "VPORQMasked512",
+               argLen:      3,
+               commutative: true,
+               asm:         x86.AVPORQ,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
-                               {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7
+                               {0, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {1, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
                        },
                        outputs: []outputInfo{
                                {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
@@ -25357,9 +27229,9 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:   "VPABSBMasked256",
+               name:   "VPOPCNTQMasked512",
                argLen: 2,
-               asm:    x86.AVPABSB,
+               asm:    x86.AVPOPCNTQ,
                reg: regInfo{
                        inputs: []inputInfo{
                                {1, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7
@@ -25371,10 +27243,9 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:        "VPADDBMasked256",
-               argLen:      3,
-               commutative: true,
-               asm:         x86.AVPADDB,
+               name:   "VPROLVQMasked512",
+               argLen: 3,
+               asm:    x86.AVPROLVQ,
                reg: regInfo{
                        inputs: []inputInfo{
                                {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7
@@ -25387,10 +27258,9 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:        "VPMAXSBMasked256",
-               argLen:      3,
-               commutative: true,
-               asm:         x86.AVPMAXSB,
+               name:   "VPRORVQMasked512",
+               argLen: 3,
+               asm:    x86.AVPRORVQ,
                reg: regInfo{
                        inputs: []inputInfo{
                                {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7
@@ -25403,10 +27273,9 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:        "VPMINSBMasked256",
-               argLen:      3,
-               commutative: true,
-               asm:         x86.AVPMINSB,
+               name:   "VPSLLQMasked512",
+               argLen: 3,
+               asm:    x86.AVPSLLQ,
                reg: regInfo{
                        inputs: []inputInfo{
                                {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7
@@ -25419,13 +27288,14 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:   "VPOPCNTBMasked256",
-               argLen: 2,
-               asm:    x86.AVPOPCNTB,
+               name:   "VPSRLQMasked512",
+               argLen: 3,
+               asm:    x86.AVPSRLQ,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {1, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7
+                               {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7
                                {0, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {1, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
                        },
                        outputs: []outputInfo{
                                {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
@@ -25433,10 +27303,9 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:        "VPADDSBMasked256",
-               argLen:      3,
-               commutative: true,
-               asm:         x86.AVPADDSB,
+               name:   "VPSRAQMasked512",
+               argLen: 3,
+               asm:    x86.AVPSRAQ,
                reg: regInfo{
                        inputs: []inputInfo{
                                {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7
@@ -25449,9 +27318,9 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:   "VPSUBSBMasked256",
+               name:   "VPSLLVQMasked512",
                argLen: 3,
-               asm:    x86.AVPSUBSB,
+               asm:    x86.AVPSLLVQ,
                reg: regInfo{
                        inputs: []inputInfo{
                                {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7
@@ -25464,9 +27333,26 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:   "VPSUBBMasked256",
+               name:         "VPSHLDVQMasked512",
+               argLen:       4,
+               resultInArg0: true,
+               asm:          x86.AVPSHLDVQ,
+               reg: regInfo{
+                       inputs: []inputInfo{
+                               {3, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7
+                               {0, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {1, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {2, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                       },
+                       outputs: []outputInfo{
+                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                       },
+               },
+       },
+       {
+               name:   "VPSRLVQMasked512",
                argLen: 3,
-               asm:    x86.AVPSUBB,
+               asm:    x86.AVPSRLVQ,
                reg: regInfo{
                        inputs: []inputInfo{
                                {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7
@@ -25479,14 +27365,16 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:        "VPMAXSB256",
-               argLen:      2,
-               commutative: true,
-               asm:         x86.AVPMAXSB,
+               name:         "VPSHRDVQMasked512",
+               argLen:       4,
+               resultInArg0: true,
+               asm:          x86.AVPSHRDVQ,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
-                               {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {3, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7
+                               {0, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {1, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {2, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
                        },
                        outputs: []outputInfo{
                                {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
@@ -25494,14 +27382,14 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:        "VPMINSB256",
-               argLen:      2,
-               commutative: true,
-               asm:         x86.AVPMINSB,
+               name:   "VPSRAVQMasked512",
+               argLen: 3,
+               asm:    x86.AVPSRAVQ,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
-                               {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7
+                               {0, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {1, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
                        },
                        outputs: []outputInfo{
                                {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
@@ -25509,14 +27397,14 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:        "VPOR256",
-               argLen:      2,
-               commutative: true,
-               asm:         x86.AVPOR,
+               name:   "VPSUBQMasked512",
+               argLen: 3,
+               asm:    x86.AVPSUBQ,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
-                               {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7
+                               {0, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {1, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
                        },
                        outputs: []outputInfo{
                                {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
@@ -25524,12 +27412,15 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:   "VPOPCNTB256",
-               argLen: 1,
-               asm:    x86.AVPOPCNTB,
+               name:        "VPXORQMasked512",
+               argLen:      3,
+               commutative: true,
+               asm:         x86.AVPXORQ,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7
+                               {0, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {1, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
                        },
                        outputs: []outputInfo{
                                {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
@@ -25537,10 +27428,10 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:        "VPADDSB256",
+               name:        "VPMAXSQ512",
                argLen:      2,
                commutative: true,
-               asm:         x86.AVPADDSB,
+               asm:         x86.AVPMAXSQ,
                reg: regInfo{
                        inputs: []inputInfo{
                                {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
@@ -25552,9 +27443,10 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:   "VPSUBSB256",
-               argLen: 2,
-               asm:    x86.AVPSUBSB,
+               name:        "VPMINSQ512",
+               argLen:      2,
+               commutative: true,
+               asm:         x86.AVPMINSQ,
                reg: regInfo{
                        inputs: []inputInfo{
                                {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
@@ -25566,9 +27458,10 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:   "VPSIGNB256",
-               argLen: 2,
-               asm:    x86.AVPSIGNB,
+               name:        "VPMULDQ512",
+               argLen:      2,
+               commutative: true,
+               asm:         x86.AVPMULDQ,
                reg: regInfo{
                        inputs: []inputInfo{
                                {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
@@ -25580,9 +27473,10 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:   "VPSUBB256",
-               argLen: 2,
-               asm:    x86.AVPSUBB,
+               name:        "VPMULLQ512",
+               argLen:      2,
+               commutative: true,
+               asm:         x86.AVPMULLQ,
                reg: regInfo{
                        inputs: []inputInfo{
                                {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
@@ -25594,10 +27488,10 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:        "VPXOR256",
+               name:        "VPORQ512",
                argLen:      2,
                commutative: true,
-               asm:         x86.AVPXOR,
+               asm:         x86.AVPORQ,
                reg: regInfo{
                        inputs: []inputInfo{
                                {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
@@ -25609,9 +27503,9 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:   "VPABSB512",
+               name:   "VPOPCNTQ512",
                argLen: 1,
-               asm:    x86.AVPABSB,
+               asm:    x86.AVPOPCNTQ,
                reg: regInfo{
                        inputs: []inputInfo{
                                {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
@@ -25622,10 +27516,9 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:        "VPADDB512",
-               argLen:      2,
-               commutative: true,
-               asm:         x86.AVPADDB,
+               name:   "VPROLVQ512",
+               argLen: 2,
+               asm:    x86.AVPROLVQ,
                reg: regInfo{
                        inputs: []inputInfo{
                                {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
@@ -25637,13 +27530,13 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:   "VPABSBMasked512",
+               name:   "VPRORVQ512",
                argLen: 2,
-               asm:    x86.AVPABSB,
+               asm:    x86.AVPRORVQ,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {1, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7
-                               {0, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
                        },
                        outputs: []outputInfo{
                                {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
@@ -25651,15 +27544,13 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:        "VPADDBMasked512",
-               argLen:      3,
-               commutative: true,
-               asm:         x86.AVPADDB,
+               name:   "VPSLLQ512",
+               argLen: 2,
+               asm:    x86.AVPSLLQ,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7
-                               {0, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
-                               {1, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
                        },
                        outputs: []outputInfo{
                                {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
@@ -25667,15 +27558,13 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:        "VPMAXSBMasked512",
-               argLen:      3,
-               commutative: true,
-               asm:         x86.AVPMAXSB,
+               name:   "VPSRLQ512",
+               argLen: 2,
+               asm:    x86.AVPSRLQ,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7
-                               {0, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
-                               {1, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
                        },
                        outputs: []outputInfo{
                                {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
@@ -25683,15 +27572,13 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:        "VPMINSBMasked512",
-               argLen:      3,
-               commutative: true,
-               asm:         x86.AVPMINSB,
+               name:   "VPSRAQ512",
+               argLen: 2,
+               asm:    x86.AVPSRAQ,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7
-                               {0, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
-                               {1, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
                        },
                        outputs: []outputInfo{
                                {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
@@ -25699,13 +27586,13 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:   "VPOPCNTBMasked512",
+               name:   "VPSLLVQ512",
                argLen: 2,
-               asm:    x86.AVPOPCNTB,
+               asm:    x86.AVPSLLVQ,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {1, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7
-                               {0, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
                        },
                        outputs: []outputInfo{
                                {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
@@ -25713,15 +27600,15 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:        "VPADDSBMasked512",
-               argLen:      3,
-               commutative: true,
-               asm:         x86.AVPADDSB,
+               name:         "VPSHLDVQ512",
+               argLen:       3,
+               resultInArg0: true,
+               asm:          x86.AVPSHLDVQ,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7
-                               {0, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
-                               {1, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
                        },
                        outputs: []outputInfo{
                                {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
@@ -25729,14 +27616,13 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:   "VPSUBSBMasked512",
-               argLen: 3,
-               asm:    x86.AVPSUBSB,
+               name:   "VPSRLVQ512",
+               argLen: 2,
+               asm:    x86.AVPSRLVQ,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7
-                               {0, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
-                               {1, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
                        },
                        outputs: []outputInfo{
                                {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
@@ -25744,14 +27630,15 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:   "VPSUBBMasked512",
-               argLen: 3,
-               asm:    x86.AVPSUBB,
+               name:         "VPSHRDVQ512",
+               argLen:       3,
+               resultInArg0: true,
+               asm:          x86.AVPSHRDVQ,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7
-                               {0, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
-                               {1, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
                        },
                        outputs: []outputInfo{
                                {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
@@ -25759,10 +27646,9 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:        "VPMAXSB512",
-               argLen:      2,
-               commutative: true,
-               asm:         x86.AVPMAXSB,
+               name:   "VPSRAVQ512",
+               argLen: 2,
+               asm:    x86.AVPSRAVQ,
                reg: regInfo{
                        inputs: []inputInfo{
                                {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
@@ -25774,10 +27660,24 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:        "VPMINSB512",
+               name:   "VPSUBQ512",
+               argLen: 2,
+               asm:    x86.AVPSUBQ,
+               reg: regInfo{
+                       inputs: []inputInfo{
+                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                       },
+                       outputs: []outputInfo{
+                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                       },
+               },
+       },
+       {
+               name:        "VPXORQ512",
                argLen:      2,
                commutative: true,
-               asm:         x86.AVPMINSB,
+               asm:         x86.AVPXORQ,
                reg: regInfo{
                        inputs: []inputInfo{
                                {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
@@ -25789,9 +27689,9 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:   "VPOPCNTB512",
+               name:   "VPABSB128",
                argLen: 1,
-               asm:    x86.AVPOPCNTB,
+               asm:    x86.AVPABSB,
                reg: regInfo{
                        inputs: []inputInfo{
                                {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
@@ -25802,10 +27702,10 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:        "VPADDSB512",
+               name:        "VPADDB128",
                argLen:      2,
                commutative: true,
-               asm:         x86.AVPADDSB,
+               asm:         x86.AVPADDB,
                reg: regInfo{
                        inputs: []inputInfo{
                                {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
@@ -25817,9 +27717,10 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:   "VPSUBSB512",
-               argLen: 2,
-               asm:    x86.AVPSUBSB,
+               name:        "VPAND128",
+               argLen:      2,
+               commutative: true,
+               asm:         x86.AVPAND,
                reg: regInfo{
                        inputs: []inputInfo{
                                {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
@@ -25831,9 +27732,9 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:   "VPSUBB512",
+               name:   "VPANDN128",
                argLen: 2,
-               asm:    x86.AVPSUBB,
+               asm:    x86.AVPANDN,
                reg: regInfo{
                        inputs: []inputInfo{
                                {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
@@ -25845,10 +27746,10 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:        "VPAVGW256",
+               name:        "VPCMPEQB128",
                argLen:      2,
                commutative: true,
-               asm:         x86.AVPAVGW,
+               asm:         x86.AVPCMPEQB,
                reg: regInfo{
                        inputs: []inputInfo{
                                {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
@@ -25860,15 +27761,27 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:        "VPAVGWMasked256",
-               argLen:      3,
-               commutative: true,
-               asm:         x86.AVPAVGW,
+               name:   "VPCMPGTB128",
+               argLen: 2,
+               asm:    x86.AVPCMPGTB,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7
+                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                       },
+                       outputs: []outputInfo{
+                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                       },
+               },
+       },
+       {
+               name:   "VPABSBMasked128",
+               argLen: 2,
+               asm:    x86.AVPABSB,
+               reg: regInfo{
+                       inputs: []inputInfo{
+                               {1, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7
                                {0, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
-                               {1, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
                        },
                        outputs: []outputInfo{
                                {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
@@ -25876,10 +27789,10 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:        "VPMAXUWMasked256",
+               name:        "VPADDBMasked128",
                argLen:      3,
                commutative: true,
-               asm:         x86.AVPMAXUW,
+               asm:         x86.AVPADDB,
                reg: regInfo{
                        inputs: []inputInfo{
                                {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7
@@ -25892,10 +27805,10 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:        "VPMINUWMasked256",
+               name:        "VPMAXSBMasked128",
                argLen:      3,
                commutative: true,
-               asm:         x86.AVPMINUW,
+               asm:         x86.AVPMAXSB,
                reg: regInfo{
                        inputs: []inputInfo{
                                {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7
@@ -25908,10 +27821,10 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:        "VPMULHUWMasked256",
+               name:        "VPMINSBMasked128",
                argLen:      3,
                commutative: true,
-               asm:         x86.AVPMULHUW,
+               asm:         x86.AVPMINSB,
                reg: regInfo{
                        inputs: []inputInfo{
                                {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7
@@ -25924,14 +27837,13 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:        "VPMAXUW256",
-               argLen:      2,
-               commutative: true,
-               asm:         x86.AVPMAXUW,
+               name:   "VPOPCNTBMasked128",
+               argLen: 2,
+               asm:    x86.AVPOPCNTB,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
-                               {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {1, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7
+                               {0, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
                        },
                        outputs: []outputInfo{
                                {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
@@ -25939,14 +27851,15 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:        "VPMINUW256",
-               argLen:      2,
+               name:        "VPADDSBMasked128",
+               argLen:      3,
                commutative: true,
-               asm:         x86.AVPMINUW,
+               asm:         x86.AVPADDSB,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
-                               {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7
+                               {0, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {1, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
                        },
                        outputs: []outputInfo{
                                {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
@@ -25954,14 +27867,29 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:        "VPMULHUW256",
-               argLen:      2,
-               commutative: true,
-               asm:         x86.AVPMULHUW,
+               name:   "VPSUBSBMasked128",
+               argLen: 3,
+               asm:    x86.AVPSUBSB,
                reg: regInfo{
                        inputs: []inputInfo{
+                               {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7
+                               {0, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {1, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                       },
+                       outputs: []outputInfo{
                                {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
-                               {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                       },
+               },
+       },
+       {
+               name:   "VPSUBBMasked128",
+               argLen: 3,
+               asm:    x86.AVPSUBB,
+               reg: regInfo{
+                       inputs: []inputInfo{
+                               {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7
+                               {0, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {1, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
                        },
                        outputs: []outputInfo{
                                {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
@@ -25969,10 +27897,10 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:        "VPAVGW512",
+               name:        "VPMAXSB128",
                argLen:      2,
                commutative: true,
-               asm:         x86.AVPAVGW,
+               asm:         x86.AVPMAXSB,
                reg: regInfo{
                        inputs: []inputInfo{
                                {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
@@ -25984,15 +27912,14 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:        "VPAVGWMasked512",
-               argLen:      3,
+               name:        "VPMINSB128",
+               argLen:      2,
                commutative: true,
-               asm:         x86.AVPAVGW,
+               asm:         x86.AVPMINSB,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7
-                               {0, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
-                               {1, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
                        },
                        outputs: []outputInfo{
                                {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
@@ -26000,15 +27927,14 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:        "VPMAXUWMasked512",
-               argLen:      3,
+               name:        "VPOR128",
+               argLen:      2,
                commutative: true,
-               asm:         x86.AVPMAXUW,
+               asm:         x86.AVPOR,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7
-                               {0, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
-                               {1, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
                        },
                        outputs: []outputInfo{
                                {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
@@ -26016,15 +27942,12 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:        "VPMINUWMasked512",
-               argLen:      3,
-               commutative: true,
-               asm:         x86.AVPMINUW,
+               name:   "VPOPCNTB128",
+               argLen: 1,
+               asm:    x86.AVPOPCNTB,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7
-                               {0, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
-                               {1, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
                        },
                        outputs: []outputInfo{
                                {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
@@ -26032,15 +27955,14 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:        "VPMULHUWMasked512",
-               argLen:      3,
+               name:        "VPADDSB128",
+               argLen:      2,
                commutative: true,
-               asm:         x86.AVPMULHUW,
+               asm:         x86.AVPADDSB,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7
-                               {0, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
-                               {1, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
                        },
                        outputs: []outputInfo{
                                {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
@@ -26048,10 +27970,9 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:        "VPMAXUW512",
-               argLen:      2,
-               commutative: true,
-               asm:         x86.AVPMAXUW,
+               name:   "VPSUBSB128",
+               argLen: 2,
+               asm:    x86.AVPSUBSB,
                reg: regInfo{
                        inputs: []inputInfo{
                                {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
@@ -26063,10 +27984,9 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:        "VPMINUW512",
-               argLen:      2,
-               commutative: true,
-               asm:         x86.AVPMINUW,
+               name:   "VPSIGNB128",
+               argLen: 2,
+               asm:    x86.AVPSIGNB,
                reg: regInfo{
                        inputs: []inputInfo{
                                {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
@@ -26078,10 +27998,9 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:        "VPMULHUW512",
-               argLen:      2,
-               commutative: true,
-               asm:         x86.AVPMULHUW,
+               name:   "VPSUBB128",
+               argLen: 2,
+               asm:    x86.AVPSUBB,
                reg: regInfo{
                        inputs: []inputInfo{
                                {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
@@ -26093,10 +28012,10 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:        "VPAVGW128",
+               name:        "VPXOR128",
                argLen:      2,
                commutative: true,
-               asm:         x86.AVPAVGW,
+               asm:         x86.AVPXOR,
                reg: regInfo{
                        inputs: []inputInfo{
                                {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
@@ -26108,15 +28027,12 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:        "VPAVGWMasked128",
-               argLen:      3,
-               commutative: true,
-               asm:         x86.AVPAVGW,
+               name:   "VPABSB256",
+               argLen: 1,
+               asm:    x86.AVPABSB,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7
-                               {0, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
-                               {1, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
                        },
                        outputs: []outputInfo{
                                {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
@@ -26124,15 +28040,14 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:        "VPMAXUWMasked128",
-               argLen:      3,
+               name:        "VPADDB256",
+               argLen:      2,
                commutative: true,
-               asm:         x86.AVPMAXUW,
+               asm:         x86.AVPADDB,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7
-                               {0, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
-                               {1, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
                        },
                        outputs: []outputInfo{
                                {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
@@ -26140,15 +28055,14 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:        "VPMINUWMasked128",
-               argLen:      3,
+               name:        "VPAND256",
+               argLen:      2,
                commutative: true,
-               asm:         x86.AVPMINUW,
+               asm:         x86.AVPAND,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7
-                               {0, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
-                               {1, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
                        },
                        outputs: []outputInfo{
                                {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
@@ -26156,15 +28070,13 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:        "VPMULHUWMasked128",
-               argLen:      3,
-               commutative: true,
-               asm:         x86.AVPMULHUW,
+               name:   "VPANDN256",
+               argLen: 2,
+               asm:    x86.AVPANDN,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7
-                               {0, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
-                               {1, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
                        },
                        outputs: []outputInfo{
                                {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
@@ -26172,10 +28084,10 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:        "VPMAXUW128",
+               name:        "VPCMPEQB256",
                argLen:      2,
                commutative: true,
-               asm:         x86.AVPMAXUW,
+               asm:         x86.AVPCMPEQB,
                reg: regInfo{
                        inputs: []inputInfo{
                                {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
@@ -26187,10 +28099,9 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:        "VPMINUW128",
-               argLen:      2,
-               commutative: true,
-               asm:         x86.AVPMINUW,
+               name:   "VPCMPGTB256",
+               argLen: 2,
+               asm:    x86.AVPCMPGTB,
                reg: regInfo{
                        inputs: []inputInfo{
                                {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
@@ -26202,14 +28113,13 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:        "VPMULHUW128",
-               argLen:      2,
-               commutative: true,
-               asm:         x86.AVPMULHUW,
+               name:   "VPABSBMasked256",
+               argLen: 2,
+               asm:    x86.AVPABSB,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
-                               {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {1, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7
+                               {0, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
                        },
                        outputs: []outputInfo{
                                {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
@@ -26217,10 +28127,10 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:        "VPMAXUDMasked512",
+               name:        "VPADDBMasked256",
                argLen:      3,
                commutative: true,
-               asm:         x86.AVPMAXUD,
+               asm:         x86.AVPADDB,
                reg: regInfo{
                        inputs: []inputInfo{
                                {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7
@@ -26233,10 +28143,10 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:        "VPMINUDMasked512",
+               name:        "VPMAXSBMasked256",
                argLen:      3,
                commutative: true,
-               asm:         x86.AVPMINUD,
+               asm:         x86.AVPMAXSB,
                reg: regInfo{
                        inputs: []inputInfo{
                                {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7
@@ -26249,14 +28159,15 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:        "VPMAXUD512",
-               argLen:      2,
+               name:        "VPMINSBMasked256",
+               argLen:      3,
                commutative: true,
-               asm:         x86.AVPMAXUD,
+               asm:         x86.AVPMINSB,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
-                               {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7
+                               {0, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {1, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
                        },
                        outputs: []outputInfo{
                                {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
@@ -26264,14 +28175,13 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:        "VPMINUD512",
-               argLen:      2,
-               commutative: true,
-               asm:         x86.AVPMINUD,
+               name:   "VPOPCNTBMasked256",
+               argLen: 2,
+               asm:    x86.AVPOPCNTB,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
-                               {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {1, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7
+                               {0, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
                        },
                        outputs: []outputInfo{
                                {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
@@ -26279,10 +28189,10 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:        "VPMAXUDMasked128",
+               name:        "VPADDSBMasked256",
                argLen:      3,
                commutative: true,
-               asm:         x86.AVPMAXUD,
+               asm:         x86.AVPADDSB,
                reg: regInfo{
                        inputs: []inputInfo{
                                {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7
@@ -26295,10 +28205,9 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:        "VPMINUDMasked128",
-               argLen:      3,
-               commutative: true,
-               asm:         x86.AVPMINUD,
+               name:   "VPSUBSBMasked256",
+               argLen: 3,
+               asm:    x86.AVPSUBSB,
                reg: regInfo{
                        inputs: []inputInfo{
                                {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7
@@ -26311,14 +28220,14 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:        "VPMAXUD128",
-               argLen:      2,
-               commutative: true,
-               asm:         x86.AVPMAXUD,
+               name:   "VPSUBBMasked256",
+               argLen: 3,
+               asm:    x86.AVPSUBB,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
-                               {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7
+                               {0, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {1, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
                        },
                        outputs: []outputInfo{
                                {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
@@ -26326,10 +28235,10 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:        "VPMINUD128",
+               name:        "VPMAXSB256",
                argLen:      2,
                commutative: true,
-               asm:         x86.AVPMINUD,
+               asm:         x86.AVPMAXSB,
                reg: regInfo{
                        inputs: []inputInfo{
                                {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
@@ -26341,10 +28250,10 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:        "VPMULUDQ128",
+               name:        "VPMINSB256",
                argLen:      2,
                commutative: true,
-               asm:         x86.AVPMULUDQ,
+               asm:         x86.AVPMINSB,
                reg: regInfo{
                        inputs: []inputInfo{
                                {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
@@ -26356,15 +28265,14 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:        "VPMAXUDMasked256",
-               argLen:      3,
+               name:        "VPOR256",
+               argLen:      2,
                commutative: true,
-               asm:         x86.AVPMAXUD,
+               asm:         x86.AVPOR,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7
-                               {0, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
-                               {1, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
                        },
                        outputs: []outputInfo{
                                {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
@@ -26372,15 +28280,12 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:        "VPMINUDMasked256",
-               argLen:      3,
-               commutative: true,
-               asm:         x86.AVPMINUD,
+               name:   "VPOPCNTB256",
+               argLen: 1,
+               asm:    x86.AVPOPCNTB,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7
-                               {0, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
-                               {1, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
                        },
                        outputs: []outputInfo{
                                {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
@@ -26388,10 +28293,10 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:        "VPMAXUD256",
+               name:        "VPADDSB256",
                argLen:      2,
                commutative: true,
-               asm:         x86.AVPMAXUD,
+               asm:         x86.AVPADDSB,
                reg: regInfo{
                        inputs: []inputInfo{
                                {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
@@ -26403,10 +28308,9 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:        "VPMINUD256",
-               argLen:      2,
-               commutative: true,
-               asm:         x86.AVPMINUD,
+               name:   "VPSUBSB256",
+               argLen: 2,
+               asm:    x86.AVPSUBSB,
                reg: regInfo{
                        inputs: []inputInfo{
                                {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
@@ -26418,10 +28322,9 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:        "VPMULUDQ256",
-               argLen:      2,
-               commutative: true,
-               asm:         x86.AVPMULUDQ,
+               name:   "VPSIGNB256",
+               argLen: 2,
+               asm:    x86.AVPSIGNB,
                reg: regInfo{
                        inputs: []inputInfo{
                                {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
@@ -26433,15 +28336,13 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:        "VPMAXUQMasked128",
-               argLen:      3,
-               commutative: true,
-               asm:         x86.AVPMAXUQ,
+               name:   "VPSUBB256",
+               argLen: 2,
+               asm:    x86.AVPSUBB,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7
-                               {0, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
-                               {1, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
                        },
                        outputs: []outputInfo{
                                {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
@@ -26449,15 +28350,14 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:        "VPMINUQMasked128",
-               argLen:      3,
+               name:        "VPXOR256",
+               argLen:      2,
                commutative: true,
-               asm:         x86.AVPMINUQ,
+               asm:         x86.AVPXOR,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7
-                               {0, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
-                               {1, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
                        },
                        outputs: []outputInfo{
                                {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
@@ -26465,15 +28365,12 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:        "VPMULUDQMasked128",
-               argLen:      3,
-               commutative: true,
-               asm:         x86.AVPMULUDQ,
+               name:   "VPABSB512",
+               argLen: 1,
+               asm:    x86.AVPABSB,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7
-                               {0, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
-                               {1, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
                        },
                        outputs: []outputInfo{
                                {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
@@ -26481,10 +28378,10 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:        "VPMAXUQ128",
+               name:        "VPADDB512",
                argLen:      2,
                commutative: true,
-               asm:         x86.AVPMAXUQ,
+               asm:         x86.AVPADDB,
                reg: regInfo{
                        inputs: []inputInfo{
                                {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
@@ -26496,14 +28393,13 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:        "VPMINUQ128",
-               argLen:      2,
-               commutative: true,
-               asm:         x86.AVPMINUQ,
+               name:   "VPABSBMasked512",
+               argLen: 2,
+               asm:    x86.AVPABSB,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
-                               {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {1, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7
+                               {0, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
                        },
                        outputs: []outputInfo{
                                {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
@@ -26511,10 +28407,10 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:        "VPMAXUQMasked256",
+               name:        "VPADDBMasked512",
                argLen:      3,
                commutative: true,
-               asm:         x86.AVPMAXUQ,
+               asm:         x86.AVPADDB,
                reg: regInfo{
                        inputs: []inputInfo{
                                {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7
@@ -26527,10 +28423,10 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:        "VPMINUQMasked256",
+               name:        "VPMAXSBMasked512",
                argLen:      3,
                commutative: true,
-               asm:         x86.AVPMINUQ,
+               asm:         x86.AVPMAXSB,
                reg: regInfo{
                        inputs: []inputInfo{
                                {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7
@@ -26543,10 +28439,10 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:        "VPMULUDQMasked256",
+               name:        "VPMINSBMasked512",
                argLen:      3,
                commutative: true,
-               asm:         x86.AVPMULUDQ,
+               asm:         x86.AVPMINSB,
                reg: regInfo{
                        inputs: []inputInfo{
                                {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7
@@ -26559,29 +28455,13 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:        "VPMAXUQ256",
-               argLen:      2,
-               commutative: true,
-               asm:         x86.AVPMAXUQ,
-               reg: regInfo{
-                       inputs: []inputInfo{
-                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
-                               {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
-                       },
-                       outputs: []outputInfo{
-                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
-                       },
-               },
-       },
-       {
-               name:        "VPMINUQ256",
-               argLen:      2,
-               commutative: true,
-               asm:         x86.AVPMINUQ,
+               name:   "VPOPCNTBMasked512",
+               argLen: 2,
+               asm:    x86.AVPOPCNTB,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
-                               {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {1, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7
+                               {0, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
                        },
                        outputs: []outputInfo{
                                {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
@@ -26589,10 +28469,10 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:        "VPMAXUQMasked512",
+               name:        "VPADDSBMasked512",
                argLen:      3,
                commutative: true,
-               asm:         x86.AVPMAXUQ,
+               asm:         x86.AVPADDSB,
                reg: regInfo{
                        inputs: []inputInfo{
                                {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7
@@ -26605,10 +28485,9 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:        "VPMINUQMasked512",
-               argLen:      3,
-               commutative: true,
-               asm:         x86.AVPMINUQ,
+               name:   "VPSUBSBMasked512",
+               argLen: 3,
+               asm:    x86.AVPSUBSB,
                reg: regInfo{
                        inputs: []inputInfo{
                                {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7
@@ -26621,10 +28500,9 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:        "VPMULUDQMasked512",
-               argLen:      3,
-               commutative: true,
-               asm:         x86.AVPMULUDQ,
+               name:   "VPSUBBMasked512",
+               argLen: 3,
+               asm:    x86.AVPSUBB,
                reg: regInfo{
                        inputs: []inputInfo{
                                {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7
@@ -26637,10 +28515,10 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:        "VPMAXUQ512",
+               name:        "VPMAXSB512",
                argLen:      2,
                commutative: true,
-               asm:         x86.AVPMAXUQ,
+               asm:         x86.AVPMAXSB,
                reg: regInfo{
                        inputs: []inputInfo{
                                {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
@@ -26652,10 +28530,10 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:        "VPMINUQ512",
+               name:        "VPMINSB512",
                argLen:      2,
                commutative: true,
-               asm:         x86.AVPMINUQ,
+               asm:         x86.AVPMINSB,
                reg: regInfo{
                        inputs: []inputInfo{
                                {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
@@ -26667,14 +28545,12 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:        "VPMULUDQ512",
-               argLen:      2,
-               commutative: true,
-               asm:         x86.AVPMULUDQ,
+               name:   "VPOPCNTB512",
+               argLen: 1,
+               asm:    x86.AVPOPCNTB,
                reg: regInfo{
                        inputs: []inputInfo{
                                {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
-                               {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
                        },
                        outputs: []outputInfo{
                                {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
@@ -26682,10 +28558,10 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:        "VPAVGB128",
+               name:        "VPADDSB512",
                argLen:      2,
                commutative: true,
-               asm:         x86.AVPAVGB,
+               asm:         x86.AVPADDSB,
                reg: regInfo{
                        inputs: []inputInfo{
                                {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
@@ -26697,10 +28573,53 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:        "VPAVGBMasked128",
-               argLen:      3,
-               commutative: true,
-               asm:         x86.AVPAVGB,
+               name:   "VPSUBSB512",
+               argLen: 2,
+               asm:    x86.AVPSUBSB,
+               reg: regInfo{
+                       inputs: []inputInfo{
+                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                       },
+                       outputs: []outputInfo{
+                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                       },
+               },
+       },
+       {
+               name:   "VPSUBB512",
+               argLen: 2,
+               asm:    x86.AVPSUBB,
+               reg: regInfo{
+                       inputs: []inputInfo{
+                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                       },
+                       outputs: []outputInfo{
+                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                       },
+               },
+       },
+       {
+               name:        "VPAVGW256",
+               argLen:      2,
+               commutative: true,
+               asm:         x86.AVPAVGW,
+               reg: regInfo{
+                       inputs: []inputInfo{
+                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                       },
+                       outputs: []outputInfo{
+                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                       },
+               },
+       },
+       {
+               name:        "VPAVGWMasked256",
+               argLen:      3,
+               commutative: true,
+               asm:         x86.AVPAVGW,
                reg: regInfo{
                        inputs: []inputInfo{
                                {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7
@@ -26713,10 +28632,10 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:        "VPMAXUBMasked128",
+               name:        "VPMAXUWMasked256",
                argLen:      3,
                commutative: true,
-               asm:         x86.AVPMAXUB,
+               asm:         x86.AVPMAXUW,
                reg: regInfo{
                        inputs: []inputInfo{
                                {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7
@@ -26729,10 +28648,10 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:        "VPMINUBMasked128",
+               name:        "VPMINUWMasked256",
                argLen:      3,
                commutative: true,
-               asm:         x86.AVPMINUB,
+               asm:         x86.AVPMINUW,
                reg: regInfo{
                        inputs: []inputInfo{
                                {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7
@@ -26745,9 +28664,10 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:   "VPMADDUBSWMasked128",
-               argLen: 3,
-               asm:    x86.AVPMADDUBSW,
+               name:        "VPMULHUWMasked256",
+               argLen:      3,
+               commutative: true,
+               asm:         x86.AVPMULHUW,
                reg: regInfo{
                        inputs: []inputInfo{
                                {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7
@@ -26760,10 +28680,10 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:        "VPMAXUB128",
+               name:        "VPMAXUW256",
                argLen:      2,
                commutative: true,
-               asm:         x86.AVPMAXUB,
+               asm:         x86.AVPMAXUW,
                reg: regInfo{
                        inputs: []inputInfo{
                                {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
@@ -26775,10 +28695,10 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:        "VPMINUB128",
+               name:        "VPMINUW256",
                argLen:      2,
                commutative: true,
-               asm:         x86.AVPMINUB,
+               asm:         x86.AVPMINUW,
                reg: regInfo{
                        inputs: []inputInfo{
                                {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
@@ -26790,9 +28710,10 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:   "VPMADDUBSW128",
-               argLen: 2,
-               asm:    x86.AVPMADDUBSW,
+               name:        "VPMULHUW256",
+               argLen:      2,
+               commutative: true,
+               asm:         x86.AVPMULHUW,
                reg: regInfo{
                        inputs: []inputInfo{
                                {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
@@ -26804,10 +28725,10 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:        "VPAVGB256",
+               name:        "VPAVGW512",
                argLen:      2,
                commutative: true,
-               asm:         x86.AVPAVGB,
+               asm:         x86.AVPAVGW,
                reg: regInfo{
                        inputs: []inputInfo{
                                {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
@@ -26819,10 +28740,10 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:        "VPAVGBMasked256",
+               name:        "VPAVGWMasked512",
                argLen:      3,
                commutative: true,
-               asm:         x86.AVPAVGB,
+               asm:         x86.AVPAVGW,
                reg: regInfo{
                        inputs: []inputInfo{
                                {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7
@@ -26835,10 +28756,10 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:        "VPMAXUBMasked256",
+               name:        "VPMAXUWMasked512",
                argLen:      3,
                commutative: true,
-               asm:         x86.AVPMAXUB,
+               asm:         x86.AVPMAXUW,
                reg: regInfo{
                        inputs: []inputInfo{
                                {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7
@@ -26851,10 +28772,10 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:        "VPMINUBMasked256",
+               name:        "VPMINUWMasked512",
                argLen:      3,
                commutative: true,
-               asm:         x86.AVPMINUB,
+               asm:         x86.AVPMINUW,
                reg: regInfo{
                        inputs: []inputInfo{
                                {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7
@@ -26867,9 +28788,10 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:   "VPMADDUBSWMasked256",
-               argLen: 3,
-               asm:    x86.AVPMADDUBSW,
+               name:        "VPMULHUWMasked512",
+               argLen:      3,
+               commutative: true,
+               asm:         x86.AVPMULHUW,
                reg: regInfo{
                        inputs: []inputInfo{
                                {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7
@@ -26882,10 +28804,10 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:        "VPMAXUB256",
+               name:        "VPMAXUW512",
                argLen:      2,
                commutative: true,
-               asm:         x86.AVPMAXUB,
+               asm:         x86.AVPMAXUW,
                reg: regInfo{
                        inputs: []inputInfo{
                                {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
@@ -26897,10 +28819,10 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:        "VPMINUB256",
+               name:        "VPMINUW512",
                argLen:      2,
                commutative: true,
-               asm:         x86.AVPMINUB,
+               asm:         x86.AVPMINUW,
                reg: regInfo{
                        inputs: []inputInfo{
                                {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
@@ -26912,9 +28834,10 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:   "VPMADDUBSW256",
-               argLen: 2,
-               asm:    x86.AVPMADDUBSW,
+               name:        "VPMULHUW512",
+               argLen:      2,
+               commutative: true,
+               asm:         x86.AVPMULHUW,
                reg: regInfo{
                        inputs: []inputInfo{
                                {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
@@ -26926,10 +28849,10 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:        "VPAVGB512",
+               name:        "VPAVGW128",
                argLen:      2,
                commutative: true,
-               asm:         x86.AVPAVGB,
+               asm:         x86.AVPAVGW,
                reg: regInfo{
                        inputs: []inputInfo{
                                {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
@@ -26941,10 +28864,10 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:        "VPAVGBMasked512",
+               name:        "VPAVGWMasked128",
                argLen:      3,
                commutative: true,
-               asm:         x86.AVPAVGB,
+               asm:         x86.AVPAVGW,
                reg: regInfo{
                        inputs: []inputInfo{
                                {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7
@@ -26957,10 +28880,10 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:        "VPMAXUBMasked512",
+               name:        "VPMAXUWMasked128",
                argLen:      3,
                commutative: true,
-               asm:         x86.AVPMAXUB,
+               asm:         x86.AVPMAXUW,
                reg: regInfo{
                        inputs: []inputInfo{
                                {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7
@@ -26973,10 +28896,10 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:        "VPMINUBMasked512",
+               name:        "VPMINUWMasked128",
                argLen:      3,
                commutative: true,
-               asm:         x86.AVPMINUB,
+               asm:         x86.AVPMINUW,
                reg: regInfo{
                        inputs: []inputInfo{
                                {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7
@@ -26989,9 +28912,10 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:   "VPMADDUBSWMasked512",
-               argLen: 3,
-               asm:    x86.AVPMADDUBSW,
+               name:        "VPMULHUWMasked128",
+               argLen:      3,
+               commutative: true,
+               asm:         x86.AVPMULHUW,
                reg: regInfo{
                        inputs: []inputInfo{
                                {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7
@@ -27004,10 +28928,10 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:        "VPMAXUB512",
+               name:        "VPMAXUW128",
                argLen:      2,
                commutative: true,
-               asm:         x86.AVPMAXUB,
+               asm:         x86.AVPMAXUW,
                reg: regInfo{
                        inputs: []inputInfo{
                                {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
@@ -27019,10 +28943,10 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:        "VPMINUB512",
+               name:        "VPMINUW128",
                argLen:      2,
                commutative: true,
-               asm:         x86.AVPMINUB,
+               asm:         x86.AVPMINUW,
                reg: regInfo{
                        inputs: []inputInfo{
                                {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
@@ -27034,9 +28958,10 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:   "VPMADDUBSW512",
-               argLen: 2,
-               asm:    x86.AVPMADDUBSW,
+               name:        "VPMULHUW128",
+               argLen:      2,
+               commutative: true,
+               asm:         x86.AVPMULHUW,
                reg: regInfo{
                        inputs: []inputInfo{
                                {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
@@ -27048,13 +28973,15 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:    "VRNDSCALEPS512",
-               auxType: auxInt8,
-               argLen:  1,
-               asm:     x86.AVRNDSCALEPS,
+               name:        "VPMAXUDMasked512",
+               argLen:      3,
+               commutative: true,
+               asm:         x86.AVPMAXUD,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7
+                               {0, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {1, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
                        },
                        outputs: []outputInfo{
                                {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
@@ -27062,13 +28989,15 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:    "VREDUCEPS512",
-               auxType: auxInt8,
-               argLen:  1,
-               asm:     x86.AVREDUCEPS,
+               name:        "VPMINUDMasked512",
+               argLen:      3,
+               commutative: true,
+               asm:         x86.AVPMINUD,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7
+                               {0, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {1, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
                        },
                        outputs: []outputInfo{
                                {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
@@ -27076,30 +29005,29 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:        "VCMPPS512",
-               auxType:     auxInt8,
+               name:        "VPMAXUD512",
                argLen:      2,
                commutative: true,
-               asm:         x86.AVCMPPS,
+               asm:         x86.AVPMAXUD,
                reg: regInfo{
                        inputs: []inputInfo{
                                {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
                                {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
                        },
                        outputs: []outputInfo{
-                               {0, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7
+                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
                        },
                },
        },
        {
-               name:    "VRNDSCALEPSMasked512",
-               auxType: auxInt8,
-               argLen:  2,
-               asm:     x86.AVRNDSCALEPS,
+               name:        "VPMINUD512",
+               argLen:      2,
+               commutative: true,
+               asm:         x86.AVPMINUD,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {1, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7
-                               {0, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
                        },
                        outputs: []outputInfo{
                                {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
@@ -27107,14 +29035,15 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:    "VREDUCEPSMasked512",
-               auxType: auxInt8,
-               argLen:  2,
-               asm:     x86.AVREDUCEPS,
+               name:        "VPMAXUDMasked128",
+               argLen:      3,
+               commutative: true,
+               asm:         x86.AVPMAXUD,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {1, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7
+                               {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7
                                {0, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {1, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
                        },
                        outputs: []outputInfo{
                                {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
@@ -27122,44 +29051,30 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:        "VCMPPSMasked512",
-               auxType:     auxInt8,
+               name:        "VPMINUDMasked128",
                argLen:      3,
                commutative: true,
-               asm:         x86.AVCMPPS,
+               asm:         x86.AVPMINUD,
                reg: regInfo{
                        inputs: []inputInfo{
                                {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7
                                {0, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
                                {1, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
                        },
-                       outputs: []outputInfo{
-                               {0, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7
-                       },
-               },
-       },
-       {
-               name:    "VROUNDPS128",
-               auxType: auxInt8,
-               argLen:  1,
-               asm:     x86.AVROUNDPS,
-               reg: regInfo{
-                       inputs: []inputInfo{
-                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
-                       },
                        outputs: []outputInfo{
                                {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
                        },
                },
        },
        {
-               name:    "VRNDSCALEPS128",
-               auxType: auxInt8,
-               argLen:  1,
-               asm:     x86.AVRNDSCALEPS,
+               name:        "VPMAXUD128",
+               argLen:      2,
+               commutative: true,
+               asm:         x86.AVPMAXUD,
                reg: regInfo{
                        inputs: []inputInfo{
                                {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
                        },
                        outputs: []outputInfo{
                                {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
@@ -27167,13 +29082,14 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:    "VREDUCEPS128",
-               auxType: auxInt8,
-               argLen:  1,
-               asm:     x86.AVREDUCEPS,
+               name:        "VPMINUD128",
+               argLen:      2,
+               commutative: true,
+               asm:         x86.AVPMINUD,
                reg: regInfo{
                        inputs: []inputInfo{
                                {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
                        },
                        outputs: []outputInfo{
                                {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
@@ -27181,11 +29097,10 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:        "VCMPPS128",
-               auxType:     auxInt8,
+               name:        "VPMULUDQ128",
                argLen:      2,
                commutative: true,
-               asm:         x86.AVCMPPS,
+               asm:         x86.AVPMULUDQ,
                reg: regInfo{
                        inputs: []inputInfo{
                                {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
@@ -27197,14 +29112,15 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:    "VRNDSCALEPSMasked128",
-               auxType: auxInt8,
-               argLen:  2,
-               asm:     x86.AVRNDSCALEPS,
+               name:        "VPMAXUDMasked256",
+               argLen:      3,
+               commutative: true,
+               asm:         x86.AVPMAXUD,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {1, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7
+                               {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7
                                {0, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {1, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
                        },
                        outputs: []outputInfo{
                                {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
@@ -27212,14 +29128,15 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:    "VREDUCEPSMasked128",
-               auxType: auxInt8,
-               argLen:  2,
-               asm:     x86.AVREDUCEPS,
+               name:        "VPMINUDMasked256",
+               argLen:      3,
+               commutative: true,
+               asm:         x86.AVPMINUD,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {1, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7
+                               {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7
                                {0, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {1, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
                        },
                        outputs: []outputInfo{
                                {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
@@ -27227,30 +29144,29 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:        "VCMPPSMasked128",
-               auxType:     auxInt8,
-               argLen:      3,
+               name:        "VPMAXUD256",
+               argLen:      2,
                commutative: true,
-               asm:         x86.AVCMPPS,
+               asm:         x86.AVPMAXUD,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7
-                               {0, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
-                               {1, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
                        },
                        outputs: []outputInfo{
-                               {0, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7
+                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
                        },
                },
        },
        {
-               name:    "VROUNDPS256",
-               auxType: auxInt8,
-               argLen:  1,
-               asm:     x86.AVROUNDPS,
+               name:        "VPMINUD256",
+               argLen:      2,
+               commutative: true,
+               asm:         x86.AVPMINUD,
                reg: regInfo{
                        inputs: []inputInfo{
                                {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
                        },
                        outputs: []outputInfo{
                                {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
@@ -27258,13 +29174,14 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:    "VRNDSCALEPS256",
-               auxType: auxInt8,
-               argLen:  1,
-               asm:     x86.AVRNDSCALEPS,
+               name:        "VPMULUDQ256",
+               argLen:      2,
+               commutative: true,
+               asm:         x86.AVPMULUDQ,
                reg: regInfo{
                        inputs: []inputInfo{
                                {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
                        },
                        outputs: []outputInfo{
                                {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
@@ -27272,13 +29189,15 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:    "VREDUCEPS256",
-               auxType: auxInt8,
-               argLen:  1,
-               asm:     x86.AVREDUCEPS,
+               name:        "VPMAXUQMasked128",
+               argLen:      3,
+               commutative: true,
+               asm:         x86.AVPMAXUQ,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7
+                               {0, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {1, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
                        },
                        outputs: []outputInfo{
                                {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
@@ -27286,15 +29205,15 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:        "VCMPPS256",
-               auxType:     auxInt8,
-               argLen:      2,
+               name:        "VPMINUQMasked128",
+               argLen:      3,
                commutative: true,
-               asm:         x86.AVCMPPS,
+               asm:         x86.AVPMINUQ,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
-                               {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7
+                               {0, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {1, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
                        },
                        outputs: []outputInfo{
                                {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
@@ -27302,14 +29221,15 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:    "VRNDSCALEPSMasked256",
-               auxType: auxInt8,
-               argLen:  2,
-               asm:     x86.AVRNDSCALEPS,
+               name:        "VPMULUDQMasked128",
+               argLen:      3,
+               commutative: true,
+               asm:         x86.AVPMULUDQ,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {1, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7
+                               {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7
                                {0, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {1, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
                        },
                        outputs: []outputInfo{
                                {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
@@ -27317,14 +29237,14 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:    "VREDUCEPSMasked256",
-               auxType: auxInt8,
-               argLen:  2,
-               asm:     x86.AVREDUCEPS,
+               name:        "VPMAXUQ128",
+               argLen:      2,
+               commutative: true,
+               asm:         x86.AVPMAXUQ,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {1, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7
-                               {0, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
                        },
                        outputs: []outputInfo{
                                {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
@@ -27332,30 +29252,30 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:        "VCMPPSMasked256",
-               auxType:     auxInt8,
-               argLen:      3,
+               name:        "VPMINUQ128",
+               argLen:      2,
                commutative: true,
-               asm:         x86.AVCMPPS,
+               asm:         x86.AVPMINUQ,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7
-                               {0, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
-                               {1, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
                        },
                        outputs: []outputInfo{
-                               {0, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7
+                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
                        },
                },
        },
        {
-               name:    "VROUNDPD128",
-               auxType: auxInt8,
-               argLen:  1,
-               asm:     x86.AVROUNDPD,
+               name:        "VPMAXUQMasked256",
+               argLen:      3,
+               commutative: true,
+               asm:         x86.AVPMAXUQ,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7
+                               {0, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {1, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
                        },
                        outputs: []outputInfo{
                                {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
@@ -27363,13 +29283,15 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:    "VRNDSCALEPD128",
-               auxType: auxInt8,
-               argLen:  1,
-               asm:     x86.AVRNDSCALEPD,
+               name:        "VPMINUQMasked256",
+               argLen:      3,
+               commutative: true,
+               asm:         x86.AVPMINUQ,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7
+                               {0, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {1, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
                        },
                        outputs: []outputInfo{
                                {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
@@ -27377,13 +29299,15 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:    "VREDUCEPD128",
-               auxType: auxInt8,
-               argLen:  1,
-               asm:     x86.AVREDUCEPD,
+               name:        "VPMULUDQMasked256",
+               argLen:      3,
+               commutative: true,
+               asm:         x86.AVPMULUDQ,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7
+                               {0, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {1, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
                        },
                        outputs: []outputInfo{
                                {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
@@ -27391,11 +29315,10 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:        "VDPPD128",
-               auxType:     auxInt8,
+               name:        "VPMAXUQ256",
                argLen:      2,
                commutative: true,
-               asm:         x86.AVDPPD,
+               asm:         x86.AVPMAXUQ,
                reg: regInfo{
                        inputs: []inputInfo{
                                {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
@@ -27407,11 +29330,10 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:        "VCMPPD128",
-               auxType:     auxInt8,
+               name:        "VPMINUQ256",
                argLen:      2,
                commutative: true,
-               asm:         x86.AVCMPPD,
+               asm:         x86.AVPMINUQ,
                reg: regInfo{
                        inputs: []inputInfo{
                                {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
@@ -27423,14 +29345,15 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:    "VRNDSCALEPDMasked128",
-               auxType: auxInt8,
-               argLen:  2,
-               asm:     x86.AVRNDSCALEPD,
+               name:        "VPMAXUQMasked512",
+               argLen:      3,
+               commutative: true,
+               asm:         x86.AVPMAXUQ,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {1, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7
+                               {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7
                                {0, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {1, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
                        },
                        outputs: []outputInfo{
                                {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
@@ -27438,14 +29361,15 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:    "VREDUCEPDMasked128",
-               auxType: auxInt8,
-               argLen:  2,
-               asm:     x86.AVREDUCEPD,
+               name:        "VPMINUQMasked512",
+               argLen:      3,
+               commutative: true,
+               asm:         x86.AVPMINUQ,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {1, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7
+                               {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7
                                {0, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {1, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
                        },
                        outputs: []outputInfo{
                                {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
@@ -27453,11 +29377,10 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:        "VCMPPDMasked128",
-               auxType:     auxInt8,
+               name:        "VPMULUDQMasked512",
                argLen:      3,
                commutative: true,
-               asm:         x86.AVCMPPD,
+               asm:         x86.AVPMULUDQ,
                reg: regInfo{
                        inputs: []inputInfo{
                                {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7
@@ -27465,18 +29388,19 @@ var opcodeTable = [...]opInfo{
                                {1, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
                        },
                        outputs: []outputInfo{
-                               {0, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7
+                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
                        },
                },
        },
        {
-               name:    "VROUNDPD256",
-               auxType: auxInt8,
-               argLen:  1,
-               asm:     x86.AVROUNDPD,
+               name:        "VPMAXUQ512",
+               argLen:      2,
+               commutative: true,
+               asm:         x86.AVPMAXUQ,
                reg: regInfo{
                        inputs: []inputInfo{
                                {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
                        },
                        outputs: []outputInfo{
                                {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
@@ -27484,13 +29408,14 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:    "VRNDSCALEPD256",
-               auxType: auxInt8,
-               argLen:  1,
-               asm:     x86.AVRNDSCALEPD,
+               name:        "VPMINUQ512",
+               argLen:      2,
+               commutative: true,
+               asm:         x86.AVPMINUQ,
                reg: regInfo{
                        inputs: []inputInfo{
                                {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
                        },
                        outputs: []outputInfo{
                                {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
@@ -27498,13 +29423,14 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:    "VREDUCEPD256",
-               auxType: auxInt8,
-               argLen:  1,
-               asm:     x86.AVREDUCEPD,
+               name:        "VPMULUDQ512",
+               argLen:      2,
+               commutative: true,
+               asm:         x86.AVPMULUDQ,
                reg: regInfo{
                        inputs: []inputInfo{
                                {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
                        },
                        outputs: []outputInfo{
                                {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
@@ -27512,11 +29438,10 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:        "VCMPPD256",
-               auxType:     auxInt8,
+               name:        "VPAVGB128",
                argLen:      2,
                commutative: true,
-               asm:         x86.AVCMPPD,
+               asm:         x86.AVPAVGB,
                reg: regInfo{
                        inputs: []inputInfo{
                                {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
@@ -27528,14 +29453,15 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:    "VRNDSCALEPDMasked256",
-               auxType: auxInt8,
-               argLen:  2,
-               asm:     x86.AVRNDSCALEPD,
+               name:        "VPAVGBMasked128",
+               argLen:      3,
+               commutative: true,
+               asm:         x86.AVPAVGB,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {1, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7
+                               {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7
                                {0, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {1, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
                        },
                        outputs: []outputInfo{
                                {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
@@ -27543,14 +29469,15 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:    "VREDUCEPDMasked256",
-               auxType: auxInt8,
-               argLen:  2,
-               asm:     x86.AVREDUCEPD,
+               name:        "VPMAXUBMasked128",
+               argLen:      3,
+               commutative: true,
+               asm:         x86.AVPMAXUB,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {1, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7
+                               {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7
                                {0, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {1, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
                        },
                        outputs: []outputInfo{
                                {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
@@ -27558,11 +29485,10 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:        "VCMPPDMasked256",
-               auxType:     auxInt8,
+               name:        "VPMINUBMasked128",
                argLen:      3,
                commutative: true,
-               asm:         x86.AVCMPPD,
+               asm:         x86.AVPMINUB,
                reg: regInfo{
                        inputs: []inputInfo{
                                {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7
@@ -27570,18 +29496,19 @@ var opcodeTable = [...]opInfo{
                                {1, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
                        },
                        outputs: []outputInfo{
-                               {0, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7
+                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
                        },
                },
        },
        {
-               name:    "VRNDSCALEPD512",
-               auxType: auxInt8,
-               argLen:  1,
-               asm:     x86.AVRNDSCALEPD,
+               name:   "VPMADDUBSWMasked128",
+               argLen: 3,
+               asm:    x86.AVPMADDUBSW,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7
+                               {0, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {1, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
                        },
                        outputs: []outputInfo{
                                {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
@@ -27589,13 +29516,14 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:    "VREDUCEPD512",
-               auxType: auxInt8,
-               argLen:  1,
-               asm:     x86.AVREDUCEPD,
+               name:        "VPMAXUB128",
+               argLen:      2,
+               commutative: true,
+               asm:         x86.AVPMAXUB,
                reg: regInfo{
                        inputs: []inputInfo{
                                {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
                        },
                        outputs: []outputInfo{
                                {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
@@ -27603,30 +29531,28 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:        "VCMPPD512",
-               auxType:     auxInt8,
+               name:        "VPMINUB128",
                argLen:      2,
                commutative: true,
-               asm:         x86.AVCMPPD,
+               asm:         x86.AVPMINUB,
                reg: regInfo{
                        inputs: []inputInfo{
                                {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
                                {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
                        },
                        outputs: []outputInfo{
-                               {0, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7
+                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
                        },
                },
        },
        {
-               name:    "VRNDSCALEPDMasked512",
-               auxType: auxInt8,
-               argLen:  2,
-               asm:     x86.AVRNDSCALEPD,
+               name:   "VPMADDUBSW128",
+               argLen: 2,
+               asm:    x86.AVPMADDUBSW,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {1, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7
-                               {0, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
                        },
                        outputs: []outputInfo{
                                {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
@@ -27634,14 +29560,14 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:    "VREDUCEPDMasked512",
-               auxType: auxInt8,
-               argLen:  2,
-               asm:     x86.AVREDUCEPD,
+               name:        "VPAVGB256",
+               argLen:      2,
+               commutative: true,
+               asm:         x86.AVPAVGB,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {1, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7
-                               {0, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
                        },
                        outputs: []outputInfo{
                                {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
@@ -27649,11 +29575,10 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:        "VCMPPDMasked512",
-               auxType:     auxInt8,
+               name:        "VPAVGBMasked256",
                argLen:      3,
                commutative: true,
-               asm:         x86.AVCMPPD,
+               asm:         x86.AVPAVGB,
                reg: regInfo{
                        inputs: []inputInfo{
                                {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7
@@ -27661,31 +29586,31 @@ var opcodeTable = [...]opInfo{
                                {1, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
                        },
                        outputs: []outputInfo{
-                               {0, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7
+                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
                        },
                },
        },
        {
-               name:    "VPCMPW256",
-               auxType: auxInt8,
-               argLen:  2,
-               asm:     x86.AVPCMPW,
+               name:        "VPMAXUBMasked256",
+               argLen:      3,
+               commutative: true,
+               asm:         x86.AVPMAXUB,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
-                               {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7
+                               {0, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {1, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
                        },
                        outputs: []outputInfo{
-                               {0, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7
+                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
                        },
                },
        },
        {
-               name:        "VPCMPWMasked256",
-               auxType:     auxInt8,
+               name:        "VPMINUBMasked256",
                argLen:      3,
                commutative: true,
-               asm:         x86.AVPCMPW,
+               asm:         x86.AVPMINUB,
                reg: regInfo{
                        inputs: []inputInfo{
                                {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7
@@ -27693,78 +29618,89 @@ var opcodeTable = [...]opInfo{
                                {1, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
                        },
                        outputs: []outputInfo{
-                               {0, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7
+                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
                        },
                },
        },
        {
-               name:        "VPCMPW512",
-               auxType:     auxInt8,
+               name:   "VPMADDUBSWMasked256",
+               argLen: 3,
+               asm:    x86.AVPMADDUBSW,
+               reg: regInfo{
+                       inputs: []inputInfo{
+                               {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7
+                               {0, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {1, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                       },
+                       outputs: []outputInfo{
+                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                       },
+               },
+       },
+       {
+               name:        "VPMAXUB256",
                argLen:      2,
                commutative: true,
-               asm:         x86.AVPCMPW,
+               asm:         x86.AVPMAXUB,
                reg: regInfo{
                        inputs: []inputInfo{
                                {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
                                {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
                        },
                        outputs: []outputInfo{
-                               {0, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7
+                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
                        },
                },
        },
        {
-               name:        "VPCMPWMasked512",
-               auxType:     auxInt8,
-               argLen:      3,
+               name:        "VPMINUB256",
+               argLen:      2,
                commutative: true,
-               asm:         x86.AVPCMPW,
+               asm:         x86.AVPMINUB,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7
-                               {0, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
-                               {1, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
                        },
                        outputs: []outputInfo{
-                               {0, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7
+                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
                        },
                },
        },
        {
-               name:    "VPEXTRW128",
-               auxType: auxInt8,
-               argLen:  1,
-               asm:     x86.AVPEXTRW,
+               name:   "VPMADDUBSW256",
+               argLen: 2,
+               asm:    x86.AVPMADDUBSW,
                reg: regInfo{
                        inputs: []inputInfo{
                                {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
                        },
                        outputs: []outputInfo{
-                               {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
+                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
                        },
                },
        },
        {
-               name:    "VPCMPW128",
-               auxType: auxInt8,
-               argLen:  2,
-               asm:     x86.AVPCMPW,
+               name:        "VPAVGB512",
+               argLen:      2,
+               commutative: true,
+               asm:         x86.AVPAVGB,
                reg: regInfo{
                        inputs: []inputInfo{
                                {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
                                {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
                        },
                        outputs: []outputInfo{
-                               {0, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7
+                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
                        },
                },
        },
        {
-               name:        "VPCMPWMasked128",
-               auxType:     auxInt8,
+               name:        "VPAVGBMasked512",
                argLen:      3,
                commutative: true,
-               asm:         x86.AVPCMPW,
+               asm:         x86.AVPAVGB,
                reg: regInfo{
                        inputs: []inputInfo{
                                {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7
@@ -27772,19 +29708,20 @@ var opcodeTable = [...]opInfo{
                                {1, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
                        },
                        outputs: []outputInfo{
-                               {0, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7
+                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
                        },
                },
        },
        {
-               name:    "VPINSRW128",
-               auxType: auxInt8,
-               argLen:  2,
-               asm:     x86.AVPINSRW,
+               name:        "VPMAXUBMasked512",
+               argLen:      3,
+               commutative: true,
+               asm:         x86.AVPMAXUB,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {1, 49135},      // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
-                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7
+                               {0, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {1, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
                        },
                        outputs: []outputInfo{
                                {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
@@ -27792,27 +29729,25 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:        "VPCMPD512",
-               auxType:     auxInt8,
-               argLen:      2,
+               name:        "VPMINUBMasked512",
+               argLen:      3,
                commutative: true,
-               asm:         x86.AVPCMPD,
+               asm:         x86.AVPMINUB,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
-                               {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7
+                               {0, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {1, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
                        },
                        outputs: []outputInfo{
-                               {0, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7
+                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
                        },
                },
        },
        {
-               name:        "VPCMPDMasked512",
-               auxType:     auxInt8,
-               argLen:      3,
-               commutative: true,
-               asm:         x86.AVPCMPD,
+               name:   "VPMADDUBSWMasked512",
+               argLen: 3,
+               asm:    x86.AVPMADDUBSW,
                reg: regInfo{
                        inputs: []inputInfo{
                                {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7
@@ -27820,64 +29755,61 @@ var opcodeTable = [...]opInfo{
                                {1, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
                        },
                        outputs: []outputInfo{
-                               {0, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7
+                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
                        },
                },
        },
        {
-               name:    "VPEXTRD128",
-               auxType: auxInt8,
-               argLen:  1,
-               asm:     x86.AVPEXTRD,
+               name:        "VPMAXUB512",
+               argLen:      2,
+               commutative: true,
+               asm:         x86.AVPMAXUB,
                reg: regInfo{
                        inputs: []inputInfo{
                                {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
                        },
                        outputs: []outputInfo{
-                               {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
+                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
                        },
                },
        },
        {
-               name:    "VPCMPD128",
-               auxType: auxInt8,
-               argLen:  2,
-               asm:     x86.AVPCMPD,
+               name:        "VPMINUB512",
+               argLen:      2,
+               commutative: true,
+               asm:         x86.AVPMINUB,
                reg: regInfo{
                        inputs: []inputInfo{
                                {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
                                {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
                        },
                        outputs: []outputInfo{
-                               {0, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7
+                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
                        },
                },
        },
        {
-               name:        "VPCMPDMasked128",
-               auxType:     auxInt8,
-               argLen:      3,
-               commutative: true,
-               asm:         x86.AVPCMPD,
+               name:   "VPMADDUBSW512",
+               argLen: 2,
+               asm:    x86.AVPMADDUBSW,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7
-                               {0, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
-                               {1, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
                        },
                        outputs: []outputInfo{
-                               {0, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7
+                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
                        },
                },
        },
        {
-               name:    "VPINSRD128",
+               name:    "VRNDSCALEPS512",
                auxType: auxInt8,
-               argLen:  2,
-               asm:     x86.AVPINSRD,
+               argLen:  1,
+               asm:     x86.AVRNDSCALEPS,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {1, 49135},      // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
                                {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
                        },
                        outputs: []outputInfo{
@@ -27886,31 +29818,29 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:    "VPCMPD256",
+               name:    "VREDUCEPS512",
                auxType: auxInt8,
-               argLen:  2,
-               asm:     x86.AVPCMPD,
+               argLen:  1,
+               asm:     x86.AVREDUCEPS,
                reg: regInfo{
                        inputs: []inputInfo{
                                {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
-                               {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
                        },
                        outputs: []outputInfo{
-                               {0, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7
+                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
                        },
                },
        },
        {
-               name:        "VPCMPDMasked256",
+               name:        "VCMPPS512",
                auxType:     auxInt8,
-               argLen:      3,
+               argLen:      2,
                commutative: true,
-               asm:         x86.AVPCMPD,
+               asm:         x86.AVCMPPS,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7
-                               {0, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
-                               {1, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
                        },
                        outputs: []outputInfo{
                                {0, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7
@@ -27918,40 +29848,41 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:    "VPEXTRQ128",
+               name:    "VRNDSCALEPSMasked512",
                auxType: auxInt8,
-               argLen:  1,
-               asm:     x86.AVPEXTRQ,
+               argLen:  2,
+               asm:     x86.AVRNDSCALEPS,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {1, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7
+                               {0, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
                        },
                        outputs: []outputInfo{
-                               {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
+                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
                        },
                },
        },
        {
-               name:    "VPCMPQ128",
+               name:    "VREDUCEPSMasked512",
                auxType: auxInt8,
                argLen:  2,
-               asm:     x86.AVPCMPQ,
+               asm:     x86.AVREDUCEPS,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
-                               {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {1, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7
+                               {0, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
                        },
                        outputs: []outputInfo{
-                               {0, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7
+                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
                        },
                },
        },
        {
-               name:        "VPCMPQMasked128",
+               name:        "VCMPPSMasked512",
                auxType:     auxInt8,
                argLen:      3,
                commutative: true,
-               asm:         x86.AVPCMPQ,
+               asm:         x86.AVCMPPS,
                reg: regInfo{
                        inputs: []inputInfo{
                                {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7
@@ -27964,13 +29895,12 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:    "VPINSRQ128",
+               name:    "VROUNDPS128",
                auxType: auxInt8,
-               argLen:  2,
-               asm:     x86.AVPINSRQ,
+               argLen:  1,
+               asm:     x86.AVROUNDPS,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {1, 49135},      // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
                                {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
                        },
                        outputs: []outputInfo{
@@ -27979,105 +29909,85 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:    "VPCMPQ256",
+               name:    "VRNDSCALEPS128",
                auxType: auxInt8,
-               argLen:  2,
-               asm:     x86.AVPCMPQ,
+               argLen:  1,
+               asm:     x86.AVRNDSCALEPS,
                reg: regInfo{
                        inputs: []inputInfo{
                                {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
-                               {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
                        },
                        outputs: []outputInfo{
-                               {0, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7
+                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
                        },
                },
        },
        {
-               name:        "VPCMPQMasked256",
-               auxType:     auxInt8,
-               argLen:      3,
-               commutative: true,
-               asm:         x86.AVPCMPQ,
+               name:    "VREDUCEPS128",
+               auxType: auxInt8,
+               argLen:  1,
+               asm:     x86.AVREDUCEPS,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7
-                               {0, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
-                               {1, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
                        },
                        outputs: []outputInfo{
-                               {0, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7
+                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
                        },
                },
        },
        {
-               name:        "VPCMPQ512",
+               name:        "VCMPPS128",
                auxType:     auxInt8,
                argLen:      2,
                commutative: true,
-               asm:         x86.AVPCMPQ,
+               asm:         x86.AVCMPPS,
                reg: regInfo{
                        inputs: []inputInfo{
                                {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
                                {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
                        },
                        outputs: []outputInfo{
-                               {0, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7
+                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
                        },
                },
        },
        {
-               name:        "VPCMPQMasked512",
-               auxType:     auxInt8,
-               argLen:      3,
-               commutative: true,
-               asm:         x86.AVPCMPQ,
+               name:    "VRNDSCALEPSMasked128",
+               auxType: auxInt8,
+               argLen:  2,
+               asm:     x86.AVRNDSCALEPS,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7
+                               {1, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7
                                {0, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
-                               {1, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
                        },
                        outputs: []outputInfo{
-                               {0, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7
-                       },
-               },
-       },
-       {
-               name:    "VPEXTRB128",
-               auxType: auxInt8,
-               argLen:  1,
-               asm:     x86.AVPEXTRB,
-               reg: regInfo{
-                       inputs: []inputInfo{
                                {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
                        },
-                       outputs: []outputInfo{
-                               {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
-                       },
                },
        },
        {
-               name:    "VPCMPB128",
+               name:    "VREDUCEPSMasked128",
                auxType: auxInt8,
                argLen:  2,
-               asm:     x86.AVPCMPB,
+               asm:     x86.AVREDUCEPS,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
-                               {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {1, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7
+                               {0, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
                        },
                        outputs: []outputInfo{
-                               {0, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7
+                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
                        },
                },
        },
        {
-               name:        "VPCMPBMasked128",
+               name:        "VCMPPSMasked128",
                auxType:     auxInt8,
                argLen:      3,
                commutative: true,
-               asm:         x86.AVPCMPB,
+               asm:         x86.AVCMPPS,
                reg: regInfo{
                        inputs: []inputInfo{
                                {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7
@@ -28090,13 +30000,12 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:    "VPINSRB128",
+               name:    "VROUNDPS256",
                auxType: auxInt8,
-               argLen:  2,
-               asm:     x86.AVPINSRB,
+               argLen:  1,
+               asm:     x86.AVROUNDPS,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {1, 49135},      // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
                                {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
                        },
                        outputs: []outputInfo{
@@ -28105,92 +30014,85 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:    "VPCMPB256",
+               name:    "VRNDSCALEPS256",
                auxType: auxInt8,
-               argLen:  2,
-               asm:     x86.AVPCMPB,
+               argLen:  1,
+               asm:     x86.AVRNDSCALEPS,
                reg: regInfo{
                        inputs: []inputInfo{
                                {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
-                               {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
                        },
                        outputs: []outputInfo{
-                               {0, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7
+                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
                        },
                },
        },
        {
-               name:        "VPCMPBMasked256",
-               auxType:     auxInt8,
-               argLen:      3,
-               commutative: true,
-               asm:         x86.AVPCMPB,
+               name:    "VREDUCEPS256",
+               auxType: auxInt8,
+               argLen:  1,
+               asm:     x86.AVREDUCEPS,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7
-                               {0, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
-                               {1, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
                        },
                        outputs: []outputInfo{
-                               {0, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7
+                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
                        },
                },
        },
        {
-               name:        "VPCMPB512",
+               name:        "VCMPPS256",
                auxType:     auxInt8,
                argLen:      2,
                commutative: true,
-               asm:         x86.AVPCMPB,
+               asm:         x86.AVCMPPS,
                reg: regInfo{
                        inputs: []inputInfo{
                                {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
                                {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
                        },
                        outputs: []outputInfo{
-                               {0, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7
+                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
                        },
                },
        },
        {
-               name:        "VPCMPBMasked512",
-               auxType:     auxInt8,
-               argLen:      3,
-               commutative: true,
-               asm:         x86.AVPCMPB,
+               name:    "VRNDSCALEPSMasked256",
+               auxType: auxInt8,
+               argLen:  2,
+               asm:     x86.AVRNDSCALEPS,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7
+                               {1, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7
                                {0, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
-                               {1, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
                        },
                        outputs: []outputInfo{
-                               {0, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7
+                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
                        },
                },
        },
        {
-               name:        "VPCMPUW256",
-               auxType:     auxInt8,
-               argLen:      2,
-               commutative: true,
-               asm:         x86.AVPCMPUW,
+               name:    "VREDUCEPSMasked256",
+               auxType: auxInt8,
+               argLen:  2,
+               asm:     x86.AVREDUCEPS,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
-                               {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {1, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7
+                               {0, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
                        },
                        outputs: []outputInfo{
-                               {0, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7
+                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
                        },
                },
        },
        {
-               name:        "VPCMPUWMasked256",
+               name:        "VCMPPSMasked256",
                auxType:     auxInt8,
                argLen:      3,
                commutative: true,
-               asm:         x86.AVPCMPUW,
+               asm:         x86.AVCMPPS,
                reg: regInfo{
                        inputs: []inputInfo{
                                {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7
@@ -28203,126 +30105,115 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:        "VPCMPUW512",
-               auxType:     auxInt8,
-               argLen:      2,
-               commutative: true,
-               asm:         x86.AVPCMPUW,
+               name:    "VROUNDPD128",
+               auxType: auxInt8,
+               argLen:  1,
+               asm:     x86.AVROUNDPD,
                reg: regInfo{
                        inputs: []inputInfo{
                                {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
-                               {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
                        },
                        outputs: []outputInfo{
-                               {0, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7
+                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
                        },
                },
        },
        {
-               name:        "VPCMPUWMasked512",
-               auxType:     auxInt8,
-               argLen:      3,
-               commutative: true,
-               asm:         x86.AVPCMPUW,
+               name:    "VRNDSCALEPD128",
+               auxType: auxInt8,
+               argLen:  1,
+               asm:     x86.AVRNDSCALEPD,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7
-                               {0, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
-                               {1, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
                        },
                        outputs: []outputInfo{
-                               {0, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7
+                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
                        },
                },
        },
        {
-               name:        "VPCMPUW128",
-               auxType:     auxInt8,
-               argLen:      2,
-               commutative: true,
-               asm:         x86.AVPCMPUW,
+               name:    "VREDUCEPD128",
+               auxType: auxInt8,
+               argLen:  1,
+               asm:     x86.AVREDUCEPD,
                reg: regInfo{
                        inputs: []inputInfo{
                                {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
-                               {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
                        },
                        outputs: []outputInfo{
-                               {0, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7
+                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
                        },
                },
        },
        {
-               name:        "VPCMPUWMasked128",
+               name:        "VDPPD128",
                auxType:     auxInt8,
-               argLen:      3,
+               argLen:      2,
                commutative: true,
-               asm:         x86.AVPCMPUW,
+               asm:         x86.AVDPPD,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7
-                               {0, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
-                               {1, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
                        },
                        outputs: []outputInfo{
-                               {0, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7
+                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
                        },
                },
        },
        {
-               name:        "VPCMPUD512",
+               name:        "VCMPPD128",
                auxType:     auxInt8,
                argLen:      2,
                commutative: true,
-               asm:         x86.AVPCMPUD,
+               asm:         x86.AVCMPPD,
                reg: regInfo{
                        inputs: []inputInfo{
                                {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
                                {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
                        },
                        outputs: []outputInfo{
-                               {0, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7
+                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
                        },
                },
        },
        {
-               name:        "VPCMPUDMasked512",
-               auxType:     auxInt8,
-               argLen:      3,
-               commutative: true,
-               asm:         x86.AVPCMPUD,
+               name:    "VRNDSCALEPDMasked128",
+               auxType: auxInt8,
+               argLen:  2,
+               asm:     x86.AVRNDSCALEPD,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7
+                               {1, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7
                                {0, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
-                               {1, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
                        },
                        outputs: []outputInfo{
-                               {0, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7
+                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
                        },
                },
        },
        {
-               name:        "VPCMPUD128",
-               auxType:     auxInt8,
-               argLen:      2,
-               commutative: true,
-               asm:         x86.AVPCMPUD,
+               name:    "VREDUCEPDMasked128",
+               auxType: auxInt8,
+               argLen:  2,
+               asm:     x86.AVREDUCEPD,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
-                               {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {1, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7
+                               {0, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
                        },
                        outputs: []outputInfo{
-                               {0, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7
+                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
                        },
                },
        },
        {
-               name:        "VPCMPUDMasked128",
+               name:        "VCMPPDMasked128",
                auxType:     auxInt8,
                argLen:      3,
                commutative: true,
-               asm:         x86.AVPCMPUD,
+               asm:         x86.AVCMPPD,
                reg: regInfo{
                        inputs: []inputInfo{
                                {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7
@@ -28335,93 +30226,99 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:        "VPCMPUD256",
-               auxType:     auxInt8,
-               argLen:      2,
-               commutative: true,
-               asm:         x86.AVPCMPUD,
+               name:    "VROUNDPD256",
+               auxType: auxInt8,
+               argLen:  1,
+               asm:     x86.AVROUNDPD,
                reg: regInfo{
                        inputs: []inputInfo{
                                {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
-                               {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
                        },
                        outputs: []outputInfo{
-                               {0, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7
+                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
                        },
                },
        },
        {
-               name:        "VPCMPUDMasked256",
-               auxType:     auxInt8,
-               argLen:      3,
-               commutative: true,
-               asm:         x86.AVPCMPUD,
-               reg: regInfo{
+               name:    "VRNDSCALEPD256",
+               auxType: auxInt8,
+               argLen:  1,
+               asm:     x86.AVRNDSCALEPD,
+               reg: regInfo{
                        inputs: []inputInfo{
-                               {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7
-                               {0, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
-                               {1, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
                        },
                        outputs: []outputInfo{
-                               {0, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7
+                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
                        },
                },
        },
        {
-               name:        "VPCMPUQ128",
+               name:    "VREDUCEPD256",
+               auxType: auxInt8,
+               argLen:  1,
+               asm:     x86.AVREDUCEPD,
+               reg: regInfo{
+                       inputs: []inputInfo{
+                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                       },
+                       outputs: []outputInfo{
+                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                       },
+               },
+       },
+       {
+               name:        "VCMPPD256",
                auxType:     auxInt8,
                argLen:      2,
                commutative: true,
-               asm:         x86.AVPCMPUQ,
+               asm:         x86.AVCMPPD,
                reg: regInfo{
                        inputs: []inputInfo{
                                {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
                                {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
                        },
                        outputs: []outputInfo{
-                               {0, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7
+                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
                        },
                },
        },
        {
-               name:        "VPCMPUQMasked128",
-               auxType:     auxInt8,
-               argLen:      3,
-               commutative: true,
-               asm:         x86.AVPCMPUQ,
+               name:    "VRNDSCALEPDMasked256",
+               auxType: auxInt8,
+               argLen:  2,
+               asm:     x86.AVRNDSCALEPD,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7
+                               {1, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7
                                {0, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
-                               {1, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
                        },
                        outputs: []outputInfo{
-                               {0, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7
+                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
                        },
                },
        },
        {
-               name:        "VPCMPUQ256",
-               auxType:     auxInt8,
-               argLen:      2,
-               commutative: true,
-               asm:         x86.AVPCMPUQ,
+               name:    "VREDUCEPDMasked256",
+               auxType: auxInt8,
+               argLen:  2,
+               asm:     x86.AVREDUCEPD,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
-                               {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {1, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7
+                               {0, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
                        },
                        outputs: []outputInfo{
-                               {0, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7
+                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
                        },
                },
        },
        {
-               name:        "VPCMPUQMasked256",
+               name:        "VCMPPDMasked256",
                auxType:     auxInt8,
                argLen:      3,
                commutative: true,
-               asm:         x86.AVPCMPUQ,
+               asm:         x86.AVCMPPD,
                reg: regInfo{
                        inputs: []inputInfo{
                                {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7
@@ -28434,44 +30331,39 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:        "VPCMPUQ512",
-               auxType:     auxInt8,
-               argLen:      2,
-               commutative: true,
-               asm:         x86.AVPCMPUQ,
+               name:    "VRNDSCALEPD512",
+               auxType: auxInt8,
+               argLen:  1,
+               asm:     x86.AVRNDSCALEPD,
                reg: regInfo{
                        inputs: []inputInfo{
                                {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
-                               {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
                        },
                        outputs: []outputInfo{
-                               {0, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7
+                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
                        },
                },
        },
        {
-               name:        "VPCMPUQMasked512",
-               auxType:     auxInt8,
-               argLen:      3,
-               commutative: true,
-               asm:         x86.AVPCMPUQ,
+               name:    "VREDUCEPD512",
+               auxType: auxInt8,
+               argLen:  1,
+               asm:     x86.AVREDUCEPD,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7
-                               {0, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
-                               {1, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
                        },
                        outputs: []outputInfo{
-                               {0, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7
+                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
                        },
                },
        },
        {
-               name:        "VPCMPUB128",
+               name:        "VCMPPD512",
                auxType:     auxInt8,
                argLen:      2,
                commutative: true,
-               asm:         x86.AVPCMPUB,
+               asm:         x86.AVCMPPD,
                reg: regInfo{
                        inputs: []inputInfo{
                                {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
@@ -28483,44 +30375,41 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:        "VPCMPUBMasked128",
-               auxType:     auxInt8,
-               argLen:      3,
-               commutative: true,
-               asm:         x86.AVPCMPUB,
+               name:    "VRNDSCALEPDMasked512",
+               auxType: auxInt8,
+               argLen:  2,
+               asm:     x86.AVRNDSCALEPD,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7
+                               {1, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7
                                {0, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
-                               {1, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
                        },
                        outputs: []outputInfo{
-                               {0, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7
+                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
                        },
                },
        },
        {
-               name:        "VPCMPUB256",
-               auxType:     auxInt8,
-               argLen:      2,
-               commutative: true,
-               asm:         x86.AVPCMPUB,
+               name:    "VREDUCEPDMasked512",
+               auxType: auxInt8,
+               argLen:  2,
+               asm:     x86.AVREDUCEPD,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
-                               {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {1, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7
+                               {0, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
                        },
                        outputs: []outputInfo{
-                               {0, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7
+                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
                        },
                },
        },
        {
-               name:        "VPCMPUBMasked256",
+               name:        "VCMPPDMasked512",
                auxType:     auxInt8,
                argLen:      3,
                commutative: true,
-               asm:         x86.AVPCMPUB,
+               asm:         x86.AVCMPPD,
                reg: regInfo{
                        inputs: []inputInfo{
                                {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7
@@ -28533,11 +30422,10 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:        "VPCMPUB512",
-               auxType:     auxInt8,
-               argLen:      2,
-               commutative: true,
-               asm:         x86.AVPCMPUB,
+               name:    "VPCMPW256",
+               auxType: auxInt8,
+               argLen:  2,
+               asm:     x86.AVPCMPW,
                reg: regInfo{
                        inputs: []inputInfo{
                                {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
@@ -28549,11 +30437,11 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:        "VPCMPUBMasked512",
+               name:        "VPCMPWMasked256",
                auxType:     auxInt8,
                argLen:      3,
                commutative: true,
-               asm:         x86.AVPCMPUB,
+               asm:         x86.AVPCMPW,
                reg: regInfo{
                        inputs: []inputInfo{
                                {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7
@@ -28565,1720 +30453,1790 @@ var opcodeTable = [...]opInfo{
                        },
                },
        },
-
        {
-               name:        "ADD",
-               argLen:      2,
-               commutative: true,
-               asm:         arm.AADD,
+               name:    "VPSHLDWMasked256",
+               auxType: auxInt8,
+               argLen:  3,
+               asm:     x86.AVPSHLDW,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
-                               {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
+                               {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7
+                               {0, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {1, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
                        },
                        outputs: []outputInfo{
-                               {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
                        },
                },
        },
        {
-               name:    "ADDconst",
-               auxType: auxInt32,
-               argLen:  1,
-               asm:     arm.AADD,
+               name:    "VPSHRDWMasked256",
+               auxType: auxInt8,
+               argLen:  3,
+               asm:     x86.AVPSHRDW,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 30719}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14
+                               {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7
+                               {0, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {1, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
                        },
                        outputs: []outputInfo{
-                               {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
                        },
                },
        },
        {
-               name:   "SUB",
-               argLen: 2,
-               asm:    arm.ASUB,
+               name:    "VPSHLDW256",
+               auxType: auxInt8,
+               argLen:  2,
+               asm:     x86.AVPSHLDW,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
-                               {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
+                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
                        },
                        outputs: []outputInfo{
-                               {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
                        },
                },
        },
        {
-               name:    "SUBconst",
-               auxType: auxInt32,
-               argLen:  1,
-               asm:     arm.ASUB,
+               name:    "VPSHRDW256",
+               auxType: auxInt8,
+               argLen:  2,
+               asm:     x86.AVPSHRDW,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
+                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
                        },
                        outputs: []outputInfo{
-                               {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
                        },
                },
        },
        {
-               name:   "RSB",
-               argLen: 2,
-               asm:    arm.ARSB,
+               name:        "VPCMPW512",
+               auxType:     auxInt8,
+               argLen:      2,
+               commutative: true,
+               asm:         x86.AVPCMPW,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
-                               {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
+                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
                        },
                        outputs: []outputInfo{
-                               {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+                               {0, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7
                        },
                },
        },
        {
-               name:    "RSBconst",
-               auxType: auxInt32,
-               argLen:  1,
-               asm:     arm.ARSB,
+               name:        "VPCMPWMasked512",
+               auxType:     auxInt8,
+               argLen:      3,
+               commutative: true,
+               asm:         x86.AVPCMPW,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
+                               {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7
+                               {0, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {1, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
                        },
                        outputs: []outputInfo{
-                               {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+                               {0, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7
                        },
                },
        },
        {
-               name:        "MUL",
-               argLen:      2,
-               commutative: true,
-               asm:         arm.AMUL,
+               name:    "VPSHLDWMasked512",
+               auxType: auxInt8,
+               argLen:  3,
+               asm:     x86.AVPSHLDW,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
-                               {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
+                               {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7
+                               {0, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {1, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
                        },
                        outputs: []outputInfo{
-                               {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
                        },
                },
        },
        {
-               name:        "HMUL",
-               argLen:      2,
-               commutative: true,
-               asm:         arm.AMULL,
+               name:    "VPSHRDWMasked512",
+               auxType: auxInt8,
+               argLen:  3,
+               asm:     x86.AVPSHRDW,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
-                               {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
+                               {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7
+                               {0, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {1, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
                        },
                        outputs: []outputInfo{
-                               {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
                        },
                },
        },
        {
-               name:        "HMULU",
-               argLen:      2,
-               commutative: true,
-               asm:         arm.AMULLU,
+               name:    "VPSHLDW512",
+               auxType: auxInt8,
+               argLen:  2,
+               asm:     x86.AVPSHLDW,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
-                               {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
+                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
                        },
                        outputs: []outputInfo{
-                               {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
                        },
                },
        },
        {
-               name:         "CALLudiv",
-               argLen:       2,
-               clobberFlags: true,
+               name:    "VPSHRDW512",
+               auxType: auxInt8,
+               argLen:  2,
+               asm:     x86.AVPSHRDW,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 2}, // R1
-                               {1, 1}, // R0
+                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
                        },
-                       clobbers: 20492, // R2 R3 R12 R14
                        outputs: []outputInfo{
-                               {0, 1}, // R0
-                               {1, 2}, // R1
+                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
                        },
                },
        },
        {
-               name:        "ADDS",
-               argLen:      2,
-               commutative: true,
-               asm:         arm.AADD,
+               name:    "VPEXTRW128",
+               auxType: auxInt8,
+               argLen:  1,
+               asm:     x86.AVPEXTRW,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
-                               {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
+                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
                        },
                        outputs: []outputInfo{
-                               {1, 0},
-                               {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+                               {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
                        },
                },
        },
        {
-               name:    "ADDSconst",
-               auxType: auxInt32,
-               argLen:  1,
-               asm:     arm.AADD,
+               name:    "VPCMPW128",
+               auxType: auxInt8,
+               argLen:  2,
+               asm:     x86.AVPCMPW,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
+                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
                        },
                        outputs: []outputInfo{
-                               {1, 0},
-                               {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+                               {0, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7
                        },
                },
        },
        {
-               name:        "ADC",
+               name:        "VPCMPWMasked128",
+               auxType:     auxInt8,
                argLen:      3,
                commutative: true,
-               asm:         arm.AADC,
+               asm:         x86.AVPCMPW,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
-                               {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+                               {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7
+                               {0, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {1, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
                        },
                        outputs: []outputInfo{
-                               {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+                               {0, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7
                        },
                },
        },
        {
-               name:    "ADCconst",
-               auxType: auxInt32,
-               argLen:  2,
-               asm:     arm.AADC,
+               name:    "VPSHLDWMasked128",
+               auxType: auxInt8,
+               argLen:  3,
+               asm:     x86.AVPSHLDW,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+                               {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7
+                               {0, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {1, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
                        },
                        outputs: []outputInfo{
-                               {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
                        },
                },
        },
        {
-               name:   "SUBS",
-               argLen: 2,
-               asm:    arm.ASUB,
+               name:    "VPSHRDWMasked128",
+               auxType: auxInt8,
+               argLen:  3,
+               asm:     x86.AVPSHRDW,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
-                               {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
+                               {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7
+                               {0, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {1, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
                        },
                        outputs: []outputInfo{
-                               {1, 0},
-                               {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
                        },
                },
        },
        {
-               name:    "SUBSconst",
-               auxType: auxInt32,
-               argLen:  1,
-               asm:     arm.ASUB,
+               name:    "VPINSRW128",
+               auxType: auxInt8,
+               argLen:  2,
+               asm:     x86.AVPINSRW,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
+                               {1, 49135},      // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
+                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
                        },
                        outputs: []outputInfo{
-                               {1, 0},
-                               {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
                        },
                },
        },
        {
-               name:    "RSBSconst",
-               auxType: auxInt32,
-               argLen:  1,
-               asm:     arm.ARSB,
+               name:    "VPSHLDW128",
+               auxType: auxInt8,
+               argLen:  2,
+               asm:     x86.AVPSHLDW,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
+                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
                        },
                        outputs: []outputInfo{
-                               {1, 0},
-                               {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
                        },
                },
        },
        {
-               name:   "SBC",
-               argLen: 3,
-               asm:    arm.ASBC,
+               name:    "VPSHRDW128",
+               auxType: auxInt8,
+               argLen:  2,
+               asm:     x86.AVPSHRDW,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
-                               {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
                        },
                        outputs: []outputInfo{
-                               {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
                        },
                },
        },
        {
-               name:    "SBCconst",
-               auxType: auxInt32,
-               argLen:  2,
-               asm:     arm.ASBC,
+               name:        "VPCMPD512",
+               auxType:     auxInt8,
+               argLen:      2,
+               commutative: true,
+               asm:         x86.AVPCMPD,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
                        },
                        outputs: []outputInfo{
-                               {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+                               {0, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7
                        },
                },
        },
        {
-               name:    "RSCconst",
-               auxType: auxInt32,
-               argLen:  2,
-               asm:     arm.ARSC,
+               name:        "VPCMPDMasked512",
+               auxType:     auxInt8,
+               argLen:      3,
+               commutative: true,
+               asm:         x86.AVPCMPD,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+                               {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7
+                               {0, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {1, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
                        },
                        outputs: []outputInfo{
-                               {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+                               {0, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7
                        },
                },
        },
        {
-               name:        "MULLU",
-               argLen:      2,
-               commutative: true,
-               asm:         arm.AMULLU,
+               name:    "VPROLDMasked512",
+               auxType: auxInt8,
+               argLen:  2,
+               asm:     x86.AVPROLD,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
-                               {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
+                               {1, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7
+                               {0, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
                        },
                        outputs: []outputInfo{
-                               {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
-                               {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
                        },
                },
        },
        {
-               name:   "MULA",
-               argLen: 3,
-               asm:    arm.AMULA,
+               name:    "VPRORDMasked512",
+               auxType: auxInt8,
+               argLen:  2,
+               asm:     x86.AVPRORD,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
-                               {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
-                               {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+                               {1, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7
+                               {0, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
                        },
                        outputs: []outputInfo{
-                               {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
                        },
                },
        },
        {
-               name:   "MULS",
-               argLen: 3,
-               asm:    arm.AMULS,
+               name:    "VPSHLDDMasked512",
+               auxType: auxInt8,
+               argLen:  3,
+               asm:     x86.AVPSHLDD,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
-                               {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
-                               {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+                               {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7
+                               {0, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {1, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
                        },
                        outputs: []outputInfo{
-                               {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
                        },
                },
        },
        {
-               name:        "ADDF",
-               argLen:      2,
-               commutative: true,
-               asm:         arm.AADDF,
+               name:    "VPSHRDDMasked512",
+               auxType: auxInt8,
+               argLen:  3,
+               asm:     x86.AVPSHRDD,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
-                               {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+                               {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7
+                               {0, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {1, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
                        },
                        outputs: []outputInfo{
-                               {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
                        },
                },
        },
        {
-               name:        "ADDD",
-               argLen:      2,
-               commutative: true,
-               asm:         arm.AADDD,
+               name:    "VPROLD512",
+               auxType: auxInt8,
+               argLen:  1,
+               asm:     x86.AVPROLD,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
-                               {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
                        },
                        outputs: []outputInfo{
-                               {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
                        },
                },
        },
        {
-               name:   "SUBF",
-               argLen: 2,
-               asm:    arm.ASUBF,
+               name:    "VPRORD512",
+               auxType: auxInt8,
+               argLen:  1,
+               asm:     x86.AVPRORD,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
-                               {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
                        },
                        outputs: []outputInfo{
-                               {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
                        },
                },
        },
        {
-               name:   "SUBD",
-               argLen: 2,
-               asm:    arm.ASUBD,
+               name:    "VPSHLDD512",
+               auxType: auxInt8,
+               argLen:  2,
+               asm:     x86.AVPSHLDD,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
-                               {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
                        },
                        outputs: []outputInfo{
-                               {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
                        },
                },
        },
        {
-               name:        "MULF",
-               argLen:      2,
-               commutative: true,
-               asm:         arm.AMULF,
+               name:    "VPSHRDD512",
+               auxType: auxInt8,
+               argLen:  2,
+               asm:     x86.AVPSHRDD,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
-                               {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
                        },
                        outputs: []outputInfo{
-                               {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
                        },
                },
        },
        {
-               name:        "MULD",
-               argLen:      2,
-               commutative: true,
-               asm:         arm.AMULD,
+               name:    "VPEXTRD128",
+               auxType: auxInt8,
+               argLen:  1,
+               asm:     x86.AVPEXTRD,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
-                               {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
                        },
                        outputs: []outputInfo{
-                               {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+                               {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
                        },
                },
        },
        {
-               name:        "NMULF",
-               argLen:      2,
-               commutative: true,
-               asm:         arm.ANMULF,
+               name:    "VPCMPD128",
+               auxType: auxInt8,
+               argLen:  2,
+               asm:     x86.AVPCMPD,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
-                               {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
                        },
                        outputs: []outputInfo{
-                               {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+                               {0, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7
                        },
                },
        },
        {
-               name:        "NMULD",
-               argLen:      2,
+               name:        "VPCMPDMasked128",
+               auxType:     auxInt8,
+               argLen:      3,
                commutative: true,
-               asm:         arm.ANMULD,
+               asm:         x86.AVPCMPD,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
-                               {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+                               {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7
+                               {0, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {1, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
                        },
                        outputs: []outputInfo{
-                               {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+                               {0, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7
                        },
                },
        },
        {
-               name:   "DIVF",
-               argLen: 2,
-               asm:    arm.ADIVF,
+               name:    "VPROLDMasked128",
+               auxType: auxInt8,
+               argLen:  2,
+               asm:     x86.AVPROLD,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
-                               {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+                               {1, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7
+                               {0, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
                        },
                        outputs: []outputInfo{
-                               {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
                        },
                },
        },
        {
-               name:   "DIVD",
-               argLen: 2,
-               asm:    arm.ADIVD,
+               name:    "VPRORDMasked128",
+               auxType: auxInt8,
+               argLen:  2,
+               asm:     x86.AVPRORD,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
-                               {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+                               {1, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7
+                               {0, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
                        },
                        outputs: []outputInfo{
-                               {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
                        },
                },
        },
        {
-               name:         "MULAF",
-               argLen:       3,
-               resultInArg0: true,
-               asm:          arm.AMULAF,
+               name:    "VPSHLDDMasked128",
+               auxType: auxInt8,
+               argLen:  3,
+               asm:     x86.AVPSHLDD,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
-                               {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
-                               {2, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+                               {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7
+                               {0, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {1, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
                        },
                        outputs: []outputInfo{
-                               {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
                        },
                },
        },
        {
-               name:         "MULAD",
-               argLen:       3,
-               resultInArg0: true,
-               asm:          arm.AMULAD,
+               name:    "VPSHRDDMasked128",
+               auxType: auxInt8,
+               argLen:  3,
+               asm:     x86.AVPSHRDD,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
-                               {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
-                               {2, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+                               {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7
+                               {0, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {1, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
                        },
                        outputs: []outputInfo{
-                               {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
                        },
                },
        },
        {
-               name:         "MULSF",
-               argLen:       3,
-               resultInArg0: true,
-               asm:          arm.AMULSF,
+               name:    "VPROLD128",
+               auxType: auxInt8,
+               argLen:  1,
+               asm:     x86.AVPROLD,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
-                               {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
-                               {2, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
                        },
                        outputs: []outputInfo{
-                               {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
                        },
                },
        },
        {
-               name:         "MULSD",
-               argLen:       3,
-               resultInArg0: true,
-               asm:          arm.AMULSD,
+               name:    "VPRORD128",
+               auxType: auxInt8,
+               argLen:  1,
+               asm:     x86.AVPRORD,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
-                               {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
-                               {2, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
                        },
                        outputs: []outputInfo{
-                               {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
                        },
                },
        },
        {
-               name:         "FMULAD",
-               argLen:       3,
-               resultInArg0: true,
-               asm:          arm.AFMULAD,
+               name:    "VPINSRD128",
+               auxType: auxInt8,
+               argLen:  2,
+               asm:     x86.AVPINSRD,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
-                               {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
-                               {2, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+                               {1, 49135},      // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
+                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
                        },
                        outputs: []outputInfo{
-                               {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
                        },
                },
        },
        {
-               name:        "AND",
-               argLen:      2,
-               commutative: true,
-               asm:         arm.AAND,
+               name:    "VPSHLDD128",
+               auxType: auxInt8,
+               argLen:  2,
+               asm:     x86.AVPSHLDD,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
-                               {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
+                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
                        },
                        outputs: []outputInfo{
-                               {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
                        },
                },
        },
        {
-               name:    "ANDconst",
-               auxType: auxInt32,
-               argLen:  1,
-               asm:     arm.AAND,
+               name:    "VPSHRDD128",
+               auxType: auxInt8,
+               argLen:  2,
+               asm:     x86.AVPSHRDD,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
+                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
                        },
                        outputs: []outputInfo{
-                               {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
                        },
                },
        },
        {
-               name:        "OR",
-               argLen:      2,
-               commutative: true,
-               asm:         arm.AORR,
+               name:    "VPCMPD256",
+               auxType: auxInt8,
+               argLen:  2,
+               asm:     x86.AVPCMPD,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
-                               {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
+                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
                        },
                        outputs: []outputInfo{
-                               {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+                               {0, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7
                        },
                },
        },
        {
-               name:    "ORconst",
-               auxType: auxInt32,
-               argLen:  1,
-               asm:     arm.AORR,
+               name:        "VPCMPDMasked256",
+               auxType:     auxInt8,
+               argLen:      3,
+               commutative: true,
+               asm:         x86.AVPCMPD,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
+                               {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7
+                               {0, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {1, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
                        },
                        outputs: []outputInfo{
-                               {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+                               {0, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7
                        },
                },
        },
        {
-               name:        "XOR",
-               argLen:      2,
-               commutative: true,
-               asm:         arm.AEOR,
+               name:    "VPROLDMasked256",
+               auxType: auxInt8,
+               argLen:  2,
+               asm:     x86.AVPROLD,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
-                               {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
+                               {1, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7
+                               {0, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
                        },
                        outputs: []outputInfo{
-                               {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
                        },
                },
        },
        {
-               name:    "XORconst",
-               auxType: auxInt32,
-               argLen:  1,
-               asm:     arm.AEOR,
+               name:    "VPRORDMasked256",
+               auxType: auxInt8,
+               argLen:  2,
+               asm:     x86.AVPRORD,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
+                               {1, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7
+                               {0, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
                        },
                        outputs: []outputInfo{
-                               {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
                        },
                },
        },
        {
-               name:   "BIC",
-               argLen: 2,
-               asm:    arm.ABIC,
+               name:    "VPSHLDDMasked256",
+               auxType: auxInt8,
+               argLen:  3,
+               asm:     x86.AVPSHLDD,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
-                               {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
+                               {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7
+                               {0, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {1, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
                        },
                        outputs: []outputInfo{
-                               {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
                        },
                },
        },
        {
-               name:    "BICconst",
-               auxType: auxInt32,
-               argLen:  1,
-               asm:     arm.ABIC,
+               name:    "VPSHRDDMasked256",
+               auxType: auxInt8,
+               argLen:  3,
+               asm:     x86.AVPSHRDD,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
+                               {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7
+                               {0, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {1, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
                        },
                        outputs: []outputInfo{
-                               {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
                        },
                },
        },
        {
-               name:    "BFX",
-               auxType: auxInt32,
+               name:    "VPROLD256",
+               auxType: auxInt8,
                argLen:  1,
-               asm:     arm.ABFX,
+               asm:     x86.AVPROLD,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
+                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
                        },
                        outputs: []outputInfo{
-                               {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
                        },
                },
        },
        {
-               name:    "BFXU",
-               auxType: auxInt32,
+               name:    "VPRORD256",
+               auxType: auxInt8,
                argLen:  1,
-               asm:     arm.ABFXU,
+               asm:     x86.AVPRORD,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
+                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
                        },
                        outputs: []outputInfo{
-                               {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
                        },
                },
        },
        {
-               name:   "MVN",
-               argLen: 1,
-               asm:    arm.AMVN,
+               name:    "VPSHLDD256",
+               auxType: auxInt8,
+               argLen:  2,
+               asm:     x86.AVPSHLDD,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
+                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
                        },
                        outputs: []outputInfo{
-                               {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
                        },
                },
        },
        {
-               name:   "NEGF",
-               argLen: 1,
-               asm:    arm.ANEGF,
+               name:    "VPSHRDD256",
+               auxType: auxInt8,
+               argLen:  2,
+               asm:     x86.AVPSHRDD,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
                        },
                        outputs: []outputInfo{
-                               {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
                        },
                },
        },
        {
-               name:   "NEGD",
-               argLen: 1,
-               asm:    arm.ANEGD,
+               name:    "VPEXTRQ128",
+               auxType: auxInt8,
+               argLen:  1,
+               asm:     x86.AVPEXTRQ,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
                        },
                        outputs: []outputInfo{
-                               {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+                               {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
                        },
                },
        },
        {
-               name:   "SQRTD",
-               argLen: 1,
-               asm:    arm.ASQRTD,
+               name:    "VPCMPQ128",
+               auxType: auxInt8,
+               argLen:  2,
+               asm:     x86.AVPCMPQ,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
                        },
                        outputs: []outputInfo{
-                               {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+                               {0, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7
                        },
                },
        },
        {
-               name:   "SQRTF",
-               argLen: 1,
-               asm:    arm.ASQRTF,
+               name:        "VPCMPQMasked128",
+               auxType:     auxInt8,
+               argLen:      3,
+               commutative: true,
+               asm:         x86.AVPCMPQ,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+                               {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7
+                               {0, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {1, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
                        },
                        outputs: []outputInfo{
-                               {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+                               {0, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7
                        },
                },
        },
        {
-               name:   "ABSD",
-               argLen: 1,
-               asm:    arm.AABSD,
+               name:    "VPROLQMasked128",
+               auxType: auxInt8,
+               argLen:  2,
+               asm:     x86.AVPROLQ,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+                               {1, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7
+                               {0, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
                        },
                        outputs: []outputInfo{
-                               {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
                        },
                },
        },
        {
-               name:   "CLZ",
-               argLen: 1,
-               asm:    arm.ACLZ,
+               name:    "VPRORQMasked128",
+               auxType: auxInt8,
+               argLen:  2,
+               asm:     x86.AVPRORQ,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
+                               {1, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7
+                               {0, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
                        },
                        outputs: []outputInfo{
-                               {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
                        },
                },
        },
        {
-               name:   "REV",
-               argLen: 1,
-               asm:    arm.AREV,
+               name:    "VPSHLDQMasked128",
+               auxType: auxInt8,
+               argLen:  3,
+               asm:     x86.AVPSHLDQ,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
+                               {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7
+                               {0, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {1, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
                        },
                        outputs: []outputInfo{
-                               {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
                        },
                },
        },
        {
-               name:   "REV16",
-               argLen: 1,
-               asm:    arm.AREV16,
+               name:    "VPSHRDQMasked128",
+               auxType: auxInt8,
+               argLen:  3,
+               asm:     x86.AVPSHRDQ,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
+                               {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7
+                               {0, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {1, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
                        },
                        outputs: []outputInfo{
-                               {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
                        },
                },
        },
        {
-               name:   "RBIT",
-               argLen: 1,
-               asm:    arm.ARBIT,
+               name:    "VPROLQ128",
+               auxType: auxInt8,
+               argLen:  1,
+               asm:     x86.AVPROLQ,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
+                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
                        },
                        outputs: []outputInfo{
-                               {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
                        },
                },
        },
        {
-               name:   "SLL",
-               argLen: 2,
-               asm:    arm.ASLL,
+               name:    "VPRORQ128",
+               auxType: auxInt8,
+               argLen:  1,
+               asm:     x86.AVPRORQ,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
-                               {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
+                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
                        },
                        outputs: []outputInfo{
-                               {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
                        },
                },
        },
        {
-               name:    "SLLconst",
-               auxType: auxInt32,
-               argLen:  1,
-               asm:     arm.ASLL,
+               name:    "VPINSRQ128",
+               auxType: auxInt8,
+               argLen:  2,
+               asm:     x86.AVPINSRQ,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
+                               {1, 49135},      // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
+                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
                        },
                        outputs: []outputInfo{
-                               {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
                        },
                },
        },
        {
-               name:   "SRL",
-               argLen: 2,
-               asm:    arm.ASRL,
+               name:    "VPSHLDQ128",
+               auxType: auxInt8,
+               argLen:  2,
+               asm:     x86.AVPSHLDQ,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
-                               {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
+                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
                        },
                        outputs: []outputInfo{
-                               {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
                        },
                },
        },
        {
-               name:    "SRLconst",
-               auxType: auxInt32,
-               argLen:  1,
-               asm:     arm.ASRL,
+               name:    "VPSHRDQ128",
+               auxType: auxInt8,
+               argLen:  2,
+               asm:     x86.AVPSHRDQ,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
+                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
                        },
                        outputs: []outputInfo{
-                               {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
                        },
                },
        },
        {
-               name:   "SRA",
-               argLen: 2,
-               asm:    arm.ASRA,
+               name:    "VPCMPQ256",
+               auxType: auxInt8,
+               argLen:  2,
+               asm:     x86.AVPCMPQ,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
-                               {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
+                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
                        },
                        outputs: []outputInfo{
-                               {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+                               {0, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7
                        },
                },
        },
        {
-               name:    "SRAconst",
-               auxType: auxInt32,
-               argLen:  1,
-               asm:     arm.ASRA,
+               name:        "VPCMPQMasked256",
+               auxType:     auxInt8,
+               argLen:      3,
+               commutative: true,
+               asm:         x86.AVPCMPQ,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
+                               {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7
+                               {0, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {1, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
                        },
                        outputs: []outputInfo{
-                               {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+                               {0, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7
                        },
                },
        },
        {
-               name:   "SRR",
-               argLen: 2,
+               name:    "VPROLQMasked256",
+               auxType: auxInt8,
+               argLen:  2,
+               asm:     x86.AVPROLQ,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
-                               {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
+                               {1, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7
+                               {0, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
                        },
                        outputs: []outputInfo{
-                               {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
                        },
                },
        },
        {
-               name:    "SRRconst",
-               auxType: auxInt32,
-               argLen:  1,
+               name:    "VPRORQMasked256",
+               auxType: auxInt8,
+               argLen:  2,
+               asm:     x86.AVPRORQ,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
+                               {1, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7
+                               {0, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
                        },
                        outputs: []outputInfo{
-                               {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
                        },
                },
        },
        {
-               name:    "ADDshiftLL",
-               auxType: auxInt32,
-               argLen:  2,
-               asm:     arm.AADD,
+               name:    "VPSHLDQMasked256",
+               auxType: auxInt8,
+               argLen:  3,
+               asm:     x86.AVPSHLDQ,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
-                               {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
+                               {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7
+                               {0, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {1, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
                        },
                        outputs: []outputInfo{
-                               {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
                        },
                },
        },
        {
-               name:    "ADDshiftRL",
-               auxType: auxInt32,
-               argLen:  2,
-               asm:     arm.AADD,
+               name:    "VPSHRDQMasked256",
+               auxType: auxInt8,
+               argLen:  3,
+               asm:     x86.AVPSHRDQ,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
-                               {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
+                               {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7
+                               {0, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {1, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
                        },
                        outputs: []outputInfo{
-                               {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
                        },
                },
        },
        {
-               name:    "ADDshiftRA",
-               auxType: auxInt32,
-               argLen:  2,
-               asm:     arm.AADD,
+               name:    "VPROLQ256",
+               auxType: auxInt8,
+               argLen:  1,
+               asm:     x86.AVPROLQ,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
-                               {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
+                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
                        },
                        outputs: []outputInfo{
-                               {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
                        },
                },
        },
        {
-               name:    "SUBshiftLL",
-               auxType: auxInt32,
-               argLen:  2,
-               asm:     arm.ASUB,
+               name:    "VPRORQ256",
+               auxType: auxInt8,
+               argLen:  1,
+               asm:     x86.AVPRORQ,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
-                               {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
+                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
                        },
                        outputs: []outputInfo{
-                               {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
                        },
                },
        },
        {
-               name:    "SUBshiftRL",
-               auxType: auxInt32,
+               name:    "VPSHLDQ256",
+               auxType: auxInt8,
                argLen:  2,
-               asm:     arm.ASUB,
+               asm:     x86.AVPSHLDQ,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
-                               {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
+                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
                        },
                        outputs: []outputInfo{
-                               {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
                        },
                },
        },
        {
-               name:    "SUBshiftRA",
-               auxType: auxInt32,
+               name:    "VPSHRDQ256",
+               auxType: auxInt8,
                argLen:  2,
-               asm:     arm.ASUB,
+               asm:     x86.AVPSHRDQ,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
-                               {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
+                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
                        },
                        outputs: []outputInfo{
-                               {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
                        },
                },
        },
        {
-               name:    "RSBshiftLL",
-               auxType: auxInt32,
-               argLen:  2,
-               asm:     arm.ARSB,
+               name:        "VPCMPQ512",
+               auxType:     auxInt8,
+               argLen:      2,
+               commutative: true,
+               asm:         x86.AVPCMPQ,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
-                               {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
+                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
                        },
                        outputs: []outputInfo{
-                               {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+                               {0, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7
                        },
                },
        },
        {
-               name:    "RSBshiftRL",
-               auxType: auxInt32,
-               argLen:  2,
-               asm:     arm.ARSB,
+               name:        "VPCMPQMasked512",
+               auxType:     auxInt8,
+               argLen:      3,
+               commutative: true,
+               asm:         x86.AVPCMPQ,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
-                               {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
+                               {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7
+                               {0, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {1, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
                        },
                        outputs: []outputInfo{
-                               {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+                               {0, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7
                        },
                },
        },
        {
-               name:    "RSBshiftRA",
-               auxType: auxInt32,
+               name:    "VPROLQMasked512",
+               auxType: auxInt8,
                argLen:  2,
-               asm:     arm.ARSB,
+               asm:     x86.AVPROLQ,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
-                               {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
+                               {1, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7
+                               {0, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
                        },
                        outputs: []outputInfo{
-                               {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
                        },
                },
        },
        {
-               name:    "ANDshiftLL",
-               auxType: auxInt32,
+               name:    "VPRORQMasked512",
+               auxType: auxInt8,
                argLen:  2,
-               asm:     arm.AAND,
+               asm:     x86.AVPRORQ,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
-                               {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
+                               {1, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7
+                               {0, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
                        },
                        outputs: []outputInfo{
-                               {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
                        },
                },
        },
        {
-               name:    "ANDshiftRL",
-               auxType: auxInt32,
-               argLen:  2,
-               asm:     arm.AAND,
+               name:    "VPSHLDQMasked512",
+               auxType: auxInt8,
+               argLen:  3,
+               asm:     x86.AVPSHLDQ,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
-                               {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
+                               {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7
+                               {0, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {1, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
                        },
                        outputs: []outputInfo{
-                               {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
                        },
                },
        },
        {
-               name:    "ANDshiftRA",
-               auxType: auxInt32,
-               argLen:  2,
-               asm:     arm.AAND,
+               name:    "VPSHRDQMasked512",
+               auxType: auxInt8,
+               argLen:  3,
+               asm:     x86.AVPSHRDQ,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
-                               {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
+                               {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7
+                               {0, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {1, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
                        },
                        outputs: []outputInfo{
-                               {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
                        },
                },
        },
        {
-               name:    "ORshiftLL",
-               auxType: auxInt32,
-               argLen:  2,
-               asm:     arm.AORR,
+               name:    "VPROLQ512",
+               auxType: auxInt8,
+               argLen:  1,
+               asm:     x86.AVPROLQ,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
-                               {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
+                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
                        },
                        outputs: []outputInfo{
-                               {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
                        },
                },
        },
        {
-               name:    "ORshiftRL",
-               auxType: auxInt32,
-               argLen:  2,
-               asm:     arm.AORR,
+               name:    "VPRORQ512",
+               auxType: auxInt8,
+               argLen:  1,
+               asm:     x86.AVPRORQ,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
-                               {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
+                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
                        },
                        outputs: []outputInfo{
-                               {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
                        },
                },
        },
        {
-               name:    "ORshiftRA",
-               auxType: auxInt32,
+               name:    "VPSHLDQ512",
+               auxType: auxInt8,
                argLen:  2,
-               asm:     arm.AORR,
+               asm:     x86.AVPSHLDQ,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
-                               {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
+                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
                        },
                        outputs: []outputInfo{
-                               {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
                        },
                },
        },
        {
-               name:    "XORshiftLL",
-               auxType: auxInt32,
+               name:    "VPSHRDQ512",
+               auxType: auxInt8,
                argLen:  2,
-               asm:     arm.AEOR,
+               asm:     x86.AVPSHRDQ,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
-                               {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
+                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
                        },
                        outputs: []outputInfo{
-                               {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
                        },
                },
        },
        {
-               name:    "XORshiftRL",
-               auxType: auxInt32,
-               argLen:  2,
-               asm:     arm.AEOR,
+               name:    "VPEXTRB128",
+               auxType: auxInt8,
+               argLen:  1,
+               asm:     x86.AVPEXTRB,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
-                               {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
+                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
                        },
                        outputs: []outputInfo{
-                               {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+                               {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
                        },
                },
        },
        {
-               name:    "XORshiftRA",
-               auxType: auxInt32,
+               name:    "VPCMPB128",
+               auxType: auxInt8,
                argLen:  2,
-               asm:     arm.AEOR,
+               asm:     x86.AVPCMPB,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
-                               {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
+                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
                        },
                        outputs: []outputInfo{
-                               {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+                               {0, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7
                        },
                },
        },
        {
-               name:    "XORshiftRR",
-               auxType: auxInt32,
-               argLen:  2,
-               asm:     arm.AEOR,
+               name:        "VPCMPBMasked128",
+               auxType:     auxInt8,
+               argLen:      3,
+               commutative: true,
+               asm:         x86.AVPCMPB,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
-                               {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
+                               {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7
+                               {0, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {1, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
                        },
                        outputs: []outputInfo{
-                               {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+                               {0, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7
                        },
                },
        },
        {
-               name:    "BICshiftLL",
-               auxType: auxInt32,
+               name:    "VPINSRB128",
+               auxType: auxInt8,
                argLen:  2,
-               asm:     arm.ABIC,
+               asm:     x86.AVPINSRB,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
-                               {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
+                               {1, 49135},      // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
+                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
                        },
                        outputs: []outputInfo{
-                               {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
                        },
                },
        },
        {
-               name:    "BICshiftRL",
-               auxType: auxInt32,
+               name:    "VPCMPB256",
+               auxType: auxInt8,
                argLen:  2,
-               asm:     arm.ABIC,
+               asm:     x86.AVPCMPB,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
-                               {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
+                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
                        },
                        outputs: []outputInfo{
-                               {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+                               {0, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7
                        },
                },
        },
        {
-               name:    "BICshiftRA",
-               auxType: auxInt32,
-               argLen:  2,
-               asm:     arm.ABIC,
+               name:        "VPCMPBMasked256",
+               auxType:     auxInt8,
+               argLen:      3,
+               commutative: true,
+               asm:         x86.AVPCMPB,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
-                               {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
+                               {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7
+                               {0, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {1, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
                        },
                        outputs: []outputInfo{
-                               {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+                               {0, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7
                        },
                },
        },
        {
-               name:    "MVNshiftLL",
-               auxType: auxInt32,
-               argLen:  1,
-               asm:     arm.AMVN,
+               name:        "VPCMPB512",
+               auxType:     auxInt8,
+               argLen:      2,
+               commutative: true,
+               asm:         x86.AVPCMPB,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
+                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
                        },
                        outputs: []outputInfo{
-                               {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+                               {0, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7
                        },
                },
        },
        {
-               name:    "MVNshiftRL",
-               auxType: auxInt32,
-               argLen:  1,
-               asm:     arm.AMVN,
+               name:        "VPCMPBMasked512",
+               auxType:     auxInt8,
+               argLen:      3,
+               commutative: true,
+               asm:         x86.AVPCMPB,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
+                               {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7
+                               {0, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {1, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
                        },
                        outputs: []outputInfo{
-                               {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+                               {0, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7
                        },
                },
        },
        {
-               name:    "MVNshiftRA",
-               auxType: auxInt32,
-               argLen:  1,
-               asm:     arm.AMVN,
+               name:        "VPCMPUW256",
+               auxType:     auxInt8,
+               argLen:      2,
+               commutative: true,
+               asm:         x86.AVPCMPUW,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
+                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
                        },
                        outputs: []outputInfo{
-                               {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+                               {0, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7
                        },
                },
        },
        {
-               name:    "ADCshiftLL",
-               auxType: auxInt32,
-               argLen:  3,
-               asm:     arm.AADC,
+               name:        "VPCMPUWMasked256",
+               auxType:     auxInt8,
+               argLen:      3,
+               commutative: true,
+               asm:         x86.AVPCMPUW,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
-                               {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+                               {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7
+                               {0, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {1, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
                        },
                        outputs: []outputInfo{
-                               {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+                               {0, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7
                        },
                },
        },
        {
-               name:    "ADCshiftRL",
-               auxType: auxInt32,
-               argLen:  3,
-               asm:     arm.AADC,
+               name:        "VPCMPUW512",
+               auxType:     auxInt8,
+               argLen:      2,
+               commutative: true,
+               asm:         x86.AVPCMPUW,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
-                               {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
                        },
                        outputs: []outputInfo{
-                               {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+                               {0, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7
                        },
                },
        },
        {
-               name:    "ADCshiftRA",
-               auxType: auxInt32,
-               argLen:  3,
-               asm:     arm.AADC,
+               name:        "VPCMPUWMasked512",
+               auxType:     auxInt8,
+               argLen:      3,
+               commutative: true,
+               asm:         x86.AVPCMPUW,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
-                               {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+                               {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7
+                               {0, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {1, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
                        },
                        outputs: []outputInfo{
-                               {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+                               {0, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7
                        },
                },
        },
        {
-               name:    "SBCshiftLL",
-               auxType: auxInt32,
-               argLen:  3,
-               asm:     arm.ASBC,
+               name:        "VPCMPUW128",
+               auxType:     auxInt8,
+               argLen:      2,
+               commutative: true,
+               asm:         x86.AVPCMPUW,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
-                               {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
                        },
                        outputs: []outputInfo{
-                               {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+                               {0, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7
                        },
                },
        },
        {
-               name:    "SBCshiftRL",
-               auxType: auxInt32,
-               argLen:  3,
-               asm:     arm.ASBC,
+               name:        "VPCMPUWMasked128",
+               auxType:     auxInt8,
+               argLen:      3,
+               commutative: true,
+               asm:         x86.AVPCMPUW,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
-                               {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+                               {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7
+                               {0, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {1, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
                        },
                        outputs: []outputInfo{
-                               {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+                               {0, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7
                        },
                },
        },
        {
-               name:    "SBCshiftRA",
-               auxType: auxInt32,
-               argLen:  3,
-               asm:     arm.ASBC,
+               name:        "VPCMPUD512",
+               auxType:     auxInt8,
+               argLen:      2,
+               commutative: true,
+               asm:         x86.AVPCMPUD,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
-                               {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
                        },
                        outputs: []outputInfo{
-                               {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+                               {0, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7
                        },
                },
        },
        {
-               name:    "RSCshiftLL",
-               auxType: auxInt32,
-               argLen:  3,
-               asm:     arm.ARSC,
+               name:        "VPCMPUDMasked512",
+               auxType:     auxInt8,
+               argLen:      3,
+               commutative: true,
+               asm:         x86.AVPCMPUD,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
-                               {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+                               {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7
+                               {0, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {1, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
                        },
                        outputs: []outputInfo{
-                               {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+                               {0, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7
                        },
                },
        },
        {
-               name:    "RSCshiftRL",
-               auxType: auxInt32,
-               argLen:  3,
-               asm:     arm.ARSC,
+               name:        "VPCMPUD128",
+               auxType:     auxInt8,
+               argLen:      2,
+               commutative: true,
+               asm:         x86.AVPCMPUD,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
-                               {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
                        },
                        outputs: []outputInfo{
-                               {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+                               {0, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7
                        },
                },
        },
        {
-               name:    "RSCshiftRA",
-               auxType: auxInt32,
-               argLen:  3,
-               asm:     arm.ARSC,
+               name:        "VPCMPUDMasked128",
+               auxType:     auxInt8,
+               argLen:      3,
+               commutative: true,
+               asm:         x86.AVPCMPUD,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
-                               {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+                               {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7
+                               {0, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {1, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
                        },
                        outputs: []outputInfo{
-                               {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+                               {0, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7
                        },
                },
        },
        {
-               name:    "ADDSshiftLL",
-               auxType: auxInt32,
-               argLen:  2,
-               asm:     arm.AADD,
+               name:        "VPCMPUD256",
+               auxType:     auxInt8,
+               argLen:      2,
+               commutative: true,
+               asm:         x86.AVPCMPUD,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
-                               {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
+                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
                        },
                        outputs: []outputInfo{
-                               {1, 0},
-                               {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+                               {0, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7
                        },
                },
        },
        {
-               name:    "ADDSshiftRL",
-               auxType: auxInt32,
-               argLen:  2,
-               asm:     arm.AADD,
+               name:        "VPCMPUDMasked256",
+               auxType:     auxInt8,
+               argLen:      3,
+               commutative: true,
+               asm:         x86.AVPCMPUD,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
-                               {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
+                               {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7
+                               {0, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {1, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
                        },
                        outputs: []outputInfo{
-                               {1, 0},
-                               {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+                               {0, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7
                        },
                },
        },
        {
-               name:    "ADDSshiftRA",
-               auxType: auxInt32,
-               argLen:  2,
-               asm:     arm.AADD,
+               name:        "VPCMPUQ128",
+               auxType:     auxInt8,
+               argLen:      2,
+               commutative: true,
+               asm:         x86.AVPCMPUQ,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
-                               {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
+                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
                        },
                        outputs: []outputInfo{
-                               {1, 0},
-                               {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+                               {0, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7
                        },
                },
        },
        {
-               name:    "SUBSshiftLL",
-               auxType: auxInt32,
-               argLen:  2,
-               asm:     arm.ASUB,
+               name:        "VPCMPUQMasked128",
+               auxType:     auxInt8,
+               argLen:      3,
+               commutative: true,
+               asm:         x86.AVPCMPUQ,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
-                               {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
+                               {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7
+                               {0, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {1, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
                        },
                        outputs: []outputInfo{
-                               {1, 0},
-                               {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+                               {0, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7
                        },
                },
        },
        {
-               name:    "SUBSshiftRL",
-               auxType: auxInt32,
-               argLen:  2,
-               asm:     arm.ASUB,
+               name:        "VPCMPUQ256",
+               auxType:     auxInt8,
+               argLen:      2,
+               commutative: true,
+               asm:         x86.AVPCMPUQ,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
-                               {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
+                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
                        },
                        outputs: []outputInfo{
-                               {1, 0},
-                               {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+                               {0, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7
                        },
                },
        },
        {
-               name:    "SUBSshiftRA",
-               auxType: auxInt32,
-               argLen:  2,
-               asm:     arm.ASUB,
+               name:        "VPCMPUQMasked256",
+               auxType:     auxInt8,
+               argLen:      3,
+               commutative: true,
+               asm:         x86.AVPCMPUQ,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
-                               {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
+                               {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7
+                               {0, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {1, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
                        },
                        outputs: []outputInfo{
-                               {1, 0},
-                               {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+                               {0, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7
                        },
                },
        },
        {
-               name:    "RSBSshiftLL",
-               auxType: auxInt32,
-               argLen:  2,
-               asm:     arm.ARSB,
+               name:        "VPCMPUQ512",
+               auxType:     auxInt8,
+               argLen:      2,
+               commutative: true,
+               asm:         x86.AVPCMPUQ,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
-                               {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
+                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
                        },
                        outputs: []outputInfo{
-                               {1, 0},
-                               {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+                               {0, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7
                        },
                },
        },
        {
-               name:    "RSBSshiftRL",
-               auxType: auxInt32,
-               argLen:  2,
-               asm:     arm.ARSB,
+               name:        "VPCMPUQMasked512",
+               auxType:     auxInt8,
+               argLen:      3,
+               commutative: true,
+               asm:         x86.AVPCMPUQ,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
-                               {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
+                               {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7
+                               {0, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {1, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
                        },
                        outputs: []outputInfo{
-                               {1, 0},
-                               {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+                               {0, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7
                        },
                },
        },
        {
-               name:    "RSBSshiftRA",
-               auxType: auxInt32,
-               argLen:  2,
-               asm:     arm.ARSB,
+               name:        "VPCMPUB128",
+               auxType:     auxInt8,
+               argLen:      2,
+               commutative: true,
+               asm:         x86.AVPCMPUB,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
-                               {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
-                       },
-                       outputs: []outputInfo{
-                               {1, 0},
-                               {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
-                       },
-               },
-       },
-       {
-               name:   "ADDshiftLLreg",
-               argLen: 3,
-               asm:    arm.AADD,
-               reg: regInfo{
-                       inputs: []inputInfo{
-                               {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
-                               {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
-                               {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
-                       },
-                       outputs: []outputInfo{
-                               {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
-                       },
-               },
-       },
-       {
-               name:   "ADDshiftRLreg",
-               argLen: 3,
-               asm:    arm.AADD,
-               reg: regInfo{
-                       inputs: []inputInfo{
-                               {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
-                               {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
-                               {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
                        },
                        outputs: []outputInfo{
-                               {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+                               {0, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7
                        },
                },
        },
        {
-               name:   "ADDshiftRAreg",
-               argLen: 3,
-               asm:    arm.AADD,
+               name:        "VPCMPUBMasked128",
+               auxType:     auxInt8,
+               argLen:      3,
+               commutative: true,
+               asm:         x86.AVPCMPUB,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
-                               {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
-                               {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+                               {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7
+                               {0, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {1, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
                        },
                        outputs: []outputInfo{
-                               {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+                               {0, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7
                        },
                },
        },
        {
-               name:   "SUBshiftLLreg",
-               argLen: 3,
-               asm:    arm.ASUB,
+               name:        "VPCMPUB256",
+               auxType:     auxInt8,
+               argLen:      2,
+               commutative: true,
+               asm:         x86.AVPCMPUB,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
-                               {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
-                               {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
                        },
                        outputs: []outputInfo{
-                               {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+                               {0, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7
                        },
                },
        },
        {
-               name:   "SUBshiftRLreg",
-               argLen: 3,
-               asm:    arm.ASUB,
+               name:        "VPCMPUBMasked256",
+               auxType:     auxInt8,
+               argLen:      3,
+               commutative: true,
+               asm:         x86.AVPCMPUB,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
-                               {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
-                               {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+                               {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7
+                               {0, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {1, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
                        },
                        outputs: []outputInfo{
-                               {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+                               {0, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7
                        },
                },
        },
        {
-               name:   "SUBshiftRAreg",
-               argLen: 3,
-               asm:    arm.ASUB,
+               name:        "VPCMPUB512",
+               auxType:     auxInt8,
+               argLen:      2,
+               commutative: true,
+               asm:         x86.AVPCMPUB,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
-                               {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
-                               {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
                        },
                        outputs: []outputInfo{
-                               {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+                               {0, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7
                        },
                },
        },
        {
-               name:   "RSBshiftLLreg",
-               argLen: 3,
-               asm:    arm.ARSB,
+               name:        "VPCMPUBMasked512",
+               auxType:     auxInt8,
+               argLen:      3,
+               commutative: true,
+               asm:         x86.AVPCMPUB,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
-                               {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
-                               {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+                               {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7
+                               {0, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {1, 2147418112},    // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
                        },
                        outputs: []outputInfo{
-                               {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+                               {0, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7
                        },
                },
        },
+
        {
-               name:   "RSBshiftRLreg",
-               argLen: 3,
-               asm:    arm.ARSB,
+               name:        "ADD",
+               argLen:      2,
+               commutative: true,
+               asm:         arm.AADD,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
-                               {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
-                               {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+                               {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
+                               {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
                        },
                        outputs: []outputInfo{
                                {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
@@ -30286,14 +32244,13 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:   "RSBshiftRAreg",
-               argLen: 3,
-               asm:    arm.ARSB,
+               name:    "ADDconst",
+               auxType: auxInt32,
+               argLen:  1,
+               asm:     arm.AADD,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
-                               {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
-                               {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+                               {0, 30719}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14
                        },
                        outputs: []outputInfo{
                                {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
@@ -30301,14 +32258,13 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:   "ANDshiftLLreg",
-               argLen: 3,
-               asm:    arm.AAND,
+               name:   "SUB",
+               argLen: 2,
+               asm:    arm.ASUB,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
-                               {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
-                               {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+                               {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
+                               {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
                        },
                        outputs: []outputInfo{
                                {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
@@ -30316,14 +32272,13 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:   "ANDshiftRLreg",
-               argLen: 3,
-               asm:    arm.AAND,
+               name:    "SUBconst",
+               auxType: auxInt32,
+               argLen:  1,
+               asm:     arm.ASUB,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
-                               {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
-                               {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+                               {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
                        },
                        outputs: []outputInfo{
                                {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
@@ -30331,14 +32286,13 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:   "ANDshiftRAreg",
-               argLen: 3,
-               asm:    arm.AAND,
+               name:   "RSB",
+               argLen: 2,
+               asm:    arm.ARSB,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
-                               {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
-                               {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+                               {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
+                               {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
                        },
                        outputs: []outputInfo{
                                {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
@@ -30346,14 +32300,13 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:   "ORshiftLLreg",
-               argLen: 3,
-               asm:    arm.AORR,
+               name:    "RSBconst",
+               auxType: auxInt32,
+               argLen:  1,
+               asm:     arm.ARSB,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
-                               {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
-                               {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+                               {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
                        },
                        outputs: []outputInfo{
                                {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
@@ -30361,14 +32314,14 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:   "ORshiftRLreg",
-               argLen: 3,
-               asm:    arm.AORR,
+               name:        "MUL",
+               argLen:      2,
+               commutative: true,
+               asm:         arm.AMUL,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
-                               {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
-                               {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+                               {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
+                               {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
                        },
                        outputs: []outputInfo{
                                {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
@@ -30376,14 +32329,14 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:   "ORshiftRAreg",
-               argLen: 3,
-               asm:    arm.AORR,
+               name:        "HMUL",
+               argLen:      2,
+               commutative: true,
+               asm:         arm.AMULL,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
-                               {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
-                               {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+                               {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
+                               {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
                        },
                        outputs: []outputInfo{
                                {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
@@ -30391,14 +32344,14 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:   "XORshiftLLreg",
-               argLen: 3,
-               asm:    arm.AEOR,
+               name:        "HMULU",
+               argLen:      2,
+               commutative: true,
+               asm:         arm.AMULLU,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
-                               {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
-                               {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+                               {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
+                               {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
                        },
                        outputs: []outputInfo{
                                {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
@@ -30406,59 +32359,61 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:   "XORshiftRLreg",
-               argLen: 3,
-               asm:    arm.AEOR,
+               name:         "CALLudiv",
+               argLen:       2,
+               clobberFlags: true,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
-                               {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
-                               {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+                               {0, 2}, // R1
+                               {1, 1}, // R0
                        },
+                       clobbers: 20492, // R2 R3 R12 R14
                        outputs: []outputInfo{
-                               {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+                               {0, 1}, // R0
+                               {1, 2}, // R1
                        },
                },
        },
        {
-               name:   "XORshiftRAreg",
-               argLen: 3,
-               asm:    arm.AEOR,
+               name:        "ADDS",
+               argLen:      2,
+               commutative: true,
+               asm:         arm.AADD,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
-                               {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
-                               {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+                               {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
+                               {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
                        },
                        outputs: []outputInfo{
+                               {1, 0},
                                {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
                        },
                },
        },
        {
-               name:   "BICshiftLLreg",
-               argLen: 3,
-               asm:    arm.ABIC,
+               name:    "ADDSconst",
+               auxType: auxInt32,
+               argLen:  1,
+               asm:     arm.AADD,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
-                               {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
-                               {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+                               {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
                        },
                        outputs: []outputInfo{
+                               {1, 0},
                                {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
                        },
                },
        },
        {
-               name:   "BICshiftRLreg",
-               argLen: 3,
-               asm:    arm.ABIC,
+               name:        "ADC",
+               argLen:      3,
+               commutative: true,
+               asm:         arm.AADC,
                reg: regInfo{
                        inputs: []inputInfo{
                                {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
                                {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
-                               {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
                        },
                        outputs: []outputInfo{
                                {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
@@ -30466,14 +32421,13 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:   "BICshiftRAreg",
-               argLen: 3,
-               asm:    arm.ABIC,
+               name:    "ADCconst",
+               auxType: auxInt32,
+               argLen:  2,
+               asm:     arm.AADC,
                reg: regInfo{
                        inputs: []inputInfo{
                                {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
-                               {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
-                               {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
                        },
                        outputs: []outputInfo{
                                {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
@@ -30481,56 +32435,58 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:   "MVNshiftLLreg",
+               name:   "SUBS",
                argLen: 2,
-               asm:    arm.AMVN,
+               asm:    arm.ASUB,
                reg: regInfo{
                        inputs: []inputInfo{
                                {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
                                {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
                        },
                        outputs: []outputInfo{
+                               {1, 0},
                                {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
                        },
                },
        },
        {
-               name:   "MVNshiftRLreg",
-               argLen: 2,
-               asm:    arm.AMVN,
+               name:    "SUBSconst",
+               auxType: auxInt32,
+               argLen:  1,
+               asm:     arm.ASUB,
                reg: regInfo{
                        inputs: []inputInfo{
                                {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
-                               {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
                        },
                        outputs: []outputInfo{
+                               {1, 0},
                                {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
                        },
                },
        },
        {
-               name:   "MVNshiftRAreg",
-               argLen: 2,
-               asm:    arm.AMVN,
+               name:    "RSBSconst",
+               auxType: auxInt32,
+               argLen:  1,
+               asm:     arm.ARSB,
                reg: regInfo{
                        inputs: []inputInfo{
                                {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
-                               {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
                        },
                        outputs: []outputInfo{
+                               {1, 0},
                                {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
                        },
                },
        },
        {
-               name:   "ADCshiftLLreg",
-               argLen: 4,
-               asm:    arm.AADC,
+               name:   "SBC",
+               argLen: 3,
+               asm:    arm.ASBC,
                reg: regInfo{
                        inputs: []inputInfo{
                                {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
                                {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
-                               {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
                        },
                        outputs: []outputInfo{
                                {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
@@ -30538,14 +32494,13 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:   "ADCshiftRLreg",
-               argLen: 4,
-               asm:    arm.AADC,
+               name:    "SBCconst",
+               auxType: auxInt32,
+               argLen:  2,
+               asm:     arm.ASBC,
                reg: regInfo{
                        inputs: []inputInfo{
                                {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
-                               {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
-                               {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
                        },
                        outputs: []outputInfo{
                                {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
@@ -30553,14 +32508,13 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:   "ADCshiftRAreg",
-               argLen: 4,
-               asm:    arm.AADC,
+               name:    "RSCconst",
+               auxType: auxInt32,
+               argLen:  2,
+               asm:     arm.ARSC,
                reg: regInfo{
                        inputs: []inputInfo{
                                {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
-                               {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
-                               {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
                        },
                        outputs: []outputInfo{
                                {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
@@ -30568,24 +32522,25 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:   "SBCshiftLLreg",
-               argLen: 4,
-               asm:    arm.ASBC,
+               name:        "MULLU",
+               argLen:      2,
+               commutative: true,
+               asm:         arm.AMULLU,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
-                               {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
-                               {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+                               {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
+                               {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
                        },
                        outputs: []outputInfo{
                                {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+                               {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
                        },
                },
        },
        {
-               name:   "SBCshiftRLreg",
-               argLen: 4,
-               asm:    arm.ASBC,
+               name:   "MULA",
+               argLen: 3,
+               asm:    arm.AMULA,
                reg: regInfo{
                        inputs: []inputInfo{
                                {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
@@ -30598,9 +32553,9 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:   "SBCshiftRAreg",
-               argLen: 4,
-               asm:    arm.ASBC,
+               name:   "MULS",
+               argLen: 3,
+               asm:    arm.AMULS,
                reg: regInfo{
                        inputs: []inputInfo{
                                {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
@@ -30613,661 +32568,713 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:   "RSCshiftLLreg",
-               argLen: 4,
-               asm:    arm.ARSC,
+               name:        "ADDF",
+               argLen:      2,
+               commutative: true,
+               asm:         arm.AADDF,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
-                               {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
-                               {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+                               {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+                               {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
                        },
                        outputs: []outputInfo{
-                               {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+                               {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
                        },
                },
        },
        {
-               name:   "RSCshiftRLreg",
-               argLen: 4,
-               asm:    arm.ARSC,
+               name:        "ADDD",
+               argLen:      2,
+               commutative: true,
+               asm:         arm.AADDD,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
-                               {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
-                               {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+                               {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+                               {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
                        },
                        outputs: []outputInfo{
-                               {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+                               {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
                        },
                },
        },
        {
-               name:   "RSCshiftRAreg",
-               argLen: 4,
-               asm:    arm.ARSC,
+               name:   "SUBF",
+               argLen: 2,
+               asm:    arm.ASUBF,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
-                               {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
-                               {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+                               {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+                               {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
                        },
                        outputs: []outputInfo{
-                               {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+                               {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
                        },
                },
        },
        {
-               name:   "ADDSshiftLLreg",
-               argLen: 3,
-               asm:    arm.AADD,
+               name:   "SUBD",
+               argLen: 2,
+               asm:    arm.ASUBD,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
-                               {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
-                               {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+                               {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+                               {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
                        },
                        outputs: []outputInfo{
-                               {1, 0},
-                               {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+                               {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
                        },
                },
        },
        {
-               name:   "ADDSshiftRLreg",
-               argLen: 3,
-               asm:    arm.AADD,
+               name:        "MULF",
+               argLen:      2,
+               commutative: true,
+               asm:         arm.AMULF,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
-                               {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
-                               {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+                               {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+                               {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
                        },
                        outputs: []outputInfo{
-                               {1, 0},
-                               {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+                               {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
                        },
                },
        },
        {
-               name:   "ADDSshiftRAreg",
-               argLen: 3,
-               asm:    arm.AADD,
+               name:        "MULD",
+               argLen:      2,
+               commutative: true,
+               asm:         arm.AMULD,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
-                               {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
-                               {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+                               {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+                               {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
                        },
                        outputs: []outputInfo{
-                               {1, 0},
-                               {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+                               {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
                        },
                },
        },
        {
-               name:   "SUBSshiftLLreg",
-               argLen: 3,
-               asm:    arm.ASUB,
+               name:        "NMULF",
+               argLen:      2,
+               commutative: true,
+               asm:         arm.ANMULF,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
-                               {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
-                               {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+                               {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+                               {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
                        },
                        outputs: []outputInfo{
-                               {1, 0},
-                               {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+                               {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
                        },
                },
        },
        {
-               name:   "SUBSshiftRLreg",
-               argLen: 3,
-               asm:    arm.ASUB,
+               name:        "NMULD",
+               argLen:      2,
+               commutative: true,
+               asm:         arm.ANMULD,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
-                               {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
-                               {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+                               {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+                               {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
                        },
                        outputs: []outputInfo{
-                               {1, 0},
-                               {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+                               {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
                        },
                },
        },
        {
-               name:   "SUBSshiftRAreg",
-               argLen: 3,
-               asm:    arm.ASUB,
+               name:   "DIVF",
+               argLen: 2,
+               asm:    arm.ADIVF,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
-                               {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
-                               {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+                               {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+                               {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
                        },
                        outputs: []outputInfo{
-                               {1, 0},
-                               {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+                               {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
                        },
                },
        },
        {
-               name:   "RSBSshiftLLreg",
-               argLen: 3,
-               asm:    arm.ARSB,
+               name:   "DIVD",
+               argLen: 2,
+               asm:    arm.ADIVD,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
-                               {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
-                               {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+                               {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+                               {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
                        },
                        outputs: []outputInfo{
-                               {1, 0},
-                               {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+                               {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
                        },
                },
        },
        {
-               name:   "RSBSshiftRLreg",
-               argLen: 3,
-               asm:    arm.ARSB,
+               name:         "MULAF",
+               argLen:       3,
+               resultInArg0: true,
+               asm:          arm.AMULAF,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
-                               {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
-                               {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+                               {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+                               {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+                               {2, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
                        },
                        outputs: []outputInfo{
-                               {1, 0},
-                               {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+                               {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
                        },
                },
        },
        {
-               name:   "RSBSshiftRAreg",
-               argLen: 3,
-               asm:    arm.ARSB,
+               name:         "MULAD",
+               argLen:       3,
+               resultInArg0: true,
+               asm:          arm.AMULAD,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
-                               {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
-                               {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+                               {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+                               {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+                               {2, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
                        },
                        outputs: []outputInfo{
-                               {1, 0},
-                               {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+                               {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
                        },
                },
        },
        {
-               name:   "CMP",
-               argLen: 2,
-               asm:    arm.ACMP,
+               name:         "MULSF",
+               argLen:       3,
+               resultInArg0: true,
+               asm:          arm.AMULSF,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
-                               {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
+                               {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+                               {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+                               {2, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+                       },
+                       outputs: []outputInfo{
+                               {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
                        },
                },
        },
        {
-               name:    "CMPconst",
-               auxType: auxInt32,
-               argLen:  1,
-               asm:     arm.ACMP,
+               name:         "MULSD",
+               argLen:       3,
+               resultInArg0: true,
+               asm:          arm.AMULSD,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
+                               {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+                               {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+                               {2, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+                       },
+                       outputs: []outputInfo{
+                               {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
                        },
                },
        },
        {
-               name:        "CMN",
+               name:         "FMULAD",
+               argLen:       3,
+               resultInArg0: true,
+               asm:          arm.AFMULAD,
+               reg: regInfo{
+                       inputs: []inputInfo{
+                               {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+                               {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+                               {2, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+                       },
+                       outputs: []outputInfo{
+                               {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+                       },
+               },
+       },
+       {
+               name:        "AND",
                argLen:      2,
                commutative: true,
-               asm:         arm.ACMN,
+               asm:         arm.AAND,
                reg: regInfo{
                        inputs: []inputInfo{
                                {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
                                {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
                        },
+                       outputs: []outputInfo{
+                               {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+                       },
                },
        },
        {
-               name:    "CMNconst",
+               name:    "ANDconst",
                auxType: auxInt32,
                argLen:  1,
-               asm:     arm.ACMN,
+               asm:     arm.AAND,
                reg: regInfo{
                        inputs: []inputInfo{
                                {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
                        },
+                       outputs: []outputInfo{
+                               {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+                       },
                },
        },
        {
-               name:        "TST",
+               name:        "OR",
                argLen:      2,
                commutative: true,
-               asm:         arm.ATST,
+               asm:         arm.AORR,
                reg: regInfo{
                        inputs: []inputInfo{
                                {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
                                {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
                        },
+                       outputs: []outputInfo{
+                               {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+                       },
                },
        },
        {
-               name:    "TSTconst",
+               name:    "ORconst",
                auxType: auxInt32,
                argLen:  1,
-               asm:     arm.ATST,
+               asm:     arm.AORR,
                reg: regInfo{
                        inputs: []inputInfo{
                                {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
                        },
+                       outputs: []outputInfo{
+                               {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+                       },
                },
        },
        {
-               name:        "TEQ",
+               name:        "XOR",
                argLen:      2,
                commutative: true,
-               asm:         arm.ATEQ,
+               asm:         arm.AEOR,
                reg: regInfo{
                        inputs: []inputInfo{
                                {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
                                {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
                        },
+                       outputs: []outputInfo{
+                               {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+                       },
                },
        },
        {
-               name:    "TEQconst",
+               name:    "XORconst",
                auxType: auxInt32,
                argLen:  1,
-               asm:     arm.ATEQ,
+               asm:     arm.AEOR,
                reg: regInfo{
                        inputs: []inputInfo{
                                {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
                        },
-               },
-       },
-       {
-               name:   "CMPF",
-               argLen: 2,
-               asm:    arm.ACMPF,
-               reg: regInfo{
-                       inputs: []inputInfo{
-                               {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
-                               {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+                       outputs: []outputInfo{
+                               {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
                        },
                },
        },
        {
-               name:   "CMPD",
+               name:   "BIC",
                argLen: 2,
-               asm:    arm.ACMPD,
-               reg: regInfo{
-                       inputs: []inputInfo{
-                               {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
-                               {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
-                       },
-               },
-       },
-       {
-               name:    "CMPshiftLL",
-               auxType: auxInt32,
-               argLen:  2,
-               asm:     arm.ACMP,
+               asm:    arm.ABIC,
                reg: regInfo{
                        inputs: []inputInfo{
                                {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
                                {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
                        },
+                       outputs: []outputInfo{
+                               {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+                       },
                },
        },
        {
-               name:    "CMPshiftRL",
+               name:    "BICconst",
                auxType: auxInt32,
-               argLen:  2,
-               asm:     arm.ACMP,
+               argLen:  1,
+               asm:     arm.ABIC,
                reg: regInfo{
                        inputs: []inputInfo{
                                {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
-                               {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
+                       },
+                       outputs: []outputInfo{
+                               {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
                        },
                },
        },
        {
-               name:    "CMPshiftRA",
+               name:    "BFX",
                auxType: auxInt32,
-               argLen:  2,
-               asm:     arm.ACMP,
+               argLen:  1,
+               asm:     arm.ABFX,
                reg: regInfo{
                        inputs: []inputInfo{
                                {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
-                               {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
+                       },
+                       outputs: []outputInfo{
+                               {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
                        },
                },
        },
        {
-               name:    "CMNshiftLL",
+               name:    "BFXU",
                auxType: auxInt32,
-               argLen:  2,
-               asm:     arm.ACMN,
+               argLen:  1,
+               asm:     arm.ABFXU,
                reg: regInfo{
                        inputs: []inputInfo{
                                {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
-                               {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
+                       },
+                       outputs: []outputInfo{
+                               {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
                        },
                },
        },
        {
-               name:    "CMNshiftRL",
-               auxType: auxInt32,
-               argLen:  2,
-               asm:     arm.ACMN,
+               name:   "MVN",
+               argLen: 1,
+               asm:    arm.AMVN,
                reg: regInfo{
                        inputs: []inputInfo{
                                {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
-                               {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
+                       },
+                       outputs: []outputInfo{
+                               {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
                        },
                },
        },
        {
-               name:    "CMNshiftRA",
-               auxType: auxInt32,
-               argLen:  2,
-               asm:     arm.ACMN,
+               name:   "NEGF",
+               argLen: 1,
+               asm:    arm.ANEGF,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
-                               {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
+                               {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+                       },
+                       outputs: []outputInfo{
+                               {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
                        },
                },
        },
        {
-               name:    "TSTshiftLL",
-               auxType: auxInt32,
-               argLen:  2,
-               asm:     arm.ATST,
+               name:   "NEGD",
+               argLen: 1,
+               asm:    arm.ANEGD,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
-                               {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
+                               {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+                       },
+                       outputs: []outputInfo{
+                               {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
                        },
                },
        },
        {
-               name:    "TSTshiftRL",
-               auxType: auxInt32,
-               argLen:  2,
-               asm:     arm.ATST,
+               name:   "SQRTD",
+               argLen: 1,
+               asm:    arm.ASQRTD,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
-                               {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
+                               {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+                       },
+                       outputs: []outputInfo{
+                               {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
                        },
                },
        },
        {
-               name:    "TSTshiftRA",
-               auxType: auxInt32,
-               argLen:  2,
-               asm:     arm.ATST,
+               name:   "SQRTF",
+               argLen: 1,
+               asm:    arm.ASQRTF,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
-                               {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
+                               {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+                       },
+                       outputs: []outputInfo{
+                               {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
                        },
                },
        },
        {
-               name:    "TEQshiftLL",
-               auxType: auxInt32,
-               argLen:  2,
-               asm:     arm.ATEQ,
+               name:   "ABSD",
+               argLen: 1,
+               asm:    arm.AABSD,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
-                               {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
+                               {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+                       },
+                       outputs: []outputInfo{
+                               {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
                        },
                },
        },
        {
-               name:    "TEQshiftRL",
-               auxType: auxInt32,
-               argLen:  2,
-               asm:     arm.ATEQ,
+               name:   "CLZ",
+               argLen: 1,
+               asm:    arm.ACLZ,
                reg: regInfo{
                        inputs: []inputInfo{
                                {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
-                               {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
+                       },
+                       outputs: []outputInfo{
+                               {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
                        },
                },
        },
        {
-               name:    "TEQshiftRA",
-               auxType: auxInt32,
-               argLen:  2,
-               asm:     arm.ATEQ,
+               name:   "REV",
+               argLen: 1,
+               asm:    arm.AREV,
                reg: regInfo{
                        inputs: []inputInfo{
                                {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
-                               {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
+                       },
+                       outputs: []outputInfo{
+                               {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
                        },
                },
        },
        {
-               name:   "CMPshiftLLreg",
-               argLen: 3,
-               asm:    arm.ACMP,
+               name:   "REV16",
+               argLen: 1,
+               asm:    arm.AREV16,
                reg: regInfo{
                        inputs: []inputInfo{
+                               {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
+                       },
+                       outputs: []outputInfo{
                                {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
-                               {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
-                               {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
                        },
                },
        },
        {
-               name:   "CMPshiftRLreg",
-               argLen: 3,
-               asm:    arm.ACMP,
+               name:   "RBIT",
+               argLen: 1,
+               asm:    arm.ARBIT,
                reg: regInfo{
                        inputs: []inputInfo{
+                               {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
+                       },
+                       outputs: []outputInfo{
                                {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
-                               {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
-                               {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
                        },
                },
        },
        {
-               name:   "CMPshiftRAreg",
-               argLen: 3,
-               asm:    arm.ACMP,
+               name:   "SLL",
+               argLen: 2,
+               asm:    arm.ASLL,
                reg: regInfo{
                        inputs: []inputInfo{
+                               {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
+                               {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
+                       },
+                       outputs: []outputInfo{
                                {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
-                               {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
-                               {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
                        },
                },
        },
        {
-               name:   "CMNshiftLLreg",
-               argLen: 3,
-               asm:    arm.ACMN,
+               name:    "SLLconst",
+               auxType: auxInt32,
+               argLen:  1,
+               asm:     arm.ASLL,
                reg: regInfo{
                        inputs: []inputInfo{
+                               {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
+                       },
+                       outputs: []outputInfo{
                                {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
-                               {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
-                               {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
                        },
                },
        },
        {
-               name:   "CMNshiftRLreg",
-               argLen: 3,
-               asm:    arm.ACMN,
+               name:   "SRL",
+               argLen: 2,
+               asm:    arm.ASRL,
                reg: regInfo{
                        inputs: []inputInfo{
+                               {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
+                               {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
+                       },
+                       outputs: []outputInfo{
                                {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
-                               {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
-                               {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
                        },
                },
        },
        {
-               name:   "CMNshiftRAreg",
-               argLen: 3,
-               asm:    arm.ACMN,
+               name:    "SRLconst",
+               auxType: auxInt32,
+               argLen:  1,
+               asm:     arm.ASRL,
                reg: regInfo{
                        inputs: []inputInfo{
+                               {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
+                       },
+                       outputs: []outputInfo{
                                {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
-                               {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
-                               {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
                        },
                },
        },
        {
-               name:   "TSTshiftLLreg",
-               argLen: 3,
-               asm:    arm.ATST,
+               name:   "SRA",
+               argLen: 2,
+               asm:    arm.ASRA,
                reg: regInfo{
                        inputs: []inputInfo{
+                               {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
+                               {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
+                       },
+                       outputs: []outputInfo{
                                {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
-                               {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
-                               {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
                        },
                },
        },
        {
-               name:   "TSTshiftRLreg",
-               argLen: 3,
-               asm:    arm.ATST,
+               name:    "SRAconst",
+               auxType: auxInt32,
+               argLen:  1,
+               asm:     arm.ASRA,
                reg: regInfo{
                        inputs: []inputInfo{
+                               {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
+                       },
+                       outputs: []outputInfo{
                                {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
-                               {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
-                               {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
                        },
                },
        },
        {
-               name:   "TSTshiftRAreg",
-               argLen: 3,
-               asm:    arm.ATST,
+               name:   "SRR",
+               argLen: 2,
                reg: regInfo{
                        inputs: []inputInfo{
+                               {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
+                               {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
+                       },
+                       outputs: []outputInfo{
                                {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
-                               {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
-                               {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
                        },
                },
        },
        {
-               name:   "TEQshiftLLreg",
-               argLen: 3,
-               asm:    arm.ATEQ,
+               name:    "SRRconst",
+               auxType: auxInt32,
+               argLen:  1,
                reg: regInfo{
                        inputs: []inputInfo{
+                               {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
+                       },
+                       outputs: []outputInfo{
                                {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
-                               {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
-                               {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
                        },
                },
        },
        {
-               name:   "TEQshiftRLreg",
-               argLen: 3,
-               asm:    arm.ATEQ,
+               name:    "ADDshiftLL",
+               auxType: auxInt32,
+               argLen:  2,
+               asm:     arm.AADD,
                reg: regInfo{
                        inputs: []inputInfo{
+                               {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
+                               {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
+                       },
+                       outputs: []outputInfo{
                                {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
-                               {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
-                               {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
                        },
                },
        },
        {
-               name:   "TEQshiftRAreg",
-               argLen: 3,
-               asm:    arm.ATEQ,
+               name:    "ADDshiftRL",
+               auxType: auxInt32,
+               argLen:  2,
+               asm:     arm.AADD,
                reg: regInfo{
                        inputs: []inputInfo{
+                               {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
+                               {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
+                       },
+                       outputs: []outputInfo{
                                {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
-                               {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
-                               {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
                        },
                },
        },
        {
-               name:   "CMPF0",
-               argLen: 1,
-               asm:    arm.ACMPF,
+               name:    "ADDshiftRA",
+               auxType: auxInt32,
+               argLen:  2,
+               asm:     arm.AADD,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+                               {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
+                               {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
+                       },
+                       outputs: []outputInfo{
+                               {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
                        },
                },
        },
        {
-               name:   "CMPD0",
-               argLen: 1,
-               asm:    arm.ACMPD,
+               name:    "SUBshiftLL",
+               auxType: auxInt32,
+               argLen:  2,
+               asm:     arm.ASUB,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+                               {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
+                               {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
                        },
-               },
-       },
-       {
-               name:              "MOVWconst",
-               auxType:           auxInt32,
-               argLen:            0,
-               rematerializeable: true,
-               asm:               arm.AMOVW,
-               reg: regInfo{
                        outputs: []outputInfo{
                                {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
                        },
                },
        },
        {
-               name:              "MOVFconst",
-               auxType:           auxFloat64,
-               argLen:            0,
-               rematerializeable: true,
-               asm:               arm.AMOVF,
+               name:    "SUBshiftRL",
+               auxType: auxInt32,
+               argLen:  2,
+               asm:     arm.ASUB,
                reg: regInfo{
+                       inputs: []inputInfo{
+                               {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
+                               {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
+                       },
                        outputs: []outputInfo{
-                               {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+                               {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
                        },
                },
        },
        {
-               name:              "MOVDconst",
-               auxType:           auxFloat64,
-               argLen:            0,
-               rematerializeable: true,
-               asm:               arm.AMOVD,
+               name:    "SUBshiftRA",
+               auxType: auxInt32,
+               argLen:  2,
+               asm:     arm.ASUB,
                reg: regInfo{
+                       inputs: []inputInfo{
+                               {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
+                               {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
+                       },
                        outputs: []outputInfo{
-                               {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+                               {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
                        },
                },
        },
        {
-               name:              "MOVWaddr",
-               auxType:           auxSymOff,
-               argLen:            1,
-               rematerializeable: true,
-               symEffect:         SymAddr,
-               asm:               arm.AMOVW,
+               name:    "RSBshiftLL",
+               auxType: auxInt32,
+               argLen:  2,
+               asm:     arm.ARSB,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 4294975488}, // SP SB
+                               {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
+                               {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
                        },
                        outputs: []outputInfo{
                                {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
@@ -31275,15 +33282,14 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:           "MOVBload",
-               auxType:        auxSymOff,
-               argLen:         2,
-               faultOnNilArg0: true,
-               symEffect:      SymRead,
-               asm:            arm.AMOVB,
+               name:    "RSBshiftRL",
+               auxType: auxInt32,
+               argLen:  2,
+               asm:     arm.ARSB,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB
+                               {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
+                               {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
                        },
                        outputs: []outputInfo{
                                {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
@@ -31291,15 +33297,14 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:           "MOVBUload",
-               auxType:        auxSymOff,
-               argLen:         2,
-               faultOnNilArg0: true,
-               symEffect:      SymRead,
-               asm:            arm.AMOVBU,
+               name:    "RSBshiftRA",
+               auxType: auxInt32,
+               argLen:  2,
+               asm:     arm.ARSB,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB
+                               {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
+                               {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
                        },
                        outputs: []outputInfo{
                                {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
@@ -31307,15 +33312,14 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:           "MOVHload",
-               auxType:        auxSymOff,
-               argLen:         2,
-               faultOnNilArg0: true,
-               symEffect:      SymRead,
-               asm:            arm.AMOVH,
+               name:    "ANDshiftLL",
+               auxType: auxInt32,
+               argLen:  2,
+               asm:     arm.AAND,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB
+                               {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
+                               {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
                        },
                        outputs: []outputInfo{
                                {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
@@ -31323,15 +33327,14 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:           "MOVHUload",
-               auxType:        auxSymOff,
-               argLen:         2,
-               faultOnNilArg0: true,
-               symEffect:      SymRead,
-               asm:            arm.AMOVHU,
+               name:    "ANDshiftRL",
+               auxType: auxInt32,
+               argLen:  2,
+               asm:     arm.AAND,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB
+                               {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
+                               {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
                        },
                        outputs: []outputInfo{
                                {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
@@ -31339,15 +33342,14 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:           "MOVWload",
-               auxType:        auxSymOff,
-               argLen:         2,
-               faultOnNilArg0: true,
-               symEffect:      SymRead,
-               asm:            arm.AMOVW,
+               name:    "ANDshiftRA",
+               auxType: auxInt32,
+               argLen:  2,
+               asm:     arm.AAND,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB
+                               {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
+                               {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
                        },
                        outputs: []outputInfo{
                                {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
@@ -31355,115 +33357,104 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:           "MOVFload",
-               auxType:        auxSymOff,
-               argLen:         2,
-               faultOnNilArg0: true,
-               symEffect:      SymRead,
-               asm:            arm.AMOVF,
+               name:    "ORshiftLL",
+               auxType: auxInt32,
+               argLen:  2,
+               asm:     arm.AORR,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB
+                               {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
+                               {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
                        },
                        outputs: []outputInfo{
-                               {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+                               {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
                        },
                },
        },
        {
-               name:           "MOVDload",
-               auxType:        auxSymOff,
-               argLen:         2,
-               faultOnNilArg0: true,
-               symEffect:      SymRead,
-               asm:            arm.AMOVD,
+               name:    "ORshiftRL",
+               auxType: auxInt32,
+               argLen:  2,
+               asm:     arm.AORR,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB
+                               {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
+                               {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
                        },
                        outputs: []outputInfo{
-                               {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+                               {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
                        },
                },
        },
        {
-               name:           "MOVBstore",
-               auxType:        auxSymOff,
-               argLen:         3,
-               faultOnNilArg0: true,
-               symEffect:      SymWrite,
-               asm:            arm.AMOVB,
+               name:    "ORshiftRA",
+               auxType: auxInt32,
+               argLen:  2,
+               asm:     arm.AORR,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {1, 22527},      // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
-                               {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB
+                               {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
+                               {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
                        },
-               },
-       },
-       {
-               name:           "MOVHstore",
-               auxType:        auxSymOff,
-               argLen:         3,
-               faultOnNilArg0: true,
-               symEffect:      SymWrite,
-               asm:            arm.AMOVH,
-               reg: regInfo{
-                       inputs: []inputInfo{
-                               {1, 22527},      // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
-                               {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB
+                       outputs: []outputInfo{
+                               {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
                        },
                },
        },
        {
-               name:           "MOVWstore",
-               auxType:        auxSymOff,
-               argLen:         3,
-               faultOnNilArg0: true,
-               symEffect:      SymWrite,
-               asm:            arm.AMOVW,
+               name:    "XORshiftLL",
+               auxType: auxInt32,
+               argLen:  2,
+               asm:     arm.AEOR,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {1, 22527},      // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
-                               {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB
+                               {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
+                               {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
+                       },
+                       outputs: []outputInfo{
+                               {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
                        },
                },
        },
        {
-               name:           "MOVFstore",
-               auxType:        auxSymOff,
-               argLen:         3,
-               faultOnNilArg0: true,
-               symEffect:      SymWrite,
-               asm:            arm.AMOVF,
+               name:    "XORshiftRL",
+               auxType: auxInt32,
+               argLen:  2,
+               asm:     arm.AEOR,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB
-                               {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+                               {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
+                               {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
+                       },
+                       outputs: []outputInfo{
+                               {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
                        },
                },
        },
        {
-               name:           "MOVDstore",
-               auxType:        auxSymOff,
-               argLen:         3,
-               faultOnNilArg0: true,
-               symEffect:      SymWrite,
-               asm:            arm.AMOVD,
+               name:    "XORshiftRA",
+               auxType: auxInt32,
+               argLen:  2,
+               asm:     arm.AEOR,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB
-                               {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+                               {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
+                               {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
+                       },
+                       outputs: []outputInfo{
+                               {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
                        },
                },
        },
        {
-               name:   "MOVWloadidx",
-               argLen: 3,
-               asm:    arm.AMOVW,
+               name:    "XORshiftRR",
+               auxType: auxInt32,
+               argLen:  2,
+               asm:     arm.AEOR,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {1, 22527},      // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
-                               {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB
+                               {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
+                               {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
                        },
                        outputs: []outputInfo{
                                {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
@@ -31471,14 +33462,14 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:    "MOVWloadshiftLL",
+               name:    "BICshiftLL",
                auxType: auxInt32,
-               argLen:  3,
-               asm:     arm.AMOVW,
+               argLen:  2,
+               asm:     arm.ABIC,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {1, 22527},      // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
-                               {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB
+                               {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
+                               {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
                        },
                        outputs: []outputInfo{
                                {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
@@ -31486,14 +33477,14 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:    "MOVWloadshiftRL",
+               name:    "BICshiftRL",
                auxType: auxInt32,
-               argLen:  3,
-               asm:     arm.AMOVW,
+               argLen:  2,
+               asm:     arm.ABIC,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {1, 22527},      // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
-                               {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB
+                               {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
+                               {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
                        },
                        outputs: []outputInfo{
                                {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
@@ -31501,14 +33492,14 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:    "MOVWloadshiftRA",
+               name:    "BICshiftRA",
                auxType: auxInt32,
-               argLen:  3,
-               asm:     arm.AMOVW,
+               argLen:  2,
+               asm:     arm.ABIC,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {1, 22527},      // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
-                               {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB
+                               {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
+                               {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
                        },
                        outputs: []outputInfo{
                                {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
@@ -31516,13 +33507,13 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:   "MOVBUloadidx",
-               argLen: 3,
-               asm:    arm.AMOVBU,
+               name:    "MVNshiftLL",
+               auxType: auxInt32,
+               argLen:  1,
+               asm:     arm.AMVN,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {1, 22527},      // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
-                               {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB
+                               {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
                        },
                        outputs: []outputInfo{
                                {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
@@ -31530,13 +33521,13 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:   "MOVBloadidx",
-               argLen: 3,
-               asm:    arm.AMOVB,
+               name:    "MVNshiftRL",
+               auxType: auxInt32,
+               argLen:  1,
+               asm:     arm.AMVN,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {1, 22527},      // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
-                               {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB
+                               {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
                        },
                        outputs: []outputInfo{
                                {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
@@ -31544,13 +33535,13 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:   "MOVHUloadidx",
-               argLen: 3,
-               asm:    arm.AMOVHU,
+               name:    "MVNshiftRA",
+               auxType: auxInt32,
+               argLen:  1,
+               asm:     arm.AMVN,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {1, 22527},      // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
-                               {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB
+                               {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
                        },
                        outputs: []outputInfo{
                                {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
@@ -31558,13 +33549,14 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:   "MOVHloadidx",
-               argLen: 3,
-               asm:    arm.AMOVH,
+               name:    "ADCshiftLL",
+               auxType: auxInt32,
+               argLen:  3,
+               asm:     arm.AADC,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {1, 22527},      // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
-                               {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB
+                               {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+                               {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
                        },
                        outputs: []outputInfo{
                                {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
@@ -31572,87 +33564,104 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:   "MOVWstoreidx",
-               argLen: 4,
-               asm:    arm.AMOVW,
+               name:    "ADCshiftRL",
+               auxType: auxInt32,
+               argLen:  3,
+               asm:     arm.AADC,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {1, 22527},      // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
-                               {2, 22527},      // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
-                               {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB
+                               {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+                               {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+                       },
+                       outputs: []outputInfo{
+                               {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
                        },
                },
        },
        {
-               name:    "MOVWstoreshiftLL",
+               name:    "ADCshiftRA",
                auxType: auxInt32,
-               argLen:  4,
-               asm:     arm.AMOVW,
+               argLen:  3,
+               asm:     arm.AADC,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {1, 22527},      // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
-                               {2, 22527},      // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
-                               {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB
+                               {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+                               {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+                       },
+                       outputs: []outputInfo{
+                               {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
                        },
                },
        },
        {
-               name:    "MOVWstoreshiftRL",
+               name:    "SBCshiftLL",
                auxType: auxInt32,
-               argLen:  4,
-               asm:     arm.AMOVW,
+               argLen:  3,
+               asm:     arm.ASBC,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {1, 22527},      // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
-                               {2, 22527},      // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
-                               {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB
+                               {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+                               {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+                       },
+                       outputs: []outputInfo{
+                               {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
                        },
                },
        },
        {
-               name:    "MOVWstoreshiftRA",
+               name:    "SBCshiftRL",
                auxType: auxInt32,
-               argLen:  4,
-               asm:     arm.AMOVW,
+               argLen:  3,
+               asm:     arm.ASBC,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {1, 22527},      // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
-                               {2, 22527},      // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
-                               {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB
+                               {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+                               {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+                       },
+                       outputs: []outputInfo{
+                               {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
                        },
                },
        },
        {
-               name:   "MOVBstoreidx",
-               argLen: 4,
-               asm:    arm.AMOVB,
+               name:    "SBCshiftRA",
+               auxType: auxInt32,
+               argLen:  3,
+               asm:     arm.ASBC,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {1, 22527},      // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
-                               {2, 22527},      // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
-                               {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB
+                               {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+                               {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+                       },
+                       outputs: []outputInfo{
+                               {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
                        },
                },
        },
        {
-               name:   "MOVHstoreidx",
-               argLen: 4,
-               asm:    arm.AMOVH,
+               name:    "RSCshiftLL",
+               auxType: auxInt32,
+               argLen:  3,
+               asm:     arm.ARSC,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {1, 22527},      // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
-                               {2, 22527},      // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
-                               {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB
+                               {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+                               {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+                       },
+                       outputs: []outputInfo{
+                               {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
                        },
                },
        },
        {
-               name:   "MOVBreg",
-               argLen: 1,
-               asm:    arm.AMOVBS,
+               name:    "RSCshiftRL",
+               auxType: auxInt32,
+               argLen:  3,
+               asm:     arm.ARSC,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
+                               {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+                               {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
                        },
                        outputs: []outputInfo{
                                {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
@@ -31660,12 +33669,14 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:   "MOVBUreg",
-               argLen: 1,
-               asm:    arm.AMOVBU,
+               name:    "RSCshiftRA",
+               auxType: auxInt32,
+               argLen:  3,
+               asm:     arm.ARSC,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
+                               {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+                               {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
                        },
                        outputs: []outputInfo{
                                {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
@@ -31673,204 +33684,233 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:   "MOVHreg",
-               argLen: 1,
-               asm:    arm.AMOVHS,
+               name:    "ADDSshiftLL",
+               auxType: auxInt32,
+               argLen:  2,
+               asm:     arm.AADD,
                reg: regInfo{
                        inputs: []inputInfo{
                                {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
+                               {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
                        },
                        outputs: []outputInfo{
+                               {1, 0},
                                {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
                        },
                },
        },
        {
-               name:   "MOVHUreg",
-               argLen: 1,
-               asm:    arm.AMOVHU,
+               name:    "ADDSshiftRL",
+               auxType: auxInt32,
+               argLen:  2,
+               asm:     arm.AADD,
                reg: regInfo{
                        inputs: []inputInfo{
                                {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
+                               {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
                        },
                        outputs: []outputInfo{
+                               {1, 0},
                                {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
                        },
                },
        },
        {
-               name:   "MOVWreg",
-               argLen: 1,
-               asm:    arm.AMOVW,
+               name:    "ADDSshiftRA",
+               auxType: auxInt32,
+               argLen:  2,
+               asm:     arm.AADD,
                reg: regInfo{
                        inputs: []inputInfo{
                                {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
+                               {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
                        },
                        outputs: []outputInfo{
+                               {1, 0},
                                {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
                        },
                },
        },
        {
-               name:         "MOVWnop",
-               argLen:       1,
-               resultInArg0: true,
+               name:    "SUBSshiftLL",
+               auxType: auxInt32,
+               argLen:  2,
+               asm:     arm.ASUB,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+                               {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
+                               {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
                        },
                        outputs: []outputInfo{
+                               {1, 0},
                                {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
                        },
                },
        },
        {
-               name:   "MOVWF",
-               argLen: 1,
-               asm:    arm.AMOVWF,
+               name:    "SUBSshiftRL",
+               auxType: auxInt32,
+               argLen:  2,
+               asm:     arm.ASUB,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+                               {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
+                               {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
                        },
-                       clobbers: 2147483648, // F15
                        outputs: []outputInfo{
-                               {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+                               {1, 0},
+                               {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
                        },
                },
        },
        {
-               name:   "MOVWD",
-               argLen: 1,
-               asm:    arm.AMOVWD,
+               name:    "SUBSshiftRA",
+               auxType: auxInt32,
+               argLen:  2,
+               asm:     arm.ASUB,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+                               {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
+                               {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
                        },
-                       clobbers: 2147483648, // F15
                        outputs: []outputInfo{
-                               {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+                               {1, 0},
+                               {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
                        },
                },
        },
        {
-               name:   "MOVWUF",
-               argLen: 1,
-               asm:    arm.AMOVWF,
+               name:    "RSBSshiftLL",
+               auxType: auxInt32,
+               argLen:  2,
+               asm:     arm.ARSB,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+                               {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
+                               {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
                        },
-                       clobbers: 2147483648, // F15
                        outputs: []outputInfo{
-                               {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+                               {1, 0},
+                               {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
                        },
                },
        },
        {
-               name:   "MOVWUD",
-               argLen: 1,
-               asm:    arm.AMOVWD,
+               name:    "RSBSshiftRL",
+               auxType: auxInt32,
+               argLen:  2,
+               asm:     arm.ARSB,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+                               {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
+                               {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
                        },
-                       clobbers: 2147483648, // F15
                        outputs: []outputInfo{
-                               {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+                               {1, 0},
+                               {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
                        },
                },
        },
        {
-               name:   "MOVFW",
-               argLen: 1,
-               asm:    arm.AMOVFW,
+               name:    "RSBSshiftRA",
+               auxType: auxInt32,
+               argLen:  2,
+               asm:     arm.ARSB,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+                               {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
+                               {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
                        },
-                       clobbers: 2147483648, // F15
                        outputs: []outputInfo{
+                               {1, 0},
                                {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
                        },
                },
        },
        {
-               name:   "MOVDW",
-               argLen: 1,
-               asm:    arm.AMOVDW,
+               name:   "ADDshiftLLreg",
+               argLen: 3,
+               asm:    arm.AADD,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+                               {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+                               {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+                               {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
                        },
-                       clobbers: 2147483648, // F15
                        outputs: []outputInfo{
                                {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
                        },
                },
        },
        {
-               name:   "MOVFWU",
-               argLen: 1,
-               asm:    arm.AMOVFW,
+               name:   "ADDshiftRLreg",
+               argLen: 3,
+               asm:    arm.AADD,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+                               {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+                               {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+                               {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
                        },
-                       clobbers: 2147483648, // F15
                        outputs: []outputInfo{
                                {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
                        },
                },
        },
        {
-               name:   "MOVDWU",
-               argLen: 1,
-               asm:    arm.AMOVDW,
+               name:   "ADDshiftRAreg",
+               argLen: 3,
+               asm:    arm.AADD,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+                               {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+                               {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+                               {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
                        },
-                       clobbers: 2147483648, // F15
                        outputs: []outputInfo{
                                {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
                        },
                },
        },
        {
-               name:   "MOVFD",
-               argLen: 1,
-               asm:    arm.AMOVFD,
+               name:   "SUBshiftLLreg",
+               argLen: 3,
+               asm:    arm.ASUB,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+                               {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+                               {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+                               {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
                        },
                        outputs: []outputInfo{
-                               {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+                               {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
                        },
                },
        },
        {
-               name:   "MOVDF",
-               argLen: 1,
-               asm:    arm.AMOVDF,
+               name:   "SUBshiftRLreg",
+               argLen: 3,
+               asm:    arm.ASUB,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+                               {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+                               {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+                               {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
                        },
                        outputs: []outputInfo{
-                               {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+                               {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
                        },
                },
        },
        {
-               name:         "CMOVWHSconst",
-               auxType:      auxInt32,
-               argLen:       2,
-               resultInArg0: true,
-               asm:          arm.AMOVW,
+               name:   "SUBshiftRAreg",
+               argLen: 3,
+               asm:    arm.ASUB,
                reg: regInfo{
                        inputs: []inputInfo{
                                {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+                               {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+                               {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
                        },
                        outputs: []outputInfo{
                                {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
@@ -31878,14 +33918,14 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:         "CMOVWLSconst",
-               auxType:      auxInt32,
-               argLen:       2,
-               resultInArg0: true,
-               asm:          arm.AMOVW,
+               name:   "RSBshiftLLreg",
+               argLen: 3,
+               asm:    arm.ARSB,
                reg: regInfo{
                        inputs: []inputInfo{
                                {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+                               {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+                               {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
                        },
                        outputs: []outputInfo{
                                {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
@@ -31893,13 +33933,14 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:   "SRAcond",
+               name:   "RSBshiftRLreg",
                argLen: 3,
-               asm:    arm.ASRA,
+               asm:    arm.ARSB,
                reg: regInfo{
                        inputs: []inputInfo{
                                {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
                                {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+                               {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
                        },
                        outputs: []outputInfo{
                                {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
@@ -31907,1997 +33948,1993 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:         "CALLstatic",
-               auxType:      auxCallOff,
-               argLen:       1,
-               clobberFlags: true,
-               call:         true,
-               reg: regInfo{
-                       clobbers: 4294924287, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
-               },
-       },
-       {
-               name:         "CALLtail",
-               auxType:      auxCallOff,
-               argLen:       1,
-               clobberFlags: true,
-               call:         true,
-               tailCall:     true,
+               name:   "RSBshiftRAreg",
+               argLen: 3,
+               asm:    arm.ARSB,
                reg: regInfo{
-                       clobbers: 4294924287, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+                       inputs: []inputInfo{
+                               {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+                               {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+                               {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+                       },
+                       outputs: []outputInfo{
+                               {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+                       },
                },
        },
        {
-               name:         "CALLclosure",
-               auxType:      auxCallOff,
-               argLen:       3,
-               clobberFlags: true,
-               call:         true,
+               name:   "ANDshiftLLreg",
+               argLen: 3,
+               asm:    arm.AAND,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {1, 128},   // R7
-                               {0, 29695}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 SP R14
+                               {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+                               {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+                               {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+                       },
+                       outputs: []outputInfo{
+                               {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
                        },
-                       clobbers: 4294924287, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
                },
        },
        {
-               name:         "CALLinter",
-               auxType:      auxCallOff,
-               argLen:       2,
-               clobberFlags: true,
-               call:         true,
+               name:   "ANDshiftRLreg",
+               argLen: 3,
+               asm:    arm.AAND,
                reg: regInfo{
                        inputs: []inputInfo{
                                {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+                               {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+                               {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+                       },
+                       outputs: []outputInfo{
+                               {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
                        },
-                       clobbers: 4294924287, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
                },
        },
        {
-               name:           "LoweredNilCheck",
-               argLen:         2,
-               nilCheck:       true,
-               faultOnNilArg0: true,
+               name:   "ANDshiftRAreg",
+               argLen: 3,
+               asm:    arm.AAND,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
+                               {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+                               {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+                               {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+                       },
+                       outputs: []outputInfo{
+                               {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
                        },
                },
        },
        {
-               name:   "Equal",
-               argLen: 1,
+               name:   "ORshiftLLreg",
+               argLen: 3,
+               asm:    arm.AORR,
                reg: regInfo{
+                       inputs: []inputInfo{
+                               {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+                               {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+                               {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+                       },
                        outputs: []outputInfo{
                                {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
                        },
                },
        },
        {
-               name:   "NotEqual",
-               argLen: 1,
+               name:   "ORshiftRLreg",
+               argLen: 3,
+               asm:    arm.AORR,
                reg: regInfo{
+                       inputs: []inputInfo{
+                               {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+                               {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+                               {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+                       },
                        outputs: []outputInfo{
                                {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
                        },
                },
        },
        {
-               name:   "LessThan",
-               argLen: 1,
+               name:   "ORshiftRAreg",
+               argLen: 3,
+               asm:    arm.AORR,
                reg: regInfo{
+                       inputs: []inputInfo{
+                               {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+                               {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+                               {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+                       },
                        outputs: []outputInfo{
                                {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
                        },
                },
        },
        {
-               name:   "LessEqual",
-               argLen: 1,
+               name:   "XORshiftLLreg",
+               argLen: 3,
+               asm:    arm.AEOR,
                reg: regInfo{
+                       inputs: []inputInfo{
+                               {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+                               {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+                               {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+                       },
                        outputs: []outputInfo{
                                {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
                        },
                },
        },
        {
-               name:   "GreaterThan",
-               argLen: 1,
+               name:   "XORshiftRLreg",
+               argLen: 3,
+               asm:    arm.AEOR,
                reg: regInfo{
+                       inputs: []inputInfo{
+                               {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+                               {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+                               {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+                       },
                        outputs: []outputInfo{
                                {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
                        },
                },
        },
        {
-               name:   "GreaterEqual",
-               argLen: 1,
+               name:   "XORshiftRAreg",
+               argLen: 3,
+               asm:    arm.AEOR,
                reg: regInfo{
+                       inputs: []inputInfo{
+                               {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+                               {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+                               {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+                       },
                        outputs: []outputInfo{
                                {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
                        },
                },
        },
        {
-               name:   "LessThanU",
-               argLen: 1,
+               name:   "BICshiftLLreg",
+               argLen: 3,
+               asm:    arm.ABIC,
                reg: regInfo{
+                       inputs: []inputInfo{
+                               {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+                               {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+                               {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+                       },
                        outputs: []outputInfo{
                                {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
                        },
                },
        },
        {
-               name:   "LessEqualU",
-               argLen: 1,
+               name:   "BICshiftRLreg",
+               argLen: 3,
+               asm:    arm.ABIC,
                reg: regInfo{
+                       inputs: []inputInfo{
+                               {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+                               {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+                               {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+                       },
                        outputs: []outputInfo{
                                {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
                        },
                },
        },
        {
-               name:   "GreaterThanU",
-               argLen: 1,
+               name:   "BICshiftRAreg",
+               argLen: 3,
+               asm:    arm.ABIC,
                reg: regInfo{
+                       inputs: []inputInfo{
+                               {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+                               {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+                               {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+                       },
                        outputs: []outputInfo{
                                {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
                        },
                },
        },
        {
-               name:   "GreaterEqualU",
-               argLen: 1,
+               name:   "MVNshiftLLreg",
+               argLen: 2,
+               asm:    arm.AMVN,
                reg: regInfo{
+                       inputs: []inputInfo{
+                               {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
+                               {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
+                       },
                        outputs: []outputInfo{
                                {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
                        },
                },
        },
        {
-               name:           "DUFFZERO",
-               auxType:        auxInt64,
-               argLen:         3,
-               faultOnNilArg0: true,
+               name:   "MVNshiftRLreg",
+               argLen: 2,
+               asm:    arm.AMVN,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 2}, // R1
-                               {1, 1}, // R0
+                               {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
+                               {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
+                       },
+                       outputs: []outputInfo{
+                               {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
                        },
-                       clobbers: 20482, // R1 R12 R14
                },
        },
        {
-               name:           "DUFFCOPY",
-               auxType:        auxInt64,
-               argLen:         3,
-               faultOnNilArg0: true,
-               faultOnNilArg1: true,
+               name:   "MVNshiftRAreg",
+               argLen: 2,
+               asm:    arm.AMVN,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 4}, // R2
-                               {1, 2}, // R1
+                               {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
+                               {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
+                       },
+                       outputs: []outputInfo{
+                               {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
                        },
-                       clobbers: 20487, // R0 R1 R2 R12 R14
                },
        },
        {
-               name:           "LoweredZero",
-               auxType:        auxInt64,
-               argLen:         4,
-               clobberFlags:   true,
-               faultOnNilArg0: true,
+               name:   "ADCshiftLLreg",
+               argLen: 4,
+               asm:    arm.AADC,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 2},     // R1
+                               {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
                                {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
                                {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
                        },
-                       clobbers: 2, // R1
+                       outputs: []outputInfo{
+                               {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+                       },
                },
        },
        {
-               name:           "LoweredMove",
-               auxType:        auxInt64,
-               argLen:         4,
-               clobberFlags:   true,
-               faultOnNilArg0: true,
-               faultOnNilArg1: true,
+               name:   "ADCshiftRLreg",
+               argLen: 4,
+               asm:    arm.AADC,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 4},     // R2
-                               {1, 2},     // R1
+                               {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+                               {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
                                {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
                        },
-                       clobbers: 6, // R1 R2
-               },
-       },
-       {
-               name:      "LoweredGetClosurePtr",
-               argLen:    0,
-               zeroWidth: true,
-               reg: regInfo{
                        outputs: []outputInfo{
-                               {0, 128}, // R7
+                               {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
                        },
                },
        },
        {
-               name:              "LoweredGetCallerSP",
-               argLen:            1,
-               rematerializeable: true,
+               name:   "ADCshiftRAreg",
+               argLen: 4,
+               asm:    arm.AADC,
                reg: regInfo{
-                       outputs: []outputInfo{
+                       inputs: []inputInfo{
                                {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+                               {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+                               {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
                        },
-               },
-       },
-       {
-               name:              "LoweredGetCallerPC",
-               argLen:            0,
-               rematerializeable: true,
-               reg: regInfo{
                        outputs: []outputInfo{
                                {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
                        },
                },
        },
        {
-               name:    "LoweredPanicBoundsA",
-               auxType: auxInt64,
-               argLen:  3,
-               call:    true,
+               name:   "SBCshiftLLreg",
+               argLen: 4,
+               asm:    arm.ASBC,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 4}, // R2
-                               {1, 8}, // R3
+                               {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+                               {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+                               {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+                       },
+                       outputs: []outputInfo{
+                               {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
                        },
                },
        },
        {
-               name:    "LoweredPanicBoundsB",
-               auxType: auxInt64,
-               argLen:  3,
-               call:    true,
+               name:   "SBCshiftRLreg",
+               argLen: 4,
+               asm:    arm.ASBC,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 2}, // R1
-                               {1, 4}, // R2
+                               {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+                               {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+                               {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+                       },
+                       outputs: []outputInfo{
+                               {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
                        },
                },
        },
        {
-               name:    "LoweredPanicBoundsC",
-               auxType: auxInt64,
-               argLen:  3,
-               call:    true,
+               name:   "SBCshiftRAreg",
+               argLen: 4,
+               asm:    arm.ASBC,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 1}, // R0
-                               {1, 2}, // R1
+                               {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+                               {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+                               {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+                       },
+                       outputs: []outputInfo{
+                               {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
                        },
                },
        },
        {
-               name:    "LoweredPanicExtendA",
-               auxType: auxInt64,
-               argLen:  4,
-               call:    true,
+               name:   "RSCshiftLLreg",
+               argLen: 4,
+               asm:    arm.ARSC,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 16}, // R4
-                               {1, 4},  // R2
-                               {2, 8},  // R3
+                               {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+                               {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+                               {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+                       },
+                       outputs: []outputInfo{
+                               {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
                        },
                },
        },
        {
-               name:    "LoweredPanicExtendB",
-               auxType: auxInt64,
-               argLen:  4,
-               call:    true,
+               name:   "RSCshiftRLreg",
+               argLen: 4,
+               asm:    arm.ARSC,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 16}, // R4
-                               {1, 2},  // R1
-                               {2, 4},  // R2
+                               {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+                               {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+                               {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+                       },
+                       outputs: []outputInfo{
+                               {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
                        },
                },
        },
        {
-               name:    "LoweredPanicExtendC",
-               auxType: auxInt64,
-               argLen:  4,
-               call:    true,
+               name:   "RSCshiftRAreg",
+               argLen: 4,
+               asm:    arm.ARSC,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 16}, // R4
-                               {1, 1},  // R0
-                               {2, 2},  // R1
+                               {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+                               {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+                               {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
                        },
-               },
-       },
-       {
-               name:    "FlagConstant",
-               auxType: auxFlagConstant,
-               argLen:  0,
-               reg:     regInfo{},
-       },
-       {
-               name:   "InvertFlags",
-               argLen: 1,
-               reg:    regInfo{},
-       },
-       {
-               name:         "LoweredWB",
-               auxType:      auxInt64,
-               argLen:       1,
-               clobberFlags: true,
-               reg: regInfo{
-                       clobbers: 4294922240, // R12 R14 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
                        outputs: []outputInfo{
-                               {0, 256}, // R8
+                               {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
                        },
                },
        },
-
        {
-               name:        "ADCSflags",
-               argLen:      3,
-               commutative: true,
-               asm:         arm64.AADCS,
+               name:   "ADDSshiftLLreg",
+               argLen: 3,
+               asm:    arm.AADD,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
-                               {1, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
+                               {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+                               {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+                               {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
                        },
                        outputs: []outputInfo{
                                {1, 0},
-                               {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
+                               {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
                        },
                },
        },
        {
-               name:   "ADCzerocarry",
-               argLen: 1,
-               asm:    arm64.AADC,
+               name:   "ADDSshiftRLreg",
+               argLen: 3,
+               asm:    arm.AADD,
                reg: regInfo{
+                       inputs: []inputInfo{
+                               {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+                               {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+                               {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+                       },
                        outputs: []outputInfo{
-                               {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
+                               {1, 0},
+                               {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
                        },
                },
        },
        {
-               name:        "ADD",
-               argLen:      2,
-               commutative: true,
-               asm:         arm64.AADD,
+               name:   "ADDSshiftRAreg",
+               argLen: 3,
+               asm:    arm.AADD,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
-                               {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
+                               {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+                               {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+                               {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
                        },
                        outputs: []outputInfo{
-                               {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
+                               {1, 0},
+                               {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
                        },
                },
        },
        {
-               name:    "ADDconst",
-               auxType: auxInt64,
-               argLen:  1,
-               asm:     arm64.AADD,
+               name:   "SUBSshiftLLreg",
+               argLen: 3,
+               asm:    arm.ASUB,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 1476395007}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP
+                               {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+                               {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+                               {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
                        },
                        outputs: []outputInfo{
-                               {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
+                               {1, 0},
+                               {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
                        },
                },
        },
        {
-               name:    "ADDSconstflags",
-               auxType: auxInt64,
-               argLen:  1,
-               asm:     arm64.AADDS,
+               name:   "SUBSshiftRLreg",
+               argLen: 3,
+               asm:    arm.ASUB,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
+                               {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+                               {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+                               {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
                        },
                        outputs: []outputInfo{
                                {1, 0},
-                               {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
+                               {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
                        },
                },
        },
        {
-               name:        "ADDSflags",
-               argLen:      2,
-               commutative: true,
-               asm:         arm64.AADDS,
+               name:   "SUBSshiftRAreg",
+               argLen: 3,
+               asm:    arm.ASUB,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
-                               {1, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
+                               {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+                               {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+                               {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
                        },
                        outputs: []outputInfo{
                                {1, 0},
-                               {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
+                               {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
                        },
                },
        },
        {
-               name:   "SUB",
-               argLen: 2,
-               asm:    arm64.ASUB,
+               name:   "RSBSshiftLLreg",
+               argLen: 3,
+               asm:    arm.ARSB,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
-                               {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
+                               {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+                               {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+                               {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
                        },
                        outputs: []outputInfo{
-                               {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
+                               {1, 0},
+                               {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
                        },
                },
        },
        {
-               name:    "SUBconst",
-               auxType: auxInt64,
-               argLen:  1,
-               asm:     arm64.ASUB,
+               name:   "RSBSshiftRLreg",
+               argLen: 3,
+               asm:    arm.ARSB,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
+                               {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+                               {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+                               {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
                        },
                        outputs: []outputInfo{
-                               {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
+                               {1, 0},
+                               {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
                        },
                },
        },
        {
-               name:   "SBCSflags",
+               name:   "RSBSshiftRAreg",
                argLen: 3,
-               asm:    arm64.ASBCS,
+               asm:    arm.ARSB,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
-                               {1, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
+                               {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+                               {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+                               {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
                        },
                        outputs: []outputInfo{
                                {1, 0},
-                               {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
+                               {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
                        },
                },
        },
        {
-               name:   "SUBSflags",
+               name:   "CMP",
                argLen: 2,
-               asm:    arm64.ASUBS,
+               asm:    arm.ACMP,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
-                               {1, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
-                       },
-                       outputs: []outputInfo{
-                               {1, 0},
-                               {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
+                               {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
+                               {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
                        },
                },
        },
        {
-               name:        "MUL",
-               argLen:      2,
-               commutative: true,
-               asm:         arm64.AMUL,
+               name:    "CMPconst",
+               auxType: auxInt32,
+               argLen:  1,
+               asm:     arm.ACMP,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
-                               {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
-                       },
-                       outputs: []outputInfo{
-                               {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
-                       },
-               },
-       },
-       {
-               name:        "MULW",
-               argLen:      2,
-               commutative: true,
-               asm:         arm64.AMULW,
-               reg: regInfo{
-                       inputs: []inputInfo{
-                               {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
-                               {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
-                       },
-                       outputs: []outputInfo{
-                               {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
+                               {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
                        },
                },
        },
        {
-               name:        "MNEG",
+               name:        "CMN",
                argLen:      2,
                commutative: true,
-               asm:         arm64.AMNEG,
+               asm:         arm.ACMN,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
-                               {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
-                       },
-                       outputs: []outputInfo{
-                               {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
+                               {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
+                               {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
                        },
                },
        },
        {
-               name:        "MNEGW",
-               argLen:      2,
-               commutative: true,
-               asm:         arm64.AMNEGW,
+               name:    "CMNconst",
+               auxType: auxInt32,
+               argLen:  1,
+               asm:     arm.ACMN,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
-                               {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
-                       },
-                       outputs: []outputInfo{
-                               {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
+                               {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
                        },
                },
        },
        {
-               name:        "MULH",
+               name:        "TST",
                argLen:      2,
                commutative: true,
-               asm:         arm64.ASMULH,
+               asm:         arm.ATST,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
-                               {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
-                       },
-                       outputs: []outputInfo{
-                               {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
+                               {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
+                               {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
                        },
                },
        },
        {
-               name:        "UMULH",
-               argLen:      2,
-               commutative: true,
-               asm:         arm64.AUMULH,
+               name:    "TSTconst",
+               auxType: auxInt32,
+               argLen:  1,
+               asm:     arm.ATST,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
-                               {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
-                       },
-                       outputs: []outputInfo{
-                               {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
+                               {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
                        },
                },
        },
        {
-               name:        "MULL",
+               name:        "TEQ",
                argLen:      2,
                commutative: true,
-               asm:         arm64.ASMULL,
+               asm:         arm.ATEQ,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
-                               {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
-                       },
-                       outputs: []outputInfo{
-                               {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
+                               {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
+                               {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
                        },
                },
        },
        {
-               name:        "UMULL",
-               argLen:      2,
-               commutative: true,
-               asm:         arm64.AUMULL,
+               name:    "TEQconst",
+               auxType: auxInt32,
+               argLen:  1,
+               asm:     arm.ATEQ,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
-                               {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
-                       },
-                       outputs: []outputInfo{
-                               {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
+                               {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
                        },
                },
        },
        {
-               name:   "DIV",
+               name:   "CMPF",
                argLen: 2,
-               asm:    arm64.ASDIV,
+               asm:    arm.ACMPF,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
-                               {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
-                       },
-                       outputs: []outputInfo{
-                               {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
+                               {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+                               {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
                        },
                },
        },
        {
-               name:   "UDIV",
+               name:   "CMPD",
                argLen: 2,
-               asm:    arm64.AUDIV,
+               asm:    arm.ACMPD,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
-                               {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
-                       },
-                       outputs: []outputInfo{
-                               {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
+                               {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+                               {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
                        },
                },
        },
        {
-               name:   "DIVW",
-               argLen: 2,
-               asm:    arm64.ASDIVW,
+               name:    "CMPshiftLL",
+               auxType: auxInt32,
+               argLen:  2,
+               asm:     arm.ACMP,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
-                               {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
-                       },
-                       outputs: []outputInfo{
-                               {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
+                               {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
+                               {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
                        },
                },
        },
        {
-               name:   "UDIVW",
-               argLen: 2,
-               asm:    arm64.AUDIVW,
+               name:    "CMPshiftRL",
+               auxType: auxInt32,
+               argLen:  2,
+               asm:     arm.ACMP,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
-                               {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
-                       },
-                       outputs: []outputInfo{
-                               {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
+                               {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
+                               {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
                        },
                },
        },
        {
-               name:   "MOD",
-               argLen: 2,
-               asm:    arm64.AREM,
+               name:    "CMPshiftRA",
+               auxType: auxInt32,
+               argLen:  2,
+               asm:     arm.ACMP,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
-                               {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
-                       },
-                       outputs: []outputInfo{
-                               {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
+                               {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
+                               {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
                        },
                },
        },
        {
-               name:   "UMOD",
-               argLen: 2,
-               asm:    arm64.AUREM,
+               name:    "CMNshiftLL",
+               auxType: auxInt32,
+               argLen:  2,
+               asm:     arm.ACMN,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
-                               {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
-                       },
-                       outputs: []outputInfo{
-                               {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
+                               {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
+                               {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
                        },
                },
        },
        {
-               name:   "MODW",
-               argLen: 2,
-               asm:    arm64.AREMW,
+               name:    "CMNshiftRL",
+               auxType: auxInt32,
+               argLen:  2,
+               asm:     arm.ACMN,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
-                               {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
-                       },
-                       outputs: []outputInfo{
-                               {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
+                               {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
+                               {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
                        },
                },
        },
        {
-               name:   "UMODW",
-               argLen: 2,
-               asm:    arm64.AUREMW,
+               name:    "CMNshiftRA",
+               auxType: auxInt32,
+               argLen:  2,
+               asm:     arm.ACMN,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
-                               {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
-                       },
-                       outputs: []outputInfo{
-                               {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
+                               {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
+                               {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
                        },
                },
        },
        {
-               name:        "FADDS",
-               argLen:      2,
-               commutative: true,
-               asm:         arm64.AFADDS,
+               name:    "TSTshiftLL",
+               auxType: auxInt32,
+               argLen:  2,
+               asm:     arm.ATST,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
-                               {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
-                       },
-                       outputs: []outputInfo{
-                               {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
+                               {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
                        },
                },
        },
        {
-               name:        "FADDD",
-               argLen:      2,
-               commutative: true,
-               asm:         arm64.AFADDD,
+               name:    "TSTshiftRL",
+               auxType: auxInt32,
+               argLen:  2,
+               asm:     arm.ATST,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
-                               {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
-                       },
-                       outputs: []outputInfo{
-                               {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
+                               {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
                        },
                },
        },
        {
-               name:   "FSUBS",
-               argLen: 2,
-               asm:    arm64.AFSUBS,
+               name:    "TSTshiftRA",
+               auxType: auxInt32,
+               argLen:  2,
+               asm:     arm.ATST,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
-                               {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
-                       },
-                       outputs: []outputInfo{
-                               {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
+                               {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
                        },
                },
        },
        {
-               name:   "FSUBD",
-               argLen: 2,
-               asm:    arm64.AFSUBD,
+               name:    "TEQshiftLL",
+               auxType: auxInt32,
+               argLen:  2,
+               asm:     arm.ATEQ,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
-                               {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
-                       },
-                       outputs: []outputInfo{
-                               {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
+                               {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
                        },
                },
        },
        {
-               name:        "FMULS",
-               argLen:      2,
-               commutative: true,
-               asm:         arm64.AFMULS,
+               name:    "TEQshiftRL",
+               auxType: auxInt32,
+               argLen:  2,
+               asm:     arm.ATEQ,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
-                               {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
-                       },
-                       outputs: []outputInfo{
-                               {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
+                               {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
                        },
                },
        },
        {
-               name:        "FMULD",
-               argLen:      2,
-               commutative: true,
-               asm:         arm64.AFMULD,
+               name:    "TEQshiftRA",
+               auxType: auxInt32,
+               argLen:  2,
+               asm:     arm.ATEQ,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
-                               {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
-                       },
-                       outputs: []outputInfo{
-                               {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
+                               {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
                        },
                },
        },
        {
-               name:        "FNMULS",
-               argLen:      2,
-               commutative: true,
-               asm:         arm64.AFNMULS,
+               name:   "CMPshiftLLreg",
+               argLen: 3,
+               asm:    arm.ACMP,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
-                               {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
-                       },
-                       outputs: []outputInfo{
-                               {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+                               {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+                               {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
                        },
                },
        },
        {
-               name:        "FNMULD",
-               argLen:      2,
-               commutative: true,
-               asm:         arm64.AFNMULD,
+               name:   "CMPshiftRLreg",
+               argLen: 3,
+               asm:    arm.ACMP,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
-                               {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
-                       },
-                       outputs: []outputInfo{
-                               {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+                               {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+                               {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
                        },
                },
        },
        {
-               name:   "FDIVS",
-               argLen: 2,
-               asm:    arm64.AFDIVS,
+               name:   "CMPshiftRAreg",
+               argLen: 3,
+               asm:    arm.ACMP,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
-                               {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
-                       },
-                       outputs: []outputInfo{
-                               {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+                               {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+                               {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
                        },
                },
        },
        {
-               name:   "FDIVD",
-               argLen: 2,
-               asm:    arm64.AFDIVD,
+               name:   "CMNshiftLLreg",
+               argLen: 3,
+               asm:    arm.ACMN,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
-                               {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
-                       },
-                       outputs: []outputInfo{
-                               {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+                               {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+                               {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
                        },
                },
        },
        {
-               name:        "AND",
-               argLen:      2,
-               commutative: true,
-               asm:         arm64.AAND,
+               name:   "CMNshiftRLreg",
+               argLen: 3,
+               asm:    arm.ACMN,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
-                               {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
-                       },
-                       outputs: []outputInfo{
-                               {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
+                               {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+                               {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+                               {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
                        },
                },
        },
        {
-               name:    "ANDconst",
-               auxType: auxInt64,
-               argLen:  1,
-               asm:     arm64.AAND,
+               name:   "CMNshiftRAreg",
+               argLen: 3,
+               asm:    arm.ACMN,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
-                       },
-                       outputs: []outputInfo{
-                               {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
+                               {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+                               {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+                               {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
                        },
                },
        },
        {
-               name:        "OR",
-               argLen:      2,
-               commutative: true,
-               asm:         arm64.AORR,
+               name:   "TSTshiftLLreg",
+               argLen: 3,
+               asm:    arm.ATST,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
-                               {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
-                       },
-                       outputs: []outputInfo{
-                               {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
+                               {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+                               {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+                               {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
                        },
                },
        },
        {
-               name:    "ORconst",
-               auxType: auxInt64,
-               argLen:  1,
-               asm:     arm64.AORR,
+               name:   "TSTshiftRLreg",
+               argLen: 3,
+               asm:    arm.ATST,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
-                       },
-                       outputs: []outputInfo{
-                               {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
+                               {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+                               {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+                               {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
                        },
                },
        },
        {
-               name:        "XOR",
-               argLen:      2,
-               commutative: true,
-               asm:         arm64.AEOR,
+               name:   "TSTshiftRAreg",
+               argLen: 3,
+               asm:    arm.ATST,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
-                               {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
-                       },
-                       outputs: []outputInfo{
-                               {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
+                               {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+                               {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+                               {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
                        },
                },
        },
        {
-               name:    "XORconst",
-               auxType: auxInt64,
-               argLen:  1,
-               asm:     arm64.AEOR,
+               name:   "TEQshiftLLreg",
+               argLen: 3,
+               asm:    arm.ATEQ,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
-                       },
-                       outputs: []outputInfo{
-                               {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
+                               {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+                               {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+                               {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
                        },
                },
        },
        {
-               name:   "BIC",
-               argLen: 2,
-               asm:    arm64.ABIC,
+               name:   "TEQshiftRLreg",
+               argLen: 3,
+               asm:    arm.ATEQ,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
-                               {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
-                       },
-                       outputs: []outputInfo{
-                               {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
+                               {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+                               {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+                               {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
                        },
                },
        },
        {
-               name:   "EON",
-               argLen: 2,
-               asm:    arm64.AEON,
+               name:   "TEQshiftRAreg",
+               argLen: 3,
+               asm:    arm.ATEQ,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
-                               {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
-                       },
-                       outputs: []outputInfo{
-                               {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
+                               {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+                               {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+                               {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
                        },
                },
        },
        {
-               name:   "ORN",
-               argLen: 2,
-               asm:    arm64.AORN,
+               name:   "CMPF0",
+               argLen: 1,
+               asm:    arm.ACMPF,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
-                               {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
-                       },
-                       outputs: []outputInfo{
-                               {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
+                               {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
                        },
                },
        },
        {
-               name:   "MVN",
+               name:   "CMPD0",
                argLen: 1,
-               asm:    arm64.AMVN,
+               asm:    arm.ACMPD,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
-                       },
-                       outputs: []outputInfo{
-                               {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
+                               {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
                        },
                },
        },
        {
-               name:   "NEG",
-               argLen: 1,
-               asm:    arm64.ANEG,
+               name:              "MOVWconst",
+               auxType:           auxInt32,
+               argLen:            0,
+               rematerializeable: true,
+               asm:               arm.AMOVW,
                reg: regInfo{
-                       inputs: []inputInfo{
-                               {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
-                       },
                        outputs: []outputInfo{
-                               {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
+                               {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
                        },
                },
        },
        {
-               name:   "NEGSflags",
-               argLen: 1,
-               asm:    arm64.ANEGS,
+               name:              "MOVFconst",
+               auxType:           auxFloat64,
+               argLen:            0,
+               rematerializeable: true,
+               asm:               arm.AMOVF,
                reg: regInfo{
-                       inputs: []inputInfo{
-                               {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
-                       },
                        outputs: []outputInfo{
-                               {1, 0},
-                               {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
+                               {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
                        },
                },
        },
        {
-               name:   "NGCzerocarry",
-               argLen: 1,
-               asm:    arm64.ANGC,
+               name:              "MOVDconst",
+               auxType:           auxFloat64,
+               argLen:            0,
+               rematerializeable: true,
+               asm:               arm.AMOVD,
                reg: regInfo{
                        outputs: []outputInfo{
-                               {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
+                               {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
                        },
                },
        },
        {
-               name:   "FABSD",
-               argLen: 1,
-               asm:    arm64.AFABSD,
+               name:              "MOVWaddr",
+               auxType:           auxSymOff,
+               argLen:            1,
+               rematerializeable: true,
+               symEffect:         SymAddr,
+               asm:               arm.AMOVW,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {0, 4294975488}, // SP SB
                        },
                        outputs: []outputInfo{
-                               {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
                        },
                },
        },
        {
-               name:   "FNEGS",
-               argLen: 1,
-               asm:    arm64.AFNEGS,
+               name:           "MOVBload",
+               auxType:        auxSymOff,
+               argLen:         2,
+               faultOnNilArg0: true,
+               symEffect:      SymRead,
+               asm:            arm.AMOVB,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB
                        },
                        outputs: []outputInfo{
-                               {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
                        },
                },
        },
        {
-               name:   "FNEGD",
-               argLen: 1,
-               asm:    arm64.AFNEGD,
+               name:           "MOVBUload",
+               auxType:        auxSymOff,
+               argLen:         2,
+               faultOnNilArg0: true,
+               symEffect:      SymRead,
+               asm:            arm.AMOVBU,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB
                        },
                        outputs: []outputInfo{
-                               {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
                        },
                },
        },
        {
-               name:   "FSQRTD",
-               argLen: 1,
-               asm:    arm64.AFSQRTD,
+               name:           "MOVHload",
+               auxType:        auxSymOff,
+               argLen:         2,
+               faultOnNilArg0: true,
+               symEffect:      SymRead,
+               asm:            arm.AMOVH,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB
                        },
                        outputs: []outputInfo{
-                               {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
                        },
                },
        },
        {
-               name:   "FSQRTS",
-               argLen: 1,
-               asm:    arm64.AFSQRTS,
+               name:           "MOVHUload",
+               auxType:        auxSymOff,
+               argLen:         2,
+               faultOnNilArg0: true,
+               symEffect:      SymRead,
+               asm:            arm.AMOVHU,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB
                        },
                        outputs: []outputInfo{
-                               {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
                        },
                },
        },
        {
-               name:   "FMIND",
-               argLen: 2,
-               asm:    arm64.AFMIND,
+               name:           "MOVWload",
+               auxType:        auxSymOff,
+               argLen:         2,
+               faultOnNilArg0: true,
+               symEffect:      SymRead,
+               asm:            arm.AMOVW,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
-                               {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB
                        },
                        outputs: []outputInfo{
-                               {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
                        },
                },
        },
        {
-               name:   "FMINS",
-               argLen: 2,
-               asm:    arm64.AFMINS,
+               name:           "MOVFload",
+               auxType:        auxSymOff,
+               argLen:         2,
+               faultOnNilArg0: true,
+               symEffect:      SymRead,
+               asm:            arm.AMOVF,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
-                               {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB
                        },
                        outputs: []outputInfo{
-                               {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
                        },
                },
        },
        {
-               name:   "FMAXD",
-               argLen: 2,
-               asm:    arm64.AFMAXD,
+               name:           "MOVDload",
+               auxType:        auxSymOff,
+               argLen:         2,
+               faultOnNilArg0: true,
+               symEffect:      SymRead,
+               asm:            arm.AMOVD,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
-                               {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB
                        },
                        outputs: []outputInfo{
-                               {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
                        },
                },
        },
        {
-               name:   "FMAXS",
-               argLen: 2,
-               asm:    arm64.AFMAXS,
+               name:           "MOVBstore",
+               auxType:        auxSymOff,
+               argLen:         3,
+               faultOnNilArg0: true,
+               symEffect:      SymWrite,
+               asm:            arm.AMOVB,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
-                               {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
-                       },
-                       outputs: []outputInfo{
-                               {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {1, 22527},      // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
+                               {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB
                        },
                },
        },
        {
-               name:   "REV",
-               argLen: 1,
-               asm:    arm64.AREV,
+               name:           "MOVHstore",
+               auxType:        auxSymOff,
+               argLen:         3,
+               faultOnNilArg0: true,
+               symEffect:      SymWrite,
+               asm:            arm.AMOVH,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
-                       },
-                       outputs: []outputInfo{
-                               {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
+                               {1, 22527},      // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
+                               {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB
                        },
                },
        },
        {
-               name:   "REVW",
-               argLen: 1,
-               asm:    arm64.AREVW,
+               name:           "MOVWstore",
+               auxType:        auxSymOff,
+               argLen:         3,
+               faultOnNilArg0: true,
+               symEffect:      SymWrite,
+               asm:            arm.AMOVW,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
-                       },
-                       outputs: []outputInfo{
-                               {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
+                               {1, 22527},      // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
+                               {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB
                        },
                },
        },
        {
-               name:   "REV16",
-               argLen: 1,
-               asm:    arm64.AREV16,
+               name:           "MOVFstore",
+               auxType:        auxSymOff,
+               argLen:         3,
+               faultOnNilArg0: true,
+               symEffect:      SymWrite,
+               asm:            arm.AMOVF,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
-                       },
-                       outputs: []outputInfo{
-                               {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
+                               {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB
+                               {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
                        },
                },
        },
        {
-               name:   "REV16W",
-               argLen: 1,
-               asm:    arm64.AREV16W,
+               name:           "MOVDstore",
+               auxType:        auxSymOff,
+               argLen:         3,
+               faultOnNilArg0: true,
+               symEffect:      SymWrite,
+               asm:            arm.AMOVD,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
-                       },
-                       outputs: []outputInfo{
-                               {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
+                               {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB
+                               {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
                        },
                },
        },
        {
-               name:   "RBIT",
-               argLen: 1,
-               asm:    arm64.ARBIT,
+               name:   "MOVWloadidx",
+               argLen: 3,
+               asm:    arm.AMOVW,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
+                               {1, 22527},      // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
+                               {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB
                        },
                        outputs: []outputInfo{
-                               {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
+                               {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
                        },
                },
        },
        {
-               name:   "RBITW",
-               argLen: 1,
-               asm:    arm64.ARBITW,
+               name:    "MOVWloadshiftLL",
+               auxType: auxInt32,
+               argLen:  3,
+               asm:     arm.AMOVW,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
+                               {1, 22527},      // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
+                               {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB
                        },
                        outputs: []outputInfo{
-                               {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
+                               {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
                        },
                },
        },
        {
-               name:   "CLZ",
-               argLen: 1,
-               asm:    arm64.ACLZ,
+               name:    "MOVWloadshiftRL",
+               auxType: auxInt32,
+               argLen:  3,
+               asm:     arm.AMOVW,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
+                               {1, 22527},      // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
+                               {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB
                        },
                        outputs: []outputInfo{
-                               {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
+                               {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
                        },
                },
        },
        {
-               name:   "CLZW",
-               argLen: 1,
-               asm:    arm64.ACLZW,
+               name:    "MOVWloadshiftRA",
+               auxType: auxInt32,
+               argLen:  3,
+               asm:     arm.AMOVW,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
+                               {1, 22527},      // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
+                               {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB
                        },
                        outputs: []outputInfo{
-                               {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
+                               {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
                        },
                },
        },
        {
-               name:   "VCNT",
-               argLen: 1,
-               asm:    arm64.AVCNT,
+               name:   "MOVBUloadidx",
+               argLen: 3,
+               asm:    arm.AMOVBU,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {1, 22527},      // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
+                               {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB
                        },
                        outputs: []outputInfo{
-                               {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
                        },
                },
        },
        {
-               name:   "VUADDLV",
-               argLen: 1,
-               asm:    arm64.AVUADDLV,
+               name:   "MOVBloadidx",
+               argLen: 3,
+               asm:    arm.AMOVB,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {1, 22527},      // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
+                               {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB
                        },
                        outputs: []outputInfo{
-                               {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
                        },
                },
        },
        {
-               name:         "LoweredRound32F",
-               argLen:       1,
-               resultInArg0: true,
-               zeroWidth:    true,
+               name:   "MOVHUloadidx",
+               argLen: 3,
+               asm:    arm.AMOVHU,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {1, 22527},      // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
+                               {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB
                        },
                        outputs: []outputInfo{
-                               {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
                        },
                },
        },
        {
-               name:         "LoweredRound64F",
-               argLen:       1,
-               resultInArg0: true,
-               zeroWidth:    true,
+               name:   "MOVHloadidx",
+               argLen: 3,
+               asm:    arm.AMOVH,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {1, 22527},      // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
+                               {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB
                        },
                        outputs: []outputInfo{
-                               {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
                        },
                },
        },
        {
-               name:   "FMADDS",
-               argLen: 3,
-               asm:    arm64.AFMADDS,
+               name:   "MOVWstoreidx",
+               argLen: 4,
+               asm:    arm.AMOVW,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
-                               {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
-                               {2, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
-                       },
-                       outputs: []outputInfo{
-                               {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {1, 22527},      // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
+                               {2, 22527},      // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
+                               {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB
                        },
                },
        },
        {
-               name:   "FMADDD",
-               argLen: 3,
-               asm:    arm64.AFMADDD,
+               name:    "MOVWstoreshiftLL",
+               auxType: auxInt32,
+               argLen:  4,
+               asm:     arm.AMOVW,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
-                               {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
-                               {2, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
-                       },
-                       outputs: []outputInfo{
-                               {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {1, 22527},      // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
+                               {2, 22527},      // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
+                               {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB
                        },
                },
        },
        {
-               name:   "FNMADDS",
-               argLen: 3,
-               asm:    arm64.AFNMADDS,
+               name:    "MOVWstoreshiftRL",
+               auxType: auxInt32,
+               argLen:  4,
+               asm:     arm.AMOVW,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
-                               {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
-                               {2, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
-                       },
-                       outputs: []outputInfo{
-                               {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {1, 22527},      // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
+                               {2, 22527},      // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
+                               {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB
                        },
                },
        },
        {
-               name:   "FNMADDD",
-               argLen: 3,
-               asm:    arm64.AFNMADDD,
+               name:    "MOVWstoreshiftRA",
+               auxType: auxInt32,
+               argLen:  4,
+               asm:     arm.AMOVW,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
-                               {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
-                               {2, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
-                       },
-                       outputs: []outputInfo{
-                               {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {1, 22527},      // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
+                               {2, 22527},      // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
+                               {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB
                        },
                },
        },
        {
-               name:   "FMSUBS",
-               argLen: 3,
-               asm:    arm64.AFMSUBS,
+               name:   "MOVBstoreidx",
+               argLen: 4,
+               asm:    arm.AMOVB,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
-                               {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
-                               {2, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
-                       },
-                       outputs: []outputInfo{
-                               {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {1, 22527},      // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
+                               {2, 22527},      // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
+                               {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB
                        },
                },
        },
        {
-               name:   "FMSUBD",
-               argLen: 3,
-               asm:    arm64.AFMSUBD,
+               name:   "MOVHstoreidx",
+               argLen: 4,
+               asm:    arm.AMOVH,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
-                               {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
-                               {2, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
-                       },
-                       outputs: []outputInfo{
-                               {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {1, 22527},      // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
+                               {2, 22527},      // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
+                               {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB
                        },
                },
        },
        {
-               name:   "FNMSUBS",
-               argLen: 3,
-               asm:    arm64.AFNMSUBS,
+               name:   "MOVBreg",
+               argLen: 1,
+               asm:    arm.AMOVBS,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
-                               {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
-                               {2, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
                        },
                        outputs: []outputInfo{
-                               {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
                        },
                },
        },
        {
-               name:   "FNMSUBD",
-               argLen: 3,
-               asm:    arm64.AFNMSUBD,
+               name:   "MOVBUreg",
+               argLen: 1,
+               asm:    arm.AMOVBU,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
-                               {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
-                               {2, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
                        },
                        outputs: []outputInfo{
-                               {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
                        },
                },
        },
        {
-               name:   "MADD",
-               argLen: 3,
-               asm:    arm64.AMADD,
+               name:   "MOVHreg",
+               argLen: 1,
+               asm:    arm.AMOVHS,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
-                               {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
-                               {2, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
+                               {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
                        },
                        outputs: []outputInfo{
-                               {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
+                               {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
                        },
                },
        },
        {
-               name:   "MADDW",
-               argLen: 3,
-               asm:    arm64.AMADDW,
+               name:   "MOVHUreg",
+               argLen: 1,
+               asm:    arm.AMOVHU,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
-                               {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
-                               {2, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
+                               {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
                        },
                        outputs: []outputInfo{
-                               {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
+                               {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
                        },
                },
        },
        {
-               name:   "MSUB",
-               argLen: 3,
-               asm:    arm64.AMSUB,
+               name:   "MOVWreg",
+               argLen: 1,
+               asm:    arm.AMOVW,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
-                               {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
-                               {2, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
+                               {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
                        },
                        outputs: []outputInfo{
-                               {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
+                               {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
                        },
                },
        },
        {
-               name:   "MSUBW",
-               argLen: 3,
-               asm:    arm64.AMSUBW,
+               name:         "MOVWnop",
+               argLen:       1,
+               resultInArg0: true,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
-                               {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
-                               {2, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
+                               {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
                        },
                        outputs: []outputInfo{
-                               {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
+                               {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
                        },
                },
        },
        {
-               name:   "SLL",
-               argLen: 2,
-               asm:    arm64.ALSL,
+               name:   "MOVWF",
+               argLen: 1,
+               asm:    arm.AMOVWF,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
-                               {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
+                               {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
                        },
+                       clobbers: 2147483648, // F15
                        outputs: []outputInfo{
-                               {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
+                               {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
                        },
                },
        },
        {
-               name:    "SLLconst",
-               auxType: auxInt64,
-               argLen:  1,
-               asm:     arm64.ALSL,
+               name:   "MOVWD",
+               argLen: 1,
+               asm:    arm.AMOVWD,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
+                               {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
                        },
+                       clobbers: 2147483648, // F15
                        outputs: []outputInfo{
-                               {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
+                               {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
                        },
                },
        },
        {
-               name:   "SRL",
-               argLen: 2,
-               asm:    arm64.ALSR,
+               name:   "MOVWUF",
+               argLen: 1,
+               asm:    arm.AMOVWF,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
-                               {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
+                               {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
                        },
+                       clobbers: 2147483648, // F15
                        outputs: []outputInfo{
-                               {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
+                               {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
                        },
                },
        },
        {
-               name:    "SRLconst",
-               auxType: auxInt64,
-               argLen:  1,
-               asm:     arm64.ALSR,
+               name:   "MOVWUD",
+               argLen: 1,
+               asm:    arm.AMOVWD,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
+                               {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
                        },
+                       clobbers: 2147483648, // F15
                        outputs: []outputInfo{
-                               {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
+                               {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
                        },
                },
        },
        {
-               name:   "SRA",
-               argLen: 2,
-               asm:    arm64.AASR,
+               name:   "MOVFW",
+               argLen: 1,
+               asm:    arm.AMOVFW,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
-                               {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
+                               {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
                        },
+                       clobbers: 2147483648, // F15
                        outputs: []outputInfo{
-                               {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
+                               {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
                        },
                },
        },
        {
-               name:    "SRAconst",
-               auxType: auxInt64,
-               argLen:  1,
-               asm:     arm64.AASR,
+               name:   "MOVDW",
+               argLen: 1,
+               asm:    arm.AMOVDW,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
+                               {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
                        },
+                       clobbers: 2147483648, // F15
                        outputs: []outputInfo{
-                               {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
+                               {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
                        },
                },
        },
        {
-               name:   "ROR",
-               argLen: 2,
-               asm:    arm64.AROR,
+               name:   "MOVFWU",
+               argLen: 1,
+               asm:    arm.AMOVFW,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
-                               {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
+                               {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
                        },
+                       clobbers: 2147483648, // F15
                        outputs: []outputInfo{
-                               {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
+                               {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
                        },
                },
        },
        {
-               name:   "RORW",
-               argLen: 2,
-               asm:    arm64.ARORW,
+               name:   "MOVDWU",
+               argLen: 1,
+               asm:    arm.AMOVDW,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
-                               {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
+                               {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
                        },
+                       clobbers: 2147483648, // F15
                        outputs: []outputInfo{
-                               {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
+                               {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
                        },
                },
        },
        {
-               name:    "RORconst",
-               auxType: auxInt64,
-               argLen:  1,
-               asm:     arm64.AROR,
+               name:   "MOVFD",
+               argLen: 1,
+               asm:    arm.AMOVFD,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
+                               {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
                        },
                        outputs: []outputInfo{
-                               {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
+                               {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
                        },
                },
        },
        {
-               name:    "RORWconst",
-               auxType: auxInt64,
-               argLen:  1,
-               asm:     arm64.ARORW,
+               name:   "MOVDF",
+               argLen: 1,
+               asm:    arm.AMOVDF,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
+                               {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
                        },
                        outputs: []outputInfo{
-                               {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
+                               {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
                        },
                },
        },
        {
-               name:    "EXTRconst",
-               auxType: auxInt64,
-               argLen:  2,
-               asm:     arm64.AEXTR,
+               name:         "CMOVWHSconst",
+               auxType:      auxInt32,
+               argLen:       2,
+               resultInArg0: true,
+               asm:          arm.AMOVW,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
-                               {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
+                               {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
                        },
                        outputs: []outputInfo{
-                               {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
+                               {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
                        },
                },
        },
        {
-               name:    "EXTRWconst",
-               auxType: auxInt64,
-               argLen:  2,
-               asm:     arm64.AEXTRW,
+               name:         "CMOVWLSconst",
+               auxType:      auxInt32,
+               argLen:       2,
+               resultInArg0: true,
+               asm:          arm.AMOVW,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
-                               {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
+                               {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
                        },
                        outputs: []outputInfo{
-                               {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
+                               {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
                        },
                },
        },
        {
-               name:   "CMP",
-               argLen: 2,
-               asm:    arm64.ACMP,
+               name:   "SRAcond",
+               argLen: 3,
+               asm:    arm.ASRA,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
-                               {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
+                               {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+                               {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+                       },
+                       outputs: []outputInfo{
+                               {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
                        },
                },
        },
        {
-               name:    "CMPconst",
-               auxType: auxInt64,
-               argLen:  1,
-               asm:     arm64.ACMP,
+               name:         "CALLstatic",
+               auxType:      auxCallOff,
+               argLen:       1,
+               clobberFlags: true,
+               call:         true,
+               reg: regInfo{
+                       clobbers: 4294924287, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+               },
+       },
+       {
+               name:         "CALLtail",
+               auxType:      auxCallOff,
+               argLen:       1,
+               clobberFlags: true,
+               call:         true,
+               tailCall:     true,
+               reg: regInfo{
+                       clobbers: 4294924287, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+               },
+       },
+       {
+               name:         "CALLclosure",
+               auxType:      auxCallOff,
+               argLen:       3,
+               clobberFlags: true,
+               call:         true,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
+                               {1, 128},   // R7
+                               {0, 29695}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 SP R14
                        },
+                       clobbers: 4294924287, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
                },
        },
        {
-               name:   "CMPW",
-               argLen: 2,
-               asm:    arm64.ACMPW,
+               name:         "CALLinter",
+               auxType:      auxCallOff,
+               argLen:       2,
+               clobberFlags: true,
+               call:         true,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
-                               {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
+                               {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
                        },
+                       clobbers: 4294924287, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
                },
        },
        {
-               name:    "CMPWconst",
-               auxType: auxInt32,
-               argLen:  1,
-               asm:     arm64.ACMPW,
+               name:           "LoweredNilCheck",
+               argLen:         2,
+               nilCheck:       true,
+               faultOnNilArg0: true,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
+                               {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
                        },
                },
        },
        {
-               name:        "CMN",
-               argLen:      2,
-               commutative: true,
-               asm:         arm64.ACMN,
+               name:   "Equal",
+               argLen: 1,
                reg: regInfo{
-                       inputs: []inputInfo{
-                               {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
-                               {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
+                       outputs: []outputInfo{
+                               {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
                        },
                },
        },
        {
-               name:    "CMNconst",
-               auxType: auxInt64,
-               argLen:  1,
-               asm:     arm64.ACMN,
+               name:   "NotEqual",
+               argLen: 1,
                reg: regInfo{
-                       inputs: []inputInfo{
-                               {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
+                       outputs: []outputInfo{
+                               {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
                        },
                },
        },
        {
-               name:        "CMNW",
-               argLen:      2,
-               commutative: true,
-               asm:         arm64.ACMNW,
+               name:   "LessThan",
+               argLen: 1,
                reg: regInfo{
-                       inputs: []inputInfo{
-                               {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
-                               {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
+                       outputs: []outputInfo{
+                               {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
                        },
                },
        },
        {
-               name:    "CMNWconst",
-               auxType: auxInt32,
-               argLen:  1,
-               asm:     arm64.ACMNW,
+               name:   "LessEqual",
+               argLen: 1,
                reg: regInfo{
-                       inputs: []inputInfo{
-                               {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
+                       outputs: []outputInfo{
+                               {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
                        },
                },
        },
        {
-               name:        "TST",
-               argLen:      2,
-               commutative: true,
-               asm:         arm64.ATST,
+               name:   "GreaterThan",
+               argLen: 1,
                reg: regInfo{
-                       inputs: []inputInfo{
-                               {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
-                               {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
+                       outputs: []outputInfo{
+                               {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
                        },
                },
        },
        {
-               name:    "TSTconst",
-               auxType: auxInt64,
-               argLen:  1,
-               asm:     arm64.ATST,
+               name:   "GreaterEqual",
+               argLen: 1,
                reg: regInfo{
-                       inputs: []inputInfo{
-                               {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
+                       outputs: []outputInfo{
+                               {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
                        },
                },
        },
        {
-               name:        "TSTW",
-               argLen:      2,
-               commutative: true,
-               asm:         arm64.ATSTW,
+               name:   "LessThanU",
+               argLen: 1,
                reg: regInfo{
-                       inputs: []inputInfo{
-                               {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
-                               {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
+                       outputs: []outputInfo{
+                               {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
                        },
                },
        },
        {
-               name:    "TSTWconst",
-               auxType: auxInt32,
-               argLen:  1,
-               asm:     arm64.ATSTW,
+               name:   "LessEqualU",
+               argLen: 1,
                reg: regInfo{
-                       inputs: []inputInfo{
-                               {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
+                       outputs: []outputInfo{
+                               {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
                        },
                },
        },
        {
-               name:   "FCMPS",
-               argLen: 2,
-               asm:    arm64.AFCMPS,
+               name:   "GreaterThanU",
+               argLen: 1,
                reg: regInfo{
-                       inputs: []inputInfo{
-                               {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
-                               {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                       outputs: []outputInfo{
+                               {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
                        },
                },
        },
        {
-               name:   "FCMPD",
-               argLen: 2,
-               asm:    arm64.AFCMPD,
+               name:   "GreaterEqualU",
+               argLen: 1,
+               reg: regInfo{
+                       outputs: []outputInfo{
+                               {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+                       },
+               },
+       },
+       {
+               name:           "DUFFZERO",
+               auxType:        auxInt64,
+               argLen:         3,
+               faultOnNilArg0: true,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
-                               {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {0, 2}, // R1
+                               {1, 1}, // R0
                        },
+                       clobbers: 20482, // R1 R12 R14
                },
        },
        {
-               name:   "FCMPS0",
-               argLen: 1,
-               asm:    arm64.AFCMPS,
+               name:           "DUFFCOPY",
+               auxType:        auxInt64,
+               argLen:         3,
+               faultOnNilArg0: true,
+               faultOnNilArg1: true,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {0, 4}, // R2
+                               {1, 2}, // R1
                        },
+                       clobbers: 20487, // R0 R1 R2 R12 R14
                },
        },
        {
-               name:   "FCMPD0",
-               argLen: 1,
-               asm:    arm64.AFCMPD,
+               name:           "LoweredZero",
+               auxType:        auxInt64,
+               argLen:         4,
+               clobberFlags:   true,
+               faultOnNilArg0: true,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {0, 2},     // R1
+                               {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+                               {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
                        },
+                       clobbers: 2, // R1
                },
        },
        {
-               name:    "MVNshiftLL",
-               auxType: auxInt64,
-               argLen:  1,
-               asm:     arm64.AMVN,
+               name:           "LoweredMove",
+               auxType:        auxInt64,
+               argLen:         4,
+               clobberFlags:   true,
+               faultOnNilArg0: true,
+               faultOnNilArg1: true,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
+                               {0, 4},     // R2
+                               {1, 2},     // R1
+                               {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
                        },
+                       clobbers: 6, // R1 R2
+               },
+       },
+       {
+               name:      "LoweredGetClosurePtr",
+               argLen:    0,
+               zeroWidth: true,
+               reg: regInfo{
                        outputs: []outputInfo{
-                               {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
+                               {0, 128}, // R7
                        },
                },
        },
        {
-               name:    "MVNshiftRL",
-               auxType: auxInt64,
-               argLen:  1,
-               asm:     arm64.AMVN,
+               name:              "LoweredGetCallerSP",
+               argLen:            1,
+               rematerializeable: true,
                reg: regInfo{
-                       inputs: []inputInfo{
-                               {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
+                       outputs: []outputInfo{
+                               {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
                        },
+               },
+       },
+       {
+               name:              "LoweredGetCallerPC",
+               argLen:            0,
+               rematerializeable: true,
+               reg: regInfo{
                        outputs: []outputInfo{
-                               {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
+                               {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
                        },
                },
        },
        {
-               name:    "MVNshiftRA",
+               name:    "LoweredPanicBoundsA",
                auxType: auxInt64,
-               argLen:  1,
-               asm:     arm64.AMVN,
+               argLen:  3,
+               call:    true,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
-                       },
-                       outputs: []outputInfo{
-                               {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
+                               {0, 4}, // R2
+                               {1, 8}, // R3
                        },
                },
        },
        {
-               name:    "MVNshiftRO",
+               name:    "LoweredPanicBoundsB",
                auxType: auxInt64,
-               argLen:  1,
-               asm:     arm64.AMVN,
+               argLen:  3,
+               call:    true,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
-                       },
-                       outputs: []outputInfo{
-                               {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
+                               {0, 2}, // R1
+                               {1, 4}, // R2
                        },
                },
        },
        {
-               name:    "NEGshiftLL",
+               name:    "LoweredPanicBoundsC",
                auxType: auxInt64,
-               argLen:  1,
-               asm:     arm64.ANEG,
+               argLen:  3,
+               call:    true,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
-                       },
-                       outputs: []outputInfo{
-                               {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
+                               {0, 1}, // R0
+                               {1, 2}, // R1
                        },
                },
        },
        {
-               name:    "NEGshiftRL",
+               name:    "LoweredPanicExtendA",
                auxType: auxInt64,
-               argLen:  1,
-               asm:     arm64.ANEG,
+               argLen:  4,
+               call:    true,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
-                       },
-                       outputs: []outputInfo{
-                               {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
+                               {0, 16}, // R4
+                               {1, 4},  // R2
+                               {2, 8},  // R3
                        },
                },
        },
        {
-               name:    "NEGshiftRA",
+               name:    "LoweredPanicExtendB",
                auxType: auxInt64,
-               argLen:  1,
-               asm:     arm64.ANEG,
+               argLen:  4,
+               call:    true,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
-                       },
-                       outputs: []outputInfo{
-                               {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
+                               {0, 16}, // R4
+                               {1, 2},  // R1
+                               {2, 4},  // R2
                        },
                },
        },
        {
-               name:    "ADDshiftLL",
+               name:    "LoweredPanicExtendC",
                auxType: auxInt64,
-               argLen:  2,
-               asm:     arm64.AADD,
+               argLen:  4,
+               call:    true,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
-                               {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
+                               {0, 16}, // R4
+                               {1, 1},  // R0
+                               {2, 2},  // R1
                        },
+               },
+       },
+       {
+               name:    "FlagConstant",
+               auxType: auxFlagConstant,
+               argLen:  0,
+               reg:     regInfo{},
+       },
+       {
+               name:   "InvertFlags",
+               argLen: 1,
+               reg:    regInfo{},
+       },
+       {
+               name:         "LoweredWB",
+               auxType:      auxInt64,
+               argLen:       1,
+               clobberFlags: true,
+               reg: regInfo{
+                       clobbers: 4294922240, // R12 R14 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
                        outputs: []outputInfo{
-                               {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
+                               {0, 256}, // R8
                        },
                },
        },
+
        {
-               name:    "ADDshiftRL",
-               auxType: auxInt64,
-               argLen:  2,
-               asm:     arm64.AADD,
+               name:        "ADCSflags",
+               argLen:      3,
+               commutative: true,
+               asm:         arm64.AADCS,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
-                               {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
+                               {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
+                               {1, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
                        },
                        outputs: []outputInfo{
+                               {1, 0},
                                {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
                        },
                },
        },
        {
-               name:    "ADDshiftRA",
-               auxType: auxInt64,
-               argLen:  2,
-               asm:     arm64.AADD,
+               name:   "ADCzerocarry",
+               argLen: 1,
+               asm:    arm64.AADC,
                reg: regInfo{
-                       inputs: []inputInfo{
-                               {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
-                               {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
-                       },
                        outputs: []outputInfo{
                                {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
                        },
                },
        },
        {
-               name:    "SUBshiftLL",
-               auxType: auxInt64,
-               argLen:  2,
-               asm:     arm64.ASUB,
+               name:        "ADD",
+               argLen:      2,
+               commutative: true,
+               asm:         arm64.AADD,
                reg: regInfo{
                        inputs: []inputInfo{
                                {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
@@ -33909,14 +35946,13 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:    "SUBshiftRL",
+               name:    "ADDconst",
                auxType: auxInt64,
-               argLen:  2,
-               asm:     arm64.ASUB,
+               argLen:  1,
+               asm:     arm64.AADD,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
-                               {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
+                               {0, 1476395007}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP
                        },
                        outputs: []outputInfo{
                                {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
@@ -33924,40 +35960,40 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:    "SUBshiftRA",
+               name:    "ADDSconstflags",
                auxType: auxInt64,
-               argLen:  2,
-               asm:     arm64.ASUB,
+               argLen:  1,
+               asm:     arm64.AADDS,
                reg: regInfo{
                        inputs: []inputInfo{
                                {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
-                               {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
                        },
                        outputs: []outputInfo{
+                               {1, 0},
                                {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
                        },
                },
        },
        {
-               name:    "ANDshiftLL",
-               auxType: auxInt64,
-               argLen:  2,
-               asm:     arm64.AAND,
+               name:        "ADDSflags",
+               argLen:      2,
+               commutative: true,
+               asm:         arm64.AADDS,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
-                               {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
+                               {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
+                               {1, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
                        },
                        outputs: []outputInfo{
+                               {1, 0},
                                {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
                        },
                },
        },
        {
-               name:    "ANDshiftRL",
-               auxType: auxInt64,
-               argLen:  2,
-               asm:     arm64.AAND,
+               name:   "SUB",
+               argLen: 2,
+               asm:    arm64.ASUB,
                reg: regInfo{
                        inputs: []inputInfo{
                                {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
@@ -33969,14 +36005,13 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:    "ANDshiftRA",
+               name:    "SUBconst",
                auxType: auxInt64,
-               argLen:  2,
-               asm:     arm64.AAND,
+               argLen:  1,
+               asm:     arm64.ASUB,
                reg: regInfo{
                        inputs: []inputInfo{
                                {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
-                               {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
                        },
                        outputs: []outputInfo{
                                {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
@@ -33984,40 +36019,40 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:    "ANDshiftRO",
-               auxType: auxInt64,
-               argLen:  2,
-               asm:     arm64.AAND,
+               name:   "SBCSflags",
+               argLen: 3,
+               asm:    arm64.ASBCS,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
-                               {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
+                               {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
+                               {1, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
                        },
                        outputs: []outputInfo{
+                               {1, 0},
                                {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
                        },
                },
        },
        {
-               name:    "ORshiftLL",
-               auxType: auxInt64,
-               argLen:  2,
-               asm:     arm64.AORR,
+               name:   "SUBSflags",
+               argLen: 2,
+               asm:    arm64.ASUBS,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
-                               {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
+                               {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
+                               {1, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
                        },
                        outputs: []outputInfo{
+                               {1, 0},
                                {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
                        },
                },
        },
        {
-               name:    "ORshiftRL",
-               auxType: auxInt64,
-               argLen:  2,
-               asm:     arm64.AORR,
+               name:        "MUL",
+               argLen:      2,
+               commutative: true,
+               asm:         arm64.AMUL,
                reg: regInfo{
                        inputs: []inputInfo{
                                {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
@@ -34029,10 +36064,10 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:    "ORshiftRA",
-               auxType: auxInt64,
-               argLen:  2,
-               asm:     arm64.AORR,
+               name:        "MULW",
+               argLen:      2,
+               commutative: true,
+               asm:         arm64.AMULW,
                reg: regInfo{
                        inputs: []inputInfo{
                                {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
@@ -34044,10 +36079,10 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:    "ORshiftRO",
-               auxType: auxInt64,
-               argLen:  2,
-               asm:     arm64.AORR,
+               name:        "MNEG",
+               argLen:      2,
+               commutative: true,
+               asm:         arm64.AMNEG,
                reg: regInfo{
                        inputs: []inputInfo{
                                {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
@@ -34059,10 +36094,10 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:    "XORshiftLL",
-               auxType: auxInt64,
-               argLen:  2,
-               asm:     arm64.AEOR,
+               name:        "MNEGW",
+               argLen:      2,
+               commutative: true,
+               asm:         arm64.AMNEGW,
                reg: regInfo{
                        inputs: []inputInfo{
                                {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
@@ -34074,10 +36109,10 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:    "XORshiftRL",
-               auxType: auxInt64,
-               argLen:  2,
-               asm:     arm64.AEOR,
+               name:        "MULH",
+               argLen:      2,
+               commutative: true,
+               asm:         arm64.ASMULH,
                reg: regInfo{
                        inputs: []inputInfo{
                                {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
@@ -34089,10 +36124,10 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:    "XORshiftRA",
-               auxType: auxInt64,
-               argLen:  2,
-               asm:     arm64.AEOR,
+               name:        "UMULH",
+               argLen:      2,
+               commutative: true,
+               asm:         arm64.AUMULH,
                reg: regInfo{
                        inputs: []inputInfo{
                                {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
@@ -34104,10 +36139,10 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:    "XORshiftRO",
-               auxType: auxInt64,
-               argLen:  2,
-               asm:     arm64.AEOR,
+               name:        "MULL",
+               argLen:      2,
+               commutative: true,
+               asm:         arm64.ASMULL,
                reg: regInfo{
                        inputs: []inputInfo{
                                {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
@@ -34119,10 +36154,10 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:    "BICshiftLL",
-               auxType: auxInt64,
-               argLen:  2,
-               asm:     arm64.ABIC,
+               name:        "UMULL",
+               argLen:      2,
+               commutative: true,
+               asm:         arm64.AUMULL,
                reg: regInfo{
                        inputs: []inputInfo{
                                {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
@@ -34134,10 +36169,9 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:    "BICshiftRL",
-               auxType: auxInt64,
-               argLen:  2,
-               asm:     arm64.ABIC,
+               name:   "DIV",
+               argLen: 2,
+               asm:    arm64.ASDIV,
                reg: regInfo{
                        inputs: []inputInfo{
                                {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
@@ -34149,10 +36183,9 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:    "BICshiftRA",
-               auxType: auxInt64,
-               argLen:  2,
-               asm:     arm64.ABIC,
+               name:   "UDIV",
+               argLen: 2,
+               asm:    arm64.AUDIV,
                reg: regInfo{
                        inputs: []inputInfo{
                                {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
@@ -34164,10 +36197,9 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:    "BICshiftRO",
-               auxType: auxInt64,
-               argLen:  2,
-               asm:     arm64.ABIC,
+               name:   "DIVW",
+               argLen: 2,
+               asm:    arm64.ASDIVW,
                reg: regInfo{
                        inputs: []inputInfo{
                                {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
@@ -34179,10 +36211,9 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:    "EONshiftLL",
-               auxType: auxInt64,
-               argLen:  2,
-               asm:     arm64.AEON,
+               name:   "UDIVW",
+               argLen: 2,
+               asm:    arm64.AUDIVW,
                reg: regInfo{
                        inputs: []inputInfo{
                                {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
@@ -34194,10 +36225,9 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:    "EONshiftRL",
-               auxType: auxInt64,
-               argLen:  2,
-               asm:     arm64.AEON,
+               name:   "MOD",
+               argLen: 2,
+               asm:    arm64.AREM,
                reg: regInfo{
                        inputs: []inputInfo{
                                {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
@@ -34209,10 +36239,9 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:    "EONshiftRA",
-               auxType: auxInt64,
-               argLen:  2,
-               asm:     arm64.AEON,
+               name:   "UMOD",
+               argLen: 2,
+               asm:    arm64.AUREM,
                reg: regInfo{
                        inputs: []inputInfo{
                                {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
@@ -34224,10 +36253,9 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:    "EONshiftRO",
-               auxType: auxInt64,
-               argLen:  2,
-               asm:     arm64.AEON,
+               name:   "MODW",
+               argLen: 2,
+               asm:    arm64.AREMW,
                reg: regInfo{
                        inputs: []inputInfo{
                                {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
@@ -34239,10 +36267,9 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:    "ORNshiftLL",
-               auxType: auxInt64,
-               argLen:  2,
-               asm:     arm64.AORN,
+               name:   "UMODW",
+               argLen: 2,
+               asm:    arm64.AUREMW,
                reg: regInfo{
                        inputs: []inputInfo{
                                {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
@@ -34254,180 +36281,203 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:    "ORNshiftRL",
-               auxType: auxInt64,
-               argLen:  2,
-               asm:     arm64.AORN,
+               name:        "FADDS",
+               argLen:      2,
+               commutative: true,
+               asm:         arm64.AFADDS,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
-                               {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
+                               {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
                        },
                        outputs: []outputInfo{
-                               {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
+                               {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
                        },
                },
        },
        {
-               name:    "ORNshiftRA",
-               auxType: auxInt64,
-               argLen:  2,
-               asm:     arm64.AORN,
+               name:        "FADDD",
+               argLen:      2,
+               commutative: true,
+               asm:         arm64.AFADDD,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
-                               {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
+                               {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
                        },
                        outputs: []outputInfo{
-                               {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
+                               {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
                        },
                },
        },
        {
-               name:    "ORNshiftRO",
-               auxType: auxInt64,
-               argLen:  2,
-               asm:     arm64.AORN,
+               name:   "FSUBS",
+               argLen: 2,
+               asm:    arm64.AFSUBS,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
-                               {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
+                               {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
                        },
                        outputs: []outputInfo{
-                               {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
+                               {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
                        },
                },
        },
        {
-               name:    "CMPshiftLL",
-               auxType: auxInt64,
-               argLen:  2,
-               asm:     arm64.ACMP,
+               name:   "FSUBD",
+               argLen: 2,
+               asm:    arm64.AFSUBD,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
-                               {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
+                               {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                       },
+                       outputs: []outputInfo{
+                               {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
                        },
                },
        },
        {
-               name:    "CMPshiftRL",
-               auxType: auxInt64,
-               argLen:  2,
-               asm:     arm64.ACMP,
+               name:        "FMULS",
+               argLen:      2,
+               commutative: true,
+               asm:         arm64.AFMULS,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
-                               {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
+                               {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                       },
+                       outputs: []outputInfo{
+                               {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
                        },
                },
        },
        {
-               name:    "CMPshiftRA",
-               auxType: auxInt64,
-               argLen:  2,
-               asm:     arm64.ACMP,
+               name:        "FMULD",
+               argLen:      2,
+               commutative: true,
+               asm:         arm64.AFMULD,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
-                               {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
+                               {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                       },
+                       outputs: []outputInfo{
+                               {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
                        },
                },
        },
        {
-               name:    "CMNshiftLL",
-               auxType: auxInt64,
-               argLen:  2,
-               asm:     arm64.ACMN,
+               name:        "FNMULS",
+               argLen:      2,
+               commutative: true,
+               asm:         arm64.AFNMULS,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
-                               {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
+                               {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                       },
+                       outputs: []outputInfo{
+                               {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
                        },
                },
        },
        {
-               name:    "CMNshiftRL",
-               auxType: auxInt64,
-               argLen:  2,
-               asm:     arm64.ACMN,
+               name:        "FNMULD",
+               argLen:      2,
+               commutative: true,
+               asm:         arm64.AFNMULD,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
-                               {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
+                               {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                       },
+                       outputs: []outputInfo{
+                               {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
                        },
                },
        },
        {
-               name:    "CMNshiftRA",
-               auxType: auxInt64,
-               argLen:  2,
-               asm:     arm64.ACMN,
+               name:   "FDIVS",
+               argLen: 2,
+               asm:    arm64.AFDIVS,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
-                               {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
+                               {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                       },
+                       outputs: []outputInfo{
+                               {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
                        },
                },
        },
        {
-               name:    "TSTshiftLL",
-               auxType: auxInt64,
-               argLen:  2,
-               asm:     arm64.ATST,
+               name:   "FDIVD",
+               argLen: 2,
+               asm:    arm64.AFDIVD,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
-                               {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
+                               {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                       },
+                       outputs: []outputInfo{
+                               {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
                        },
                },
        },
        {
-               name:    "TSTshiftRL",
-               auxType: auxInt64,
-               argLen:  2,
-               asm:     arm64.ATST,
+               name:        "AND",
+               argLen:      2,
+               commutative: true,
+               asm:         arm64.AAND,
                reg: regInfo{
                        inputs: []inputInfo{
                                {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
                                {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
                        },
+                       outputs: []outputInfo{
+                               {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
+                       },
                },
        },
        {
-               name:    "TSTshiftRA",
+               name:    "ANDconst",
                auxType: auxInt64,
-               argLen:  2,
-               asm:     arm64.ATST,
+               argLen:  1,
+               asm:     arm64.AAND,
                reg: regInfo{
                        inputs: []inputInfo{
                                {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
-                               {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
+                       },
+                       outputs: []outputInfo{
+                               {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
                        },
                },
        },
        {
-               name:    "TSTshiftRO",
-               auxType: auxInt64,
-               argLen:  2,
-               asm:     arm64.ATST,
+               name:        "OR",
+               argLen:      2,
+               commutative: true,
+               asm:         arm64.AORR,
                reg: regInfo{
                        inputs: []inputInfo{
                                {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
                                {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
                        },
+                       outputs: []outputInfo{
+                               {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
+                       },
                },
        },
        {
-               name:         "BFI",
-               auxType:      auxARM64BitField,
-               argLen:       2,
-               resultInArg0: true,
-               asm:          arm64.ABFI,
+               name:    "ORconst",
+               auxType: auxInt64,
+               argLen:  1,
+               asm:     arm64.AORR,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
-                               {1, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
+                               {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
                        },
                        outputs: []outputInfo{
                                {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
@@ -34435,15 +36485,14 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:         "BFXIL",
-               auxType:      auxARM64BitField,
-               argLen:       2,
-               resultInArg0: true,
-               asm:          arm64.ABFXIL,
+               name:        "XOR",
+               argLen:      2,
+               commutative: true,
+               asm:         arm64.AEOR,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
-                               {1, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
+                               {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
+                               {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
                        },
                        outputs: []outputInfo{
                                {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
@@ -34451,10 +36500,10 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:    "SBFIZ",
-               auxType: auxARM64BitField,
+               name:    "XORconst",
+               auxType: auxInt64,
                argLen:  1,
-               asm:     arm64.ASBFIZ,
+               asm:     arm64.AEOR,
                reg: regInfo{
                        inputs: []inputInfo{
                                {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
@@ -34465,13 +36514,13 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:    "SBFX",
-               auxType: auxARM64BitField,
-               argLen:  1,
-               asm:     arm64.ASBFX,
+               name:   "BIC",
+               argLen: 2,
+               asm:    arm64.ABIC,
                reg: regInfo{
                        inputs: []inputInfo{
                                {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
+                               {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
                        },
                        outputs: []outputInfo{
                                {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
@@ -34479,13 +36528,13 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:    "UBFIZ",
-               auxType: auxARM64BitField,
-               argLen:  1,
-               asm:     arm64.AUBFIZ,
+               name:   "EON",
+               argLen: 2,
+               asm:    arm64.AEON,
                reg: regInfo{
                        inputs: []inputInfo{
                                {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
+                               {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
                        },
                        outputs: []outputInfo{
                                {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
@@ -34493,13 +36542,13 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:    "UBFX",
-               auxType: auxARM64BitField,
-               argLen:  1,
-               asm:     arm64.AUBFX,
+               name:   "ORN",
+               argLen: 2,
+               asm:    arm64.AORN,
                reg: regInfo{
                        inputs: []inputInfo{
                                {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
+                               {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
                        },
                        outputs: []outputInfo{
                                {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
@@ -34507,179 +36556,142 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:              "MOVDconst",
-               auxType:           auxInt64,
-               argLen:            0,
-               rematerializeable: true,
-               asm:               arm64.AMOVD,
+               name:   "MVN",
+               argLen: 1,
+               asm:    arm64.AMVN,
                reg: regInfo{
+                       inputs: []inputInfo{
+                               {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
+                       },
                        outputs: []outputInfo{
                                {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
                        },
                },
        },
        {
-               name:              "FMOVSconst",
-               auxType:           auxFloat64,
-               argLen:            0,
-               rematerializeable: true,
-               asm:               arm64.AFMOVS,
+               name:   "NEG",
+               argLen: 1,
+               asm:    arm64.ANEG,
                reg: regInfo{
-                       outputs: []outputInfo{
-                               {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                       inputs: []inputInfo{
+                               {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
                        },
-               },
-       },
-       {
-               name:              "FMOVDconst",
-               auxType:           auxFloat64,
-               argLen:            0,
-               rematerializeable: true,
-               asm:               arm64.AFMOVD,
-               reg: regInfo{
                        outputs: []outputInfo{
-                               {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
                        },
                },
        },
        {
-               name:              "MOVDaddr",
-               auxType:           auxSymOff,
-               argLen:            1,
-               rematerializeable: true,
-               symEffect:         SymAddr,
-               asm:               arm64.AMOVD,
+               name:   "NEGSflags",
+               argLen: 1,
+               asm:    arm64.ANEGS,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 9223372037928517632}, // SP SB
+                               {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
                        },
                        outputs: []outputInfo{
+                               {1, 0},
                                {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
                        },
                },
        },
        {
-               name:           "MOVBload",
-               auxType:        auxSymOff,
-               argLen:         2,
-               faultOnNilArg0: true,
-               symEffect:      SymRead,
-               asm:            arm64.AMOVB,
+               name:   "NGCzerocarry",
+               argLen: 1,
+               asm:    arm64.ANGC,
                reg: regInfo{
-                       inputs: []inputInfo{
-                               {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
-                       },
                        outputs: []outputInfo{
                                {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
                        },
                },
        },
        {
-               name:           "MOVBUload",
-               auxType:        auxSymOff,
-               argLen:         2,
-               faultOnNilArg0: true,
-               symEffect:      SymRead,
-               asm:            arm64.AMOVBU,
+               name:   "FABSD",
+               argLen: 1,
+               asm:    arm64.AFABSD,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
+                               {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
                        },
                        outputs: []outputInfo{
-                               {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
+                               {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
                        },
                },
        },
        {
-               name:           "MOVHload",
-               auxType:        auxSymOff,
-               argLen:         2,
-               faultOnNilArg0: true,
-               symEffect:      SymRead,
-               asm:            arm64.AMOVH,
+               name:   "FNEGS",
+               argLen: 1,
+               asm:    arm64.AFNEGS,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
+                               {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
                        },
                        outputs: []outputInfo{
-                               {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
+                               {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
                        },
                },
        },
        {
-               name:           "MOVHUload",
-               auxType:        auxSymOff,
-               argLen:         2,
-               faultOnNilArg0: true,
-               symEffect:      SymRead,
-               asm:            arm64.AMOVHU,
+               name:   "FNEGD",
+               argLen: 1,
+               asm:    arm64.AFNEGD,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
+                               {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
                        },
                        outputs: []outputInfo{
-                               {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
+                               {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
                        },
                },
        },
        {
-               name:           "MOVWload",
-               auxType:        auxSymOff,
-               argLen:         2,
-               faultOnNilArg0: true,
-               symEffect:      SymRead,
-               asm:            arm64.AMOVW,
+               name:   "FSQRTD",
+               argLen: 1,
+               asm:    arm64.AFSQRTD,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
+                               {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
                        },
                        outputs: []outputInfo{
-                               {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
+                               {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
                        },
                },
        },
        {
-               name:           "MOVWUload",
-               auxType:        auxSymOff,
-               argLen:         2,
-               faultOnNilArg0: true,
-               symEffect:      SymRead,
-               asm:            arm64.AMOVWU,
+               name:   "FSQRTS",
+               argLen: 1,
+               asm:    arm64.AFSQRTS,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
+                               {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
                        },
                        outputs: []outputInfo{
-                               {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
+                               {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
                        },
                },
        },
        {
-               name:           "MOVDload",
-               auxType:        auxSymOff,
-               argLen:         2,
-               faultOnNilArg0: true,
-               symEffect:      SymRead,
-               asm:            arm64.AMOVD,
+               name:   "FMIND",
+               argLen: 2,
+               asm:    arm64.AFMIND,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
+                               {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
                        },
                        outputs: []outputInfo{
-                               {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
+                               {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
                        },
                },
        },
        {
-               name:           "FMOVSload",
-               auxType:        auxSymOff,
-               argLen:         2,
-               faultOnNilArg0: true,
-               symEffect:      SymRead,
-               asm:            arm64.AFMOVS,
+               name:   "FMINS",
+               argLen: 2,
+               asm:    arm64.AFMINS,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
+                               {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
                        },
                        outputs: []outputInfo{
                                {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
@@ -34687,15 +36699,13 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:           "FMOVDload",
-               auxType:        auxSymOff,
-               argLen:         2,
-               faultOnNilArg0: true,
-               symEffect:      SymRead,
-               asm:            arm64.AFMOVD,
+               name:   "FMAXD",
+               argLen: 2,
+               asm:    arm64.AFMAXD,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
+                               {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
                        },
                        outputs: []outputInfo{
                                {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
@@ -34703,98 +36713,78 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:           "LDP",
-               auxType:        auxSymOff,
-               argLen:         2,
-               faultOnNilArg0: true,
-               symEffect:      SymRead,
-               asm:            arm64.ALDP,
+               name:   "FMAXS",
+               argLen: 2,
+               asm:    arm64.AFMAXS,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
+                               {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
                        },
                        outputs: []outputInfo{
-                               {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
-                               {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
+                               {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
                        },
                },
        },
        {
-               name:           "LDPW",
-               auxType:        auxSymOff,
-               argLen:         2,
-               faultOnNilArg0: true,
-               symEffect:      SymRead,
-               asm:            arm64.ALDPW,
+               name:   "REV",
+               argLen: 1,
+               asm:    arm64.AREV,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
+                               {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
                        },
                        outputs: []outputInfo{
-                               {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
-                               {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
+                               {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
                        },
                },
        },
        {
-               name:           "LDPSW",
-               auxType:        auxSymOff,
-               argLen:         2,
-               faultOnNilArg0: true,
-               symEffect:      SymRead,
-               asm:            arm64.ALDPSW,
+               name:   "REVW",
+               argLen: 1,
+               asm:    arm64.AREVW,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
+                               {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
                        },
                        outputs: []outputInfo{
-                               {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
-                               {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
+                               {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
                        },
                },
        },
        {
-               name:           "FLDPD",
-               auxType:        auxSymOff,
-               argLen:         2,
-               faultOnNilArg0: true,
-               symEffect:      SymRead,
-               asm:            arm64.AFLDPD,
+               name:   "REV16",
+               argLen: 1,
+               asm:    arm64.AREV16,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
+                               {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
                        },
                        outputs: []outputInfo{
-                               {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
-                               {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
                        },
                },
        },
        {
-               name:           "FLDPS",
-               auxType:        auxSymOff,
-               argLen:         2,
-               faultOnNilArg0: true,
-               symEffect:      SymRead,
-               asm:            arm64.AFLDPS,
+               name:   "REV16W",
+               argLen: 1,
+               asm:    arm64.AREV16W,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
+                               {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
                        },
                        outputs: []outputInfo{
-                               {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
-                               {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
                        },
                },
        },
        {
-               name:   "MOVDloadidx",
-               argLen: 3,
-               asm:    arm64.AMOVD,
+               name:   "RBIT",
+               argLen: 1,
+               asm:    arm64.ARBIT,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {1, 402653183},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
-                               {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
+                               {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
                        },
                        outputs: []outputInfo{
                                {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
@@ -34802,13 +36792,12 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:   "MOVWloadidx",
-               argLen: 3,
-               asm:    arm64.AMOVW,
+               name:   "RBITW",
+               argLen: 1,
+               asm:    arm64.ARBITW,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {1, 402653183},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
-                               {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
+                               {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
                        },
                        outputs: []outputInfo{
                                {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
@@ -34816,13 +36805,12 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:   "MOVWUloadidx",
-               argLen: 3,
-               asm:    arm64.AMOVWU,
+               name:   "CLZ",
+               argLen: 1,
+               asm:    arm64.ACLZ,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {1, 402653183},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
-                               {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
+                               {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
                        },
                        outputs: []outputInfo{
                                {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
@@ -34830,13 +36818,12 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:   "MOVHloadidx",
-               argLen: 3,
-               asm:    arm64.AMOVH,
+               name:   "CLZW",
+               argLen: 1,
+               asm:    arm64.ACLZW,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {1, 402653183},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
-                               {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
+                               {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
                        },
                        outputs: []outputInfo{
                                {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
@@ -34844,55 +36831,53 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:   "MOVHUloadidx",
-               argLen: 3,
-               asm:    arm64.AMOVHU,
+               name:   "VCNT",
+               argLen: 1,
+               asm:    arm64.AVCNT,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {1, 402653183},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
-                               {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
+                               {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
                        },
                        outputs: []outputInfo{
-                               {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
+                               {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
                        },
                },
        },
        {
-               name:   "MOVBloadidx",
-               argLen: 3,
-               asm:    arm64.AMOVB,
+               name:   "VUADDLV",
+               argLen: 1,
+               asm:    arm64.AVUADDLV,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {1, 402653183},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
-                               {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
+                               {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
                        },
                        outputs: []outputInfo{
-                               {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
+                               {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
                        },
                },
        },
        {
-               name:   "MOVBUloadidx",
-               argLen: 3,
-               asm:    arm64.AMOVBU,
+               name:         "LoweredRound32F",
+               argLen:       1,
+               resultInArg0: true,
+               zeroWidth:    true,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {1, 402653183},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
-                               {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
+                               {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
                        },
                        outputs: []outputInfo{
-                               {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
+                               {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
                        },
                },
        },
        {
-               name:   "FMOVSloadidx",
-               argLen: 3,
-               asm:    arm64.AFMOVS,
+               name:         "LoweredRound64F",
+               argLen:       1,
+               resultInArg0: true,
+               zeroWidth:    true,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {1, 402653183},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
-                               {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
+                               {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
                        },
                        outputs: []outputInfo{
                                {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
@@ -34900,13 +36885,14 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:   "FMOVDloadidx",
+               name:   "FMADDS",
                argLen: 3,
-               asm:    arm64.AFMOVD,
+               asm:    arm64.AFMADDS,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {1, 402653183},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
-                               {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
+                               {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {2, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
                        },
                        outputs: []outputInfo{
                                {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
@@ -34914,83 +36900,89 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:   "MOVHloadidx2",
+               name:   "FMADDD",
                argLen: 3,
-               asm:    arm64.AMOVH,
+               asm:    arm64.AFMADDD,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {1, 402653183},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
-                               {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
+                               {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {2, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
                        },
                        outputs: []outputInfo{
-                               {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
+                               {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
                        },
                },
        },
        {
-               name:   "MOVHUloadidx2",
+               name:   "FNMADDS",
                argLen: 3,
-               asm:    arm64.AMOVHU,
+               asm:    arm64.AFNMADDS,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {1, 402653183},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
-                               {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
+                               {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {2, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
                        },
                        outputs: []outputInfo{
-                               {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
+                               {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
                        },
                },
        },
        {
-               name:   "MOVWloadidx4",
+               name:   "FNMADDD",
                argLen: 3,
-               asm:    arm64.AMOVW,
+               asm:    arm64.AFNMADDD,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {1, 402653183},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
-                               {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
+                               {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {2, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
                        },
                        outputs: []outputInfo{
-                               {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
+                               {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
                        },
                },
        },
        {
-               name:   "MOVWUloadidx4",
+               name:   "FMSUBS",
                argLen: 3,
-               asm:    arm64.AMOVWU,
+               asm:    arm64.AFMSUBS,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {1, 402653183},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
-                               {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
+                               {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {2, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
                        },
                        outputs: []outputInfo{
-                               {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
+                               {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
                        },
                },
        },
        {
-               name:   "MOVDloadidx8",
+               name:   "FMSUBD",
                argLen: 3,
-               asm:    arm64.AMOVD,
+               asm:    arm64.AFMSUBD,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {1, 402653183},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
-                               {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
+                               {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {2, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
                        },
                        outputs: []outputInfo{
-                               {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
+                               {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
                        },
                },
        },
        {
-               name:   "FMOVSloadidx4",
+               name:   "FNMSUBS",
                argLen: 3,
-               asm:    arm64.AFMOVS,
+               asm:    arm64.AFNMSUBS,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {1, 402653183},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
-                               {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
+                               {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {2, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
                        },
                        outputs: []outputInfo{
                                {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
@@ -34998,13 +36990,14 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:   "FMOVDloadidx8",
+               name:   "FNMSUBD",
                argLen: 3,
-               asm:    arm64.AFMOVD,
+               asm:    arm64.AFNMSUBD,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {1, 402653183},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
-                               {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
+                               {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {2, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
                        },
                        outputs: []outputInfo{
                                {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
@@ -35012,389 +37005,418 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:           "MOVBstore",
-               auxType:        auxSymOff,
-               argLen:         3,
-               faultOnNilArg0: true,
-               symEffect:      SymWrite,
-               asm:            arm64.AMOVB,
+               name:   "MADD",
+               argLen: 3,
+               asm:    arm64.AMADD,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {1, 939524095},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO
-                               {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
+                               {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
+                               {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
+                               {2, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
+                       },
+                       outputs: []outputInfo{
+                               {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
                        },
                },
        },
        {
-               name:           "MOVHstore",
-               auxType:        auxSymOff,
-               argLen:         3,
-               faultOnNilArg0: true,
-               symEffect:      SymWrite,
-               asm:            arm64.AMOVH,
+               name:   "MADDW",
+               argLen: 3,
+               asm:    arm64.AMADDW,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {1, 939524095},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO
-                               {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
+                               {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
+                               {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
+                               {2, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
+                       },
+                       outputs: []outputInfo{
+                               {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
                        },
                },
        },
        {
-               name:           "MOVWstore",
-               auxType:        auxSymOff,
-               argLen:         3,
-               faultOnNilArg0: true,
-               symEffect:      SymWrite,
-               asm:            arm64.AMOVW,
+               name:   "MSUB",
+               argLen: 3,
+               asm:    arm64.AMSUB,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {1, 939524095},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO
-                               {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
+                               {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
+                               {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
+                               {2, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
+                       },
+                       outputs: []outputInfo{
+                               {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
                        },
                },
        },
        {
-               name:           "MOVDstore",
-               auxType:        auxSymOff,
-               argLen:         3,
-               faultOnNilArg0: true,
-               symEffect:      SymWrite,
-               asm:            arm64.AMOVD,
+               name:   "MSUBW",
+               argLen: 3,
+               asm:    arm64.AMSUBW,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {1, 939524095},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO
-                               {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
+                               {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
+                               {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
+                               {2, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
+                       },
+                       outputs: []outputInfo{
+                               {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
                        },
                },
        },
        {
-               name:           "FMOVSstore",
-               auxType:        auxSymOff,
-               argLen:         3,
-               faultOnNilArg0: true,
-               symEffect:      SymWrite,
-               asm:            arm64.AFMOVS,
+               name:   "SLL",
+               argLen: 2,
+               asm:    arm64.ALSL,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
-                               {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
+                               {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
+                       },
+                       outputs: []outputInfo{
+                               {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
                        },
                },
        },
        {
-               name:           "FMOVDstore",
-               auxType:        auxSymOff,
-               argLen:         3,
-               faultOnNilArg0: true,
-               symEffect:      SymWrite,
-               asm:            arm64.AFMOVD,
+               name:    "SLLconst",
+               auxType: auxInt64,
+               argLen:  1,
+               asm:     arm64.ALSL,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
-                               {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
+                       },
+                       outputs: []outputInfo{
+                               {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
                        },
                },
        },
        {
-               name:           "STP",
-               auxType:        auxSymOff,
-               argLen:         4,
-               faultOnNilArg0: true,
-               symEffect:      SymWrite,
-               asm:            arm64.ASTP,
+               name:   "SRL",
+               argLen: 2,
+               asm:    arm64.ALSR,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {1, 939524095},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO
-                               {2, 939524095},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO
-                               {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
+                               {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
+                               {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
+                       },
+                       outputs: []outputInfo{
+                               {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
                        },
                },
        },
        {
-               name:           "STPW",
-               auxType:        auxSymOff,
-               argLen:         4,
-               faultOnNilArg0: true,
-               symEffect:      SymWrite,
-               asm:            arm64.ASTPW,
+               name:    "SRLconst",
+               auxType: auxInt64,
+               argLen:  1,
+               asm:     arm64.ALSR,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {1, 939524095},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO
-                               {2, 939524095},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO
-                               {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
+                               {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
+                       },
+                       outputs: []outputInfo{
+                               {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
                        },
                },
        },
        {
-               name:           "FSTPD",
-               auxType:        auxSymOff,
-               argLen:         4,
-               faultOnNilArg0: true,
-               symEffect:      SymWrite,
-               asm:            arm64.AFSTPD,
+               name:   "SRA",
+               argLen: 2,
+               asm:    arm64.AASR,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
-                               {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
-                               {2, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
+                               {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
+                       },
+                       outputs: []outputInfo{
+                               {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
                        },
                },
        },
        {
-               name:           "FSTPS",
-               auxType:        auxSymOff,
-               argLen:         4,
-               faultOnNilArg0: true,
-               symEffect:      SymWrite,
-               asm:            arm64.AFSTPS,
+               name:    "SRAconst",
+               auxType: auxInt64,
+               argLen:  1,
+               asm:     arm64.AASR,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
-                               {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
-                               {2, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
+                       },
+                       outputs: []outputInfo{
+                               {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
                        },
                },
        },
        {
-               name:   "MOVBstoreidx",
-               argLen: 4,
-               asm:    arm64.AMOVB,
+               name:   "ROR",
+               argLen: 2,
+               asm:    arm64.AROR,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {1, 939524095},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO
-                               {2, 939524095},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO
-                               {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
+                               {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
+                               {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
+                       },
+                       outputs: []outputInfo{
+                               {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
                        },
                },
        },
        {
-               name:   "MOVHstoreidx",
-               argLen: 4,
-               asm:    arm64.AMOVH,
+               name:   "RORW",
+               argLen: 2,
+               asm:    arm64.ARORW,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {1, 939524095},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO
-                               {2, 939524095},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO
-                               {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
+                               {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
+                               {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
+                       },
+                       outputs: []outputInfo{
+                               {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
                        },
                },
        },
        {
-               name:   "MOVWstoreidx",
-               argLen: 4,
-               asm:    arm64.AMOVW,
+               name:    "RORconst",
+               auxType: auxInt64,
+               argLen:  1,
+               asm:     arm64.AROR,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {1, 939524095},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO
-                               {2, 939524095},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO
-                               {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
+                               {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
+                       },
+                       outputs: []outputInfo{
+                               {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
                        },
                },
        },
        {
-               name:   "MOVDstoreidx",
-               argLen: 4,
-               asm:    arm64.AMOVD,
+               name:    "RORWconst",
+               auxType: auxInt64,
+               argLen:  1,
+               asm:     arm64.ARORW,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {1, 939524095},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO
-                               {2, 939524095},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO
-                               {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
+                               {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
+                       },
+                       outputs: []outputInfo{
+                               {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
                        },
                },
        },
        {
-               name:   "FMOVSstoreidx",
-               argLen: 4,
-               asm:    arm64.AFMOVS,
+               name:    "EXTRconst",
+               auxType: auxInt64,
+               argLen:  2,
+               asm:     arm64.AEXTR,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {1, 402653183},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
-                               {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
-                               {2, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
+                               {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
+                       },
+                       outputs: []outputInfo{
+                               {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
                        },
                },
        },
        {
-               name:   "FMOVDstoreidx",
-               argLen: 4,
-               asm:    arm64.AFMOVD,
+               name:    "EXTRWconst",
+               auxType: auxInt64,
+               argLen:  2,
+               asm:     arm64.AEXTRW,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {1, 402653183},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
-                               {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
-                               {2, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
+                               {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
+                       },
+                       outputs: []outputInfo{
+                               {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
                        },
                },
        },
        {
-               name:   "MOVHstoreidx2",
-               argLen: 4,
-               asm:    arm64.AMOVH,
+               name:   "CMP",
+               argLen: 2,
+               asm:    arm64.ACMP,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {1, 939524095},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO
-                               {2, 939524095},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO
-                               {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
+                               {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
+                               {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
                        },
                },
        },
        {
-               name:   "MOVWstoreidx4",
-               argLen: 4,
-               asm:    arm64.AMOVW,
+               name:    "CMPconst",
+               auxType: auxInt64,
+               argLen:  1,
+               asm:     arm64.ACMP,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {1, 939524095},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO
-                               {2, 939524095},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO
-                               {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
+                               {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
                        },
                },
        },
        {
-               name:   "MOVDstoreidx8",
-               argLen: 4,
-               asm:    arm64.AMOVD,
+               name:   "CMPW",
+               argLen: 2,
+               asm:    arm64.ACMPW,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {1, 939524095},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO
-                               {2, 939524095},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO
-                               {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
+                               {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
+                               {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
                        },
                },
        },
        {
-               name:   "FMOVSstoreidx4",
-               argLen: 4,
-               asm:    arm64.AFMOVS,
+               name:    "CMPWconst",
+               auxType: auxInt32,
+               argLen:  1,
+               asm:     arm64.ACMPW,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {1, 402653183},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
-                               {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
-                               {2, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
                        },
                },
        },
        {
-               name:   "FMOVDstoreidx8",
-               argLen: 4,
-               asm:    arm64.AFMOVD,
+               name:        "CMN",
+               argLen:      2,
+               commutative: true,
+               asm:         arm64.ACMN,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {1, 402653183},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
-                               {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
-                               {2, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
+                               {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
                        },
                },
        },
        {
-               name:   "FMOVDgpfp",
-               argLen: 1,
-               asm:    arm64.AFMOVD,
+               name:    "CMNconst",
+               auxType: auxInt64,
+               argLen:  1,
+               asm:     arm64.ACMN,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
-                       },
-                       outputs: []outputInfo{
-                               {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
                        },
                },
        },
        {
-               name:   "FMOVDfpgp",
-               argLen: 1,
-               asm:    arm64.AFMOVD,
+               name:        "CMNW",
+               argLen:      2,
+               commutative: true,
+               asm:         arm64.ACMNW,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
-                       },
-                       outputs: []outputInfo{
-                               {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
+                               {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
+                               {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
                        },
                },
        },
        {
-               name:   "FMOVSgpfp",
-               argLen: 1,
-               asm:    arm64.AFMOVS,
+               name:    "CMNWconst",
+               auxType: auxInt32,
+               argLen:  1,
+               asm:     arm64.ACMNW,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
-                       },
-                       outputs: []outputInfo{
-                               {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
                        },
                },
        },
        {
-               name:   "FMOVSfpgp",
-               argLen: 1,
-               asm:    arm64.AFMOVS,
+               name:        "TST",
+               argLen:      2,
+               commutative: true,
+               asm:         arm64.ATST,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
-                       },
-                       outputs: []outputInfo{
-                               {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
+                               {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
+                               {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
                        },
                },
        },
        {
-               name:   "MOVBreg",
-               argLen: 1,
-               asm:    arm64.AMOVB,
+               name:    "TSTconst",
+               auxType: auxInt64,
+               argLen:  1,
+               asm:     arm64.ATST,
                reg: regInfo{
                        inputs: []inputInfo{
                                {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
                        },
-                       outputs: []outputInfo{
-                               {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
-                       },
                },
        },
        {
-               name:   "MOVBUreg",
-               argLen: 1,
-               asm:    arm64.AMOVBU,
+               name:        "TSTW",
+               argLen:      2,
+               commutative: true,
+               asm:         arm64.ATSTW,
                reg: regInfo{
                        inputs: []inputInfo{
                                {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
-                       },
-                       outputs: []outputInfo{
-                               {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
+                               {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
                        },
                },
        },
        {
-               name:   "MOVHreg",
-               argLen: 1,
-               asm:    arm64.AMOVH,
+               name:    "TSTWconst",
+               auxType: auxInt32,
+               argLen:  1,
+               asm:     arm64.ATSTW,
                reg: regInfo{
                        inputs: []inputInfo{
                                {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
                        },
-                       outputs: []outputInfo{
-                               {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
+               },
+       },
+       {
+               name:   "FCMPS",
+               argLen: 2,
+               asm:    arm64.AFCMPS,
+               reg: regInfo{
+                       inputs: []inputInfo{
+                               {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
                        },
                },
        },
        {
-               name:   "MOVHUreg",
-               argLen: 1,
-               asm:    arm64.AMOVHU,
+               name:   "FCMPD",
+               argLen: 2,
+               asm:    arm64.AFCMPD,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
+                               {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
                        },
-                       outputs: []outputInfo{
-                               {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
+               },
+       },
+       {
+               name:   "FCMPS0",
+               argLen: 1,
+               asm:    arm64.AFCMPS,
+               reg: regInfo{
+                       inputs: []inputInfo{
+                               {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
                        },
                },
        },
        {
-               name:   "MOVWreg",
+               name:   "FCMPD0",
                argLen: 1,
-               asm:    arm64.AMOVW,
+               asm:    arm64.AFCMPD,
+               reg: regInfo{
+                       inputs: []inputInfo{
+                               {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                       },
+               },
+       },
+       {
+               name:    "MVNshiftLL",
+               auxType: auxInt64,
+               argLen:  1,
+               asm:     arm64.AMVN,
                reg: regInfo{
                        inputs: []inputInfo{
                                {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
@@ -35405,9 +37427,10 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:   "MOVWUreg",
-               argLen: 1,
-               asm:    arm64.AMOVWU,
+               name:    "MVNshiftRL",
+               auxType: auxInt64,
+               argLen:  1,
+               asm:     arm64.AMVN,
                reg: regInfo{
                        inputs: []inputInfo{
                                {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
@@ -35418,9 +37441,10 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:   "MOVDreg",
-               argLen: 1,
-               asm:    arm64.AMOVD,
+               name:    "MVNshiftRA",
+               auxType: auxInt64,
+               argLen:  1,
+               asm:     arm64.AMVN,
                reg: regInfo{
                        inputs: []inputInfo{
                                {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
@@ -35431,12 +37455,13 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:         "MOVDnop",
-               argLen:       1,
-               resultInArg0: true,
+               name:    "MVNshiftRO",
+               auxType: auxInt64,
+               argLen:  1,
+               asm:     arm64.AMVN,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
+                               {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
                        },
                        outputs: []outputInfo{
                                {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
@@ -35444,116 +37469,131 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:   "SCVTFWS",
-               argLen: 1,
-               asm:    arm64.ASCVTFWS,
+               name:    "NEGshiftLL",
+               auxType: auxInt64,
+               argLen:  1,
+               asm:     arm64.ANEG,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
+                               {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
                        },
                        outputs: []outputInfo{
-                               {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
                        },
                },
        },
        {
-               name:   "SCVTFWD",
-               argLen: 1,
-               asm:    arm64.ASCVTFWD,
+               name:    "NEGshiftRL",
+               auxType: auxInt64,
+               argLen:  1,
+               asm:     arm64.ANEG,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
+                               {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
                        },
                        outputs: []outputInfo{
-                               {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
                        },
                },
        },
        {
-               name:   "UCVTFWS",
-               argLen: 1,
-               asm:    arm64.AUCVTFWS,
+               name:    "NEGshiftRA",
+               auxType: auxInt64,
+               argLen:  1,
+               asm:     arm64.ANEG,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
+                               {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
                        },
                        outputs: []outputInfo{
-                               {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
                        },
                },
        },
        {
-               name:   "UCVTFWD",
-               argLen: 1,
-               asm:    arm64.AUCVTFWD,
+               name:    "ADDshiftLL",
+               auxType: auxInt64,
+               argLen:  2,
+               asm:     arm64.AADD,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
+                               {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
+                               {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
                        },
                        outputs: []outputInfo{
-                               {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
                        },
                },
        },
        {
-               name:   "SCVTFS",
-               argLen: 1,
-               asm:    arm64.ASCVTFS,
+               name:    "ADDshiftRL",
+               auxType: auxInt64,
+               argLen:  2,
+               asm:     arm64.AADD,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
+                               {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
+                               {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
                        },
                        outputs: []outputInfo{
-                               {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
                        },
                },
        },
        {
-               name:   "SCVTFD",
-               argLen: 1,
-               asm:    arm64.ASCVTFD,
+               name:    "ADDshiftRA",
+               auxType: auxInt64,
+               argLen:  2,
+               asm:     arm64.AADD,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
+                               {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
+                               {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
                        },
                        outputs: []outputInfo{
-                               {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
                        },
                },
        },
        {
-               name:   "UCVTFS",
-               argLen: 1,
-               asm:    arm64.AUCVTFS,
+               name:    "SUBshiftLL",
+               auxType: auxInt64,
+               argLen:  2,
+               asm:     arm64.ASUB,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
+                               {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
+                               {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
                        },
                        outputs: []outputInfo{
-                               {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
                        },
                },
        },
        {
-               name:   "UCVTFD",
-               argLen: 1,
-               asm:    arm64.AUCVTFD,
+               name:    "SUBshiftRL",
+               auxType: auxInt64,
+               argLen:  2,
+               asm:     arm64.ASUB,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
+                               {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
+                               {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
                        },
                        outputs: []outputInfo{
-                               {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
                        },
                },
        },
        {
-               name:   "FCVTZSSW",
-               argLen: 1,
-               asm:    arm64.AFCVTZSSW,
+               name:    "SUBshiftRA",
+               auxType: auxInt64,
+               argLen:  2,
+               asm:     arm64.ASUB,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
+                               {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
                        },
                        outputs: []outputInfo{
                                {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
@@ -35561,12 +37601,14 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:   "FCVTZSDW",
-               argLen: 1,
-               asm:    arm64.AFCVTZSDW,
+               name:    "ANDshiftLL",
+               auxType: auxInt64,
+               argLen:  2,
+               asm:     arm64.AAND,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
+                               {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
                        },
                        outputs: []outputInfo{
                                {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
@@ -35574,12 +37616,14 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:   "FCVTZUSW",
-               argLen: 1,
-               asm:    arm64.AFCVTZUSW,
+               name:    "ANDshiftRL",
+               auxType: auxInt64,
+               argLen:  2,
+               asm:     arm64.AAND,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
+                               {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
                        },
                        outputs: []outputInfo{
                                {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
@@ -35587,12 +37631,14 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:   "FCVTZUDW",
-               argLen: 1,
-               asm:    arm64.AFCVTZUDW,
+               name:    "ANDshiftRA",
+               auxType: auxInt64,
+               argLen:  2,
+               asm:     arm64.AAND,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
+                               {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
                        },
                        outputs: []outputInfo{
                                {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
@@ -35600,12 +37646,14 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:   "FCVTZSS",
-               argLen: 1,
-               asm:    arm64.AFCVTZSS,
+               name:    "ANDshiftRO",
+               auxType: auxInt64,
+               argLen:  2,
+               asm:     arm64.AAND,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
+                               {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
                        },
                        outputs: []outputInfo{
                                {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
@@ -35613,12 +37661,14 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:   "FCVTZSD",
-               argLen: 1,
-               asm:    arm64.AFCVTZSD,
+               name:    "ORshiftLL",
+               auxType: auxInt64,
+               argLen:  2,
+               asm:     arm64.AORR,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
+                               {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
                        },
                        outputs: []outputInfo{
                                {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
@@ -35626,12 +37676,14 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:   "FCVTZUS",
-               argLen: 1,
-               asm:    arm64.AFCVTZUS,
+               name:    "ORshiftRL",
+               auxType: auxInt64,
+               argLen:  2,
+               asm:     arm64.AORR,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
+                               {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
                        },
                        outputs: []outputInfo{
                                {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
@@ -35639,12 +37691,14 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:   "FCVTZUD",
-               argLen: 1,
-               asm:    arm64.AFCVTZUD,
+               name:    "ORshiftRA",
+               auxType: auxInt64,
+               argLen:  2,
+               asm:     arm64.AORR,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
+                               {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
                        },
                        outputs: []outputInfo{
                                {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
@@ -35652,105 +37706,119 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:   "FCVTSD",
-               argLen: 1,
-               asm:    arm64.AFCVTSD,
+               name:    "ORshiftRO",
+               auxType: auxInt64,
+               argLen:  2,
+               asm:     arm64.AORR,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
+                               {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
                        },
                        outputs: []outputInfo{
-                               {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
                        },
                },
        },
        {
-               name:   "FCVTDS",
-               argLen: 1,
-               asm:    arm64.AFCVTDS,
+               name:    "XORshiftLL",
+               auxType: auxInt64,
+               argLen:  2,
+               asm:     arm64.AEOR,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
+                               {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
                        },
                        outputs: []outputInfo{
-                               {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
                        },
                },
        },
        {
-               name:   "FRINTAD",
-               argLen: 1,
-               asm:    arm64.AFRINTAD,
+               name:    "XORshiftRL",
+               auxType: auxInt64,
+               argLen:  2,
+               asm:     arm64.AEOR,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
+                               {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
                        },
                        outputs: []outputInfo{
-                               {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
                        },
                },
        },
        {
-               name:   "FRINTMD",
-               argLen: 1,
-               asm:    arm64.AFRINTMD,
+               name:    "XORshiftRA",
+               auxType: auxInt64,
+               argLen:  2,
+               asm:     arm64.AEOR,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
+                               {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
                        },
                        outputs: []outputInfo{
-                               {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
                        },
                },
        },
        {
-               name:   "FRINTND",
-               argLen: 1,
-               asm:    arm64.AFRINTND,
+               name:    "XORshiftRO",
+               auxType: auxInt64,
+               argLen:  2,
+               asm:     arm64.AEOR,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
+                               {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
                        },
                        outputs: []outputInfo{
-                               {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
                        },
                },
        },
        {
-               name:   "FRINTPD",
-               argLen: 1,
-               asm:    arm64.AFRINTPD,
+               name:    "BICshiftLL",
+               auxType: auxInt64,
+               argLen:  2,
+               asm:     arm64.ABIC,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
+                               {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
                        },
                        outputs: []outputInfo{
-                               {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
                        },
                },
        },
        {
-               name:   "FRINTZD",
-               argLen: 1,
-               asm:    arm64.AFRINTZD,
+               name:    "BICshiftRL",
+               auxType: auxInt64,
+               argLen:  2,
+               asm:     arm64.ABIC,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
+                               {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
                        },
                        outputs: []outputInfo{
-                               {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
                        },
                },
        },
        {
-               name:    "CSEL",
-               auxType: auxCCop,
-               argLen:  3,
-               asm:     arm64.ACSEL,
+               name:    "BICshiftRA",
+               auxType: auxInt64,
+               argLen:  2,
+               asm:     arm64.ABIC,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
-                               {1, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
+                               {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
+                               {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
                        },
                        outputs: []outputInfo{
                                {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
@@ -35758,13 +37826,14 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:    "CSEL0",
-               auxType: auxCCop,
+               name:    "BICshiftRO",
+               auxType: auxInt64,
                argLen:  2,
-               asm:     arm64.ACSEL,
+               asm:     arm64.ABIC,
                reg: regInfo{
                        inputs: []inputInfo{
                                {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
+                               {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
                        },
                        outputs: []outputInfo{
                                {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
@@ -35772,14 +37841,14 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:    "CSINC",
-               auxType: auxCCop,
-               argLen:  3,
-               asm:     arm64.ACSINC,
+               name:    "EONshiftLL",
+               auxType: auxInt64,
+               argLen:  2,
+               asm:     arm64.AEON,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
-                               {1, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
+                               {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
+                               {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
                        },
                        outputs: []outputInfo{
                                {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
@@ -35787,14 +37856,14 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:    "CSINV",
-               auxType: auxCCop,
-               argLen:  3,
-               asm:     arm64.ACSINV,
+               name:    "EONshiftRL",
+               auxType: auxInt64,
+               argLen:  2,
+               asm:     arm64.AEON,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
-                               {1, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
+                               {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
+                               {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
                        },
                        outputs: []outputInfo{
                                {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
@@ -35802,14 +37871,14 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:    "CSNEG",
-               auxType: auxCCop,
-               argLen:  3,
-               asm:     arm64.ACSNEG,
+               name:    "EONshiftRA",
+               auxType: auxInt64,
+               argLen:  2,
+               asm:     arm64.AEON,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
-                               {1, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
+                               {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
+                               {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
                        },
                        outputs: []outputInfo{
                                {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
@@ -35817,231 +37886,294 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:    "CSETM",
-               auxType: auxCCop,
-               argLen:  1,
-               asm:     arm64.ACSETM,
+               name:    "EONshiftRO",
+               auxType: auxInt64,
+               argLen:  2,
+               asm:     arm64.AEON,
                reg: regInfo{
+                       inputs: []inputInfo{
+                               {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
+                               {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
+                       },
                        outputs: []outputInfo{
                                {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
                        },
                },
        },
        {
-               name:         "CALLstatic",
-               auxType:      auxCallOff,
-               argLen:       -1,
-               clobberFlags: true,
-               call:         true,
-               reg: regInfo{
-                       clobbers: 9223372035109945343, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
-               },
-       },
-       {
-               name:         "CALLtail",
-               auxType:      auxCallOff,
-               argLen:       -1,
-               clobberFlags: true,
-               call:         true,
-               tailCall:     true,
-               reg: regInfo{
-                       clobbers: 9223372035109945343, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
-               },
-       },
-       {
-               name:         "CALLclosure",
-               auxType:      auxCallOff,
-               argLen:       -1,
-               clobberFlags: true,
-               call:         true,
+               name:    "ORNshiftLL",
+               auxType: auxInt64,
+               argLen:  2,
+               asm:     arm64.AORN,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {1, 33554432},   // R26
-                               {0, 1409286143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 SP
+                               {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
+                               {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
+                       },
+                       outputs: []outputInfo{
+                               {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
                        },
-                       clobbers: 9223372035109945343, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
                },
        },
        {
-               name:         "CALLinter",
-               auxType:      auxCallOff,
-               argLen:       -1,
-               clobberFlags: true,
-               call:         true,
+               name:    "ORNshiftRL",
+               auxType: auxInt64,
+               argLen:  2,
+               asm:     arm64.AORN,
                reg: regInfo{
                        inputs: []inputInfo{
+                               {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
+                               {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
+                       },
+                       outputs: []outputInfo{
                                {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
                        },
-                       clobbers: 9223372035109945343, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
                },
        },
        {
-               name:           "LoweredNilCheck",
-               argLen:         2,
-               nilCheck:       true,
-               faultOnNilArg0: true,
+               name:    "ORNshiftRA",
+               auxType: auxInt64,
+               argLen:  2,
+               asm:     arm64.AORN,
                reg: regInfo{
                        inputs: []inputInfo{
                                {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
+                               {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
+                       },
+                       outputs: []outputInfo{
+                               {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
                        },
                },
        },
        {
-               name:   "Equal",
-               argLen: 1,
+               name:    "ORNshiftRO",
+               auxType: auxInt64,
+               argLen:  2,
+               asm:     arm64.AORN,
                reg: regInfo{
+                       inputs: []inputInfo{
+                               {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
+                               {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
+                       },
                        outputs: []outputInfo{
                                {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
                        },
                },
        },
        {
-               name:   "NotEqual",
-               argLen: 1,
+               name:    "CMPshiftLL",
+               auxType: auxInt64,
+               argLen:  2,
+               asm:     arm64.ACMP,
                reg: regInfo{
-                       outputs: []outputInfo{
-                               {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
+                       inputs: []inputInfo{
+                               {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
+                               {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
                        },
                },
        },
        {
-               name:   "LessThan",
-               argLen: 1,
+               name:    "CMPshiftRL",
+               auxType: auxInt64,
+               argLen:  2,
+               asm:     arm64.ACMP,
                reg: regInfo{
-                       outputs: []outputInfo{
-                               {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
+                       inputs: []inputInfo{
+                               {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
+                               {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
                        },
                },
        },
        {
-               name:   "LessEqual",
-               argLen: 1,
+               name:    "CMPshiftRA",
+               auxType: auxInt64,
+               argLen:  2,
+               asm:     arm64.ACMP,
                reg: regInfo{
-                       outputs: []outputInfo{
-                               {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
+                       inputs: []inputInfo{
+                               {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
+                               {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
                        },
                },
        },
        {
-               name:   "GreaterThan",
-               argLen: 1,
+               name:    "CMNshiftLL",
+               auxType: auxInt64,
+               argLen:  2,
+               asm:     arm64.ACMN,
                reg: regInfo{
-                       outputs: []outputInfo{
-                               {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
+                       inputs: []inputInfo{
+                               {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
+                               {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
                        },
                },
        },
        {
-               name:   "GreaterEqual",
-               argLen: 1,
+               name:    "CMNshiftRL",
+               auxType: auxInt64,
+               argLen:  2,
+               asm:     arm64.ACMN,
                reg: regInfo{
-                       outputs: []outputInfo{
-                               {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
+                       inputs: []inputInfo{
+                               {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
+                               {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
                        },
                },
        },
        {
-               name:   "LessThanU",
-               argLen: 1,
+               name:    "CMNshiftRA",
+               auxType: auxInt64,
+               argLen:  2,
+               asm:     arm64.ACMN,
                reg: regInfo{
-                       outputs: []outputInfo{
-                               {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
+                       inputs: []inputInfo{
+                               {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
+                               {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
                        },
                },
        },
        {
-               name:   "LessEqualU",
-               argLen: 1,
+               name:    "TSTshiftLL",
+               auxType: auxInt64,
+               argLen:  2,
+               asm:     arm64.ATST,
                reg: regInfo{
-                       outputs: []outputInfo{
-                               {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
+                       inputs: []inputInfo{
+                               {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
+                               {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
                        },
                },
        },
        {
-               name:   "GreaterThanU",
-               argLen: 1,
+               name:    "TSTshiftRL",
+               auxType: auxInt64,
+               argLen:  2,
+               asm:     arm64.ATST,
                reg: regInfo{
-                       outputs: []outputInfo{
-                               {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
+                       inputs: []inputInfo{
+                               {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
+                               {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
                        },
                },
        },
        {
-               name:   "GreaterEqualU",
-               argLen: 1,
+               name:    "TSTshiftRA",
+               auxType: auxInt64,
+               argLen:  2,
+               asm:     arm64.ATST,
                reg: regInfo{
-                       outputs: []outputInfo{
-                               {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
+                       inputs: []inputInfo{
+                               {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
+                               {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
                        },
                },
        },
        {
-               name:   "LessThanF",
-               argLen: 1,
+               name:    "TSTshiftRO",
+               auxType: auxInt64,
+               argLen:  2,
+               asm:     arm64.ATST,
                reg: regInfo{
-                       outputs: []outputInfo{
-                               {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
+                       inputs: []inputInfo{
+                               {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
+                               {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
                        },
                },
        },
        {
-               name:   "LessEqualF",
-               argLen: 1,
+               name:         "BFI",
+               auxType:      auxARM64BitField,
+               argLen:       2,
+               resultInArg0: true,
+               asm:          arm64.ABFI,
                reg: regInfo{
+                       inputs: []inputInfo{
+                               {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
+                               {1, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
+                       },
                        outputs: []outputInfo{
                                {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
                        },
                },
        },
        {
-               name:   "GreaterThanF",
-               argLen: 1,
+               name:         "BFXIL",
+               auxType:      auxARM64BitField,
+               argLen:       2,
+               resultInArg0: true,
+               asm:          arm64.ABFXIL,
                reg: regInfo{
+                       inputs: []inputInfo{
+                               {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
+                               {1, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
+                       },
                        outputs: []outputInfo{
                                {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
                        },
                },
        },
        {
-               name:   "GreaterEqualF",
-               argLen: 1,
+               name:    "SBFIZ",
+               auxType: auxARM64BitField,
+               argLen:  1,
+               asm:     arm64.ASBFIZ,
                reg: regInfo{
+                       inputs: []inputInfo{
+                               {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
+                       },
                        outputs: []outputInfo{
                                {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
                        },
                },
        },
        {
-               name:   "NotLessThanF",
-               argLen: 1,
+               name:    "SBFX",
+               auxType: auxARM64BitField,
+               argLen:  1,
+               asm:     arm64.ASBFX,
                reg: regInfo{
+                       inputs: []inputInfo{
+                               {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
+                       },
                        outputs: []outputInfo{
                                {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
                        },
                },
        },
        {
-               name:   "NotLessEqualF",
-               argLen: 1,
+               name:    "UBFIZ",
+               auxType: auxARM64BitField,
+               argLen:  1,
+               asm:     arm64.AUBFIZ,
                reg: regInfo{
+                       inputs: []inputInfo{
+                               {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
+                       },
                        outputs: []outputInfo{
                                {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
                        },
                },
        },
        {
-               name:   "NotGreaterThanF",
-               argLen: 1,
+               name:    "UBFX",
+               auxType: auxARM64BitField,
+               argLen:  1,
+               asm:     arm64.AUBFX,
                reg: regInfo{
+                       inputs: []inputInfo{
+                               {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
+                       },
                        outputs: []outputInfo{
                                {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
                        },
                },
        },
        {
-               name:   "NotGreaterEqualF",
-               argLen: 1,
+               name:              "MOVDconst",
+               auxType:           auxInt64,
+               argLen:            0,
+               rematerializeable: true,
+               asm:               arm64.AMOVD,
                reg: regInfo{
                        outputs: []outputInfo{
                                {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
@@ -36049,122 +38181,132 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:   "LessThanNoov",
-               argLen: 1,
+               name:              "FMOVSconst",
+               auxType:           auxFloat64,
+               argLen:            0,
+               rematerializeable: true,
+               asm:               arm64.AFMOVS,
                reg: regInfo{
                        outputs: []outputInfo{
-                               {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
+                               {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
                        },
                },
        },
        {
-               name:   "GreaterEqualNoov",
-               argLen: 1,
+               name:              "FMOVDconst",
+               auxType:           auxFloat64,
+               argLen:            0,
+               rematerializeable: true,
+               asm:               arm64.AFMOVD,
                reg: regInfo{
                        outputs: []outputInfo{
-                               {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
+                               {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
                        },
                },
        },
        {
-               name:        "DUFFZERO",
-               auxType:     auxInt64,
-               argLen:      2,
-               unsafePoint: true,
+               name:              "MOVDaddr",
+               auxType:           auxSymOff,
+               argLen:            1,
+               rematerializeable: true,
+               symEffect:         SymAddr,
+               asm:               arm64.AMOVD,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 524288}, // R20
+                               {0, 9223372037928517632}, // SP SB
+                       },
+                       outputs: []outputInfo{
+                               {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
                        },
-                       clobbers: 269156352, // R16 R17 R20 R30
                },
        },
        {
-               name:           "LoweredZero",
-               argLen:         3,
-               clobberFlags:   true,
+               name:           "MOVBload",
+               auxType:        auxSymOff,
+               argLen:         2,
                faultOnNilArg0: true,
+               symEffect:      SymRead,
+               asm:            arm64.AMOVB,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 65536},     // R16
-                               {1, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
+                               {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
+                       },
+                       outputs: []outputInfo{
+                               {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
                        },
-                       clobbers: 65536, // R16
                },
        },
        {
-               name:        "DUFFCOPY",
-               auxType:     auxInt64,
-               argLen:      3,
-               unsafePoint: true,
+               name:           "MOVBUload",
+               auxType:        auxSymOff,
+               argLen:         2,
+               faultOnNilArg0: true,
+               symEffect:      SymRead,
+               asm:            arm64.AMOVBU,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 1048576}, // R21
-                               {1, 524288},  // R20
+                               {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
+                       },
+                       outputs: []outputInfo{
+                               {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
                        },
-                       clobbers: 303759360, // R16 R17 R20 R21 R26 R30
                },
        },
        {
-               name:           "LoweredMove",
-               argLen:         4,
-               clobberFlags:   true,
+               name:           "MOVHload",
+               auxType:        auxSymOff,
+               argLen:         2,
                faultOnNilArg0: true,
-               faultOnNilArg1: true,
+               symEffect:      SymRead,
+               asm:            arm64.AMOVH,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 131072},    // R17
-                               {1, 65536},     // R16
-                               {2, 318767103}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R26 R30
+                               {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
                        },
-                       clobbers: 16973824, // R16 R17 R25
-               },
-       },
-       {
-               name:      "LoweredGetClosurePtr",
-               argLen:    0,
-               zeroWidth: true,
-               reg: regInfo{
                        outputs: []outputInfo{
-                               {0, 33554432}, // R26
+                               {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
                        },
                },
        },
        {
-               name:              "LoweredGetCallerSP",
-               argLen:            1,
-               rematerializeable: true,
+               name:           "MOVHUload",
+               auxType:        auxSymOff,
+               argLen:         2,
+               faultOnNilArg0: true,
+               symEffect:      SymRead,
+               asm:            arm64.AMOVHU,
                reg: regInfo{
+                       inputs: []inputInfo{
+                               {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
+                       },
                        outputs: []outputInfo{
                                {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
                        },
                },
        },
        {
-               name:              "LoweredGetCallerPC",
-               argLen:            0,
-               rematerializeable: true,
+               name:           "MOVWload",
+               auxType:        auxSymOff,
+               argLen:         2,
+               faultOnNilArg0: true,
+               symEffect:      SymRead,
+               asm:            arm64.AMOVW,
                reg: regInfo{
+                       inputs: []inputInfo{
+                               {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
+                       },
                        outputs: []outputInfo{
                                {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
                        },
                },
        },
        {
-               name:    "FlagConstant",
-               auxType: auxFlagConstant,
-               argLen:  0,
-               reg:     regInfo{},
-       },
-       {
-               name:   "InvertFlags",
-               argLen: 1,
-               reg:    regInfo{},
-       },
-       {
-               name:           "LDAR",
+               name:           "MOVWUload",
+               auxType:        auxSymOff,
                argLen:         2,
                faultOnNilArg0: true,
-               asm:            arm64.ALDAR,
+               symEffect:      SymRead,
+               asm:            arm64.AMOVWU,
                reg: regInfo{
                        inputs: []inputInfo{
                                {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
@@ -36175,10 +38317,12 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:           "LDARB",
+               name:           "MOVDload",
+               auxType:        auxSymOff,
                argLen:         2,
                faultOnNilArg0: true,
-               asm:            arm64.ALDARB,
+               symEffect:      SymRead,
+               asm:            arm64.AMOVD,
                reg: regInfo{
                        inputs: []inputInfo{
                                {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
@@ -36189,118 +38333,129 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:           "LDARW",
+               name:           "FMOVSload",
+               auxType:        auxSymOff,
                argLen:         2,
                faultOnNilArg0: true,
-               asm:            arm64.ALDARW,
+               symEffect:      SymRead,
+               asm:            arm64.AFMOVS,
                reg: regInfo{
                        inputs: []inputInfo{
                                {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
                        },
                        outputs: []outputInfo{
-                               {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
+                               {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
                        },
                },
        },
        {
-               name:           "STLRB",
-               argLen:         3,
+               name:           "FMOVDload",
+               auxType:        auxSymOff,
+               argLen:         2,
                faultOnNilArg0: true,
-               hasSideEffects: true,
-               asm:            arm64.ASTLRB,
+               symEffect:      SymRead,
+               asm:            arm64.AFMOVD,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {1, 939524095},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO
                                {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
                        },
+                       outputs: []outputInfo{
+                               {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                       },
                },
        },
        {
-               name:           "STLR",
-               argLen:         3,
+               name:           "LDP",
+               auxType:        auxSymOff,
+               argLen:         2,
                faultOnNilArg0: true,
-               hasSideEffects: true,
-               asm:            arm64.ASTLR,
+               symEffect:      SymRead,
+               asm:            arm64.ALDP,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {1, 939524095},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO
                                {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
                        },
+                       outputs: []outputInfo{
+                               {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
+                               {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
+                       },
                },
        },
        {
-               name:           "STLRW",
-               argLen:         3,
+               name:           "LDPW",
+               auxType:        auxSymOff,
+               argLen:         2,
                faultOnNilArg0: true,
-               hasSideEffects: true,
-               asm:            arm64.ASTLRW,
+               symEffect:      SymRead,
+               asm:            arm64.ALDPW,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {1, 939524095},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO
                                {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
                        },
+                       outputs: []outputInfo{
+                               {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
+                               {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
+                       },
                },
        },
        {
-               name:            "LoweredAtomicExchange64",
-               argLen:          3,
-               resultNotInArgs: true,
-               faultOnNilArg0:  true,
-               hasSideEffects:  true,
-               unsafePoint:     true,
+               name:           "LDPSW",
+               auxType:        auxSymOff,
+               argLen:         2,
+               faultOnNilArg0: true,
+               symEffect:      SymRead,
+               asm:            arm64.ALDPSW,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {1, 939524095},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO
                                {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
                        },
                        outputs: []outputInfo{
-                               {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
+                               {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
+                               {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
                        },
                },
        },
        {
-               name:            "LoweredAtomicExchange32",
-               argLen:          3,
-               resultNotInArgs: true,
-               faultOnNilArg0:  true,
-               hasSideEffects:  true,
-               unsafePoint:     true,
+               name:           "FLDPD",
+               auxType:        auxSymOff,
+               argLen:         2,
+               faultOnNilArg0: true,
+               symEffect:      SymRead,
+               asm:            arm64.AFLDPD,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {1, 939524095},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO
                                {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
                        },
                        outputs: []outputInfo{
-                               {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
+                               {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
                        },
                },
        },
        {
-               name:            "LoweredAtomicExchange8",
-               argLen:          3,
-               resultNotInArgs: true,
-               faultOnNilArg0:  true,
-               hasSideEffects:  true,
-               unsafePoint:     true,
+               name:           "FLDPS",
+               auxType:        auxSymOff,
+               argLen:         2,
+               faultOnNilArg0: true,
+               symEffect:      SymRead,
+               asm:            arm64.AFLDPS,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {1, 939524095},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO
                                {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
                        },
                        outputs: []outputInfo{
-                               {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
+                               {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
                        },
                },
        },
        {
-               name:            "LoweredAtomicExchange64Variant",
-               argLen:          3,
-               resultNotInArgs: true,
-               faultOnNilArg0:  true,
-               hasSideEffects:  true,
+               name:   "MOVDloadidx",
+               argLen: 3,
+               asm:    arm64.AMOVD,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {1, 939524095},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO
+                               {1, 402653183},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
                                {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
                        },
                        outputs: []outputInfo{
@@ -36309,14 +38464,12 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:            "LoweredAtomicExchange32Variant",
-               argLen:          3,
-               resultNotInArgs: true,
-               faultOnNilArg0:  true,
-               hasSideEffects:  true,
+               name:   "MOVWloadidx",
+               argLen: 3,
+               asm:    arm64.AMOVW,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {1, 939524095},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO
+                               {1, 402653183},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
                                {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
                        },
                        outputs: []outputInfo{
@@ -36325,15 +38478,12 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:            "LoweredAtomicExchange8Variant",
-               argLen:          3,
-               resultNotInArgs: true,
-               faultOnNilArg0:  true,
-               hasSideEffects:  true,
-               unsafePoint:     true,
+               name:   "MOVWUloadidx",
+               argLen: 3,
+               asm:    arm64.AMOVWU,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {1, 939524095},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO
+                               {1, 402653183},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
                                {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
                        },
                        outputs: []outputInfo{
@@ -36342,15 +38492,12 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:            "LoweredAtomicAdd64",
-               argLen:          3,
-               resultNotInArgs: true,
-               faultOnNilArg0:  true,
-               hasSideEffects:  true,
-               unsafePoint:     true,
+               name:   "MOVHloadidx",
+               argLen: 3,
+               asm:    arm64.AMOVH,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {1, 939524095},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO
+                               {1, 402653183},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
                                {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
                        },
                        outputs: []outputInfo{
@@ -36359,15 +38506,12 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:            "LoweredAtomicAdd32",
-               argLen:          3,
-               resultNotInArgs: true,
-               faultOnNilArg0:  true,
-               hasSideEffects:  true,
-               unsafePoint:     true,
+               name:   "MOVHUloadidx",
+               argLen: 3,
+               asm:    arm64.AMOVHU,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {1, 939524095},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO
+                               {1, 402653183},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
                                {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
                        },
                        outputs: []outputInfo{
@@ -36376,14 +38520,12 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:            "LoweredAtomicAdd64Variant",
-               argLen:          3,
-               resultNotInArgs: true,
-               faultOnNilArg0:  true,
-               hasSideEffects:  true,
+               name:   "MOVBloadidx",
+               argLen: 3,
+               asm:    arm64.AMOVB,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {1, 939524095},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO
+                               {1, 402653183},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
                                {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
                        },
                        outputs: []outputInfo{
@@ -36392,14 +38534,12 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:            "LoweredAtomicAdd32Variant",
-               argLen:          3,
-               resultNotInArgs: true,
-               faultOnNilArg0:  true,
-               hasSideEffects:  true,
+               name:   "MOVBUloadidx",
+               argLen: 3,
+               asm:    arm64.AMOVBU,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {1, 939524095},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO
+                               {1, 402653183},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
                                {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
                        },
                        outputs: []outputInfo{
@@ -36408,55 +38548,40 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:            "LoweredAtomicCas64",
-               argLen:          4,
-               resultNotInArgs: true,
-               clobberFlags:    true,
-               faultOnNilArg0:  true,
-               hasSideEffects:  true,
-               unsafePoint:     true,
+               name:   "FMOVSloadidx",
+               argLen: 3,
+               asm:    arm64.AFMOVS,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {1, 939524095},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO
-                               {2, 939524095},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO
+                               {1, 402653183},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
                                {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
                        },
                        outputs: []outputInfo{
-                               {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
+                               {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
                        },
                },
        },
        {
-               name:            "LoweredAtomicCas32",
-               argLen:          4,
-               resultNotInArgs: true,
-               clobberFlags:    true,
-               faultOnNilArg0:  true,
-               hasSideEffects:  true,
-               unsafePoint:     true,
+               name:   "FMOVDloadidx",
+               argLen: 3,
+               asm:    arm64.AFMOVD,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {1, 939524095},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO
-                               {2, 939524095},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO
+                               {1, 402653183},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
                                {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
                        },
                        outputs: []outputInfo{
-                               {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
+                               {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
                        },
                },
        },
        {
-               name:            "LoweredAtomicCas64Variant",
-               argLen:          4,
-               resultNotInArgs: true,
-               clobberFlags:    true,
-               faultOnNilArg0:  true,
-               hasSideEffects:  true,
-               unsafePoint:     true,
+               name:   "MOVHloadidx2",
+               argLen: 3,
+               asm:    arm64.AMOVH,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {1, 939524095},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO
-                               {2, 939524095},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO
+                               {1, 402653183},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
                                {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
                        },
                        outputs: []outputInfo{
@@ -36465,17 +38590,12 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:            "LoweredAtomicCas32Variant",
-               argLen:          4,
-               resultNotInArgs: true,
-               clobberFlags:    true,
-               faultOnNilArg0:  true,
-               hasSideEffects:  true,
-               unsafePoint:     true,
+               name:   "MOVHUloadidx2",
+               argLen: 3,
+               asm:    arm64.AMOVHU,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {1, 939524095},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO
-                               {2, 939524095},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO
+                               {1, 402653183},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
                                {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
                        },
                        outputs: []outputInfo{
@@ -36484,17 +38604,12 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:            "LoweredAtomicAnd8",
-               argLen:          3,
-               resultNotInArgs: true,
-               needIntTemp:     true,
-               faultOnNilArg0:  true,
-               hasSideEffects:  true,
-               unsafePoint:     true,
-               asm:             arm64.AAND,
+               name:   "MOVWloadidx4",
+               argLen: 3,
+               asm:    arm64.AMOVW,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {1, 939524095},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO
+                               {1, 402653183},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
                                {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
                        },
                        outputs: []outputInfo{
@@ -36503,17 +38618,12 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:            "LoweredAtomicOr8",
-               argLen:          3,
-               resultNotInArgs: true,
-               needIntTemp:     true,
-               faultOnNilArg0:  true,
-               hasSideEffects:  true,
-               unsafePoint:     true,
-               asm:             arm64.AORR,
+               name:   "MOVWUloadidx4",
+               argLen: 3,
+               asm:    arm64.AMOVWU,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {1, 939524095},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO
+                               {1, 402653183},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
                                {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
                        },
                        outputs: []outputInfo{
@@ -36522,17 +38632,12 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:            "LoweredAtomicAnd64",
-               argLen:          3,
-               resultNotInArgs: true,
-               needIntTemp:     true,
-               faultOnNilArg0:  true,
-               hasSideEffects:  true,
-               unsafePoint:     true,
-               asm:             arm64.AAND,
+               name:   "MOVDloadidx8",
+               argLen: 3,
+               asm:    arm64.AMOVD,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {1, 939524095},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO
+                               {1, 402653183},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
                                {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
                        },
                        outputs: []outputInfo{
@@ -36541,2090 +38646,1995 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:            "LoweredAtomicOr64",
-               argLen:          3,
-               resultNotInArgs: true,
-               needIntTemp:     true,
-               faultOnNilArg0:  true,
-               hasSideEffects:  true,
-               unsafePoint:     true,
-               asm:             arm64.AORR,
+               name:   "FMOVSloadidx4",
+               argLen: 3,
+               asm:    arm64.AFMOVS,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {1, 939524095},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO
+                               {1, 402653183},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
                                {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
                        },
                        outputs: []outputInfo{
-                               {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
+                               {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
                        },
                },
        },
        {
-               name:            "LoweredAtomicAnd32",
-               argLen:          3,
-               resultNotInArgs: true,
-               needIntTemp:     true,
-               faultOnNilArg0:  true,
-               hasSideEffects:  true,
-               unsafePoint:     true,
-               asm:             arm64.AAND,
+               name:   "FMOVDloadidx8",
+               argLen: 3,
+               asm:    arm64.AFMOVD,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {1, 939524095},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO
+                               {1, 402653183},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
                                {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
                        },
                        outputs: []outputInfo{
-                               {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
+                               {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
                        },
                },
        },
        {
-               name:            "LoweredAtomicOr32",
-               argLen:          3,
-               resultNotInArgs: true,
-               needIntTemp:     true,
-               faultOnNilArg0:  true,
-               hasSideEffects:  true,
-               unsafePoint:     true,
-               asm:             arm64.AORR,
+               name:           "MOVBstore",
+               auxType:        auxSymOff,
+               argLen:         3,
+               faultOnNilArg0: true,
+               symEffect:      SymWrite,
+               asm:            arm64.AMOVB,
                reg: regInfo{
                        inputs: []inputInfo{
                                {1, 939524095},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO
                                {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
                        },
-                       outputs: []outputInfo{
-                               {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
-                       },
                },
        },
        {
-               name:            "LoweredAtomicAnd8Variant",
-               argLen:          3,
-               resultNotInArgs: true,
-               faultOnNilArg0:  true,
-               hasSideEffects:  true,
-               unsafePoint:     true,
+               name:           "MOVHstore",
+               auxType:        auxSymOff,
+               argLen:         3,
+               faultOnNilArg0: true,
+               symEffect:      SymWrite,
+               asm:            arm64.AMOVH,
                reg: regInfo{
                        inputs: []inputInfo{
                                {1, 939524095},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO
                                {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
                        },
-                       outputs: []outputInfo{
-                               {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
-                       },
                },
        },
        {
-               name:            "LoweredAtomicOr8Variant",
-               argLen:          3,
-               resultNotInArgs: true,
-               faultOnNilArg0:  true,
-               hasSideEffects:  true,
+               name:           "MOVWstore",
+               auxType:        auxSymOff,
+               argLen:         3,
+               faultOnNilArg0: true,
+               symEffect:      SymWrite,
+               asm:            arm64.AMOVW,
                reg: regInfo{
                        inputs: []inputInfo{
                                {1, 939524095},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO
                                {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
                        },
-                       outputs: []outputInfo{
-                               {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
-                       },
                },
        },
        {
-               name:            "LoweredAtomicAnd64Variant",
-               argLen:          3,
-               resultNotInArgs: true,
-               faultOnNilArg0:  true,
-               hasSideEffects:  true,
-               unsafePoint:     true,
+               name:           "MOVDstore",
+               auxType:        auxSymOff,
+               argLen:         3,
+               faultOnNilArg0: true,
+               symEffect:      SymWrite,
+               asm:            arm64.AMOVD,
                reg: regInfo{
                        inputs: []inputInfo{
                                {1, 939524095},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO
                                {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
                        },
-                       outputs: []outputInfo{
-                               {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
-                       },
                },
        },
        {
-               name:            "LoweredAtomicOr64Variant",
-               argLen:          3,
-               resultNotInArgs: true,
-               faultOnNilArg0:  true,
-               hasSideEffects:  true,
+               name:           "FMOVSstore",
+               auxType:        auxSymOff,
+               argLen:         3,
+               faultOnNilArg0: true,
+               symEffect:      SymWrite,
+               asm:            arm64.AFMOVS,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {1, 939524095},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO
                                {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
-                       },
-                       outputs: []outputInfo{
-                               {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
+                               {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
                        },
                },
        },
        {
-               name:            "LoweredAtomicAnd32Variant",
-               argLen:          3,
-               resultNotInArgs: true,
-               faultOnNilArg0:  true,
-               hasSideEffects:  true,
-               unsafePoint:     true,
+               name:           "FMOVDstore",
+               auxType:        auxSymOff,
+               argLen:         3,
+               faultOnNilArg0: true,
+               symEffect:      SymWrite,
+               asm:            arm64.AFMOVD,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {1, 939524095},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO
                                {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
-                       },
-                       outputs: []outputInfo{
-                               {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
+                               {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
                        },
                },
        },
        {
-               name:            "LoweredAtomicOr32Variant",
-               argLen:          3,
-               resultNotInArgs: true,
-               faultOnNilArg0:  true,
-               hasSideEffects:  true,
+               name:           "STP",
+               auxType:        auxSymOff,
+               argLen:         4,
+               faultOnNilArg0: true,
+               symEffect:      SymWrite,
+               asm:            arm64.ASTP,
                reg: regInfo{
                        inputs: []inputInfo{
                                {1, 939524095},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO
+                               {2, 939524095},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO
                                {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
                        },
-                       outputs: []outputInfo{
-                               {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
-                       },
                },
        },
        {
-               name:         "LoweredWB",
-               auxType:      auxInt64,
-               argLen:       1,
-               clobberFlags: true,
+               name:           "STPW",
+               auxType:        auxSymOff,
+               argLen:         4,
+               faultOnNilArg0: true,
+               symEffect:      SymWrite,
+               asm:            arm64.ASTPW,
                reg: regInfo{
-                       clobbers: 9223372034975924224, // R16 R17 R30 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
-                       outputs: []outputInfo{
-                               {0, 16777216}, // R25
+                       inputs: []inputInfo{
+                               {1, 939524095},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO
+                               {2, 939524095},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO
+                               {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
                        },
                },
        },
        {
-               name:    "LoweredPanicBoundsA",
-               auxType: auxInt64,
-               argLen:  3,
-               call:    true,
+               name:           "FSTPD",
+               auxType:        auxSymOff,
+               argLen:         4,
+               faultOnNilArg0: true,
+               symEffect:      SymWrite,
+               asm:            arm64.AFSTPD,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 4}, // R2
-                               {1, 8}, // R3
+                               {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
+                               {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {2, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
                        },
                },
        },
        {
-               name:    "LoweredPanicBoundsB",
-               auxType: auxInt64,
-               argLen:  3,
-               call:    true,
+               name:           "FSTPS",
+               auxType:        auxSymOff,
+               argLen:         4,
+               faultOnNilArg0: true,
+               symEffect:      SymWrite,
+               asm:            arm64.AFSTPS,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 2}, // R1
-                               {1, 4}, // R2
+                               {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
+                               {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {2, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
                        },
                },
        },
        {
-               name:    "LoweredPanicBoundsC",
-               auxType: auxInt64,
-               argLen:  3,
-               call:    true,
+               name:   "MOVBstoreidx",
+               argLen: 4,
+               asm:    arm64.AMOVB,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 1}, // R0
-                               {1, 2}, // R1
+                               {1, 939524095},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO
+                               {2, 939524095},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO
+                               {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
                        },
                },
        },
        {
-               name:           "PRFM",
-               auxType:        auxInt64,
-               argLen:         2,
-               hasSideEffects: true,
-               asm:            arm64.APRFM,
+               name:   "MOVHstoreidx",
+               argLen: 4,
+               asm:    arm64.AMOVH,
                reg: regInfo{
                        inputs: []inputInfo{
+                               {1, 939524095},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO
+                               {2, 939524095},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO
                                {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
                        },
                },
        },
        {
-               name:           "DMB",
-               auxType:        auxInt64,
-               argLen:         1,
-               hasSideEffects: true,
-               asm:            arm64.ADMB,
-               reg:            regInfo{},
+               name:   "MOVWstoreidx",
+               argLen: 4,
+               asm:    arm64.AMOVW,
+               reg: regInfo{
+                       inputs: []inputInfo{
+                               {1, 939524095},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO
+                               {2, 939524095},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO
+                               {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
+                       },
+               },
        },
        {
-               name:      "ZERO",
-               argLen:    0,
-               zeroWidth: true,
-               fixedReg:  true,
-               reg:       regInfo{},
+               name:   "MOVDstoreidx",
+               argLen: 4,
+               asm:    arm64.AMOVD,
+               reg: regInfo{
+                       inputs: []inputInfo{
+                               {1, 939524095},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO
+                               {2, 939524095},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO
+                               {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
+                       },
+               },
        },
-
        {
-               name:   "NEGV",
-               argLen: 1,
+               name:   "FMOVSstoreidx",
+               argLen: 4,
+               asm:    arm64.AFMOVS,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
-                       },
-                       outputs: []outputInfo{
-                               {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
+                               {1, 402653183},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
+                               {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
+                               {2, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
                        },
                },
        },
        {
-               name:   "NEGF",
-               argLen: 1,
-               asm:    loong64.ANEGF,
+               name:   "FMOVDstoreidx",
+               argLen: 4,
+               asm:    arm64.AFMOVD,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
-                       },
-                       outputs: []outputInfo{
-                               {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {1, 402653183},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
+                               {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
+                               {2, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
                        },
                },
        },
        {
-               name:   "NEGD",
-               argLen: 1,
-               asm:    loong64.ANEGD,
+               name:   "MOVHstoreidx2",
+               argLen: 4,
+               asm:    arm64.AMOVH,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
-                       },
-                       outputs: []outputInfo{
-                               {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {1, 939524095},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO
+                               {2, 939524095},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO
+                               {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
                        },
                },
        },
        {
-               name:   "SQRTD",
-               argLen: 1,
-               asm:    loong64.ASQRTD,
+               name:   "MOVWstoreidx4",
+               argLen: 4,
+               asm:    arm64.AMOVW,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
-                       },
-                       outputs: []outputInfo{
-                               {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {1, 939524095},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO
+                               {2, 939524095},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO
+                               {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
                        },
                },
        },
        {
-               name:   "SQRTF",
-               argLen: 1,
-               asm:    loong64.ASQRTF,
+               name:   "MOVDstoreidx8",
+               argLen: 4,
+               asm:    arm64.AMOVD,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
-                       },
-                       outputs: []outputInfo{
-                               {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {1, 939524095},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO
+                               {2, 939524095},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO
+                               {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
                        },
                },
        },
        {
-               name:   "ABSD",
-               argLen: 1,
-               asm:    loong64.AABSD,
+               name:   "FMOVSstoreidx4",
+               argLen: 4,
+               asm:    arm64.AFMOVS,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
-                       },
-                       outputs: []outputInfo{
-                               {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {1, 402653183},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
+                               {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
+                               {2, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
                        },
                },
        },
        {
-               name:   "CLZW",
-               argLen: 1,
-               asm:    loong64.ACLZW,
+               name:   "FMOVDstoreidx8",
+               argLen: 4,
+               asm:    arm64.AFMOVD,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
-                       },
-                       outputs: []outputInfo{
-                               {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
+                               {1, 402653183},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
+                               {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
+                               {2, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
                        },
                },
        },
        {
-               name:   "CLZV",
+               name:   "FMOVDgpfp",
                argLen: 1,
-               asm:    loong64.ACLZV,
+               asm:    arm64.AFMOVD,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
+                               {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
                        },
                        outputs: []outputInfo{
-                               {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
+                               {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
                        },
                },
        },
        {
-               name:   "CTZW",
+               name:   "FMOVDfpgp",
                argLen: 1,
-               asm:    loong64.ACTZW,
+               asm:    arm64.AFMOVD,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
+                               {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
                        },
                        outputs: []outputInfo{
-                               {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
+                               {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
                        },
                },
        },
        {
-               name:   "CTZV",
+               name:   "FMOVSgpfp",
                argLen: 1,
-               asm:    loong64.ACTZV,
+               asm:    arm64.AFMOVS,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
+                               {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
                        },
                        outputs: []outputInfo{
-                               {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
+                               {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
                        },
                },
        },
        {
-               name:   "REVB2H",
+               name:   "FMOVSfpgp",
                argLen: 1,
-               asm:    loong64.AREVB2H,
+               asm:    arm64.AFMOVS,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
+                               {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
                        },
                        outputs: []outputInfo{
-                               {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
+                               {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
                        },
                },
        },
        {
-               name:   "REVB2W",
+               name:   "MOVBreg",
                argLen: 1,
-               asm:    loong64.AREVB2W,
+               asm:    arm64.AMOVB,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
+                               {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
                        },
                        outputs: []outputInfo{
-                               {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
+                               {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
                        },
                },
        },
        {
-               name:   "REVBV",
+               name:   "MOVBUreg",
                argLen: 1,
-               asm:    loong64.AREVBV,
+               asm:    arm64.AMOVBU,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
+                               {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
                        },
                        outputs: []outputInfo{
-                               {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
+                               {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
                        },
                },
        },
        {
-               name:   "BITREV4B",
+               name:   "MOVHreg",
                argLen: 1,
-               asm:    loong64.ABITREV4B,
+               asm:    arm64.AMOVH,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
+                               {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
                        },
                        outputs: []outputInfo{
-                               {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
+                               {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
                        },
                },
        },
        {
-               name:   "BITREVW",
+               name:   "MOVHUreg",
                argLen: 1,
-               asm:    loong64.ABITREVW,
+               asm:    arm64.AMOVHU,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
+                               {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
                        },
                        outputs: []outputInfo{
-                               {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
+                               {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
                        },
                },
        },
        {
-               name:   "BITREVV",
+               name:   "MOVWreg",
                argLen: 1,
-               asm:    loong64.ABITREVV,
+               asm:    arm64.AMOVW,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
+                               {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
                        },
                        outputs: []outputInfo{
-                               {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
+                               {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
                        },
                },
        },
        {
-               name:   "VPCNT64",
+               name:   "MOVWUreg",
                argLen: 1,
-               asm:    loong64.AVPCNTV,
+               asm:    arm64.AMOVWU,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
                        },
                        outputs: []outputInfo{
-                               {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
                        },
                },
        },
        {
-               name:   "VPCNT32",
+               name:   "MOVDreg",
                argLen: 1,
-               asm:    loong64.AVPCNTW,
+               asm:    arm64.AMOVD,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
                        },
                        outputs: []outputInfo{
-                               {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
                        },
                },
        },
        {
-               name:   "VPCNT16",
-               argLen: 1,
-               asm:    loong64.AVPCNTH,
+               name:         "MOVDnop",
+               argLen:       1,
+               resultInArg0: true,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
                        },
                        outputs: []outputInfo{
-                               {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
                        },
                },
        },
        {
-               name:        "ADDV",
-               argLen:      2,
-               commutative: true,
-               asm:         loong64.AADDVU,
+               name:   "SCVTFWS",
+               argLen: 1,
+               asm:    arm64.ASCVTFWS,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
-                               {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
+                               {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
                        },
                        outputs: []outputInfo{
-                               {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
+                               {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
                        },
                },
        },
        {
-               name:    "ADDVconst",
-               auxType: auxInt64,
-               argLen:  1,
-               asm:     loong64.AADDVU,
+               name:   "SCVTFWD",
+               argLen: 1,
+               asm:    arm64.ASCVTFWD,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 1073741820}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
+                               {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
                        },
                        outputs: []outputInfo{
-                               {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
+                               {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
                        },
                },
        },
        {
-               name:   "SUBV",
-               argLen: 2,
-               asm:    loong64.ASUBVU,
+               name:   "UCVTFWS",
+               argLen: 1,
+               asm:    arm64.AUCVTFWS,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
-                               {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
+                               {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
                        },
                        outputs: []outputInfo{
-                               {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
+                               {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
                        },
                },
        },
        {
-               name:    "SUBVconst",
-               auxType: auxInt64,
-               argLen:  1,
-               asm:     loong64.ASUBVU,
+               name:   "UCVTFWD",
+               argLen: 1,
+               asm:    arm64.AUCVTFWD,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
+                               {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
                        },
                        outputs: []outputInfo{
-                               {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
+                               {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
                        },
                },
        },
        {
-               name:        "MULV",
-               argLen:      2,
-               commutative: true,
-               asm:         loong64.AMULV,
+               name:   "SCVTFS",
+               argLen: 1,
+               asm:    arm64.ASCVTFS,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
-                               {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
+                               {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
                        },
                        outputs: []outputInfo{
-                               {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
+                               {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
                        },
                },
        },
        {
-               name:        "MULHV",
-               argLen:      2,
-               commutative: true,
-               asm:         loong64.AMULHV,
+               name:   "SCVTFD",
+               argLen: 1,
+               asm:    arm64.ASCVTFD,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
-                               {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
+                               {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
                        },
                        outputs: []outputInfo{
-                               {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
+                               {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
                        },
                },
        },
        {
-               name:        "MULHVU",
-               argLen:      2,
-               commutative: true,
-               asm:         loong64.AMULHVU,
+               name:   "UCVTFS",
+               argLen: 1,
+               asm:    arm64.AUCVTFS,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
-                               {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
+                               {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
                        },
                        outputs: []outputInfo{
-                               {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
+                               {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
                        },
                },
        },
        {
-               name:   "DIVV",
-               argLen: 2,
-               asm:    loong64.ADIVV,
+               name:   "UCVTFD",
+               argLen: 1,
+               asm:    arm64.AUCVTFD,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
-                               {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
+                               {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
                        },
                        outputs: []outputInfo{
-                               {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
+                               {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
                        },
                },
        },
        {
-               name:   "DIVVU",
-               argLen: 2,
-               asm:    loong64.ADIVVU,
+               name:   "FCVTZSSW",
+               argLen: 1,
+               asm:    arm64.AFCVTZSSW,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
-                               {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
+                               {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
                        },
                        outputs: []outputInfo{
-                               {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
+                               {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
                        },
                },
        },
        {
-               name:   "REMV",
-               argLen: 2,
-               asm:    loong64.AREMV,
+               name:   "FCVTZSDW",
+               argLen: 1,
+               asm:    arm64.AFCVTZSDW,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
-                               {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
+                               {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
                        },
                        outputs: []outputInfo{
-                               {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
+                               {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
                        },
                },
        },
        {
-               name:   "REMVU",
-               argLen: 2,
-               asm:    loong64.AREMVU,
+               name:   "FCVTZUSW",
+               argLen: 1,
+               asm:    arm64.AFCVTZUSW,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
-                               {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
+                               {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
                        },
                        outputs: []outputInfo{
-                               {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
+                               {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
                        },
                },
        },
        {
-               name:        "ADDF",
-               argLen:      2,
-               commutative: true,
-               asm:         loong64.AADDF,
+               name:   "FCVTZUDW",
+               argLen: 1,
+               asm:    arm64.AFCVTZUDW,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
-                               {1, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
                        },
                        outputs: []outputInfo{
-                               {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
                        },
                },
        },
        {
-               name:        "ADDD",
-               argLen:      2,
-               commutative: true,
-               asm:         loong64.AADDD,
+               name:   "FCVTZSS",
+               argLen: 1,
+               asm:    arm64.AFCVTZSS,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
-                               {1, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
                        },
                        outputs: []outputInfo{
-                               {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
                        },
                },
        },
        {
-               name:   "SUBF",
-               argLen: 2,
-               asm:    loong64.ASUBF,
+               name:   "FCVTZSD",
+               argLen: 1,
+               asm:    arm64.AFCVTZSD,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
-                               {1, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
                        },
                        outputs: []outputInfo{
-                               {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
                        },
                },
        },
        {
-               name:   "SUBD",
-               argLen: 2,
-               asm:    loong64.ASUBD,
+               name:   "FCVTZUS",
+               argLen: 1,
+               asm:    arm64.AFCVTZUS,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
-                               {1, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
                        },
                        outputs: []outputInfo{
-                               {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
                        },
                },
        },
        {
-               name:        "MULF",
-               argLen:      2,
-               commutative: true,
-               asm:         loong64.AMULF,
+               name:   "FCVTZUD",
+               argLen: 1,
+               asm:    arm64.AFCVTZUD,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
-                               {1, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
                        },
                        outputs: []outputInfo{
-                               {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
                        },
                },
        },
        {
-               name:        "MULD",
-               argLen:      2,
-               commutative: true,
-               asm:         loong64.AMULD,
+               name:   "FCVTSD",
+               argLen: 1,
+               asm:    arm64.AFCVTSD,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
-                               {1, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
                        },
                        outputs: []outputInfo{
-                               {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
                        },
                },
        },
        {
-               name:   "DIVF",
-               argLen: 2,
-               asm:    loong64.ADIVF,
+               name:   "FCVTDS",
+               argLen: 1,
+               asm:    arm64.AFCVTDS,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
-                               {1, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
                        },
                        outputs: []outputInfo{
-                               {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
                        },
                },
        },
        {
-               name:   "DIVD",
-               argLen: 2,
-               asm:    loong64.ADIVD,
+               name:   "FRINTAD",
+               argLen: 1,
+               asm:    arm64.AFRINTAD,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
-                               {1, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
                        },
                        outputs: []outputInfo{
-                               {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
                        },
                },
        },
        {
-               name:        "AND",
-               argLen:      2,
-               commutative: true,
-               asm:         loong64.AAND,
+               name:   "FRINTMD",
+               argLen: 1,
+               asm:    arm64.AFRINTMD,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
-                               {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
+                               {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
                        },
                        outputs: []outputInfo{
-                               {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
+                               {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
                        },
                },
        },
        {
-               name:    "ANDconst",
-               auxType: auxInt64,
-               argLen:  1,
-               asm:     loong64.AAND,
+               name:   "FRINTND",
+               argLen: 1,
+               asm:    arm64.AFRINTND,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
+                               {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
                        },
                        outputs: []outputInfo{
-                               {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
+                               {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
                        },
                },
        },
        {
-               name:        "OR",
-               argLen:      2,
-               commutative: true,
-               asm:         loong64.AOR,
+               name:   "FRINTPD",
+               argLen: 1,
+               asm:    arm64.AFRINTPD,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
-                               {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
+                               {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
                        },
                        outputs: []outputInfo{
-                               {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
+                               {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
                        },
                },
        },
        {
-               name:    "ORconst",
-               auxType: auxInt64,
-               argLen:  1,
-               asm:     loong64.AOR,
+               name:   "FRINTZD",
+               argLen: 1,
+               asm:    arm64.AFRINTZD,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
+                               {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
                        },
                        outputs: []outputInfo{
-                               {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
+                               {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
                        },
                },
        },
        {
-               name:        "XOR",
-               argLen:      2,
-               commutative: true,
-               asm:         loong64.AXOR,
+               name:    "CSEL",
+               auxType: auxCCop,
+               argLen:  3,
+               asm:     arm64.ACSEL,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
-                               {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
+                               {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
+                               {1, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
                        },
                        outputs: []outputInfo{
-                               {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
+                               {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
                        },
                },
        },
        {
-               name:    "XORconst",
-               auxType: auxInt64,
-               argLen:  1,
-               asm:     loong64.AXOR,
+               name:    "CSEL0",
+               auxType: auxCCop,
+               argLen:  2,
+               asm:     arm64.ACSEL,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
+                               {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
                        },
                        outputs: []outputInfo{
-                               {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
+                               {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
                        },
                },
        },
        {
-               name:        "NOR",
-               argLen:      2,
-               commutative: true,
-               asm:         loong64.ANOR,
+               name:    "CSINC",
+               auxType: auxCCop,
+               argLen:  3,
+               asm:     arm64.ACSINC,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
-                               {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
+                               {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
+                               {1, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
                        },
                        outputs: []outputInfo{
-                               {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
+                               {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
                        },
                },
        },
        {
-               name:    "NORconst",
-               auxType: auxInt64,
-               argLen:  1,
-               asm:     loong64.ANOR,
+               name:    "CSINV",
+               auxType: auxCCop,
+               argLen:  3,
+               asm:     arm64.ACSINV,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
+                               {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
+                               {1, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
                        },
                        outputs: []outputInfo{
-                               {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
+                               {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
                        },
                },
        },
        {
-               name:   "ANDN",
-               argLen: 2,
-               asm:    loong64.AANDN,
+               name:    "CSNEG",
+               auxType: auxCCop,
+               argLen:  3,
+               asm:     arm64.ACSNEG,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
-                               {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
+                               {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
+                               {1, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
                        },
                        outputs: []outputInfo{
-                               {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
+                               {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
                        },
                },
        },
        {
-               name:   "ORN",
-               argLen: 2,
-               asm:    loong64.AORN,
+               name:    "CSETM",
+               auxType: auxCCop,
+               argLen:  1,
+               asm:     arm64.ACSETM,
                reg: regInfo{
-                       inputs: []inputInfo{
-                               {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
-                               {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
-                       },
                        outputs: []outputInfo{
-                               {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
+                               {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
                        },
                },
        },
        {
-               name:        "FMADDF",
-               argLen:      3,
-               commutative: true,
-               asm:         loong64.AFMADDF,
+               name:         "CALLstatic",
+               auxType:      auxCallOff,
+               argLen:       -1,
+               clobberFlags: true,
+               call:         true,
                reg: regInfo{
-                       inputs: []inputInfo{
-                               {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
-                               {1, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
-                               {2, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
-                       },
-                       outputs: []outputInfo{
-                               {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
-                       },
+                       clobbers: 9223372035109945343, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
                },
        },
        {
-               name:        "FMADDD",
-               argLen:      3,
-               commutative: true,
-               asm:         loong64.AFMADDD,
+               name:         "CALLtail",
+               auxType:      auxCallOff,
+               argLen:       -1,
+               clobberFlags: true,
+               call:         true,
+               tailCall:     true,
                reg: regInfo{
-                       inputs: []inputInfo{
-                               {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
-                               {1, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
-                               {2, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
-                       },
-                       outputs: []outputInfo{
-                               {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
-                       },
+                       clobbers: 9223372035109945343, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
                },
        },
        {
-               name:        "FMSUBF",
-               argLen:      3,
-               commutative: true,
-               asm:         loong64.AFMSUBF,
+               name:         "CALLclosure",
+               auxType:      auxCallOff,
+               argLen:       -1,
+               clobberFlags: true,
+               call:         true,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
-                               {1, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
-                               {2, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
-                       },
-                       outputs: []outputInfo{
-                               {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {1, 33554432},   // R26
+                               {0, 1409286143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 SP
                        },
+                       clobbers: 9223372035109945343, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
                },
        },
        {
-               name:        "FMSUBD",
-               argLen:      3,
-               commutative: true,
-               asm:         loong64.AFMSUBD,
+               name:         "CALLinter",
+               auxType:      auxCallOff,
+               argLen:       -1,
+               clobberFlags: true,
+               call:         true,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
-                               {1, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
-                               {2, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
-                       },
-                       outputs: []outputInfo{
-                               {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
                        },
+                       clobbers: 9223372035109945343, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
                },
        },
        {
-               name:        "FNMADDF",
-               argLen:      3,
-               commutative: true,
-               asm:         loong64.AFNMADDF,
+               name:           "LoweredNilCheck",
+               argLen:         2,
+               nilCheck:       true,
+               faultOnNilArg0: true,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
-                               {1, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
-                               {2, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
                        },
+               },
+       },
+       {
+               name:   "Equal",
+               argLen: 1,
+               reg: regInfo{
                        outputs: []outputInfo{
-                               {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
                        },
                },
        },
        {
-               name:        "FNMADDD",
-               argLen:      3,
-               commutative: true,
-               asm:         loong64.AFNMADDD,
+               name:   "NotEqual",
+               argLen: 1,
                reg: regInfo{
-                       inputs: []inputInfo{
-                               {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
-                               {1, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
-                               {2, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
-                       },
                        outputs: []outputInfo{
-                               {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
                        },
                },
        },
        {
-               name:        "FNMSUBF",
-               argLen:      3,
-               commutative: true,
-               asm:         loong64.AFNMSUBF,
+               name:   "LessThan",
+               argLen: 1,
                reg: regInfo{
-                       inputs: []inputInfo{
-                               {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
-                               {1, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
-                               {2, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
-                       },
                        outputs: []outputInfo{
-                               {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
                        },
                },
        },
        {
-               name:        "FNMSUBD",
-               argLen:      3,
-               commutative: true,
-               asm:         loong64.AFNMSUBD,
+               name:   "LessEqual",
+               argLen: 1,
                reg: regInfo{
-                       inputs: []inputInfo{
-                               {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
-                               {1, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
-                               {2, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
-                       },
                        outputs: []outputInfo{
-                               {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
                        },
                },
        },
        {
-               name:            "FMINF",
-               argLen:          2,
-               commutative:     true,
-               resultNotInArgs: true,
-               asm:             loong64.AFMINF,
+               name:   "GreaterThan",
+               argLen: 1,
                reg: regInfo{
-                       inputs: []inputInfo{
-                               {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
-                               {1, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
-                       },
                        outputs: []outputInfo{
-                               {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
                        },
                },
        },
        {
-               name:            "FMIND",
-               argLen:          2,
-               commutative:     true,
-               resultNotInArgs: true,
-               asm:             loong64.AFMIND,
+               name:   "GreaterEqual",
+               argLen: 1,
                reg: regInfo{
-                       inputs: []inputInfo{
-                               {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
-                               {1, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
-                       },
                        outputs: []outputInfo{
-                               {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
                        },
                },
        },
        {
-               name:            "FMAXF",
-               argLen:          2,
-               commutative:     true,
-               resultNotInArgs: true,
-               asm:             loong64.AFMAXF,
+               name:   "LessThanU",
+               argLen: 1,
                reg: regInfo{
-                       inputs: []inputInfo{
-                               {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
-                               {1, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
-                       },
                        outputs: []outputInfo{
-                               {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
                        },
                },
        },
        {
-               name:            "FMAXD",
-               argLen:          2,
-               commutative:     true,
-               resultNotInArgs: true,
-               asm:             loong64.AFMAXD,
+               name:   "LessEqualU",
+               argLen: 1,
                reg: regInfo{
-                       inputs: []inputInfo{
-                               {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
-                               {1, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
-                       },
                        outputs: []outputInfo{
-                               {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
                        },
                },
        },
        {
-               name:   "MASKEQZ",
-               argLen: 2,
-               asm:    loong64.AMASKEQZ,
+               name:   "GreaterThanU",
+               argLen: 1,
                reg: regInfo{
-                       inputs: []inputInfo{
-                               {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
-                               {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
-                       },
                        outputs: []outputInfo{
-                               {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
+                               {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
                        },
                },
        },
        {
-               name:   "MASKNEZ",
-               argLen: 2,
-               asm:    loong64.AMASKNEZ,
+               name:   "GreaterEqualU",
+               argLen: 1,
                reg: regInfo{
-                       inputs: []inputInfo{
-                               {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
-                               {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
-                       },
                        outputs: []outputInfo{
-                               {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
+                               {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
                        },
                },
        },
        {
-               name:   "FCOPYSGD",
-               argLen: 2,
-               asm:    loong64.AFCOPYSGD,
+               name:   "LessThanF",
+               argLen: 1,
                reg: regInfo{
-                       inputs: []inputInfo{
-                               {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
-                               {1, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
-                       },
                        outputs: []outputInfo{
-                               {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
                        },
                },
        },
        {
-               name:   "SLL",
-               argLen: 2,
-               asm:    loong64.ASLL,
+               name:   "LessEqualF",
+               argLen: 1,
                reg: regInfo{
-                       inputs: []inputInfo{
-                               {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
-                               {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
-                       },
                        outputs: []outputInfo{
-                               {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
+                               {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
                        },
                },
        },
        {
-               name:   "SLLV",
-               argLen: 2,
-               asm:    loong64.ASLLV,
+               name:   "GreaterThanF",
+               argLen: 1,
                reg: regInfo{
-                       inputs: []inputInfo{
-                               {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
-                               {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
-                       },
                        outputs: []outputInfo{
-                               {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
+                               {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
                        },
                },
        },
        {
-               name:    "SLLconst",
-               auxType: auxInt64,
-               argLen:  1,
-               asm:     loong64.ASLL,
+               name:   "GreaterEqualF",
+               argLen: 1,
                reg: regInfo{
-                       inputs: []inputInfo{
-                               {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
-                       },
                        outputs: []outputInfo{
-                               {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
+                               {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
                        },
                },
        },
        {
-               name:    "SLLVconst",
-               auxType: auxInt64,
-               argLen:  1,
-               asm:     loong64.ASLLV,
+               name:   "NotLessThanF",
+               argLen: 1,
                reg: regInfo{
-                       inputs: []inputInfo{
-                               {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
-                       },
                        outputs: []outputInfo{
-                               {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
+                               {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
                        },
                },
        },
        {
-               name:   "SRL",
-               argLen: 2,
-               asm:    loong64.ASRL,
+               name:   "NotLessEqualF",
+               argLen: 1,
                reg: regInfo{
-                       inputs: []inputInfo{
-                               {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
-                               {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
-                       },
                        outputs: []outputInfo{
-                               {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
+                               {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
                        },
                },
        },
        {
-               name:   "SRLV",
-               argLen: 2,
-               asm:    loong64.ASRLV,
+               name:   "NotGreaterThanF",
+               argLen: 1,
                reg: regInfo{
-                       inputs: []inputInfo{
-                               {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
-                               {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
-                       },
                        outputs: []outputInfo{
-                               {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
+                               {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
                        },
                },
        },
        {
-               name:    "SRLconst",
-               auxType: auxInt64,
-               argLen:  1,
-               asm:     loong64.ASRL,
+               name:   "NotGreaterEqualF",
+               argLen: 1,
                reg: regInfo{
-                       inputs: []inputInfo{
-                               {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
-                       },
                        outputs: []outputInfo{
-                               {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
+                               {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
                        },
                },
        },
        {
-               name:    "SRLVconst",
-               auxType: auxInt64,
-               argLen:  1,
-               asm:     loong64.ASRLV,
+               name:   "LessThanNoov",
+               argLen: 1,
                reg: regInfo{
-                       inputs: []inputInfo{
-                               {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
-                       },
                        outputs: []outputInfo{
-                               {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
+                               {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
                        },
                },
        },
        {
-               name:   "SRA",
-               argLen: 2,
-               asm:    loong64.ASRA,
+               name:   "GreaterEqualNoov",
+               argLen: 1,
                reg: regInfo{
-                       inputs: []inputInfo{
-                               {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
-                               {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
-                       },
                        outputs: []outputInfo{
-                               {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
+                               {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
                        },
                },
        },
        {
-               name:   "SRAV",
-               argLen: 2,
-               asm:    loong64.ASRAV,
+               name:        "DUFFZERO",
+               auxType:     auxInt64,
+               argLen:      2,
+               unsafePoint: true,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
-                               {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
-                       },
-                       outputs: []outputInfo{
-                               {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
+                               {0, 524288}, // R20
                        },
+                       clobbers: 269156352, // R16 R17 R20 R30
                },
        },
        {
-               name:    "SRAconst",
-               auxType: auxInt64,
-               argLen:  1,
-               asm:     loong64.ASRA,
+               name:           "LoweredZero",
+               argLen:         3,
+               clobberFlags:   true,
+               faultOnNilArg0: true,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
-                       },
-                       outputs: []outputInfo{
-                               {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
+                               {0, 65536},     // R16
+                               {1, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
                        },
+                       clobbers: 65536, // R16
                },
        },
        {
-               name:    "SRAVconst",
-               auxType: auxInt64,
-               argLen:  1,
-               asm:     loong64.ASRAV,
+               name:        "DUFFCOPY",
+               auxType:     auxInt64,
+               argLen:      3,
+               unsafePoint: true,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
-                       },
-                       outputs: []outputInfo{
-                               {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
+                               {0, 1048576}, // R21
+                               {1, 524288},  // R20
                        },
+                       clobbers: 303759360, // R16 R17 R20 R21 R26 R30
                },
        },
        {
-               name:   "ROTR",
-               argLen: 2,
-               asm:    loong64.AROTR,
+               name:           "LoweredMove",
+               argLen:         4,
+               clobberFlags:   true,
+               faultOnNilArg0: true,
+               faultOnNilArg1: true,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
-                               {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
-                       },
-                       outputs: []outputInfo{
-                               {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
+                               {0, 131072},    // R17
+                               {1, 65536},     // R16
+                               {2, 318767103}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R26 R30
                        },
+                       clobbers: 16973824, // R16 R17 R25
                },
        },
        {
-               name:   "ROTRV",
-               argLen: 2,
-               asm:    loong64.AROTRV,
+               name:      "LoweredGetClosurePtr",
+               argLen:    0,
+               zeroWidth: true,
                reg: regInfo{
-                       inputs: []inputInfo{
-                               {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
-                               {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
-                       },
                        outputs: []outputInfo{
-                               {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
+                               {0, 33554432}, // R26
                        },
                },
        },
        {
-               name:    "ROTRconst",
-               auxType: auxInt64,
-               argLen:  1,
-               asm:     loong64.AROTR,
+               name:              "LoweredGetCallerSP",
+               argLen:            1,
+               rematerializeable: true,
                reg: regInfo{
-                       inputs: []inputInfo{
-                               {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
-                       },
                        outputs: []outputInfo{
-                               {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
+                               {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
                        },
                },
        },
        {
-               name:    "ROTRVconst",
-               auxType: auxInt64,
-               argLen:  1,
-               asm:     loong64.AROTRV,
+               name:              "LoweredGetCallerPC",
+               argLen:            0,
+               rematerializeable: true,
                reg: regInfo{
-                       inputs: []inputInfo{
-                               {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
-                       },
                        outputs: []outputInfo{
-                               {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
+                               {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
                        },
                },
        },
        {
-               name:   "SGT",
-               argLen: 2,
-               asm:    loong64.ASGT,
-               reg: regInfo{
-                       inputs: []inputInfo{
-                               {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
-                               {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
-                       },
-                       outputs: []outputInfo{
-                               {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
-                       },
-               },
+               name:    "FlagConstant",
+               auxType: auxFlagConstant,
+               argLen:  0,
+               reg:     regInfo{},
        },
        {
-               name:    "SGTconst",
-               auxType: auxInt64,
-               argLen:  1,
-               asm:     loong64.ASGT,
+               name:   "InvertFlags",
+               argLen: 1,
+               reg:    regInfo{},
+       },
+       {
+               name:           "LDAR",
+               argLen:         2,
+               faultOnNilArg0: true,
+               asm:            arm64.ALDAR,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
+                               {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
                        },
                        outputs: []outputInfo{
-                               {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
+                               {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
                        },
                },
        },
        {
-               name:   "SGTU",
-               argLen: 2,
-               asm:    loong64.ASGTU,
+               name:           "LDARB",
+               argLen:         2,
+               faultOnNilArg0: true,
+               asm:            arm64.ALDARB,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
-                               {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
+                               {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
                        },
                        outputs: []outputInfo{
-                               {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
+                               {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
                        },
                },
        },
        {
-               name:    "SGTUconst",
-               auxType: auxInt64,
-               argLen:  1,
-               asm:     loong64.ASGTU,
+               name:           "LDARW",
+               argLen:         2,
+               faultOnNilArg0: true,
+               asm:            arm64.ALDARW,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
+                               {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
                        },
                        outputs: []outputInfo{
-                               {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
+                               {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
                        },
                },
        },
        {
-               name:   "CMPEQF",
-               argLen: 2,
-               asm:    loong64.ACMPEQF,
+               name:           "STLRB",
+               argLen:         3,
+               faultOnNilArg0: true,
+               hasSideEffects: true,
+               asm:            arm64.ASTLRB,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
-                               {1, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {1, 939524095},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO
+                               {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
                        },
                },
        },
        {
-               name:   "CMPEQD",
-               argLen: 2,
-               asm:    loong64.ACMPEQD,
+               name:           "STLR",
+               argLen:         3,
+               faultOnNilArg0: true,
+               hasSideEffects: true,
+               asm:            arm64.ASTLR,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
-                               {1, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {1, 939524095},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO
+                               {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
                        },
                },
        },
        {
-               name:   "CMPGEF",
-               argLen: 2,
-               asm:    loong64.ACMPGEF,
+               name:           "STLRW",
+               argLen:         3,
+               faultOnNilArg0: true,
+               hasSideEffects: true,
+               asm:            arm64.ASTLRW,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
-                               {1, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {1, 939524095},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO
+                               {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
                        },
                },
        },
        {
-               name:   "CMPGED",
-               argLen: 2,
-               asm:    loong64.ACMPGED,
+               name:            "LoweredAtomicExchange64",
+               argLen:          3,
+               resultNotInArgs: true,
+               faultOnNilArg0:  true,
+               hasSideEffects:  true,
+               unsafePoint:     true,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
-                               {1, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {1, 939524095},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO
+                               {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
+                       },
+                       outputs: []outputInfo{
+                               {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
                        },
                },
        },
        {
-               name:   "CMPGTF",
-               argLen: 2,
-               asm:    loong64.ACMPGTF,
+               name:            "LoweredAtomicExchange32",
+               argLen:          3,
+               resultNotInArgs: true,
+               faultOnNilArg0:  true,
+               hasSideEffects:  true,
+               unsafePoint:     true,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
-                               {1, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {1, 939524095},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO
+                               {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
+                       },
+                       outputs: []outputInfo{
+                               {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
                        },
                },
        },
        {
-               name:   "CMPGTD",
-               argLen: 2,
-               asm:    loong64.ACMPGTD,
+               name:            "LoweredAtomicExchange8",
+               argLen:          3,
+               resultNotInArgs: true,
+               faultOnNilArg0:  true,
+               hasSideEffects:  true,
+               unsafePoint:     true,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
-                               {1, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {1, 939524095},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO
+                               {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
+                       },
+                       outputs: []outputInfo{
+                               {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
                        },
                },
        },
        {
-               name:    "BSTRPICKW",
-               auxType: auxInt64,
-               argLen:  1,
-               asm:     loong64.ABSTRPICKW,
+               name:            "LoweredAtomicExchange64Variant",
+               argLen:          3,
+               resultNotInArgs: true,
+               faultOnNilArg0:  true,
+               hasSideEffects:  true,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
+                               {1, 939524095},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO
+                               {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
                        },
                        outputs: []outputInfo{
-                               {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
+                               {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
                        },
                },
        },
        {
-               name:    "BSTRPICKV",
-               auxType: auxInt64,
-               argLen:  1,
-               asm:     loong64.ABSTRPICKV,
+               name:            "LoweredAtomicExchange32Variant",
+               argLen:          3,
+               resultNotInArgs: true,
+               faultOnNilArg0:  true,
+               hasSideEffects:  true,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
+                               {1, 939524095},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO
+                               {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
                        },
                        outputs: []outputInfo{
-                               {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
+                               {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
                        },
                },
        },
        {
-               name:              "MOVVconst",
-               auxType:           auxInt64,
-               argLen:            0,
-               rematerializeable: true,
-               asm:               loong64.AMOVV,
+               name:            "LoweredAtomicExchange8Variant",
+               argLen:          3,
+               resultNotInArgs: true,
+               faultOnNilArg0:  true,
+               hasSideEffects:  true,
+               unsafePoint:     true,
                reg: regInfo{
+                       inputs: []inputInfo{
+                               {1, 939524095},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO
+                               {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
+                       },
                        outputs: []outputInfo{
-                               {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
+                               {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
                        },
                },
        },
        {
-               name:              "MOVFconst",
-               auxType:           auxFloat64,
-               argLen:            0,
-               rematerializeable: true,
-               asm:               loong64.AMOVF,
+               name:            "LoweredAtomicAdd64",
+               argLen:          3,
+               resultNotInArgs: true,
+               faultOnNilArg0:  true,
+               hasSideEffects:  true,
+               unsafePoint:     true,
                reg: regInfo{
+                       inputs: []inputInfo{
+                               {1, 939524095},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO
+                               {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
+                       },
                        outputs: []outputInfo{
-                               {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
                        },
                },
        },
        {
-               name:              "MOVDconst",
-               auxType:           auxFloat64,
-               argLen:            0,
-               rematerializeable: true,
-               asm:               loong64.AMOVD,
+               name:            "LoweredAtomicAdd32",
+               argLen:          3,
+               resultNotInArgs: true,
+               faultOnNilArg0:  true,
+               hasSideEffects:  true,
+               unsafePoint:     true,
                reg: regInfo{
+                       inputs: []inputInfo{
+                               {1, 939524095},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO
+                               {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
+                       },
                        outputs: []outputInfo{
-                               {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
                        },
                },
        },
        {
-               name:              "MOVVaddr",
-               auxType:           auxSymOff,
-               argLen:            1,
-               rematerializeable: true,
-               symEffect:         SymAddr,
-               asm:               loong64.AMOVV,
+               name:            "LoweredAtomicAdd64Variant",
+               argLen:          3,
+               resultNotInArgs: true,
+               faultOnNilArg0:  true,
+               hasSideEffects:  true,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 4611686018427387908}, // SP SB
+                               {1, 939524095},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO
+                               {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
                        },
                        outputs: []outputInfo{
-                               {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
+                               {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
                        },
                },
        },
        {
-               name:           "MOVBload",
-               auxType:        auxSymOff,
-               argLen:         2,
-               faultOnNilArg0: true,
-               symEffect:      SymRead,
-               asm:            loong64.AMOVB,
+               name:            "LoweredAtomicAdd32Variant",
+               argLen:          3,
+               resultNotInArgs: true,
+               faultOnNilArg0:  true,
+               hasSideEffects:  true,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
+                               {1, 939524095},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO
+                               {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
                        },
                        outputs: []outputInfo{
-                               {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
+                               {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
                        },
                },
        },
        {
-               name:           "MOVBUload",
-               auxType:        auxSymOff,
-               argLen:         2,
-               faultOnNilArg0: true,
-               symEffect:      SymRead,
-               asm:            loong64.AMOVBU,
+               name:            "LoweredAtomicCas64",
+               argLen:          4,
+               resultNotInArgs: true,
+               clobberFlags:    true,
+               faultOnNilArg0:  true,
+               hasSideEffects:  true,
+               unsafePoint:     true,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
+                               {1, 939524095},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO
+                               {2, 939524095},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO
+                               {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
                        },
                        outputs: []outputInfo{
-                               {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
+                               {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
                        },
                },
        },
        {
-               name:           "MOVHload",
-               auxType:        auxSymOff,
-               argLen:         2,
-               faultOnNilArg0: true,
-               symEffect:      SymRead,
-               asm:            loong64.AMOVH,
+               name:            "LoweredAtomicCas32",
+               argLen:          4,
+               resultNotInArgs: true,
+               clobberFlags:    true,
+               faultOnNilArg0:  true,
+               hasSideEffects:  true,
+               unsafePoint:     true,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
+                               {1, 939524095},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO
+                               {2, 939524095},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO
+                               {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
                        },
                        outputs: []outputInfo{
-                               {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
+                               {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
                        },
                },
        },
        {
-               name:           "MOVHUload",
-               auxType:        auxSymOff,
-               argLen:         2,
-               faultOnNilArg0: true,
-               symEffect:      SymRead,
-               asm:            loong64.AMOVHU,
+               name:            "LoweredAtomicCas64Variant",
+               argLen:          4,
+               resultNotInArgs: true,
+               clobberFlags:    true,
+               faultOnNilArg0:  true,
+               hasSideEffects:  true,
+               unsafePoint:     true,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
+                               {1, 939524095},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO
+                               {2, 939524095},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO
+                               {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
                        },
                        outputs: []outputInfo{
-                               {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
+                               {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
                        },
                },
        },
        {
-               name:           "MOVWload",
-               auxType:        auxSymOff,
-               argLen:         2,
-               faultOnNilArg0: true,
-               symEffect:      SymRead,
-               asm:            loong64.AMOVW,
+               name:            "LoweredAtomicCas32Variant",
+               argLen:          4,
+               resultNotInArgs: true,
+               clobberFlags:    true,
+               faultOnNilArg0:  true,
+               hasSideEffects:  true,
+               unsafePoint:     true,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
+                               {1, 939524095},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO
+                               {2, 939524095},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO
+                               {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
                        },
                        outputs: []outputInfo{
-                               {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
+                               {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
                        },
                },
        },
        {
-               name:           "MOVWUload",
-               auxType:        auxSymOff,
-               argLen:         2,
-               faultOnNilArg0: true,
-               symEffect:      SymRead,
-               asm:            loong64.AMOVWU,
+               name:            "LoweredAtomicAnd8",
+               argLen:          3,
+               resultNotInArgs: true,
+               needIntTemp:     true,
+               faultOnNilArg0:  true,
+               hasSideEffects:  true,
+               unsafePoint:     true,
+               asm:             arm64.AAND,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
+                               {1, 939524095},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO
+                               {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
                        },
                        outputs: []outputInfo{
-                               {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
+                               {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
                        },
                },
        },
        {
-               name:           "MOVVload",
-               auxType:        auxSymOff,
-               argLen:         2,
-               faultOnNilArg0: true,
-               symEffect:      SymRead,
-               asm:            loong64.AMOVV,
+               name:            "LoweredAtomicOr8",
+               argLen:          3,
+               resultNotInArgs: true,
+               needIntTemp:     true,
+               faultOnNilArg0:  true,
+               hasSideEffects:  true,
+               unsafePoint:     true,
+               asm:             arm64.AORR,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
+                               {1, 939524095},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO
+                               {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
                        },
                        outputs: []outputInfo{
-                               {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
+                               {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
                        },
                },
        },
        {
-               name:           "MOVFload",
-               auxType:        auxSymOff,
-               argLen:         2,
-               faultOnNilArg0: true,
-               symEffect:      SymRead,
-               asm:            loong64.AMOVF,
+               name:            "LoweredAtomicAnd64",
+               argLen:          3,
+               resultNotInArgs: true,
+               needIntTemp:     true,
+               faultOnNilArg0:  true,
+               hasSideEffects:  true,
+               unsafePoint:     true,
+               asm:             arm64.AAND,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
+                               {1, 939524095},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO
+                               {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
                        },
                        outputs: []outputInfo{
-                               {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
                        },
                },
        },
        {
-               name:           "MOVDload",
-               auxType:        auxSymOff,
-               argLen:         2,
-               faultOnNilArg0: true,
-               symEffect:      SymRead,
-               asm:            loong64.AMOVD,
+               name:            "LoweredAtomicOr64",
+               argLen:          3,
+               resultNotInArgs: true,
+               needIntTemp:     true,
+               faultOnNilArg0:  true,
+               hasSideEffects:  true,
+               unsafePoint:     true,
+               asm:             arm64.AORR,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
+                               {1, 939524095},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO
+                               {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
                        },
                        outputs: []outputInfo{
-                               {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
                        },
                },
        },
        {
-               name:   "MOVVloadidx",
-               argLen: 3,
-               asm:    loong64.AMOVV,
+               name:            "LoweredAtomicAnd32",
+               argLen:          3,
+               resultNotInArgs: true,
+               needIntTemp:     true,
+               faultOnNilArg0:  true,
+               hasSideEffects:  true,
+               unsafePoint:     true,
+               asm:             arm64.AAND,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {1, 1073741816},          // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
-                               {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
+                               {1, 939524095},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO
+                               {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
                        },
                        outputs: []outputInfo{
-                               {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
+                               {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
                        },
                },
        },
        {
-               name:   "MOVWloadidx",
-               argLen: 3,
-               asm:    loong64.AMOVW,
+               name:            "LoweredAtomicOr32",
+               argLen:          3,
+               resultNotInArgs: true,
+               needIntTemp:     true,
+               faultOnNilArg0:  true,
+               hasSideEffects:  true,
+               unsafePoint:     true,
+               asm:             arm64.AORR,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {1, 1073741816},          // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
-                               {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
+                               {1, 939524095},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO
+                               {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
                        },
                        outputs: []outputInfo{
-                               {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
+                               {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
                        },
                },
        },
        {
-               name:   "MOVWUloadidx",
-               argLen: 3,
-               asm:    loong64.AMOVWU,
+               name:            "LoweredAtomicAnd8Variant",
+               argLen:          3,
+               resultNotInArgs: true,
+               faultOnNilArg0:  true,
+               hasSideEffects:  true,
+               unsafePoint:     true,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {1, 1073741816},          // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
-                               {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
+                               {1, 939524095},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO
+                               {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
                        },
                        outputs: []outputInfo{
-                               {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
+                               {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
                        },
                },
        },
        {
-               name:   "MOVHloadidx",
-               argLen: 3,
-               asm:    loong64.AMOVH,
+               name:            "LoweredAtomicOr8Variant",
+               argLen:          3,
+               resultNotInArgs: true,
+               faultOnNilArg0:  true,
+               hasSideEffects:  true,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {1, 1073741816},          // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
-                               {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
+                               {1, 939524095},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO
+                               {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
                        },
                        outputs: []outputInfo{
-                               {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
+                               {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
                        },
                },
        },
        {
-               name:   "MOVHUloadidx",
-               argLen: 3,
-               asm:    loong64.AMOVHU,
+               name:            "LoweredAtomicAnd64Variant",
+               argLen:          3,
+               resultNotInArgs: true,
+               faultOnNilArg0:  true,
+               hasSideEffects:  true,
+               unsafePoint:     true,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {1, 1073741816},          // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
-                               {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
+                               {1, 939524095},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO
+                               {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
                        },
                        outputs: []outputInfo{
-                               {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
+                               {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
                        },
                },
        },
        {
-               name:   "MOVBloadidx",
-               argLen: 3,
-               asm:    loong64.AMOVB,
+               name:            "LoweredAtomicOr64Variant",
+               argLen:          3,
+               resultNotInArgs: true,
+               faultOnNilArg0:  true,
+               hasSideEffects:  true,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {1, 1073741816},          // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
-                               {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
+                               {1, 939524095},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO
+                               {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
                        },
                        outputs: []outputInfo{
-                               {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
+                               {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
                        },
                },
        },
        {
-               name:   "MOVBUloadidx",
-               argLen: 3,
-               asm:    loong64.AMOVBU,
+               name:            "LoweredAtomicAnd32Variant",
+               argLen:          3,
+               resultNotInArgs: true,
+               faultOnNilArg0:  true,
+               hasSideEffects:  true,
+               unsafePoint:     true,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {1, 1073741816},          // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
-                               {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
+                               {1, 939524095},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO
+                               {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
                        },
                        outputs: []outputInfo{
-                               {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
+                               {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
                        },
                },
        },
        {
-               name:   "MOVFloadidx",
-               argLen: 3,
-               asm:    loong64.AMOVF,
+               name:            "LoweredAtomicOr32Variant",
+               argLen:          3,
+               resultNotInArgs: true,
+               faultOnNilArg0:  true,
+               hasSideEffects:  true,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {1, 1073741816},          // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
-                               {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
+                               {1, 939524095},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO
+                               {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
                        },
                        outputs: []outputInfo{
-                               {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
                        },
                },
        },
        {
-               name:   "MOVDloadidx",
-               argLen: 3,
-               asm:    loong64.AMOVD,
+               name:         "LoweredWB",
+               auxType:      auxInt64,
+               argLen:       1,
+               clobberFlags: true,
                reg: regInfo{
-                       inputs: []inputInfo{
-                               {1, 1073741816},          // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
-                               {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
-                       },
+                       clobbers: 9223372034975924224, // R16 R17 R30 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
                        outputs: []outputInfo{
-                               {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {0, 16777216}, // R25
                        },
                },
        },
        {
-               name:           "MOVBstore",
-               auxType:        auxSymOff,
-               argLen:         3,
-               faultOnNilArg0: true,
-               symEffect:      SymWrite,
-               asm:            loong64.AMOVB,
+               name:    "LoweredPanicBoundsA",
+               auxType: auxInt64,
+               argLen:  3,
+               call:    true,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {1, 1073741816},          // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
-                               {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
+                               {0, 4}, // R2
+                               {1, 8}, // R3
                        },
                },
        },
        {
-               name:           "MOVHstore",
-               auxType:        auxSymOff,
-               argLen:         3,
-               faultOnNilArg0: true,
-               symEffect:      SymWrite,
-               asm:            loong64.AMOVH,
+               name:    "LoweredPanicBoundsB",
+               auxType: auxInt64,
+               argLen:  3,
+               call:    true,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {1, 1073741816},          // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
-                               {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
+                               {0, 2}, // R1
+                               {1, 4}, // R2
                        },
                },
        },
        {
-               name:           "MOVWstore",
-               auxType:        auxSymOff,
-               argLen:         3,
-               faultOnNilArg0: true,
-               symEffect:      SymWrite,
-               asm:            loong64.AMOVW,
+               name:    "LoweredPanicBoundsC",
+               auxType: auxInt64,
+               argLen:  3,
+               call:    true,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {1, 1073741816},          // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
-                               {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
+                               {0, 1}, // R0
+                               {1, 2}, // R1
                        },
                },
        },
        {
-               name:           "MOVVstore",
-               auxType:        auxSymOff,
-               argLen:         3,
-               faultOnNilArg0: true,
-               symEffect:      SymWrite,
-               asm:            loong64.AMOVV,
+               name:           "PRFM",
+               auxType:        auxInt64,
+               argLen:         2,
+               hasSideEffects: true,
+               asm:            arm64.APRFM,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {1, 1073741816},          // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
-                               {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
+                               {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
                        },
                },
        },
        {
-               name:           "MOVFstore",
-               auxType:        auxSymOff,
-               argLen:         3,
-               faultOnNilArg0: true,
-               symEffect:      SymWrite,
-               asm:            loong64.AMOVF,
+               name:           "DMB",
+               auxType:        auxInt64,
+               argLen:         1,
+               hasSideEffects: true,
+               asm:            arm64.ADMB,
+               reg:            regInfo{},
+       },
+       {
+               name:      "ZERO",
+               argLen:    0,
+               zeroWidth: true,
+               fixedReg:  true,
+               reg:       regInfo{},
+       },
+
+       {
+               name:   "NEGV",
+               argLen: 1,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
-                               {1, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
+                       },
+                       outputs: []outputInfo{
+                               {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
                        },
                },
        },
        {
-               name:           "MOVDstore",
-               auxType:        auxSymOff,
-               argLen:         3,
-               faultOnNilArg0: true,
-               symEffect:      SymWrite,
-               asm:            loong64.AMOVD,
+               name:   "NEGF",
+               argLen: 1,
+               asm:    loong64.ANEGF,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
-                               {1, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                       },
+                       outputs: []outputInfo{
+                               {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
                        },
                },
        },
        {
-               name:   "MOVBstoreidx",
-               argLen: 4,
-               asm:    loong64.AMOVB,
+               name:   "NEGD",
+               argLen: 1,
+               asm:    loong64.ANEGD,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {1, 1073741816},          // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
-                               {2, 1073741816},          // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
-                               {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
+                               {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                       },
+                       outputs: []outputInfo{
+                               {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
                        },
                },
        },
        {
-               name:   "MOVHstoreidx",
-               argLen: 4,
-               asm:    loong64.AMOVH,
+               name:   "SQRTD",
+               argLen: 1,
+               asm:    loong64.ASQRTD,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {1, 1073741816},          // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
-                               {2, 1073741816},          // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
-                               {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
+                               {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                       },
+                       outputs: []outputInfo{
+                               {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
                        },
                },
        },
        {
-               name:   "MOVWstoreidx",
-               argLen: 4,
-               asm:    loong64.AMOVW,
+               name:   "SQRTF",
+               argLen: 1,
+               asm:    loong64.ASQRTF,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {1, 1073741816},          // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
-                               {2, 1073741816},          // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
-                               {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
+                               {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                       },
+                       outputs: []outputInfo{
+                               {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
                        },
                },
        },
        {
-               name:   "MOVVstoreidx",
-               argLen: 4,
-               asm:    loong64.AMOVV,
+               name:   "ABSD",
+               argLen: 1,
+               asm:    loong64.AABSD,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {1, 1073741816},          // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
-                               {2, 1073741816},          // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
-                               {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
+                               {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                       },
+                       outputs: []outputInfo{
+                               {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
                        },
                },
        },
        {
-               name:   "MOVFstoreidx",
-               argLen: 4,
-               asm:    loong64.AMOVF,
+               name:   "CLZW",
+               argLen: 1,
+               asm:    loong64.ACLZW,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {1, 1073741816},          // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
-                               {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
-                               {2, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
+                       },
+                       outputs: []outputInfo{
+                               {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
                        },
                },
        },
        {
-               name:   "MOVDstoreidx",
-               argLen: 4,
-               asm:    loong64.AMOVD,
+               name:   "CLZV",
+               argLen: 1,
+               asm:    loong64.ACLZV,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {1, 1073741816},          // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
-                               {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
-                               {2, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
+                       },
+                       outputs: []outputInfo{
+                               {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
                        },
                },
        },
        {
-               name:           "MOVBstorezero",
-               auxType:        auxSymOff,
-               argLen:         2,
-               faultOnNilArg0: true,
-               symEffect:      SymWrite,
-               asm:            loong64.AMOVB,
+               name:   "CTZW",
+               argLen: 1,
+               asm:    loong64.ACTZW,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
+                               {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
                        },
-               },
-       },
-       {
-               name:           "MOVHstorezero",
-               auxType:        auxSymOff,
-               argLen:         2,
-               faultOnNilArg0: true,
-               symEffect:      SymWrite,
-               asm:            loong64.AMOVH,
-               reg: regInfo{
-                       inputs: []inputInfo{
-                               {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
+                       outputs: []outputInfo{
+                               {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
                        },
                },
        },
        {
-               name:           "MOVWstorezero",
-               auxType:        auxSymOff,
-               argLen:         2,
-               faultOnNilArg0: true,
-               symEffect:      SymWrite,
-               asm:            loong64.AMOVW,
+               name:   "CTZV",
+               argLen: 1,
+               asm:    loong64.ACTZV,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
+                               {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
+                       },
+                       outputs: []outputInfo{
+                               {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
                        },
                },
        },
        {
-               name:           "MOVVstorezero",
-               auxType:        auxSymOff,
-               argLen:         2,
-               faultOnNilArg0: true,
-               symEffect:      SymWrite,
-               asm:            loong64.AMOVV,
+               name:   "REVB2H",
+               argLen: 1,
+               asm:    loong64.AREVB2H,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
+                               {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
+                       },
+                       outputs: []outputInfo{
+                               {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
                        },
                },
        },
        {
-               name:   "MOVBstorezeroidx",
-               argLen: 3,
-               asm:    loong64.AMOVB,
+               name:   "REVB2W",
+               argLen: 1,
+               asm:    loong64.AREVB2W,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {1, 1073741816},          // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
-                               {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
+                               {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
+                       },
+                       outputs: []outputInfo{
+                               {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
                        },
                },
        },
        {
-               name:   "MOVHstorezeroidx",
-               argLen: 3,
-               asm:    loong64.AMOVH,
+               name:   "REVBV",
+               argLen: 1,
+               asm:    loong64.AREVBV,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {1, 1073741816},          // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
-                               {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
+                               {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
+                       },
+                       outputs: []outputInfo{
+                               {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
                        },
                },
        },
        {
-               name:   "MOVWstorezeroidx",
-               argLen: 3,
-               asm:    loong64.AMOVW,
+               name:   "BITREV4B",
+               argLen: 1,
+               asm:    loong64.ABITREV4B,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {1, 1073741816},          // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
-                               {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
+                               {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
+                       },
+                       outputs: []outputInfo{
+                               {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
                        },
                },
        },
        {
-               name:   "MOVVstorezeroidx",
-               argLen: 3,
-               asm:    loong64.AMOVV,
+               name:   "BITREVW",
+               argLen: 1,
+               asm:    loong64.ABITREVW,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {1, 1073741816},          // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
-                               {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
+                               {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
+                       },
+                       outputs: []outputInfo{
+                               {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
                        },
                },
        },
        {
-               name:   "MOVWfpgp",
+               name:   "BITREVV",
                argLen: 1,
-               asm:    loong64.AMOVW,
+               asm:    loong64.ABITREVV,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
                        },
                        outputs: []outputInfo{
                                {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
@@ -38632,12 +40642,12 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:   "MOVWgpfp",
+               name:   "VPCNT64",
                argLen: 1,
-               asm:    loong64.AMOVW,
+               asm:    loong64.AVPCNTV,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
+                               {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
                        },
                        outputs: []outputInfo{
                                {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
@@ -38645,25 +40655,25 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:   "MOVVfpgp",
+               name:   "VPCNT32",
                argLen: 1,
-               asm:    loong64.AMOVV,
+               asm:    loong64.AVPCNTW,
                reg: regInfo{
                        inputs: []inputInfo{
                                {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
                        },
                        outputs: []outputInfo{
-                               {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
+                               {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
                        },
                },
        },
        {
-               name:   "MOVVgpfp",
+               name:   "VPCNT16",
                argLen: 1,
-               asm:    loong64.AMOVV,
+               asm:    loong64.AVPCNTH,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
+                               {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
                        },
                        outputs: []outputInfo{
                                {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
@@ -38671,12 +40681,14 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:   "MOVBreg",
-               argLen: 1,
-               asm:    loong64.AMOVB,
+               name:        "ADDV",
+               argLen:      2,
+               commutative: true,
+               asm:         loong64.AADDVU,
                reg: regInfo{
                        inputs: []inputInfo{
                                {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
+                               {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
                        },
                        outputs: []outputInfo{
                                {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
@@ -38684,12 +40696,13 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:   "MOVBUreg",
-               argLen: 1,
-               asm:    loong64.AMOVBU,
+               name:    "ADDVconst",
+               auxType: auxInt64,
+               argLen:  1,
+               asm:     loong64.AADDVU,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
+                               {0, 1073741820}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
                        },
                        outputs: []outputInfo{
                                {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
@@ -38697,12 +40710,13 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:   "MOVHreg",
-               argLen: 1,
-               asm:    loong64.AMOVH,
+               name:   "SUBV",
+               argLen: 2,
+               asm:    loong64.ASUBVU,
                reg: regInfo{
                        inputs: []inputInfo{
                                {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
+                               {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
                        },
                        outputs: []outputInfo{
                                {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
@@ -38710,9 +40724,10 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:   "MOVHUreg",
-               argLen: 1,
-               asm:    loong64.AMOVHU,
+               name:    "SUBVconst",
+               auxType: auxInt64,
+               argLen:  1,
+               asm:     loong64.ASUBVU,
                reg: regInfo{
                        inputs: []inputInfo{
                                {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
@@ -38723,12 +40738,14 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:   "MOVWreg",
-               argLen: 1,
-               asm:    loong64.AMOVW,
+               name:        "MULV",
+               argLen:      2,
+               commutative: true,
+               asm:         loong64.AMULV,
                reg: regInfo{
                        inputs: []inputInfo{
                                {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
+                               {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
                        },
                        outputs: []outputInfo{
                                {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
@@ -38736,12 +40753,14 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:   "MOVWUreg",
-               argLen: 1,
-               asm:    loong64.AMOVWU,
+               name:        "MULHV",
+               argLen:      2,
+               commutative: true,
+               asm:         loong64.AMULHV,
                reg: regInfo{
                        inputs: []inputInfo{
                                {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
+                               {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
                        },
                        outputs: []outputInfo{
                                {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
@@ -38749,12 +40768,14 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:   "MOVVreg",
-               argLen: 1,
-               asm:    loong64.AMOVV,
+               name:        "MULHVU",
+               argLen:      2,
+               commutative: true,
+               asm:         loong64.AMULHVU,
                reg: regInfo{
                        inputs: []inputInfo{
                                {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
+                               {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
                        },
                        outputs: []outputInfo{
                                {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
@@ -38762,12 +40783,13 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:         "MOVVnop",
-               argLen:       1,
-               resultInArg0: true,
+               name:   "DIVV",
+               argLen: 2,
+               asm:    loong64.ADIVV,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
+                               {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
+                               {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
                        },
                        outputs: []outputInfo{
                                {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
@@ -38775,51 +40797,56 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:   "MOVWF",
-               argLen: 1,
-               asm:    loong64.AMOVWF,
+               name:   "DIVVU",
+               argLen: 2,
+               asm:    loong64.ADIVVU,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
+                               {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
                        },
                        outputs: []outputInfo{
-                               {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
                        },
                },
        },
        {
-               name:   "MOVWD",
-               argLen: 1,
-               asm:    loong64.AMOVWD,
+               name:   "REMV",
+               argLen: 2,
+               asm:    loong64.AREMV,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
+                               {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
                        },
                        outputs: []outputInfo{
-                               {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
                        },
                },
        },
        {
-               name:   "MOVVF",
-               argLen: 1,
-               asm:    loong64.AMOVVF,
+               name:   "REMVU",
+               argLen: 2,
+               asm:    loong64.AREMVU,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
+                               {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
                        },
                        outputs: []outputInfo{
-                               {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
                        },
                },
        },
        {
-               name:   "MOVVD",
-               argLen: 1,
-               asm:    loong64.AMOVVD,
+               name:        "ADDF",
+               argLen:      2,
+               commutative: true,
+               asm:         loong64.AADDF,
                reg: regInfo{
                        inputs: []inputInfo{
                                {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {1, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
                        },
                        outputs: []outputInfo{
                                {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
@@ -38827,12 +40854,14 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:   "TRUNCFW",
-               argLen: 1,
-               asm:    loong64.ATRUNCFW,
+               name:        "ADDD",
+               argLen:      2,
+               commutative: true,
+               asm:         loong64.AADDD,
                reg: regInfo{
                        inputs: []inputInfo{
                                {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {1, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
                        },
                        outputs: []outputInfo{
                                {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
@@ -38840,12 +40869,13 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:   "TRUNCDW",
-               argLen: 1,
-               asm:    loong64.ATRUNCDW,
+               name:   "SUBF",
+               argLen: 2,
+               asm:    loong64.ASUBF,
                reg: regInfo{
                        inputs: []inputInfo{
                                {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {1, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
                        },
                        outputs: []outputInfo{
                                {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
@@ -38853,12 +40883,13 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:   "TRUNCFV",
-               argLen: 1,
-               asm:    loong64.ATRUNCFV,
+               name:   "SUBD",
+               argLen: 2,
+               asm:    loong64.ASUBD,
                reg: regInfo{
                        inputs: []inputInfo{
                                {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {1, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
                        },
                        outputs: []outputInfo{
                                {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
@@ -38866,12 +40897,14 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:   "TRUNCDV",
-               argLen: 1,
-               asm:    loong64.ATRUNCDV,
+               name:        "MULF",
+               argLen:      2,
+               commutative: true,
+               asm:         loong64.AMULF,
                reg: regInfo{
                        inputs: []inputInfo{
                                {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {1, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
                        },
                        outputs: []outputInfo{
                                {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
@@ -38879,12 +40912,14 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:   "MOVFD",
-               argLen: 1,
-               asm:    loong64.AMOVFD,
+               name:        "MULD",
+               argLen:      2,
+               commutative: true,
+               asm:         loong64.AMULD,
                reg: regInfo{
                        inputs: []inputInfo{
                                {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {1, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
                        },
                        outputs: []outputInfo{
                                {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
@@ -38892,12 +40927,13 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:   "MOVDF",
-               argLen: 1,
-               asm:    loong64.AMOVDF,
+               name:   "DIVF",
+               argLen: 2,
+               asm:    loong64.ADIVF,
                reg: regInfo{
                        inputs: []inputInfo{
                                {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {1, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
                        },
                        outputs: []outputInfo{
                                {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
@@ -38905,12 +40941,13 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:         "LoweredRound32F",
-               argLen:       1,
-               resultInArg0: true,
+               name:   "DIVD",
+               argLen: 2,
+               asm:    loong64.ADIVD,
                reg: regInfo{
                        inputs: []inputInfo{
                                {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {1, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
                        },
                        outputs: []outputInfo{
                                {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
@@ -38918,127 +40955,129 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:         "LoweredRound64F",
-               argLen:       1,
-               resultInArg0: true,
+               name:        "AND",
+               argLen:      2,
+               commutative: true,
+               asm:         loong64.AAND,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
+                               {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
                        },
                        outputs: []outputInfo{
-                               {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
                        },
                },
        },
        {
-               name:         "CALLstatic",
-               auxType:      auxCallOff,
-               argLen:       -1,
-               clobberFlags: true,
-               call:         true,
-               reg: regInfo{
-                       clobbers: 4611686018427387896, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
-               },
-       },
-       {
-               name:         "CALLtail",
-               auxType:      auxCallOff,
-               argLen:       -1,
-               clobberFlags: true,
-               call:         true,
-               tailCall:     true,
+               name:    "ANDconst",
+               auxType: auxInt64,
+               argLen:  1,
+               asm:     loong64.AAND,
                reg: regInfo{
-                       clobbers: 4611686018427387896, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                       inputs: []inputInfo{
+                               {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
+                       },
+                       outputs: []outputInfo{
+                               {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
+                       },
                },
        },
        {
-               name:         "CALLclosure",
-               auxType:      auxCallOff,
-               argLen:       -1,
-               clobberFlags: true,
-               call:         true,
+               name:        "OR",
+               argLen:      2,
+               commutative: true,
+               asm:         loong64.AOR,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {1, 268435456},  // R29
-                               {0, 1071644668}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
+                               {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
+                               {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
+                       },
+                       outputs: []outputInfo{
+                               {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
                        },
-                       clobbers: 4611686018427387896, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
                },
        },
        {
-               name:         "CALLinter",
-               auxType:      auxCallOff,
-               argLen:       -1,
-               clobberFlags: true,
-               call:         true,
+               name:    "ORconst",
+               auxType: auxInt64,
+               argLen:  1,
+               asm:     loong64.AOR,
                reg: regInfo{
                        inputs: []inputInfo{
+                               {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
+                       },
+                       outputs: []outputInfo{
                                {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
                        },
-                       clobbers: 4611686018427387896, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
                },
        },
        {
-               name:           "DUFFZERO",
-               auxType:        auxInt64,
-               argLen:         2,
-               faultOnNilArg0: true,
+               name:        "XOR",
+               argLen:      2,
+               commutative: true,
+               asm:         loong64.AXOR,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 524288}, // R20
+                               {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
+                               {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
+                       },
+                       outputs: []outputInfo{
+                               {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
                        },
-                       clobbers: 524290, // R1 R20
                },
        },
        {
-               name:           "DUFFCOPY",
-               auxType:        auxInt64,
-               argLen:         3,
-               faultOnNilArg0: true,
-               faultOnNilArg1: true,
+               name:    "XORconst",
+               auxType: auxInt64,
+               argLen:  1,
+               asm:     loong64.AXOR,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 1048576}, // R21
-                               {1, 524288},  // R20
+                               {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
+                       },
+                       outputs: []outputInfo{
+                               {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
                        },
-                       clobbers: 1572866, // R1 R20 R21
                },
        },
        {
-               name:           "LoweredZero",
-               auxType:        auxInt64,
-               argLen:         3,
-               faultOnNilArg0: true,
+               name:        "NOR",
+               argLen:      2,
+               commutative: true,
+               asm:         loong64.ANOR,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 524288},     // R20
-                               {1, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
+                               {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
+                               {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
+                       },
+                       outputs: []outputInfo{
+                               {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
                        },
-                       clobbers: 524288, // R20
                },
        },
        {
-               name:           "LoweredMove",
-               auxType:        auxInt64,
-               argLen:         4,
-               faultOnNilArg0: true,
-               faultOnNilArg1: true,
+               name:    "NORconst",
+               auxType: auxInt64,
+               argLen:  1,
+               asm:     loong64.ANOR,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 1048576},    // R21
-                               {1, 524288},     // R20
-                               {2, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
+                               {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
+                       },
+                       outputs: []outputInfo{
+                               {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
                        },
-                       clobbers: 1572864, // R20 R21
                },
        },
        {
-               name:           "LoweredAtomicLoad8",
-               argLen:         2,
-               faultOnNilArg0: true,
+               name:   "ANDN",
+               argLen: 2,
+               asm:    loong64.AANDN,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
+                               {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
+                               {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
                        },
                        outputs: []outputInfo{
                                {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
@@ -39046,12 +41085,13 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:           "LoweredAtomicLoad32",
-               argLen:         2,
-               faultOnNilArg0: true,
+               name:   "ORN",
+               argLen: 2,
+               asm:    loong64.AORN,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
+                               {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
+                               {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
                        },
                        outputs: []outputInfo{
                                {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
@@ -39059,182 +41099,205 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:           "LoweredAtomicLoad64",
-               argLen:         2,
-               faultOnNilArg0: true,
+               name:        "FMADDF",
+               argLen:      3,
+               commutative: true,
+               asm:         loong64.AFMADDF,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
+                               {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {1, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {2, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
                        },
                        outputs: []outputInfo{
-                               {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
+                               {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
                        },
                },
        },
        {
-               name:           "LoweredAtomicStore8",
-               argLen:         3,
-               faultOnNilArg0: true,
-               hasSideEffects: true,
+               name:        "FMADDD",
+               argLen:      3,
+               commutative: true,
+               asm:         loong64.AFMADDD,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {1, 1073741816},          // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
-                               {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
+                               {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {1, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {2, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                       },
+                       outputs: []outputInfo{
+                               {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
                        },
                },
        },
        {
-               name:           "LoweredAtomicStore32",
-               argLen:         3,
-               faultOnNilArg0: true,
-               hasSideEffects: true,
+               name:        "FMSUBF",
+               argLen:      3,
+               commutative: true,
+               asm:         loong64.AFMSUBF,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {1, 1073741816},          // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
-                               {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
+                               {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {1, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {2, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                       },
+                       outputs: []outputInfo{
+                               {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
                        },
                },
        },
        {
-               name:           "LoweredAtomicStore64",
-               argLen:         3,
-               faultOnNilArg0: true,
-               hasSideEffects: true,
+               name:        "FMSUBD",
+               argLen:      3,
+               commutative: true,
+               asm:         loong64.AFMSUBD,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {1, 1073741816},          // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
-                               {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
+                               {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {1, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {2, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                       },
+                       outputs: []outputInfo{
+                               {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
                        },
                },
        },
        {
-               name:           "LoweredAtomicStore8Variant",
-               argLen:         3,
-               faultOnNilArg0: true,
-               hasSideEffects: true,
+               name:        "FNMADDF",
+               argLen:      3,
+               commutative: true,
+               asm:         loong64.AFNMADDF,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {1, 1073741816},          // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
-                               {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
+                               {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {1, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {2, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                       },
+                       outputs: []outputInfo{
+                               {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
                        },
                },
        },
        {
-               name:           "LoweredAtomicStore32Variant",
-               argLen:         3,
-               faultOnNilArg0: true,
-               hasSideEffects: true,
+               name:        "FNMADDD",
+               argLen:      3,
+               commutative: true,
+               asm:         loong64.AFNMADDD,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {1, 1073741816},          // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
-                               {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
+                               {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {1, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {2, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                       },
+                       outputs: []outputInfo{
+                               {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
                        },
                },
        },
        {
-               name:           "LoweredAtomicStore64Variant",
-               argLen:         3,
-               faultOnNilArg0: true,
-               hasSideEffects: true,
+               name:        "FNMSUBF",
+               argLen:      3,
+               commutative: true,
+               asm:         loong64.AFNMSUBF,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {1, 1073741816},          // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
-                               {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
+                               {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {1, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {2, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                       },
+                       outputs: []outputInfo{
+                               {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
                        },
                },
        },
        {
-               name:            "LoweredAtomicExchange32",
-               argLen:          3,
-               resultNotInArgs: true,
-               faultOnNilArg0:  true,
-               hasSideEffects:  true,
+               name:        "FNMSUBD",
+               argLen:      3,
+               commutative: true,
+               asm:         loong64.AFNMSUBD,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {1, 1073741816},          // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
-                               {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
+                               {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {1, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {2, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
                        },
                        outputs: []outputInfo{
-                               {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
+                               {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
                        },
                },
        },
        {
-               name:            "LoweredAtomicExchange64",
-               argLen:          3,
+               name:            "FMINF",
+               argLen:          2,
+               commutative:     true,
                resultNotInArgs: true,
-               faultOnNilArg0:  true,
-               hasSideEffects:  true,
+               asm:             loong64.AFMINF,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {1, 1073741816},          // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
-                               {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
+                               {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {1, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
                        },
                        outputs: []outputInfo{
-                               {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
+                               {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
                        },
                },
        },
        {
-               name:            "LoweredAtomicExchange8Variant",
-               argLen:          3,
+               name:            "FMIND",
+               argLen:          2,
+               commutative:     true,
                resultNotInArgs: true,
-               faultOnNilArg0:  true,
-               hasSideEffects:  true,
+               asm:             loong64.AFMIND,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {1, 1073741816},          // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
-                               {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
+                               {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {1, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
                        },
                        outputs: []outputInfo{
-                               {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
+                               {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
                        },
                },
        },
        {
-               name:            "LoweredAtomicAdd32",
-               argLen:          3,
+               name:            "FMAXF",
+               argLen:          2,
+               commutative:     true,
                resultNotInArgs: true,
-               faultOnNilArg0:  true,
-               hasSideEffects:  true,
+               asm:             loong64.AFMAXF,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {1, 1073741816},          // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
-                               {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
+                               {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {1, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
                        },
                        outputs: []outputInfo{
-                               {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
+                               {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
                        },
                },
        },
        {
-               name:            "LoweredAtomicAdd64",
-               argLen:          3,
+               name:            "FMAXD",
+               argLen:          2,
+               commutative:     true,
                resultNotInArgs: true,
-               faultOnNilArg0:  true,
-               hasSideEffects:  true,
+               asm:             loong64.AFMAXD,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {1, 1073741816},          // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
-                               {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
+                               {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {1, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
                        },
                        outputs: []outputInfo{
-                               {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
+                               {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
                        },
                },
        },
        {
-               name:            "LoweredAtomicCas32",
-               argLen:          4,
-               resultNotInArgs: true,
-               faultOnNilArg0:  true,
-               hasSideEffects:  true,
-               unsafePoint:     true,
+               name:   "MASKEQZ",
+               argLen: 2,
+               asm:    loong64.AMASKEQZ,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {1, 1073741816},          // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
-                               {2, 1073741816},          // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
-                               {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
+                               {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
+                               {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
                        },
                        outputs: []outputInfo{
                                {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
@@ -39242,17 +41305,13 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:            "LoweredAtomicCas64",
-               argLen:          4,
-               resultNotInArgs: true,
-               faultOnNilArg0:  true,
-               hasSideEffects:  true,
-               unsafePoint:     true,
+               name:   "MASKNEZ",
+               argLen: 2,
+               asm:    loong64.AMASKNEZ,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {1, 1073741816},          // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
-                               {2, 1073741816},          // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
-                               {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
+                               {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
+                               {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
                        },
                        outputs: []outputInfo{
                                {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
@@ -39260,35 +41319,27 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:            "LoweredAtomicCas64Variant",
-               argLen:          4,
-               resultNotInArgs: true,
-               faultOnNilArg0:  true,
-               hasSideEffects:  true,
-               unsafePoint:     true,
+               name:   "FCOPYSGD",
+               argLen: 2,
+               asm:    loong64.AFCOPYSGD,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {1, 1073741816},          // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
-                               {2, 1073741816},          // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
-                               {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
+                               {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {1, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
                        },
                        outputs: []outputInfo{
-                               {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
+                               {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
                        },
                },
        },
        {
-               name:            "LoweredAtomicCas32Variant",
-               argLen:          4,
-               resultNotInArgs: true,
-               faultOnNilArg0:  true,
-               hasSideEffects:  true,
-               unsafePoint:     true,
+               name:   "SLL",
+               argLen: 2,
+               asm:    loong64.ASLL,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {1, 1073741816},          // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
-                               {2, 1073741816},          // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
-                               {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
+                               {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
+                               {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
                        },
                        outputs: []outputInfo{
                                {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
@@ -39296,16 +41347,13 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:            "LoweredAtomicAnd32",
-               argLen:          3,
-               resultNotInArgs: true,
-               faultOnNilArg0:  true,
-               hasSideEffects:  true,
-               asm:             loong64.AAMANDDBW,
+               name:   "SLLV",
+               argLen: 2,
+               asm:    loong64.ASLLV,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {1, 1073741816},          // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
-                               {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
+                               {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
+                               {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
                        },
                        outputs: []outputInfo{
                                {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
@@ -39313,16 +41361,13 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:            "LoweredAtomicOr32",
-               argLen:          3,
-               resultNotInArgs: true,
-               faultOnNilArg0:  true,
-               hasSideEffects:  true,
-               asm:             loong64.AAMORDBW,
+               name:    "SLLconst",
+               auxType: auxInt64,
+               argLen:  1,
+               asm:     loong64.ASLL,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {1, 1073741816},          // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
-                               {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
+                               {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
                        },
                        outputs: []outputInfo{
                                {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
@@ -39330,16 +41375,13 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:            "LoweredAtomicAnd32value",
-               argLen:          3,
-               resultNotInArgs: true,
-               faultOnNilArg0:  true,
-               hasSideEffects:  true,
-               asm:             loong64.AAMANDDBW,
+               name:    "SLLVconst",
+               auxType: auxInt64,
+               argLen:  1,
+               asm:     loong64.ASLLV,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {1, 1073741816},          // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
-                               {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
+                               {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
                        },
                        outputs: []outputInfo{
                                {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
@@ -39347,16 +41389,13 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:            "LoweredAtomicAnd64value",
-               argLen:          3,
-               resultNotInArgs: true,
-               faultOnNilArg0:  true,
-               hasSideEffects:  true,
-               asm:             loong64.AAMANDDBV,
+               name:   "SRL",
+               argLen: 2,
+               asm:    loong64.ASRL,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {1, 1073741816},          // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
-                               {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
+                               {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
+                               {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
                        },
                        outputs: []outputInfo{
                                {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
@@ -39364,16 +41403,13 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:            "LoweredAtomicOr32value",
-               argLen:          3,
-               resultNotInArgs: true,
-               faultOnNilArg0:  true,
-               hasSideEffects:  true,
-               asm:             loong64.AAMORDBW,
+               name:   "SRLV",
+               argLen: 2,
+               asm:    loong64.ASRLV,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {1, 1073741816},          // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
-                               {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
+                               {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
+                               {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
                        },
                        outputs: []outputInfo{
                                {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
@@ -39381,16 +41417,13 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:            "LoweredAtomicOr64value",
-               argLen:          3,
-               resultNotInArgs: true,
-               faultOnNilArg0:  true,
-               hasSideEffects:  true,
-               asm:             loong64.AAMORDBV,
+               name:    "SRLconst",
+               auxType: auxInt64,
+               argLen:  1,
+               asm:     loong64.ASRL,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {1, 1073741816},          // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
-                               {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
+                               {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
                        },
                        outputs: []outputInfo{
                                {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
@@ -39398,1481 +41431,1480 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:           "LoweredNilCheck",
-               argLen:         2,
-               nilCheck:       true,
-               faultOnNilArg0: true,
+               name:    "SRLVconst",
+               auxType: auxInt64,
+               argLen:  1,
+               asm:     loong64.ASRLV,
                reg: regInfo{
                        inputs: []inputInfo{
                                {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
                        },
-               },
-       },
-       {
-               name:   "FPFlagTrue",
-               argLen: 1,
-               reg: regInfo{
                        outputs: []outputInfo{
                                {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
                        },
                },
        },
        {
-               name:   "FPFlagFalse",
-               argLen: 1,
+               name:   "SRA",
+               argLen: 2,
+               asm:    loong64.ASRA,
                reg: regInfo{
+                       inputs: []inputInfo{
+                               {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
+                               {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
+                       },
                        outputs: []outputInfo{
                                {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
                        },
                },
        },
        {
-               name:      "LoweredGetClosurePtr",
-               argLen:    0,
-               zeroWidth: true,
+               name:   "SRAV",
+               argLen: 2,
+               asm:    loong64.ASRAV,
                reg: regInfo{
+                       inputs: []inputInfo{
+                               {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
+                               {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
+                       },
                        outputs: []outputInfo{
-                               {0, 268435456}, // R29
+                               {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
                        },
                },
        },
        {
-               name:              "LoweredGetCallerSP",
-               argLen:            1,
-               rematerializeable: true,
+               name:    "SRAconst",
+               auxType: auxInt64,
+               argLen:  1,
+               asm:     loong64.ASRA,
                reg: regInfo{
+                       inputs: []inputInfo{
+                               {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
+                       },
                        outputs: []outputInfo{
                                {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
                        },
                },
        },
        {
-               name:              "LoweredGetCallerPC",
-               argLen:            0,
-               rematerializeable: true,
+               name:    "SRAVconst",
+               auxType: auxInt64,
+               argLen:  1,
+               asm:     loong64.ASRAV,
                reg: regInfo{
+                       inputs: []inputInfo{
+                               {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
+                       },
                        outputs: []outputInfo{
                                {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
                        },
                },
        },
        {
-               name:         "LoweredWB",
-               auxType:      auxInt64,
-               argLen:       1,
-               clobberFlags: true,
+               name:   "ROTR",
+               argLen: 2,
+               asm:    loong64.AROTR,
                reg: regInfo{
-                       clobbers: 4611686017353646082, // R1 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                       inputs: []inputInfo{
+                               {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
+                               {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
+                       },
                        outputs: []outputInfo{
-                               {0, 268435456}, // R29
+                               {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
                        },
                },
        },
        {
-               name:           "LoweredPubBarrier",
-               argLen:         1,
-               hasSideEffects: true,
-               asm:            loong64.ADBAR,
-               reg:            regInfo{},
-       },
-       {
-               name:    "LoweredPanicBoundsA",
-               auxType: auxInt64,
-               argLen:  3,
-               call:    true,
+               name:   "ROTRV",
+               argLen: 2,
+               asm:    loong64.AROTRV,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 4194304}, // R23
-                               {1, 8388608}, // R24
+                               {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
+                               {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
+                       },
+                       outputs: []outputInfo{
+                               {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
                        },
                },
        },
        {
-               name:    "LoweredPanicBoundsB",
+               name:    "ROTRconst",
                auxType: auxInt64,
-               argLen:  3,
-               call:    true,
+               argLen:  1,
+               asm:     loong64.AROTR,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 1048576}, // R21
-                               {1, 4194304}, // R23
+                               {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
+                       },
+                       outputs: []outputInfo{
+                               {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
                        },
                },
        },
        {
-               name:    "LoweredPanicBoundsC",
+               name:    "ROTRVconst",
                auxType: auxInt64,
-               argLen:  3,
-               call:    true,
+               argLen:  1,
+               asm:     loong64.AROTRV,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 524288},  // R20
-                               {1, 1048576}, // R21
+                               {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
+                       },
+                       outputs: []outputInfo{
+                               {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
                        },
                },
        },
        {
-               name:           "PRELD",
-               auxType:        auxInt64,
-               argLen:         2,
-               hasSideEffects: true,
-               asm:            loong64.APRELD,
+               name:   "SGT",
+               argLen: 2,
+               asm:    loong64.ASGT,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 1073741820}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
+                               {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
+                               {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
+                       },
+                       outputs: []outputInfo{
+                               {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
                        },
                },
        },
        {
-               name:           "PRELDX",
-               auxType:        auxInt64,
-               argLen:         2,
-               hasSideEffects: true,
-               asm:            loong64.APRELDX,
+               name:    "SGTconst",
+               auxType: auxInt64,
+               argLen:  1,
+               asm:     loong64.ASGT,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 1073741820}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
+                               {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
+                       },
+                       outputs: []outputInfo{
+                               {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
                        },
                },
        },
-
        {
-               name:        "ADD",
-               argLen:      2,
-               commutative: true,
-               asm:         mips.AADDU,
+               name:   "SGTU",
+               argLen: 2,
+               asm:    loong64.ASGTU,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
-                               {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
+                               {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
+                               {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
                        },
                        outputs: []outputInfo{
-                               {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
+                               {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
                        },
                },
        },
        {
-               name:    "ADDconst",
-               auxType: auxInt32,
+               name:    "SGTUconst",
+               auxType: auxInt64,
                argLen:  1,
-               asm:     mips.AADDU,
+               asm:     loong64.ASGTU,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 536870910}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31
+                               {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
                        },
                        outputs: []outputInfo{
-                               {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
+                               {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
                        },
                },
        },
        {
-               name:   "SUB",
+               name:   "CMPEQF",
                argLen: 2,
-               asm:    mips.ASUBU,
+               asm:    loong64.ACMPEQF,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
-                               {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
-                       },
-                       outputs: []outputInfo{
-                               {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
+                               {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {1, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
                        },
                },
        },
        {
-               name:    "SUBconst",
-               auxType: auxInt32,
-               argLen:  1,
-               asm:     mips.ASUBU,
+               name:   "CMPEQD",
+               argLen: 2,
+               asm:    loong64.ACMPEQD,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
-                       },
-                       outputs: []outputInfo{
-                               {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
+                               {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {1, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
                        },
                },
        },
        {
-               name:        "MUL",
-               argLen:      2,
-               commutative: true,
-               asm:         mips.AMUL,
+               name:   "CMPGEF",
+               argLen: 2,
+               asm:    loong64.ACMPGEF,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
-                               {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
-                       },
-                       clobbers: 105553116266496, // HI LO
-                       outputs: []outputInfo{
-                               {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
+                               {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {1, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
                        },
                },
        },
        {
-               name:        "MULT",
-               argLen:      2,
-               commutative: true,
-               asm:         mips.AMUL,
+               name:   "CMPGED",
+               argLen: 2,
+               asm:    loong64.ACMPGED,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
-                               {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
-                       },
-                       outputs: []outputInfo{
-                               {0, 35184372088832}, // HI
-                               {1, 70368744177664}, // LO
+                               {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {1, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
                        },
                },
        },
        {
-               name:        "MULTU",
-               argLen:      2,
-               commutative: true,
-               asm:         mips.AMULU,
+               name:   "CMPGTF",
+               argLen: 2,
+               asm:    loong64.ACMPGTF,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
-                               {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
-                       },
-                       outputs: []outputInfo{
-                               {0, 35184372088832}, // HI
-                               {1, 70368744177664}, // LO
+                               {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {1, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
                        },
                },
        },
        {
-               name:   "DIV",
+               name:   "CMPGTD",
                argLen: 2,
-               asm:    mips.ADIV,
+               asm:    loong64.ACMPGTD,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
-                               {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
-                       },
-                       outputs: []outputInfo{
-                               {0, 35184372088832}, // HI
-                               {1, 70368744177664}, // LO
+                               {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {1, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
                        },
                },
        },
        {
-               name:   "DIVU",
-               argLen: 2,
-               asm:    mips.ADIVU,
+               name:    "BSTRPICKW",
+               auxType: auxInt64,
+               argLen:  1,
+               asm:     loong64.ABSTRPICKW,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
-                               {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
+                               {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
                        },
                        outputs: []outputInfo{
-                               {0, 35184372088832}, // HI
-                               {1, 70368744177664}, // LO
+                               {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
                        },
                },
        },
        {
-               name:        "ADDF",
-               argLen:      2,
-               commutative: true,
-               asm:         mips.AADDF,
+               name:    "BSTRPICKV",
+               auxType: auxInt64,
+               argLen:  1,
+               asm:     loong64.ABSTRPICKV,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
-                               {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
+                               {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
                        },
                        outputs: []outputInfo{
-                               {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
+                               {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
                        },
                },
        },
        {
-               name:        "ADDD",
-               argLen:      2,
-               commutative: true,
-               asm:         mips.AADDD,
+               name:              "MOVVconst",
+               auxType:           auxInt64,
+               argLen:            0,
+               rematerializeable: true,
+               asm:               loong64.AMOVV,
                reg: regInfo{
-                       inputs: []inputInfo{
-                               {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
-                               {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
-                       },
                        outputs: []outputInfo{
-                               {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
+                               {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
                        },
                },
        },
        {
-               name:   "SUBF",
-               argLen: 2,
-               asm:    mips.ASUBF,
+               name:              "MOVFconst",
+               auxType:           auxFloat64,
+               argLen:            0,
+               rematerializeable: true,
+               asm:               loong64.AMOVF,
                reg: regInfo{
-                       inputs: []inputInfo{
-                               {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
-                               {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
-                       },
                        outputs: []outputInfo{
-                               {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
+                               {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
                        },
                },
        },
        {
-               name:   "SUBD",
-               argLen: 2,
-               asm:    mips.ASUBD,
+               name:              "MOVDconst",
+               auxType:           auxFloat64,
+               argLen:            0,
+               rematerializeable: true,
+               asm:               loong64.AMOVD,
                reg: regInfo{
-                       inputs: []inputInfo{
-                               {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
-                               {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
-                       },
                        outputs: []outputInfo{
-                               {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
+                               {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
                        },
                },
        },
        {
-               name:        "MULF",
-               argLen:      2,
-               commutative: true,
-               asm:         mips.AMULF,
+               name:              "MOVVaddr",
+               auxType:           auxSymOff,
+               argLen:            1,
+               rematerializeable: true,
+               symEffect:         SymAddr,
+               asm:               loong64.AMOVV,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
-                               {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
+                               {0, 4611686018427387908}, // SP SB
                        },
                        outputs: []outputInfo{
-                               {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
+                               {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
                        },
                },
        },
        {
-               name:        "MULD",
-               argLen:      2,
-               commutative: true,
-               asm:         mips.AMULD,
+               name:           "MOVBload",
+               auxType:        auxSymOff,
+               argLen:         2,
+               faultOnNilArg0: true,
+               symEffect:      SymRead,
+               asm:            loong64.AMOVB,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
-                               {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
+                               {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
                        },
                        outputs: []outputInfo{
-                               {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
+                               {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
                        },
                },
        },
        {
-               name:   "DIVF",
-               argLen: 2,
-               asm:    mips.ADIVF,
+               name:           "MOVBUload",
+               auxType:        auxSymOff,
+               argLen:         2,
+               faultOnNilArg0: true,
+               symEffect:      SymRead,
+               asm:            loong64.AMOVBU,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
-                               {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
+                               {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
                        },
                        outputs: []outputInfo{
-                               {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
+                               {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
                        },
                },
        },
        {
-               name:   "DIVD",
-               argLen: 2,
-               asm:    mips.ADIVD,
+               name:           "MOVHload",
+               auxType:        auxSymOff,
+               argLen:         2,
+               faultOnNilArg0: true,
+               symEffect:      SymRead,
+               asm:            loong64.AMOVH,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
-                               {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
+                               {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
                        },
                        outputs: []outputInfo{
-                               {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
+                               {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
                        },
                },
        },
        {
-               name:        "AND",
-               argLen:      2,
-               commutative: true,
-               asm:         mips.AAND,
+               name:           "MOVHUload",
+               auxType:        auxSymOff,
+               argLen:         2,
+               faultOnNilArg0: true,
+               symEffect:      SymRead,
+               asm:            loong64.AMOVHU,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
-                               {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
+                               {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
                        },
                        outputs: []outputInfo{
-                               {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
+                               {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
                        },
                },
        },
        {
-               name:    "ANDconst",
-               auxType: auxInt32,
-               argLen:  1,
-               asm:     mips.AAND,
+               name:           "MOVWload",
+               auxType:        auxSymOff,
+               argLen:         2,
+               faultOnNilArg0: true,
+               symEffect:      SymRead,
+               asm:            loong64.AMOVW,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
+                               {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
                        },
                        outputs: []outputInfo{
-                               {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
+                               {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
                        },
                },
        },
        {
-               name:        "OR",
-               argLen:      2,
-               commutative: true,
-               asm:         mips.AOR,
+               name:           "MOVWUload",
+               auxType:        auxSymOff,
+               argLen:         2,
+               faultOnNilArg0: true,
+               symEffect:      SymRead,
+               asm:            loong64.AMOVWU,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
-                               {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
+                               {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
                        },
                        outputs: []outputInfo{
-                               {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
+                               {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
                        },
                },
        },
        {
-               name:    "ORconst",
-               auxType: auxInt32,
-               argLen:  1,
-               asm:     mips.AOR,
+               name:           "MOVVload",
+               auxType:        auxSymOff,
+               argLen:         2,
+               faultOnNilArg0: true,
+               symEffect:      SymRead,
+               asm:            loong64.AMOVV,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
+                               {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
                        },
                        outputs: []outputInfo{
-                               {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
+                               {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
                        },
                },
        },
        {
-               name:        "XOR",
-               argLen:      2,
-               commutative: true,
-               asm:         mips.AXOR,
+               name:           "MOVFload",
+               auxType:        auxSymOff,
+               argLen:         2,
+               faultOnNilArg0: true,
+               symEffect:      SymRead,
+               asm:            loong64.AMOVF,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
-                               {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
+                               {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
                        },
                        outputs: []outputInfo{
-                               {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
+                               {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
                        },
                },
        },
        {
-               name:    "XORconst",
-               auxType: auxInt32,
-               argLen:  1,
-               asm:     mips.AXOR,
+               name:           "MOVDload",
+               auxType:        auxSymOff,
+               argLen:         2,
+               faultOnNilArg0: true,
+               symEffect:      SymRead,
+               asm:            loong64.AMOVD,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
+                               {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
                        },
                        outputs: []outputInfo{
-                               {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
+                               {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
                        },
                },
        },
        {
-               name:        "NOR",
-               argLen:      2,
-               commutative: true,
-               asm:         mips.ANOR,
+               name:   "MOVVloadidx",
+               argLen: 3,
+               asm:    loong64.AMOVV,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
-                               {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
+                               {1, 1073741816},          // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
+                               {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
                        },
                        outputs: []outputInfo{
-                               {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
+                               {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
                        },
                },
        },
        {
-               name:    "NORconst",
-               auxType: auxInt32,
-               argLen:  1,
-               asm:     mips.ANOR,
+               name:   "MOVWloadidx",
+               argLen: 3,
+               asm:    loong64.AMOVW,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
+                               {1, 1073741816},          // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
+                               {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
                        },
                        outputs: []outputInfo{
-                               {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
+                               {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
                        },
                },
        },
        {
-               name:   "NEG",
-               argLen: 1,
+               name:   "MOVWUloadidx",
+               argLen: 3,
+               asm:    loong64.AMOVWU,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
+                               {1, 1073741816},          // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
+                               {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
                        },
                        outputs: []outputInfo{
-                               {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
+                               {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
                        },
                },
        },
        {
-               name:   "NEGF",
-               argLen: 1,
-               asm:    mips.ANEGF,
+               name:   "MOVHloadidx",
+               argLen: 3,
+               asm:    loong64.AMOVH,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
+                               {1, 1073741816},          // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
+                               {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
                        },
                        outputs: []outputInfo{
-                               {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
+                               {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
                        },
                },
        },
        {
-               name:   "NEGD",
-               argLen: 1,
-               asm:    mips.ANEGD,
+               name:   "MOVHUloadidx",
+               argLen: 3,
+               asm:    loong64.AMOVHU,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
+                               {1, 1073741816},          // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
+                               {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
                        },
                        outputs: []outputInfo{
-                               {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
+                               {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
                        },
                },
        },
        {
-               name:   "ABSD",
-               argLen: 1,
-               asm:    mips.AABSD,
+               name:   "MOVBloadidx",
+               argLen: 3,
+               asm:    loong64.AMOVB,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
+                               {1, 1073741816},          // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
+                               {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
                        },
                        outputs: []outputInfo{
-                               {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
+                               {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
                        },
                },
        },
        {
-               name:   "SQRTD",
-               argLen: 1,
-               asm:    mips.ASQRTD,
+               name:   "MOVBUloadidx",
+               argLen: 3,
+               asm:    loong64.AMOVBU,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
+                               {1, 1073741816},          // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
+                               {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
                        },
                        outputs: []outputInfo{
-                               {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
+                               {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
                        },
                },
        },
        {
-               name:   "SQRTF",
-               argLen: 1,
-               asm:    mips.ASQRTF,
+               name:   "MOVFloadidx",
+               argLen: 3,
+               asm:    loong64.AMOVF,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
+                               {1, 1073741816},          // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
+                               {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
                        },
                        outputs: []outputInfo{
-                               {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
+                               {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
                        },
                },
        },
        {
-               name:   "SLL",
-               argLen: 2,
-               asm:    mips.ASLL,
+               name:   "MOVDloadidx",
+               argLen: 3,
+               asm:    loong64.AMOVD,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
-                               {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
+                               {1, 1073741816},          // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
+                               {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
                        },
                        outputs: []outputInfo{
-                               {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
+                               {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
                        },
                },
        },
        {
-               name:    "SLLconst",
-               auxType: auxInt32,
-               argLen:  1,
-               asm:     mips.ASLL,
+               name:           "MOVBstore",
+               auxType:        auxSymOff,
+               argLen:         3,
+               faultOnNilArg0: true,
+               symEffect:      SymWrite,
+               asm:            loong64.AMOVB,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
-                       },
-                       outputs: []outputInfo{
-                               {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
+                               {1, 1073741816},          // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
+                               {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
                        },
                },
        },
        {
-               name:   "SRL",
-               argLen: 2,
-               asm:    mips.ASRL,
+               name:           "MOVHstore",
+               auxType:        auxSymOff,
+               argLen:         3,
+               faultOnNilArg0: true,
+               symEffect:      SymWrite,
+               asm:            loong64.AMOVH,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
-                               {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
-                       },
-                       outputs: []outputInfo{
-                               {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
+                               {1, 1073741816},          // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
+                               {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
                        },
                },
        },
        {
-               name:    "SRLconst",
-               auxType: auxInt32,
-               argLen:  1,
-               asm:     mips.ASRL,
+               name:           "MOVWstore",
+               auxType:        auxSymOff,
+               argLen:         3,
+               faultOnNilArg0: true,
+               symEffect:      SymWrite,
+               asm:            loong64.AMOVW,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
-                       },
-                       outputs: []outputInfo{
-                               {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
+                               {1, 1073741816},          // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
+                               {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
                        },
                },
        },
        {
-               name:   "SRA",
-               argLen: 2,
-               asm:    mips.ASRA,
+               name:           "MOVVstore",
+               auxType:        auxSymOff,
+               argLen:         3,
+               faultOnNilArg0: true,
+               symEffect:      SymWrite,
+               asm:            loong64.AMOVV,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
-                               {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
-                       },
-                       outputs: []outputInfo{
-                               {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
+                               {1, 1073741816},          // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
+                               {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
                        },
                },
        },
        {
-               name:    "SRAconst",
-               auxType: auxInt32,
-               argLen:  1,
-               asm:     mips.ASRA,
+               name:           "MOVFstore",
+               auxType:        auxSymOff,
+               argLen:         3,
+               faultOnNilArg0: true,
+               symEffect:      SymWrite,
+               asm:            loong64.AMOVF,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
-                       },
-                       outputs: []outputInfo{
-                               {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
+                               {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
+                               {1, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
                        },
                },
        },
        {
-               name:   "CLZ",
-               argLen: 1,
-               asm:    mips.ACLZ,
+               name:           "MOVDstore",
+               auxType:        auxSymOff,
+               argLen:         3,
+               faultOnNilArg0: true,
+               symEffect:      SymWrite,
+               asm:            loong64.AMOVD,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
-                       },
-                       outputs: []outputInfo{
-                               {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
+                               {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
+                               {1, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
                        },
                },
        },
        {
-               name:   "SGT",
-               argLen: 2,
-               asm:    mips.ASGT,
+               name:   "MOVBstoreidx",
+               argLen: 4,
+               asm:    loong64.AMOVB,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
-                               {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
-                       },
-                       outputs: []outputInfo{
-                               {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
+                               {1, 1073741816},          // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
+                               {2, 1073741816},          // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
+                               {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
                        },
                },
        },
        {
-               name:    "SGTconst",
-               auxType: auxInt32,
-               argLen:  1,
-               asm:     mips.ASGT,
+               name:   "MOVHstoreidx",
+               argLen: 4,
+               asm:    loong64.AMOVH,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
-                       },
-                       outputs: []outputInfo{
-                               {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
+                               {1, 1073741816},          // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
+                               {2, 1073741816},          // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
+                               {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
                        },
                },
        },
        {
-               name:   "SGTzero",
-               argLen: 1,
-               asm:    mips.ASGT,
+               name:   "MOVWstoreidx",
+               argLen: 4,
+               asm:    loong64.AMOVW,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
-                       },
-                       outputs: []outputInfo{
-                               {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
+                               {1, 1073741816},          // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
+                               {2, 1073741816},          // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
+                               {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
                        },
                },
        },
        {
-               name:   "SGTU",
-               argLen: 2,
-               asm:    mips.ASGTU,
+               name:   "MOVVstoreidx",
+               argLen: 4,
+               asm:    loong64.AMOVV,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
-                               {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
-                       },
-                       outputs: []outputInfo{
-                               {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
+                               {1, 1073741816},          // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
+                               {2, 1073741816},          // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
+                               {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
                        },
                },
        },
        {
-               name:    "SGTUconst",
-               auxType: auxInt32,
-               argLen:  1,
-               asm:     mips.ASGTU,
+               name:   "MOVFstoreidx",
+               argLen: 4,
+               asm:    loong64.AMOVF,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
-                       },
-                       outputs: []outputInfo{
-                               {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
+                               {1, 1073741816},          // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
+                               {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
+                               {2, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
                        },
                },
        },
        {
-               name:   "SGTUzero",
-               argLen: 1,
-               asm:    mips.ASGTU,
+               name:   "MOVDstoreidx",
+               argLen: 4,
+               asm:    loong64.AMOVD,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
-                       },
-                       outputs: []outputInfo{
-                               {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
+                               {1, 1073741816},          // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
+                               {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
+                               {2, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
                        },
                },
        },
        {
-               name:   "CMPEQF",
-               argLen: 2,
-               asm:    mips.ACMPEQF,
+               name:           "MOVBstorezero",
+               auxType:        auxSymOff,
+               argLen:         2,
+               faultOnNilArg0: true,
+               symEffect:      SymWrite,
+               asm:            loong64.AMOVB,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
-                               {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
+                               {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
                        },
                },
        },
        {
-               name:   "CMPEQD",
-               argLen: 2,
-               asm:    mips.ACMPEQD,
+               name:           "MOVHstorezero",
+               auxType:        auxSymOff,
+               argLen:         2,
+               faultOnNilArg0: true,
+               symEffect:      SymWrite,
+               asm:            loong64.AMOVH,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
-                               {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
+                               {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
                        },
                },
        },
        {
-               name:   "CMPGEF",
-               argLen: 2,
-               asm:    mips.ACMPGEF,
+               name:           "MOVWstorezero",
+               auxType:        auxSymOff,
+               argLen:         2,
+               faultOnNilArg0: true,
+               symEffect:      SymWrite,
+               asm:            loong64.AMOVW,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
-                               {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
+                               {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
                        },
                },
        },
        {
-               name:   "CMPGED",
-               argLen: 2,
-               asm:    mips.ACMPGED,
+               name:           "MOVVstorezero",
+               auxType:        auxSymOff,
+               argLen:         2,
+               faultOnNilArg0: true,
+               symEffect:      SymWrite,
+               asm:            loong64.AMOVV,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
-                               {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
+                               {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
                        },
                },
        },
        {
-               name:   "CMPGTF",
-               argLen: 2,
-               asm:    mips.ACMPGTF,
+               name:   "MOVBstorezeroidx",
+               argLen: 3,
+               asm:    loong64.AMOVB,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
-                               {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
+                               {1, 1073741816},          // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
+                               {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
                        },
                },
        },
        {
-               name:   "CMPGTD",
-               argLen: 2,
-               asm:    mips.ACMPGTD,
+               name:   "MOVHstorezeroidx",
+               argLen: 3,
+               asm:    loong64.AMOVH,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
-                               {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
-                       },
-               },
-       },
-       {
-               name:              "MOVWconst",
-               auxType:           auxInt32,
-               argLen:            0,
-               rematerializeable: true,
-               asm:               mips.AMOVW,
-               reg: regInfo{
-                       outputs: []outputInfo{
-                               {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
-                       },
-               },
-       },
-       {
-               name:              "MOVFconst",
-               auxType:           auxFloat32,
-               argLen:            0,
-               rematerializeable: true,
-               asm:               mips.AMOVF,
-               reg: regInfo{
-                       outputs: []outputInfo{
-                               {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
-                       },
-               },
-       },
-       {
-               name:              "MOVDconst",
-               auxType:           auxFloat64,
-               argLen:            0,
-               rematerializeable: true,
-               asm:               mips.AMOVD,
-               reg: regInfo{
-                       outputs: []outputInfo{
-                               {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
+                               {1, 1073741816},          // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
+                               {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
                        },
                },
        },
        {
-               name:              "MOVWaddr",
-               auxType:           auxSymOff,
-               argLen:            1,
-               rematerializeable: true,
-               symEffect:         SymAddr,
-               asm:               mips.AMOVW,
+               name:   "MOVWstorezeroidx",
+               argLen: 3,
+               asm:    loong64.AMOVW,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 140737555464192}, // SP SB
-                       },
-                       outputs: []outputInfo{
-                               {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
+                               {1, 1073741816},          // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
+                               {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
                        },
                },
        },
        {
-               name:           "MOVBload",
-               auxType:        auxSymOff,
-               argLen:         2,
-               faultOnNilArg0: true,
-               symEffect:      SymRead,
-               asm:            mips.AMOVB,
+               name:   "MOVVstorezeroidx",
+               argLen: 3,
+               asm:    loong64.AMOVV,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB
-                       },
-                       outputs: []outputInfo{
-                               {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
+                               {1, 1073741816},          // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
+                               {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
                        },
                },
        },
        {
-               name:           "MOVBUload",
-               auxType:        auxSymOff,
-               argLen:         2,
-               faultOnNilArg0: true,
-               symEffect:      SymRead,
-               asm:            mips.AMOVBU,
+               name:   "MOVWfpgp",
+               argLen: 1,
+               asm:    loong64.AMOVW,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB
+                               {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
                        },
                        outputs: []outputInfo{
-                               {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
+                               {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
                        },
                },
        },
        {
-               name:           "MOVHload",
-               auxType:        auxSymOff,
-               argLen:         2,
-               faultOnNilArg0: true,
-               symEffect:      SymRead,
-               asm:            mips.AMOVH,
+               name:   "MOVWgpfp",
+               argLen: 1,
+               asm:    loong64.AMOVW,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB
+                               {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
                        },
                        outputs: []outputInfo{
-                               {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
+                               {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
                        },
                },
        },
        {
-               name:           "MOVHUload",
-               auxType:        auxSymOff,
-               argLen:         2,
-               faultOnNilArg0: true,
-               symEffect:      SymRead,
-               asm:            mips.AMOVHU,
+               name:   "MOVVfpgp",
+               argLen: 1,
+               asm:    loong64.AMOVV,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB
+                               {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
                        },
                        outputs: []outputInfo{
-                               {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
+                               {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
                        },
                },
        },
        {
-               name:           "MOVWload",
-               auxType:        auxSymOff,
-               argLen:         2,
-               faultOnNilArg0: true,
-               symEffect:      SymRead,
-               asm:            mips.AMOVW,
+               name:   "MOVVgpfp",
+               argLen: 1,
+               asm:    loong64.AMOVV,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB
+                               {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
                        },
                        outputs: []outputInfo{
-                               {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
+                               {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
                        },
                },
        },
        {
-               name:           "MOVFload",
-               auxType:        auxSymOff,
-               argLen:         2,
-               faultOnNilArg0: true,
-               symEffect:      SymRead,
-               asm:            mips.AMOVF,
+               name:   "MOVBreg",
+               argLen: 1,
+               asm:    loong64.AMOVB,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB
+                               {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
                        },
                        outputs: []outputInfo{
-                               {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
+                               {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
                        },
                },
        },
        {
-               name:           "MOVDload",
-               auxType:        auxSymOff,
-               argLen:         2,
-               faultOnNilArg0: true,
-               symEffect:      SymRead,
-               asm:            mips.AMOVD,
+               name:   "MOVBUreg",
+               argLen: 1,
+               asm:    loong64.AMOVBU,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB
+                               {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
                        },
                        outputs: []outputInfo{
-                               {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
-                       },
-               },
-       },
-       {
-               name:           "MOVBstore",
-               auxType:        auxSymOff,
-               argLen:         3,
-               faultOnNilArg0: true,
-               symEffect:      SymWrite,
-               asm:            mips.AMOVB,
-               reg: regInfo{
-                       inputs: []inputInfo{
-                               {1, 469762046},       // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
-                               {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB
-                       },
-               },
-       },
-       {
-               name:           "MOVHstore",
-               auxType:        auxSymOff,
-               argLen:         3,
-               faultOnNilArg0: true,
-               symEffect:      SymWrite,
-               asm:            mips.AMOVH,
-               reg: regInfo{
-                       inputs: []inputInfo{
-                               {1, 469762046},       // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
-                               {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB
-                       },
-               },
-       },
-       {
-               name:           "MOVWstore",
-               auxType:        auxSymOff,
-               argLen:         3,
-               faultOnNilArg0: true,
-               symEffect:      SymWrite,
-               asm:            mips.AMOVW,
-               reg: regInfo{
-                       inputs: []inputInfo{
-                               {1, 469762046},       // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
-                               {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB
-                       },
-               },
-       },
-       {
-               name:           "MOVFstore",
-               auxType:        auxSymOff,
-               argLen:         3,
-               faultOnNilArg0: true,
-               symEffect:      SymWrite,
-               asm:            mips.AMOVF,
-               reg: regInfo{
-                       inputs: []inputInfo{
-                               {1, 35183835217920},  // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
-                               {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB
+                               {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
                        },
                },
        },
        {
-               name:           "MOVDstore",
-               auxType:        auxSymOff,
-               argLen:         3,
-               faultOnNilArg0: true,
-               symEffect:      SymWrite,
-               asm:            mips.AMOVD,
+               name:   "MOVHreg",
+               argLen: 1,
+               asm:    loong64.AMOVH,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {1, 35183835217920},  // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
-                               {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB
+                               {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
                        },
-               },
-       },
-       {
-               name:           "MOVBstorezero",
-               auxType:        auxSymOff,
-               argLen:         2,
-               faultOnNilArg0: true,
-               symEffect:      SymWrite,
-               asm:            mips.AMOVB,
-               reg: regInfo{
-                       inputs: []inputInfo{
-                               {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB
+                       outputs: []outputInfo{
+                               {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
                        },
                },
        },
        {
-               name:           "MOVHstorezero",
-               auxType:        auxSymOff,
-               argLen:         2,
-               faultOnNilArg0: true,
-               symEffect:      SymWrite,
-               asm:            mips.AMOVH,
+               name:   "MOVHUreg",
+               argLen: 1,
+               asm:    loong64.AMOVHU,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB
+                               {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
                        },
-               },
-       },
-       {
-               name:           "MOVWstorezero",
-               auxType:        auxSymOff,
-               argLen:         2,
-               faultOnNilArg0: true,
-               symEffect:      SymWrite,
-               asm:            mips.AMOVW,
-               reg: regInfo{
-                       inputs: []inputInfo{
-                               {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB
+                       outputs: []outputInfo{
+                               {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
                        },
                },
        },
        {
-               name:   "MOVWfpgp",
+               name:   "MOVWreg",
                argLen: 1,
-               asm:    mips.AMOVW,
+               asm:    loong64.AMOVW,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
+                               {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
                        },
                        outputs: []outputInfo{
-                               {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
+                               {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
                        },
                },
        },
        {
-               name:   "MOVWgpfp",
+               name:   "MOVWUreg",
                argLen: 1,
-               asm:    mips.AMOVW,
+               asm:    loong64.AMOVWU,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
+                               {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
                        },
                        outputs: []outputInfo{
-                               {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
+                               {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
                        },
                },
        },
        {
-               name:   "MOVBreg",
+               name:   "MOVVreg",
                argLen: 1,
-               asm:    mips.AMOVB,
+               asm:    loong64.AMOVV,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
+                               {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
                        },
                        outputs: []outputInfo{
-                               {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
+                               {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
                        },
                },
        },
        {
-               name:   "MOVBUreg",
-               argLen: 1,
-               asm:    mips.AMOVBU,
+               name:         "MOVVnop",
+               argLen:       1,
+               resultInArg0: true,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
+                               {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
                        },
                        outputs: []outputInfo{
-                               {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
+                               {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
                        },
                },
        },
        {
-               name:   "MOVHreg",
+               name:   "MOVWF",
                argLen: 1,
-               asm:    mips.AMOVH,
+               asm:    loong64.AMOVWF,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
+                               {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
                        },
                        outputs: []outputInfo{
-                               {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
+                               {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
                        },
                },
        },
        {
-               name:   "MOVHUreg",
+               name:   "MOVWD",
                argLen: 1,
-               asm:    mips.AMOVHU,
+               asm:    loong64.AMOVWD,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
+                               {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
                        },
                        outputs: []outputInfo{
-                               {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
+                               {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
                        },
                },
        },
        {
-               name:   "MOVWreg",
+               name:   "MOVVF",
                argLen: 1,
-               asm:    mips.AMOVW,
+               asm:    loong64.AMOVVF,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
+                               {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
                        },
                        outputs: []outputInfo{
-                               {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
+                               {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
                        },
                },
        },
        {
-               name:         "MOVWnop",
-               argLen:       1,
-               resultInArg0: true,
+               name:   "MOVVD",
+               argLen: 1,
+               asm:    loong64.AMOVVD,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
+                               {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
                        },
                        outputs: []outputInfo{
-                               {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
+                               {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
                        },
                },
        },
        {
-               name:         "CMOVZ",
-               argLen:       3,
-               resultInArg0: true,
-               asm:          mips.ACMOVZ,
+               name:   "TRUNCFW",
+               argLen: 1,
+               asm:    loong64.ATRUNCFW,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
-                               {1, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
-                               {2, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
+                               {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
                        },
                        outputs: []outputInfo{
-                               {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
+                               {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
                        },
                },
        },
        {
-               name:         "CMOVZzero",
-               argLen:       2,
-               resultInArg0: true,
-               asm:          mips.ACMOVZ,
+               name:   "TRUNCDW",
+               argLen: 1,
+               asm:    loong64.ATRUNCDW,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
-                               {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
+                               {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
                        },
                        outputs: []outputInfo{
-                               {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
+                               {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
                        },
                },
        },
        {
-               name:   "MOVWF",
+               name:   "TRUNCFV",
                argLen: 1,
-               asm:    mips.AMOVWF,
+               asm:    loong64.ATRUNCFV,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
+                               {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
                        },
                        outputs: []outputInfo{
-                               {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
+                               {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
                        },
                },
        },
        {
-               name:   "MOVWD",
+               name:   "TRUNCDV",
                argLen: 1,
-               asm:    mips.AMOVWD,
+               asm:    loong64.ATRUNCDV,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
+                               {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
                        },
                        outputs: []outputInfo{
-                               {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
+                               {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
                        },
                },
        },
        {
-               name:   "TRUNCFW",
+               name:   "MOVFD",
                argLen: 1,
-               asm:    mips.ATRUNCFW,
+               asm:    loong64.AMOVFD,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
+                               {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
                        },
                        outputs: []outputInfo{
-                               {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
+                               {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
                        },
                },
        },
        {
-               name:   "TRUNCDW",
+               name:   "MOVDF",
                argLen: 1,
-               asm:    mips.ATRUNCDW,
+               asm:    loong64.AMOVDF,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
+                               {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
                        },
                        outputs: []outputInfo{
-                               {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
+                               {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
                        },
                },
        },
        {
-               name:   "MOVFD",
-               argLen: 1,
-               asm:    mips.AMOVFD,
+               name:         "LoweredRound32F",
+               argLen:       1,
+               resultInArg0: true,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
+                               {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
                        },
                        outputs: []outputInfo{
-                               {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
+                               {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
                        },
                },
        },
        {
-               name:   "MOVDF",
-               argLen: 1,
-               asm:    mips.AMOVDF,
+               name:         "LoweredRound64F",
+               argLen:       1,
+               resultInArg0: true,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
+                               {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
                        },
                        outputs: []outputInfo{
-                               {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
+                               {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
                        },
                },
        },
        {
                name:         "CALLstatic",
                auxType:      auxCallOff,
-               argLen:       1,
+               argLen:       -1,
                clobberFlags: true,
                call:         true,
                reg: regInfo{
-                       clobbers: 140737421246462, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 HI LO
+                       clobbers: 4611686018427387896, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
                },
        },
        {
                name:         "CALLtail",
                auxType:      auxCallOff,
-               argLen:       1,
+               argLen:       -1,
                clobberFlags: true,
                call:         true,
                tailCall:     true,
                reg: regInfo{
-                       clobbers: 140737421246462, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 HI LO
+                       clobbers: 4611686018427387896, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
                },
        },
        {
                name:         "CALLclosure",
                auxType:      auxCallOff,
-               argLen:       3,
+               argLen:       -1,
                clobberFlags: true,
                call:         true,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {1, 4194304},   // R22
-                               {0, 402653182}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP R31
+                               {1, 268435456},  // R29
+                               {0, 1071644668}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
                        },
-                       clobbers: 140737421246462, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 HI LO
+                       clobbers: 4611686018427387896, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
                },
        },
        {
                name:         "CALLinter",
                auxType:      auxCallOff,
-               argLen:       2,
+               argLen:       -1,
                clobberFlags: true,
                call:         true,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
+                               {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
                        },
-                       clobbers: 140737421246462, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 HI LO
+                       clobbers: 4611686018427387896, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
                },
        },
        {
-               name:           "LoweredAtomicLoad8",
+               name:           "DUFFZERO",
+               auxType:        auxInt64,
                argLen:         2,
                faultOnNilArg0: true,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB
-                       },
-                       outputs: []outputInfo{
-                               {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
+                               {0, 524288}, // R20
                        },
+                       clobbers: 524290, // R1 R20
                },
        },
        {
-               name:           "LoweredAtomicLoad32",
-               argLen:         2,
+               name:           "DUFFCOPY",
+               auxType:        auxInt64,
+               argLen:         3,
                faultOnNilArg0: true,
+               faultOnNilArg1: true,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB
-                       },
-                       outputs: []outputInfo{
-                               {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
+                               {0, 1048576}, // R21
+                               {1, 524288},  // R20
                        },
+                       clobbers: 1572866, // R1 R20 R21
                },
        },
        {
-               name:           "LoweredAtomicStore8",
+               name:           "LoweredZero",
+               auxType:        auxInt64,
                argLen:         3,
                faultOnNilArg0: true,
-               hasSideEffects: true,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {1, 469762046},       // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
-                               {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB
+                               {0, 524288},     // R20
+                               {1, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
                        },
+                       clobbers: 524288, // R20
                },
        },
        {
-               name:           "LoweredAtomicStore32",
-               argLen:         3,
+               name:           "LoweredMove",
+               auxType:        auxInt64,
+               argLen:         4,
                faultOnNilArg0: true,
-               hasSideEffects: true,
+               faultOnNilArg1: true,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {1, 469762046},       // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
-                               {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB
+                               {0, 1048576},    // R21
+                               {1, 524288},     // R20
+                               {2, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
                        },
+                       clobbers: 1572864, // R20 R21
                },
        },
        {
-               name:           "LoweredAtomicStorezero",
+               name:           "LoweredAtomicLoad8",
                argLen:         2,
                faultOnNilArg0: true,
-               hasSideEffects: true,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB
+                               {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
+                       },
+                       outputs: []outputInfo{
+                               {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
                        },
                },
        },
        {
-               name:            "LoweredAtomicExchange",
-               argLen:          3,
-               resultNotInArgs: true,
-               faultOnNilArg0:  true,
-               hasSideEffects:  true,
-               unsafePoint:     true,
+               name:           "LoweredAtomicLoad32",
+               argLen:         2,
+               faultOnNilArg0: true,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {1, 469762046},       // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
-                               {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB
+                               {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
                        },
                        outputs: []outputInfo{
-                               {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
+                               {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
                        },
                },
        },
        {
-               name:            "LoweredAtomicAdd",
-               argLen:          3,
-               resultNotInArgs: true,
-               faultOnNilArg0:  true,
-               hasSideEffects:  true,
-               unsafePoint:     true,
+               name:           "LoweredAtomicLoad64",
+               argLen:         2,
+               faultOnNilArg0: true,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {1, 469762046},       // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
-                               {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB
+                               {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
                        },
                        outputs: []outputInfo{
-                               {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
+                               {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
                        },
                },
        },
        {
-               name:            "LoweredAtomicAddconst",
-               auxType:         auxInt32,
-               argLen:          2,
+               name:           "LoweredAtomicStore8",
+               argLen:         3,
+               faultOnNilArg0: true,
+               hasSideEffects: true,
+               reg: regInfo{
+                       inputs: []inputInfo{
+                               {1, 1073741816},          // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
+                               {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
+                       },
+               },
+       },
+       {
+               name:           "LoweredAtomicStore32",
+               argLen:         3,
+               faultOnNilArg0: true,
+               hasSideEffects: true,
+               reg: regInfo{
+                       inputs: []inputInfo{
+                               {1, 1073741816},          // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
+                               {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
+                       },
+               },
+       },
+       {
+               name:           "LoweredAtomicStore64",
+               argLen:         3,
+               faultOnNilArg0: true,
+               hasSideEffects: true,
+               reg: regInfo{
+                       inputs: []inputInfo{
+                               {1, 1073741816},          // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
+                               {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
+                       },
+               },
+       },
+       {
+               name:           "LoweredAtomicStore8Variant",
+               argLen:         3,
+               faultOnNilArg0: true,
+               hasSideEffects: true,
+               reg: regInfo{
+                       inputs: []inputInfo{
+                               {1, 1073741816},          // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
+                               {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
+                       },
+               },
+       },
+       {
+               name:           "LoweredAtomicStore32Variant",
+               argLen:         3,
+               faultOnNilArg0: true,
+               hasSideEffects: true,
+               reg: regInfo{
+                       inputs: []inputInfo{
+                               {1, 1073741816},          // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
+                               {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
+                       },
+               },
+       },
+       {
+               name:           "LoweredAtomicStore64Variant",
+               argLen:         3,
+               faultOnNilArg0: true,
+               hasSideEffects: true,
+               reg: regInfo{
+                       inputs: []inputInfo{
+                               {1, 1073741816},          // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
+                               {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
+                       },
+               },
+       },
+       {
+               name:            "LoweredAtomicExchange32",
+               argLen:          3,
+               resultNotInArgs: true,
+               faultOnNilArg0:  true,
+               hasSideEffects:  true,
+               reg: regInfo{
+                       inputs: []inputInfo{
+                               {1, 1073741816},          // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
+                               {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
+                       },
+                       outputs: []outputInfo{
+                               {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
+                       },
+               },
+       },
+       {
+               name:            "LoweredAtomicExchange64",
+               argLen:          3,
+               resultNotInArgs: true,
+               faultOnNilArg0:  true,
+               hasSideEffects:  true,
+               reg: regInfo{
+                       inputs: []inputInfo{
+                               {1, 1073741816},          // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
+                               {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
+                       },
+                       outputs: []outputInfo{
+                               {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
+                       },
+               },
+       },
+       {
+               name:            "LoweredAtomicExchange8Variant",
+               argLen:          3,
+               resultNotInArgs: true,
+               faultOnNilArg0:  true,
+               hasSideEffects:  true,
+               reg: regInfo{
+                       inputs: []inputInfo{
+                               {1, 1073741816},          // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
+                               {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
+                       },
+                       outputs: []outputInfo{
+                               {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
+                       },
+               },
+       },
+       {
+               name:            "LoweredAtomicAdd32",
+               argLen:          3,
+               resultNotInArgs: true,
+               faultOnNilArg0:  true,
+               hasSideEffects:  true,
+               reg: regInfo{
+                       inputs: []inputInfo{
+                               {1, 1073741816},          // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
+                               {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
+                       },
+                       outputs: []outputInfo{
+                               {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
+                       },
+               },
+       },
+       {
+               name:            "LoweredAtomicAdd64",
+               argLen:          3,
+               resultNotInArgs: true,
+               faultOnNilArg0:  true,
+               hasSideEffects:  true,
+               reg: regInfo{
+                       inputs: []inputInfo{
+                               {1, 1073741816},          // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
+                               {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
+                       },
+                       outputs: []outputInfo{
+                               {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
+                       },
+               },
+       },
+       {
+               name:            "LoweredAtomicCas32",
+               argLen:          4,
                resultNotInArgs: true,
                faultOnNilArg0:  true,
                hasSideEffects:  true,
                unsafePoint:     true,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB
+                               {1, 1073741816},          // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
+                               {2, 1073741816},          // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
+                               {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
                        },
                        outputs: []outputInfo{
-                               {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
+                               {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
                        },
                },
        },
        {
-               name:            "LoweredAtomicCas",
+               name:            "LoweredAtomicCas64",
                argLen:          4,
                resultNotInArgs: true,
                faultOnNilArg0:  true,
@@ -40880,69 +42912,151 @@ var opcodeTable = [...]opInfo{
                unsafePoint:     true,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {1, 469762046},       // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
-                               {2, 469762046},       // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
-                               {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB
+                               {1, 1073741816},          // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
+                               {2, 1073741816},          // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
+                               {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
                        },
                        outputs: []outputInfo{
-                               {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
+                               {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
                        },
                },
        },
        {
-               name:           "LoweredAtomicAnd",
-               argLen:         3,
-               faultOnNilArg0: true,
-               hasSideEffects: true,
-               unsafePoint:    true,
-               asm:            mips.AAND,
+               name:            "LoweredAtomicCas64Variant",
+               argLen:          4,
+               resultNotInArgs: true,
+               faultOnNilArg0:  true,
+               hasSideEffects:  true,
+               unsafePoint:     true,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {1, 469762046},       // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
-                               {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB
+                               {1, 1073741816},          // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
+                               {2, 1073741816},          // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
+                               {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
+                       },
+                       outputs: []outputInfo{
+                               {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
                        },
                },
        },
        {
-               name:           "LoweredAtomicOr",
-               argLen:         3,
-               faultOnNilArg0: true,
-               hasSideEffects: true,
-               unsafePoint:    true,
-               asm:            mips.AOR,
+               name:            "LoweredAtomicCas32Variant",
+               argLen:          4,
+               resultNotInArgs: true,
+               faultOnNilArg0:  true,
+               hasSideEffects:  true,
+               unsafePoint:     true,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {1, 469762046},       // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
-                               {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB
+                               {1, 1073741816},          // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
+                               {2, 1073741816},          // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
+                               {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
+                       },
+                       outputs: []outputInfo{
+                               {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
                        },
                },
        },
        {
-               name:           "LoweredZero",
-               auxType:        auxInt32,
-               argLen:         3,
-               faultOnNilArg0: true,
+               name:            "LoweredAtomicAnd32",
+               argLen:          3,
+               resultNotInArgs: true,
+               faultOnNilArg0:  true,
+               hasSideEffects:  true,
+               asm:             loong64.AAMANDDBW,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 2},         // R1
-                               {1, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
+                               {1, 1073741816},          // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
+                               {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
+                       },
+                       outputs: []outputInfo{
+                               {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
                        },
-                       clobbers: 2, // R1
                },
        },
        {
-               name:           "LoweredMove",
-               auxType:        auxInt32,
-               argLen:         4,
-               faultOnNilArg0: true,
-               faultOnNilArg1: true,
+               name:            "LoweredAtomicOr32",
+               argLen:          3,
+               resultNotInArgs: true,
+               faultOnNilArg0:  true,
+               hasSideEffects:  true,
+               asm:             loong64.AAMORDBW,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 4},         // R2
-                               {1, 2},         // R1
-                               {2, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
+                               {1, 1073741816},          // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
+                               {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
+                       },
+                       outputs: []outputInfo{
+                               {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
+                       },
+               },
+       },
+       {
+               name:            "LoweredAtomicAnd32value",
+               argLen:          3,
+               resultNotInArgs: true,
+               faultOnNilArg0:  true,
+               hasSideEffects:  true,
+               asm:             loong64.AAMANDDBW,
+               reg: regInfo{
+                       inputs: []inputInfo{
+                               {1, 1073741816},          // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
+                               {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
+                       },
+                       outputs: []outputInfo{
+                               {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
+                       },
+               },
+       },
+       {
+               name:            "LoweredAtomicAnd64value",
+               argLen:          3,
+               resultNotInArgs: true,
+               faultOnNilArg0:  true,
+               hasSideEffects:  true,
+               asm:             loong64.AAMANDDBV,
+               reg: regInfo{
+                       inputs: []inputInfo{
+                               {1, 1073741816},          // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
+                               {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
+                       },
+                       outputs: []outputInfo{
+                               {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
+                       },
+               },
+       },
+       {
+               name:            "LoweredAtomicOr32value",
+               argLen:          3,
+               resultNotInArgs: true,
+               faultOnNilArg0:  true,
+               hasSideEffects:  true,
+               asm:             loong64.AAMORDBW,
+               reg: regInfo{
+                       inputs: []inputInfo{
+                               {1, 1073741816},          // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
+                               {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
+                       },
+                       outputs: []outputInfo{
+                               {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
+                       },
+               },
+       },
+       {
+               name:            "LoweredAtomicOr64value",
+               argLen:          3,
+               resultNotInArgs: true,
+               faultOnNilArg0:  true,
+               hasSideEffects:  true,
+               asm:             loong64.AAMORDBV,
+               reg: regInfo{
+                       inputs: []inputInfo{
+                               {1, 1073741816},          // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
+                               {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
+                       },
+                       outputs: []outputInfo{
+                               {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
                        },
-                       clobbers: 6, // R1 R2
                },
        },
        {
@@ -40952,7 +43066,7 @@ var opcodeTable = [...]opInfo{
                faultOnNilArg0: true,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
+                               {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
                        },
                },
        },
@@ -40961,7 +43075,7 @@ var opcodeTable = [...]opInfo{
                argLen: 1,
                reg: regInfo{
                        outputs: []outputInfo{
-                               {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
+                               {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
                        },
                },
        },
@@ -40970,7 +43084,7 @@ var opcodeTable = [...]opInfo{
                argLen: 1,
                reg: regInfo{
                        outputs: []outputInfo{
-                               {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
+                               {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
                        },
                },
        },
@@ -40980,7 +43094,7 @@ var opcodeTable = [...]opInfo{
                zeroWidth: true,
                reg: regInfo{
                        outputs: []outputInfo{
-                               {0, 4194304}, // R22
+                               {0, 268435456}, // R29
                        },
                },
        },
@@ -40990,7 +43104,7 @@ var opcodeTable = [...]opInfo{
                rematerializeable: true,
                reg: regInfo{
                        outputs: []outputInfo{
-                               {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
+                               {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
                        },
                },
        },
@@ -41000,7 +43114,7 @@ var opcodeTable = [...]opInfo{
                rematerializeable: true,
                reg: regInfo{
                        outputs: []outputInfo{
-                               {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
+                               {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
                        },
                },
        },
@@ -41010,9 +43124,9 @@ var opcodeTable = [...]opInfo{
                argLen:       1,
                clobberFlags: true,
                reg: regInfo{
-                       clobbers: 140737219919872, // R31 F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 HI LO
+                       clobbers: 4611686017353646082, // R1 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
                        outputs: []outputInfo{
-                               {0, 16777216}, // R25
+                               {0, 268435456}, // R29
                        },
                },
        },
@@ -41020,7 +43134,7 @@ var opcodeTable = [...]opInfo{
                name:           "LoweredPubBarrier",
                argLen:         1,
                hasSideEffects: true,
-               asm:            mips.ASYNC,
+               asm:            loong64.ADBAR,
                reg:            regInfo{},
        },
        {
@@ -41030,8 +43144,8 @@ var opcodeTable = [...]opInfo{
                call:    true,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 8},  // R3
-                               {1, 16}, // R4
+                               {0, 4194304}, // R23
+                               {1, 8388608}, // R24
                        },
                },
        },
@@ -41042,8 +43156,8 @@ var opcodeTable = [...]opInfo{
                call:    true,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 4}, // R2
-                               {1, 8}, // R3
+                               {0, 1048576}, // R21
+                               {1, 4194304}, // R23
                        },
                },
        },
@@ -41054,167 +43168,168 @@ var opcodeTable = [...]opInfo{
                call:    true,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 2}, // R1
-                               {1, 4}, // R2
-                       },
-               },
-       },
-       {
-               name:    "LoweredPanicExtendA",
-               auxType: auxInt64,
-               argLen:  4,
-               call:    true,
-               reg: regInfo{
-                       inputs: []inputInfo{
-                               {0, 32}, // R5
-                               {1, 8},  // R3
-                               {2, 16}, // R4
+                               {0, 524288},  // R20
+                               {1, 1048576}, // R21
                        },
                },
        },
        {
-               name:    "LoweredPanicExtendB",
-               auxType: auxInt64,
-               argLen:  4,
-               call:    true,
+               name:           "PRELD",
+               auxType:        auxInt64,
+               argLen:         2,
+               hasSideEffects: true,
+               asm:            loong64.APRELD,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 32}, // R5
-                               {1, 4},  // R2
-                               {2, 8},  // R3
+                               {0, 1073741820}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
                        },
                },
        },
        {
-               name:    "LoweredPanicExtendC",
-               auxType: auxInt64,
-               argLen:  4,
-               call:    true,
+               name:           "PRELDX",
+               auxType:        auxInt64,
+               argLen:         2,
+               hasSideEffects: true,
+               asm:            loong64.APRELDX,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 32}, // R5
-                               {1, 2},  // R1
-                               {2, 4},  // R2
+                               {0, 1073741820}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
                        },
                },
        },
 
        {
-               name:        "ADDV",
+               name:        "ADD",
                argLen:      2,
                commutative: true,
-               asm:         mips.AADDVU,
+               asm:         mips.AADDU,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
-                               {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
+                               {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
+                               {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
                        },
                        outputs: []outputInfo{
-                               {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
+                               {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
                        },
                },
        },
        {
-               name:    "ADDVconst",
-               auxType: auxInt64,
+               name:    "ADDconst",
+               auxType: auxInt32,
                argLen:  1,
-               asm:     mips.AADDVU,
+               asm:     mips.AADDU,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 268435454}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31
+                               {0, 536870910}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31
                        },
                        outputs: []outputInfo{
-                               {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
+                               {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
                        },
                },
        },
        {
-               name:   "SUBV",
+               name:   "SUB",
                argLen: 2,
-               asm:    mips.ASUBVU,
+               asm:    mips.ASUBU,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
-                               {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
+                               {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
+                               {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
                        },
                        outputs: []outputInfo{
-                               {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
+                               {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
                        },
                },
        },
        {
-               name:    "SUBVconst",
-               auxType: auxInt64,
+               name:    "SUBconst",
+               auxType: auxInt32,
                argLen:  1,
-               asm:     mips.ASUBVU,
+               asm:     mips.ASUBU,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
+                               {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
                        },
                        outputs: []outputInfo{
-                               {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
+                               {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
                        },
                },
        },
        {
-               name:        "MULV",
+               name:        "MUL",
                argLen:      2,
                commutative: true,
-               asm:         mips.AMULV,
+               asm:         mips.AMUL,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
-                               {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
+                               {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
+                               {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
                        },
+                       clobbers: 105553116266496, // HI LO
                        outputs: []outputInfo{
-                               {0, 1152921504606846976}, // HI
-                               {1, 2305843009213693952}, // LO
+                               {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
                        },
                },
        },
        {
-               name:        "MULVU",
+               name:        "MULT",
                argLen:      2,
                commutative: true,
-               asm:         mips.AMULVU,
+               asm:         mips.AMUL,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
-                               {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
+                               {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
+                               {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
                        },
                        outputs: []outputInfo{
-                               {0, 1152921504606846976}, // HI
-                               {1, 2305843009213693952}, // LO
+                               {0, 35184372088832}, // HI
+                               {1, 70368744177664}, // LO
                        },
                },
        },
        {
-               name:   "DIVV",
+               name:        "MULTU",
+               argLen:      2,
+               commutative: true,
+               asm:         mips.AMULU,
+               reg: regInfo{
+                       inputs: []inputInfo{
+                               {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
+                               {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
+                       },
+                       outputs: []outputInfo{
+                               {0, 35184372088832}, // HI
+                               {1, 70368744177664}, // LO
+                       },
+               },
+       },
+       {
+               name:   "DIV",
                argLen: 2,
-               asm:    mips.ADIVV,
+               asm:    mips.ADIV,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
-                               {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
+                               {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
+                               {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
                        },
                        outputs: []outputInfo{
-                               {0, 1152921504606846976}, // HI
-                               {1, 2305843009213693952}, // LO
+                               {0, 35184372088832}, // HI
+                               {1, 70368744177664}, // LO
                        },
                },
        },
        {
-               name:   "DIVVU",
+               name:   "DIVU",
                argLen: 2,
-               asm:    mips.ADIVVU,
+               asm:    mips.ADIVU,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
-                               {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
+                               {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
+                               {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
                        },
                        outputs: []outputInfo{
-                               {0, 1152921504606846976}, // HI
-                               {1, 2305843009213693952}, // LO
+                               {0, 35184372088832}, // HI
+                               {1, 70368744177664}, // LO
                        },
                },
        },
@@ -41225,11 +43340,11 @@ var opcodeTable = [...]opInfo{
                asm:         mips.AADDF,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
-                               {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
+                               {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
                        },
                        outputs: []outputInfo{
-                               {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
                        },
                },
        },
@@ -41240,11 +43355,11 @@ var opcodeTable = [...]opInfo{
                asm:         mips.AADDD,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
-                               {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
+                               {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
                        },
                        outputs: []outputInfo{
-                               {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
                        },
                },
        },
@@ -41254,11 +43369,11 @@ var opcodeTable = [...]opInfo{
                asm:    mips.ASUBF,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
-                               {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
+                               {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
                        },
                        outputs: []outputInfo{
-                               {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
                        },
                },
        },
@@ -41268,11 +43383,11 @@ var opcodeTable = [...]opInfo{
                asm:    mips.ASUBD,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
-                               {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
+                               {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
                        },
                        outputs: []outputInfo{
-                               {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
                        },
                },
        },
@@ -41283,11 +43398,11 @@ var opcodeTable = [...]opInfo{
                asm:         mips.AMULF,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
-                               {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
+                               {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
                        },
                        outputs: []outputInfo{
-                               {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
                        },
                },
        },
@@ -41298,11 +43413,11 @@ var opcodeTable = [...]opInfo{
                asm:         mips.AMULD,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
-                               {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
+                               {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
                        },
                        outputs: []outputInfo{
-                               {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
                        },
                },
        },
@@ -41312,11 +43427,11 @@ var opcodeTable = [...]opInfo{
                asm:    mips.ADIVF,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
-                               {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
+                               {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
                        },
                        outputs: []outputInfo{
-                               {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
                        },
                },
        },
@@ -41326,11 +43441,11 @@ var opcodeTable = [...]opInfo{
                asm:    mips.ADIVD,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
-                               {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
+                               {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
                        },
                        outputs: []outputInfo{
-                               {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
                        },
                },
        },
@@ -41341,25 +43456,25 @@ var opcodeTable = [...]opInfo{
                asm:         mips.AAND,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
-                               {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
+                               {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
+                               {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
                        },
                        outputs: []outputInfo{
-                               {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
+                               {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
                        },
                },
        },
        {
                name:    "ANDconst",
-               auxType: auxInt64,
+               auxType: auxInt32,
                argLen:  1,
                asm:     mips.AAND,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
+                               {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
                        },
                        outputs: []outputInfo{
-                               {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
+                               {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
                        },
                },
        },
@@ -41370,25 +43485,25 @@ var opcodeTable = [...]opInfo{
                asm:         mips.AOR,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
-                               {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
+                               {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
+                               {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
                        },
                        outputs: []outputInfo{
-                               {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
+                               {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
                        },
                },
        },
        {
                name:    "ORconst",
-               auxType: auxInt64,
+               auxType: auxInt32,
                argLen:  1,
                asm:     mips.AOR,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
+                               {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
                        },
                        outputs: []outputInfo{
-                               {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
+                               {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
                        },
                },
        },
@@ -41399,25 +43514,25 @@ var opcodeTable = [...]opInfo{
                asm:         mips.AXOR,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
-                               {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
+                               {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
+                               {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
                        },
                        outputs: []outputInfo{
-                               {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
+                               {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
                        },
                },
        },
        {
                name:    "XORconst",
-               auxType: auxInt64,
+               auxType: auxInt32,
                argLen:  1,
                asm:     mips.AXOR,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
+                               {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
                        },
                        outputs: []outputInfo{
-                               {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
+                               {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
                        },
                },
        },
@@ -41428,37 +43543,37 @@ var opcodeTable = [...]opInfo{
                asm:         mips.ANOR,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
-                               {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
+                               {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
+                               {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
                        },
                        outputs: []outputInfo{
-                               {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
+                               {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
                        },
                },
        },
        {
                name:    "NORconst",
-               auxType: auxInt64,
+               auxType: auxInt32,
                argLen:  1,
                asm:     mips.ANOR,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
+                               {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
                        },
                        outputs: []outputInfo{
-                               {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
+                               {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
                        },
                },
        },
        {
-               name:   "NEGV",
+               name:   "NEG",
                argLen: 1,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
+                               {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
                        },
                        outputs: []outputInfo{
-                               {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
+                               {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
                        },
                },
        },
@@ -41468,10 +43583,10 @@ var opcodeTable = [...]opInfo{
                asm:    mips.ANEGF,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
                        },
                        outputs: []outputInfo{
-                               {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
                        },
                },
        },
@@ -41481,10 +43596,10 @@ var opcodeTable = [...]opInfo{
                asm:    mips.ANEGD,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
                        },
                        outputs: []outputInfo{
-                               {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
                        },
                },
        },
@@ -41494,10 +43609,10 @@ var opcodeTable = [...]opInfo{
                asm:    mips.AABSD,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
                        },
                        outputs: []outputInfo{
-                               {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
                        },
                },
        },
@@ -41507,10 +43622,10 @@ var opcodeTable = [...]opInfo{
                asm:    mips.ASQRTD,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
                        },
                        outputs: []outputInfo{
-                               {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
                        },
                },
        },
@@ -41520,94 +43635,107 @@ var opcodeTable = [...]opInfo{
                asm:    mips.ASQRTF,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
                        },
                        outputs: []outputInfo{
-                               {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
                        },
                },
        },
        {
-               name:   "SLLV",
+               name:   "SLL",
                argLen: 2,
-               asm:    mips.ASLLV,
+               asm:    mips.ASLL,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
-                               {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
+                               {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
+                               {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
                        },
                        outputs: []outputInfo{
-                               {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
+                               {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
                        },
                },
        },
        {
-               name:    "SLLVconst",
-               auxType: auxInt64,
+               name:    "SLLconst",
+               auxType: auxInt32,
                argLen:  1,
-               asm:     mips.ASLLV,
+               asm:     mips.ASLL,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
+                               {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
                        },
                        outputs: []outputInfo{
-                               {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
+                               {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
                        },
                },
        },
        {
-               name:   "SRLV",
+               name:   "SRL",
                argLen: 2,
-               asm:    mips.ASRLV,
+               asm:    mips.ASRL,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
-                               {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
+                               {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
+                               {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
                        },
                        outputs: []outputInfo{
-                               {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
+                               {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
                        },
                },
        },
        {
-               name:    "SRLVconst",
-               auxType: auxInt64,
+               name:    "SRLconst",
+               auxType: auxInt32,
                argLen:  1,
-               asm:     mips.ASRLV,
+               asm:     mips.ASRL,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
+                               {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
                        },
                        outputs: []outputInfo{
-                               {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
+                               {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
                        },
                },
        },
        {
-               name:   "SRAV",
+               name:   "SRA",
                argLen: 2,
-               asm:    mips.ASRAV,
+               asm:    mips.ASRA,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
-                               {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
+                               {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
+                               {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
                        },
                        outputs: []outputInfo{
-                               {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
+                               {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
                        },
                },
        },
        {
-               name:    "SRAVconst",
-               auxType: auxInt64,
+               name:    "SRAconst",
+               auxType: auxInt32,
                argLen:  1,
-               asm:     mips.ASRAV,
+               asm:     mips.ASRA,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
+                               {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
                        },
                        outputs: []outputInfo{
-                               {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
+                               {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
+                       },
+               },
+       },
+       {
+               name:   "CLZ",
+               argLen: 1,
+               asm:    mips.ACLZ,
+               reg: regInfo{
+                       inputs: []inputInfo{
+                               {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
+                       },
+                       outputs: []outputInfo{
+                               {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
                        },
                },
        },
@@ -41617,25 +43745,38 @@ var opcodeTable = [...]opInfo{
                asm:    mips.ASGT,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
-                               {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
+                               {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
+                               {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
                        },
                        outputs: []outputInfo{
-                               {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
+                               {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
                        },
                },
        },
        {
                name:    "SGTconst",
-               auxType: auxInt64,
+               auxType: auxInt32,
                argLen:  1,
                asm:     mips.ASGT,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
+                               {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
                        },
                        outputs: []outputInfo{
-                               {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
+                               {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
+                       },
+               },
+       },
+       {
+               name:   "SGTzero",
+               argLen: 1,
+               asm:    mips.ASGT,
+               reg: regInfo{
+                       inputs: []inputInfo{
+                               {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
+                       },
+                       outputs: []outputInfo{
+                               {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
                        },
                },
        },
@@ -41645,25 +43786,38 @@ var opcodeTable = [...]opInfo{
                asm:    mips.ASGTU,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
-                               {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
+                               {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
+                               {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
                        },
                        outputs: []outputInfo{
-                               {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
+                               {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
                        },
                },
        },
        {
                name:    "SGTUconst",
-               auxType: auxInt64,
+               auxType: auxInt32,
                argLen:  1,
                asm:     mips.ASGTU,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
+                               {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
                        },
                        outputs: []outputInfo{
-                               {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
+                               {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
+                       },
+               },
+       },
+       {
+               name:   "SGTUzero",
+               argLen: 1,
+               asm:    mips.ASGTU,
+               reg: regInfo{
+                       inputs: []inputInfo{
+                               {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
+                       },
+                       outputs: []outputInfo{
+                               {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
                        },
                },
        },
@@ -41673,8 +43827,8 @@ var opcodeTable = [...]opInfo{
                asm:    mips.ACMPEQF,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
-                               {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
+                               {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
                        },
                },
        },
@@ -41684,8 +43838,8 @@ var opcodeTable = [...]opInfo{
                asm:    mips.ACMPEQD,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
-                               {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
+                               {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
                        },
                },
        },
@@ -41695,8 +43849,8 @@ var opcodeTable = [...]opInfo{
                asm:    mips.ACMPGEF,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
-                               {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
+                               {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
                        },
                },
        },
@@ -41706,8 +43860,8 @@ var opcodeTable = [...]opInfo{
                asm:    mips.ACMPGED,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
-                               {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
+                               {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
                        },
                },
        },
@@ -41717,8 +43871,8 @@ var opcodeTable = [...]opInfo{
                asm:    mips.ACMPGTF,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
-                               {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
+                               {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
                        },
                },
        },
@@ -41728,32 +43882,32 @@ var opcodeTable = [...]opInfo{
                asm:    mips.ACMPGTD,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
-                               {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
+                               {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
                        },
                },
        },
        {
-               name:              "MOVVconst",
-               auxType:           auxInt64,
+               name:              "MOVWconst",
+               auxType:           auxInt32,
                argLen:            0,
                rematerializeable: true,
-               asm:               mips.AMOVV,
+               asm:               mips.AMOVW,
                reg: regInfo{
                        outputs: []outputInfo{
-                               {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
+                               {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
                        },
                },
        },
        {
                name:              "MOVFconst",
-               auxType:           auxFloat64,
+               auxType:           auxFloat32,
                argLen:            0,
                rematerializeable: true,
                asm:               mips.AMOVF,
                reg: regInfo{
                        outputs: []outputInfo{
-                               {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
                        },
                },
        },
@@ -41765,23 +43919,23 @@ var opcodeTable = [...]opInfo{
                asm:               mips.AMOVD,
                reg: regInfo{
                        outputs: []outputInfo{
-                               {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
                        },
                },
        },
        {
-               name:              "MOVVaddr",
+               name:              "MOVWaddr",
                auxType:           auxSymOff,
                argLen:            1,
                rematerializeable: true,
                symEffect:         SymAddr,
-               asm:               mips.AMOVV,
+               asm:               mips.AMOVW,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 4611686018460942336}, // SP SB
+                               {0, 140737555464192}, // SP SB
                        },
                        outputs: []outputInfo{
-                               {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
+                               {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
                        },
                },
        },
@@ -41794,10 +43948,10 @@ var opcodeTable = [...]opInfo{
                asm:            mips.AMOVB,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB
+                               {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB
                        },
                        outputs: []outputInfo{
-                               {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
+                               {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
                        },
                },
        },
@@ -41810,10 +43964,10 @@ var opcodeTable = [...]opInfo{
                asm:            mips.AMOVBU,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB
+                               {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB
                        },
                        outputs: []outputInfo{
-                               {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
+                               {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
                        },
                },
        },
@@ -41826,10 +43980,10 @@ var opcodeTable = [...]opInfo{
                asm:            mips.AMOVH,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB
+                               {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB
                        },
                        outputs: []outputInfo{
-                               {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
+                               {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
                        },
                },
        },
@@ -41842,10 +43996,10 @@ var opcodeTable = [...]opInfo{
                asm:            mips.AMOVHU,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB
+                               {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB
                        },
                        outputs: []outputInfo{
-                               {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
+                               {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
                        },
                },
        },
@@ -41858,42 +44012,10 @@ var opcodeTable = [...]opInfo{
                asm:            mips.AMOVW,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB
-                       },
-                       outputs: []outputInfo{
-                               {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
-                       },
-               },
-       },
-       {
-               name:           "MOVWUload",
-               auxType:        auxSymOff,
-               argLen:         2,
-               faultOnNilArg0: true,
-               symEffect:      SymRead,
-               asm:            mips.AMOVWU,
-               reg: regInfo{
-                       inputs: []inputInfo{
-                               {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB
-                       },
-                       outputs: []outputInfo{
-                               {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
-                       },
-               },
-       },
-       {
-               name:           "MOVVload",
-               auxType:        auxSymOff,
-               argLen:         2,
-               faultOnNilArg0: true,
-               symEffect:      SymRead,
-               asm:            mips.AMOVV,
-               reg: regInfo{
-                       inputs: []inputInfo{
-                               {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB
+                               {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB
                        },
                        outputs: []outputInfo{
-                               {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
+                               {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
                        },
                },
        },
@@ -41906,10 +44028,10 @@ var opcodeTable = [...]opInfo{
                asm:            mips.AMOVF,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB
+                               {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB
                        },
                        outputs: []outputInfo{
-                               {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
                        },
                },
        },
@@ -41922,10 +44044,10 @@ var opcodeTable = [...]opInfo{
                asm:            mips.AMOVD,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB
+                               {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB
                        },
                        outputs: []outputInfo{
-                               {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
                        },
                },
        },
@@ -41938,8 +44060,8 @@ var opcodeTable = [...]opInfo{
                asm:            mips.AMOVB,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {1, 234881022},           // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
-                               {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB
+                               {1, 469762046},       // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
+                               {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB
                        },
                },
        },
@@ -41952,8 +44074,8 @@ var opcodeTable = [...]opInfo{
                asm:            mips.AMOVH,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {1, 234881022},           // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
-                               {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB
+                               {1, 469762046},       // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
+                               {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB
                        },
                },
        },
@@ -41966,22 +44088,8 @@ var opcodeTable = [...]opInfo{
                asm:            mips.AMOVW,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {1, 234881022},           // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
-                               {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB
-                       },
-               },
-       },
-       {
-               name:           "MOVVstore",
-               auxType:        auxSymOff,
-               argLen:         3,
-               faultOnNilArg0: true,
-               symEffect:      SymWrite,
-               asm:            mips.AMOVV,
-               reg: regInfo{
-                       inputs: []inputInfo{
-                               {1, 234881022},           // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
-                               {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB
+                               {1, 469762046},       // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
+                               {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB
                        },
                },
        },
@@ -41994,8 +44102,8 @@ var opcodeTable = [...]opInfo{
                asm:            mips.AMOVF,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB
-                               {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {1, 35183835217920},  // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
+                               {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB
                        },
                },
        },
@@ -42008,8 +44116,8 @@ var opcodeTable = [...]opInfo{
                asm:            mips.AMOVD,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB
-                               {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {1, 35183835217920},  // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
+                               {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB
                        },
                },
        },
@@ -42022,7 +44130,7 @@ var opcodeTable = [...]opInfo{
                asm:            mips.AMOVB,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB
+                               {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB
                        },
                },
        },
@@ -42035,7 +44143,7 @@ var opcodeTable = [...]opInfo{
                asm:            mips.AMOVH,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB
+                               {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB
                        },
                },
        },
@@ -42048,20 +44156,7 @@ var opcodeTable = [...]opInfo{
                asm:            mips.AMOVW,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB
-                       },
-               },
-       },
-       {
-               name:           "MOVVstorezero",
-               auxType:        auxSymOff,
-               argLen:         2,
-               faultOnNilArg0: true,
-               symEffect:      SymWrite,
-               asm:            mips.AMOVV,
-               reg: regInfo{
-                       inputs: []inputInfo{
-                               {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB
+                               {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB
                        },
                },
        },
@@ -42071,10 +44166,10 @@ var opcodeTable = [...]opInfo{
                asm:    mips.AMOVW,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
                        },
                        outputs: []outputInfo{
-                               {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
+                               {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
                        },
                },
        },
@@ -42084,36 +44179,10 @@ var opcodeTable = [...]opInfo{
                asm:    mips.AMOVW,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
-                       },
-                       outputs: []outputInfo{
-                               {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
-                       },
-               },
-       },
-       {
-               name:   "MOVVfpgp",
-               argLen: 1,
-               asm:    mips.AMOVV,
-               reg: regInfo{
-                       inputs: []inputInfo{
-                               {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
-                       },
-                       outputs: []outputInfo{
-                               {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
-                       },
-               },
-       },
-       {
-               name:   "MOVVgpfp",
-               argLen: 1,
-               asm:    mips.AMOVV,
-               reg: regInfo{
-                       inputs: []inputInfo{
-                               {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
+                               {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
                        },
                        outputs: []outputInfo{
-                               {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
                        },
                },
        },
@@ -42123,10 +44192,10 @@ var opcodeTable = [...]opInfo{
                asm:    mips.AMOVB,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
+                               {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
                        },
                        outputs: []outputInfo{
-                               {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
+                               {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
                        },
                },
        },
@@ -42136,10 +44205,10 @@ var opcodeTable = [...]opInfo{
                asm:    mips.AMOVBU,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
+                               {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
                        },
                        outputs: []outputInfo{
-                               {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
+                               {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
                        },
                },
        },
@@ -42149,10 +44218,10 @@ var opcodeTable = [...]opInfo{
                asm:    mips.AMOVH,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
+                               {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
                        },
                        outputs: []outputInfo{
-                               {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
+                               {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
                        },
                },
        },
@@ -42162,10 +44231,10 @@ var opcodeTable = [...]opInfo{
                asm:    mips.AMOVHU,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
+                               {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
                        },
                        outputs: []outputInfo{
-                               {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
+                               {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
                        },
                },
        },
@@ -42175,49 +44244,54 @@ var opcodeTable = [...]opInfo{
                asm:    mips.AMOVW,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
+                               {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
                        },
                        outputs: []outputInfo{
-                               {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
+                               {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
                        },
                },
        },
        {
-               name:   "MOVWUreg",
-               argLen: 1,
-               asm:    mips.AMOVWU,
+               name:         "MOVWnop",
+               argLen:       1,
+               resultInArg0: true,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
+                               {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
                        },
                        outputs: []outputInfo{
-                               {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
+                               {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
                        },
                },
        },
        {
-               name:   "MOVVreg",
-               argLen: 1,
-               asm:    mips.AMOVV,
+               name:         "CMOVZ",
+               argLen:       3,
+               resultInArg0: true,
+               asm:          mips.ACMOVZ,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
+                               {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
+                               {1, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
+                               {2, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
                        },
                        outputs: []outputInfo{
-                               {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
+                               {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
                        },
                },
        },
        {
-               name:         "MOVVnop",
-               argLen:       1,
+               name:         "CMOVZzero",
+               argLen:       2,
                resultInArg0: true,
+               asm:          mips.ACMOVZ,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
+                               {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
+                               {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
                        },
                        outputs: []outputInfo{
-                               {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
+                               {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
                        },
                },
        },
@@ -42227,10 +44301,10 @@ var opcodeTable = [...]opInfo{
                asm:    mips.AMOVWF,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
                        },
                        outputs: []outputInfo{
-                               {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
                        },
                },
        },
@@ -42240,101 +44314,49 @@ var opcodeTable = [...]opInfo{
                asm:    mips.AMOVWD,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
                        },
                        outputs: []outputInfo{
-                               {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
                        },
                },
        },
        {
-               name:   "MOVVF",
+               name:   "TRUNCFW",
                argLen: 1,
-               asm:    mips.AMOVVF,
+               asm:    mips.ATRUNCFW,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
                        },
                        outputs: []outputInfo{
-                               {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
                        },
                },
        },
        {
-               name:   "MOVVD",
+               name:   "TRUNCDW",
                argLen: 1,
-               asm:    mips.AMOVVD,
+               asm:    mips.ATRUNCDW,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
                        },
                        outputs: []outputInfo{
-                               {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
                        },
                },
        },
        {
-               name:   "TRUNCFW",
+               name:   "MOVFD",
                argLen: 1,
-               asm:    mips.ATRUNCFW,
+               asm:    mips.AMOVFD,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
                        },
                        outputs: []outputInfo{
-                               {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
-                       },
-               },
-       },
-       {
-               name:   "TRUNCDW",
-               argLen: 1,
-               asm:    mips.ATRUNCDW,
-               reg: regInfo{
-                       inputs: []inputInfo{
-                               {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
-                       },
-                       outputs: []outputInfo{
-                               {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
-                       },
-               },
-       },
-       {
-               name:   "TRUNCFV",
-               argLen: 1,
-               asm:    mips.ATRUNCFV,
-               reg: regInfo{
-                       inputs: []inputInfo{
-                               {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
-                       },
-                       outputs: []outputInfo{
-                               {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
-                       },
-               },
-       },
-       {
-               name:   "TRUNCDV",
-               argLen: 1,
-               asm:    mips.ATRUNCDV,
-               reg: regInfo{
-                       inputs: []inputInfo{
-                               {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
-                       },
-                       outputs: []outputInfo{
-                               {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
-                       },
-               },
-       },
-       {
-               name:   "MOVFD",
-               argLen: 1,
-               asm:    mips.AMOVFD,
-               reg: regInfo{
-                       inputs: []inputInfo{
-                               {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
-                       },
-                       outputs: []outputInfo{
-                               {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
                        },
                },
        },
@@ -42344,10 +44366,10 @@ var opcodeTable = [...]opInfo{
                asm:    mips.AMOVDF,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
                        },
                        outputs: []outputInfo{
-                               {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
                        },
                },
        },
@@ -42358,7 +44380,7 @@ var opcodeTable = [...]opInfo{
                clobberFlags: true,
                call:         true,
                reg: regInfo{
-                       clobbers: 4611686018393833470, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 HI LO
+                       clobbers: 140737421246462, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 HI LO
                },
        },
        {
@@ -42369,7 +44391,7 @@ var opcodeTable = [...]opInfo{
                call:         true,
                tailCall:     true,
                reg: regInfo{
-                       clobbers: 4611686018393833470, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 HI LO
+                       clobbers: 140737421246462, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 HI LO
                },
        },
        {
@@ -42381,9 +44403,9 @@ var opcodeTable = [...]opInfo{
                reg: regInfo{
                        inputs: []inputInfo{
                                {1, 4194304},   // R22
-                               {0, 201326590}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP R31
+                               {0, 402653182}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP R31
                        },
-                       clobbers: 4611686018393833470, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 HI LO
+                       clobbers: 140737421246462, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 HI LO
                },
        },
        {
@@ -42394,93 +44416,9 @@ var opcodeTable = [...]opInfo{
                call:         true,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
-                       },
-                       clobbers: 4611686018393833470, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 HI LO
-               },
-       },
-       {
-               name:           "DUFFZERO",
-               auxType:        auxInt64,
-               argLen:         2,
-               faultOnNilArg0: true,
-               reg: regInfo{
-                       inputs: []inputInfo{
-                               {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
-                       },
-                       clobbers: 134217730, // R1 R31
-               },
-       },
-       {
-               name:           "DUFFCOPY",
-               auxType:        auxInt64,
-               argLen:         3,
-               faultOnNilArg0: true,
-               faultOnNilArg1: true,
-               reg: regInfo{
-                       inputs: []inputInfo{
-                               {0, 4}, // R2
-                               {1, 2}, // R1
-                       },
-                       clobbers: 134217734, // R1 R2 R31
-               },
-       },
-       {
-               name:           "LoweredZero",
-               auxType:        auxInt64,
-               argLen:         3,
-               clobberFlags:   true,
-               faultOnNilArg0: true,
-               reg: regInfo{
-                       inputs: []inputInfo{
-                               {0, 2},         // R1
-                               {1, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
-                       },
-                       clobbers: 2, // R1
-               },
-       },
-       {
-               name:           "LoweredMove",
-               auxType:        auxInt64,
-               argLen:         4,
-               clobberFlags:   true,
-               faultOnNilArg0: true,
-               faultOnNilArg1: true,
-               reg: regInfo{
-                       inputs: []inputInfo{
-                               {0, 4},         // R2
-                               {1, 2},         // R1
-                               {2, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
-                       },
-                       clobbers: 6, // R1 R2
-               },
-       },
-       {
-               name:           "LoweredAtomicAnd32",
-               argLen:         3,
-               faultOnNilArg0: true,
-               hasSideEffects: true,
-               unsafePoint:    true,
-               asm:            mips.AAND,
-               reg: regInfo{
-                       inputs: []inputInfo{
-                               {1, 234881022},           // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
-                               {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB
-                       },
-               },
-       },
-       {
-               name:           "LoweredAtomicOr32",
-               argLen:         3,
-               faultOnNilArg0: true,
-               hasSideEffects: true,
-               unsafePoint:    true,
-               asm:            mips.AOR,
-               reg: regInfo{
-                       inputs: []inputInfo{
-                               {1, 234881022},           // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
-                               {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB
+                               {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
                        },
+                       clobbers: 140737421246462, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 HI LO
                },
        },
        {
@@ -42489,10 +44427,10 @@ var opcodeTable = [...]opInfo{
                faultOnNilArg0: true,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB
+                               {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB
                        },
                        outputs: []outputInfo{
-                               {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
+                               {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
                        },
                },
        },
@@ -42502,23 +44440,10 @@ var opcodeTable = [...]opInfo{
                faultOnNilArg0: true,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB
-                       },
-                       outputs: []outputInfo{
-                               {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
-                       },
-               },
-       },
-       {
-               name:           "LoweredAtomicLoad64",
-               argLen:         2,
-               faultOnNilArg0: true,
-               reg: regInfo{
-                       inputs: []inputInfo{
-                               {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB
+                               {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB
                        },
                        outputs: []outputInfo{
-                               {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
+                               {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
                        },
                },
        },
@@ -42529,8 +44454,8 @@ var opcodeTable = [...]opInfo{
                hasSideEffects: true,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {1, 234881022},           // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
-                               {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB
+                               {1, 469762046},       // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
+                               {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB
                        },
                },
        },
@@ -42541,47 +44466,24 @@ var opcodeTable = [...]opInfo{
                hasSideEffects: true,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {1, 234881022},           // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
-                               {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB
-                       },
-               },
-       },
-       {
-               name:           "LoweredAtomicStore64",
-               argLen:         3,
-               faultOnNilArg0: true,
-               hasSideEffects: true,
-               reg: regInfo{
-                       inputs: []inputInfo{
-                               {1, 234881022},           // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
-                               {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB
-                       },
-               },
-       },
-       {
-               name:           "LoweredAtomicStorezero32",
-               argLen:         2,
-               faultOnNilArg0: true,
-               hasSideEffects: true,
-               reg: regInfo{
-                       inputs: []inputInfo{
-                               {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB
+                               {1, 469762046},       // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
+                               {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB
                        },
                },
        },
        {
-               name:           "LoweredAtomicStorezero64",
+               name:           "LoweredAtomicStorezero",
                argLen:         2,
                faultOnNilArg0: true,
                hasSideEffects: true,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB
+                               {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB
                        },
                },
        },
        {
-               name:            "LoweredAtomicExchange32",
+               name:            "LoweredAtomicExchange",
                argLen:          3,
                resultNotInArgs: true,
                faultOnNilArg0:  true,
@@ -42589,16 +44491,16 @@ var opcodeTable = [...]opInfo{
                unsafePoint:     true,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {1, 234881022},           // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
-                               {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB
+                               {1, 469762046},       // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
+                               {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB
                        },
                        outputs: []outputInfo{
-                               {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
+                               {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
                        },
                },
        },
        {
-               name:            "LoweredAtomicExchange64",
+               name:            "LoweredAtomicAdd",
                argLen:          3,
                resultNotInArgs: true,
                faultOnNilArg0:  true,
@@ -42606,116 +44508,103 @@ var opcodeTable = [...]opInfo{
                unsafePoint:     true,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {1, 234881022},           // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
-                               {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB
+                               {1, 469762046},       // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
+                               {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB
                        },
                        outputs: []outputInfo{
-                               {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
+                               {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
                        },
                },
        },
        {
-               name:            "LoweredAtomicAdd32",
-               argLen:          3,
+               name:            "LoweredAtomicAddconst",
+               auxType:         auxInt32,
+               argLen:          2,
                resultNotInArgs: true,
                faultOnNilArg0:  true,
                hasSideEffects:  true,
                unsafePoint:     true,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {1, 234881022},           // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
-                               {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB
+                               {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB
                        },
                        outputs: []outputInfo{
-                               {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
+                               {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
                        },
                },
        },
        {
-               name:            "LoweredAtomicAdd64",
-               argLen:          3,
+               name:            "LoweredAtomicCas",
+               argLen:          4,
                resultNotInArgs: true,
                faultOnNilArg0:  true,
                hasSideEffects:  true,
                unsafePoint:     true,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {1, 234881022},           // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
-                               {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB
+                               {1, 469762046},       // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
+                               {2, 469762046},       // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
+                               {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB
                        },
                        outputs: []outputInfo{
-                               {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
+                               {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
                        },
                },
        },
        {
-               name:            "LoweredAtomicAddconst32",
-               auxType:         auxInt32,
-               argLen:          2,
-               resultNotInArgs: true,
-               faultOnNilArg0:  true,
-               hasSideEffects:  true,
-               unsafePoint:     true,
+               name:           "LoweredAtomicAnd",
+               argLen:         3,
+               faultOnNilArg0: true,
+               hasSideEffects: true,
+               unsafePoint:    true,
+               asm:            mips.AAND,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB
-                       },
-                       outputs: []outputInfo{
-                               {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
+                               {1, 469762046},       // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
+                               {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB
                        },
                },
        },
        {
-               name:            "LoweredAtomicAddconst64",
-               auxType:         auxInt64,
-               argLen:          2,
-               resultNotInArgs: true,
-               faultOnNilArg0:  true,
-               hasSideEffects:  true,
-               unsafePoint:     true,
+               name:           "LoweredAtomicOr",
+               argLen:         3,
+               faultOnNilArg0: true,
+               hasSideEffects: true,
+               unsafePoint:    true,
+               asm:            mips.AOR,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB
-                       },
-                       outputs: []outputInfo{
-                               {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
+                               {1, 469762046},       // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
+                               {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB
                        },
                },
        },
        {
-               name:            "LoweredAtomicCas32",
-               argLen:          4,
-               resultNotInArgs: true,
-               faultOnNilArg0:  true,
-               hasSideEffects:  true,
-               unsafePoint:     true,
+               name:           "LoweredZero",
+               auxType:        auxInt32,
+               argLen:         3,
+               faultOnNilArg0: true,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {1, 234881022},           // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
-                               {2, 234881022},           // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
-                               {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB
-                       },
-                       outputs: []outputInfo{
-                               {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
+                               {0, 2},         // R1
+                               {1, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
                        },
+                       clobbers: 2, // R1
                },
        },
        {
-               name:            "LoweredAtomicCas64",
-               argLen:          4,
-               resultNotInArgs: true,
-               faultOnNilArg0:  true,
-               hasSideEffects:  true,
-               unsafePoint:     true,
+               name:           "LoweredMove",
+               auxType:        auxInt32,
+               argLen:         4,
+               faultOnNilArg0: true,
+               faultOnNilArg1: true,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {1, 234881022},           // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
-                               {2, 234881022},           // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
-                               {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB
-                       },
-                       outputs: []outputInfo{
-                               {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
+                               {0, 4},         // R2
+                               {1, 2},         // R1
+                               {2, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
                        },
+                       clobbers: 6, // R1 R2
                },
        },
        {
@@ -42725,7 +44614,7 @@ var opcodeTable = [...]opInfo{
                faultOnNilArg0: true,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
+                               {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
                        },
                },
        },
@@ -42734,7 +44623,7 @@ var opcodeTable = [...]opInfo{
                argLen: 1,
                reg: regInfo{
                        outputs: []outputInfo{
-                               {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
+                               {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
                        },
                },
        },
@@ -42743,7 +44632,7 @@ var opcodeTable = [...]opInfo{
                argLen: 1,
                reg: regInfo{
                        outputs: []outputInfo{
-                               {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
+                               {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
                        },
                },
        },
@@ -42763,7 +44652,7 @@ var opcodeTable = [...]opInfo{
                rematerializeable: true,
                reg: regInfo{
                        outputs: []outputInfo{
-                               {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
+                               {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
                        },
                },
        },
@@ -42773,7 +44662,7 @@ var opcodeTable = [...]opInfo{
                rematerializeable: true,
                reg: regInfo{
                        outputs: []outputInfo{
-                               {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
+                               {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
                        },
                },
        },
@@ -42783,7 +44672,7 @@ var opcodeTable = [...]opInfo{
                argLen:       1,
                clobberFlags: true,
                reg: regInfo{
-                       clobbers: 4611686018293170176, // R31 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 HI LO
+                       clobbers: 140737219919872, // R31 F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 HI LO
                        outputs: []outputInfo{
                                {0, 16777216}, // R25
                        },
@@ -42832,1743 +44721,1789 @@ var opcodeTable = [...]opInfo{
                        },
                },
        },
-
        {
-               name:        "ADD",
-               argLen:      2,
-               commutative: true,
-               asm:         ppc64.AADD,
+               name:    "LoweredPanicExtendA",
+               auxType: auxInt64,
+               argLen:  4,
+               call:    true,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
-                               {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+                               {0, 32}, // R5
+                               {1, 8},  // R3
+                               {2, 16}, // R4
                        },
-                       outputs: []outputInfo{
-                               {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+               },
+       },
+       {
+               name:    "LoweredPanicExtendB",
+               auxType: auxInt64,
+               argLen:  4,
+               call:    true,
+               reg: regInfo{
+                       inputs: []inputInfo{
+                               {0, 32}, // R5
+                               {1, 4},  // R2
+                               {2, 8},  // R3
                        },
                },
        },
        {
-               name:        "ADDCC",
+               name:    "LoweredPanicExtendC",
+               auxType: auxInt64,
+               argLen:  4,
+               call:    true,
+               reg: regInfo{
+                       inputs: []inputInfo{
+                               {0, 32}, // R5
+                               {1, 2},  // R1
+                               {2, 4},  // R2
+                       },
+               },
+       },
+
+       {
+               name:        "ADDV",
                argLen:      2,
                commutative: true,
-               asm:         ppc64.AADDCC,
+               asm:         mips.AADDVU,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
-                               {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+                               {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
+                               {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
                        },
                        outputs: []outputInfo{
-                               {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+                               {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
                        },
                },
        },
        {
-               name:    "ADDconst",
+               name:    "ADDVconst",
                auxType: auxInt64,
                argLen:  1,
-               asm:     ppc64.AADD,
+               asm:     mips.AADDVU,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+                               {0, 268435454}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31
                        },
                        outputs: []outputInfo{
-                               {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+                               {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
                        },
                },
        },
        {
-               name:    "ADDCCconst",
+               name:   "SUBV",
+               argLen: 2,
+               asm:    mips.ASUBVU,
+               reg: regInfo{
+                       inputs: []inputInfo{
+                               {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
+                               {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
+                       },
+                       outputs: []outputInfo{
+                               {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
+                       },
+               },
+       },
+       {
+               name:    "SUBVconst",
                auxType: auxInt64,
                argLen:  1,
-               asm:     ppc64.AADDCCC,
+               asm:     mips.ASUBVU,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+                               {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
                        },
-                       clobbers: 9223372036854775808, // XER
                        outputs: []outputInfo{
-                               {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+                               {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
                        },
                },
        },
        {
-               name:        "FADD",
+               name:        "MULV",
                argLen:      2,
                commutative: true,
-               asm:         ppc64.AFADD,
+               asm:         mips.AMULV,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
-                               {1, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
+                               {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
+                               {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
                        },
                        outputs: []outputInfo{
-                               {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
+                               {0, 1152921504606846976}, // HI
+                               {1, 2305843009213693952}, // LO
                        },
                },
        },
        {
-               name:        "FADDS",
+               name:        "MULVU",
                argLen:      2,
                commutative: true,
-               asm:         ppc64.AFADDS,
+               asm:         mips.AMULVU,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
-                               {1, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
+                               {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
+                               {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
                        },
                        outputs: []outputInfo{
-                               {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
+                               {0, 1152921504606846976}, // HI
+                               {1, 2305843009213693952}, // LO
                        },
                },
        },
        {
-               name:   "SUB",
+               name:   "DIVV",
                argLen: 2,
-               asm:    ppc64.ASUB,
+               asm:    mips.ADIVV,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
-                               {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+                               {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
+                               {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
                        },
                        outputs: []outputInfo{
-                               {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+                               {0, 1152921504606846976}, // HI
+                               {1, 2305843009213693952}, // LO
                        },
                },
        },
        {
-               name:   "SUBCC",
+               name:   "DIVVU",
                argLen: 2,
-               asm:    ppc64.ASUBCC,
+               asm:    mips.ADIVVU,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
-                               {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+                               {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
+                               {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
                        },
                        outputs: []outputInfo{
-                               {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+                               {0, 1152921504606846976}, // HI
+                               {1, 2305843009213693952}, // LO
                        },
                },
        },
        {
-               name:    "SUBFCconst",
-               auxType: auxInt64,
-               argLen:  1,
-               asm:     ppc64.ASUBC,
+               name:        "ADDF",
+               argLen:      2,
+               commutative: true,
+               asm:         mips.AADDF,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+                               {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
                        },
-                       clobbers: 9223372036854775808, // XER
                        outputs: []outputInfo{
-                               {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+                               {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
                        },
                },
        },
        {
-               name:   "FSUB",
-               argLen: 2,
-               asm:    ppc64.AFSUB,
+               name:        "ADDD",
+               argLen:      2,
+               commutative: true,
+               asm:         mips.AADDD,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
-                               {1, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
+                               {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
                        },
                        outputs: []outputInfo{
-                               {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
+                               {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
                        },
                },
        },
        {
-               name:   "FSUBS",
+               name:   "SUBF",
                argLen: 2,
-               asm:    ppc64.AFSUBS,
+               asm:    mips.ASUBF,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
-                               {1, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
+                               {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
                        },
                        outputs: []outputInfo{
-                               {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
+                               {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
                        },
                },
        },
        {
-               name:   "XSMINJDP",
+               name:   "SUBD",
                argLen: 2,
-               asm:    ppc64.AXSMINJDP,
+               asm:    mips.ASUBD,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
-                               {1, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
+                               {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
                        },
                        outputs: []outputInfo{
-                               {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
+                               {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
                        },
                },
        },
        {
-               name:   "XSMAXJDP",
-               argLen: 2,
-               asm:    ppc64.AXSMAXJDP,
-               reg: regInfo{
+               name:        "MULF",
+               argLen:      2,
+               commutative: true,
+               asm:         mips.AMULF,
+               reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
-                               {1, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
+                               {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
                        },
                        outputs: []outputInfo{
-                               {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
+                               {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
                        },
                },
        },
        {
-               name:        "MULLD",
+               name:        "MULD",
                argLen:      2,
                commutative: true,
-               asm:         ppc64.AMULLD,
+               asm:         mips.AMULD,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
-                               {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+                               {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
                        },
                        outputs: []outputInfo{
-                               {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+                               {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
                        },
                },
        },
        {
-               name:        "MULLW",
-               argLen:      2,
-               commutative: true,
-               asm:         ppc64.AMULLW,
+               name:   "DIVF",
+               argLen: 2,
+               asm:    mips.ADIVF,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
-                               {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+                               {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
                        },
                        outputs: []outputInfo{
-                               {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+                               {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
                        },
                },
        },
        {
-               name:    "MULLDconst",
-               auxType: auxInt32,
-               argLen:  1,
-               asm:     ppc64.AMULLD,
+               name:   "DIVD",
+               argLen: 2,
+               asm:    mips.ADIVD,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+                               {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
                        },
                        outputs: []outputInfo{
-                               {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+                               {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
                        },
                },
        },
        {
-               name:    "MULLWconst",
-               auxType: auxInt32,
-               argLen:  1,
-               asm:     ppc64.AMULLW,
+               name:        "AND",
+               argLen:      2,
+               commutative: true,
+               asm:         mips.AAND,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+                               {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
+                               {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
                        },
                        outputs: []outputInfo{
-                               {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+                               {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
                        },
                },
        },
        {
-               name:   "MADDLD",
-               argLen: 3,
-               asm:    ppc64.AMADDLD,
+               name:    "ANDconst",
+               auxType: auxInt64,
+               argLen:  1,
+               asm:     mips.AAND,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
-                               {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
-                               {2, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+                               {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
                        },
                        outputs: []outputInfo{
-                               {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+                               {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
                        },
                },
        },
        {
-               name:        "MULHD",
+               name:        "OR",
                argLen:      2,
                commutative: true,
-               asm:         ppc64.AMULHD,
+               asm:         mips.AOR,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
-                               {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+                               {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
+                               {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
                        },
                        outputs: []outputInfo{
-                               {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+                               {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
                        },
                },
        },
        {
-               name:        "MULHW",
-               argLen:      2,
-               commutative: true,
-               asm:         ppc64.AMULHW,
+               name:    "ORconst",
+               auxType: auxInt64,
+               argLen:  1,
+               asm:     mips.AOR,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
-                               {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+                               {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
                        },
                        outputs: []outputInfo{
-                               {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+                               {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
                        },
                },
        },
        {
-               name:        "MULHDU",
+               name:        "XOR",
                argLen:      2,
                commutative: true,
-               asm:         ppc64.AMULHDU,
+               asm:         mips.AXOR,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
-                               {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+                               {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
+                               {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
                        },
                        outputs: []outputInfo{
-                               {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+                               {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
                        },
                },
        },
        {
-               name:        "MULHDUCC",
-               argLen:      2,
-               commutative: true,
-               asm:         ppc64.AMULHDUCC,
+               name:    "XORconst",
+               auxType: auxInt64,
+               argLen:  1,
+               asm:     mips.AXOR,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
-                               {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+                               {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
                        },
                        outputs: []outputInfo{
-                               {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+                               {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
                        },
                },
        },
        {
-               name:        "MULHWU",
+               name:        "NOR",
                argLen:      2,
                commutative: true,
-               asm:         ppc64.AMULHWU,
+               asm:         mips.ANOR,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
-                               {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+                               {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
+                               {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
                        },
                        outputs: []outputInfo{
-                               {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+                               {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
                        },
                },
        },
        {
-               name:        "FMUL",
-               argLen:      2,
-               commutative: true,
-               asm:         ppc64.AFMUL,
+               name:    "NORconst",
+               auxType: auxInt64,
+               argLen:  1,
+               asm:     mips.ANOR,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
-                               {1, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
+                               {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
                        },
                        outputs: []outputInfo{
-                               {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
+                               {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
                        },
                },
        },
        {
-               name:        "FMULS",
-               argLen:      2,
-               commutative: true,
-               asm:         ppc64.AFMULS,
+               name:   "NEGV",
+               argLen: 1,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
-                               {1, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
+                               {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
                        },
                        outputs: []outputInfo{
-                               {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
+                               {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
                        },
                },
        },
        {
-               name:   "FMADD",
-               argLen: 3,
-               asm:    ppc64.AFMADD,
+               name:   "NEGF",
+               argLen: 1,
+               asm:    mips.ANEGF,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
-                               {1, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
-                               {2, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
+                               {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
                        },
                        outputs: []outputInfo{
-                               {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
+                               {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
                        },
                },
        },
        {
-               name:   "FMADDS",
-               argLen: 3,
-               asm:    ppc64.AFMADDS,
+               name:   "NEGD",
+               argLen: 1,
+               asm:    mips.ANEGD,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
-                               {1, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
-                               {2, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
+                               {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
                        },
                        outputs: []outputInfo{
-                               {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
+                               {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
                        },
                },
        },
        {
-               name:   "FMSUB",
-               argLen: 3,
-               asm:    ppc64.AFMSUB,
+               name:   "ABSD",
+               argLen: 1,
+               asm:    mips.AABSD,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
-                               {1, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
-                               {2, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
+                               {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
                        },
                        outputs: []outputInfo{
-                               {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
+                               {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
                        },
                },
        },
        {
-               name:   "FMSUBS",
-               argLen: 3,
-               asm:    ppc64.AFMSUBS,
+               name:   "SQRTD",
+               argLen: 1,
+               asm:    mips.ASQRTD,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
-                               {1, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
-                               {2, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
+                               {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
                        },
                        outputs: []outputInfo{
-                               {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
+                               {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
                        },
                },
        },
        {
-               name:   "SRAD",
-               argLen: 2,
-               asm:    ppc64.ASRAD,
+               name:   "SQRTF",
+               argLen: 1,
+               asm:    mips.ASQRTF,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
-                               {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+                               {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
                        },
-                       clobbers: 9223372036854775808, // XER
                        outputs: []outputInfo{
-                               {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+                               {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
                        },
                },
        },
        {
-               name:   "SRAW",
+               name:   "SLLV",
                argLen: 2,
-               asm:    ppc64.ASRAW,
+               asm:    mips.ASLLV,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
-                               {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+                               {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
+                               {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
                        },
-                       clobbers: 9223372036854775808, // XER
                        outputs: []outputInfo{
-                               {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+                               {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
                        },
                },
        },
        {
-               name:   "SRD",
-               argLen: 2,
-               asm:    ppc64.ASRD,
+               name:    "SLLVconst",
+               auxType: auxInt64,
+               argLen:  1,
+               asm:     mips.ASLLV,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
-                               {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+                               {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
                        },
                        outputs: []outputInfo{
-                               {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+                               {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
                        },
                },
        },
        {
-               name:   "SRW",
+               name:   "SRLV",
                argLen: 2,
-               asm:    ppc64.ASRW,
+               asm:    mips.ASRLV,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
-                               {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+                               {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
+                               {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
                        },
                        outputs: []outputInfo{
-                               {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+                               {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
                        },
                },
        },
        {
-               name:   "SLD",
-               argLen: 2,
-               asm:    ppc64.ASLD,
+               name:    "SRLVconst",
+               auxType: auxInt64,
+               argLen:  1,
+               asm:     mips.ASRLV,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
-                               {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+                               {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
                        },
                        outputs: []outputInfo{
-                               {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+                               {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
                        },
                },
        },
        {
-               name:   "SLW",
+               name:   "SRAV",
                argLen: 2,
-               asm:    ppc64.ASLW,
+               asm:    mips.ASRAV,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
-                               {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+                               {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
+                               {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
                        },
                        outputs: []outputInfo{
-                               {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+                               {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
                        },
                },
        },
        {
-               name:   "ROTL",
-               argLen: 2,
-               asm:    ppc64.AROTL,
+               name:    "SRAVconst",
+               auxType: auxInt64,
+               argLen:  1,
+               asm:     mips.ASRAV,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
-                               {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+                               {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
                        },
                        outputs: []outputInfo{
-                               {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+                               {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
                        },
                },
        },
        {
-               name:   "ROTLW",
+               name:   "SGT",
                argLen: 2,
-               asm:    ppc64.AROTLW,
+               asm:    mips.ASGT,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
-                               {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+                               {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
+                               {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
                        },
                        outputs: []outputInfo{
-                               {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+                               {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
                        },
                },
        },
        {
-               name:    "CLRLSLWI",
-               auxType: auxInt32,
+               name:    "SGTconst",
+               auxType: auxInt64,
                argLen:  1,
-               asm:     ppc64.ACLRLSLWI,
+               asm:     mips.ASGT,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+                               {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
                        },
                        outputs: []outputInfo{
-                               {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+                               {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
                        },
                },
        },
        {
-               name:    "CLRLSLDI",
-               auxType: auxInt32,
-               argLen:  1,
-               asm:     ppc64.ACLRLSLDI,
+               name:   "SGTU",
+               argLen: 2,
+               asm:    mips.ASGTU,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+                               {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
+                               {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
                        },
                        outputs: []outputInfo{
-                               {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+                               {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
                        },
                },
        },
        {
-               name:        "ADDC",
-               argLen:      2,
-               commutative: true,
-               asm:         ppc64.AADDC,
+               name:    "SGTUconst",
+               auxType: auxInt64,
+               argLen:  1,
+               asm:     mips.ASGTU,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
-                               {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+                               {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
                        },
-                       clobbers: 9223372036854775808, // XER
                        outputs: []outputInfo{
-                               {1, 9223372036854775808}, // XER
-                               {0, 1073733624},          // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+                               {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
                        },
                },
        },
        {
-               name:   "SUBC",
+               name:   "CMPEQF",
                argLen: 2,
-               asm:    ppc64.ASUBC,
+               asm:    mips.ACMPEQF,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
-                               {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
-                       },
-                       clobbers: 9223372036854775808, // XER
-                       outputs: []outputInfo{
-                               {1, 9223372036854775808}, // XER
-                               {0, 1073733624},          // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+                               {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
                        },
                },
        },
        {
-               name:    "ADDCconst",
-               auxType: auxInt64,
-               argLen:  1,
-               asm:     ppc64.AADDC,
+               name:   "CMPEQD",
+               argLen: 2,
+               asm:    mips.ACMPEQD,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
-                       },
-                       outputs: []outputInfo{
-                               {1, 9223372036854775808}, // XER
-                               {0, 1073733624},          // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+                               {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
                        },
                },
        },
        {
-               name:    "SUBCconst",
-               auxType: auxInt64,
-               argLen:  1,
-               asm:     ppc64.ASUBC,
+               name:   "CMPGEF",
+               argLen: 2,
+               asm:    mips.ACMPGEF,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
-                       },
-                       outputs: []outputInfo{
-                               {1, 9223372036854775808}, // XER
-                               {0, 1073733624},          // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+                               {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
                        },
                },
        },
        {
-               name:        "ADDE",
-               argLen:      3,
-               commutative: true,
-               asm:         ppc64.AADDE,
+               name:   "CMPGED",
+               argLen: 2,
+               asm:    mips.ACMPGED,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {2, 9223372036854775808}, // XER
-                               {0, 1073733630},          // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
-                               {1, 1073733630},          // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
-                       },
-                       clobbers: 9223372036854775808, // XER
-                       outputs: []outputInfo{
-                               {1, 9223372036854775808}, // XER
-                               {0, 1073733624},          // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+                               {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
                        },
                },
        },
        {
-               name:   "ADDZE",
+               name:   "CMPGTF",
                argLen: 2,
-               asm:    ppc64.AADDZE,
+               asm:    mips.ACMPGTF,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {1, 9223372036854775808}, // XER
-                               {0, 1073733630},          // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
-                       },
-                       clobbers: 9223372036854775808, // XER
-                       outputs: []outputInfo{
-                               {1, 9223372036854775808}, // XER
-                               {0, 1073733624},          // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+                               {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
                        },
                },
        },
        {
-               name:   "SUBE",
-               argLen: 3,
-               asm:    ppc64.ASUBE,
+               name:   "CMPGTD",
+               argLen: 2,
+               asm:    mips.ACMPGTD,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {2, 9223372036854775808}, // XER
-                               {0, 1073733630},          // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
-                               {1, 1073733630},          // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
-                       },
-                       clobbers: 9223372036854775808, // XER
-                       outputs: []outputInfo{
-                               {1, 9223372036854775808}, // XER
-                               {0, 1073733624},          // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+                               {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
                        },
                },
        },
        {
-               name:   "ADDZEzero",
-               argLen: 1,
-               asm:    ppc64.AADDZE,
+               name:              "MOVVconst",
+               auxType:           auxInt64,
+               argLen:            0,
+               rematerializeable: true,
+               asm:               mips.AMOVV,
                reg: regInfo{
-                       inputs: []inputInfo{
-                               {0, 9223372036854775808}, // XER
-                       },
-                       clobbers: 9223372036854775808, // XER
                        outputs: []outputInfo{
-                               {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+                               {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
                        },
                },
        },
        {
-               name:   "SUBZEzero",
-               argLen: 1,
-               asm:    ppc64.ASUBZE,
+               name:              "MOVFconst",
+               auxType:           auxFloat64,
+               argLen:            0,
+               rematerializeable: true,
+               asm:               mips.AMOVF,
                reg: regInfo{
-                       inputs: []inputInfo{
-                               {0, 9223372036854775808}, // XER
-                       },
-                       clobbers: 9223372036854775808, // XER
                        outputs: []outputInfo{
-                               {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+                               {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
                        },
                },
        },
        {
-               name:    "SRADconst",
-               auxType: auxInt64,
-               argLen:  1,
-               asm:     ppc64.ASRAD,
+               name:              "MOVDconst",
+               auxType:           auxFloat64,
+               argLen:            0,
+               rematerializeable: true,
+               asm:               mips.AMOVD,
                reg: regInfo{
-                       inputs: []inputInfo{
-                               {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
-                       },
-                       clobbers: 9223372036854775808, // XER
                        outputs: []outputInfo{
-                               {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+                               {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
                        },
                },
        },
        {
-               name:    "SRAWconst",
-               auxType: auxInt64,
-               argLen:  1,
-               asm:     ppc64.ASRAW,
+               name:              "MOVVaddr",
+               auxType:           auxSymOff,
+               argLen:            1,
+               rematerializeable: true,
+               symEffect:         SymAddr,
+               asm:               mips.AMOVV,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+                               {0, 4611686018460942336}, // SP SB
                        },
-                       clobbers: 9223372036854775808, // XER
                        outputs: []outputInfo{
-                               {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+                               {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
                        },
                },
        },
        {
-               name:    "SRDconst",
-               auxType: auxInt64,
-               argLen:  1,
-               asm:     ppc64.ASRD,
+               name:           "MOVBload",
+               auxType:        auxSymOff,
+               argLen:         2,
+               faultOnNilArg0: true,
+               symEffect:      SymRead,
+               asm:            mips.AMOVB,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+                               {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB
                        },
                        outputs: []outputInfo{
-                               {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+                               {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
                        },
                },
        },
        {
-               name:    "SRWconst",
-               auxType: auxInt64,
-               argLen:  1,
-               asm:     ppc64.ASRW,
+               name:           "MOVBUload",
+               auxType:        auxSymOff,
+               argLen:         2,
+               faultOnNilArg0: true,
+               symEffect:      SymRead,
+               asm:            mips.AMOVBU,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+                               {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB
                        },
                        outputs: []outputInfo{
-                               {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+                               {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
                        },
                },
        },
        {
-               name:    "SLDconst",
-               auxType: auxInt64,
-               argLen:  1,
-               asm:     ppc64.ASLD,
+               name:           "MOVHload",
+               auxType:        auxSymOff,
+               argLen:         2,
+               faultOnNilArg0: true,
+               symEffect:      SymRead,
+               asm:            mips.AMOVH,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+                               {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB
                        },
                        outputs: []outputInfo{
-                               {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+                               {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
                        },
                },
        },
        {
-               name:    "SLWconst",
-               auxType: auxInt64,
-               argLen:  1,
-               asm:     ppc64.ASLW,
+               name:           "MOVHUload",
+               auxType:        auxSymOff,
+               argLen:         2,
+               faultOnNilArg0: true,
+               symEffect:      SymRead,
+               asm:            mips.AMOVHU,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+                               {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB
                        },
                        outputs: []outputInfo{
-                               {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+                               {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
                        },
                },
        },
        {
-               name:    "ROTLconst",
-               auxType: auxInt64,
-               argLen:  1,
-               asm:     ppc64.AROTL,
+               name:           "MOVWload",
+               auxType:        auxSymOff,
+               argLen:         2,
+               faultOnNilArg0: true,
+               symEffect:      SymRead,
+               asm:            mips.AMOVW,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+                               {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB
                        },
                        outputs: []outputInfo{
-                               {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+                               {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
                        },
                },
        },
        {
-               name:    "ROTLWconst",
-               auxType: auxInt64,
-               argLen:  1,
-               asm:     ppc64.AROTLW,
+               name:           "MOVWUload",
+               auxType:        auxSymOff,
+               argLen:         2,
+               faultOnNilArg0: true,
+               symEffect:      SymRead,
+               asm:            mips.AMOVWU,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+                               {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB
                        },
                        outputs: []outputInfo{
-                               {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+                               {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
                        },
                },
        },
        {
-               name:    "EXTSWSLconst",
-               auxType: auxInt64,
-               argLen:  1,
-               asm:     ppc64.AEXTSWSLI,
+               name:           "MOVVload",
+               auxType:        auxSymOff,
+               argLen:         2,
+               faultOnNilArg0: true,
+               symEffect:      SymRead,
+               asm:            mips.AMOVV,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+                               {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB
                        },
                        outputs: []outputInfo{
-                               {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+                               {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
                        },
                },
        },
        {
-               name:    "RLWINM",
-               auxType: auxInt64,
-               argLen:  1,
-               asm:     ppc64.ARLWNM,
+               name:           "MOVFload",
+               auxType:        auxSymOff,
+               argLen:         2,
+               faultOnNilArg0: true,
+               symEffect:      SymRead,
+               asm:            mips.AMOVF,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+                               {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB
                        },
                        outputs: []outputInfo{
-                               {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+                               {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
                        },
                },
        },
        {
-               name:    "RLWNM",
-               auxType: auxInt64,
-               argLen:  2,
-               asm:     ppc64.ARLWNM,
+               name:           "MOVDload",
+               auxType:        auxSymOff,
+               argLen:         2,
+               faultOnNilArg0: true,
+               symEffect:      SymRead,
+               asm:            mips.AMOVD,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
-                               {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+                               {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB
                        },
                        outputs: []outputInfo{
-                               {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+                               {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
                        },
                },
        },
        {
-               name:         "RLWMI",
-               auxType:      auxInt64,
-               argLen:       2,
-               resultInArg0: true,
-               asm:          ppc64.ARLWMI,
+               name:           "MOVBstore",
+               auxType:        auxSymOff,
+               argLen:         3,
+               faultOnNilArg0: true,
+               symEffect:      SymWrite,
+               asm:            mips.AMOVB,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
-                               {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
-                       },
-                       outputs: []outputInfo{
-                               {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+                               {1, 234881022},           // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
+                               {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB
                        },
                },
        },
        {
-               name:    "RLDICL",
-               auxType: auxInt64,
-               argLen:  1,
-               asm:     ppc64.ARLDICL,
+               name:           "MOVHstore",
+               auxType:        auxSymOff,
+               argLen:         3,
+               faultOnNilArg0: true,
+               symEffect:      SymWrite,
+               asm:            mips.AMOVH,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
-                       },
-                       outputs: []outputInfo{
-                               {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+                               {1, 234881022},           // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
+                               {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB
                        },
                },
        },
        {
-               name:    "RLDICLCC",
-               auxType: auxInt64,
-               argLen:  1,
-               asm:     ppc64.ARLDICLCC,
+               name:           "MOVWstore",
+               auxType:        auxSymOff,
+               argLen:         3,
+               faultOnNilArg0: true,
+               symEffect:      SymWrite,
+               asm:            mips.AMOVW,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
-                       },
-                       outputs: []outputInfo{
-                               {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+                               {1, 234881022},           // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
+                               {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB
                        },
                },
        },
        {
-               name:    "RLDICR",
-               auxType: auxInt64,
-               argLen:  1,
-               asm:     ppc64.ARLDICR,
+               name:           "MOVVstore",
+               auxType:        auxSymOff,
+               argLen:         3,
+               faultOnNilArg0: true,
+               symEffect:      SymWrite,
+               asm:            mips.AMOVV,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
-                       },
-                       outputs: []outputInfo{
-                               {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+                               {1, 234881022},           // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
+                               {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB
                        },
                },
        },
        {
-               name:   "CNTLZD",
-               argLen: 1,
-               asm:    ppc64.ACNTLZD,
+               name:           "MOVFstore",
+               auxType:        auxSymOff,
+               argLen:         3,
+               faultOnNilArg0: true,
+               symEffect:      SymWrite,
+               asm:            mips.AMOVF,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
-                       },
-                       outputs: []outputInfo{
-                               {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+                               {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB
+                               {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
                        },
                },
        },
        {
-               name:   "CNTLZDCC",
-               argLen: 1,
-               asm:    ppc64.ACNTLZDCC,
+               name:           "MOVDstore",
+               auxType:        auxSymOff,
+               argLen:         3,
+               faultOnNilArg0: true,
+               symEffect:      SymWrite,
+               asm:            mips.AMOVD,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
-                       },
-                       outputs: []outputInfo{
-                               {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+                               {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB
+                               {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
                        },
                },
        },
        {
-               name:   "CNTLZW",
-               argLen: 1,
-               asm:    ppc64.ACNTLZW,
+               name:           "MOVBstorezero",
+               auxType:        auxSymOff,
+               argLen:         2,
+               faultOnNilArg0: true,
+               symEffect:      SymWrite,
+               asm:            mips.AMOVB,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
-                       },
-                       outputs: []outputInfo{
-                               {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+                               {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB
                        },
                },
        },
        {
-               name:   "CNTTZD",
-               argLen: 1,
-               asm:    ppc64.ACNTTZD,
+               name:           "MOVHstorezero",
+               auxType:        auxSymOff,
+               argLen:         2,
+               faultOnNilArg0: true,
+               symEffect:      SymWrite,
+               asm:            mips.AMOVH,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
-                       },
-                       outputs: []outputInfo{
-                               {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+                               {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB
                        },
                },
        },
        {
-               name:   "CNTTZW",
-               argLen: 1,
-               asm:    ppc64.ACNTTZW,
+               name:           "MOVWstorezero",
+               auxType:        auxSymOff,
+               argLen:         2,
+               faultOnNilArg0: true,
+               symEffect:      SymWrite,
+               asm:            mips.AMOVW,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
-                       },
-                       outputs: []outputInfo{
-                               {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+                               {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB
                        },
                },
        },
        {
-               name:   "POPCNTD",
-               argLen: 1,
-               asm:    ppc64.APOPCNTD,
+               name:           "MOVVstorezero",
+               auxType:        auxSymOff,
+               argLen:         2,
+               faultOnNilArg0: true,
+               symEffect:      SymWrite,
+               asm:            mips.AMOVV,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
-                       },
-                       outputs: []outputInfo{
-                               {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+                               {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB
                        },
                },
        },
        {
-               name:   "POPCNTW",
+               name:   "MOVWfpgp",
                argLen: 1,
-               asm:    ppc64.APOPCNTW,
+               asm:    mips.AMOVW,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+                               {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
                        },
                        outputs: []outputInfo{
-                               {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+                               {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
                        },
                },
        },
        {
-               name:   "POPCNTB",
+               name:   "MOVWgpfp",
                argLen: 1,
-               asm:    ppc64.APOPCNTB,
+               asm:    mips.AMOVW,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+                               {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
                        },
                        outputs: []outputInfo{
-                               {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+                               {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
                        },
                },
        },
        {
-               name:   "FDIV",
-               argLen: 2,
-               asm:    ppc64.AFDIV,
+               name:   "MOVVfpgp",
+               argLen: 1,
+               asm:    mips.AMOVV,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
-                               {1, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
+                               {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
                        },
                        outputs: []outputInfo{
-                               {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
+                               {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
                        },
                },
        },
        {
-               name:   "FDIVS",
-               argLen: 2,
-               asm:    ppc64.AFDIVS,
+               name:   "MOVVgpfp",
+               argLen: 1,
+               asm:    mips.AMOVV,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
-                               {1, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
+                               {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
                        },
                        outputs: []outputInfo{
-                               {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
+                               {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
                        },
                },
        },
        {
-               name:   "DIVD",
-               argLen: 2,
-               asm:    ppc64.ADIVD,
+               name:   "MOVBreg",
+               argLen: 1,
+               asm:    mips.AMOVB,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
-                               {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+                               {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
                        },
                        outputs: []outputInfo{
-                               {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+                               {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
                        },
                },
        },
        {
-               name:   "DIVW",
-               argLen: 2,
-               asm:    ppc64.ADIVW,
+               name:   "MOVBUreg",
+               argLen: 1,
+               asm:    mips.AMOVBU,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
-                               {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+                               {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
                        },
                        outputs: []outputInfo{
-                               {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+                               {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
                        },
                },
        },
        {
-               name:   "DIVDU",
-               argLen: 2,
-               asm:    ppc64.ADIVDU,
+               name:   "MOVHreg",
+               argLen: 1,
+               asm:    mips.AMOVH,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
-                               {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+                               {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
                        },
                        outputs: []outputInfo{
-                               {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+                               {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
                        },
                },
        },
        {
-               name:   "DIVWU",
-               argLen: 2,
-               asm:    ppc64.ADIVWU,
+               name:   "MOVHUreg",
+               argLen: 1,
+               asm:    mips.AMOVHU,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
-                               {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+                               {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
                        },
                        outputs: []outputInfo{
-                               {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+                               {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
                        },
                },
        },
        {
-               name:   "MODUD",
-               argLen: 2,
-               asm:    ppc64.AMODUD,
+               name:   "MOVWreg",
+               argLen: 1,
+               asm:    mips.AMOVW,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
-                               {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+                               {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
                        },
                        outputs: []outputInfo{
-                               {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+                               {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
                        },
                },
        },
        {
-               name:   "MODSD",
-               argLen: 2,
-               asm:    ppc64.AMODSD,
+               name:   "MOVWUreg",
+               argLen: 1,
+               asm:    mips.AMOVWU,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
-                               {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+                               {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
                        },
                        outputs: []outputInfo{
-                               {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+                               {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
                        },
                },
        },
        {
-               name:   "MODUW",
-               argLen: 2,
-               asm:    ppc64.AMODUW,
+               name:   "MOVVreg",
+               argLen: 1,
+               asm:    mips.AMOVV,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
-                               {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+                               {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
                        },
                        outputs: []outputInfo{
-                               {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+                               {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
                        },
                },
        },
        {
-               name:   "MODSW",
-               argLen: 2,
-               asm:    ppc64.AMODSW,
+               name:         "MOVVnop",
+               argLen:       1,
+               resultInArg0: true,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
-                               {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+                               {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
                        },
                        outputs: []outputInfo{
-                               {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+                               {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
                        },
                },
        },
        {
-               name:   "FCTIDZ",
+               name:   "MOVWF",
                argLen: 1,
-               asm:    ppc64.AFCTIDZ,
+               asm:    mips.AMOVWF,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
+                               {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
                        },
                        outputs: []outputInfo{
-                               {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
+                               {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
                        },
                },
        },
        {
-               name:   "FCTIWZ",
+               name:   "MOVWD",
                argLen: 1,
-               asm:    ppc64.AFCTIWZ,
+               asm:    mips.AMOVWD,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
+                               {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
                        },
                        outputs: []outputInfo{
-                               {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
+                               {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
                        },
                },
        },
        {
-               name:   "FCFID",
+               name:   "MOVVF",
                argLen: 1,
-               asm:    ppc64.AFCFID,
+               asm:    mips.AMOVVF,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
+                               {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
                        },
                        outputs: []outputInfo{
-                               {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
+                               {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
                        },
                },
        },
        {
-               name:   "FCFIDS",
+               name:   "MOVVD",
                argLen: 1,
-               asm:    ppc64.AFCFIDS,
+               asm:    mips.AMOVVD,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
+                               {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
                        },
                        outputs: []outputInfo{
-                               {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
+                               {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
                        },
                },
        },
        {
-               name:   "FRSP",
+               name:   "TRUNCFW",
                argLen: 1,
-               asm:    ppc64.AFRSP,
+               asm:    mips.ATRUNCFW,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
+                               {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
                        },
                        outputs: []outputInfo{
-                               {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
+                               {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
                        },
                },
        },
        {
-               name:   "MFVSRD",
+               name:   "TRUNCDW",
                argLen: 1,
-               asm:    ppc64.AMFVSRD,
+               asm:    mips.ATRUNCDW,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
+                               {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
                        },
                        outputs: []outputInfo{
-                               {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+                               {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
                        },
                },
        },
        {
-               name:   "MTVSRD",
+               name:   "TRUNCFV",
                argLen: 1,
-               asm:    ppc64.AMTVSRD,
+               asm:    mips.ATRUNCFV,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+                               {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
                        },
                        outputs: []outputInfo{
-                               {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
+                               {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
                        },
                },
        },
        {
-               name:        "AND",
-               argLen:      2,
-               commutative: true,
-               asm:         ppc64.AAND,
+               name:   "TRUNCDV",
+               argLen: 1,
+               asm:    mips.ATRUNCDV,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
-                               {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+                               {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
                        },
                        outputs: []outputInfo{
-                               {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+                               {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
                        },
                },
        },
        {
-               name:   "ANDN",
-               argLen: 2,
-               asm:    ppc64.AANDN,
+               name:   "MOVFD",
+               argLen: 1,
+               asm:    mips.AMOVFD,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
-                               {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+                               {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
                        },
                        outputs: []outputInfo{
-                               {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+                               {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
                        },
                },
        },
        {
-               name:   "ANDNCC",
-               argLen: 2,
-               asm:    ppc64.AANDNCC,
+               name:   "MOVDF",
+               argLen: 1,
+               asm:    mips.AMOVDF,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
-                               {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+                               {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
                        },
                        outputs: []outputInfo{
-                               {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+                               {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
                        },
                },
        },
        {
-               name:        "ANDCC",
-               argLen:      2,
-               commutative: true,
-               asm:         ppc64.AANDCC,
+               name:         "CALLstatic",
+               auxType:      auxCallOff,
+               argLen:       1,
+               clobberFlags: true,
+               call:         true,
                reg: regInfo{
-                       inputs: []inputInfo{
-                               {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
-                               {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
-                       },
-                       outputs: []outputInfo{
-                               {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
-                       },
+                       clobbers: 4611686018393833470, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 HI LO
                },
        },
        {
-               name:        "OR",
-               argLen:      2,
-               commutative: true,
-               asm:         ppc64.AOR,
+               name:         "CALLtail",
+               auxType:      auxCallOff,
+               argLen:       1,
+               clobberFlags: true,
+               call:         true,
+               tailCall:     true,
                reg: regInfo{
-                       inputs: []inputInfo{
-                               {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
-                               {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
-                       },
-                       outputs: []outputInfo{
-                               {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
-                       },
+                       clobbers: 4611686018393833470, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 HI LO
                },
        },
        {
-               name:   "ORN",
-               argLen: 2,
-               asm:    ppc64.AORN,
+               name:         "CALLclosure",
+               auxType:      auxCallOff,
+               argLen:       3,
+               clobberFlags: true,
+               call:         true,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
-                               {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
-                       },
-                       outputs: []outputInfo{
-                               {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+                               {1, 4194304},   // R22
+                               {0, 201326590}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP R31
                        },
+                       clobbers: 4611686018393833470, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 HI LO
                },
        },
        {
-               name:        "ORCC",
-               argLen:      2,
-               commutative: true,
-               asm:         ppc64.AORCC,
-               reg: regInfo{
-                       inputs: []inputInfo{
-                               {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
-                               {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
-                       },
-                       outputs: []outputInfo{
-                               {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+               name:         "CALLinter",
+               auxType:      auxCallOff,
+               argLen:       2,
+               clobberFlags: true,
+               call:         true,
+               reg: regInfo{
+                       inputs: []inputInfo{
+                               {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
                        },
+                       clobbers: 4611686018393833470, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 HI LO
                },
        },
        {
-               name:        "NOR",
-               argLen:      2,
-               commutative: true,
-               asm:         ppc64.ANOR,
+               name:           "DUFFZERO",
+               auxType:        auxInt64,
+               argLen:         2,
+               faultOnNilArg0: true,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
-                               {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
-                       },
-                       outputs: []outputInfo{
-                               {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+                               {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
                        },
+                       clobbers: 134217730, // R1 R31
                },
        },
        {
-               name:        "NORCC",
-               argLen:      2,
-               commutative: true,
-               asm:         ppc64.ANORCC,
+               name:           "DUFFCOPY",
+               auxType:        auxInt64,
+               argLen:         3,
+               faultOnNilArg0: true,
+               faultOnNilArg1: true,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
-                               {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
-                       },
-                       outputs: []outputInfo{
-                               {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+                               {0, 4}, // R2
+                               {1, 2}, // R1
                        },
+                       clobbers: 134217734, // R1 R2 R31
                },
        },
        {
-               name:        "XOR",
-               argLen:      2,
-               commutative: true,
-               asm:         ppc64.AXOR,
+               name:           "LoweredZero",
+               auxType:        auxInt64,
+               argLen:         3,
+               clobberFlags:   true,
+               faultOnNilArg0: true,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
-                               {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
-                       },
-                       outputs: []outputInfo{
-                               {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+                               {0, 2},         // R1
+                               {1, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
                        },
+                       clobbers: 2, // R1
                },
        },
        {
-               name:        "XORCC",
-               argLen:      2,
-               commutative: true,
-               asm:         ppc64.AXORCC,
+               name:           "LoweredMove",
+               auxType:        auxInt64,
+               argLen:         4,
+               clobberFlags:   true,
+               faultOnNilArg0: true,
+               faultOnNilArg1: true,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
-                               {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
-                       },
-                       outputs: []outputInfo{
-                               {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+                               {0, 4},         // R2
+                               {1, 2},         // R1
+                               {2, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
                        },
+                       clobbers: 6, // R1 R2
                },
        },
        {
-               name:        "EQV",
-               argLen:      2,
-               commutative: true,
-               asm:         ppc64.AEQV,
+               name:           "LoweredAtomicAnd32",
+               argLen:         3,
+               faultOnNilArg0: true,
+               hasSideEffects: true,
+               unsafePoint:    true,
+               asm:            mips.AAND,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
-                               {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
-                       },
-                       outputs: []outputInfo{
-                               {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+                               {1, 234881022},           // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
+                               {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB
                        },
                },
        },
        {
-               name:   "NEG",
-               argLen: 1,
-               asm:    ppc64.ANEG,
+               name:           "LoweredAtomicOr32",
+               argLen:         3,
+               faultOnNilArg0: true,
+               hasSideEffects: true,
+               unsafePoint:    true,
+               asm:            mips.AOR,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
-                       },
-                       outputs: []outputInfo{
-                               {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+                               {1, 234881022},           // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
+                               {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB
                        },
                },
        },
        {
-               name:   "NEGCC",
-               argLen: 1,
-               asm:    ppc64.ANEGCC,
+               name:           "LoweredAtomicLoad8",
+               argLen:         2,
+               faultOnNilArg0: true,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+                               {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB
                        },
                        outputs: []outputInfo{
-                               {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+                               {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
                        },
                },
        },
        {
-               name:   "BRD",
-               argLen: 1,
-               asm:    ppc64.ABRD,
+               name:           "LoweredAtomicLoad32",
+               argLen:         2,
+               faultOnNilArg0: true,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+                               {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB
                        },
                        outputs: []outputInfo{
-                               {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+                               {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
                        },
                },
        },
        {
-               name:   "BRW",
-               argLen: 1,
-               asm:    ppc64.ABRW,
+               name:           "LoweredAtomicLoad64",
+               argLen:         2,
+               faultOnNilArg0: true,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+                               {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB
                        },
                        outputs: []outputInfo{
-                               {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+                               {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
                        },
                },
        },
        {
-               name:   "BRH",
-               argLen: 1,
-               asm:    ppc64.ABRH,
+               name:           "LoweredAtomicStore8",
+               argLen:         3,
+               faultOnNilArg0: true,
+               hasSideEffects: true,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
-                       },
-                       outputs: []outputInfo{
-                               {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+                               {1, 234881022},           // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
+                               {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB
                        },
                },
        },
        {
-               name:   "FNEG",
-               argLen: 1,
-               asm:    ppc64.AFNEG,
+               name:           "LoweredAtomicStore32",
+               argLen:         3,
+               faultOnNilArg0: true,
+               hasSideEffects: true,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
+                               {1, 234881022},           // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
+                               {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB
                        },
-                       outputs: []outputInfo{
-                               {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
+               },
+       },
+       {
+               name:           "LoweredAtomicStore64",
+               argLen:         3,
+               faultOnNilArg0: true,
+               hasSideEffects: true,
+               reg: regInfo{
+                       inputs: []inputInfo{
+                               {1, 234881022},           // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
+                               {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB
                        },
                },
        },
        {
-               name:   "FSQRT",
-               argLen: 1,
-               asm:    ppc64.AFSQRT,
+               name:           "LoweredAtomicStorezero32",
+               argLen:         2,
+               faultOnNilArg0: true,
+               hasSideEffects: true,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
+                               {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB
                        },
-                       outputs: []outputInfo{
-                               {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
+               },
+       },
+       {
+               name:           "LoweredAtomicStorezero64",
+               argLen:         2,
+               faultOnNilArg0: true,
+               hasSideEffects: true,
+               reg: regInfo{
+                       inputs: []inputInfo{
+                               {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB
                        },
                },
        },
        {
-               name:   "FSQRTS",
-               argLen: 1,
-               asm:    ppc64.AFSQRTS,
+               name:            "LoweredAtomicExchange32",
+               argLen:          3,
+               resultNotInArgs: true,
+               faultOnNilArg0:  true,
+               hasSideEffects:  true,
+               unsafePoint:     true,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
+                               {1, 234881022},           // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
+                               {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB
                        },
                        outputs: []outputInfo{
-                               {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
+                               {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
                        },
                },
        },
        {
-               name:   "FFLOOR",
-               argLen: 1,
-               asm:    ppc64.AFRIM,
+               name:            "LoweredAtomicExchange64",
+               argLen:          3,
+               resultNotInArgs: true,
+               faultOnNilArg0:  true,
+               hasSideEffects:  true,
+               unsafePoint:     true,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
+                               {1, 234881022},           // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
+                               {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB
                        },
                        outputs: []outputInfo{
-                               {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
+                               {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
                        },
                },
        },
        {
-               name:   "FCEIL",
-               argLen: 1,
-               asm:    ppc64.AFRIP,
+               name:            "LoweredAtomicAdd32",
+               argLen:          3,
+               resultNotInArgs: true,
+               faultOnNilArg0:  true,
+               hasSideEffects:  true,
+               unsafePoint:     true,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
+                               {1, 234881022},           // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
+                               {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB
                        },
                        outputs: []outputInfo{
-                               {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
+                               {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
                        },
                },
        },
        {
-               name:   "FTRUNC",
-               argLen: 1,
-               asm:    ppc64.AFRIZ,
+               name:            "LoweredAtomicAdd64",
+               argLen:          3,
+               resultNotInArgs: true,
+               faultOnNilArg0:  true,
+               hasSideEffects:  true,
+               unsafePoint:     true,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
+                               {1, 234881022},           // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
+                               {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB
                        },
                        outputs: []outputInfo{
-                               {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
+                               {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
                        },
                },
        },
        {
-               name:   "FROUND",
-               argLen: 1,
-               asm:    ppc64.AFRIN,
+               name:            "LoweredAtomicAddconst32",
+               auxType:         auxInt32,
+               argLen:          2,
+               resultNotInArgs: true,
+               faultOnNilArg0:  true,
+               hasSideEffects:  true,
+               unsafePoint:     true,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
+                               {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB
                        },
                        outputs: []outputInfo{
-                               {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
+                               {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
                        },
                },
        },
        {
-               name:   "FABS",
-               argLen: 1,
-               asm:    ppc64.AFABS,
+               name:            "LoweredAtomicAddconst64",
+               auxType:         auxInt64,
+               argLen:          2,
+               resultNotInArgs: true,
+               faultOnNilArg0:  true,
+               hasSideEffects:  true,
+               unsafePoint:     true,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
+                               {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB
                        },
                        outputs: []outputInfo{
-                               {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
+                               {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
                        },
                },
        },
        {
-               name:   "FNABS",
-               argLen: 1,
-               asm:    ppc64.AFNABS,
+               name:            "LoweredAtomicCas32",
+               argLen:          4,
+               resultNotInArgs: true,
+               faultOnNilArg0:  true,
+               hasSideEffects:  true,
+               unsafePoint:     true,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
+                               {1, 234881022},           // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
+                               {2, 234881022},           // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
+                               {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB
                        },
                        outputs: []outputInfo{
-                               {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
+                               {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
                        },
                },
        },
        {
-               name:   "FCPSGN",
-               argLen: 2,
-               asm:    ppc64.AFCPSGN,
+               name:            "LoweredAtomicCas64",
+               argLen:          4,
+               resultNotInArgs: true,
+               faultOnNilArg0:  true,
+               hasSideEffects:  true,
+               unsafePoint:     true,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
-                               {1, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
+                               {1, 234881022},           // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
+                               {2, 234881022},           // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
+                               {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB
                        },
                        outputs: []outputInfo{
-                               {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
+                               {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
                        },
                },
        },
        {
-               name:    "ORconst",
-               auxType: auxInt64,
-               argLen:  1,
-               asm:     ppc64.AOR,
+               name:           "LoweredNilCheck",
+               argLen:         2,
+               nilCheck:       true,
+               faultOnNilArg0: true,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+                               {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
                        },
+               },
+       },
+       {
+               name:   "FPFlagTrue",
+               argLen: 1,
+               reg: regInfo{
                        outputs: []outputInfo{
-                               {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+                               {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
                        },
                },
        },
        {
-               name:    "XORconst",
-               auxType: auxInt64,
-               argLen:  1,
-               asm:     ppc64.AXOR,
+               name:   "FPFlagFalse",
+               argLen: 1,
                reg: regInfo{
-                       inputs: []inputInfo{
-                               {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+                       outputs: []outputInfo{
+                               {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
                        },
+               },
+       },
+       {
+               name:      "LoweredGetClosurePtr",
+               argLen:    0,
+               zeroWidth: true,
+               reg: regInfo{
                        outputs: []outputInfo{
-                               {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+                               {0, 4194304}, // R22
                        },
                },
        },
        {
-               name:    "ANDCCconst",
-               auxType: auxInt64,
-               argLen:  1,
-               asm:     ppc64.AANDCC,
+               name:              "LoweredGetCallerSP",
+               argLen:            1,
+               rematerializeable: true,
                reg: regInfo{
-                       inputs: []inputInfo{
-                               {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+                       outputs: []outputInfo{
+                               {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
                        },
+               },
+       },
+       {
+               name:              "LoweredGetCallerPC",
+               argLen:            0,
+               rematerializeable: true,
+               reg: regInfo{
                        outputs: []outputInfo{
-                               {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+                               {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
                        },
                },
        },
        {
-               name:         "ANDconst",
+               name:         "LoweredWB",
                auxType:      auxInt64,
                argLen:       1,
                clobberFlags: true,
-               asm:          ppc64.AANDCC,
                reg: regInfo{
-                       inputs: []inputInfo{
-                               {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
-                       },
+                       clobbers: 4611686018293170176, // R31 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 HI LO
                        outputs: []outputInfo{
-                               {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+                               {0, 16777216}, // R25
                        },
                },
        },
        {
-               name:   "MOVBreg",
-               argLen: 1,
-               asm:    ppc64.AMOVB,
+               name:           "LoweredPubBarrier",
+               argLen:         1,
+               hasSideEffects: true,
+               asm:            mips.ASYNC,
+               reg:            regInfo{},
+       },
+       {
+               name:    "LoweredPanicBoundsA",
+               auxType: auxInt64,
+               argLen:  3,
+               call:    true,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
-                       },
-                       outputs: []outputInfo{
-                               {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+                               {0, 8},  // R3
+                               {1, 16}, // R4
                        },
                },
        },
        {
-               name:   "MOVBZreg",
-               argLen: 1,
-               asm:    ppc64.AMOVBZ,
+               name:    "LoweredPanicBoundsB",
+               auxType: auxInt64,
+               argLen:  3,
+               call:    true,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
-                       },
-                       outputs: []outputInfo{
-                               {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+                               {0, 4}, // R2
+                               {1, 8}, // R3
                        },
                },
        },
        {
-               name:   "MOVHreg",
-               argLen: 1,
-               asm:    ppc64.AMOVH,
+               name:    "LoweredPanicBoundsC",
+               auxType: auxInt64,
+               argLen:  3,
+               call:    true,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
-                       },
-                       outputs: []outputInfo{
-                               {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+                               {0, 2}, // R1
+                               {1, 4}, // R2
                        },
                },
        },
+
        {
-               name:   "MOVHZreg",
-               argLen: 1,
-               asm:    ppc64.AMOVHZ,
+               name:        "ADD",
+               argLen:      2,
+               commutative: true,
+               asm:         ppc64.AADD,
                reg: regInfo{
                        inputs: []inputInfo{
                                {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+                               {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
                        },
                        outputs: []outputInfo{
                                {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
@@ -44576,12 +46511,14 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:   "MOVWreg",
-               argLen: 1,
-               asm:    ppc64.AMOVW,
+               name:        "ADDCC",
+               argLen:      2,
+               commutative: true,
+               asm:         ppc64.AADDCC,
                reg: regInfo{
                        inputs: []inputInfo{
                                {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+                               {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
                        },
                        outputs: []outputInfo{
                                {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
@@ -44589,9 +46526,10 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:   "MOVWZreg",
-               argLen: 1,
-               asm:    ppc64.AMOVWZ,
+               name:    "ADDconst",
+               auxType: auxInt64,
+               argLen:  1,
+               asm:     ppc64.AADD,
                reg: regInfo{
                        inputs: []inputInfo{
                                {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
@@ -44602,63 +46540,58 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:           "MOVBZload",
-               auxType:        auxSymOff,
-               argLen:         2,
-               faultOnNilArg0: true,
-               symEffect:      SymRead,
-               asm:            ppc64.AMOVBZ,
+               name:    "ADDCCconst",
+               auxType: auxInt64,
+               argLen:  1,
+               asm:     ppc64.AADDCCC,
                reg: regInfo{
                        inputs: []inputInfo{
                                {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
                        },
+                       clobbers: 9223372036854775808, // XER
                        outputs: []outputInfo{
                                {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
                        },
                },
        },
        {
-               name:           "MOVHload",
-               auxType:        auxSymOff,
-               argLen:         2,
-               faultOnNilArg0: true,
-               symEffect:      SymRead,
-               asm:            ppc64.AMOVH,
+               name:        "FADD",
+               argLen:      2,
+               commutative: true,
+               asm:         ppc64.AFADD,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+                               {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
+                               {1, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
                        },
                        outputs: []outputInfo{
-                               {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+                               {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
                        },
                },
        },
        {
-               name:           "MOVHZload",
-               auxType:        auxSymOff,
-               argLen:         2,
-               faultOnNilArg0: true,
-               symEffect:      SymRead,
-               asm:            ppc64.AMOVHZ,
+               name:        "FADDS",
+               argLen:      2,
+               commutative: true,
+               asm:         ppc64.AFADDS,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+                               {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
+                               {1, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
                        },
                        outputs: []outputInfo{
-                               {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+                               {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
                        },
                },
        },
        {
-               name:           "MOVWload",
-               auxType:        auxSymOff,
-               argLen:         2,
-               faultOnNilArg0: true,
-               symEffect:      SymRead,
-               asm:            ppc64.AMOVW,
+               name:   "SUB",
+               argLen: 2,
+               asm:    ppc64.ASUB,
                reg: regInfo{
                        inputs: []inputInfo{
                                {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+                               {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
                        },
                        outputs: []outputInfo{
                                {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
@@ -44666,15 +46599,13 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:           "MOVWZload",
-               auxType:        auxSymOff,
-               argLen:         2,
-               faultOnNilArg0: true,
-               symEffect:      SymRead,
-               asm:            ppc64.AMOVWZ,
+               name:   "SUBCC",
+               argLen: 2,
+               asm:    ppc64.ASUBCC,
                reg: regInfo{
                        inputs: []inputInfo{
                                {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+                               {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
                        },
                        outputs: []outputInfo{
                                {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
@@ -44682,85 +46613,85 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:           "MOVDload",
-               auxType:        auxSymOff,
-               argLen:         2,
-               faultOnNilArg0: true,
-               symEffect:      SymRead,
-               asm:            ppc64.AMOVD,
+               name:    "SUBFCconst",
+               auxType: auxInt64,
+               argLen:  1,
+               asm:     ppc64.ASUBC,
                reg: regInfo{
                        inputs: []inputInfo{
                                {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
                        },
+                       clobbers: 9223372036854775808, // XER
                        outputs: []outputInfo{
                                {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
                        },
                },
        },
        {
-               name:           "MOVDBRload",
-               argLen:         2,
-               faultOnNilArg0: true,
-               asm:            ppc64.AMOVDBR,
+               name:   "FSUB",
+               argLen: 2,
+               asm:    ppc64.AFSUB,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+                               {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
+                               {1, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
                        },
                        outputs: []outputInfo{
-                               {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+                               {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
                        },
                },
        },
        {
-               name:           "MOVWBRload",
-               argLen:         2,
-               faultOnNilArg0: true,
-               asm:            ppc64.AMOVWBR,
+               name:   "FSUBS",
+               argLen: 2,
+               asm:    ppc64.AFSUBS,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+                               {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
+                               {1, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
                        },
                        outputs: []outputInfo{
-                               {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+                               {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
                        },
                },
        },
        {
-               name:           "MOVHBRload",
-               argLen:         2,
-               faultOnNilArg0: true,
-               asm:            ppc64.AMOVHBR,
+               name:   "XSMINJDP",
+               argLen: 2,
+               asm:    ppc64.AXSMINJDP,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+                               {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
+                               {1, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
                        },
                        outputs: []outputInfo{
-                               {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+                               {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
                        },
                },
        },
        {
-               name:   "MOVBZloadidx",
-               argLen: 3,
-               asm:    ppc64.AMOVBZ,
+               name:   "XSMAXJDP",
+               argLen: 2,
+               asm:    ppc64.AXSMAXJDP,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {1, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
-                               {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+                               {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
+                               {1, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
                        },
                        outputs: []outputInfo{
-                               {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+                               {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
                        },
                },
        },
        {
-               name:   "MOVHloadidx",
-               argLen: 3,
-               asm:    ppc64.AMOVH,
+               name:        "MULLD",
+               argLen:      2,
+               commutative: true,
+               asm:         ppc64.AMULLD,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {1, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
                                {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+                               {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
                        },
                        outputs: []outputInfo{
                                {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
@@ -44768,13 +46699,14 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:   "MOVHZloadidx",
-               argLen: 3,
-               asm:    ppc64.AMOVHZ,
+               name:        "MULLW",
+               argLen:      2,
+               commutative: true,
+               asm:         ppc64.AMULLW,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {1, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
                                {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+                               {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
                        },
                        outputs: []outputInfo{
                                {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
@@ -44782,12 +46714,12 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:   "MOVWloadidx",
-               argLen: 3,
-               asm:    ppc64.AMOVW,
+               name:    "MULLDconst",
+               auxType: auxInt32,
+               argLen:  1,
+               asm:     ppc64.AMULLD,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {1, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
                                {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
                        },
                        outputs: []outputInfo{
@@ -44796,12 +46728,12 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:   "MOVWZloadidx",
-               argLen: 3,
-               asm:    ppc64.AMOVWZ,
+               name:    "MULLWconst",
+               auxType: auxInt32,
+               argLen:  1,
+               asm:     ppc64.AMULLW,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {1, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
                                {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
                        },
                        outputs: []outputInfo{
@@ -44810,13 +46742,14 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:   "MOVDloadidx",
+               name:   "MADDLD",
                argLen: 3,
-               asm:    ppc64.AMOVD,
+               asm:    ppc64.AMADDLD,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {1, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
                                {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+                               {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+                               {2, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
                        },
                        outputs: []outputInfo{
                                {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
@@ -44824,13 +46757,14 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:   "MOVHBRloadidx",
-               argLen: 3,
-               asm:    ppc64.AMOVHBR,
+               name:        "MULHD",
+               argLen:      2,
+               commutative: true,
+               asm:         ppc64.AMULHD,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {1, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
                                {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+                               {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
                        },
                        outputs: []outputInfo{
                                {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
@@ -44838,13 +46772,14 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:   "MOVWBRloadidx",
-               argLen: 3,
-               asm:    ppc64.AMOVWBR,
+               name:        "MULHW",
+               argLen:      2,
+               commutative: true,
+               asm:         ppc64.AMULHW,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {1, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
                                {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+                               {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
                        },
                        outputs: []outputInfo{
                                {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
@@ -44852,13 +46787,14 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:   "MOVDBRloadidx",
-               argLen: 3,
-               asm:    ppc64.AMOVDBR,
+               name:        "MULHDU",
+               argLen:      2,
+               commutative: true,
+               asm:         ppc64.AMULHDU,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {1, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
                                {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+                               {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
                        },
                        outputs: []outputInfo{
                                {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
@@ -44866,91 +46802,104 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:   "FMOVDloadidx",
-               argLen: 3,
-               asm:    ppc64.AFMOVD,
+               name:        "MULHDUCC",
+               argLen:      2,
+               commutative: true,
+               asm:         ppc64.AMULHDUCC,
                reg: regInfo{
                        inputs: []inputInfo{
                                {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
                                {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
                        },
                        outputs: []outputInfo{
-                               {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
+                               {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
                        },
                },
        },
        {
-               name:   "FMOVSloadidx",
-               argLen: 3,
-               asm:    ppc64.AFMOVS,
+               name:        "MULHWU",
+               argLen:      2,
+               commutative: true,
+               asm:         ppc64.AMULHWU,
                reg: regInfo{
                        inputs: []inputInfo{
                                {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
                                {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
                        },
                        outputs: []outputInfo{
-                               {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
+                               {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
                        },
                },
        },
        {
-               name:           "DCBT",
-               auxType:        auxInt64,
-               argLen:         2,
-               hasSideEffects: true,
-               asm:            ppc64.ADCBT,
+               name:        "FMUL",
+               argLen:      2,
+               commutative: true,
+               asm:         ppc64.AFMUL,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+                               {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
+                               {1, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
+                       },
+                       outputs: []outputInfo{
+                               {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
                        },
                },
        },
        {
-               name:           "MOVDBRstore",
-               argLen:         3,
-               faultOnNilArg0: true,
-               asm:            ppc64.AMOVDBR,
+               name:        "FMULS",
+               argLen:      2,
+               commutative: true,
+               asm:         ppc64.AFMULS,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
-                               {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+                               {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
+                               {1, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
+                       },
+                       outputs: []outputInfo{
+                               {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
                        },
                },
        },
        {
-               name:           "MOVWBRstore",
-               argLen:         3,
-               faultOnNilArg0: true,
-               asm:            ppc64.AMOVWBR,
+               name:   "FMADD",
+               argLen: 3,
+               asm:    ppc64.AFMADD,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
-                               {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+                               {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
+                               {1, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
+                               {2, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
+                       },
+                       outputs: []outputInfo{
+                               {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
                        },
                },
        },
        {
-               name:           "MOVHBRstore",
-               argLen:         3,
-               faultOnNilArg0: true,
-               asm:            ppc64.AMOVHBR,
+               name:   "FMADDS",
+               argLen: 3,
+               asm:    ppc64.AFMADDS,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
-                               {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+                               {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
+                               {1, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
+                               {2, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
+                       },
+                       outputs: []outputInfo{
+                               {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
                        },
                },
        },
        {
-               name:           "FMOVDload",
-               auxType:        auxSymOff,
-               argLen:         2,
-               faultOnNilArg0: true,
-               symEffect:      SymRead,
-               asm:            ppc64.AFMOVD,
+               name:   "FMSUB",
+               argLen: 3,
+               asm:    ppc64.AFMSUB,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+                               {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
+                               {1, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
+                               {2, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
                        },
                        outputs: []outputInfo{
                                {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
@@ -44958,15 +46907,14 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:           "FMOVSload",
-               auxType:        auxSymOff,
-               argLen:         2,
-               faultOnNilArg0: true,
-               symEffect:      SymRead,
-               asm:            ppc64.AFMOVS,
+               name:   "FMSUBS",
+               argLen: 3,
+               asm:    ppc64.AFMSUBS,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+                               {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
+                               {1, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
+                               {2, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
                        },
                        outputs: []outputInfo{
                                {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
@@ -44974,409 +46922,440 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:           "MOVBstore",
-               auxType:        auxSymOff,
-               argLen:         3,
-               faultOnNilArg0: true,
-               symEffect:      SymWrite,
-               asm:            ppc64.AMOVB,
+               name:   "SRAD",
+               argLen: 2,
+               asm:    ppc64.ASRAD,
                reg: regInfo{
                        inputs: []inputInfo{
                                {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
                                {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
                        },
+                       clobbers: 9223372036854775808, // XER
+                       outputs: []outputInfo{
+                               {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+                       },
                },
        },
        {
-               name:           "MOVHstore",
-               auxType:        auxSymOff,
-               argLen:         3,
-               faultOnNilArg0: true,
-               symEffect:      SymWrite,
-               asm:            ppc64.AMOVH,
+               name:   "SRAW",
+               argLen: 2,
+               asm:    ppc64.ASRAW,
                reg: regInfo{
                        inputs: []inputInfo{
                                {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
                                {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
                        },
+                       clobbers: 9223372036854775808, // XER
+                       outputs: []outputInfo{
+                               {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+                       },
                },
        },
        {
-               name:           "MOVWstore",
-               auxType:        auxSymOff,
-               argLen:         3,
-               faultOnNilArg0: true,
-               symEffect:      SymWrite,
-               asm:            ppc64.AMOVW,
+               name:   "SRD",
+               argLen: 2,
+               asm:    ppc64.ASRD,
                reg: regInfo{
                        inputs: []inputInfo{
                                {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
                                {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
                        },
+                       outputs: []outputInfo{
+                               {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+                       },
                },
        },
        {
-               name:           "MOVDstore",
-               auxType:        auxSymOff,
-               argLen:         3,
-               faultOnNilArg0: true,
-               symEffect:      SymWrite,
-               asm:            ppc64.AMOVD,
+               name:   "SRW",
+               argLen: 2,
+               asm:    ppc64.ASRW,
                reg: regInfo{
                        inputs: []inputInfo{
                                {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
                                {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
                        },
-               },
-       },
-       {
-               name:           "FMOVDstore",
-               auxType:        auxSymOff,
-               argLen:         3,
-               faultOnNilArg0: true,
-               symEffect:      SymWrite,
-               asm:            ppc64.AFMOVD,
-               reg: regInfo{
-                       inputs: []inputInfo{
-                               {0, 1073733630},          // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
-                               {1, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
-                       },
-               },
-       },
-       {
-               name:           "FMOVSstore",
-               auxType:        auxSymOff,
-               argLen:         3,
-               faultOnNilArg0: true,
-               symEffect:      SymWrite,
-               asm:            ppc64.AFMOVS,
-               reg: regInfo{
-                       inputs: []inputInfo{
-                               {0, 1073733630},          // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
-                               {1, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
+                       outputs: []outputInfo{
+                               {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
                        },
                },
        },
        {
-               name:   "MOVBstoreidx",
-               argLen: 4,
-               asm:    ppc64.AMOVB,
+               name:   "SLD",
+               argLen: 2,
+               asm:    ppc64.ASLD,
                reg: regInfo{
                        inputs: []inputInfo{
                                {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
                                {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
-                               {2, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+                       },
+                       outputs: []outputInfo{
+                               {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
                        },
                },
        },
        {
-               name:   "MOVHstoreidx",
-               argLen: 4,
-               asm:    ppc64.AMOVH,
+               name:   "SLW",
+               argLen: 2,
+               asm:    ppc64.ASLW,
                reg: regInfo{
                        inputs: []inputInfo{
                                {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
                                {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
-                               {2, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+                       },
+                       outputs: []outputInfo{
+                               {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
                        },
                },
        },
        {
-               name:   "MOVWstoreidx",
-               argLen: 4,
-               asm:    ppc64.AMOVW,
+               name:   "ROTL",
+               argLen: 2,
+               asm:    ppc64.AROTL,
                reg: regInfo{
                        inputs: []inputInfo{
                                {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
                                {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
-                               {2, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+                       },
+                       outputs: []outputInfo{
+                               {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
                        },
                },
        },
        {
-               name:   "MOVDstoreidx",
-               argLen: 4,
-               asm:    ppc64.AMOVD,
+               name:   "ROTLW",
+               argLen: 2,
+               asm:    ppc64.AROTLW,
                reg: regInfo{
                        inputs: []inputInfo{
                                {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
                                {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
-                               {2, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+                       },
+                       outputs: []outputInfo{
+                               {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
                        },
                },
        },
        {
-               name:   "FMOVDstoreidx",
-               argLen: 4,
-               asm:    ppc64.AFMOVD,
+               name:    "CLRLSLWI",
+               auxType: auxInt32,
+               argLen:  1,
+               asm:     ppc64.ACLRLSLWI,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 1073733630},          // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
-                               {1, 1073733630},          // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
-                               {2, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
+                               {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+                       },
+                       outputs: []outputInfo{
+                               {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
                        },
                },
        },
        {
-               name:   "FMOVSstoreidx",
-               argLen: 4,
-               asm:    ppc64.AFMOVS,
+               name:    "CLRLSLDI",
+               auxType: auxInt32,
+               argLen:  1,
+               asm:     ppc64.ACLRLSLDI,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 1073733630},          // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
-                               {1, 1073733630},          // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
-                               {2, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
+                               {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+                       },
+                       outputs: []outputInfo{
+                               {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
                        },
                },
        },
        {
-               name:   "MOVHBRstoreidx",
-               argLen: 4,
-               asm:    ppc64.AMOVHBR,
+               name:        "ADDC",
+               argLen:      2,
+               commutative: true,
+               asm:         ppc64.AADDC,
                reg: regInfo{
                        inputs: []inputInfo{
                                {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
                                {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
-                               {2, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+                       },
+                       clobbers: 9223372036854775808, // XER
+                       outputs: []outputInfo{
+                               {1, 9223372036854775808}, // XER
+                               {0, 1073733624},          // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
                        },
                },
        },
        {
-               name:   "MOVWBRstoreidx",
-               argLen: 4,
-               asm:    ppc64.AMOVWBR,
+               name:   "SUBC",
+               argLen: 2,
+               asm:    ppc64.ASUBC,
                reg: regInfo{
                        inputs: []inputInfo{
                                {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
                                {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
-                               {2, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+                       },
+                       clobbers: 9223372036854775808, // XER
+                       outputs: []outputInfo{
+                               {1, 9223372036854775808}, // XER
+                               {0, 1073733624},          // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
                        },
                },
        },
        {
-               name:   "MOVDBRstoreidx",
-               argLen: 4,
-               asm:    ppc64.AMOVDBR,
+               name:    "ADDCconst",
+               auxType: auxInt64,
+               argLen:  1,
+               asm:     ppc64.AADDC,
                reg: regInfo{
                        inputs: []inputInfo{
                                {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
-                               {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
-                               {2, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+                       },
+                       outputs: []outputInfo{
+                               {1, 9223372036854775808}, // XER
+                               {0, 1073733624},          // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
                        },
                },
        },
        {
-               name:           "MOVBstorezero",
-               auxType:        auxSymOff,
-               argLen:         2,
-               faultOnNilArg0: true,
-               symEffect:      SymWrite,
-               asm:            ppc64.AMOVB,
+               name:    "SUBCconst",
+               auxType: auxInt64,
+               argLen:  1,
+               asm:     ppc64.ASUBC,
                reg: regInfo{
                        inputs: []inputInfo{
                                {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
                        },
+                       outputs: []outputInfo{
+                               {1, 9223372036854775808}, // XER
+                               {0, 1073733624},          // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+                       },
                },
        },
        {
-               name:           "MOVHstorezero",
-               auxType:        auxSymOff,
-               argLen:         2,
-               faultOnNilArg0: true,
-               symEffect:      SymWrite,
-               asm:            ppc64.AMOVH,
+               name:        "ADDE",
+               argLen:      3,
+               commutative: true,
+               asm:         ppc64.AADDE,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+                               {2, 9223372036854775808}, // XER
+                               {0, 1073733630},          // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+                               {1, 1073733630},          // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+                       },
+                       clobbers: 9223372036854775808, // XER
+                       outputs: []outputInfo{
+                               {1, 9223372036854775808}, // XER
+                               {0, 1073733624},          // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
                        },
                },
        },
        {
-               name:           "MOVWstorezero",
-               auxType:        auxSymOff,
-               argLen:         2,
-               faultOnNilArg0: true,
-               symEffect:      SymWrite,
-               asm:            ppc64.AMOVW,
+               name:   "ADDZE",
+               argLen: 2,
+               asm:    ppc64.AADDZE,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+                               {1, 9223372036854775808}, // XER
+                               {0, 1073733630},          // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+                       },
+                       clobbers: 9223372036854775808, // XER
+                       outputs: []outputInfo{
+                               {1, 9223372036854775808}, // XER
+                               {0, 1073733624},          // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
                        },
                },
        },
        {
-               name:           "MOVDstorezero",
-               auxType:        auxSymOff,
-               argLen:         2,
-               faultOnNilArg0: true,
-               symEffect:      SymWrite,
-               asm:            ppc64.AMOVD,
+               name:   "SUBE",
+               argLen: 3,
+               asm:    ppc64.ASUBE,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+                               {2, 9223372036854775808}, // XER
+                               {0, 1073733630},          // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+                               {1, 1073733630},          // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+                       },
+                       clobbers: 9223372036854775808, // XER
+                       outputs: []outputInfo{
+                               {1, 9223372036854775808}, // XER
+                               {0, 1073733624},          // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
                        },
                },
        },
        {
-               name:              "MOVDaddr",
-               auxType:           auxSymOff,
-               argLen:            1,
-               rematerializeable: true,
-               symEffect:         SymAddr,
-               asm:               ppc64.AMOVD,
+               name:   "ADDZEzero",
+               argLen: 1,
+               asm:    ppc64.AADDZE,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+                               {0, 9223372036854775808}, // XER
                        },
+                       clobbers: 9223372036854775808, // XER
                        outputs: []outputInfo{
                                {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
                        },
                },
        },
        {
-               name:              "MOVDconst",
-               auxType:           auxInt64,
-               argLen:            0,
-               rematerializeable: true,
-               asm:               ppc64.AMOVD,
+               name:   "SUBZEzero",
+               argLen: 1,
+               asm:    ppc64.ASUBZE,
                reg: regInfo{
+                       inputs: []inputInfo{
+                               {0, 9223372036854775808}, // XER
+                       },
+                       clobbers: 9223372036854775808, // XER
                        outputs: []outputInfo{
                                {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
                        },
                },
        },
        {
-               name:              "FMOVDconst",
-               auxType:           auxFloat64,
-               argLen:            0,
-               rematerializeable: true,
-               asm:               ppc64.AFMOVD,
-               reg: regInfo{
-                       outputs: []outputInfo{
-                               {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
-                       },
-               },
-       },
-       {
-               name:              "FMOVSconst",
-               auxType:           auxFloat32,
-               argLen:            0,
-               rematerializeable: true,
-               asm:               ppc64.AFMOVS,
+               name:    "SRADconst",
+               auxType: auxInt64,
+               argLen:  1,
+               asm:     ppc64.ASRAD,
                reg: regInfo{
+                       inputs: []inputInfo{
+                               {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+                       },
+                       clobbers: 9223372036854775808, // XER
                        outputs: []outputInfo{
-                               {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
+                               {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
                        },
                },
        },
        {
-               name:   "FCMPU",
-               argLen: 2,
-               asm:    ppc64.AFCMPU,
+               name:    "SRAWconst",
+               auxType: auxInt64,
+               argLen:  1,
+               asm:     ppc64.ASRAW,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
-                               {1, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
+                               {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+                       },
+                       clobbers: 9223372036854775808, // XER
+                       outputs: []outputInfo{
+                               {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
                        },
                },
        },
        {
-               name:   "CMP",
-               argLen: 2,
-               asm:    ppc64.ACMP,
+               name:    "SRDconst",
+               auxType: auxInt64,
+               argLen:  1,
+               asm:     ppc64.ASRD,
                reg: regInfo{
                        inputs: []inputInfo{
                                {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
-                               {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+                       },
+                       outputs: []outputInfo{
+                               {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
                        },
                },
        },
        {
-               name:   "CMPU",
-               argLen: 2,
-               asm:    ppc64.ACMPU,
+               name:    "SRWconst",
+               auxType: auxInt64,
+               argLen:  1,
+               asm:     ppc64.ASRW,
                reg: regInfo{
                        inputs: []inputInfo{
                                {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
-                               {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+                       },
+                       outputs: []outputInfo{
+                               {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
                        },
                },
        },
        {
-               name:   "CMPW",
-               argLen: 2,
-               asm:    ppc64.ACMPW,
+               name:    "SLDconst",
+               auxType: auxInt64,
+               argLen:  1,
+               asm:     ppc64.ASLD,
                reg: regInfo{
                        inputs: []inputInfo{
                                {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
-                               {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+                       },
+                       outputs: []outputInfo{
+                               {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
                        },
                },
        },
        {
-               name:   "CMPWU",
-               argLen: 2,
-               asm:    ppc64.ACMPWU,
+               name:    "SLWconst",
+               auxType: auxInt64,
+               argLen:  1,
+               asm:     ppc64.ASLW,
                reg: regInfo{
                        inputs: []inputInfo{
                                {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
-                               {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+                       },
+                       outputs: []outputInfo{
+                               {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
                        },
                },
        },
        {
-               name:    "CMPconst",
+               name:    "ROTLconst",
                auxType: auxInt64,
                argLen:  1,
-               asm:     ppc64.ACMP,
+               asm:     ppc64.AROTL,
                reg: regInfo{
                        inputs: []inputInfo{
                                {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
                        },
+                       outputs: []outputInfo{
+                               {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+                       },
                },
        },
        {
-               name:    "CMPUconst",
+               name:    "ROTLWconst",
                auxType: auxInt64,
                argLen:  1,
-               asm:     ppc64.ACMPU,
+               asm:     ppc64.AROTLW,
                reg: regInfo{
                        inputs: []inputInfo{
                                {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
                        },
+                       outputs: []outputInfo{
+                               {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+                       },
                },
        },
        {
-               name:    "CMPWconst",
-               auxType: auxInt32,
+               name:    "EXTSWSLconst",
+               auxType: auxInt64,
                argLen:  1,
-               asm:     ppc64.ACMPW,
+               asm:     ppc64.AEXTSWSLI,
                reg: regInfo{
                        inputs: []inputInfo{
                                {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
                        },
+                       outputs: []outputInfo{
+                               {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+                       },
                },
        },
        {
-               name:    "CMPWUconst",
-               auxType: auxInt32,
+               name:    "RLWINM",
+               auxType: auxInt64,
                argLen:  1,
-               asm:     ppc64.ACMPWU,
+               asm:     ppc64.ARLWNM,
                reg: regInfo{
                        inputs: []inputInfo{
                                {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
                        },
+                       outputs: []outputInfo{
+                               {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+                       },
                },
        },
        {
-               name:    "ISEL",
-               auxType: auxInt32,
-               argLen:  3,
-               asm:     ppc64.AISEL,
+               name:    "RLWNM",
+               auxType: auxInt64,
+               argLen:  2,
+               asm:     ppc64.ARLWNM,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
-                               {1, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+                               {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+                               {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
                        },
                        outputs: []outputInfo{
                                {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
@@ -45384,13 +47363,15 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:    "ISELZ",
-               auxType: auxInt32,
-               argLen:  2,
-               asm:     ppc64.AISEL,
+               name:         "RLWMI",
+               auxType:      auxInt64,
+               argLen:       2,
+               resultInArg0: true,
+               asm:          ppc64.ARLWMI,
                reg: regInfo{
                        inputs: []inputInfo{
                                {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+                               {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
                        },
                        outputs: []outputInfo{
                                {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
@@ -45398,396 +47379,434 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:    "SETBC",
-               auxType: auxInt32,
+               name:    "RLDICL",
+               auxType: auxInt64,
                argLen:  1,
-               asm:     ppc64.ASETBC,
+               asm:     ppc64.ARLDICL,
                reg: regInfo{
+                       inputs: []inputInfo{
+                               {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+                       },
                        outputs: []outputInfo{
                                {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
                        },
                },
        },
        {
-               name:    "SETBCR",
-               auxType: auxInt32,
+               name:    "RLDICLCC",
+               auxType: auxInt64,
                argLen:  1,
-               asm:     ppc64.ASETBCR,
+               asm:     ppc64.ARLDICLCC,
                reg: regInfo{
+                       inputs: []inputInfo{
+                               {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+                       },
                        outputs: []outputInfo{
                                {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
                        },
                },
        },
        {
-               name:   "Equal",
-               argLen: 1,
+               name:    "RLDICR",
+               auxType: auxInt64,
+               argLen:  1,
+               asm:     ppc64.ARLDICR,
                reg: regInfo{
+                       inputs: []inputInfo{
+                               {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+                       },
                        outputs: []outputInfo{
                                {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
                        },
                },
        },
        {
-               name:   "NotEqual",
+               name:   "CNTLZD",
                argLen: 1,
+               asm:    ppc64.ACNTLZD,
                reg: regInfo{
+                       inputs: []inputInfo{
+                               {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+                       },
                        outputs: []outputInfo{
                                {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
                        },
                },
        },
        {
-               name:   "LessThan",
+               name:   "CNTLZDCC",
                argLen: 1,
+               asm:    ppc64.ACNTLZDCC,
                reg: regInfo{
+                       inputs: []inputInfo{
+                               {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+                       },
                        outputs: []outputInfo{
                                {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
                        },
                },
        },
        {
-               name:   "FLessThan",
+               name:   "CNTLZW",
                argLen: 1,
+               asm:    ppc64.ACNTLZW,
                reg: regInfo{
+                       inputs: []inputInfo{
+                               {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+                       },
                        outputs: []outputInfo{
                                {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
                        },
                },
        },
        {
-               name:   "LessEqual",
+               name:   "CNTTZD",
                argLen: 1,
+               asm:    ppc64.ACNTTZD,
                reg: regInfo{
+                       inputs: []inputInfo{
+                               {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+                       },
                        outputs: []outputInfo{
                                {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
                        },
                },
        },
        {
-               name:   "FLessEqual",
+               name:   "CNTTZW",
                argLen: 1,
+               asm:    ppc64.ACNTTZW,
                reg: regInfo{
+                       inputs: []inputInfo{
+                               {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+                       },
                        outputs: []outputInfo{
                                {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
                        },
                },
        },
        {
-               name:   "GreaterThan",
+               name:   "POPCNTD",
                argLen: 1,
+               asm:    ppc64.APOPCNTD,
                reg: regInfo{
+                       inputs: []inputInfo{
+                               {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+                       },
                        outputs: []outputInfo{
                                {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
                        },
                },
        },
        {
-               name:   "FGreaterThan",
+               name:   "POPCNTW",
                argLen: 1,
+               asm:    ppc64.APOPCNTW,
                reg: regInfo{
+                       inputs: []inputInfo{
+                               {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+                       },
                        outputs: []outputInfo{
                                {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
                        },
                },
        },
        {
-               name:   "GreaterEqual",
+               name:   "POPCNTB",
                argLen: 1,
+               asm:    ppc64.APOPCNTB,
                reg: regInfo{
+                       inputs: []inputInfo{
+                               {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+                       },
                        outputs: []outputInfo{
                                {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
                        },
                },
        },
        {
-               name:   "FGreaterEqual",
-               argLen: 1,
+               name:   "FDIV",
+               argLen: 2,
+               asm:    ppc64.AFDIV,
                reg: regInfo{
+                       inputs: []inputInfo{
+                               {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
+                               {1, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
+                       },
                        outputs: []outputInfo{
-                               {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+                               {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
                        },
                },
        },
        {
-               name:      "LoweredGetClosurePtr",
-               argLen:    0,
-               zeroWidth: true,
+               name:   "FDIVS",
+               argLen: 2,
+               asm:    ppc64.AFDIVS,
                reg: regInfo{
+                       inputs: []inputInfo{
+                               {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
+                               {1, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
+                       },
                        outputs: []outputInfo{
-                               {0, 2048}, // R11
+                               {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
                        },
                },
        },
        {
-               name:              "LoweredGetCallerSP",
-               argLen:            1,
-               rematerializeable: true,
+               name:   "DIVD",
+               argLen: 2,
+               asm:    ppc64.ADIVD,
                reg: regInfo{
+                       inputs: []inputInfo{
+                               {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+                               {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+                       },
                        outputs: []outputInfo{
                                {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
                        },
                },
        },
        {
-               name:              "LoweredGetCallerPC",
-               argLen:            0,
-               rematerializeable: true,
+               name:   "DIVW",
+               argLen: 2,
+               asm:    ppc64.ADIVW,
                reg: regInfo{
+                       inputs: []inputInfo{
+                               {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+                               {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+                       },
                        outputs: []outputInfo{
                                {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
                        },
                },
        },
        {
-               name:           "LoweredNilCheck",
-               argLen:         2,
-               clobberFlags:   true,
-               nilCheck:       true,
-               faultOnNilArg0: true,
+               name:   "DIVDU",
+               argLen: 2,
+               asm:    ppc64.ADIVDU,
                reg: regInfo{
                        inputs: []inputInfo{
                                {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+                               {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+                       },
+                       outputs: []outputInfo{
+                               {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
                        },
-                       clobbers: 2147483648, // R31
                },
        },
        {
-               name:         "LoweredRound32F",
-               argLen:       1,
-               resultInArg0: true,
-               zeroWidth:    true,
+               name:   "DIVWU",
+               argLen: 2,
+               asm:    ppc64.ADIVWU,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
+                               {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+                               {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
                        },
                        outputs: []outputInfo{
-                               {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
+                               {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
                        },
                },
        },
        {
-               name:         "LoweredRound64F",
-               argLen:       1,
-               resultInArg0: true,
-               zeroWidth:    true,
+               name:   "MODUD",
+               argLen: 2,
+               asm:    ppc64.AMODUD,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
+                               {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+                               {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
                        },
                        outputs: []outputInfo{
-                               {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
+                               {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
                        },
                },
        },
        {
-               name:         "CALLstatic",
-               auxType:      auxCallOff,
-               argLen:       -1,
-               clobberFlags: true,
-               call:         true,
-               reg: regInfo{
-                       clobbers: 18446744071562059768, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 g F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 XER
-               },
-       },
-       {
-               name:         "CALLtail",
-               auxType:      auxCallOff,
-               argLen:       -1,
-               clobberFlags: true,
-               call:         true,
-               tailCall:     true,
-               reg: regInfo{
-                       clobbers: 18446744071562059768, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 g F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 XER
-               },
-       },
-       {
-               name:         "CALLclosure",
-               auxType:      auxCallOff,
-               argLen:       -1,
-               clobberFlags: true,
-               call:         true,
+               name:   "MODSD",
+               argLen: 2,
+               asm:    ppc64.AMODSD,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 4096}, // R12
-                               {1, 2048}, // R11
+                               {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+                               {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+                       },
+                       outputs: []outputInfo{
+                               {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
                        },
-                       clobbers: 18446744071562059768, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 g F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 XER
                },
        },
        {
-               name:         "CALLinter",
-               auxType:      auxCallOff,
-               argLen:       -1,
-               clobberFlags: true,
-               call:         true,
+               name:   "MODUW",
+               argLen: 2,
+               asm:    ppc64.AMODUW,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 4096}, // R12
+                               {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+                               {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+                       },
+                       outputs: []outputInfo{
+                               {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
                        },
-                       clobbers: 18446744071562059768, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 g F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 XER
                },
        },
        {
-               name:           "LoweredZero",
-               auxType:        auxInt64,
-               argLen:         2,
-               clobberFlags:   true,
-               faultOnNilArg0: true,
-               unsafePoint:    true,
+               name:   "MODSW",
+               argLen: 2,
+               asm:    ppc64.AMODSW,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 1048576}, // R20
+                               {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+                               {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+                       },
+                       outputs: []outputInfo{
+                               {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
                        },
-                       clobbers: 1048576, // R20
                },
        },
        {
-               name:           "LoweredZeroShort",
-               auxType:        auxInt64,
-               argLen:         2,
-               faultOnNilArg0: true,
-               unsafePoint:    true,
+               name:   "FCTIDZ",
+               argLen: 1,
+               asm:    ppc64.AFCTIDZ,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+                               {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
+                       },
+                       outputs: []outputInfo{
+                               {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
                        },
                },
        },
        {
-               name:           "LoweredQuadZeroShort",
-               auxType:        auxInt64,
-               argLen:         2,
-               faultOnNilArg0: true,
-               unsafePoint:    true,
+               name:   "FCTIWZ",
+               argLen: 1,
+               asm:    ppc64.AFCTIWZ,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+                               {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
+                       },
+                       outputs: []outputInfo{
+                               {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
                        },
                },
        },
        {
-               name:           "LoweredQuadZero",
-               auxType:        auxInt64,
-               argLen:         2,
-               clobberFlags:   true,
-               faultOnNilArg0: true,
-               unsafePoint:    true,
+               name:   "FCFID",
+               argLen: 1,
+               asm:    ppc64.AFCFID,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 1048576}, // R20
+                               {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
+                       },
+                       outputs: []outputInfo{
+                               {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
                        },
-                       clobbers: 1048576, // R20
                },
        },
        {
-               name:           "LoweredMove",
-               auxType:        auxInt64,
-               argLen:         3,
-               clobberFlags:   true,
-               faultOnNilArg0: true,
-               faultOnNilArg1: true,
-               unsafePoint:    true,
+               name:   "FCFIDS",
+               argLen: 1,
+               asm:    ppc64.AFCFIDS,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 1048576}, // R20
-                               {1, 2097152}, // R21
+                               {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
+                       },
+                       outputs: []outputInfo{
+                               {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
                        },
-                       clobbers: 3145728, // R20 R21
                },
        },
        {
-               name:           "LoweredMoveShort",
-               auxType:        auxInt64,
-               argLen:         3,
-               faultOnNilArg0: true,
-               faultOnNilArg1: true,
-               unsafePoint:    true,
+               name:   "FRSP",
+               argLen: 1,
+               asm:    ppc64.AFRSP,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
-                               {1, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+                               {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
+                       },
+                       outputs: []outputInfo{
+                               {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
                        },
                },
        },
        {
-               name:           "LoweredQuadMove",
-               auxType:        auxInt64,
-               argLen:         3,
-               clobberFlags:   true,
-               faultOnNilArg0: true,
-               faultOnNilArg1: true,
-               unsafePoint:    true,
+               name:   "MFVSRD",
+               argLen: 1,
+               asm:    ppc64.AMFVSRD,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 1048576}, // R20
-                               {1, 2097152}, // R21
+                               {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
+                       },
+                       outputs: []outputInfo{
+                               {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
                        },
-                       clobbers: 3145728, // R20 R21
                },
        },
        {
-               name:           "LoweredQuadMoveShort",
-               auxType:        auxInt64,
-               argLen:         3,
-               faultOnNilArg0: true,
-               faultOnNilArg1: true,
-               unsafePoint:    true,
+               name:   "MTVSRD",
+               argLen: 1,
+               asm:    ppc64.AMTVSRD,
                reg: regInfo{
                        inputs: []inputInfo{
                                {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
-                               {1, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+                       },
+                       outputs: []outputInfo{
+                               {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
                        },
                },
        },
        {
-               name:           "LoweredAtomicStore8",
-               auxType:        auxInt64,
-               argLen:         3,
-               faultOnNilArg0: true,
-               hasSideEffects: true,
+               name:        "AND",
+               argLen:      2,
+               commutative: true,
+               asm:         ppc64.AAND,
                reg: regInfo{
                        inputs: []inputInfo{
                                {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
                                {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
                        },
+                       outputs: []outputInfo{
+                               {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+                       },
                },
        },
        {
-               name:           "LoweredAtomicStore32",
-               auxType:        auxInt64,
-               argLen:         3,
-               faultOnNilArg0: true,
-               hasSideEffects: true,
+               name:   "ANDN",
+               argLen: 2,
+               asm:    ppc64.AANDN,
                reg: regInfo{
                        inputs: []inputInfo{
                                {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
                                {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
                        },
+                       outputs: []outputInfo{
+                               {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+                       },
                },
        },
        {
-               name:           "LoweredAtomicStore64",
-               auxType:        auxInt64,
-               argLen:         3,
-               faultOnNilArg0: true,
-               hasSideEffects: true,
+               name:   "ANDNCC",
+               argLen: 2,
+               asm:    ppc64.AANDNCC,
                reg: regInfo{
                        inputs: []inputInfo{
                                {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
                                {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
                        },
+                       outputs: []outputInfo{
+                               {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+                       },
                },
        },
        {
-               name:           "LoweredAtomicLoad8",
-               auxType:        auxInt64,
-               argLen:         2,
-               clobberFlags:   true,
-               faultOnNilArg0: true,
+               name:        "ANDCC",
+               argLen:      2,
+               commutative: true,
+               asm:         ppc64.AANDCC,
                reg: regInfo{
                        inputs: []inputInfo{
                                {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+                               {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
                        },
                        outputs: []outputInfo{
                                {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
@@ -45795,14 +47814,14 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:           "LoweredAtomicLoad32",
-               auxType:        auxInt64,
-               argLen:         2,
-               clobberFlags:   true,
-               faultOnNilArg0: true,
+               name:        "OR",
+               argLen:      2,
+               commutative: true,
+               asm:         ppc64.AOR,
                reg: regInfo{
                        inputs: []inputInfo{
                                {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+                               {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
                        },
                        outputs: []outputInfo{
                                {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
@@ -45810,14 +47829,13 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:           "LoweredAtomicLoad64",
-               auxType:        auxInt64,
-               argLen:         2,
-               clobberFlags:   true,
-               faultOnNilArg0: true,
+               name:   "ORN",
+               argLen: 2,
+               asm:    ppc64.AORN,
                reg: regInfo{
                        inputs: []inputInfo{
                                {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+                               {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
                        },
                        outputs: []outputInfo{
                                {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
@@ -45825,14 +47843,14 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:           "LoweredAtomicLoadPtr",
-               auxType:        auxInt64,
-               argLen:         2,
-               clobberFlags:   true,
-               faultOnNilArg0: true,
+               name:        "ORCC",
+               argLen:      2,
+               commutative: true,
+               asm:         ppc64.AORCC,
                reg: regInfo{
                        inputs: []inputInfo{
                                {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+                               {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
                        },
                        outputs: []outputInfo{
                                {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
@@ -45840,16 +47858,14 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:            "LoweredAtomicAdd32",
-               argLen:          3,
-               resultNotInArgs: true,
-               clobberFlags:    true,
-               faultOnNilArg0:  true,
-               hasSideEffects:  true,
+               name:        "NOR",
+               argLen:      2,
+               commutative: true,
+               asm:         ppc64.ANOR,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {1, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
                                {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+                               {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
                        },
                        outputs: []outputInfo{
                                {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
@@ -45857,16 +47873,14 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:            "LoweredAtomicAdd64",
-               argLen:          3,
-               resultNotInArgs: true,
-               clobberFlags:    true,
-               faultOnNilArg0:  true,
-               hasSideEffects:  true,
+               name:        "NORCC",
+               argLen:      2,
+               commutative: true,
+               asm:         ppc64.ANORCC,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {1, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
                                {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+                               {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
                        },
                        outputs: []outputInfo{
                                {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
@@ -45874,16 +47888,14 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:            "LoweredAtomicExchange8",
-               argLen:          3,
-               resultNotInArgs: true,
-               clobberFlags:    true,
-               faultOnNilArg0:  true,
-               hasSideEffects:  true,
+               name:        "XOR",
+               argLen:      2,
+               commutative: true,
+               asm:         ppc64.AXOR,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {1, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
                                {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+                               {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
                        },
                        outputs: []outputInfo{
                                {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
@@ -45891,16 +47903,14 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:            "LoweredAtomicExchange32",
-               argLen:          3,
-               resultNotInArgs: true,
-               clobberFlags:    true,
-               faultOnNilArg0:  true,
-               hasSideEffects:  true,
+               name:        "XORCC",
+               argLen:      2,
+               commutative: true,
+               asm:         ppc64.AXORCC,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {1, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
                                {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+                               {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
                        },
                        outputs: []outputInfo{
                                {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
@@ -45908,16 +47918,14 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:            "LoweredAtomicExchange64",
-               argLen:          3,
-               resultNotInArgs: true,
-               clobberFlags:    true,
-               faultOnNilArg0:  true,
-               hasSideEffects:  true,
+               name:        "EQV",
+               argLen:      2,
+               commutative: true,
+               asm:         ppc64.AEQV,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {1, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
                                {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+                               {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
                        },
                        outputs: []outputInfo{
                                {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
@@ -45925,17 +47933,11 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:            "LoweredAtomicCas64",
-               auxType:         auxInt64,
-               argLen:          4,
-               resultNotInArgs: true,
-               clobberFlags:    true,
-               faultOnNilArg0:  true,
-               hasSideEffects:  true,
+               name:   "NEG",
+               argLen: 1,
+               asm:    ppc64.ANEG,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {1, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
-                               {2, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
                                {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
                        },
                        outputs: []outputInfo{
@@ -45944,17 +47946,11 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:            "LoweredAtomicCas32",
-               auxType:         auxInt64,
-               argLen:          4,
-               resultNotInArgs: true,
-               clobberFlags:    true,
-               faultOnNilArg0:  true,
-               hasSideEffects:  true,
+               name:   "NEGCC",
+               argLen: 1,
+               asm:    ppc64.ANEGCC,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {1, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
-                               {2, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
                                {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
                        },
                        outputs: []outputInfo{
@@ -45963,1464 +47959,1272 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:           "LoweredAtomicAnd8",
-               argLen:         3,
-               faultOnNilArg0: true,
-               hasSideEffects: true,
-               asm:            ppc64.AAND,
+               name:   "BRD",
+               argLen: 1,
+               asm:    ppc64.ABRD,
                reg: regInfo{
                        inputs: []inputInfo{
                                {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
-                               {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
                        },
-               },
-       },
-       {
-               name:           "LoweredAtomicAnd32",
-               argLen:         3,
-               faultOnNilArg0: true,
-               hasSideEffects: true,
-               asm:            ppc64.AAND,
-               reg: regInfo{
-                       inputs: []inputInfo{
-                               {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
-                               {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+                       outputs: []outputInfo{
+                               {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
                        },
                },
        },
        {
-               name:           "LoweredAtomicOr8",
-               argLen:         3,
-               faultOnNilArg0: true,
-               hasSideEffects: true,
-               asm:            ppc64.AOR,
+               name:   "BRW",
+               argLen: 1,
+               asm:    ppc64.ABRW,
                reg: regInfo{
                        inputs: []inputInfo{
                                {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
-                               {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+                       },
+                       outputs: []outputInfo{
+                               {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
                        },
                },
        },
        {
-               name:           "LoweredAtomicOr32",
-               argLen:         3,
-               faultOnNilArg0: true,
-               hasSideEffects: true,
-               asm:            ppc64.AOR,
+               name:   "BRH",
+               argLen: 1,
+               asm:    ppc64.ABRH,
                reg: regInfo{
                        inputs: []inputInfo{
                                {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
-                               {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
                        },
-               },
-       },
-       {
-               name:         "LoweredWB",
-               auxType:      auxInt64,
-               argLen:       1,
-               clobberFlags: true,
-               reg: regInfo{
-                       clobbers: 18446744072632408064, // R11 R12 R18 R19 R22 R23 R24 R25 R26 R27 R28 R29 R31 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 XER
                        outputs: []outputInfo{
-                               {0, 536870912}, // R29
-                       },
-               },
-       },
-       {
-               name:           "LoweredPubBarrier",
-               argLen:         1,
-               hasSideEffects: true,
-               asm:            ppc64.ALWSYNC,
-               reg:            regInfo{},
-       },
-       {
-               name:    "LoweredPanicBoundsA",
-               auxType: auxInt64,
-               argLen:  3,
-               call:    true,
-               reg: regInfo{
-                       inputs: []inputInfo{
-                               {0, 32}, // R5
-                               {1, 64}, // R6
+                               {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
                        },
                },
        },
        {
-               name:    "LoweredPanicBoundsB",
-               auxType: auxInt64,
-               argLen:  3,
-               call:    true,
+               name:   "FNEG",
+               argLen: 1,
+               asm:    ppc64.AFNEG,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 16}, // R4
-                               {1, 32}, // R5
+                               {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
                        },
-               },
-       },
-       {
-               name:    "LoweredPanicBoundsC",
-               auxType: auxInt64,
-               argLen:  3,
-               call:    true,
-               reg: regInfo{
-                       inputs: []inputInfo{
-                               {0, 8},  // R3
-                               {1, 16}, // R4
+                       outputs: []outputInfo{
+                               {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
                        },
                },
        },
        {
-               name:   "InvertFlags",
+               name:   "FSQRT",
                argLen: 1,
-               reg:    regInfo{},
-       },
-       {
-               name:   "FlagEQ",
-               argLen: 0,
-               reg:    regInfo{},
-       },
-       {
-               name:   "FlagLT",
-               argLen: 0,
-               reg:    regInfo{},
-       },
-       {
-               name:   "FlagGT",
-               argLen: 0,
-               reg:    regInfo{},
-       },
-
-       {
-               name:        "ADD",
-               argLen:      2,
-               commutative: true,
-               asm:         riscv.AADD,
+               asm:    ppc64.AFSQRT,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
-                               {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+                               {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
                        },
                        outputs: []outputInfo{
-                               {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+                               {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
                        },
                },
        },
        {
-               name:    "ADDI",
-               auxType: auxInt64,
-               argLen:  1,
-               asm:     riscv.AADDI,
+               name:   "FSQRTS",
+               argLen: 1,
+               asm:    ppc64.AFSQRTS,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB
+                               {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
                        },
                        outputs: []outputInfo{
-                               {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+                               {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
                        },
                },
        },
        {
-               name:    "ADDIW",
-               auxType: auxInt64,
-               argLen:  1,
-               asm:     riscv.AADDIW,
+               name:   "FFLOOR",
+               argLen: 1,
+               asm:    ppc64.AFRIM,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+                               {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
                        },
                        outputs: []outputInfo{
-                               {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+                               {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
                        },
                },
        },
        {
-               name:   "NEG",
+               name:   "FCEIL",
                argLen: 1,
-               asm:    riscv.ANEG,
+               asm:    ppc64.AFRIP,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+                               {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
                        },
                        outputs: []outputInfo{
-                               {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+                               {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
                        },
                },
        },
        {
-               name:   "NEGW",
+               name:   "FTRUNC",
                argLen: 1,
-               asm:    riscv.ANEGW,
+               asm:    ppc64.AFRIZ,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+                               {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
                        },
                        outputs: []outputInfo{
-                               {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+                               {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
                        },
                },
        },
        {
-               name:   "SUB",
-               argLen: 2,
-               asm:    riscv.ASUB,
+               name:   "FROUND",
+               argLen: 1,
+               asm:    ppc64.AFRIN,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
-                               {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+                               {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
                        },
                        outputs: []outputInfo{
-                               {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+                               {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
                        },
                },
        },
        {
-               name:   "SUBW",
-               argLen: 2,
-               asm:    riscv.ASUBW,
+               name:   "FABS",
+               argLen: 1,
+               asm:    ppc64.AFABS,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
-                               {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+                               {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
                        },
                        outputs: []outputInfo{
-                               {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+                               {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
                        },
                },
        },
        {
-               name:        "MUL",
-               argLen:      2,
-               commutative: true,
-               asm:         riscv.AMUL,
+               name:   "FNABS",
+               argLen: 1,
+               asm:    ppc64.AFNABS,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
-                               {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+                               {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
                        },
                        outputs: []outputInfo{
-                               {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+                               {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
                        },
                },
        },
        {
-               name:        "MULW",
-               argLen:      2,
-               commutative: true,
-               asm:         riscv.AMULW,
+               name:   "FCPSGN",
+               argLen: 2,
+               asm:    ppc64.AFCPSGN,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
-                               {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+                               {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
+                               {1, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
                        },
                        outputs: []outputInfo{
-                               {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+                               {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
                        },
                },
        },
        {
-               name:        "MULH",
-               argLen:      2,
-               commutative: true,
-               asm:         riscv.AMULH,
+               name:    "ORconst",
+               auxType: auxInt64,
+               argLen:  1,
+               asm:     ppc64.AOR,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
-                               {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+                               {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
                        },
                        outputs: []outputInfo{
-                               {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+                               {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
                        },
                },
        },
        {
-               name:        "MULHU",
-               argLen:      2,
-               commutative: true,
-               asm:         riscv.AMULHU,
+               name:    "XORconst",
+               auxType: auxInt64,
+               argLen:  1,
+               asm:     ppc64.AXOR,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
-                               {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+                               {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
                        },
                        outputs: []outputInfo{
-                               {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+                               {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
                        },
                },
        },
        {
-               name:            "LoweredMuluhilo",
-               argLen:          2,
-               resultNotInArgs: true,
+               name:    "ANDCCconst",
+               auxType: auxInt64,
+               argLen:  1,
+               asm:     ppc64.AANDCC,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
-                               {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+                               {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
                        },
                        outputs: []outputInfo{
-                               {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
-                               {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+                               {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
                        },
                },
        },
        {
-               name:            "LoweredMuluover",
-               argLen:          2,
-               resultNotInArgs: true,
+               name:         "ANDconst",
+               auxType:      auxInt64,
+               argLen:       1,
+               clobberFlags: true,
+               asm:          ppc64.AANDCC,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
-                               {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+                               {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
                        },
                        outputs: []outputInfo{
-                               {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
-                               {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+                               {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
                        },
                },
        },
        {
-               name:   "DIV",
-               argLen: 2,
-               asm:    riscv.ADIV,
+               name:   "MOVBreg",
+               argLen: 1,
+               asm:    ppc64.AMOVB,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
-                               {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+                               {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
                        },
                        outputs: []outputInfo{
-                               {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+                               {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
                        },
                },
        },
        {
-               name:   "DIVU",
-               argLen: 2,
-               asm:    riscv.ADIVU,
+               name:   "MOVBZreg",
+               argLen: 1,
+               asm:    ppc64.AMOVBZ,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
-                               {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+                               {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
                        },
                        outputs: []outputInfo{
-                               {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+                               {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
                        },
                },
        },
        {
-               name:   "DIVW",
-               argLen: 2,
-               asm:    riscv.ADIVW,
+               name:   "MOVHreg",
+               argLen: 1,
+               asm:    ppc64.AMOVH,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
-                               {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+                               {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
                        },
                        outputs: []outputInfo{
-                               {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+                               {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
                        },
                },
        },
        {
-               name:   "DIVUW",
-               argLen: 2,
-               asm:    riscv.ADIVUW,
+               name:   "MOVHZreg",
+               argLen: 1,
+               asm:    ppc64.AMOVHZ,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
-                               {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+                               {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
                        },
                        outputs: []outputInfo{
-                               {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+                               {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
                        },
                },
        },
        {
-               name:   "REM",
-               argLen: 2,
-               asm:    riscv.AREM,
+               name:   "MOVWreg",
+               argLen: 1,
+               asm:    ppc64.AMOVW,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
-                               {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+                               {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
                        },
                        outputs: []outputInfo{
-                               {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+                               {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
                        },
                },
        },
        {
-               name:   "REMU",
-               argLen: 2,
-               asm:    riscv.AREMU,
+               name:   "MOVWZreg",
+               argLen: 1,
+               asm:    ppc64.AMOVWZ,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
-                               {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+                               {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
                        },
                        outputs: []outputInfo{
-                               {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+                               {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
                        },
                },
        },
        {
-               name:   "REMW",
-               argLen: 2,
-               asm:    riscv.AREMW,
+               name:           "MOVBZload",
+               auxType:        auxSymOff,
+               argLen:         2,
+               faultOnNilArg0: true,
+               symEffect:      SymRead,
+               asm:            ppc64.AMOVBZ,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
-                               {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+                               {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
                        },
                        outputs: []outputInfo{
-                               {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+                               {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
                        },
                },
        },
        {
-               name:   "REMUW",
-               argLen: 2,
-               asm:    riscv.AREMUW,
+               name:           "MOVHload",
+               auxType:        auxSymOff,
+               argLen:         2,
+               faultOnNilArg0: true,
+               symEffect:      SymRead,
+               asm:            ppc64.AMOVH,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
-                               {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+                               {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
                        },
                        outputs: []outputInfo{
-                               {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+                               {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
                        },
                },
        },
        {
-               name:              "MOVaddr",
-               auxType:           auxSymOff,
-               argLen:            1,
-               rematerializeable: true,
-               symEffect:         SymAddr,
-               asm:               riscv.AMOV,
+               name:           "MOVHZload",
+               auxType:        auxSymOff,
+               argLen:         2,
+               faultOnNilArg0: true,
+               symEffect:      SymRead,
+               asm:            ppc64.AMOVHZ,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB
-                       },
-                       outputs: []outputInfo{
-                               {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+                               {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
                        },
-               },
-       },
-       {
-               name:              "MOVDconst",
-               auxType:           auxInt64,
-               argLen:            0,
-               rematerializeable: true,
-               asm:               riscv.AMOV,
-               reg: regInfo{
                        outputs: []outputInfo{
-                               {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+                               {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
                        },
                },
        },
        {
-               name:           "MOVBload",
+               name:           "MOVWload",
                auxType:        auxSymOff,
                argLen:         2,
                faultOnNilArg0: true,
                symEffect:      SymRead,
-               asm:            riscv.AMOVB,
+               asm:            ppc64.AMOVW,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB
+                               {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
                        },
                        outputs: []outputInfo{
-                               {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+                               {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
                        },
                },
        },
        {
-               name:           "MOVHload",
+               name:           "MOVWZload",
                auxType:        auxSymOff,
                argLen:         2,
                faultOnNilArg0: true,
                symEffect:      SymRead,
-               asm:            riscv.AMOVH,
+               asm:            ppc64.AMOVWZ,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB
+                               {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
                        },
                        outputs: []outputInfo{
-                               {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+                               {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
                        },
                },
        },
        {
-               name:           "MOVWload",
+               name:           "MOVDload",
                auxType:        auxSymOff,
                argLen:         2,
                faultOnNilArg0: true,
                symEffect:      SymRead,
-               asm:            riscv.AMOVW,
+               asm:            ppc64.AMOVD,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB
+                               {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
                        },
                        outputs: []outputInfo{
-                               {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+                               {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
                        },
                },
        },
        {
-               name:           "MOVDload",
-               auxType:        auxSymOff,
+               name:           "MOVDBRload",
                argLen:         2,
                faultOnNilArg0: true,
-               symEffect:      SymRead,
-               asm:            riscv.AMOV,
+               asm:            ppc64.AMOVDBR,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB
+                               {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
                        },
                        outputs: []outputInfo{
-                               {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+                               {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
                        },
                },
        },
        {
-               name:           "MOVBUload",
-               auxType:        auxSymOff,
+               name:           "MOVWBRload",
                argLen:         2,
                faultOnNilArg0: true,
-               symEffect:      SymRead,
-               asm:            riscv.AMOVBU,
+               asm:            ppc64.AMOVWBR,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB
+                               {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
                        },
                        outputs: []outputInfo{
-                               {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+                               {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
                        },
                },
        },
        {
-               name:           "MOVHUload",
-               auxType:        auxSymOff,
+               name:           "MOVHBRload",
                argLen:         2,
                faultOnNilArg0: true,
-               symEffect:      SymRead,
-               asm:            riscv.AMOVHU,
+               asm:            ppc64.AMOVHBR,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB
+                               {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
                        },
                        outputs: []outputInfo{
-                               {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+                               {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
                        },
                },
        },
        {
-               name:           "MOVWUload",
-               auxType:        auxSymOff,
-               argLen:         2,
-               faultOnNilArg0: true,
-               symEffect:      SymRead,
-               asm:            riscv.AMOVWU,
+               name:   "MOVBZloadidx",
+               argLen: 3,
+               asm:    ppc64.AMOVBZ,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB
+                               {1, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+                               {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
                        },
                        outputs: []outputInfo{
-                               {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+                               {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
                        },
                },
        },
        {
-               name:           "MOVBstore",
-               auxType:        auxSymOff,
-               argLen:         3,
-               faultOnNilArg0: true,
-               symEffect:      SymWrite,
-               asm:            riscv.AMOVB,
+               name:   "MOVHloadidx",
+               argLen: 3,
+               asm:    ppc64.AMOVH,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {1, 1006632946},          // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
-                               {0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB
+                               {1, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+                               {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
                        },
-               },
-       },
-       {
-               name:           "MOVHstore",
-               auxType:        auxSymOff,
-               argLen:         3,
-               faultOnNilArg0: true,
-               symEffect:      SymWrite,
-               asm:            riscv.AMOVH,
-               reg: regInfo{
-                       inputs: []inputInfo{
-                               {1, 1006632946},          // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
-                               {0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB
+                       outputs: []outputInfo{
+                               {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
                        },
                },
        },
        {
-               name:           "MOVWstore",
-               auxType:        auxSymOff,
-               argLen:         3,
-               faultOnNilArg0: true,
-               symEffect:      SymWrite,
-               asm:            riscv.AMOVW,
+               name:   "MOVHZloadidx",
+               argLen: 3,
+               asm:    ppc64.AMOVHZ,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {1, 1006632946},          // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
-                               {0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB
+                               {1, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+                               {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
                        },
-               },
-       },
-       {
-               name:           "MOVDstore",
-               auxType:        auxSymOff,
-               argLen:         3,
-               faultOnNilArg0: true,
-               symEffect:      SymWrite,
-               asm:            riscv.AMOV,
-               reg: regInfo{
-                       inputs: []inputInfo{
-                               {1, 1006632946},          // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
-                               {0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB
+                       outputs: []outputInfo{
+                               {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
                        },
                },
        },
        {
-               name:           "MOVBstorezero",
-               auxType:        auxSymOff,
-               argLen:         2,
-               faultOnNilArg0: true,
-               symEffect:      SymWrite,
-               asm:            riscv.AMOVB,
+               name:   "MOVWloadidx",
+               argLen: 3,
+               asm:    ppc64.AMOVW,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB
+                               {1, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+                               {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
                        },
-               },
-       },
-       {
-               name:           "MOVHstorezero",
-               auxType:        auxSymOff,
-               argLen:         2,
-               faultOnNilArg0: true,
-               symEffect:      SymWrite,
-               asm:            riscv.AMOVH,
-               reg: regInfo{
-                       inputs: []inputInfo{
-                               {0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB
+                       outputs: []outputInfo{
+                               {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
                        },
                },
        },
        {
-               name:           "MOVWstorezero",
-               auxType:        auxSymOff,
-               argLen:         2,
-               faultOnNilArg0: true,
-               symEffect:      SymWrite,
-               asm:            riscv.AMOVW,
+               name:   "MOVWZloadidx",
+               argLen: 3,
+               asm:    ppc64.AMOVWZ,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB
+                               {1, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+                               {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
                        },
-               },
-       },
-       {
-               name:           "MOVDstorezero",
-               auxType:        auxSymOff,
-               argLen:         2,
-               faultOnNilArg0: true,
-               symEffect:      SymWrite,
-               asm:            riscv.AMOV,
-               reg: regInfo{
-                       inputs: []inputInfo{
-                               {0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB
+                       outputs: []outputInfo{
+                               {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
                        },
                },
        },
        {
-               name:   "MOVBreg",
-               argLen: 1,
-               asm:    riscv.AMOVB,
+               name:   "MOVDloadidx",
+               argLen: 3,
+               asm:    ppc64.AMOVD,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+                               {1, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+                               {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
                        },
                        outputs: []outputInfo{
-                               {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+                               {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
                        },
                },
        },
        {
-               name:   "MOVHreg",
-               argLen: 1,
-               asm:    riscv.AMOVH,
+               name:   "MOVHBRloadidx",
+               argLen: 3,
+               asm:    ppc64.AMOVHBR,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+                               {1, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+                               {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
                        },
                        outputs: []outputInfo{
-                               {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+                               {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
                        },
                },
        },
        {
-               name:   "MOVWreg",
-               argLen: 1,
-               asm:    riscv.AMOVW,
+               name:   "MOVWBRloadidx",
+               argLen: 3,
+               asm:    ppc64.AMOVWBR,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+                               {1, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+                               {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
                        },
                        outputs: []outputInfo{
-                               {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+                               {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
                        },
                },
        },
        {
-               name:   "MOVDreg",
-               argLen: 1,
-               asm:    riscv.AMOV,
+               name:   "MOVDBRloadidx",
+               argLen: 3,
+               asm:    ppc64.AMOVDBR,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+                               {1, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+                               {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
                        },
                        outputs: []outputInfo{
-                               {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+                               {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
                        },
                },
        },
        {
-               name:   "MOVBUreg",
-               argLen: 1,
-               asm:    riscv.AMOVBU,
+               name:   "FMOVDloadidx",
+               argLen: 3,
+               asm:    ppc64.AFMOVD,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+                               {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+                               {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
                        },
                        outputs: []outputInfo{
-                               {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+                               {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
                        },
                },
        },
        {
-               name:   "MOVHUreg",
-               argLen: 1,
-               asm:    riscv.AMOVHU,
+               name:   "FMOVSloadidx",
+               argLen: 3,
+               asm:    ppc64.AFMOVS,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+                               {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+                               {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
                        },
                        outputs: []outputInfo{
-                               {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+                               {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
                        },
                },
        },
        {
-               name:   "MOVWUreg",
-               argLen: 1,
-               asm:    riscv.AMOVWU,
+               name:           "DCBT",
+               auxType:        auxInt64,
+               argLen:         2,
+               hasSideEffects: true,
+               asm:            ppc64.ADCBT,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
-                       },
-                       outputs: []outputInfo{
-                               {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+                               {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
                        },
                },
        },
        {
-               name:         "MOVDnop",
-               argLen:       1,
-               resultInArg0: true,
+               name:           "MOVDBRstore",
+               argLen:         3,
+               faultOnNilArg0: true,
+               asm:            ppc64.AMOVDBR,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
-                       },
-                       outputs: []outputInfo{
-                               {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+                               {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+                               {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
                        },
                },
        },
        {
-               name:   "SLL",
-               argLen: 2,
-               asm:    riscv.ASLL,
+               name:           "MOVWBRstore",
+               argLen:         3,
+               faultOnNilArg0: true,
+               asm:            ppc64.AMOVWBR,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
-                               {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
-                       },
-                       outputs: []outputInfo{
-                               {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+                               {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+                               {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
                        },
                },
        },
        {
-               name:   "SLLW",
-               argLen: 2,
-               asm:    riscv.ASLLW,
+               name:           "MOVHBRstore",
+               argLen:         3,
+               faultOnNilArg0: true,
+               asm:            ppc64.AMOVHBR,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
-                               {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
-                       },
-                       outputs: []outputInfo{
-                               {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+                               {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+                               {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
                        },
                },
        },
        {
-               name:   "SRA",
-               argLen: 2,
-               asm:    riscv.ASRA,
+               name:           "FMOVDload",
+               auxType:        auxSymOff,
+               argLen:         2,
+               faultOnNilArg0: true,
+               symEffect:      SymRead,
+               asm:            ppc64.AFMOVD,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
-                               {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+                               {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
                        },
                        outputs: []outputInfo{
-                               {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+                               {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
                        },
                },
        },
        {
-               name:   "SRAW",
-               argLen: 2,
-               asm:    riscv.ASRAW,
+               name:           "FMOVSload",
+               auxType:        auxSymOff,
+               argLen:         2,
+               faultOnNilArg0: true,
+               symEffect:      SymRead,
+               asm:            ppc64.AFMOVS,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
-                               {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+                               {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
                        },
                        outputs: []outputInfo{
-                               {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+                               {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
                        },
                },
        },
        {
-               name:   "SRL",
-               argLen: 2,
-               asm:    riscv.ASRL,
+               name:           "MOVBstore",
+               auxType:        auxSymOff,
+               argLen:         3,
+               faultOnNilArg0: true,
+               symEffect:      SymWrite,
+               asm:            ppc64.AMOVB,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
-                               {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
-                       },
-                       outputs: []outputInfo{
-                               {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+                               {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+                               {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
                        },
                },
        },
        {
-               name:   "SRLW",
-               argLen: 2,
-               asm:    riscv.ASRLW,
+               name:           "MOVHstore",
+               auxType:        auxSymOff,
+               argLen:         3,
+               faultOnNilArg0: true,
+               symEffect:      SymWrite,
+               asm:            ppc64.AMOVH,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
-                               {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
-                       },
-                       outputs: []outputInfo{
-                               {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+                               {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+                               {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
                        },
                },
        },
        {
-               name:    "SLLI",
-               auxType: auxInt64,
-               argLen:  1,
-               asm:     riscv.ASLLI,
+               name:           "MOVWstore",
+               auxType:        auxSymOff,
+               argLen:         3,
+               faultOnNilArg0: true,
+               symEffect:      SymWrite,
+               asm:            ppc64.AMOVW,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
-                       },
-                       outputs: []outputInfo{
-                               {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+                               {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+                               {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
                        },
                },
        },
        {
-               name:    "SLLIW",
-               auxType: auxInt64,
-               argLen:  1,
-               asm:     riscv.ASLLIW,
+               name:           "MOVDstore",
+               auxType:        auxSymOff,
+               argLen:         3,
+               faultOnNilArg0: true,
+               symEffect:      SymWrite,
+               asm:            ppc64.AMOVD,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
-                       },
-                       outputs: []outputInfo{
-                               {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+                               {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+                               {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
                        },
                },
        },
        {
-               name:    "SRAI",
-               auxType: auxInt64,
-               argLen:  1,
-               asm:     riscv.ASRAI,
+               name:           "FMOVDstore",
+               auxType:        auxSymOff,
+               argLen:         3,
+               faultOnNilArg0: true,
+               symEffect:      SymWrite,
+               asm:            ppc64.AFMOVD,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
-                       },
-                       outputs: []outputInfo{
-                               {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+                               {0, 1073733630},          // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+                               {1, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
                        },
                },
        },
        {
-               name:    "SRAIW",
-               auxType: auxInt64,
-               argLen:  1,
-               asm:     riscv.ASRAIW,
+               name:           "FMOVSstore",
+               auxType:        auxSymOff,
+               argLen:         3,
+               faultOnNilArg0: true,
+               symEffect:      SymWrite,
+               asm:            ppc64.AFMOVS,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
-                       },
-                       outputs: []outputInfo{
-                               {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+                               {0, 1073733630},          // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+                               {1, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
                        },
                },
        },
        {
-               name:    "SRLI",
-               auxType: auxInt64,
-               argLen:  1,
-               asm:     riscv.ASRLI,
+               name:   "MOVBstoreidx",
+               argLen: 4,
+               asm:    ppc64.AMOVB,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
-                       },
-                       outputs: []outputInfo{
-                               {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+                               {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+                               {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+                               {2, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
                        },
                },
        },
        {
-               name:    "SRLIW",
-               auxType: auxInt64,
-               argLen:  1,
-               asm:     riscv.ASRLIW,
+               name:   "MOVHstoreidx",
+               argLen: 4,
+               asm:    ppc64.AMOVH,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
-                       },
-                       outputs: []outputInfo{
-                               {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+                               {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+                               {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+                               {2, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
                        },
                },
        },
        {
-               name:   "SH1ADD",
-               argLen: 2,
-               asm:    riscv.ASH1ADD,
+               name:   "MOVWstoreidx",
+               argLen: 4,
+               asm:    ppc64.AMOVW,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
-                               {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
-                       },
-                       outputs: []outputInfo{
-                               {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+                               {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+                               {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+                               {2, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
                        },
                },
        },
        {
-               name:   "SH2ADD",
-               argLen: 2,
-               asm:    riscv.ASH2ADD,
+               name:   "MOVDstoreidx",
+               argLen: 4,
+               asm:    ppc64.AMOVD,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
-                               {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
-                       },
-                       outputs: []outputInfo{
-                               {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+                               {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+                               {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+                               {2, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
                        },
                },
        },
        {
-               name:   "SH3ADD",
-               argLen: 2,
-               asm:    riscv.ASH3ADD,
+               name:   "FMOVDstoreidx",
+               argLen: 4,
+               asm:    ppc64.AFMOVD,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
-                               {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
-                       },
-                       outputs: []outputInfo{
-                               {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+                               {0, 1073733630},          // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+                               {1, 1073733630},          // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+                               {2, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
                        },
                },
        },
        {
-               name:        "AND",
-               argLen:      2,
-               commutative: true,
-               asm:         riscv.AAND,
+               name:   "FMOVSstoreidx",
+               argLen: 4,
+               asm:    ppc64.AFMOVS,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
-                               {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
-                       },
-                       outputs: []outputInfo{
-                               {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+                               {0, 1073733630},          // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+                               {1, 1073733630},          // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+                               {2, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
                        },
                },
        },
        {
-               name:   "ANDN",
-               argLen: 2,
-               asm:    riscv.AANDN,
+               name:   "MOVHBRstoreidx",
+               argLen: 4,
+               asm:    ppc64.AMOVHBR,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
-                               {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
-                       },
-                       outputs: []outputInfo{
-                               {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+                               {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+                               {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+                               {2, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
                        },
                },
        },
        {
-               name:    "ANDI",
-               auxType: auxInt64,
-               argLen:  1,
-               asm:     riscv.AANDI,
+               name:   "MOVWBRstoreidx",
+               argLen: 4,
+               asm:    ppc64.AMOVWBR,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
-                       },
-                       outputs: []outputInfo{
-                               {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+                               {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+                               {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+                               {2, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
                        },
                },
        },
        {
-               name:   "CLZ",
-               argLen: 1,
-               asm:    riscv.ACLZ,
+               name:   "MOVDBRstoreidx",
+               argLen: 4,
+               asm:    ppc64.AMOVDBR,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
-                       },
-                       outputs: []outputInfo{
-                               {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+                               {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+                               {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+                               {2, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
                        },
                },
        },
        {
-               name:   "CLZW",
-               argLen: 1,
-               asm:    riscv.ACLZW,
+               name:           "MOVBstorezero",
+               auxType:        auxSymOff,
+               argLen:         2,
+               faultOnNilArg0: true,
+               symEffect:      SymWrite,
+               asm:            ppc64.AMOVB,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
-                       },
-                       outputs: []outputInfo{
-                               {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+                               {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
                        },
                },
        },
        {
-               name:   "CPOP",
-               argLen: 1,
-               asm:    riscv.ACPOP,
+               name:           "MOVHstorezero",
+               auxType:        auxSymOff,
+               argLen:         2,
+               faultOnNilArg0: true,
+               symEffect:      SymWrite,
+               asm:            ppc64.AMOVH,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
-                       },
-                       outputs: []outputInfo{
-                               {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+                               {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
                        },
                },
        },
        {
-               name:   "CPOPW",
-               argLen: 1,
-               asm:    riscv.ACPOPW,
+               name:           "MOVWstorezero",
+               auxType:        auxSymOff,
+               argLen:         2,
+               faultOnNilArg0: true,
+               symEffect:      SymWrite,
+               asm:            ppc64.AMOVW,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
-                       },
-                       outputs: []outputInfo{
-                               {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+                               {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
                        },
                },
        },
        {
-               name:   "CTZ",
-               argLen: 1,
-               asm:    riscv.ACTZ,
+               name:           "MOVDstorezero",
+               auxType:        auxSymOff,
+               argLen:         2,
+               faultOnNilArg0: true,
+               symEffect:      SymWrite,
+               asm:            ppc64.AMOVD,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
-                       },
-                       outputs: []outputInfo{
-                               {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+                               {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
                        },
                },
        },
        {
-               name:   "CTZW",
-               argLen: 1,
-               asm:    riscv.ACTZW,
+               name:              "MOVDaddr",
+               auxType:           auxSymOff,
+               argLen:            1,
+               rematerializeable: true,
+               symEffect:         SymAddr,
+               asm:               ppc64.AMOVD,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+                               {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
                        },
                        outputs: []outputInfo{
-                               {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+                               {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
                        },
                },
        },
        {
-               name:   "NOT",
-               argLen: 1,
-               asm:    riscv.ANOT,
+               name:              "MOVDconst",
+               auxType:           auxInt64,
+               argLen:            0,
+               rematerializeable: true,
+               asm:               ppc64.AMOVD,
                reg: regInfo{
-                       inputs: []inputInfo{
-                               {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
-                       },
                        outputs: []outputInfo{
-                               {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+                               {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
                        },
                },
        },
        {
-               name:        "OR",
-               argLen:      2,
-               commutative: true,
-               asm:         riscv.AOR,
+               name:              "FMOVDconst",
+               auxType:           auxFloat64,
+               argLen:            0,
+               rematerializeable: true,
+               asm:               ppc64.AFMOVD,
                reg: regInfo{
-                       inputs: []inputInfo{
-                               {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
-                               {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
-                       },
                        outputs: []outputInfo{
-                               {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+                               {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
                        },
                },
        },
        {
-               name:   "ORN",
-               argLen: 2,
-               asm:    riscv.AORN,
+               name:              "FMOVSconst",
+               auxType:           auxFloat32,
+               argLen:            0,
+               rematerializeable: true,
+               asm:               ppc64.AFMOVS,
                reg: regInfo{
-                       inputs: []inputInfo{
-                               {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
-                               {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
-                       },
                        outputs: []outputInfo{
-                               {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+                               {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
                        },
                },
        },
        {
-               name:    "ORI",
-               auxType: auxInt64,
-               argLen:  1,
-               asm:     riscv.AORI,
+               name:   "FCMPU",
+               argLen: 2,
+               asm:    ppc64.AFCMPU,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
-                       },
-                       outputs: []outputInfo{
-                               {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+                               {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
+                               {1, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
                        },
                },
        },
        {
-               name:   "REV8",
-               argLen: 1,
-               asm:    riscv.AREV8,
+               name:   "CMP",
+               argLen: 2,
+               asm:    ppc64.ACMP,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
-                       },
-                       outputs: []outputInfo{
-                               {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+                               {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+                               {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
                        },
                },
        },
        {
-               name:   "ROL",
+               name:   "CMPU",
                argLen: 2,
-               asm:    riscv.AROL,
+               asm:    ppc64.ACMPU,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
-                               {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
-                       },
-                       outputs: []outputInfo{
-                               {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+                               {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+                               {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
                        },
                },
        },
        {
-               name:   "ROLW",
+               name:   "CMPW",
                argLen: 2,
-               asm:    riscv.AROLW,
+               asm:    ppc64.ACMPW,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
-                               {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
-                       },
-                       outputs: []outputInfo{
-                               {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+                               {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+                               {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
                        },
                },
        },
        {
-               name:   "ROR",
+               name:   "CMPWU",
                argLen: 2,
-               asm:    riscv.AROR,
+               asm:    ppc64.ACMPWU,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
-                               {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
-                       },
-                       outputs: []outputInfo{
-                               {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+                               {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+                               {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
                        },
                },
        },
        {
-               name:    "RORI",
+               name:    "CMPconst",
                auxType: auxInt64,
                argLen:  1,
-               asm:     riscv.ARORI,
+               asm:     ppc64.ACMP,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
-                       },
-                       outputs: []outputInfo{
-                               {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+                               {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
                        },
                },
        },
        {
-               name:    "RORIW",
+               name:    "CMPUconst",
                auxType: auxInt64,
                argLen:  1,
-               asm:     riscv.ARORIW,
+               asm:     ppc64.ACMPU,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
-                       },
-                       outputs: []outputInfo{
-                               {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+                               {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
                        },
                },
        },
        {
-               name:   "RORW",
-               argLen: 2,
-               asm:    riscv.ARORW,
+               name:    "CMPWconst",
+               auxType: auxInt32,
+               argLen:  1,
+               asm:     ppc64.ACMPW,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
-                               {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+                               {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
                        },
-                       outputs: []outputInfo{
-                               {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+               },
+       },
+       {
+               name:    "CMPWUconst",
+               auxType: auxInt32,
+               argLen:  1,
+               asm:     ppc64.ACMPWU,
+               reg: regInfo{
+                       inputs: []inputInfo{
+                               {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
                        },
                },
        },
        {
-               name:        "XNOR",
-               argLen:      2,
-               commutative: true,
-               asm:         riscv.AXNOR,
+               name:    "ISEL",
+               auxType: auxInt32,
+               argLen:  3,
+               asm:     ppc64.AISEL,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
-                               {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+                               {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+                               {1, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
                        },
                        outputs: []outputInfo{
-                               {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+                               {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
                        },
                },
        },
        {
-               name:        "XOR",
-               argLen:      2,
-               commutative: true,
-               asm:         riscv.AXOR,
+               name:    "ISELZ",
+               auxType: auxInt32,
+               argLen:  2,
+               asm:     ppc64.AISEL,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
-                               {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+                               {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
                        },
                        outputs: []outputInfo{
-                               {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+                               {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
                        },
                },
        },
        {
-               name:    "XORI",
-               auxType: auxInt64,
+               name:    "SETBC",
+               auxType: auxInt32,
                argLen:  1,
-               asm:     riscv.AXORI,
+               asm:     ppc64.ASETBC,
                reg: regInfo{
-                       inputs: []inputInfo{
-                               {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
-                       },
                        outputs: []outputInfo{
-                               {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+                               {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
                        },
                },
        },
        {
-               name:        "MIN",
-               argLen:      2,
-               commutative: true,
-               asm:         riscv.AMIN,
+               name:    "SETBCR",
+               auxType: auxInt32,
+               argLen:  1,
+               asm:     ppc64.ASETBCR,
                reg: regInfo{
-                       inputs: []inputInfo{
-                               {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
-                               {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
-                       },
                        outputs: []outputInfo{
-                               {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+                               {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
                        },
                },
        },
        {
-               name:        "MAX",
-               argLen:      2,
-               commutative: true,
-               asm:         riscv.AMAX,
+               name:   "Equal",
+               argLen: 1,
                reg: regInfo{
-                       inputs: []inputInfo{
-                               {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
-                               {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
-                       },
                        outputs: []outputInfo{
-                               {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+                               {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
                        },
                },
        },
        {
-               name:        "MINU",
-               argLen:      2,
-               commutative: true,
-               asm:         riscv.AMINU,
+               name:   "NotEqual",
+               argLen: 1,
                reg: regInfo{
-                       inputs: []inputInfo{
-                               {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
-                               {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
-                       },
                        outputs: []outputInfo{
-                               {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+                               {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
                        },
                },
        },
        {
-               name:        "MAXU",
-               argLen:      2,
-               commutative: true,
-               asm:         riscv.AMAXU,
+               name:   "LessThan",
+               argLen: 1,
                reg: regInfo{
-                       inputs: []inputInfo{
-                               {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
-                               {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
-                       },
                        outputs: []outputInfo{
-                               {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+                               {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
                        },
                },
        },
        {
-               name:   "SEQZ",
+               name:   "FLessThan",
                argLen: 1,
-               asm:    riscv.ASEQZ,
                reg: regInfo{
-                       inputs: []inputInfo{
-                               {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+                       outputs: []outputInfo{
+                               {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
                        },
+               },
+       },
+       {
+               name:   "LessEqual",
+               argLen: 1,
+               reg: regInfo{
                        outputs: []outputInfo{
-                               {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+                               {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
                        },
                },
        },
        {
-               name:   "SNEZ",
+               name:   "FLessEqual",
                argLen: 1,
-               asm:    riscv.ASNEZ,
                reg: regInfo{
-                       inputs: []inputInfo{
-                               {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+                       outputs: []outputInfo{
+                               {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
                        },
+               },
+       },
+       {
+               name:   "GreaterThan",
+               argLen: 1,
+               reg: regInfo{
                        outputs: []outputInfo{
-                               {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+                               {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
                        },
                },
        },
        {
-               name:   "SLT",
-               argLen: 2,
-               asm:    riscv.ASLT,
+               name:   "FGreaterThan",
+               argLen: 1,
                reg: regInfo{
-                       inputs: []inputInfo{
-                               {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
-                               {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+                       outputs: []outputInfo{
+                               {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
                        },
+               },
+       },
+       {
+               name:   "GreaterEqual",
+               argLen: 1,
+               reg: regInfo{
                        outputs: []outputInfo{
-                               {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+                               {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
                        },
                },
        },
        {
-               name:    "SLTI",
-               auxType: auxInt64,
-               argLen:  1,
-               asm:     riscv.ASLTI,
+               name:   "FGreaterEqual",
+               argLen: 1,
                reg: regInfo{
-                       inputs: []inputInfo{
-                               {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+                       outputs: []outputInfo{
+                               {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
                        },
+               },
+       },
+       {
+               name:      "LoweredGetClosurePtr",
+               argLen:    0,
+               zeroWidth: true,
+               reg: regInfo{
                        outputs: []outputInfo{
-                               {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+                               {0, 2048}, // R11
                        },
                },
        },
        {
-               name:   "SLTU",
-               argLen: 2,
-               asm:    riscv.ASLTU,
+               name:              "LoweredGetCallerSP",
+               argLen:            1,
+               rematerializeable: true,
                reg: regInfo{
-                       inputs: []inputInfo{
-                               {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
-                               {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+                       outputs: []outputInfo{
+                               {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
                        },
+               },
+       },
+       {
+               name:              "LoweredGetCallerPC",
+               argLen:            0,
+               rematerializeable: true,
+               reg: regInfo{
                        outputs: []outputInfo{
-                               {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+                               {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
                        },
                },
        },
        {
-               name:    "SLTIU",
-               auxType: auxInt64,
-               argLen:  1,
-               asm:     riscv.ASLTIU,
+               name:           "LoweredNilCheck",
+               argLen:         2,
+               clobberFlags:   true,
+               nilCheck:       true,
+               faultOnNilArg0: true,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
-                       },
-                       outputs: []outputInfo{
-                               {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+                               {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
                        },
+                       clobbers: 2147483648, // R31
                },
        },
        {
                name:         "LoweredRound32F",
                argLen:       1,
                resultInArg0: true,
+               zeroWidth:    true,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
                        },
                        outputs: []outputInfo{
-                               {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
                        },
                },
        },
@@ -47428,353 +49232,447 @@ var opcodeTable = [...]opInfo{
                name:         "LoweredRound64F",
                argLen:       1,
                resultInArg0: true,
+               zeroWidth:    true,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
                        },
                        outputs: []outputInfo{
-                               {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
                        },
                },
        },
        {
-               name:    "CALLstatic",
-               auxType: auxCallOff,
-               argLen:  -1,
-               call:    true,
+               name:         "CALLstatic",
+               auxType:      auxCallOff,
+               argLen:       -1,
+               clobberFlags: true,
+               call:         true,
                reg: regInfo{
-                       clobbers: 9223372035781033968, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                       clobbers: 18446744071562059768, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 g F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 XER
                },
        },
        {
-               name:     "CALLtail",
-               auxType:  auxCallOff,
-               argLen:   -1,
-               call:     true,
-               tailCall: true,
+               name:         "CALLtail",
+               auxType:      auxCallOff,
+               argLen:       -1,
+               clobberFlags: true,
+               call:         true,
+               tailCall:     true,
                reg: regInfo{
-                       clobbers: 9223372035781033968, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                       clobbers: 18446744071562059768, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 g F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 XER
                },
        },
        {
-               name:    "CALLclosure",
-               auxType: auxCallOff,
-               argLen:  -1,
-               call:    true,
+               name:         "CALLclosure",
+               auxType:      auxCallOff,
+               argLen:       -1,
+               clobberFlags: true,
+               call:         true,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {1, 33554432},   // X26
-                               {0, 1006632946}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+                               {0, 4096}, // R12
+                               {1, 2048}, // R11
                        },
-                       clobbers: 9223372035781033968, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                       clobbers: 18446744071562059768, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 g F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 XER
                },
        },
        {
-               name:    "CALLinter",
-               auxType: auxCallOff,
-               argLen:  -1,
-               call:    true,
+               name:         "CALLinter",
+               auxType:      auxCallOff,
+               argLen:       -1,
+               clobberFlags: true,
+               call:         true,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+                               {0, 4096}, // R12
                        },
-                       clobbers: 9223372035781033968, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                       clobbers: 18446744071562059768, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 g F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 XER
                },
        },
        {
-               name:           "DUFFZERO",
+               name:           "LoweredZero",
                auxType:        auxInt64,
                argLen:         2,
+               clobberFlags:   true,
                faultOnNilArg0: true,
+               unsafePoint:    true,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 16777216}, // X25
+                               {0, 1048576}, // R20
                        },
-                       clobbers: 16777216, // X25
+                       clobbers: 1048576, // R20
                },
        },
        {
-               name:           "DUFFCOPY",
+               name:           "LoweredZeroShort",
                auxType:        auxInt64,
-               argLen:         3,
+               argLen:         2,
                faultOnNilArg0: true,
-               faultOnNilArg1: true,
+               unsafePoint:    true,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 16777216}, // X25
-                               {1, 8388608},  // X24
+                               {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
                        },
-                       clobbers: 25165824, // X24 X25
                },
        },
        {
-               name:           "LoweredZero",
+               name:           "LoweredQuadZeroShort",
                auxType:        auxInt64,
-               argLen:         3,
+               argLen:         2,
                faultOnNilArg0: true,
+               unsafePoint:    true,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 16},         // X5
-                               {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+                               {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
                        },
-                       clobbers: 16, // X5
                },
        },
        {
-               name:           "LoweredMove",
+               name:           "LoweredQuadZero",
                auxType:        auxInt64,
-               argLen:         4,
+               argLen:         2,
+               clobberFlags:   true,
                faultOnNilArg0: true,
-               faultOnNilArg1: true,
+               unsafePoint:    true,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 16},         // X5
-                               {1, 32},         // X6
-                               {2, 1006632880}, // X5 X6 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+                               {0, 1048576}, // R20
                        },
-                       clobbers: 112, // X5 X6 X7
+                       clobbers: 1048576, // R20
                },
        },
        {
-               name:           "LoweredAtomicLoad8",
-               argLen:         2,
+               name:           "LoweredMove",
+               auxType:        auxInt64,
+               argLen:         3,
+               clobberFlags:   true,
                faultOnNilArg0: true,
+               faultOnNilArg1: true,
+               unsafePoint:    true,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB
-                       },
-                       outputs: []outputInfo{
-                               {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+                               {0, 1048576}, // R20
+                               {1, 2097152}, // R21
                        },
+                       clobbers: 3145728, // R20 R21
                },
        },
        {
-               name:           "LoweredAtomicLoad32",
-               argLen:         2,
+               name:           "LoweredMoveShort",
+               auxType:        auxInt64,
+               argLen:         3,
                faultOnNilArg0: true,
+               faultOnNilArg1: true,
+               unsafePoint:    true,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB
-                       },
-                       outputs: []outputInfo{
-                               {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+                               {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+                               {1, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
                        },
                },
        },
        {
-               name:           "LoweredAtomicLoad64",
-               argLen:         2,
+               name:           "LoweredQuadMove",
+               auxType:        auxInt64,
+               argLen:         3,
+               clobberFlags:   true,
                faultOnNilArg0: true,
+               faultOnNilArg1: true,
+               unsafePoint:    true,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB
+                               {0, 1048576}, // R20
+                               {1, 2097152}, // R21
                        },
-                       outputs: []outputInfo{
-                               {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+                       clobbers: 3145728, // R20 R21
+               },
+       },
+       {
+               name:           "LoweredQuadMoveShort",
+               auxType:        auxInt64,
+               argLen:         3,
+               faultOnNilArg0: true,
+               faultOnNilArg1: true,
+               unsafePoint:    true,
+               reg: regInfo{
+                       inputs: []inputInfo{
+                               {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+                               {1, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
                        },
                },
        },
        {
                name:           "LoweredAtomicStore8",
+               auxType:        auxInt64,
                argLen:         3,
                faultOnNilArg0: true,
                hasSideEffects: true,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {1, 1006632946},          // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
-                               {0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB
+                               {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+                               {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
                        },
                },
        },
        {
                name:           "LoweredAtomicStore32",
+               auxType:        auxInt64,
                argLen:         3,
                faultOnNilArg0: true,
                hasSideEffects: true,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {1, 1006632946},          // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
-                               {0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB
+                               {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+                               {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
                        },
                },
        },
        {
                name:           "LoweredAtomicStore64",
+               auxType:        auxInt64,
                argLen:         3,
                faultOnNilArg0: true,
                hasSideEffects: true,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {1, 1006632946},          // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
-                               {0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB
+                               {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+                               {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
                        },
                },
        },
        {
-               name:            "LoweredAtomicExchange32",
+               name:           "LoweredAtomicLoad8",
+               auxType:        auxInt64,
+               argLen:         2,
+               clobberFlags:   true,
+               faultOnNilArg0: true,
+               reg: regInfo{
+                       inputs: []inputInfo{
+                               {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+                       },
+                       outputs: []outputInfo{
+                               {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+                       },
+               },
+       },
+       {
+               name:           "LoweredAtomicLoad32",
+               auxType:        auxInt64,
+               argLen:         2,
+               clobberFlags:   true,
+               faultOnNilArg0: true,
+               reg: regInfo{
+                       inputs: []inputInfo{
+                               {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+                       },
+                       outputs: []outputInfo{
+                               {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+                       },
+               },
+       },
+       {
+               name:           "LoweredAtomicLoad64",
+               auxType:        auxInt64,
+               argLen:         2,
+               clobberFlags:   true,
+               faultOnNilArg0: true,
+               reg: regInfo{
+                       inputs: []inputInfo{
+                               {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+                       },
+                       outputs: []outputInfo{
+                               {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+                       },
+               },
+       },
+       {
+               name:           "LoweredAtomicLoadPtr",
+               auxType:        auxInt64,
+               argLen:         2,
+               clobberFlags:   true,
+               faultOnNilArg0: true,
+               reg: regInfo{
+                       inputs: []inputInfo{
+                               {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+                       },
+                       outputs: []outputInfo{
+                               {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+                       },
+               },
+       },
+       {
+               name:            "LoweredAtomicAdd32",
                argLen:          3,
                resultNotInArgs: true,
+               clobberFlags:    true,
                faultOnNilArg0:  true,
                hasSideEffects:  true,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {1, 1073741808},          // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30
-                               {0, 9223372037928517618}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30 SB
+                               {1, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+                               {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
                        },
                        outputs: []outputInfo{
-                               {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+                               {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
                        },
                },
        },
        {
-               name:            "LoweredAtomicExchange64",
+               name:            "LoweredAtomicAdd64",
                argLen:          3,
                resultNotInArgs: true,
+               clobberFlags:    true,
                faultOnNilArg0:  true,
                hasSideEffects:  true,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {1, 1073741808},          // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30
-                               {0, 9223372037928517618}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30 SB
+                               {1, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+                               {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
                        },
                        outputs: []outputInfo{
-                               {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+                               {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
                        },
                },
        },
        {
-               name:            "LoweredAtomicAdd32",
+               name:            "LoweredAtomicExchange8",
                argLen:          3,
                resultNotInArgs: true,
+               clobberFlags:    true,
                faultOnNilArg0:  true,
                hasSideEffects:  true,
-               unsafePoint:     true,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {1, 1073741808},          // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30
-                               {0, 9223372037928517618}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30 SB
+                               {1, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+                               {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
                        },
                        outputs: []outputInfo{
-                               {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+                               {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
                        },
                },
        },
        {
-               name:            "LoweredAtomicAdd64",
+               name:            "LoweredAtomicExchange32",
                argLen:          3,
                resultNotInArgs: true,
+               clobberFlags:    true,
                faultOnNilArg0:  true,
                hasSideEffects:  true,
-               unsafePoint:     true,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {1, 1073741808},          // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30
-                               {0, 9223372037928517618}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30 SB
+                               {1, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+                               {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
                        },
                        outputs: []outputInfo{
-                               {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+                               {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
                        },
                },
        },
        {
-               name:            "LoweredAtomicCas32",
-               argLen:          4,
+               name:            "LoweredAtomicExchange64",
+               argLen:          3,
                resultNotInArgs: true,
+               clobberFlags:    true,
                faultOnNilArg0:  true,
                hasSideEffects:  true,
-               unsafePoint:     true,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {1, 1073741808},          // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30
-                               {2, 1073741808},          // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30
-                               {0, 9223372037928517618}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30 SB
+                               {1, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+                               {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
                        },
                        outputs: []outputInfo{
-                               {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+                               {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
                        },
                },
        },
        {
                name:            "LoweredAtomicCas64",
+               auxType:         auxInt64,
                argLen:          4,
                resultNotInArgs: true,
+               clobberFlags:    true,
                faultOnNilArg0:  true,
                hasSideEffects:  true,
-               unsafePoint:     true,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {1, 1073741808},          // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30
-                               {2, 1073741808},          // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30
-                               {0, 9223372037928517618}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30 SB
+                               {1, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+                               {2, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+                               {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
                        },
                        outputs: []outputInfo{
-                               {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+                               {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
                        },
                },
        },
        {
-               name:           "LoweredAtomicAnd32",
-               argLen:         3,
-               faultOnNilArg0: true,
-               hasSideEffects: true,
-               asm:            riscv.AAMOANDW,
+               name:            "LoweredAtomicCas32",
+               auxType:         auxInt64,
+               argLen:          4,
+               resultNotInArgs: true,
+               clobberFlags:    true,
+               faultOnNilArg0:  true,
+               hasSideEffects:  true,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {1, 1073741808},          // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30
-                               {0, 9223372037928517618}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30 SB
+                               {1, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+                               {2, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+                               {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+                       },
+                       outputs: []outputInfo{
+                               {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
                        },
                },
        },
        {
-               name:           "LoweredAtomicOr32",
+               name:           "LoweredAtomicAnd8",
                argLen:         3,
                faultOnNilArg0: true,
                hasSideEffects: true,
-               asm:            riscv.AAMOORW,
+               asm:            ppc64.AAND,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {1, 1073741808},          // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30
-                               {0, 9223372037928517618}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30 SB
+                               {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+                               {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
                        },
                },
        },
        {
-               name:           "LoweredNilCheck",
-               argLen:         2,
-               nilCheck:       true,
+               name:           "LoweredAtomicAnd32",
+               argLen:         3,
                faultOnNilArg0: true,
+               hasSideEffects: true,
+               asm:            ppc64.AAND,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 1006632946}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
-                       },
-               },
-       },
-       {
-               name:   "LoweredGetClosurePtr",
-               argLen: 0,
-               reg: regInfo{
-                       outputs: []outputInfo{
-                               {0, 33554432}, // X26
+                               {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+                               {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
                        },
                },
        },
        {
-               name:              "LoweredGetCallerSP",
-               argLen:            1,
-               rematerializeable: true,
+               name:           "LoweredAtomicOr8",
+               argLen:         3,
+               faultOnNilArg0: true,
+               hasSideEffects: true,
+               asm:            ppc64.AOR,
                reg: regInfo{
-                       outputs: []outputInfo{
-                               {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+                       inputs: []inputInfo{
+                               {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+                               {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
                        },
                },
        },
        {
-               name:              "LoweredGetCallerPC",
-               argLen:            0,
-               rematerializeable: true,
+               name:           "LoweredAtomicOr32",
+               argLen:         3,
+               faultOnNilArg0: true,
+               hasSideEffects: true,
+               asm:            ppc64.AOR,
                reg: regInfo{
-                       outputs: []outputInfo{
-                               {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+                       inputs: []inputInfo{
+                               {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
+                               {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
                        },
                },
        },
@@ -47784,9 +49682,9 @@ var opcodeTable = [...]opInfo{
                argLen:       1,
                clobberFlags: true,
                reg: regInfo{
-                       clobbers: 9223372034707292160, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                       clobbers: 18446744072632408064, // R11 R12 R18 R19 R22 R23 R24 R25 R26 R27 R28 R29 R31 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 XER
                        outputs: []outputInfo{
-                               {0, 8388608}, // X24
+                               {0, 536870912}, // R29
                        },
                },
        },
@@ -47794,7 +49692,7 @@ var opcodeTable = [...]opInfo{
                name:           "LoweredPubBarrier",
                argLen:         1,
                hasSideEffects: true,
-               asm:            riscv.AFENCE,
+               asm:            ppc64.ALWSYNC,
                reg:            regInfo{},
        },
        {
@@ -47804,8 +49702,8 @@ var opcodeTable = [...]opInfo{
                call:    true,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 64},        // X7
-                               {1, 134217728}, // X28
+                               {0, 32}, // R5
+                               {1, 64}, // R6
                        },
                },
        },
@@ -47816,8 +49714,8 @@ var opcodeTable = [...]opInfo{
                call:    true,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 32}, // X6
-                               {1, 64}, // X7
+                               {0, 16}, // R4
+                               {1, 32}, // R5
                        },
                },
        },
@@ -47828,205 +49726,227 @@ var opcodeTable = [...]opInfo{
                call:    true,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 16}, // X5
-                               {1, 32}, // X6
+                               {0, 8},  // R3
+                               {1, 16}, // R4
                        },
                },
        },
        {
-               name:        "FADDS",
+               name:   "InvertFlags",
+               argLen: 1,
+               reg:    regInfo{},
+       },
+       {
+               name:   "FlagEQ",
+               argLen: 0,
+               reg:    regInfo{},
+       },
+       {
+               name:   "FlagLT",
+               argLen: 0,
+               reg:    regInfo{},
+       },
+       {
+               name:   "FlagGT",
+               argLen: 0,
+               reg:    regInfo{},
+       },
+
+       {
+               name:        "ADD",
                argLen:      2,
                commutative: true,
-               asm:         riscv.AFADDS,
+               asm:         riscv.AADD,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
-                               {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+                               {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
                        },
                        outputs: []outputInfo{
-                               {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
                        },
                },
        },
        {
-               name:   "FSUBS",
-               argLen: 2,
-               asm:    riscv.AFSUBS,
+               name:    "ADDI",
+               auxType: auxInt64,
+               argLen:  1,
+               asm:     riscv.AADDI,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
-                               {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB
                        },
                        outputs: []outputInfo{
-                               {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
                        },
                },
        },
        {
-               name:        "FMULS",
-               argLen:      2,
-               commutative: true,
-               asm:         riscv.AFMULS,
+               name:    "ADDIW",
+               auxType: auxInt64,
+               argLen:  1,
+               asm:     riscv.AADDIW,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
-                               {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
                        },
                        outputs: []outputInfo{
-                               {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
                        },
                },
        },
        {
-               name:   "FDIVS",
-               argLen: 2,
-               asm:    riscv.AFDIVS,
+               name:   "NEG",
+               argLen: 1,
+               asm:    riscv.ANEG,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
-                               {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
                        },
                        outputs: []outputInfo{
-                               {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
                        },
                },
        },
        {
-               name:        "FMADDS",
-               argLen:      3,
-               commutative: true,
-               asm:         riscv.AFMADDS,
+               name:   "NEGW",
+               argLen: 1,
+               asm:    riscv.ANEGW,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
-                               {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
-                               {2, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
                        },
                        outputs: []outputInfo{
-                               {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
                        },
                },
        },
        {
-               name:        "FMSUBS",
-               argLen:      3,
-               commutative: true,
-               asm:         riscv.AFMSUBS,
+               name:   "SUB",
+               argLen: 2,
+               asm:    riscv.ASUB,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
-                               {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
-                               {2, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+                               {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
                        },
                        outputs: []outputInfo{
-                               {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
                        },
                },
        },
        {
-               name:        "FNMADDS",
-               argLen:      3,
-               commutative: true,
-               asm:         riscv.AFNMADDS,
+               name:   "SUBW",
+               argLen: 2,
+               asm:    riscv.ASUBW,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
-                               {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
-                               {2, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+                               {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
                        },
                        outputs: []outputInfo{
-                               {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
                        },
                },
        },
        {
-               name:        "FNMSUBS",
-               argLen:      3,
+               name:        "MUL",
+               argLen:      2,
                commutative: true,
-               asm:         riscv.AFNMSUBS,
+               asm:         riscv.AMUL,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
-                               {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
-                               {2, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+                               {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
                        },
                        outputs: []outputInfo{
-                               {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
                        },
                },
        },
        {
-               name:   "FSQRTS",
-               argLen: 1,
-               asm:    riscv.AFSQRTS,
+               name:        "MULW",
+               argLen:      2,
+               commutative: true,
+               asm:         riscv.AMULW,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+                               {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
                        },
                        outputs: []outputInfo{
-                               {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
                        },
                },
        },
        {
-               name:   "FNEGS",
-               argLen: 1,
-               asm:    riscv.AFNEGS,
+               name:        "MULH",
+               argLen:      2,
+               commutative: true,
+               asm:         riscv.AMULH,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+                               {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
                        },
                        outputs: []outputInfo{
-                               {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
                        },
                },
        },
        {
-               name:   "FMVSX",
-               argLen: 1,
-               asm:    riscv.AFMVSX,
+               name:        "MULHU",
+               argLen:      2,
+               commutative: true,
+               asm:         riscv.AMULHU,
                reg: regInfo{
                        inputs: []inputInfo{
                                {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+                               {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
                        },
                        outputs: []outputInfo{
-                               {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
                        },
                },
        },
        {
-               name:   "FCVTSW",
-               argLen: 1,
-               asm:    riscv.AFCVTSW,
+               name:            "LoweredMuluhilo",
+               argLen:          2,
+               resultNotInArgs: true,
                reg: regInfo{
                        inputs: []inputInfo{
                                {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+                               {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
                        },
                        outputs: []outputInfo{
-                               {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+                               {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
                        },
                },
        },
        {
-               name:   "FCVTSL",
-               argLen: 1,
-               asm:    riscv.AFCVTSL,
+               name:            "LoweredMuluover",
+               argLen:          2,
+               resultNotInArgs: true,
                reg: regInfo{
                        inputs: []inputInfo{
                                {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+                               {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
                        },
                        outputs: []outputInfo{
-                               {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+                               {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
                        },
                },
        },
        {
-               name:   "FCVTWS",
-               argLen: 1,
-               asm:    riscv.AFCVTWS,
+               name:   "DIV",
+               argLen: 2,
+               asm:    riscv.ADIV,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+                               {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
                        },
                        outputs: []outputInfo{
                                {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
@@ -48034,12 +49954,13 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:   "FCVTLS",
-               argLen: 1,
-               asm:    riscv.AFCVTLS,
+               name:   "DIVU",
+               argLen: 2,
+               asm:    riscv.ADIVU,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+                               {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
                        },
                        outputs: []outputInfo{
                                {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
@@ -48047,44 +49968,41 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:           "FMOVWload",
-               auxType:        auxSymOff,
-               argLen:         2,
-               faultOnNilArg0: true,
-               symEffect:      SymRead,
-               asm:            riscv.AMOVF,
+               name:   "DIVW",
+               argLen: 2,
+               asm:    riscv.ADIVW,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB
+                               {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+                               {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
                        },
                        outputs: []outputInfo{
-                               {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
                        },
                },
        },
        {
-               name:           "FMOVWstore",
-               auxType:        auxSymOff,
-               argLen:         3,
-               faultOnNilArg0: true,
-               symEffect:      SymWrite,
-               asm:            riscv.AMOVF,
+               name:   "DIVUW",
+               argLen: 2,
+               asm:    riscv.ADIVUW,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB
-                               {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+                               {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+                       },
+                       outputs: []outputInfo{
+                               {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
                        },
                },
        },
        {
-               name:        "FEQS",
-               argLen:      2,
-               commutative: true,
-               asm:         riscv.AFEQS,
+               name:   "REM",
+               argLen: 2,
+               asm:    riscv.AREM,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
-                               {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+                               {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
                        },
                        outputs: []outputInfo{
                                {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
@@ -48092,14 +50010,13 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:        "FNES",
-               argLen:      2,
-               commutative: true,
-               asm:         riscv.AFNES,
+               name:   "REMU",
+               argLen: 2,
+               asm:    riscv.AREMU,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
-                               {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+                               {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
                        },
                        outputs: []outputInfo{
                                {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
@@ -48107,13 +50024,13 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:   "FLTS",
+               name:   "REMW",
                argLen: 2,
-               asm:    riscv.AFLTS,
+               asm:    riscv.AREMW,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
-                               {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+                               {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
                        },
                        outputs: []outputInfo{
                                {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
@@ -48121,13 +50038,13 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:   "FLES",
+               name:   "REMUW",
                argLen: 2,
-               asm:    riscv.AFLES,
+               asm:    riscv.AREMUW,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
-                               {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+                               {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
                        },
                        outputs: []outputInfo{
                                {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
@@ -48135,258 +50052,299 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:            "LoweredFMAXS",
-               argLen:          2,
-               commutative:     true,
-               resultNotInArgs: true,
-               asm:             riscv.AFMAXS,
+               name:              "MOVaddr",
+               auxType:           auxSymOff,
+               argLen:            1,
+               rematerializeable: true,
+               symEffect:         SymAddr,
+               asm:               riscv.AMOV,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
-                               {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB
                        },
                        outputs: []outputInfo{
-                               {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
                        },
                },
        },
        {
-               name:            "LoweredFMINS",
-               argLen:          2,
-               commutative:     true,
-               resultNotInArgs: true,
-               asm:             riscv.AFMINS,
+               name:              "MOVDconst",
+               auxType:           auxInt64,
+               argLen:            0,
+               rematerializeable: true,
+               asm:               riscv.AMOV,
                reg: regInfo{
-                       inputs: []inputInfo{
-                               {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
-                               {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
-                       },
                        outputs: []outputInfo{
-                               {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
                        },
                },
        },
        {
-               name:        "FADDD",
-               argLen:      2,
-               commutative: true,
-               asm:         riscv.AFADDD,
+               name:           "MOVBload",
+               auxType:        auxSymOff,
+               argLen:         2,
+               faultOnNilArg0: true,
+               symEffect:      SymRead,
+               asm:            riscv.AMOVB,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
-                               {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB
                        },
                        outputs: []outputInfo{
-                               {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
                        },
                },
        },
        {
-               name:   "FSUBD",
-               argLen: 2,
-               asm:    riscv.AFSUBD,
+               name:           "MOVHload",
+               auxType:        auxSymOff,
+               argLen:         2,
+               faultOnNilArg0: true,
+               symEffect:      SymRead,
+               asm:            riscv.AMOVH,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
-                               {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB
                        },
                        outputs: []outputInfo{
-                               {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
                        },
                },
        },
        {
-               name:        "FMULD",
-               argLen:      2,
-               commutative: true,
-               asm:         riscv.AFMULD,
+               name:           "MOVWload",
+               auxType:        auxSymOff,
+               argLen:         2,
+               faultOnNilArg0: true,
+               symEffect:      SymRead,
+               asm:            riscv.AMOVW,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
-                               {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB
                        },
                        outputs: []outputInfo{
-                               {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
                        },
                },
        },
        {
-               name:   "FDIVD",
-               argLen: 2,
-               asm:    riscv.AFDIVD,
+               name:           "MOVDload",
+               auxType:        auxSymOff,
+               argLen:         2,
+               faultOnNilArg0: true,
+               symEffect:      SymRead,
+               asm:            riscv.AMOV,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
-                               {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB
                        },
                        outputs: []outputInfo{
-                               {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
                        },
                },
        },
        {
-               name:        "FMADDD",
-               argLen:      3,
-               commutative: true,
-               asm:         riscv.AFMADDD,
+               name:           "MOVBUload",
+               auxType:        auxSymOff,
+               argLen:         2,
+               faultOnNilArg0: true,
+               symEffect:      SymRead,
+               asm:            riscv.AMOVBU,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
-                               {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
-                               {2, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB
                        },
                        outputs: []outputInfo{
-                               {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
                        },
                },
        },
        {
-               name:        "FMSUBD",
-               argLen:      3,
-               commutative: true,
-               asm:         riscv.AFMSUBD,
+               name:           "MOVHUload",
+               auxType:        auxSymOff,
+               argLen:         2,
+               faultOnNilArg0: true,
+               symEffect:      SymRead,
+               asm:            riscv.AMOVHU,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
-                               {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
-                               {2, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB
                        },
                        outputs: []outputInfo{
-                               {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
                        },
                },
        },
        {
-               name:        "FNMADDD",
-               argLen:      3,
-               commutative: true,
-               asm:         riscv.AFNMADDD,
+               name:           "MOVWUload",
+               auxType:        auxSymOff,
+               argLen:         2,
+               faultOnNilArg0: true,
+               symEffect:      SymRead,
+               asm:            riscv.AMOVWU,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
-                               {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
-                               {2, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB
                        },
                        outputs: []outputInfo{
-                               {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
                        },
                },
        },
        {
-               name:        "FNMSUBD",
-               argLen:      3,
-               commutative: true,
-               asm:         riscv.AFNMSUBD,
+               name:           "MOVBstore",
+               auxType:        auxSymOff,
+               argLen:         3,
+               faultOnNilArg0: true,
+               symEffect:      SymWrite,
+               asm:            riscv.AMOVB,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
-                               {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
-                               {2, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
-                       },
-                       outputs: []outputInfo{
-                               {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {1, 1006632946},          // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+                               {0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB
                        },
                },
        },
        {
-               name:   "FSQRTD",
-               argLen: 1,
-               asm:    riscv.AFSQRTD,
+               name:           "MOVHstore",
+               auxType:        auxSymOff,
+               argLen:         3,
+               faultOnNilArg0: true,
+               symEffect:      SymWrite,
+               asm:            riscv.AMOVH,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
-                       },
-                       outputs: []outputInfo{
-                               {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {1, 1006632946},          // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+                               {0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB
                        },
                },
        },
        {
-               name:   "FNEGD",
-               argLen: 1,
-               asm:    riscv.AFNEGD,
+               name:           "MOVWstore",
+               auxType:        auxSymOff,
+               argLen:         3,
+               faultOnNilArg0: true,
+               symEffect:      SymWrite,
+               asm:            riscv.AMOVW,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {1, 1006632946},          // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+                               {0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB
                        },
-                       outputs: []outputInfo{
-                               {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+               },
+       },
+       {
+               name:           "MOVDstore",
+               auxType:        auxSymOff,
+               argLen:         3,
+               faultOnNilArg0: true,
+               symEffect:      SymWrite,
+               asm:            riscv.AMOV,
+               reg: regInfo{
+                       inputs: []inputInfo{
+                               {1, 1006632946},          // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+                               {0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB
                        },
                },
        },
        {
-               name:   "FABSD",
-               argLen: 1,
-               asm:    riscv.AFABSD,
+               name:           "MOVBstorezero",
+               auxType:        auxSymOff,
+               argLen:         2,
+               faultOnNilArg0: true,
+               symEffect:      SymWrite,
+               asm:            riscv.AMOVB,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB
                        },
-                       outputs: []outputInfo{
-                               {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+               },
+       },
+       {
+               name:           "MOVHstorezero",
+               auxType:        auxSymOff,
+               argLen:         2,
+               faultOnNilArg0: true,
+               symEffect:      SymWrite,
+               asm:            riscv.AMOVH,
+               reg: regInfo{
+                       inputs: []inputInfo{
+                               {0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB
                        },
                },
        },
        {
-               name:   "FSGNJD",
-               argLen: 2,
-               asm:    riscv.AFSGNJD,
+               name:           "MOVWstorezero",
+               auxType:        auxSymOff,
+               argLen:         2,
+               faultOnNilArg0: true,
+               symEffect:      SymWrite,
+               asm:            riscv.AMOVW,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
-                               {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB
                        },
-                       outputs: []outputInfo{
-                               {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+               },
+       },
+       {
+               name:           "MOVDstorezero",
+               auxType:        auxSymOff,
+               argLen:         2,
+               faultOnNilArg0: true,
+               symEffect:      SymWrite,
+               asm:            riscv.AMOV,
+               reg: regInfo{
+                       inputs: []inputInfo{
+                               {0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB
                        },
                },
        },
        {
-               name:   "FMVDX",
+               name:   "MOVBreg",
                argLen: 1,
-               asm:    riscv.AFMVDX,
+               asm:    riscv.AMOVB,
                reg: regInfo{
                        inputs: []inputInfo{
                                {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
                        },
                        outputs: []outputInfo{
-                               {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
                        },
                },
        },
        {
-               name:   "FCVTDW",
+               name:   "MOVHreg",
                argLen: 1,
-               asm:    riscv.AFCVTDW,
+               asm:    riscv.AMOVH,
                reg: regInfo{
                        inputs: []inputInfo{
                                {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
                        },
                        outputs: []outputInfo{
-                               {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
                        },
                },
        },
        {
-               name:   "FCVTDL",
+               name:   "MOVWreg",
                argLen: 1,
-               asm:    riscv.AFCVTDL,
+               asm:    riscv.AMOVW,
                reg: regInfo{
                        inputs: []inputInfo{
                                {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
                        },
                        outputs: []outputInfo{
-                               {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
                        },
                },
        },
        {
-               name:   "FCVTWD",
+               name:   "MOVDreg",
                argLen: 1,
-               asm:    riscv.AFCVTWD,
+               asm:    riscv.AMOV,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
                        },
                        outputs: []outputInfo{
                                {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
@@ -48394,12 +50352,12 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:   "FCVTLD",
+               name:   "MOVBUreg",
                argLen: 1,
-               asm:    riscv.AFCVTLD,
+               asm:    riscv.AMOVBU,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
                        },
                        outputs: []outputInfo{
                                {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
@@ -48407,70 +50365,66 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:   "FCVTDS",
+               name:   "MOVHUreg",
                argLen: 1,
-               asm:    riscv.AFCVTDS,
+               asm:    riscv.AMOVHU,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
                        },
                        outputs: []outputInfo{
-                               {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
                        },
                },
        },
        {
-               name:   "FCVTSD",
+               name:   "MOVWUreg",
                argLen: 1,
-               asm:    riscv.AFCVTSD,
+               asm:    riscv.AMOVWU,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
                        },
                        outputs: []outputInfo{
-                               {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
                        },
                },
        },
        {
-               name:           "FMOVDload",
-               auxType:        auxSymOff,
-               argLen:         2,
-               faultOnNilArg0: true,
-               symEffect:      SymRead,
-               asm:            riscv.AMOVD,
+               name:         "MOVDnop",
+               argLen:       1,
+               resultInArg0: true,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB
+                               {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
                        },
                        outputs: []outputInfo{
-                               {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
                        },
                },
        },
        {
-               name:           "FMOVDstore",
-               auxType:        auxSymOff,
-               argLen:         3,
-               faultOnNilArg0: true,
-               symEffect:      SymWrite,
-               asm:            riscv.AMOVD,
+               name:   "SLL",
+               argLen: 2,
+               asm:    riscv.ASLL,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB
-                               {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+                               {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+                       },
+                       outputs: []outputInfo{
+                               {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
                        },
                },
        },
        {
-               name:        "FEQD",
-               argLen:      2,
-               commutative: true,
-               asm:         riscv.AFEQD,
+               name:   "SLLW",
+               argLen: 2,
+               asm:    riscv.ASLLW,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
-                               {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+                               {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
                        },
                        outputs: []outputInfo{
                                {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
@@ -48478,14 +50432,13 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:        "FNED",
-               argLen:      2,
-               commutative: true,
-               asm:         riscv.AFNED,
+               name:   "SRA",
+               argLen: 2,
+               asm:    riscv.ASRA,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
-                               {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+                               {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
                        },
                        outputs: []outputInfo{
                                {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
@@ -48493,13 +50446,13 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:   "FLTD",
+               name:   "SRAW",
                argLen: 2,
-               asm:    riscv.AFLTD,
+               asm:    riscv.ASRAW,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
-                               {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+                               {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
                        },
                        outputs: []outputInfo{
                                {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
@@ -48507,13 +50460,13 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:   "FLED",
+               name:   "SRL",
                argLen: 2,
-               asm:    riscv.AFLED,
+               asm:    riscv.ASRL,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
-                               {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+                               {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
                        },
                        outputs: []outputInfo{
                                {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
@@ -48521,1879 +50474,1819 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:            "LoweredFMIND",
-               argLen:          2,
-               commutative:     true,
-               resultNotInArgs: true,
-               asm:             riscv.AFMIND,
+               name:   "SRLW",
+               argLen: 2,
+               asm:    riscv.ASRLW,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
-                               {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+                               {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
                        },
                        outputs: []outputInfo{
-                               {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
                        },
                },
        },
        {
-               name:            "LoweredFMAXD",
-               argLen:          2,
-               commutative:     true,
-               resultNotInArgs: true,
-               asm:             riscv.AFMAXD,
+               name:    "SLLI",
+               auxType: auxInt64,
+               argLen:  1,
+               asm:     riscv.ASLLI,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
-                               {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
                        },
                        outputs: []outputInfo{
-                               {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
                        },
                },
        },
-
        {
-               name:         "FADDS",
-               argLen:       2,
-               commutative:  true,
-               resultInArg0: true,
-               asm:          s390x.AFADDS,
+               name:    "SLLIW",
+               auxType: auxInt64,
+               argLen:  1,
+               asm:     riscv.ASLLIW,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
-                               {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+                               {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
                        },
                        outputs: []outputInfo{
-                               {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+                               {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
                        },
                },
        },
        {
-               name:         "FADD",
-               argLen:       2,
-               commutative:  true,
-               resultInArg0: true,
-               asm:          s390x.AFADD,
+               name:    "SRAI",
+               auxType: auxInt64,
+               argLen:  1,
+               asm:     riscv.ASRAI,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
-                               {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+                               {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
                        },
                        outputs: []outputInfo{
-                               {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+                               {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
                        },
                },
        },
        {
-               name:         "FSUBS",
-               argLen:       2,
-               resultInArg0: true,
-               asm:          s390x.AFSUBS,
+               name:    "SRAIW",
+               auxType: auxInt64,
+               argLen:  1,
+               asm:     riscv.ASRAIW,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
-                               {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+                               {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
                        },
                        outputs: []outputInfo{
-                               {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+                               {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
                        },
                },
        },
        {
-               name:         "FSUB",
-               argLen:       2,
-               resultInArg0: true,
-               asm:          s390x.AFSUB,
+               name:    "SRLI",
+               auxType: auxInt64,
+               argLen:  1,
+               asm:     riscv.ASRLI,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
-                               {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+                               {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
                        },
                        outputs: []outputInfo{
-                               {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+                               {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
                        },
                },
        },
        {
-               name:         "FMULS",
-               argLen:       2,
-               commutative:  true,
-               resultInArg0: true,
-               asm:          s390x.AFMULS,
+               name:    "SRLIW",
+               auxType: auxInt64,
+               argLen:  1,
+               asm:     riscv.ASRLIW,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
-                               {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+                               {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
                        },
                        outputs: []outputInfo{
-                               {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+                               {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
                        },
                },
        },
        {
-               name:         "FMUL",
-               argLen:       2,
-               commutative:  true,
-               resultInArg0: true,
-               asm:          s390x.AFMUL,
+               name:   "SH1ADD",
+               argLen: 2,
+               asm:    riscv.ASH1ADD,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
-                               {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+                               {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+                               {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
                        },
                        outputs: []outputInfo{
-                               {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+                               {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
                        },
                },
        },
        {
-               name:         "FDIVS",
-               argLen:       2,
-               resultInArg0: true,
-               asm:          s390x.AFDIVS,
-               reg: regInfo{
+               name:   "SH2ADD",
+               argLen: 2,
+               asm:    riscv.ASH2ADD,
+               reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
-                               {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+                               {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+                               {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
                        },
                        outputs: []outputInfo{
-                               {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+                               {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
                        },
                },
        },
        {
-               name:         "FDIV",
-               argLen:       2,
-               resultInArg0: true,
-               asm:          s390x.AFDIV,
+               name:   "SH3ADD",
+               argLen: 2,
+               asm:    riscv.ASH3ADD,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
-                               {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+                               {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+                               {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
                        },
                        outputs: []outputInfo{
-                               {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+                               {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
                        },
                },
        },
        {
-               name:         "FNEGS",
-               argLen:       1,
-               clobberFlags: true,
-               asm:          s390x.AFNEGS,
+               name:        "AND",
+               argLen:      2,
+               commutative: true,
+               asm:         riscv.AAND,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+                               {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+                               {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
                        },
                        outputs: []outputInfo{
-                               {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+                               {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
                        },
                },
        },
        {
-               name:         "FNEG",
-               argLen:       1,
-               clobberFlags: true,
-               asm:          s390x.AFNEG,
+               name:   "ANDN",
+               argLen: 2,
+               asm:    riscv.AANDN,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+                               {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+                               {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
                        },
                        outputs: []outputInfo{
-                               {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+                               {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
                        },
                },
        },
        {
-               name:         "FMADDS",
-               argLen:       3,
-               resultInArg0: true,
-               asm:          s390x.AFMADDS,
+               name:    "ANDI",
+               auxType: auxInt64,
+               argLen:  1,
+               asm:     riscv.AANDI,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
-                               {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
-                               {2, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+                               {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
                        },
                        outputs: []outputInfo{
-                               {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+                               {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
                        },
                },
        },
        {
-               name:         "FMADD",
-               argLen:       3,
-               resultInArg0: true,
-               asm:          s390x.AFMADD,
+               name:   "CLZ",
+               argLen: 1,
+               asm:    riscv.ACLZ,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
-                               {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
-                               {2, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+                               {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
                        },
                        outputs: []outputInfo{
-                               {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+                               {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
                        },
                },
        },
        {
-               name:         "FMSUBS",
-               argLen:       3,
-               resultInArg0: true,
-               asm:          s390x.AFMSUBS,
+               name:   "CLZW",
+               argLen: 1,
+               asm:    riscv.ACLZW,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
-                               {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
-                               {2, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+                               {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
                        },
                        outputs: []outputInfo{
-                               {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+                               {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
                        },
                },
        },
        {
-               name:         "FMSUB",
-               argLen:       3,
-               resultInArg0: true,
-               asm:          s390x.AFMSUB,
+               name:   "CPOP",
+               argLen: 1,
+               asm:    riscv.ACPOP,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
-                               {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
-                               {2, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+                               {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
                        },
                        outputs: []outputInfo{
-                               {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+                               {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
                        },
                },
        },
        {
-               name:   "LPDFR",
+               name:   "CPOPW",
                argLen: 1,
-               asm:    s390x.ALPDFR,
+               asm:    riscv.ACPOPW,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+                               {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
                        },
                        outputs: []outputInfo{
-                               {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+                               {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
                        },
                },
        },
        {
-               name:   "LNDFR",
+               name:   "CTZ",
                argLen: 1,
-               asm:    s390x.ALNDFR,
+               asm:    riscv.ACTZ,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+                               {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
                        },
                        outputs: []outputInfo{
-                               {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+                               {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
                        },
                },
        },
        {
-               name:   "CPSDR",
-               argLen: 2,
-               asm:    s390x.ACPSDR,
+               name:   "CTZW",
+               argLen: 1,
+               asm:    riscv.ACTZW,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
-                               {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+                               {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
                        },
                        outputs: []outputInfo{
-                               {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+                               {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
                        },
                },
        },
        {
-               name:    "FIDBR",
-               auxType: auxInt8,
-               argLen:  1,
-               asm:     s390x.AFIDBR,
+               name:   "NOT",
+               argLen: 1,
+               asm:    riscv.ANOT,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+                               {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
                        },
                        outputs: []outputInfo{
-                               {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+                               {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
                        },
                },
        },
        {
-               name:           "FMOVSload",
-               auxType:        auxSymOff,
-               argLen:         2,
-               faultOnNilArg0: true,
-               symEffect:      SymRead,
-               asm:            s390x.AFMOVS,
+               name:        "OR",
+               argLen:      2,
+               commutative: true,
+               asm:         riscv.AOR,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB
+                               {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+                               {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
                        },
                        outputs: []outputInfo{
-                               {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+                               {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
                        },
                },
        },
        {
-               name:           "FMOVDload",
-               auxType:        auxSymOff,
-               argLen:         2,
-               faultOnNilArg0: true,
-               symEffect:      SymRead,
-               asm:            s390x.AFMOVD,
+               name:   "ORN",
+               argLen: 2,
+               asm:    riscv.AORN,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB
+                               {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+                               {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
                        },
                        outputs: []outputInfo{
-                               {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+                               {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
                        },
                },
        },
        {
-               name:              "FMOVSconst",
-               auxType:           auxFloat32,
-               argLen:            0,
-               rematerializeable: true,
-               asm:               s390x.AFMOVS,
+               name:    "ORI",
+               auxType: auxInt64,
+               argLen:  1,
+               asm:     riscv.AORI,
                reg: regInfo{
-                       outputs: []outputInfo{
-                               {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+                       inputs: []inputInfo{
+                               {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
                        },
-               },
-       },
-       {
-               name:              "FMOVDconst",
-               auxType:           auxFloat64,
-               argLen:            0,
-               rematerializeable: true,
-               asm:               s390x.AFMOVD,
-               reg: regInfo{
                        outputs: []outputInfo{
-                               {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+                               {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
                        },
                },
        },
        {
-               name:      "FMOVSloadidx",
-               auxType:   auxSymOff,
-               argLen:    3,
-               symEffect: SymRead,
-               asm:       s390x.AFMOVS,
+               name:   "REV8",
+               argLen: 1,
+               asm:    riscv.AREV8,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
-                               {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
+                               {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
                        },
                        outputs: []outputInfo{
-                               {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+                               {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
                        },
                },
        },
        {
-               name:      "FMOVDloadidx",
-               auxType:   auxSymOff,
-               argLen:    3,
-               symEffect: SymRead,
-               asm:       s390x.AFMOVD,
+               name:   "ROL",
+               argLen: 2,
+               asm:    riscv.AROL,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
-                               {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
+                               {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+                               {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
                        },
                        outputs: []outputInfo{
-                               {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+                               {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
                        },
                },
        },
        {
-               name:           "FMOVSstore",
-               auxType:        auxSymOff,
-               argLen:         3,
-               faultOnNilArg0: true,
-               symEffect:      SymWrite,
-               asm:            s390x.AFMOVS,
+               name:   "ROLW",
+               argLen: 2,
+               asm:    riscv.AROLW,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB
-                               {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+                               {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+                               {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+                       },
+                       outputs: []outputInfo{
+                               {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
                        },
                },
        },
        {
-               name:           "FMOVDstore",
-               auxType:        auxSymOff,
-               argLen:         3,
-               faultOnNilArg0: true,
-               symEffect:      SymWrite,
-               asm:            s390x.AFMOVD,
+               name:   "ROR",
+               argLen: 2,
+               asm:    riscv.AROR,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB
-                               {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+                               {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+                               {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+                       },
+                       outputs: []outputInfo{
+                               {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
                        },
                },
        },
        {
-               name:      "FMOVSstoreidx",
-               auxType:   auxSymOff,
-               argLen:    4,
-               symEffect: SymWrite,
-               asm:       s390x.AFMOVS,
+               name:    "RORI",
+               auxType: auxInt64,
+               argLen:  1,
+               asm:     riscv.ARORI,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 56318},      // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
-                               {1, 56318},      // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
-                               {2, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+                               {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+                       },
+                       outputs: []outputInfo{
+                               {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
                        },
                },
        },
        {
-               name:      "FMOVDstoreidx",
-               auxType:   auxSymOff,
-               argLen:    4,
-               symEffect: SymWrite,
-               asm:       s390x.AFMOVD,
+               name:    "RORIW",
+               auxType: auxInt64,
+               argLen:  1,
+               asm:     riscv.ARORIW,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 56318},      // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
-                               {1, 56318},      // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
-                               {2, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+                               {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+                       },
+                       outputs: []outputInfo{
+                               {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
                        },
                },
        },
        {
-               name:         "ADD",
-               argLen:       2,
-               commutative:  true,
-               clobberFlags: true,
-               asm:          s390x.AADD,
+               name:   "RORW",
+               argLen: 2,
+               asm:    riscv.ARORW,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {1, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
-                               {0, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
+                               {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+                               {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
                        },
                        outputs: []outputInfo{
-                               {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+                               {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
                        },
                },
        },
        {
-               name:         "ADDW",
-               argLen:       2,
-               commutative:  true,
-               clobberFlags: true,
-               asm:          s390x.AADDW,
+               name:        "XNOR",
+               argLen:      2,
+               commutative: true,
+               asm:         riscv.AXNOR,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {1, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
-                               {0, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
+                               {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+                               {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
                        },
                        outputs: []outputInfo{
-                               {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+                               {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
                        },
                },
        },
        {
-               name:         "ADDconst",
-               auxType:      auxInt32,
-               argLen:       1,
-               clobberFlags: true,
-               asm:          s390x.AADD,
+               name:        "XOR",
+               argLen:      2,
+               commutative: true,
+               asm:         riscv.AXOR,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
+                               {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+                               {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
                        },
                        outputs: []outputInfo{
-                               {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+                               {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
                        },
                },
        },
        {
-               name:         "ADDWconst",
-               auxType:      auxInt32,
-               argLen:       1,
-               clobberFlags: true,
-               asm:          s390x.AADDW,
+               name:    "XORI",
+               auxType: auxInt64,
+               argLen:  1,
+               asm:     riscv.AXORI,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
+                               {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
                        },
                        outputs: []outputInfo{
-                               {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+                               {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
                        },
                },
        },
        {
-               name:           "ADDload",
-               auxType:        auxSymOff,
-               argLen:         3,
-               resultInArg0:   true,
-               clobberFlags:   true,
-               faultOnNilArg1: true,
-               symEffect:      SymRead,
-               asm:            s390x.AADD,
+               name:        "MIN",
+               argLen:      2,
+               commutative: true,
+               asm:         riscv.AMIN,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
-                               {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
+                               {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+                               {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
                        },
                        outputs: []outputInfo{
-                               {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+                               {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
                        },
                },
        },
        {
-               name:           "ADDWload",
-               auxType:        auxSymOff,
-               argLen:         3,
-               resultInArg0:   true,
-               clobberFlags:   true,
-               faultOnNilArg1: true,
-               symEffect:      SymRead,
-               asm:            s390x.AADDW,
+               name:        "MAX",
+               argLen:      2,
+               commutative: true,
+               asm:         riscv.AMAX,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
-                               {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
+                               {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+                               {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
                        },
                        outputs: []outputInfo{
-                               {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+                               {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
                        },
                },
        },
        {
-               name:         "SUB",
-               argLen:       2,
-               clobberFlags: true,
-               asm:          s390x.ASUB,
+               name:        "MINU",
+               argLen:      2,
+               commutative: true,
+               asm:         riscv.AMINU,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
-                               {1, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+                               {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+                               {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
                        },
                        outputs: []outputInfo{
-                               {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+                               {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
                        },
                },
        },
        {
-               name:         "SUBW",
-               argLen:       2,
-               clobberFlags: true,
-               asm:          s390x.ASUBW,
+               name:        "MAXU",
+               argLen:      2,
+               commutative: true,
+               asm:         riscv.AMAXU,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
-                               {1, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+                               {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+                               {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
                        },
                        outputs: []outputInfo{
-                               {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+                               {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
                        },
                },
        },
        {
-               name:         "SUBconst",
-               auxType:      auxInt32,
-               argLen:       1,
-               resultInArg0: true,
-               clobberFlags: true,
-               asm:          s390x.ASUB,
+               name:   "SEQZ",
+               argLen: 1,
+               asm:    riscv.ASEQZ,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+                               {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
                        },
                        outputs: []outputInfo{
-                               {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+                               {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
                        },
                },
        },
        {
-               name:         "SUBWconst",
-               auxType:      auxInt32,
-               argLen:       1,
-               resultInArg0: true,
-               clobberFlags: true,
-               asm:          s390x.ASUBW,
+               name:   "SNEZ",
+               argLen: 1,
+               asm:    riscv.ASNEZ,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+                               {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
                        },
                        outputs: []outputInfo{
-                               {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+                               {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
                        },
                },
        },
        {
-               name:           "SUBload",
-               auxType:        auxSymOff,
-               argLen:         3,
-               resultInArg0:   true,
-               clobberFlags:   true,
-               faultOnNilArg1: true,
-               symEffect:      SymRead,
-               asm:            s390x.ASUB,
+               name:   "SLT",
+               argLen: 2,
+               asm:    riscv.ASLT,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
-                               {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
+                               {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+                               {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
                        },
                        outputs: []outputInfo{
-                               {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+                               {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
                        },
                },
        },
        {
-               name:           "SUBWload",
-               auxType:        auxSymOff,
-               argLen:         3,
-               resultInArg0:   true,
-               clobberFlags:   true,
-               faultOnNilArg1: true,
-               symEffect:      SymRead,
-               asm:            s390x.ASUBW,
+               name:    "SLTI",
+               auxType: auxInt64,
+               argLen:  1,
+               asm:     riscv.ASLTI,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
-                               {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
+                               {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
                        },
                        outputs: []outputInfo{
-                               {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+                               {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
                        },
                },
        },
        {
-               name:         "MULLD",
-               argLen:       2,
-               commutative:  true,
-               resultInArg0: true,
-               clobberFlags: true,
-               asm:          s390x.AMULLD,
+               name:   "SLTU",
+               argLen: 2,
+               asm:    riscv.ASLTU,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
-                               {1, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+                               {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+                               {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
                        },
                        outputs: []outputInfo{
-                               {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+                               {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
                        },
                },
        },
        {
-               name:         "MULLW",
-               argLen:       2,
-               commutative:  true,
-               resultInArg0: true,
-               clobberFlags: true,
-               asm:          s390x.AMULLW,
+               name:    "SLTIU",
+               auxType: auxInt64,
+               argLen:  1,
+               asm:     riscv.ASLTIU,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
-                               {1, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+                               {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
                        },
                        outputs: []outputInfo{
-                               {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+                               {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
                        },
                },
        },
        {
-               name:         "MULLDconst",
-               auxType:      auxInt32,
+               name:         "LoweredRound32F",
                argLen:       1,
                resultInArg0: true,
-               clobberFlags: true,
-               asm:          s390x.AMULLD,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+                               {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
                        },
                        outputs: []outputInfo{
-                               {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+                               {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
                        },
                },
        },
        {
-               name:         "MULLWconst",
-               auxType:      auxInt32,
+               name:         "LoweredRound64F",
                argLen:       1,
                resultInArg0: true,
-               clobberFlags: true,
-               asm:          s390x.AMULLW,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+                               {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
                        },
                        outputs: []outputInfo{
-                               {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+                               {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
                        },
                },
        },
        {
-               name:           "MULLDload",
-               auxType:        auxSymOff,
-               argLen:         3,
-               resultInArg0:   true,
-               clobberFlags:   true,
-               faultOnNilArg1: true,
-               symEffect:      SymRead,
-               asm:            s390x.AMULLD,
+               name:    "CALLstatic",
+               auxType: auxCallOff,
+               argLen:  -1,
+               call:    true,
+               reg: regInfo{
+                       clobbers: 9223372035781033968, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+               },
+       },
+       {
+               name:     "CALLtail",
+               auxType:  auxCallOff,
+               argLen:   -1,
+               call:     true,
+               tailCall: true,
+               reg: regInfo{
+                       clobbers: 9223372035781033968, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+               },
+       },
+       {
+               name:    "CALLclosure",
+               auxType: auxCallOff,
+               argLen:  -1,
+               call:    true,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
-                               {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
+                               {1, 33554432},   // X26
+                               {0, 1006632946}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
                        },
-                       outputs: []outputInfo{
-                               {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+                       clobbers: 9223372035781033968, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+               },
+       },
+       {
+               name:    "CALLinter",
+               auxType: auxCallOff,
+               argLen:  -1,
+               call:    true,
+               reg: regInfo{
+                       inputs: []inputInfo{
+                               {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+                       },
+                       clobbers: 9223372035781033968, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+               },
+       },
+       {
+               name:           "DUFFZERO",
+               auxType:        auxInt64,
+               argLen:         2,
+               faultOnNilArg0: true,
+               reg: regInfo{
+                       inputs: []inputInfo{
+                               {0, 16777216}, // X25
                        },
+                       clobbers: 16777216, // X25
                },
        },
        {
-               name:           "MULLWload",
-               auxType:        auxSymOff,
+               name:           "DUFFCOPY",
+               auxType:        auxInt64,
                argLen:         3,
-               resultInArg0:   true,
-               clobberFlags:   true,
+               faultOnNilArg0: true,
                faultOnNilArg1: true,
-               symEffect:      SymRead,
-               asm:            s390x.AMULLW,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
-                               {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
-                       },
-                       outputs: []outputInfo{
-                               {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+                               {0, 16777216}, // X25
+                               {1, 8388608},  // X24
                        },
+                       clobbers: 25165824, // X24 X25
                },
        },
        {
-               name:         "MULHD",
-               argLen:       2,
-               commutative:  true,
-               resultInArg0: true,
-               clobberFlags: true,
-               asm:          s390x.AMULHD,
+               name:           "LoweredZero",
+               auxType:        auxInt64,
+               argLen:         3,
+               faultOnNilArg0: true,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
-                               {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
-                       },
-                       clobbers: 2048, // R11
-                       outputs: []outputInfo{
-                               {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+                               {0, 16},         // X5
+                               {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
                        },
+                       clobbers: 16, // X5
                },
        },
        {
-               name:         "MULHDU",
-               argLen:       2,
-               commutative:  true,
-               resultInArg0: true,
-               clobberFlags: true,
-               asm:          s390x.AMULHDU,
+               name:           "LoweredMove",
+               auxType:        auxInt64,
+               argLen:         4,
+               faultOnNilArg0: true,
+               faultOnNilArg1: true,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
-                               {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
-                       },
-                       clobbers: 2048, // R11
-                       outputs: []outputInfo{
-                               {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+                               {0, 16},         // X5
+                               {1, 32},         // X6
+                               {2, 1006632880}, // X5 X6 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
                        },
+                       clobbers: 112, // X5 X6 X7
                },
        },
        {
-               name:         "DIVD",
-               argLen:       2,
-               resultInArg0: true,
-               clobberFlags: true,
-               asm:          s390x.ADIVD,
+               name:           "LoweredAtomicLoad8",
+               argLen:         2,
+               faultOnNilArg0: true,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
-                               {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+                               {0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB
                        },
-                       clobbers: 2048, // R11
                        outputs: []outputInfo{
-                               {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+                               {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
                        },
                },
        },
        {
-               name:         "DIVW",
-               argLen:       2,
-               resultInArg0: true,
-               clobberFlags: true,
-               asm:          s390x.ADIVW,
+               name:           "LoweredAtomicLoad32",
+               argLen:         2,
+               faultOnNilArg0: true,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
-                               {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+                               {0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB
                        },
-                       clobbers: 2048, // R11
                        outputs: []outputInfo{
-                               {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+                               {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
                        },
                },
        },
        {
-               name:         "DIVDU",
-               argLen:       2,
-               resultInArg0: true,
-               clobberFlags: true,
-               asm:          s390x.ADIVDU,
+               name:           "LoweredAtomicLoad64",
+               argLen:         2,
+               faultOnNilArg0: true,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
-                               {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+                               {0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB
                        },
-                       clobbers: 2048, // R11
                        outputs: []outputInfo{
-                               {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+                               {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
                        },
                },
        },
        {
-               name:         "DIVWU",
-               argLen:       2,
-               resultInArg0: true,
-               clobberFlags: true,
-               asm:          s390x.ADIVWU,
+               name:           "LoweredAtomicStore8",
+               argLen:         3,
+               faultOnNilArg0: true,
+               hasSideEffects: true,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
-                               {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
-                       },
-                       clobbers: 2048, // R11
-                       outputs: []outputInfo{
-                               {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+                               {1, 1006632946},          // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+                               {0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB
                        },
                },
        },
        {
-               name:         "MODD",
-               argLen:       2,
-               resultInArg0: true,
-               clobberFlags: true,
-               asm:          s390x.AMODD,
+               name:           "LoweredAtomicStore32",
+               argLen:         3,
+               faultOnNilArg0: true,
+               hasSideEffects: true,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
-                               {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
-                       },
-                       clobbers: 2048, // R11
-                       outputs: []outputInfo{
-                               {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+                               {1, 1006632946},          // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+                               {0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB
                        },
                },
        },
        {
-               name:         "MODW",
-               argLen:       2,
-               resultInArg0: true,
-               clobberFlags: true,
-               asm:          s390x.AMODW,
+               name:           "LoweredAtomicStore64",
+               argLen:         3,
+               faultOnNilArg0: true,
+               hasSideEffects: true,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
-                               {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
-                       },
-                       clobbers: 2048, // R11
-                       outputs: []outputInfo{
-                               {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+                               {1, 1006632946},          // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+                               {0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB
                        },
                },
        },
        {
-               name:         "MODDU",
-               argLen:       2,
-               resultInArg0: true,
-               clobberFlags: true,
-               asm:          s390x.AMODDU,
+               name:            "LoweredAtomicExchange32",
+               argLen:          3,
+               resultNotInArgs: true,
+               faultOnNilArg0:  true,
+               hasSideEffects:  true,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
-                               {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+                               {1, 1073741808},          // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30
+                               {0, 9223372037928517618}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30 SB
                        },
-                       clobbers: 2048, // R11
                        outputs: []outputInfo{
-                               {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+                               {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
                        },
                },
        },
        {
-               name:         "MODWU",
-               argLen:       2,
-               resultInArg0: true,
-               clobberFlags: true,
-               asm:          s390x.AMODWU,
+               name:            "LoweredAtomicExchange64",
+               argLen:          3,
+               resultNotInArgs: true,
+               faultOnNilArg0:  true,
+               hasSideEffects:  true,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
-                               {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+                               {1, 1073741808},          // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30
+                               {0, 9223372037928517618}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30 SB
                        },
-                       clobbers: 2048, // R11
                        outputs: []outputInfo{
-                               {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+                               {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
                        },
                },
        },
        {
-               name:         "AND",
-               argLen:       2,
-               commutative:  true,
-               clobberFlags: true,
-               asm:          s390x.AAND,
+               name:            "LoweredAtomicAdd32",
+               argLen:          3,
+               resultNotInArgs: true,
+               faultOnNilArg0:  true,
+               hasSideEffects:  true,
+               unsafePoint:     true,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
-                               {1, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+                               {1, 1073741808},          // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30
+                               {0, 9223372037928517618}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30 SB
                        },
                        outputs: []outputInfo{
-                               {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+                               {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
                        },
                },
        },
        {
-               name:         "ANDW",
-               argLen:       2,
-               commutative:  true,
-               clobberFlags: true,
-               asm:          s390x.AANDW,
+               name:            "LoweredAtomicAdd64",
+               argLen:          3,
+               resultNotInArgs: true,
+               faultOnNilArg0:  true,
+               hasSideEffects:  true,
+               unsafePoint:     true,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
-                               {1, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+                               {1, 1073741808},          // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30
+                               {0, 9223372037928517618}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30 SB
                        },
                        outputs: []outputInfo{
-                               {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+                               {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
                        },
                },
        },
        {
-               name:         "ANDconst",
-               auxType:      auxInt64,
-               argLen:       1,
-               resultInArg0: true,
-               clobberFlags: true,
-               asm:          s390x.AAND,
+               name:            "LoweredAtomicCas32",
+               argLen:          4,
+               resultNotInArgs: true,
+               faultOnNilArg0:  true,
+               hasSideEffects:  true,
+               unsafePoint:     true,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+                               {1, 1073741808},          // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30
+                               {2, 1073741808},          // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30
+                               {0, 9223372037928517618}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30 SB
                        },
                        outputs: []outputInfo{
-                               {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+                               {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
                        },
                },
        },
        {
-               name:         "ANDWconst",
-               auxType:      auxInt32,
-               argLen:       1,
-               resultInArg0: true,
-               clobberFlags: true,
-               asm:          s390x.AANDW,
+               name:            "LoweredAtomicCas64",
+               argLen:          4,
+               resultNotInArgs: true,
+               faultOnNilArg0:  true,
+               hasSideEffects:  true,
+               unsafePoint:     true,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+                               {1, 1073741808},          // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30
+                               {2, 1073741808},          // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30
+                               {0, 9223372037928517618}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30 SB
                        },
                        outputs: []outputInfo{
-                               {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+                               {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
                        },
                },
        },
        {
-               name:           "ANDload",
-               auxType:        auxSymOff,
+               name:           "LoweredAtomicAnd32",
                argLen:         3,
-               resultInArg0:   true,
-               clobberFlags:   true,
-               faultOnNilArg1: true,
-               symEffect:      SymRead,
-               asm:            s390x.AAND,
+               faultOnNilArg0: true,
+               hasSideEffects: true,
+               asm:            riscv.AAMOANDW,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
-                               {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
-                       },
-                       outputs: []outputInfo{
-                               {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+                               {1, 1073741808},          // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30
+                               {0, 9223372037928517618}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30 SB
                        },
                },
        },
        {
-               name:           "ANDWload",
-               auxType:        auxSymOff,
+               name:           "LoweredAtomicOr32",
                argLen:         3,
-               resultInArg0:   true,
-               clobberFlags:   true,
-               faultOnNilArg1: true,
-               symEffect:      SymRead,
-               asm:            s390x.AANDW,
+               faultOnNilArg0: true,
+               hasSideEffects: true,
+               asm:            riscv.AAMOORW,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
-                               {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
-                       },
-                       outputs: []outputInfo{
-                               {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+                               {1, 1073741808},          // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30
+                               {0, 9223372037928517618}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30 SB
                        },
                },
        },
        {
-               name:         "OR",
-               argLen:       2,
-               commutative:  true,
-               clobberFlags: true,
-               asm:          s390x.AOR,
+               name:           "LoweredNilCheck",
+               argLen:         2,
+               nilCheck:       true,
+               faultOnNilArg0: true,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
-                               {1, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+                               {0, 1006632946}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
                        },
+               },
+       },
+       {
+               name:   "LoweredGetClosurePtr",
+               argLen: 0,
+               reg: regInfo{
                        outputs: []outputInfo{
-                               {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+                               {0, 33554432}, // X26
                        },
                },
        },
        {
-               name:         "ORW",
-               argLen:       2,
-               commutative:  true,
-               clobberFlags: true,
-               asm:          s390x.AORW,
+               name:              "LoweredGetCallerSP",
+               argLen:            1,
+               rematerializeable: true,
                reg: regInfo{
-                       inputs: []inputInfo{
-                               {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
-                               {1, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+                       outputs: []outputInfo{
+                               {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
                        },
+               },
+       },
+       {
+               name:              "LoweredGetCallerPC",
+               argLen:            0,
+               rematerializeable: true,
+               reg: regInfo{
                        outputs: []outputInfo{
-                               {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+                               {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
                        },
                },
        },
        {
-               name:         "ORconst",
+               name:         "LoweredWB",
                auxType:      auxInt64,
                argLen:       1,
-               resultInArg0: true,
                clobberFlags: true,
-               asm:          s390x.AOR,
                reg: regInfo{
-                       inputs: []inputInfo{
-                               {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
-                       },
+                       clobbers: 9223372034707292160, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
                        outputs: []outputInfo{
-                               {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+                               {0, 8388608}, // X24
                        },
                },
        },
        {
-               name:         "ORWconst",
-               auxType:      auxInt32,
-               argLen:       1,
-               resultInArg0: true,
-               clobberFlags: true,
-               asm:          s390x.AORW,
+               name:           "LoweredPubBarrier",
+               argLen:         1,
+               hasSideEffects: true,
+               asm:            riscv.AFENCE,
+               reg:            regInfo{},
+       },
+       {
+               name:    "LoweredPanicBoundsA",
+               auxType: auxInt64,
+               argLen:  3,
+               call:    true,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
-                       },
-                       outputs: []outputInfo{
-                               {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+                               {0, 64},        // X7
+                               {1, 134217728}, // X28
                        },
                },
        },
        {
-               name:           "ORload",
-               auxType:        auxSymOff,
-               argLen:         3,
-               resultInArg0:   true,
-               clobberFlags:   true,
-               faultOnNilArg1: true,
-               symEffect:      SymRead,
-               asm:            s390x.AOR,
+               name:    "LoweredPanicBoundsB",
+               auxType: auxInt64,
+               argLen:  3,
+               call:    true,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
-                               {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
-                       },
-                       outputs: []outputInfo{
-                               {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+                               {0, 32}, // X6
+                               {1, 64}, // X7
                        },
                },
        },
        {
-               name:           "ORWload",
-               auxType:        auxSymOff,
-               argLen:         3,
-               resultInArg0:   true,
-               clobberFlags:   true,
-               faultOnNilArg1: true,
-               symEffect:      SymRead,
-               asm:            s390x.AORW,
+               name:    "LoweredPanicBoundsC",
+               auxType: auxInt64,
+               argLen:  3,
+               call:    true,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
-                               {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
-                       },
-                       outputs: []outputInfo{
-                               {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+                               {0, 16}, // X5
+                               {1, 32}, // X6
                        },
                },
        },
        {
-               name:         "XOR",
-               argLen:       2,
-               commutative:  true,
-               clobberFlags: true,
-               asm:          s390x.AXOR,
+               name:        "FADDS",
+               argLen:      2,
+               commutative: true,
+               asm:         riscv.AFADDS,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
-                               {1, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+                               {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
                        },
                        outputs: []outputInfo{
-                               {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+                               {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
                        },
                },
        },
        {
-               name:         "XORW",
-               argLen:       2,
-               commutative:  true,
-               clobberFlags: true,
-               asm:          s390x.AXORW,
+               name:   "FSUBS",
+               argLen: 2,
+               asm:    riscv.AFSUBS,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
-                               {1, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+                               {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
                        },
                        outputs: []outputInfo{
-                               {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+                               {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
                        },
                },
        },
        {
-               name:         "XORconst",
-               auxType:      auxInt64,
-               argLen:       1,
-               resultInArg0: true,
-               clobberFlags: true,
-               asm:          s390x.AXOR,
+               name:        "FMULS",
+               argLen:      2,
+               commutative: true,
+               asm:         riscv.AFMULS,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+                               {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
                        },
                        outputs: []outputInfo{
-                               {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+                               {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
                        },
                },
        },
        {
-               name:         "XORWconst",
-               auxType:      auxInt32,
-               argLen:       1,
-               resultInArg0: true,
-               clobberFlags: true,
-               asm:          s390x.AXORW,
+               name:   "FDIVS",
+               argLen: 2,
+               asm:    riscv.AFDIVS,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+                               {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
                        },
                        outputs: []outputInfo{
-                               {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+                               {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
                        },
                },
        },
        {
-               name:           "XORload",
-               auxType:        auxSymOff,
-               argLen:         3,
-               resultInArg0:   true,
-               clobberFlags:   true,
-               faultOnNilArg1: true,
-               symEffect:      SymRead,
-               asm:            s390x.AXOR,
+               name:        "FMADDS",
+               argLen:      3,
+               commutative: true,
+               asm:         riscv.AFMADDS,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
-                               {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
+                               {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {2, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
                        },
                        outputs: []outputInfo{
-                               {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+                               {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
                        },
                },
        },
        {
-               name:           "XORWload",
-               auxType:        auxSymOff,
-               argLen:         3,
-               resultInArg0:   true,
-               clobberFlags:   true,
-               faultOnNilArg1: true,
-               symEffect:      SymRead,
-               asm:            s390x.AXORW,
+               name:        "FMSUBS",
+               argLen:      3,
+               commutative: true,
+               asm:         riscv.AFMSUBS,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
-                               {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
+                               {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {2, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
                        },
                        outputs: []outputInfo{
-                               {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+                               {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
                        },
                },
        },
        {
-               name:        "ADDC",
-               argLen:      2,
+               name:        "FNMADDS",
+               argLen:      3,
                commutative: true,
-               asm:         s390x.AADDC,
+               asm:         riscv.AFNMADDS,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
-                               {1, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+                               {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {2, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
                        },
                        outputs: []outputInfo{
-                               {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+                               {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
                        },
                },
        },
        {
-               name:    "ADDCconst",
-               auxType: auxInt16,
-               argLen:  1,
-               asm:     s390x.AADDC,
+               name:        "FNMSUBS",
+               argLen:      3,
+               commutative: true,
+               asm:         riscv.AFNMSUBS,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+                               {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {2, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
                        },
                        outputs: []outputInfo{
-                               {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+                               {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
                        },
                },
        },
        {
-               name:         "ADDE",
-               argLen:       3,
-               commutative:  true,
-               resultInArg0: true,
-               asm:          s390x.AADDE,
+               name:   "FSQRTS",
+               argLen: 1,
+               asm:    riscv.AFSQRTS,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
-                               {1, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+                               {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
                        },
                        outputs: []outputInfo{
-                               {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+                               {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
                        },
                },
        },
        {
-               name:   "SUBC",
-               argLen: 2,
-               asm:    s390x.ASUBC,
+               name:   "FNEGS",
+               argLen: 1,
+               asm:    riscv.AFNEGS,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
-                               {1, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+                               {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
                        },
                        outputs: []outputInfo{
-                               {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+                               {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
                        },
                },
        },
        {
-               name:         "SUBE",
-               argLen:       3,
-               resultInArg0: true,
-               asm:          s390x.ASUBE,
+               name:   "FMVSX",
+               argLen: 1,
+               asm:    riscv.AFMVSX,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
-                               {1, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+                               {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
                        },
                        outputs: []outputInfo{
-                               {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+                               {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
                        },
                },
        },
        {
-               name:   "CMP",
-               argLen: 2,
-               asm:    s390x.ACMP,
+               name:   "FCVTSW",
+               argLen: 1,
+               asm:    riscv.AFCVTSW,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
-                               {1, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
+                               {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+                       },
+                       outputs: []outputInfo{
+                               {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
                        },
                },
        },
        {
-               name:   "CMPW",
-               argLen: 2,
-               asm:    s390x.ACMPW,
+               name:   "FCVTSL",
+               argLen: 1,
+               asm:    riscv.AFCVTSL,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
-                               {1, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
+                               {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+                       },
+                       outputs: []outputInfo{
+                               {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
                        },
                },
        },
        {
-               name:   "CMPU",
-               argLen: 2,
-               asm:    s390x.ACMPU,
+               name:   "FCVTWS",
+               argLen: 1,
+               asm:    riscv.AFCVTWS,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
-                               {1, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
+                               {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                       },
+                       outputs: []outputInfo{
+                               {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
                        },
                },
        },
        {
-               name:   "CMPWU",
-               argLen: 2,
-               asm:    s390x.ACMPWU,
+               name:   "FCVTLS",
+               argLen: 1,
+               asm:    riscv.AFCVTLS,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
-                               {1, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
+                               {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                       },
+                       outputs: []outputInfo{
+                               {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
                        },
                },
        },
        {
-               name:    "CMPconst",
-               auxType: auxInt32,
-               argLen:  1,
-               asm:     s390x.ACMP,
+               name:           "FMOVWload",
+               auxType:        auxSymOff,
+               argLen:         2,
+               faultOnNilArg0: true,
+               symEffect:      SymRead,
+               asm:            riscv.AMOVF,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
+                               {0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB
+                       },
+                       outputs: []outputInfo{
+                               {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
                        },
                },
        },
        {
-               name:    "CMPWconst",
-               auxType: auxInt32,
-               argLen:  1,
-               asm:     s390x.ACMPW,
+               name:           "FMOVWstore",
+               auxType:        auxSymOff,
+               argLen:         3,
+               faultOnNilArg0: true,
+               symEffect:      SymWrite,
+               asm:            riscv.AMOVF,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
+                               {0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB
+                               {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
                        },
                },
        },
        {
-               name:    "CMPUconst",
-               auxType: auxInt32,
-               argLen:  1,
-               asm:     s390x.ACMPU,
+               name:        "FEQS",
+               argLen:      2,
+               commutative: true,
+               asm:         riscv.AFEQS,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
+                               {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                       },
+                       outputs: []outputInfo{
+                               {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
                        },
                },
        },
        {
-               name:    "CMPWUconst",
-               auxType: auxInt32,
-               argLen:  1,
-               asm:     s390x.ACMPWU,
+               name:        "FNES",
+               argLen:      2,
+               commutative: true,
+               asm:         riscv.AFNES,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
+                               {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                       },
+                       outputs: []outputInfo{
+                               {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
                        },
                },
        },
        {
-               name:   "FCMPS",
+               name:   "FLTS",
                argLen: 2,
-               asm:    s390x.ACEBR,
+               asm:    riscv.AFLTS,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
-                               {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+                               {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                       },
+                       outputs: []outputInfo{
+                               {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
                        },
                },
        },
        {
-               name:   "FCMP",
+               name:   "FLES",
                argLen: 2,
-               asm:    s390x.AFCMPU,
+               asm:    riscv.AFLES,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
-                               {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+                               {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                       },
+                       outputs: []outputInfo{
+                               {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
                        },
                },
        },
        {
-               name:   "LTDBR",
-               argLen: 1,
-               asm:    s390x.ALTDBR,
+               name:            "LoweredFMAXS",
+               argLen:          2,
+               commutative:     true,
+               resultNotInArgs: true,
+               asm:             riscv.AFMAXS,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+                               {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                       },
+                       outputs: []outputInfo{
+                               {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
                        },
                },
        },
        {
-               name:   "LTEBR",
-               argLen: 1,
-               asm:    s390x.ALTEBR,
+               name:            "LoweredFMINS",
+               argLen:          2,
+               commutative:     true,
+               resultNotInArgs: true,
+               asm:             riscv.AFMINS,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+                               {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                       },
+                       outputs: []outputInfo{
+                               {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
                        },
                },
        },
        {
-               name:   "SLD",
-               argLen: 2,
-               asm:    s390x.ASLD,
+               name:        "FADDD",
+               argLen:      2,
+               commutative: true,
+               asm:         riscv.AFADDD,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {1, 23550}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
-                               {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+                               {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
                        },
                        outputs: []outputInfo{
-                               {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+                               {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
                        },
                },
        },
        {
-               name:   "SLW",
+               name:   "FSUBD",
                argLen: 2,
-               asm:    s390x.ASLW,
+               asm:    riscv.AFSUBD,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {1, 23550}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
-                               {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+                               {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
                        },
                        outputs: []outputInfo{
-                               {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+                               {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
                        },
                },
        },
        {
-               name:    "SLDconst",
-               auxType: auxUInt8,
-               argLen:  1,
-               asm:     s390x.ASLD,
+               name:        "FMULD",
+               argLen:      2,
+               commutative: true,
+               asm:         riscv.AFMULD,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+                               {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
                        },
                        outputs: []outputInfo{
-                               {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+                               {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
                        },
                },
        },
        {
-               name:    "SLWconst",
-               auxType: auxUInt8,
-               argLen:  1,
-               asm:     s390x.ASLW,
+               name:   "FDIVD",
+               argLen: 2,
+               asm:    riscv.AFDIVD,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+                               {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
                        },
                        outputs: []outputInfo{
-                               {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+                               {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
                        },
                },
        },
        {
-               name:   "SRD",
-               argLen: 2,
-               asm:    s390x.ASRD,
+               name:        "FMADDD",
+               argLen:      3,
+               commutative: true,
+               asm:         riscv.AFMADDD,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {1, 23550}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
-                               {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+                               {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {2, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
                        },
                        outputs: []outputInfo{
-                               {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+                               {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
                        },
                },
        },
        {
-               name:   "SRW",
-               argLen: 2,
-               asm:    s390x.ASRW,
+               name:        "FMSUBD",
+               argLen:      3,
+               commutative: true,
+               asm:         riscv.AFMSUBD,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {1, 23550}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
-                               {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+                               {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {2, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
                        },
                        outputs: []outputInfo{
-                               {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+                               {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
                        },
                },
        },
        {
-               name:    "SRDconst",
-               auxType: auxUInt8,
-               argLen:  1,
-               asm:     s390x.ASRD,
+               name:        "FNMADDD",
+               argLen:      3,
+               commutative: true,
+               asm:         riscv.AFNMADDD,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+                               {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {2, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
                        },
                        outputs: []outputInfo{
-                               {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+                               {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
                        },
                },
        },
        {
-               name:    "SRWconst",
-               auxType: auxUInt8,
-               argLen:  1,
-               asm:     s390x.ASRW,
+               name:        "FNMSUBD",
+               argLen:      3,
+               commutative: true,
+               asm:         riscv.AFNMSUBD,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+                               {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {2, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
                        },
                        outputs: []outputInfo{
-                               {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+                               {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
                        },
                },
        },
        {
-               name:         "SRAD",
-               argLen:       2,
-               clobberFlags: true,
-               asm:          s390x.ASRAD,
+               name:   "FSQRTD",
+               argLen: 1,
+               asm:    riscv.AFSQRTD,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {1, 23550}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
-                               {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+                               {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
                        },
                        outputs: []outputInfo{
-                               {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+                               {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
                        },
                },
        },
        {
-               name:         "SRAW",
-               argLen:       2,
-               clobberFlags: true,
-               asm:          s390x.ASRAW,
+               name:   "FNEGD",
+               argLen: 1,
+               asm:    riscv.AFNEGD,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {1, 23550}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
-                               {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+                               {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
                        },
                        outputs: []outputInfo{
-                               {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+                               {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
                        },
                },
        },
        {
-               name:         "SRADconst",
-               auxType:      auxUInt8,
-               argLen:       1,
-               clobberFlags: true,
-               asm:          s390x.ASRAD,
+               name:   "FABSD",
+               argLen: 1,
+               asm:    riscv.AFABSD,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+                               {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
                        },
                        outputs: []outputInfo{
-                               {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+                               {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
                        },
                },
        },
        {
-               name:         "SRAWconst",
-               auxType:      auxUInt8,
-               argLen:       1,
-               clobberFlags: true,
-               asm:          s390x.ASRAW,
+               name:   "FSGNJD",
+               argLen: 2,
+               asm:    riscv.AFSGNJD,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+                               {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
                        },
                        outputs: []outputInfo{
-                               {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+                               {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
                        },
                },
        },
        {
-               name:   "RLLG",
-               argLen: 2,
-               asm:    s390x.ARLLG,
+               name:   "FMVDX",
+               argLen: 1,
+               asm:    riscv.AFMVDX,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {1, 23550}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
-                               {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+                               {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
                        },
                        outputs: []outputInfo{
-                               {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+                               {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
                        },
                },
        },
        {
-               name:   "RLL",
-               argLen: 2,
-               asm:    s390x.ARLL,
+               name:   "FCVTDW",
+               argLen: 1,
+               asm:    riscv.AFCVTDW,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {1, 23550}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
-                               {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+                               {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
                        },
                        outputs: []outputInfo{
-                               {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+                               {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
                        },
                },
        },
        {
-               name:    "RLLconst",
-               auxType: auxUInt8,
-               argLen:  1,
-               asm:     s390x.ARLL,
+               name:   "FCVTDL",
+               argLen: 1,
+               asm:    riscv.AFCVTDL,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+                               {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
                        },
                        outputs: []outputInfo{
-                               {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+                               {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
                        },
                },
        },
        {
-               name:         "RXSBG",
-               auxType:      auxS390XRotateParams,
-               argLen:       2,
-               resultInArg0: true,
-               clobberFlags: true,
-               asm:          s390x.ARXSBG,
+               name:   "FCVTWD",
+               argLen: 1,
+               asm:    riscv.AFCVTWD,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
-                               {1, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+                               {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
                        },
                        outputs: []outputInfo{
-                               {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+                               {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
                        },
                },
        },
        {
-               name:         "RISBGZ",
-               auxType:      auxS390XRotateParams,
-               argLen:       1,
-               clobberFlags: true,
-               asm:          s390x.ARISBGZ,
+               name:   "FCVTLD",
+               argLen: 1,
+               asm:    riscv.AFCVTLD,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+                               {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
                        },
                        outputs: []outputInfo{
-                               {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+                               {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
                        },
                },
        },
        {
-               name:         "NEG",
-               argLen:       1,
-               clobberFlags: true,
-               asm:          s390x.ANEG,
+               name:   "FCVTDS",
+               argLen: 1,
+               asm:    riscv.AFCVTDS,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+                               {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
                        },
                        outputs: []outputInfo{
-                               {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+                               {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
                        },
                },
        },
        {
-               name:         "NEGW",
-               argLen:       1,
-               clobberFlags: true,
-               asm:          s390x.ANEGW,
+               name:   "FCVTSD",
+               argLen: 1,
+               asm:    riscv.AFCVTSD,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+                               {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
                        },
                        outputs: []outputInfo{
-                               {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+                               {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
                        },
                },
        },
        {
-               name:         "NOT",
-               argLen:       1,
-               resultInArg0: true,
-               clobberFlags: true,
+               name:           "FMOVDload",
+               auxType:        auxSymOff,
+               argLen:         2,
+               faultOnNilArg0: true,
+               symEffect:      SymRead,
+               asm:            riscv.AMOVD,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+                               {0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB
                        },
                        outputs: []outputInfo{
-                               {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+                               {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
                        },
                },
        },
        {
-               name:         "NOTW",
-               argLen:       1,
-               resultInArg0: true,
-               clobberFlags: true,
+               name:           "FMOVDstore",
+               auxType:        auxSymOff,
+               argLen:         3,
+               faultOnNilArg0: true,
+               symEffect:      SymWrite,
+               asm:            riscv.AMOVD,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
-                       },
-                       outputs: []outputInfo{
-                               {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+                               {0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB
+                               {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
                        },
                },
        },
        {
-               name:   "FSQRT",
-               argLen: 1,
-               asm:    s390x.AFSQRT,
+               name:        "FEQD",
+               argLen:      2,
+               commutative: true,
+               asm:         riscv.AFEQD,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+                               {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
                        },
                        outputs: []outputInfo{
-                               {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+                               {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
                        },
                },
        },
        {
-               name:   "FSQRTS",
-               argLen: 1,
-               asm:    s390x.AFSQRTS,
+               name:        "FNED",
+               argLen:      2,
+               commutative: true,
+               asm:         riscv.AFNED,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+                               {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
                        },
                        outputs: []outputInfo{
-                               {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+                               {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
                        },
                },
        },
        {
-               name:         "LOCGR",
-               auxType:      auxS390XCCMask,
-               argLen:       3,
-               resultInArg0: true,
-               asm:          s390x.ALOCGR,
+               name:   "FLTD",
+               argLen: 2,
+               asm:    riscv.AFLTD,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
-                               {1, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+                               {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
                        },
                        outputs: []outputInfo{
-                               {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+                               {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
                        },
                },
        },
        {
-               name:   "MOVBreg",
-               argLen: 1,
-               asm:    s390x.AMOVB,
+               name:   "FLED",
+               argLen: 2,
+               asm:    riscv.AFLED,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
+                               {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
                        },
                        outputs: []outputInfo{
-                               {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+                               {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
                        },
                },
        },
        {
-               name:   "MOVBZreg",
-               argLen: 1,
-               asm:    s390x.AMOVBZ,
+               name:            "LoweredFMIND",
+               argLen:          2,
+               commutative:     true,
+               resultNotInArgs: true,
+               asm:             riscv.AFMIND,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
+                               {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
                        },
                        outputs: []outputInfo{
-                               {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+                               {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
                        },
                },
        },
        {
-               name:   "MOVHreg",
-               argLen: 1,
-               asm:    s390x.AMOVH,
+               name:            "LoweredFMAXD",
+               argLen:          2,
+               commutative:     true,
+               resultNotInArgs: true,
+               asm:             riscv.AFMAXD,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
+                               {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
                        },
                        outputs: []outputInfo{
-                               {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+                               {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
                        },
                },
        },
+
        {
-               name:   "MOVHZreg",
-               argLen: 1,
-               asm:    s390x.AMOVHZ,
+               name:         "FADDS",
+               argLen:       2,
+               commutative:  true,
+               resultInArg0: true,
+               asm:          s390x.AFADDS,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
+                               {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+                               {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
                        },
                        outputs: []outputInfo{
-                               {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+                               {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
                        },
                },
        },
        {
-               name:   "MOVWreg",
-               argLen: 1,
-               asm:    s390x.AMOVW,
+               name:         "FADD",
+               argLen:       2,
+               commutative:  true,
+               resultInArg0: true,
+               asm:          s390x.AFADD,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
+                               {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+                               {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
                        },
                        outputs: []outputInfo{
-                               {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+                               {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
                        },
                },
        },
        {
-               name:   "MOVWZreg",
-               argLen: 1,
-               asm:    s390x.AMOVWZ,
+               name:         "FSUBS",
+               argLen:       2,
+               resultInArg0: true,
+               asm:          s390x.AFSUBS,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
+                               {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+                               {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
                        },
                        outputs: []outputInfo{
-                               {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+                               {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
                        },
                },
        },
        {
-               name:              "MOVDconst",
-               auxType:           auxInt64,
-               argLen:            0,
-               rematerializeable: true,
-               asm:               s390x.AMOVD,
+               name:         "FSUB",
+               argLen:       2,
+               resultInArg0: true,
+               asm:          s390x.AFSUB,
                reg: regInfo{
+                       inputs: []inputInfo{
+                               {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+                               {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+                       },
                        outputs: []outputInfo{
-                               {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+                               {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
                        },
                },
        },
        {
-               name:   "LDGR",
-               argLen: 1,
-               asm:    s390x.ALDGR,
+               name:         "FMULS",
+               argLen:       2,
+               commutative:  true,
+               resultInArg0: true,
+               asm:          s390x.AFMULS,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+                               {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+                               {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
                        },
                        outputs: []outputInfo{
                                {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
@@ -50401,82 +52294,89 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:   "LGDR",
-               argLen: 1,
-               asm:    s390x.ALGDR,
+               name:         "FMUL",
+               argLen:       2,
+               commutative:  true,
+               resultInArg0: true,
+               asm:          s390x.AFMUL,
                reg: regInfo{
                        inputs: []inputInfo{
                                {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+                               {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
                        },
                        outputs: []outputInfo{
-                               {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+                               {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
                        },
                },
        },
        {
-               name:         "CFDBRA",
-               argLen:       1,
-               clobberFlags: true,
-               asm:          s390x.ACFDBRA,
+               name:         "FDIVS",
+               argLen:       2,
+               resultInArg0: true,
+               asm:          s390x.AFDIVS,
                reg: regInfo{
                        inputs: []inputInfo{
                                {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+                               {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
                        },
                        outputs: []outputInfo{
-                               {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+                               {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
                        },
                },
        },
        {
-               name:         "CGDBRA",
-               argLen:       1,
-               clobberFlags: true,
-               asm:          s390x.ACGDBRA,
+               name:         "FDIV",
+               argLen:       2,
+               resultInArg0: true,
+               asm:          s390x.AFDIV,
                reg: regInfo{
                        inputs: []inputInfo{
                                {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+                               {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
                        },
                        outputs: []outputInfo{
-                               {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+                               {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
                        },
                },
        },
        {
-               name:         "CFEBRA",
+               name:         "FNEGS",
                argLen:       1,
                clobberFlags: true,
-               asm:          s390x.ACFEBRA,
+               asm:          s390x.AFNEGS,
                reg: regInfo{
                        inputs: []inputInfo{
                                {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
                        },
                        outputs: []outputInfo{
-                               {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+                               {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
                        },
                },
        },
        {
-               name:         "CGEBRA",
+               name:         "FNEG",
                argLen:       1,
                clobberFlags: true,
-               asm:          s390x.ACGEBRA,
+               asm:          s390x.AFNEG,
                reg: regInfo{
                        inputs: []inputInfo{
                                {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
                        },
                        outputs: []outputInfo{
-                               {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+                               {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
                        },
                },
        },
        {
-               name:         "CEFBRA",
-               argLen:       1,
-               clobberFlags: true,
-               asm:          s390x.ACEFBRA,
+               name:         "FMADDS",
+               argLen:       3,
+               resultInArg0: true,
+               asm:          s390x.AFMADDS,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+                               {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+                               {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+                               {2, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
                        },
                        outputs: []outputInfo{
                                {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
@@ -50484,13 +52384,15 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:         "CDFBRA",
-               argLen:       1,
-               clobberFlags: true,
-               asm:          s390x.ACDFBRA,
+               name:         "FMADD",
+               argLen:       3,
+               resultInArg0: true,
+               asm:          s390x.AFMADD,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+                               {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+                               {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+                               {2, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
                        },
                        outputs: []outputInfo{
                                {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
@@ -50498,13 +52400,15 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:         "CEGBRA",
-               argLen:       1,
-               clobberFlags: true,
-               asm:          s390x.ACEGBRA,
+               name:         "FMSUBS",
+               argLen:       3,
+               resultInArg0: true,
+               asm:          s390x.AFMSUBS,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+                               {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+                               {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+                               {2, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
                        },
                        outputs: []outputInfo{
                                {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
@@ -50512,13 +52416,15 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:         "CDGBRA",
-               argLen:       1,
-               clobberFlags: true,
-               asm:          s390x.ACDGBRA,
+               name:         "FMSUB",
+               argLen:       3,
+               resultInArg0: true,
+               asm:          s390x.AFMSUB,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+                               {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+                               {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+                               {2, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
                        },
                        outputs: []outputInfo{
                                {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
@@ -50526,69 +52432,69 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:         "CLFEBR",
-               argLen:       1,
-               clobberFlags: true,
-               asm:          s390x.ACLFEBR,
+               name:   "LPDFR",
+               argLen: 1,
+               asm:    s390x.ALPDFR,
                reg: regInfo{
                        inputs: []inputInfo{
                                {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
                        },
                        outputs: []outputInfo{
-                               {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+                               {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
                        },
                },
        },
        {
-               name:         "CLFDBR",
-               argLen:       1,
-               clobberFlags: true,
-               asm:          s390x.ACLFDBR,
+               name:   "LNDFR",
+               argLen: 1,
+               asm:    s390x.ALNDFR,
                reg: regInfo{
                        inputs: []inputInfo{
                                {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
                        },
                        outputs: []outputInfo{
-                               {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+                               {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
                        },
                },
        },
        {
-               name:         "CLGEBR",
-               argLen:       1,
-               clobberFlags: true,
-               asm:          s390x.ACLGEBR,
+               name:   "CPSDR",
+               argLen: 2,
+               asm:    s390x.ACPSDR,
                reg: regInfo{
                        inputs: []inputInfo{
                                {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+                               {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
                        },
                        outputs: []outputInfo{
-                               {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+                               {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
                        },
                },
        },
        {
-               name:         "CLGDBR",
-               argLen:       1,
-               clobberFlags: true,
-               asm:          s390x.ACLGDBR,
+               name:    "FIDBR",
+               auxType: auxInt8,
+               argLen:  1,
+               asm:     s390x.AFIDBR,
                reg: regInfo{
                        inputs: []inputInfo{
                                {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
                        },
                        outputs: []outputInfo{
-                               {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+                               {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
                        },
                },
        },
        {
-               name:         "CELFBR",
-               argLen:       1,
-               clobberFlags: true,
-               asm:          s390x.ACELFBR,
+               name:           "FMOVSload",
+               auxType:        auxSymOff,
+               argLen:         2,
+               faultOnNilArg0: true,
+               symEffect:      SymRead,
+               asm:            s390x.AFMOVS,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+                               {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB
                        },
                        outputs: []outputInfo{
                                {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
@@ -50596,13 +52502,15 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:         "CDLFBR",
-               argLen:       1,
-               clobberFlags: true,
-               asm:          s390x.ACDLFBR,
+               name:           "FMOVDload",
+               auxType:        auxSymOff,
+               argLen:         2,
+               faultOnNilArg0: true,
+               symEffect:      SymRead,
+               asm:            s390x.AFMOVD,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+                               {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB
                        },
                        outputs: []outputInfo{
                                {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
@@ -50610,40 +52518,39 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:         "CELGBR",
-               argLen:       1,
-               clobberFlags: true,
-               asm:          s390x.ACELGBR,
+               name:              "FMOVSconst",
+               auxType:           auxFloat32,
+               argLen:            0,
+               rematerializeable: true,
+               asm:               s390x.AFMOVS,
                reg: regInfo{
-                       inputs: []inputInfo{
-                               {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
-                       },
                        outputs: []outputInfo{
                                {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
                        },
                },
        },
        {
-               name:         "CDLGBR",
-               argLen:       1,
-               clobberFlags: true,
-               asm:          s390x.ACDLGBR,
+               name:              "FMOVDconst",
+               auxType:           auxFloat64,
+               argLen:            0,
+               rematerializeable: true,
+               asm:               s390x.AFMOVD,
                reg: regInfo{
-                       inputs: []inputInfo{
-                               {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
-                       },
                        outputs: []outputInfo{
                                {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
                        },
                },
        },
        {
-               name:   "LEDBR",
-               argLen: 1,
-               asm:    s390x.ALEDBR,
+               name:      "FMOVSloadidx",
+               auxType:   auxSymOff,
+               argLen:    3,
+               symEffect: SymRead,
+               asm:       s390x.AFMOVS,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+                               {0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
+                               {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
                        },
                        outputs: []outputInfo{
                                {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
@@ -50651,12 +52558,15 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:   "LDEBR",
-               argLen: 1,
-               asm:    s390x.ALDEBR,
+               name:      "FMOVDloadidx",
+               auxType:   auxSymOff,
+               argLen:    3,
+               symEffect: SymRead,
+               asm:       s390x.AFMOVD,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+                               {0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
+                               {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
                        },
                        outputs: []outputInfo{
                                {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
@@ -50664,45 +52574,71 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:              "MOVDaddr",
-               auxType:           auxSymOff,
-               argLen:            1,
-               rematerializeable: true,
-               symEffect:         SymAddr,
+               name:           "FMOVSstore",
+               auxType:        auxSymOff,
+               argLen:         3,
+               faultOnNilArg0: true,
+               symEffect:      SymWrite,
+               asm:            s390x.AFMOVS,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 4295000064}, // SP SB
+                               {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB
+                               {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
                        },
-                       outputs: []outputInfo{
-                               {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+               },
+       },
+       {
+               name:           "FMOVDstore",
+               auxType:        auxSymOff,
+               argLen:         3,
+               faultOnNilArg0: true,
+               symEffect:      SymWrite,
+               asm:            s390x.AFMOVD,
+               reg: regInfo{
+                       inputs: []inputInfo{
+                               {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB
+                               {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
                        },
                },
        },
        {
-               name:      "MOVDaddridx",
+               name:      "FMOVSstoreidx",
                auxType:   auxSymOff,
-               argLen:    2,
-               symEffect: SymAddr,
+               argLen:    4,
+               symEffect: SymWrite,
+               asm:       s390x.AFMOVS,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 4295000064}, // SP SB
+                               {0, 56318},      // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
                                {1, 56318},      // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
+                               {2, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
                        },
-                       outputs: []outputInfo{
-                               {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+               },
+       },
+       {
+               name:      "FMOVDstoreidx",
+               auxType:   auxSymOff,
+               argLen:    4,
+               symEffect: SymWrite,
+               asm:       s390x.AFMOVD,
+               reg: regInfo{
+                       inputs: []inputInfo{
+                               {0, 56318},      // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
+                               {1, 56318},      // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
+                               {2, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
                        },
                },
        },
        {
-               name:           "MOVBZload",
-               auxType:        auxSymOff,
-               argLen:         2,
-               faultOnNilArg0: true,
-               symEffect:      SymRead,
-               asm:            s390x.AMOVBZ,
+               name:         "ADD",
+               argLen:       2,
+               commutative:  true,
+               clobberFlags: true,
+               asm:          s390x.AADD,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB
+                               {1, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+                               {0, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
                        },
                        outputs: []outputInfo{
                                {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
@@ -50710,15 +52646,15 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:           "MOVBload",
-               auxType:        auxSymOff,
-               argLen:         2,
-               faultOnNilArg0: true,
-               symEffect:      SymRead,
-               asm:            s390x.AMOVB,
+               name:         "ADDW",
+               argLen:       2,
+               commutative:  true,
+               clobberFlags: true,
+               asm:          s390x.AADDW,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB
+                               {1, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+                               {0, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
                        },
                        outputs: []outputInfo{
                                {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
@@ -50726,15 +52662,14 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:           "MOVHZload",
-               auxType:        auxSymOff,
-               argLen:         2,
-               faultOnNilArg0: true,
-               symEffect:      SymRead,
-               asm:            s390x.AMOVHZ,
+               name:         "ADDconst",
+               auxType:      auxInt32,
+               argLen:       1,
+               clobberFlags: true,
+               asm:          s390x.AADD,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB
+                               {0, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
                        },
                        outputs: []outputInfo{
                                {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
@@ -50742,15 +52677,14 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:           "MOVHload",
-               auxType:        auxSymOff,
-               argLen:         2,
-               faultOnNilArg0: true,
-               symEffect:      SymRead,
-               asm:            s390x.AMOVH,
+               name:         "ADDWconst",
+               auxType:      auxInt32,
+               argLen:       1,
+               clobberFlags: true,
+               asm:          s390x.AADDW,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB
+                               {0, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
                        },
                        outputs: []outputInfo{
                                {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
@@ -50758,15 +52692,18 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:           "MOVWZload",
+               name:           "ADDload",
                auxType:        auxSymOff,
-               argLen:         2,
-               faultOnNilArg0: true,
+               argLen:         3,
+               resultInArg0:   true,
+               clobberFlags:   true,
+               faultOnNilArg1: true,
                symEffect:      SymRead,
-               asm:            s390x.AMOVWZ,
+               asm:            s390x.AADD,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB
+                               {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+                               {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
                        },
                        outputs: []outputInfo{
                                {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
@@ -50774,15 +52711,18 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:           "MOVWload",
+               name:           "ADDWload",
                auxType:        auxSymOff,
-               argLen:         2,
-               faultOnNilArg0: true,
+               argLen:         3,
+               resultInArg0:   true,
+               clobberFlags:   true,
+               faultOnNilArg1: true,
                symEffect:      SymRead,
-               asm:            s390x.AMOVW,
+               asm:            s390x.AADDW,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB
+                               {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+                               {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
                        },
                        outputs: []outputInfo{
                                {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
@@ -50790,15 +52730,14 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:           "MOVDload",
-               auxType:        auxSymOff,
-               argLen:         2,
-               faultOnNilArg0: true,
-               symEffect:      SymRead,
-               asm:            s390x.AMOVD,
+               name:         "SUB",
+               argLen:       2,
+               clobberFlags: true,
+               asm:          s390x.ASUB,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB
+                               {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+                               {1, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
                        },
                        outputs: []outputInfo{
                                {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
@@ -50806,12 +52745,14 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:   "MOVWBR",
-               argLen: 1,
-               asm:    s390x.AMOVWBR,
+               name:         "SUBW",
+               argLen:       2,
+               clobberFlags: true,
+               asm:          s390x.ASUBW,
                reg: regInfo{
                        inputs: []inputInfo{
                                {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+                               {1, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
                        },
                        outputs: []outputInfo{
                                {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
@@ -50819,9 +52760,12 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:   "MOVDBR",
-               argLen: 1,
-               asm:    s390x.AMOVDBR,
+               name:         "SUBconst",
+               auxType:      auxInt32,
+               argLen:       1,
+               resultInArg0: true,
+               clobberFlags: true,
+               asm:          s390x.ASUB,
                reg: regInfo{
                        inputs: []inputInfo{
                                {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
@@ -50832,15 +52776,15 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:           "MOVHBRload",
-               auxType:        auxSymOff,
-               argLen:         2,
-               faultOnNilArg0: true,
-               symEffect:      SymRead,
-               asm:            s390x.AMOVHBR,
+               name:         "SUBWconst",
+               auxType:      auxInt32,
+               argLen:       1,
+               resultInArg0: true,
+               clobberFlags: true,
+               asm:          s390x.ASUBW,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB
+                               {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
                        },
                        outputs: []outputInfo{
                                {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
@@ -50848,15 +52792,18 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:           "MOVWBRload",
+               name:           "SUBload",
                auxType:        auxSymOff,
-               argLen:         2,
-               faultOnNilArg0: true,
+               argLen:         3,
+               resultInArg0:   true,
+               clobberFlags:   true,
+               faultOnNilArg1: true,
                symEffect:      SymRead,
-               asm:            s390x.AMOVWBR,
+               asm:            s390x.ASUB,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB
+                               {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+                               {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
                        },
                        outputs: []outputInfo{
                                {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
@@ -50864,15 +52811,18 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:           "MOVDBRload",
+               name:           "SUBWload",
                auxType:        auxSymOff,
-               argLen:         2,
-               faultOnNilArg0: true,
+               argLen:         3,
+               resultInArg0:   true,
+               clobberFlags:   true,
+               faultOnNilArg1: true,
                symEffect:      SymRead,
-               asm:            s390x.AMOVDBR,
+               asm:            s390x.ASUBW,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB
+                               {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+                               {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
                        },
                        outputs: []outputInfo{
                                {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
@@ -50880,266 +52830,291 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:           "MOVBstore",
-               auxType:        auxSymOff,
-               argLen:         3,
-               faultOnNilArg0: true,
-               symEffect:      SymWrite,
-               asm:            s390x.AMOVB,
+               name:         "MULLD",
+               argLen:       2,
+               commutative:  true,
+               resultInArg0: true,
+               clobberFlags: true,
+               asm:          s390x.AMULLD,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB
-                               {1, 56319},      // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
+                               {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+                               {1, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+                       },
+                       outputs: []outputInfo{
+                               {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
                        },
                },
        },
        {
-               name:           "MOVHstore",
-               auxType:        auxSymOff,
-               argLen:         3,
-               faultOnNilArg0: true,
-               symEffect:      SymWrite,
-               asm:            s390x.AMOVH,
+               name:         "MULLW",
+               argLen:       2,
+               commutative:  true,
+               resultInArg0: true,
+               clobberFlags: true,
+               asm:          s390x.AMULLW,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB
-                               {1, 56319},      // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
+                               {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+                               {1, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+                       },
+                       outputs: []outputInfo{
+                               {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
                        },
                },
        },
        {
-               name:           "MOVWstore",
-               auxType:        auxSymOff,
-               argLen:         3,
-               faultOnNilArg0: true,
-               symEffect:      SymWrite,
-               asm:            s390x.AMOVW,
+               name:         "MULLDconst",
+               auxType:      auxInt32,
+               argLen:       1,
+               resultInArg0: true,
+               clobberFlags: true,
+               asm:          s390x.AMULLD,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB
-                               {1, 56319},      // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
+                               {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+                       },
+                       outputs: []outputInfo{
+                               {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
                        },
                },
        },
        {
-               name:           "MOVDstore",
-               auxType:        auxSymOff,
-               argLen:         3,
-               faultOnNilArg0: true,
-               symEffect:      SymWrite,
-               asm:            s390x.AMOVD,
+               name:         "MULLWconst",
+               auxType:      auxInt32,
+               argLen:       1,
+               resultInArg0: true,
+               clobberFlags: true,
+               asm:          s390x.AMULLW,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB
-                               {1, 56319},      // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
+                               {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+                       },
+                       outputs: []outputInfo{
+                               {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
                        },
                },
        },
        {
-               name:           "MOVHBRstore",
+               name:           "MULLDload",
                auxType:        auxSymOff,
                argLen:         3,
-               faultOnNilArg0: true,
-               symEffect:      SymWrite,
-               asm:            s390x.AMOVHBR,
+               resultInArg0:   true,
+               clobberFlags:   true,
+               faultOnNilArg1: true,
+               symEffect:      SymRead,
+               asm:            s390x.AMULLD,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
-                               {1, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
+                               {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+                               {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
+                       },
+                       outputs: []outputInfo{
+                               {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
                        },
                },
        },
        {
-               name:           "MOVWBRstore",
+               name:           "MULLWload",
                auxType:        auxSymOff,
                argLen:         3,
-               faultOnNilArg0: true,
-               symEffect:      SymWrite,
-               asm:            s390x.AMOVWBR,
+               resultInArg0:   true,
+               clobberFlags:   true,
+               faultOnNilArg1: true,
+               symEffect:      SymRead,
+               asm:            s390x.AMULLW,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
-                               {1, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
+                               {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+                               {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
+                       },
+                       outputs: []outputInfo{
+                               {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
                        },
                },
        },
        {
-               name:           "MOVDBRstore",
-               auxType:        auxSymOff,
-               argLen:         3,
-               faultOnNilArg0: true,
-               symEffect:      SymWrite,
-               asm:            s390x.AMOVDBR,
+               name:         "MULHD",
+               argLen:       2,
+               commutative:  true,
+               resultInArg0: true,
+               clobberFlags: true,
+               asm:          s390x.AMULHD,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
-                               {1, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
+                               {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+                               {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+                       },
+                       clobbers: 2048, // R11
+                       outputs: []outputInfo{
+                               {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
                        },
                },
        },
        {
-               name:           "MVC",
-               auxType:        auxSymValAndOff,
-               argLen:         3,
-               clobberFlags:   true,
-               faultOnNilArg0: true,
-               faultOnNilArg1: true,
-               symEffect:      SymNone,
-               asm:            s390x.AMVC,
+               name:         "MULHDU",
+               argLen:       2,
+               commutative:  true,
+               resultInArg0: true,
+               clobberFlags: true,
+               asm:          s390x.AMULHDU,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
-                               {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
+                               {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+                               {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+                       },
+                       clobbers: 2048, // R11
+                       outputs: []outputInfo{
+                               {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
                        },
                },
        },
        {
-               name:        "MOVBZloadidx",
-               auxType:     auxSymOff,
-               argLen:      3,
-               commutative: true,
-               symEffect:   SymRead,
-               asm:         s390x.AMOVBZ,
+               name:         "DIVD",
+               argLen:       2,
+               resultInArg0: true,
+               clobberFlags: true,
+               asm:          s390x.ADIVD,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {1, 56318},      // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
-                               {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB
+                               {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+                               {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
                        },
+                       clobbers: 2048, // R11
                        outputs: []outputInfo{
-                               {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+                               {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
                        },
                },
        },
        {
-               name:        "MOVBloadidx",
-               auxType:     auxSymOff,
-               argLen:      3,
-               commutative: true,
-               symEffect:   SymRead,
-               asm:         s390x.AMOVB,
+               name:         "DIVW",
+               argLen:       2,
+               resultInArg0: true,
+               clobberFlags: true,
+               asm:          s390x.ADIVW,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {1, 56318},      // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
-                               {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB
+                               {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+                               {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
                        },
+                       clobbers: 2048, // R11
                        outputs: []outputInfo{
-                               {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+                               {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
                        },
                },
        },
        {
-               name:        "MOVHZloadidx",
-               auxType:     auxSymOff,
-               argLen:      3,
-               commutative: true,
-               symEffect:   SymRead,
-               asm:         s390x.AMOVHZ,
+               name:         "DIVDU",
+               argLen:       2,
+               resultInArg0: true,
+               clobberFlags: true,
+               asm:          s390x.ADIVDU,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {1, 56318},      // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
-                               {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB
+                               {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+                               {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
                        },
+                       clobbers: 2048, // R11
                        outputs: []outputInfo{
-                               {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+                               {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
                        },
                },
        },
        {
-               name:        "MOVHloadidx",
-               auxType:     auxSymOff,
-               argLen:      3,
-               commutative: true,
-               symEffect:   SymRead,
-               asm:         s390x.AMOVH,
+               name:         "DIVWU",
+               argLen:       2,
+               resultInArg0: true,
+               clobberFlags: true,
+               asm:          s390x.ADIVWU,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {1, 56318},      // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
-                               {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB
+                               {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+                               {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
                        },
+                       clobbers: 2048, // R11
                        outputs: []outputInfo{
-                               {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+                               {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
                        },
                },
        },
        {
-               name:        "MOVWZloadidx",
-               auxType:     auxSymOff,
-               argLen:      3,
-               commutative: true,
-               symEffect:   SymRead,
-               asm:         s390x.AMOVWZ,
+               name:         "MODD",
+               argLen:       2,
+               resultInArg0: true,
+               clobberFlags: true,
+               asm:          s390x.AMODD,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {1, 56318},      // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
-                               {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB
+                               {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+                               {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
                        },
+                       clobbers: 2048, // R11
                        outputs: []outputInfo{
-                               {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+                               {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
                        },
                },
        },
        {
-               name:        "MOVWloadidx",
-               auxType:     auxSymOff,
-               argLen:      3,
-               commutative: true,
-               symEffect:   SymRead,
-               asm:         s390x.AMOVW,
+               name:         "MODW",
+               argLen:       2,
+               resultInArg0: true,
+               clobberFlags: true,
+               asm:          s390x.AMODW,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {1, 56318},      // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
-                               {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB
+                               {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+                               {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
                        },
+                       clobbers: 2048, // R11
                        outputs: []outputInfo{
-                               {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+                               {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
                        },
                },
        },
        {
-               name:        "MOVDloadidx",
-               auxType:     auxSymOff,
-               argLen:      3,
-               commutative: true,
-               symEffect:   SymRead,
-               asm:         s390x.AMOVD,
+               name:         "MODDU",
+               argLen:       2,
+               resultInArg0: true,
+               clobberFlags: true,
+               asm:          s390x.AMODDU,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {1, 56318},      // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
-                               {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB
+                               {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+                               {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
                        },
+                       clobbers: 2048, // R11
                        outputs: []outputInfo{
-                               {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+                               {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
                        },
                },
        },
        {
-               name:        "MOVHBRloadidx",
-               auxType:     auxSymOff,
-               argLen:      3,
-               commutative: true,
-               symEffect:   SymRead,
-               asm:         s390x.AMOVHBR,
+               name:         "MODWU",
+               argLen:       2,
+               resultInArg0: true,
+               clobberFlags: true,
+               asm:          s390x.AMODWU,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {1, 56318},      // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
-                               {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB
+                               {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
+                               {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
                        },
+                       clobbers: 2048, // R11
                        outputs: []outputInfo{
-                               {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+                               {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
                        },
                },
        },
        {
-               name:        "MOVWBRloadidx",
-               auxType:     auxSymOff,
-               argLen:      3,
-               commutative: true,
-               symEffect:   SymRead,
-               asm:         s390x.AMOVWBR,
+               name:         "AND",
+               argLen:       2,
+               commutative:  true,
+               clobberFlags: true,
+               asm:          s390x.AAND,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {1, 56318},      // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
-                               {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB
+                               {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+                               {1, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
                        },
                        outputs: []outputInfo{
                                {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
@@ -51147,16 +53122,15 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:        "MOVDBRloadidx",
-               auxType:     auxSymOff,
-               argLen:      3,
-               commutative: true,
-               symEffect:   SymRead,
-               asm:         s390x.AMOVDBR,
+               name:         "ANDW",
+               argLen:       2,
+               commutative:  true,
+               clobberFlags: true,
+               asm:          s390x.AANDW,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {1, 56318},      // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
-                               {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB
+                               {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+                               {1, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
                        },
                        outputs: []outputInfo{
                                {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
@@ -51164,392 +53138,491 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:        "MOVBstoreidx",
-               auxType:     auxSymOff,
-               argLen:      4,
-               commutative: true,
-               symEffect:   SymWrite,
-               asm:         s390x.AMOVB,
+               name:         "ANDconst",
+               auxType:      auxInt64,
+               argLen:       1,
+               resultInArg0: true,
+               clobberFlags: true,
+               asm:          s390x.AAND,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
-                               {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
-                               {2, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
+                               {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+                       },
+                       outputs: []outputInfo{
+                               {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
                        },
                },
        },
        {
-               name:        "MOVHstoreidx",
-               auxType:     auxSymOff,
-               argLen:      4,
-               commutative: true,
-               symEffect:   SymWrite,
-               asm:         s390x.AMOVH,
+               name:         "ANDWconst",
+               auxType:      auxInt32,
+               argLen:       1,
+               resultInArg0: true,
+               clobberFlags: true,
+               asm:          s390x.AANDW,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
-                               {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
-                               {2, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
+                               {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+                       },
+                       outputs: []outputInfo{
+                               {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
                        },
                },
        },
        {
-               name:        "MOVWstoreidx",
-               auxType:     auxSymOff,
-               argLen:      4,
-               commutative: true,
-               symEffect:   SymWrite,
-               asm:         s390x.AMOVW,
+               name:           "ANDload",
+               auxType:        auxSymOff,
+               argLen:         3,
+               resultInArg0:   true,
+               clobberFlags:   true,
+               faultOnNilArg1: true,
+               symEffect:      SymRead,
+               asm:            s390x.AAND,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
+                               {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
                                {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
-                               {2, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
+                       },
+                       outputs: []outputInfo{
+                               {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
                        },
                },
        },
        {
-               name:        "MOVDstoreidx",
-               auxType:     auxSymOff,
-               argLen:      4,
-               commutative: true,
-               symEffect:   SymWrite,
-               asm:         s390x.AMOVD,
+               name:           "ANDWload",
+               auxType:        auxSymOff,
+               argLen:         3,
+               resultInArg0:   true,
+               clobberFlags:   true,
+               faultOnNilArg1: true,
+               symEffect:      SymRead,
+               asm:            s390x.AANDW,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
+                               {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
                                {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
-                               {2, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
+                       },
+                       outputs: []outputInfo{
+                               {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
                        },
                },
        },
        {
-               name:        "MOVHBRstoreidx",
-               auxType:     auxSymOff,
-               argLen:      4,
-               commutative: true,
-               symEffect:   SymWrite,
-               asm:         s390x.AMOVHBR,
+               name:         "OR",
+               argLen:       2,
+               commutative:  true,
+               clobberFlags: true,
+               asm:          s390x.AOR,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
-                               {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
-                               {2, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
+                               {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+                               {1, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+                       },
+                       outputs: []outputInfo{
+                               {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
                        },
                },
        },
        {
-               name:        "MOVWBRstoreidx",
-               auxType:     auxSymOff,
-               argLen:      4,
-               commutative: true,
-               symEffect:   SymWrite,
-               asm:         s390x.AMOVWBR,
+               name:         "ORW",
+               argLen:       2,
+               commutative:  true,
+               clobberFlags: true,
+               asm:          s390x.AORW,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
-                               {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
-                               {2, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
+                               {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+                               {1, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+                       },
+                       outputs: []outputInfo{
+                               {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
                        },
                },
        },
        {
-               name:        "MOVDBRstoreidx",
-               auxType:     auxSymOff,
-               argLen:      4,
-               commutative: true,
-               symEffect:   SymWrite,
-               asm:         s390x.AMOVDBR,
+               name:         "ORconst",
+               auxType:      auxInt64,
+               argLen:       1,
+               resultInArg0: true,
+               clobberFlags: true,
+               asm:          s390x.AOR,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
-                               {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
-                               {2, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
+                               {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+                       },
+                       outputs: []outputInfo{
+                               {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
                        },
                },
        },
        {
-               name:           "MOVBstoreconst",
-               auxType:        auxSymValAndOff,
-               argLen:         2,
-               faultOnNilArg0: true,
-               symEffect:      SymWrite,
-               asm:            s390x.AMOVB,
+               name:         "ORWconst",
+               auxType:      auxInt32,
+               argLen:       1,
+               resultInArg0: true,
+               clobberFlags: true,
+               asm:          s390x.AORW,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB
+                               {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+                       },
+                       outputs: []outputInfo{
+                               {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
                        },
                },
        },
        {
-               name:           "MOVHstoreconst",
-               auxType:        auxSymValAndOff,
-               argLen:         2,
-               faultOnNilArg0: true,
-               symEffect:      SymWrite,
-               asm:            s390x.AMOVH,
+               name:           "ORload",
+               auxType:        auxSymOff,
+               argLen:         3,
+               resultInArg0:   true,
+               clobberFlags:   true,
+               faultOnNilArg1: true,
+               symEffect:      SymRead,
+               asm:            s390x.AOR,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB
+                               {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+                               {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
+                       },
+                       outputs: []outputInfo{
+                               {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
                        },
                },
        },
        {
-               name:           "MOVWstoreconst",
-               auxType:        auxSymValAndOff,
-               argLen:         2,
-               faultOnNilArg0: true,
-               symEffect:      SymWrite,
-               asm:            s390x.AMOVW,
+               name:           "ORWload",
+               auxType:        auxSymOff,
+               argLen:         3,
+               resultInArg0:   true,
+               clobberFlags:   true,
+               faultOnNilArg1: true,
+               symEffect:      SymRead,
+               asm:            s390x.AORW,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB
+                               {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+                               {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
+                       },
+                       outputs: []outputInfo{
+                               {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
                        },
                },
        },
        {
-               name:           "MOVDstoreconst",
-               auxType:        auxSymValAndOff,
-               argLen:         2,
-               faultOnNilArg0: true,
-               symEffect:      SymWrite,
-               asm:            s390x.AMOVD,
+               name:         "XOR",
+               argLen:       2,
+               commutative:  true,
+               clobberFlags: true,
+               asm:          s390x.AXOR,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB
+                               {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+                               {1, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+                       },
+                       outputs: []outputInfo{
+                               {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
                        },
                },
        },
        {
-               name:           "CLEAR",
-               auxType:        auxSymValAndOff,
-               argLen:         2,
-               clobberFlags:   true,
-               faultOnNilArg0: true,
-               symEffect:      SymWrite,
-               asm:            s390x.ACLEAR,
+               name:         "XORW",
+               argLen:       2,
+               commutative:  true,
+               clobberFlags: true,
+               asm:          s390x.AXORW,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 23550}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+                               {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+                               {1, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+                       },
+                       outputs: []outputInfo{
+                               {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
                        },
                },
        },
        {
-               name:         "CALLstatic",
-               auxType:      auxCallOff,
+               name:         "XORconst",
+               auxType:      auxInt64,
                argLen:       1,
+               resultInArg0: true,
                clobberFlags: true,
-               call:         true,
+               asm:          s390x.AXOR,
                reg: regInfo{
-                       clobbers: 4294933503, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 g R14 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+                       inputs: []inputInfo{
+                               {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+                       },
+                       outputs: []outputInfo{
+                               {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+                       },
                },
        },
        {
-               name:         "CALLtail",
-               auxType:      auxCallOff,
+               name:         "XORWconst",
+               auxType:      auxInt32,
                argLen:       1,
+               resultInArg0: true,
                clobberFlags: true,
-               call:         true,
-               tailCall:     true,
+               asm:          s390x.AXORW,
                reg: regInfo{
-                       clobbers: 4294933503, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 g R14 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+                       inputs: []inputInfo{
+                               {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+                       },
+                       outputs: []outputInfo{
+                               {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+                       },
                },
        },
        {
-               name:         "CALLclosure",
-               auxType:      auxCallOff,
-               argLen:       3,
-               clobberFlags: true,
-               call:         true,
+               name:           "XORload",
+               auxType:        auxSymOff,
+               argLen:         3,
+               resultInArg0:   true,
+               clobberFlags:   true,
+               faultOnNilArg1: true,
+               symEffect:      SymRead,
+               asm:            s390x.AXOR,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {1, 4096},  // R12
-                               {0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
+                               {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+                               {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
+                       },
+                       outputs: []outputInfo{
+                               {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
                        },
-                       clobbers: 4294933503, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 g R14 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
                },
        },
        {
-               name:         "CALLinter",
-               auxType:      auxCallOff,
-               argLen:       2,
-               clobberFlags: true,
-               call:         true,
+               name:           "XORWload",
+               auxType:        auxSymOff,
+               argLen:         3,
+               resultInArg0:   true,
+               clobberFlags:   true,
+               faultOnNilArg1: true,
+               symEffect:      SymRead,
+               asm:            s390x.AXORW,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 23550}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+                               {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+                               {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
+                       },
+                       outputs: []outputInfo{
+                               {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
                        },
-                       clobbers: 4294933503, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 g R14 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
                },
        },
        {
-               name:   "InvertFlags",
-               argLen: 1,
-               reg:    regInfo{},
+               name:        "ADDC",
+               argLen:      2,
+               commutative: true,
+               asm:         s390x.AADDC,
+               reg: regInfo{
+                       inputs: []inputInfo{
+                               {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+                               {1, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+                       },
+                       outputs: []outputInfo{
+                               {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+                       },
+               },
        },
        {
-               name:   "LoweredGetG",
-               argLen: 1,
+               name:    "ADDCconst",
+               auxType: auxInt16,
+               argLen:  1,
+               asm:     s390x.AADDC,
                reg: regInfo{
+                       inputs: []inputInfo{
+                               {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+                       },
                        outputs: []outputInfo{
                                {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
                        },
                },
        },
        {
-               name:      "LoweredGetClosurePtr",
-               argLen:    0,
-               zeroWidth: true,
+               name:         "ADDE",
+               argLen:       3,
+               commutative:  true,
+               resultInArg0: true,
+               asm:          s390x.AADDE,
                reg: regInfo{
+                       inputs: []inputInfo{
+                               {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+                               {1, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+                       },
                        outputs: []outputInfo{
-                               {0, 4096}, // R12
+                               {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
                        },
                },
        },
        {
-               name:              "LoweredGetCallerSP",
-               argLen:            1,
-               rematerializeable: true,
+               name:   "SUBC",
+               argLen: 2,
+               asm:    s390x.ASUBC,
                reg: regInfo{
+                       inputs: []inputInfo{
+                               {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+                               {1, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+                       },
                        outputs: []outputInfo{
                                {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
                        },
                },
        },
        {
-               name:              "LoweredGetCallerPC",
-               argLen:            0,
-               rematerializeable: true,
+               name:         "SUBE",
+               argLen:       3,
+               resultInArg0: true,
+               asm:          s390x.ASUBE,
                reg: regInfo{
+                       inputs: []inputInfo{
+                               {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+                               {1, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+                       },
                        outputs: []outputInfo{
                                {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
                        },
                },
        },
        {
-               name:           "LoweredNilCheck",
-               argLen:         2,
-               clobberFlags:   true,
-               nilCheck:       true,
-               faultOnNilArg0: true,
+               name:   "CMP",
+               argLen: 2,
+               asm:    s390x.ACMP,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
+                               {0, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
+                               {1, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
                        },
                },
        },
        {
-               name:         "LoweredRound32F",
-               argLen:       1,
-               resultInArg0: true,
-               zeroWidth:    true,
+               name:   "CMPW",
+               argLen: 2,
+               asm:    s390x.ACMPW,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
-                       },
-                       outputs: []outputInfo{
-                               {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+                               {0, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
+                               {1, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
                        },
                },
        },
        {
-               name:         "LoweredRound64F",
-               argLen:       1,
-               resultInArg0: true,
-               zeroWidth:    true,
+               name:   "CMPU",
+               argLen: 2,
+               asm:    s390x.ACMPU,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
-                       },
-                       outputs: []outputInfo{
-                               {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+                               {0, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
+                               {1, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
                        },
                },
        },
        {
-               name:         "LoweredWB",
-               auxType:      auxInt64,
-               argLen:       1,
-               clobberFlags: true,
+               name:   "CMPWU",
+               argLen: 2,
+               asm:    s390x.ACMPWU,
                reg: regInfo{
-                       clobbers: 4294918146, // R1 R14 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
-                       outputs: []outputInfo{
-                               {0, 512}, // R9
+                       inputs: []inputInfo{
+                               {0, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
+                               {1, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
                        },
                },
        },
        {
-               name:    "LoweredPanicBoundsA",
-               auxType: auxInt64,
-               argLen:  3,
-               call:    true,
+               name:    "CMPconst",
+               auxType: auxInt32,
+               argLen:  1,
+               asm:     s390x.ACMP,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 4}, // R2
-                               {1, 8}, // R3
+                               {0, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
                        },
                },
        },
        {
-               name:    "LoweredPanicBoundsB",
-               auxType: auxInt64,
-               argLen:  3,
-               call:    true,
+               name:    "CMPWconst",
+               auxType: auxInt32,
+               argLen:  1,
+               asm:     s390x.ACMPW,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 2}, // R1
-                               {1, 4}, // R2
+                               {0, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
                        },
                },
        },
        {
-               name:    "LoweredPanicBoundsC",
-               auxType: auxInt64,
-               argLen:  3,
-               call:    true,
+               name:    "CMPUconst",
+               auxType: auxInt32,
+               argLen:  1,
+               asm:     s390x.ACMPU,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 1}, // R0
-                               {1, 2}, // R1
+                               {0, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
                        },
                },
        },
        {
-               name:   "FlagEQ",
-               argLen: 0,
-               reg:    regInfo{},
+               name:    "CMPWUconst",
+               auxType: auxInt32,
+               argLen:  1,
+               asm:     s390x.ACMPWU,
+               reg: regInfo{
+                       inputs: []inputInfo{
+                               {0, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
+                       },
+               },
        },
        {
-               name:   "FlagLT",
-               argLen: 0,
-               reg:    regInfo{},
+               name:   "FCMPS",
+               argLen: 2,
+               asm:    s390x.ACEBR,
+               reg: regInfo{
+                       inputs: []inputInfo{
+                               {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+                               {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+                       },
+               },
        },
        {
-               name:   "FlagGT",
-               argLen: 0,
-               reg:    regInfo{},
+               name:   "FCMP",
+               argLen: 2,
+               asm:    s390x.AFCMPU,
+               reg: regInfo{
+                       inputs: []inputInfo{
+                               {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+                               {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+                       },
+               },
        },
        {
-               name:   "FlagOV",
-               argLen: 0,
-               reg:    regInfo{},
+               name:   "LTDBR",
+               argLen: 1,
+               asm:    s390x.ALTDBR,
+               reg: regInfo{
+                       inputs: []inputInfo{
+                               {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+                       },
+               },
        },
        {
-               name:   "SYNC",
+               name:   "LTEBR",
                argLen: 1,
-               asm:    s390x.ASYNC,
-               reg:    regInfo{},
+               asm:    s390x.ALTEBR,
+               reg: regInfo{
+                       inputs: []inputInfo{
+                               {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+                       },
+               },
        },
        {
-               name:           "MOVBZatomicload",
-               auxType:        auxSymOff,
-               argLen:         2,
-               faultOnNilArg0: true,
-               symEffect:      SymRead,
-               asm:            s390x.AMOVBZ,
+               name:   "SLD",
+               argLen: 2,
+               asm:    s390x.ASLD,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB
+                               {1, 23550}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+                               {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
                        },
                        outputs: []outputInfo{
                                {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
@@ -51557,15 +53630,13 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:           "MOVWZatomicload",
-               auxType:        auxSymOff,
-               argLen:         2,
-               faultOnNilArg0: true,
-               symEffect:      SymRead,
-               asm:            s390x.AMOVWZ,
+               name:   "SLW",
+               argLen: 2,
+               asm:    s390x.ASLW,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB
+                               {1, 23550}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+                               {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
                        },
                        outputs: []outputInfo{
                                {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
@@ -51573,15 +53644,13 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:           "MOVDatomicload",
-               auxType:        auxSymOff,
-               argLen:         2,
-               faultOnNilArg0: true,
-               symEffect:      SymRead,
-               asm:            s390x.AMOVD,
+               name:    "SLDconst",
+               auxType: auxUInt8,
+               argLen:  1,
+               asm:     s390x.ASLD,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB
+                               {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
                        },
                        outputs: []outputInfo{
                                {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
@@ -51589,66 +53658,55 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:           "MOVBatomicstore",
-               auxType:        auxSymOff,
-               argLen:         3,
-               clobberFlags:   true,
-               faultOnNilArg0: true,
-               hasSideEffects: true,
-               symEffect:      SymWrite,
-               asm:            s390x.AMOVB,
+               name:    "SLWconst",
+               auxType: auxUInt8,
+               argLen:  1,
+               asm:     s390x.ASLW,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB
-                               {1, 56319},      // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
+                               {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+                       },
+                       outputs: []outputInfo{
+                               {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
                        },
                },
        },
        {
-               name:           "MOVWatomicstore",
-               auxType:        auxSymOff,
-               argLen:         3,
-               clobberFlags:   true,
-               faultOnNilArg0: true,
-               hasSideEffects: true,
-               symEffect:      SymWrite,
-               asm:            s390x.AMOVW,
+               name:   "SRD",
+               argLen: 2,
+               asm:    s390x.ASRD,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB
-                               {1, 56319},      // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
+                               {1, 23550}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+                               {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+                       },
+                       outputs: []outputInfo{
+                               {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
                        },
                },
        },
        {
-               name:           "MOVDatomicstore",
-               auxType:        auxSymOff,
-               argLen:         3,
-               clobberFlags:   true,
-               faultOnNilArg0: true,
-               hasSideEffects: true,
-               symEffect:      SymWrite,
-               asm:            s390x.AMOVD,
+               name:   "SRW",
+               argLen: 2,
+               asm:    s390x.ASRW,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB
-                               {1, 56319},      // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
+                               {1, 23550}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+                               {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+                       },
+                       outputs: []outputInfo{
+                               {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
                        },
                },
        },
        {
-               name:           "LAA",
-               auxType:        auxSymOff,
-               argLen:         3,
-               clobberFlags:   true,
-               faultOnNilArg0: true,
-               hasSideEffects: true,
-               symEffect:      SymRdWr,
-               asm:            s390x.ALAA,
+               name:    "SRDconst",
+               auxType: auxUInt8,
+               argLen:  1,
+               asm:     s390x.ASRD,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB
-                               {1, 56319},      // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
+                               {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
                        },
                        outputs: []outputInfo{
                                {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
@@ -51656,18 +53714,13 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:           "LAAG",
-               auxType:        auxSymOff,
-               argLen:         3,
-               clobberFlags:   true,
-               faultOnNilArg0: true,
-               hasSideEffects: true,
-               symEffect:      SymRdWr,
-               asm:            s390x.ALAAG,
+               name:    "SRWconst",
+               auxType: auxUInt8,
+               argLen:  1,
+               asm:     s390x.ASRW,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB
-                               {1, 56319},      // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
+                               {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
                        },
                        outputs: []outputInfo{
                                {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
@@ -51675,173 +53728,130 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:   "AddTupleFirst32",
-               argLen: 2,
-               reg:    regInfo{},
-       },
-       {
-               name:   "AddTupleFirst64",
-               argLen: 2,
-               reg:    regInfo{},
-       },
-       {
-               name:           "LAN",
-               argLen:         3,
-               clobberFlags:   true,
-               hasSideEffects: true,
-               asm:            s390x.ALAN,
+               name:         "SRAD",
+               argLen:       2,
+               clobberFlags: true,
+               asm:          s390x.ASRAD,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB
-                               {1, 56319},      // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
+                               {1, 23550}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+                               {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+                       },
+                       outputs: []outputInfo{
+                               {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
                        },
                },
        },
        {
-               name:           "LANfloor",
-               argLen:         3,
-               clobberFlags:   true,
-               hasSideEffects: true,
-               asm:            s390x.ALAN,
-               reg: regInfo{
-                       inputs: []inputInfo{
-                               {0, 2},     // R1
-                               {1, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
-                       },
-                       clobbers: 2, // R1
-               },
-       },
-       {
-               name:           "LAO",
-               argLen:         3,
-               clobberFlags:   true,
-               hasSideEffects: true,
-               asm:            s390x.ALAO,
+               name:         "SRAW",
+               argLen:       2,
+               clobberFlags: true,
+               asm:          s390x.ASRAW,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB
-                               {1, 56319},      // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
+                               {1, 23550}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+                               {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+                       },
+                       outputs: []outputInfo{
+                               {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
                        },
                },
        },
        {
-               name:           "LAOfloor",
-               argLen:         3,
-               clobberFlags:   true,
-               hasSideEffects: true,
-               asm:            s390x.ALAO,
+               name:         "SRADconst",
+               auxType:      auxUInt8,
+               argLen:       1,
+               clobberFlags: true,
+               asm:          s390x.ASRAD,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 2},     // R1
-                               {1, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
+                               {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+                       },
+                       outputs: []outputInfo{
+                               {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
                        },
-                       clobbers: 2, // R1
                },
        },
        {
-               name:           "LoweredAtomicCas32",
-               auxType:        auxSymOff,
-               argLen:         4,
-               clobberFlags:   true,
-               faultOnNilArg0: true,
-               hasSideEffects: true,
-               symEffect:      SymRdWr,
-               asm:            s390x.ACS,
+               name:         "SRAWconst",
+               auxType:      auxUInt8,
+               argLen:       1,
+               clobberFlags: true,
+               asm:          s390x.ASRAW,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {1, 1},     // R0
-                               {0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
-                               {2, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
+                               {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
                        },
-                       clobbers: 1, // R0
                        outputs: []outputInfo{
-                               {1, 0},
                                {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
                        },
                },
        },
        {
-               name:           "LoweredAtomicCas64",
-               auxType:        auxSymOff,
-               argLen:         4,
-               clobberFlags:   true,
-               faultOnNilArg0: true,
-               hasSideEffects: true,
-               symEffect:      SymRdWr,
-               asm:            s390x.ACSG,
+               name:   "RLLG",
+               argLen: 2,
+               asm:    s390x.ARLLG,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {1, 1},     // R0
-                               {0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
-                               {2, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
+                               {1, 23550}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+                               {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
                        },
-                       clobbers: 1, // R0
                        outputs: []outputInfo{
-                               {1, 0},
                                {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
                        },
                },
        },
        {
-               name:           "LoweredAtomicExchange32",
-               auxType:        auxSymOff,
-               argLen:         3,
-               clobberFlags:   true,
-               faultOnNilArg0: true,
-               hasSideEffects: true,
-               symEffect:      SymRdWr,
-               asm:            s390x.ACS,
+               name:   "RLL",
+               argLen: 2,
+               asm:    s390x.ARLL,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
-                               {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
+                               {1, 23550}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+                               {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
                        },
                        outputs: []outputInfo{
-                               {1, 0},
-                               {0, 1}, // R0
+                               {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
                        },
                },
        },
        {
-               name:           "LoweredAtomicExchange64",
-               auxType:        auxSymOff,
-               argLen:         3,
-               clobberFlags:   true,
-               faultOnNilArg0: true,
-               hasSideEffects: true,
-               symEffect:      SymRdWr,
-               asm:            s390x.ACSG,
+               name:    "RLLconst",
+               auxType: auxUInt8,
+               argLen:  1,
+               asm:     s390x.ARLL,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
-                               {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
+                               {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
                        },
                        outputs: []outputInfo{
-                               {1, 0},
-                               {0, 1}, // R0
+                               {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
                        },
                },
        },
        {
-               name:         "FLOGR",
-               argLen:       1,
+               name:         "RXSBG",
+               auxType:      auxS390XRotateParams,
+               argLen:       2,
+               resultInArg0: true,
                clobberFlags: true,
-               asm:          s390x.AFLOGR,
+               asm:          s390x.ARXSBG,
                reg: regInfo{
                        inputs: []inputInfo{
                                {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+                               {1, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
                        },
-                       clobbers: 2, // R1
                        outputs: []outputInfo{
-                               {0, 1}, // R0
+                               {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
                        },
                },
        },
        {
-               name:         "POPCNT",
+               name:         "RISBGZ",
+               auxType:      auxS390XRotateParams,
                argLen:       1,
                clobberFlags: true,
-               asm:          s390x.APOPCNT,
+               asm:          s390x.ARISBGZ,
                reg: regInfo{
                        inputs: []inputInfo{
                                {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
@@ -51852,480 +53862,423 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:   "MLGR",
-               argLen: 2,
-               asm:    s390x.AMLGR,
+               name:         "NEG",
+               argLen:       1,
+               clobberFlags: true,
+               asm:          s390x.ANEG,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {1, 8},     // R3
                                {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
                        },
                        outputs: []outputInfo{
-                               {0, 4}, // R2
-                               {1, 8}, // R3
+                               {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
                        },
                },
        },
        {
-               name:   "SumBytes2",
-               argLen: 1,
-               reg:    regInfo{},
-       },
-       {
-               name:   "SumBytes4",
-               argLen: 1,
-               reg:    regInfo{},
-       },
-       {
-               name:   "SumBytes8",
-               argLen: 1,
-               reg:    regInfo{},
-       },
-       {
-               name:           "STMG2",
-               auxType:        auxSymOff,
-               argLen:         4,
-               clobberFlags:   true,
-               faultOnNilArg0: true,
-               symEffect:      SymWrite,
-               asm:            s390x.ASTMG,
+               name:         "NEGW",
+               argLen:       1,
+               clobberFlags: true,
+               asm:          s390x.ANEGW,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {1, 2},     // R1
-                               {2, 4},     // R2
-                               {0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
+                               {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
                        },
-               },
-       },
-       {
-               name:           "STMG3",
-               auxType:        auxSymOff,
-               argLen:         5,
-               clobberFlags:   true,
-               faultOnNilArg0: true,
-               symEffect:      SymWrite,
-               asm:            s390x.ASTMG,
-               reg: regInfo{
-                       inputs: []inputInfo{
-                               {1, 2},     // R1
-                               {2, 4},     // R2
-                               {3, 8},     // R3
-                               {0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
+                       outputs: []outputInfo{
+                               {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
                        },
                },
        },
        {
-               name:           "STMG4",
-               auxType:        auxSymOff,
-               argLen:         6,
-               clobberFlags:   true,
-               faultOnNilArg0: true,
-               symEffect:      SymWrite,
-               asm:            s390x.ASTMG,
+               name:         "NOT",
+               argLen:       1,
+               resultInArg0: true,
+               clobberFlags: true,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {1, 2},     // R1
-                               {2, 4},     // R2
-                               {3, 8},     // R3
-                               {4, 16},    // R4
-                               {0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
+                               {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+                       },
+                       outputs: []outputInfo{
+                               {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
                        },
                },
        },
        {
-               name:           "STM2",
-               auxType:        auxSymOff,
-               argLen:         4,
-               clobberFlags:   true,
-               faultOnNilArg0: true,
-               symEffect:      SymWrite,
-               asm:            s390x.ASTMY,
+               name:         "NOTW",
+               argLen:       1,
+               resultInArg0: true,
+               clobberFlags: true,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {1, 2},     // R1
-                               {2, 4},     // R2
-                               {0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
+                               {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+                       },
+                       outputs: []outputInfo{
+                               {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
                        },
                },
        },
        {
-               name:           "STM3",
-               auxType:        auxSymOff,
-               argLen:         5,
-               clobberFlags:   true,
-               faultOnNilArg0: true,
-               symEffect:      SymWrite,
-               asm:            s390x.ASTMY,
+               name:   "FSQRT",
+               argLen: 1,
+               asm:    s390x.AFSQRT,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {1, 2},     // R1
-                               {2, 4},     // R2
-                               {3, 8},     // R3
-                               {0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
+                               {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+                       },
+                       outputs: []outputInfo{
+                               {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
                        },
                },
        },
        {
-               name:           "STM4",
-               auxType:        auxSymOff,
-               argLen:         6,
-               clobberFlags:   true,
-               faultOnNilArg0: true,
-               symEffect:      SymWrite,
-               asm:            s390x.ASTMY,
+               name:   "FSQRTS",
+               argLen: 1,
+               asm:    s390x.AFSQRTS,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {1, 2},     // R1
-                               {2, 4},     // R2
-                               {3, 8},     // R3
-                               {4, 16},    // R4
-                               {0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
+                               {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+                       },
+                       outputs: []outputInfo{
+                               {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
                        },
                },
        },
        {
-               name:           "LoweredMove",
-               auxType:        auxInt64,
-               argLen:         4,
-               clobberFlags:   true,
-               faultOnNilArg0: true,
-               faultOnNilArg1: true,
+               name:         "LOCGR",
+               auxType:      auxS390XCCMask,
+               argLen:       3,
+               resultInArg0: true,
+               asm:          s390x.ALOCGR,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 2},     // R1
-                               {1, 4},     // R2
-                               {2, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
+                               {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+                               {1, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+                       },
+                       outputs: []outputInfo{
+                               {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
                        },
-                       clobbers: 6, // R1 R2
                },
        },
        {
-               name:           "LoweredZero",
-               auxType:        auxInt64,
-               argLen:         3,
-               clobberFlags:   true,
-               faultOnNilArg0: true,
+               name:   "MOVBreg",
+               argLen: 1,
+               asm:    s390x.AMOVB,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 2},     // R1
-                               {1, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
+                               {0, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
+                       },
+                       outputs: []outputInfo{
+                               {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
                        },
-                       clobbers: 2, // R1
-               },
-       },
-
-       {
-               name:    "LoweredStaticCall",
-               auxType: auxCallOff,
-               argLen:  1,
-               call:    true,
-               reg: regInfo{
-                       clobbers: 844424930131967, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 g
-               },
-       },
-       {
-               name:     "LoweredTailCall",
-               auxType:  auxCallOff,
-               argLen:   1,
-               call:     true,
-               tailCall: true,
-               reg: regInfo{
-                       clobbers: 844424930131967, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 g
                },
        },
        {
-               name:    "LoweredClosureCall",
-               auxType: auxCallOff,
-               argLen:  3,
-               call:    true,
+               name:   "MOVBZreg",
+               argLen: 1,
+               asm:    s390x.AMOVBZ,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
-                               {1, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
+                               {0, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
+                       },
+                       outputs: []outputInfo{
+                               {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
                        },
-                       clobbers: 844424930131967, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 g
                },
        },
        {
-               name:    "LoweredInterCall",
-               auxType: auxCallOff,
-               argLen:  2,
-               call:    true,
+               name:   "MOVHreg",
+               argLen: 1,
+               asm:    s390x.AMOVH,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
+                               {0, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
+                       },
+                       outputs: []outputInfo{
+                               {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
                        },
-                       clobbers: 844424930131967, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 g
                },
        },
        {
-               name:              "LoweredAddr",
-               auxType:           auxSymOff,
-               argLen:            1,
-               rematerializeable: true,
-               symEffect:         SymAddr,
+               name:   "MOVHZreg",
+               argLen: 1,
+               asm:    s390x.AMOVHZ,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
+                               {0, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
                        },
                        outputs: []outputInfo{
-                               {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
+                               {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
                        },
                },
        },
        {
-               name:    "LoweredMove",
-               auxType: auxInt64,
-               argLen:  3,
+               name:   "MOVWreg",
+               argLen: 1,
+               asm:    s390x.AMOVW,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
-                               {1, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
+                               {0, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
+                       },
+                       outputs: []outputInfo{
+                               {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
                        },
                },
        },
        {
-               name:    "LoweredZero",
-               auxType: auxInt64,
-               argLen:  2,
+               name:   "MOVWZreg",
+               argLen: 1,
+               asm:    s390x.AMOVWZ,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
+                               {0, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
                        },
-               },
-       },
-       {
-               name:   "LoweredGetClosurePtr",
-               argLen: 0,
-               reg: regInfo{
                        outputs: []outputInfo{
-                               {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
+                               {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
                        },
                },
        },
        {
-               name:              "LoweredGetCallerPC",
+               name:              "MOVDconst",
+               auxType:           auxInt64,
                argLen:            0,
                rematerializeable: true,
+               asm:               s390x.AMOVD,
                reg: regInfo{
                        outputs: []outputInfo{
-                               {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
+                               {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
                        },
                },
        },
        {
-               name:              "LoweredGetCallerSP",
-               argLen:            1,
-               rematerializeable: true,
+               name:   "LDGR",
+               argLen: 1,
+               asm:    s390x.ALDGR,
                reg: regInfo{
+                       inputs: []inputInfo{
+                               {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+                       },
                        outputs: []outputInfo{
-                               {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
+                               {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
                        },
                },
        },
        {
-               name:           "LoweredNilCheck",
-               argLen:         2,
-               nilCheck:       true,
-               faultOnNilArg0: true,
+               name:   "LGDR",
+               argLen: 1,
+               asm:    s390x.ALGDR,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
+                               {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+                       },
+                       outputs: []outputInfo{
+                               {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
                        },
                },
        },
        {
-               name:    "LoweredWB",
-               auxType: auxInt64,
-               argLen:  1,
+               name:         "CFDBRA",
+               argLen:       1,
+               clobberFlags: true,
+               asm:          s390x.ACFDBRA,
                reg: regInfo{
-                       clobbers: 844424930131967, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 g
+                       inputs: []inputInfo{
+                               {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+                       },
                        outputs: []outputInfo{
-                               {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
+                               {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
                        },
                },
        },
        {
-               name:   "LoweredConvert",
-               argLen: 2,
+               name:         "CGDBRA",
+               argLen:       1,
+               clobberFlags: true,
+               asm:          s390x.ACGDBRA,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
+                               {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
                        },
                        outputs: []outputInfo{
-                               {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
+                               {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
                        },
                },
        },
        {
-               name:   "Select",
-               argLen: 3,
-               asm:    wasm.ASelect,
+               name:         "CFEBRA",
+               argLen:       1,
+               clobberFlags: true,
+               asm:          s390x.ACFEBRA,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
-                               {1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
-                               {2, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
+                               {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
                        },
                        outputs: []outputInfo{
-                               {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
+                               {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
                        },
                },
        },
        {
-               name:    "I64Load8U",
-               auxType: auxInt64,
-               argLen:  2,
-               asm:     wasm.AI64Load8U,
+               name:         "CGEBRA",
+               argLen:       1,
+               clobberFlags: true,
+               asm:          s390x.ACGEBRA,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 1407374883618815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP SB
+                               {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
                        },
                        outputs: []outputInfo{
-                               {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
+                               {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
                        },
                },
        },
        {
-               name:    "I64Load8S",
-               auxType: auxInt64,
-               argLen:  2,
-               asm:     wasm.AI64Load8S,
+               name:         "CEFBRA",
+               argLen:       1,
+               clobberFlags: true,
+               asm:          s390x.ACEFBRA,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 1407374883618815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP SB
+                               {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
                        },
                        outputs: []outputInfo{
-                               {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
+                               {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
                        },
                },
        },
        {
-               name:    "I64Load16U",
-               auxType: auxInt64,
-               argLen:  2,
-               asm:     wasm.AI64Load16U,
+               name:         "CDFBRA",
+               argLen:       1,
+               clobberFlags: true,
+               asm:          s390x.ACDFBRA,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 1407374883618815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP SB
+                               {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
                        },
                        outputs: []outputInfo{
-                               {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
+                               {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
                        },
                },
        },
        {
-               name:    "I64Load16S",
-               auxType: auxInt64,
-               argLen:  2,
-               asm:     wasm.AI64Load16S,
+               name:         "CEGBRA",
+               argLen:       1,
+               clobberFlags: true,
+               asm:          s390x.ACEGBRA,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 1407374883618815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP SB
+                               {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
                        },
                        outputs: []outputInfo{
-                               {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
+                               {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
                        },
                },
        },
        {
-               name:    "I64Load32U",
-               auxType: auxInt64,
-               argLen:  2,
-               asm:     wasm.AI64Load32U,
+               name:         "CDGBRA",
+               argLen:       1,
+               clobberFlags: true,
+               asm:          s390x.ACDGBRA,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 1407374883618815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP SB
+                               {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
                        },
                        outputs: []outputInfo{
-                               {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
+                               {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
                        },
                },
        },
        {
-               name:    "I64Load32S",
-               auxType: auxInt64,
-               argLen:  2,
-               asm:     wasm.AI64Load32S,
+               name:         "CLFEBR",
+               argLen:       1,
+               clobberFlags: true,
+               asm:          s390x.ACLFEBR,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 1407374883618815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP SB
+                               {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
                        },
                        outputs: []outputInfo{
-                               {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
+                               {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
                        },
                },
        },
        {
-               name:    "I64Load",
-               auxType: auxInt64,
-               argLen:  2,
-               asm:     wasm.AI64Load,
+               name:         "CLFDBR",
+               argLen:       1,
+               clobberFlags: true,
+               asm:          s390x.ACLFDBR,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 1407374883618815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP SB
+                               {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
                        },
                        outputs: []outputInfo{
-                               {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
+                               {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
                        },
                },
        },
        {
-               name:    "I64Store8",
-               auxType: auxInt64,
-               argLen:  3,
-               asm:     wasm.AI64Store8,
+               name:         "CLGEBR",
+               argLen:       1,
+               clobberFlags: true,
+               asm:          s390x.ACLGEBR,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {1, 281474976776191},  // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
-                               {0, 1407374883618815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP SB
+                               {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+                       },
+                       outputs: []outputInfo{
+                               {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
                        },
                },
        },
        {
-               name:    "I64Store16",
-               auxType: auxInt64,
-               argLen:  3,
-               asm:     wasm.AI64Store16,
+               name:         "CLGDBR",
+               argLen:       1,
+               clobberFlags: true,
+               asm:          s390x.ACLGDBR,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {1, 281474976776191},  // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
-                               {0, 1407374883618815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP SB
+                               {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+                       },
+                       outputs: []outputInfo{
+                               {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
                        },
                },
        },
        {
-               name:    "I64Store32",
-               auxType: auxInt64,
-               argLen:  3,
-               asm:     wasm.AI64Store32,
+               name:         "CELFBR",
+               argLen:       1,
+               clobberFlags: true,
+               asm:          s390x.ACELFBR,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {1, 281474976776191},  // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
-                               {0, 1407374883618815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP SB
+                               {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+                       },
+                       outputs: []outputInfo{
+                               {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
                        },
                },
        },
        {
-               name:    "I64Store",
-               auxType: auxInt64,
-               argLen:  3,
-               asm:     wasm.AI64Store,
+               name:         "CDLFBR",
+               argLen:       1,
+               clobberFlags: true,
+               asm:          s390x.ACDLFBR,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {1, 281474976776191},  // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
-                               {0, 1407374883618815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP SB
+                               {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
+                       },
+                       outputs: []outputInfo{
+                               {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
                        },
                },
        },
        {
-               name:    "F32Load",
-               auxType: auxInt64,
-               argLen:  2,
-               asm:     wasm.AF32Load,
+               name:         "CELGBR",
+               argLen:       1,
+               clobberFlags: true,
+               asm:          s390x.ACELGBR,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 1407374883618815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP SB
+                               {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
                        },
                        outputs: []outputInfo{
                                {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
@@ -52333,790 +54286,828 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:    "F64Load",
-               auxType: auxInt64,
-               argLen:  2,
-               asm:     wasm.AF64Load,
+               name:         "CDLGBR",
+               argLen:       1,
+               clobberFlags: true,
+               asm:          s390x.ACDLGBR,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 1407374883618815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP SB
+                               {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
                        },
                        outputs: []outputInfo{
-                               {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
                        },
                },
        },
        {
-               name:    "F32Store",
-               auxType: auxInt64,
-               argLen:  3,
-               asm:     wasm.AF32Store,
+               name:   "LEDBR",
+               argLen: 1,
+               asm:    s390x.ALEDBR,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {1, 4294901760},       // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
-                               {0, 1407374883618815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP SB
+                               {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+                       },
+                       outputs: []outputInfo{
+                               {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
                        },
                },
        },
        {
-               name:    "F64Store",
-               auxType: auxInt64,
-               argLen:  3,
-               asm:     wasm.AF64Store,
+               name:   "LDEBR",
+               argLen: 1,
+               asm:    s390x.ALDEBR,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {1, 281470681743360},  // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
-                               {0, 1407374883618815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP SB
+                               {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
                        },
-               },
-       },
-       {
-               name:              "I64Const",
-               auxType:           auxInt64,
-               argLen:            0,
-               rematerializeable: true,
-               reg: regInfo{
                        outputs: []outputInfo{
-                               {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
+                               {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
                        },
                },
        },
        {
-               name:              "F32Const",
-               auxType:           auxFloat32,
-               argLen:            0,
+               name:              "MOVDaddr",
+               auxType:           auxSymOff,
+               argLen:            1,
                rematerializeable: true,
+               symEffect:         SymAddr,
                reg: regInfo{
+                       inputs: []inputInfo{
+                               {0, 4295000064}, // SP SB
+                       },
                        outputs: []outputInfo{
-                               {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+                               {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
                        },
                },
        },
        {
-               name:              "F64Const",
-               auxType:           auxFloat64,
-               argLen:            0,
-               rematerializeable: true,
+               name:      "MOVDaddridx",
+               auxType:   auxSymOff,
+               argLen:    2,
+               symEffect: SymAddr,
                reg: regInfo{
+                       inputs: []inputInfo{
+                               {0, 4295000064}, // SP SB
+                               {1, 56318},      // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
+                       },
                        outputs: []outputInfo{
-                               {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
                        },
                },
        },
        {
-               name:   "I64Eqz",
-               argLen: 1,
-               asm:    wasm.AI64Eqz,
+               name:           "MOVBZload",
+               auxType:        auxSymOff,
+               argLen:         2,
+               faultOnNilArg0: true,
+               symEffect:      SymRead,
+               asm:            s390x.AMOVBZ,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
+                               {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB
                        },
                        outputs: []outputInfo{
-                               {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
+                               {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
                        },
                },
        },
        {
-               name:   "I64Eq",
-               argLen: 2,
-               asm:    wasm.AI64Eq,
+               name:           "MOVBload",
+               auxType:        auxSymOff,
+               argLen:         2,
+               faultOnNilArg0: true,
+               symEffect:      SymRead,
+               asm:            s390x.AMOVB,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
-                               {1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
+                               {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB
                        },
                        outputs: []outputInfo{
-                               {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
+                               {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
                        },
                },
        },
        {
-               name:   "I64Ne",
-               argLen: 2,
-               asm:    wasm.AI64Ne,
+               name:           "MOVHZload",
+               auxType:        auxSymOff,
+               argLen:         2,
+               faultOnNilArg0: true,
+               symEffect:      SymRead,
+               asm:            s390x.AMOVHZ,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
-                               {1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
+                               {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB
                        },
                        outputs: []outputInfo{
-                               {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
+                               {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
                        },
                },
        },
        {
-               name:   "I64LtS",
-               argLen: 2,
-               asm:    wasm.AI64LtS,
+               name:           "MOVHload",
+               auxType:        auxSymOff,
+               argLen:         2,
+               faultOnNilArg0: true,
+               symEffect:      SymRead,
+               asm:            s390x.AMOVH,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
-                               {1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
+                               {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB
                        },
                        outputs: []outputInfo{
-                               {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
+                               {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
                        },
                },
        },
        {
-               name:   "I64LtU",
-               argLen: 2,
-               asm:    wasm.AI64LtU,
+               name:           "MOVWZload",
+               auxType:        auxSymOff,
+               argLen:         2,
+               faultOnNilArg0: true,
+               symEffect:      SymRead,
+               asm:            s390x.AMOVWZ,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
-                               {1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
+                               {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB
                        },
                        outputs: []outputInfo{
-                               {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
+                               {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
                        },
                },
        },
        {
-               name:   "I64GtS",
-               argLen: 2,
-               asm:    wasm.AI64GtS,
+               name:           "MOVWload",
+               auxType:        auxSymOff,
+               argLen:         2,
+               faultOnNilArg0: true,
+               symEffect:      SymRead,
+               asm:            s390x.AMOVW,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
-                               {1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
+                               {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB
                        },
                        outputs: []outputInfo{
-                               {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
+                               {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
                        },
                },
        },
        {
-               name:   "I64GtU",
-               argLen: 2,
-               asm:    wasm.AI64GtU,
+               name:           "MOVDload",
+               auxType:        auxSymOff,
+               argLen:         2,
+               faultOnNilArg0: true,
+               symEffect:      SymRead,
+               asm:            s390x.AMOVD,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
-                               {1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
+                               {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB
                        },
                        outputs: []outputInfo{
-                               {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
+                               {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
                        },
                },
        },
        {
-               name:   "I64LeS",
-               argLen: 2,
-               asm:    wasm.AI64LeS,
+               name:   "MOVWBR",
+               argLen: 1,
+               asm:    s390x.AMOVWBR,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
-                               {1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
+                               {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
                        },
                        outputs: []outputInfo{
-                               {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
+                               {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
                        },
                },
        },
        {
-               name:   "I64LeU",
-               argLen: 2,
-               asm:    wasm.AI64LeU,
+               name:   "MOVDBR",
+               argLen: 1,
+               asm:    s390x.AMOVDBR,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
-                               {1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
+                               {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
                        },
                        outputs: []outputInfo{
-                               {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
+                               {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
                        },
                },
        },
        {
-               name:   "I64GeS",
-               argLen: 2,
-               asm:    wasm.AI64GeS,
+               name:           "MOVHBRload",
+               auxType:        auxSymOff,
+               argLen:         2,
+               faultOnNilArg0: true,
+               symEffect:      SymRead,
+               asm:            s390x.AMOVHBR,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
-                               {1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
+                               {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB
                        },
                        outputs: []outputInfo{
-                               {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
+                               {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
                        },
                },
        },
        {
-               name:   "I64GeU",
-               argLen: 2,
-               asm:    wasm.AI64GeU,
+               name:           "MOVWBRload",
+               auxType:        auxSymOff,
+               argLen:         2,
+               faultOnNilArg0: true,
+               symEffect:      SymRead,
+               asm:            s390x.AMOVWBR,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
-                               {1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
+                               {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB
                        },
                        outputs: []outputInfo{
-                               {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
+                               {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
                        },
                },
        },
        {
-               name:   "F32Eq",
-               argLen: 2,
-               asm:    wasm.AF32Eq,
+               name:           "MOVDBRload",
+               auxType:        auxSymOff,
+               argLen:         2,
+               faultOnNilArg0: true,
+               symEffect:      SymRead,
+               asm:            s390x.AMOVDBR,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
-                               {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+                               {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB
                        },
                        outputs: []outputInfo{
-                               {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
+                               {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
                        },
                },
        },
        {
-               name:   "F32Ne",
-               argLen: 2,
-               asm:    wasm.AF32Ne,
+               name:           "MOVBstore",
+               auxType:        auxSymOff,
+               argLen:         3,
+               faultOnNilArg0: true,
+               symEffect:      SymWrite,
+               asm:            s390x.AMOVB,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
-                               {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
-                       },
-                       outputs: []outputInfo{
-                               {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
+                               {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB
+                               {1, 56319},      // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
                        },
                },
        },
        {
-               name:   "F32Lt",
-               argLen: 2,
-               asm:    wasm.AF32Lt,
+               name:           "MOVHstore",
+               auxType:        auxSymOff,
+               argLen:         3,
+               faultOnNilArg0: true,
+               symEffect:      SymWrite,
+               asm:            s390x.AMOVH,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
-                               {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
-                       },
-                       outputs: []outputInfo{
-                               {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
+                               {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB
+                               {1, 56319},      // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
                        },
                },
        },
        {
-               name:   "F32Gt",
-               argLen: 2,
-               asm:    wasm.AF32Gt,
+               name:           "MOVWstore",
+               auxType:        auxSymOff,
+               argLen:         3,
+               faultOnNilArg0: true,
+               symEffect:      SymWrite,
+               asm:            s390x.AMOVW,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
-                               {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
-                       },
-                       outputs: []outputInfo{
-                               {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
+                               {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB
+                               {1, 56319},      // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
                        },
                },
        },
        {
-               name:   "F32Le",
-               argLen: 2,
-               asm:    wasm.AF32Le,
+               name:           "MOVDstore",
+               auxType:        auxSymOff,
+               argLen:         3,
+               faultOnNilArg0: true,
+               symEffect:      SymWrite,
+               asm:            s390x.AMOVD,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
-                               {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
-                       },
-                       outputs: []outputInfo{
-                               {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
+                               {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB
+                               {1, 56319},      // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
                        },
                },
        },
        {
-               name:   "F32Ge",
-               argLen: 2,
-               asm:    wasm.AF32Ge,
+               name:           "MOVHBRstore",
+               auxType:        auxSymOff,
+               argLen:         3,
+               faultOnNilArg0: true,
+               symEffect:      SymWrite,
+               asm:            s390x.AMOVHBR,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
-                               {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
-                       },
-                       outputs: []outputInfo{
-                               {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
+                               {0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
+                               {1, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
                        },
                },
        },
        {
-               name:   "F64Eq",
-               argLen: 2,
-               asm:    wasm.AF64Eq,
+               name:           "MOVWBRstore",
+               auxType:        auxSymOff,
+               argLen:         3,
+               faultOnNilArg0: true,
+               symEffect:      SymWrite,
+               asm:            s390x.AMOVWBR,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
-                               {1, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
-                       },
-                       outputs: []outputInfo{
-                               {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
+                               {0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
+                               {1, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
                        },
                },
        },
        {
-               name:   "F64Ne",
-               argLen: 2,
-               asm:    wasm.AF64Ne,
+               name:           "MOVDBRstore",
+               auxType:        auxSymOff,
+               argLen:         3,
+               faultOnNilArg0: true,
+               symEffect:      SymWrite,
+               asm:            s390x.AMOVDBR,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
-                               {1, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
-                       },
-                       outputs: []outputInfo{
-                               {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
+                               {0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
+                               {1, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
                        },
                },
        },
        {
-               name:   "F64Lt",
-               argLen: 2,
-               asm:    wasm.AF64Lt,
+               name:           "MVC",
+               auxType:        auxSymValAndOff,
+               argLen:         3,
+               clobberFlags:   true,
+               faultOnNilArg0: true,
+               faultOnNilArg1: true,
+               symEffect:      SymNone,
+               asm:            s390x.AMVC,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
-                               {1, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
-                       },
-                       outputs: []outputInfo{
-                               {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
+                               {0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
+                               {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
                        },
                },
        },
        {
-               name:   "F64Gt",
-               argLen: 2,
-               asm:    wasm.AF64Gt,
+               name:        "MOVBZloadidx",
+               auxType:     auxSymOff,
+               argLen:      3,
+               commutative: true,
+               symEffect:   SymRead,
+               asm:         s390x.AMOVBZ,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
-                               {1, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {1, 56318},      // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
+                               {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB
                        },
                        outputs: []outputInfo{
-                               {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
+                               {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
                        },
                },
        },
        {
-               name:   "F64Le",
-               argLen: 2,
-               asm:    wasm.AF64Le,
+               name:        "MOVBloadidx",
+               auxType:     auxSymOff,
+               argLen:      3,
+               commutative: true,
+               symEffect:   SymRead,
+               asm:         s390x.AMOVB,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
-                               {1, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {1, 56318},      // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
+                               {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB
                        },
                        outputs: []outputInfo{
-                               {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
+                               {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
                        },
                },
        },
        {
-               name:   "F64Ge",
-               argLen: 2,
-               asm:    wasm.AF64Ge,
+               name:        "MOVHZloadidx",
+               auxType:     auxSymOff,
+               argLen:      3,
+               commutative: true,
+               symEffect:   SymRead,
+               asm:         s390x.AMOVHZ,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
-                               {1, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {1, 56318},      // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
+                               {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB
                        },
                        outputs: []outputInfo{
-                               {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
+                               {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
                        },
                },
        },
        {
-               name:   "I64Add",
-               argLen: 2,
-               asm:    wasm.AI64Add,
+               name:        "MOVHloadidx",
+               auxType:     auxSymOff,
+               argLen:      3,
+               commutative: true,
+               symEffect:   SymRead,
+               asm:         s390x.AMOVH,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
-                               {1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
+                               {1, 56318},      // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
+                               {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB
                        },
                        outputs: []outputInfo{
-                               {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
+                               {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
                        },
                },
        },
        {
-               name:    "I64AddConst",
-               auxType: auxInt64,
-               argLen:  1,
-               asm:     wasm.AI64Add,
+               name:        "MOVWZloadidx",
+               auxType:     auxSymOff,
+               argLen:      3,
+               commutative: true,
+               symEffect:   SymRead,
+               asm:         s390x.AMOVWZ,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
+                               {1, 56318},      // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
+                               {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB
                        },
                        outputs: []outputInfo{
-                               {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
+                               {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
                        },
                },
        },
        {
-               name:   "I64Sub",
-               argLen: 2,
-               asm:    wasm.AI64Sub,
+               name:        "MOVWloadidx",
+               auxType:     auxSymOff,
+               argLen:      3,
+               commutative: true,
+               symEffect:   SymRead,
+               asm:         s390x.AMOVW,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
-                               {1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
+                               {1, 56318},      // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
+                               {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB
                        },
                        outputs: []outputInfo{
-                               {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
+                               {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
                        },
                },
        },
        {
-               name:   "I64Mul",
-               argLen: 2,
-               asm:    wasm.AI64Mul,
+               name:        "MOVDloadidx",
+               auxType:     auxSymOff,
+               argLen:      3,
+               commutative: true,
+               symEffect:   SymRead,
+               asm:         s390x.AMOVD,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
-                               {1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
+                               {1, 56318},      // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
+                               {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB
                        },
                        outputs: []outputInfo{
-                               {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
+                               {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
                        },
                },
        },
        {
-               name:   "I64DivS",
-               argLen: 2,
-               asm:    wasm.AI64DivS,
+               name:        "MOVHBRloadidx",
+               auxType:     auxSymOff,
+               argLen:      3,
+               commutative: true,
+               symEffect:   SymRead,
+               asm:         s390x.AMOVHBR,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
-                               {1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
+                               {1, 56318},      // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
+                               {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB
                        },
                        outputs: []outputInfo{
-                               {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
+                               {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
                        },
                },
        },
        {
-               name:   "I64DivU",
-               argLen: 2,
-               asm:    wasm.AI64DivU,
+               name:        "MOVWBRloadidx",
+               auxType:     auxSymOff,
+               argLen:      3,
+               commutative: true,
+               symEffect:   SymRead,
+               asm:         s390x.AMOVWBR,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
-                               {1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
+                               {1, 56318},      // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
+                               {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB
                        },
                        outputs: []outputInfo{
-                               {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
+                               {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
                        },
                },
        },
        {
-               name:   "I64RemS",
-               argLen: 2,
-               asm:    wasm.AI64RemS,
+               name:        "MOVDBRloadidx",
+               auxType:     auxSymOff,
+               argLen:      3,
+               commutative: true,
+               symEffect:   SymRead,
+               asm:         s390x.AMOVDBR,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
-                               {1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
+                               {1, 56318},      // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
+                               {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB
                        },
                        outputs: []outputInfo{
-                               {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
+                               {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
                        },
                },
        },
        {
-               name:   "I64RemU",
-               argLen: 2,
-               asm:    wasm.AI64RemU,
+               name:        "MOVBstoreidx",
+               auxType:     auxSymOff,
+               argLen:      4,
+               commutative: true,
+               symEffect:   SymWrite,
+               asm:         s390x.AMOVB,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
-                               {1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
-                       },
-                       outputs: []outputInfo{
-                               {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
+                               {0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
+                               {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
+                               {2, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
                        },
                },
        },
        {
-               name:   "I64And",
-               argLen: 2,
-               asm:    wasm.AI64And,
+               name:        "MOVHstoreidx",
+               auxType:     auxSymOff,
+               argLen:      4,
+               commutative: true,
+               symEffect:   SymWrite,
+               asm:         s390x.AMOVH,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
-                               {1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
-                       },
-                       outputs: []outputInfo{
-                               {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
+                               {0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
+                               {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
+                               {2, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
                        },
                },
        },
        {
-               name:   "I64Or",
-               argLen: 2,
-               asm:    wasm.AI64Or,
+               name:        "MOVWstoreidx",
+               auxType:     auxSymOff,
+               argLen:      4,
+               commutative: true,
+               symEffect:   SymWrite,
+               asm:         s390x.AMOVW,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
-                               {1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
-                       },
-                       outputs: []outputInfo{
-                               {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
+                               {0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
+                               {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
+                               {2, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
                        },
                },
        },
        {
-               name:   "I64Xor",
-               argLen: 2,
-               asm:    wasm.AI64Xor,
+               name:        "MOVDstoreidx",
+               auxType:     auxSymOff,
+               argLen:      4,
+               commutative: true,
+               symEffect:   SymWrite,
+               asm:         s390x.AMOVD,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
-                               {1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
-                       },
-                       outputs: []outputInfo{
-                               {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
+                               {0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
+                               {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
+                               {2, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
                        },
                },
        },
        {
-               name:   "I64Shl",
-               argLen: 2,
-               asm:    wasm.AI64Shl,
+               name:        "MOVHBRstoreidx",
+               auxType:     auxSymOff,
+               argLen:      4,
+               commutative: true,
+               symEffect:   SymWrite,
+               asm:         s390x.AMOVHBR,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
-                               {1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
-                       },
-                       outputs: []outputInfo{
-                               {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
+                               {0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
+                               {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
+                               {2, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
                        },
                },
        },
        {
-               name:   "I64ShrS",
-               argLen: 2,
-               asm:    wasm.AI64ShrS,
+               name:        "MOVWBRstoreidx",
+               auxType:     auxSymOff,
+               argLen:      4,
+               commutative: true,
+               symEffect:   SymWrite,
+               asm:         s390x.AMOVWBR,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
-                               {1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
-                       },
-                       outputs: []outputInfo{
-                               {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
+                               {0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
+                               {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
+                               {2, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
                        },
                },
        },
        {
-               name:   "I64ShrU",
-               argLen: 2,
-               asm:    wasm.AI64ShrU,
+               name:        "MOVDBRstoreidx",
+               auxType:     auxSymOff,
+               argLen:      4,
+               commutative: true,
+               symEffect:   SymWrite,
+               asm:         s390x.AMOVDBR,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
-                               {1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
-                       },
-                       outputs: []outputInfo{
-                               {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
+                               {0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
+                               {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
+                               {2, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
                        },
                },
        },
        {
-               name:   "F32Neg",
-               argLen: 1,
-               asm:    wasm.AF32Neg,
+               name:           "MOVBstoreconst",
+               auxType:        auxSymValAndOff,
+               argLen:         2,
+               faultOnNilArg0: true,
+               symEffect:      SymWrite,
+               asm:            s390x.AMOVB,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
-                       },
-                       outputs: []outputInfo{
-                               {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+                               {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB
                        },
                },
        },
        {
-               name:   "F32Add",
-               argLen: 2,
-               asm:    wasm.AF32Add,
+               name:           "MOVHstoreconst",
+               auxType:        auxSymValAndOff,
+               argLen:         2,
+               faultOnNilArg0: true,
+               symEffect:      SymWrite,
+               asm:            s390x.AMOVH,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
-                               {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
-                       },
-                       outputs: []outputInfo{
-                               {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+                               {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB
                        },
                },
        },
        {
-               name:   "F32Sub",
-               argLen: 2,
-               asm:    wasm.AF32Sub,
+               name:           "MOVWstoreconst",
+               auxType:        auxSymValAndOff,
+               argLen:         2,
+               faultOnNilArg0: true,
+               symEffect:      SymWrite,
+               asm:            s390x.AMOVW,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
-                               {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
-                       },
-                       outputs: []outputInfo{
-                               {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+                               {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB
                        },
                },
        },
        {
-               name:   "F32Mul",
-               argLen: 2,
-               asm:    wasm.AF32Mul,
+               name:           "MOVDstoreconst",
+               auxType:        auxSymValAndOff,
+               argLen:         2,
+               faultOnNilArg0: true,
+               symEffect:      SymWrite,
+               asm:            s390x.AMOVD,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
-                               {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
-                       },
-                       outputs: []outputInfo{
-                               {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+                               {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB
                        },
                },
        },
        {
-               name:   "F32Div",
-               argLen: 2,
-               asm:    wasm.AF32Div,
+               name:           "CLEAR",
+               auxType:        auxSymValAndOff,
+               argLen:         2,
+               clobberFlags:   true,
+               faultOnNilArg0: true,
+               symEffect:      SymWrite,
+               asm:            s390x.ACLEAR,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
-                               {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
-                       },
-                       outputs: []outputInfo{
-                               {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+                               {0, 23550}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
                        },
                },
        },
        {
-               name:   "F64Neg",
-               argLen: 1,
-               asm:    wasm.AF64Neg,
+               name:         "CALLstatic",
+               auxType:      auxCallOff,
+               argLen:       1,
+               clobberFlags: true,
+               call:         true,
                reg: regInfo{
-                       inputs: []inputInfo{
-                               {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
-                       },
-                       outputs: []outputInfo{
-                               {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
-                       },
+                       clobbers: 4294933503, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 g R14 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
                },
        },
        {
-               name:   "F64Add",
-               argLen: 2,
-               asm:    wasm.AF64Add,
+               name:         "CALLtail",
+               auxType:      auxCallOff,
+               argLen:       1,
+               clobberFlags: true,
+               call:         true,
+               tailCall:     true,
                reg: regInfo{
-                       inputs: []inputInfo{
-                               {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
-                               {1, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
-                       },
-                       outputs: []outputInfo{
-                               {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
-                       },
+                       clobbers: 4294933503, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 g R14 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
                },
        },
        {
-               name:   "F64Sub",
-               argLen: 2,
-               asm:    wasm.AF64Sub,
+               name:         "CALLclosure",
+               auxType:      auxCallOff,
+               argLen:       3,
+               clobberFlags: true,
+               call:         true,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
-                               {1, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
-                       },
-                       outputs: []outputInfo{
-                               {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {1, 4096},  // R12
+                               {0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
                        },
+                       clobbers: 4294933503, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 g R14 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
                },
        },
        {
-               name:   "F64Mul",
-               argLen: 2,
-               asm:    wasm.AF64Mul,
+               name:         "CALLinter",
+               auxType:      auxCallOff,
+               argLen:       2,
+               clobberFlags: true,
+               call:         true,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
-                               {1, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
-                       },
-                       outputs: []outputInfo{
-                               {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {0, 23550}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
                        },
+                       clobbers: 4294933503, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 g R14 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
                },
        },
        {
-               name:   "F64Div",
-               argLen: 2,
-               asm:    wasm.AF64Div,
+               name:   "InvertFlags",
+               argLen: 1,
+               reg:    regInfo{},
+       },
+       {
+               name:   "LoweredGetG",
+               argLen: 1,
                reg: regInfo{
-                       inputs: []inputInfo{
-                               {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
-                               {1, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
-                       },
                        outputs: []outputInfo{
-                               {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
                        },
                },
        },
        {
-               name:   "I64TruncSatF64S",
-               argLen: 1,
-               asm:    wasm.AI64TruncSatF64S,
+               name:      "LoweredGetClosurePtr",
+               argLen:    0,
+               zeroWidth: true,
                reg: regInfo{
-                       inputs: []inputInfo{
-                               {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
-                       },
                        outputs: []outputInfo{
-                               {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
+                               {0, 4096}, // R12
                        },
                },
        },
        {
-               name:   "I64TruncSatF64U",
-               argLen: 1,
-               asm:    wasm.AI64TruncSatF64U,
+               name:              "LoweredGetCallerSP",
+               argLen:            1,
+               rematerializeable: true,
                reg: regInfo{
-                       inputs: []inputInfo{
-                               {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
-                       },
                        outputs: []outputInfo{
-                               {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
+                               {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
                        },
                },
        },
        {
-               name:   "I64TruncSatF32S",
-               argLen: 1,
-               asm:    wasm.AI64TruncSatF32S,
+               name:              "LoweredGetCallerPC",
+               argLen:            0,
+               rematerializeable: true,
                reg: regInfo{
-                       inputs: []inputInfo{
-                               {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
-                       },
                        outputs: []outputInfo{
-                               {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
+                               {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
                        },
                },
        },
        {
-               name:   "I64TruncSatF32U",
-               argLen: 1,
-               asm:    wasm.AI64TruncSatF32U,
+               name:           "LoweredNilCheck",
+               argLen:         2,
+               clobberFlags:   true,
+               nilCheck:       true,
+               faultOnNilArg0: true,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
-                       },
-                       outputs: []outputInfo{
-                               {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
+                               {0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
                        },
                },
        },
        {
-               name:   "F32ConvertI64S",
-               argLen: 1,
-               asm:    wasm.AF32ConvertI64S,
+               name:         "LoweredRound32F",
+               argLen:       1,
+               resultInArg0: true,
+               zeroWidth:    true,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
+                               {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
                        },
                        outputs: []outputInfo{
                                {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
@@ -53124,12 +55115,13 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:   "F32ConvertI64U",
-               argLen: 1,
-               asm:    wasm.AF32ConvertI64U,
+               name:         "LoweredRound64F",
+               argLen:       1,
+               resultInArg0: true,
+               zeroWidth:    true,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
+                               {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
                        },
                        outputs: []outputInfo{
                                {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
@@ -53137,10242 +55129,14022 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:   "F64ConvertI64S",
-               argLen: 1,
-               asm:    wasm.AF64ConvertI64S,
+               name:         "LoweredWB",
+               auxType:      auxInt64,
+               argLen:       1,
+               clobberFlags: true,
                reg: regInfo{
-                       inputs: []inputInfo{
-                               {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
-                       },
+                       clobbers: 4294918146, // R1 R14 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
                        outputs: []outputInfo{
-                               {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {0, 512}, // R9
                        },
                },
        },
        {
-               name:   "F64ConvertI64U",
-               argLen: 1,
-               asm:    wasm.AF64ConvertI64U,
+               name:    "LoweredPanicBoundsA",
+               auxType: auxInt64,
+               argLen:  3,
+               call:    true,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
-                       },
-                       outputs: []outputInfo{
-                               {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {0, 4}, // R2
+                               {1, 8}, // R3
                        },
                },
        },
        {
-               name:   "F32DemoteF64",
-               argLen: 1,
-               asm:    wasm.AF32DemoteF64,
+               name:    "LoweredPanicBoundsB",
+               auxType: auxInt64,
+               argLen:  3,
+               call:    true,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
-                       },
-                       outputs: []outputInfo{
-                               {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+                               {0, 2}, // R1
+                               {1, 4}, // R2
                        },
                },
        },
        {
-               name:   "F64PromoteF32",
-               argLen: 1,
-               asm:    wasm.AF64PromoteF32,
+               name:    "LoweredPanicBoundsC",
+               auxType: auxInt64,
+               argLen:  3,
+               call:    true,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
-                       },
-                       outputs: []outputInfo{
-                               {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {0, 1}, // R0
+                               {1, 2}, // R1
                        },
                },
        },
        {
-               name:   "I64Extend8S",
+               name:   "FlagEQ",
+               argLen: 0,
+               reg:    regInfo{},
+       },
+       {
+               name:   "FlagLT",
+               argLen: 0,
+               reg:    regInfo{},
+       },
+       {
+               name:   "FlagGT",
+               argLen: 0,
+               reg:    regInfo{},
+       },
+       {
+               name:   "FlagOV",
+               argLen: 0,
+               reg:    regInfo{},
+       },
+       {
+               name:   "SYNC",
                argLen: 1,
-               asm:    wasm.AI64Extend8S,
+               asm:    s390x.ASYNC,
+               reg:    regInfo{},
+       },
+       {
+               name:           "MOVBZatomicload",
+               auxType:        auxSymOff,
+               argLen:         2,
+               faultOnNilArg0: true,
+               symEffect:      SymRead,
+               asm:            s390x.AMOVBZ,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
+                               {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB
                        },
                        outputs: []outputInfo{
-                               {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
+                               {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
                        },
                },
        },
        {
-               name:   "I64Extend16S",
-               argLen: 1,
-               asm:    wasm.AI64Extend16S,
+               name:           "MOVWZatomicload",
+               auxType:        auxSymOff,
+               argLen:         2,
+               faultOnNilArg0: true,
+               symEffect:      SymRead,
+               asm:            s390x.AMOVWZ,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
+                               {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB
                        },
                        outputs: []outputInfo{
-                               {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
+                               {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
                        },
                },
        },
        {
-               name:   "I64Extend32S",
-               argLen: 1,
-               asm:    wasm.AI64Extend32S,
+               name:           "MOVDatomicload",
+               auxType:        auxSymOff,
+               argLen:         2,
+               faultOnNilArg0: true,
+               symEffect:      SymRead,
+               asm:            s390x.AMOVD,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
+                               {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB
                        },
                        outputs: []outputInfo{
-                               {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
+                               {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
                        },
                },
        },
        {
-               name:   "F32Sqrt",
-               argLen: 1,
-               asm:    wasm.AF32Sqrt,
+               name:           "MOVBatomicstore",
+               auxType:        auxSymOff,
+               argLen:         3,
+               clobberFlags:   true,
+               faultOnNilArg0: true,
+               hasSideEffects: true,
+               symEffect:      SymWrite,
+               asm:            s390x.AMOVB,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
-                       },
-                       outputs: []outputInfo{
-                               {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+                               {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB
+                               {1, 56319},      // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
                        },
                },
        },
        {
-               name:   "F32Trunc",
-               argLen: 1,
-               asm:    wasm.AF32Trunc,
+               name:           "MOVWatomicstore",
+               auxType:        auxSymOff,
+               argLen:         3,
+               clobberFlags:   true,
+               faultOnNilArg0: true,
+               hasSideEffects: true,
+               symEffect:      SymWrite,
+               asm:            s390x.AMOVW,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
-                       },
-                       outputs: []outputInfo{
-                               {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+                               {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB
+                               {1, 56319},      // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
                        },
                },
        },
        {
-               name:   "F32Ceil",
-               argLen: 1,
-               asm:    wasm.AF32Ceil,
+               name:           "MOVDatomicstore",
+               auxType:        auxSymOff,
+               argLen:         3,
+               clobberFlags:   true,
+               faultOnNilArg0: true,
+               hasSideEffects: true,
+               symEffect:      SymWrite,
+               asm:            s390x.AMOVD,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
-                       },
-                       outputs: []outputInfo{
-                               {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+                               {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB
+                               {1, 56319},      // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
                        },
                },
        },
        {
-               name:   "F32Floor",
-               argLen: 1,
-               asm:    wasm.AF32Floor,
+               name:           "LAA",
+               auxType:        auxSymOff,
+               argLen:         3,
+               clobberFlags:   true,
+               faultOnNilArg0: true,
+               hasSideEffects: true,
+               symEffect:      SymRdWr,
+               asm:            s390x.ALAA,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+                               {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB
+                               {1, 56319},      // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
                        },
                        outputs: []outputInfo{
-                               {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+                               {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
                        },
                },
        },
        {
-               name:   "F32Nearest",
-               argLen: 1,
-               asm:    wasm.AF32Nearest,
+               name:           "LAAG",
+               auxType:        auxSymOff,
+               argLen:         3,
+               clobberFlags:   true,
+               faultOnNilArg0: true,
+               hasSideEffects: true,
+               symEffect:      SymRdWr,
+               asm:            s390x.ALAAG,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+                               {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB
+                               {1, 56319},      // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
                        },
                        outputs: []outputInfo{
-                               {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+                               {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
                        },
                },
        },
        {
-               name:   "F32Abs",
-               argLen: 1,
-               asm:    wasm.AF32Abs,
+               name:   "AddTupleFirst32",
+               argLen: 2,
+               reg:    regInfo{},
+       },
+       {
+               name:   "AddTupleFirst64",
+               argLen: 2,
+               reg:    regInfo{},
+       },
+       {
+               name:           "LAN",
+               argLen:         3,
+               clobberFlags:   true,
+               hasSideEffects: true,
+               asm:            s390x.ALAN,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
-                       },
-                       outputs: []outputInfo{
-                               {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+                               {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB
+                               {1, 56319},      // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
                        },
                },
        },
        {
-               name:   "F32Copysign",
-               argLen: 2,
-               asm:    wasm.AF32Copysign,
+               name:           "LANfloor",
+               argLen:         3,
+               clobberFlags:   true,
+               hasSideEffects: true,
+               asm:            s390x.ALAN,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
-                               {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
-                       },
-                       outputs: []outputInfo{
-                               {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+                               {0, 2},     // R1
+                               {1, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
                        },
+                       clobbers: 2, // R1
                },
        },
        {
-               name:   "F64Sqrt",
-               argLen: 1,
-               asm:    wasm.AF64Sqrt,
+               name:           "LAO",
+               argLen:         3,
+               clobberFlags:   true,
+               hasSideEffects: true,
+               asm:            s390x.ALAO,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB
+                               {1, 56319},      // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
                        },
-                       outputs: []outputInfo{
-                               {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+               },
+       },
+       {
+               name:           "LAOfloor",
+               argLen:         3,
+               clobberFlags:   true,
+               hasSideEffects: true,
+               asm:            s390x.ALAO,
+               reg: regInfo{
+                       inputs: []inputInfo{
+                               {0, 2},     // R1
+                               {1, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
                        },
+                       clobbers: 2, // R1
                },
        },
        {
-               name:   "F64Trunc",
-               argLen: 1,
-               asm:    wasm.AF64Trunc,
+               name:           "LoweredAtomicCas32",
+               auxType:        auxSymOff,
+               argLen:         4,
+               clobberFlags:   true,
+               faultOnNilArg0: true,
+               hasSideEffects: true,
+               symEffect:      SymRdWr,
+               asm:            s390x.ACS,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {1, 1},     // R0
+                               {0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
+                               {2, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
                        },
+                       clobbers: 1, // R0
                        outputs: []outputInfo{
-                               {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {1, 0},
+                               {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
                        },
                },
        },
        {
-               name:   "F64Ceil",
-               argLen: 1,
-               asm:    wasm.AF64Ceil,
+               name:           "LoweredAtomicCas64",
+               auxType:        auxSymOff,
+               argLen:         4,
+               clobberFlags:   true,
+               faultOnNilArg0: true,
+               hasSideEffects: true,
+               symEffect:      SymRdWr,
+               asm:            s390x.ACSG,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {1, 1},     // R0
+                               {0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
+                               {2, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
                        },
+                       clobbers: 1, // R0
                        outputs: []outputInfo{
-                               {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {1, 0},
+                               {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
                        },
                },
        },
        {
-               name:   "F64Floor",
-               argLen: 1,
-               asm:    wasm.AF64Floor,
+               name:           "LoweredAtomicExchange32",
+               auxType:        auxSymOff,
+               argLen:         3,
+               clobberFlags:   true,
+               faultOnNilArg0: true,
+               hasSideEffects: true,
+               symEffect:      SymRdWr,
+               asm:            s390x.ACS,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
+                               {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
                        },
                        outputs: []outputInfo{
-                               {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {1, 0},
+                               {0, 1}, // R0
                        },
                },
        },
        {
-               name:   "F64Nearest",
-               argLen: 1,
-               asm:    wasm.AF64Nearest,
+               name:           "LoweredAtomicExchange64",
+               auxType:        auxSymOff,
+               argLen:         3,
+               clobberFlags:   true,
+               faultOnNilArg0: true,
+               hasSideEffects: true,
+               symEffect:      SymRdWr,
+               asm:            s390x.ACSG,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
+                               {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
                        },
                        outputs: []outputInfo{
-                               {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {1, 0},
+                               {0, 1}, // R0
                        },
                },
        },
        {
-               name:   "F64Abs",
-               argLen: 1,
-               asm:    wasm.AF64Abs,
+               name:         "FLOGR",
+               argLen:       1,
+               clobberFlags: true,
+               asm:          s390x.AFLOGR,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
                        },
+                       clobbers: 2, // R1
                        outputs: []outputInfo{
-                               {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {0, 1}, // R0
                        },
                },
        },
        {
-               name:   "F64Copysign",
-               argLen: 2,
-               asm:    wasm.AF64Copysign,
+               name:         "POPCNT",
+               argLen:       1,
+               clobberFlags: true,
+               asm:          s390x.APOPCNT,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
-                               {1, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
                        },
                        outputs: []outputInfo{
-                               {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
                        },
                },
        },
        {
-               name:   "I64Ctz",
-               argLen: 1,
-               asm:    wasm.AI64Ctz,
+               name:   "MLGR",
+               argLen: 2,
+               asm:    s390x.AMLGR,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
+                               {1, 8},     // R3
+                               {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
                        },
                        outputs: []outputInfo{
-                               {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
+                               {0, 4}, // R2
+                               {1, 8}, // R3
                        },
                },
        },
        {
-               name:   "I64Clz",
+               name:   "SumBytes2",
                argLen: 1,
-               asm:    wasm.AI64Clz,
+               reg:    regInfo{},
+       },
+       {
+               name:   "SumBytes4",
+               argLen: 1,
+               reg:    regInfo{},
+       },
+       {
+               name:   "SumBytes8",
+               argLen: 1,
+               reg:    regInfo{},
+       },
+       {
+               name:           "STMG2",
+               auxType:        auxSymOff,
+               argLen:         4,
+               clobberFlags:   true,
+               faultOnNilArg0: true,
+               symEffect:      SymWrite,
+               asm:            s390x.ASTMG,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
-                       },
-                       outputs: []outputInfo{
-                               {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
+                               {1, 2},     // R1
+                               {2, 4},     // R2
+                               {0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
                        },
                },
        },
        {
-               name:   "I32Rotl",
-               argLen: 2,
-               asm:    wasm.AI32Rotl,
+               name:           "STMG3",
+               auxType:        auxSymOff,
+               argLen:         5,
+               clobberFlags:   true,
+               faultOnNilArg0: true,
+               symEffect:      SymWrite,
+               asm:            s390x.ASTMG,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
-                               {1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
-                       },
-                       outputs: []outputInfo{
-                               {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
+                               {1, 2},     // R1
+                               {2, 4},     // R2
+                               {3, 8},     // R3
+                               {0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
                        },
                },
        },
        {
-               name:   "I64Rotl",
-               argLen: 2,
-               asm:    wasm.AI64Rotl,
+               name:           "STMG4",
+               auxType:        auxSymOff,
+               argLen:         6,
+               clobberFlags:   true,
+               faultOnNilArg0: true,
+               symEffect:      SymWrite,
+               asm:            s390x.ASTMG,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
-                               {1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
-                       },
-                       outputs: []outputInfo{
-                               {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
+                               {1, 2},     // R1
+                               {2, 4},     // R2
+                               {3, 8},     // R3
+                               {4, 16},    // R4
+                               {0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
                        },
                },
        },
        {
-               name:   "I64Popcnt",
-               argLen: 1,
-               asm:    wasm.AI64Popcnt,
+               name:           "STM2",
+               auxType:        auxSymOff,
+               argLen:         4,
+               clobberFlags:   true,
+               faultOnNilArg0: true,
+               symEffect:      SymWrite,
+               asm:            s390x.ASTMY,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
-                       },
-                       outputs: []outputInfo{
-                               {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
+                               {1, 2},     // R1
+                               {2, 4},     // R2
+                               {0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
                        },
                },
        },
-
        {
-               name:        "Add8",
-               argLen:      2,
-               commutative: true,
-               generic:     true,
+               name:           "STM3",
+               auxType:        auxSymOff,
+               argLen:         5,
+               clobberFlags:   true,
+               faultOnNilArg0: true,
+               symEffect:      SymWrite,
+               asm:            s390x.ASTMY,
+               reg: regInfo{
+                       inputs: []inputInfo{
+                               {1, 2},     // R1
+                               {2, 4},     // R2
+                               {3, 8},     // R3
+                               {0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
+                       },
+               },
        },
        {
-               name:        "Add16",
-               argLen:      2,
-               commutative: true,
-               generic:     true,
+               name:           "STM4",
+               auxType:        auxSymOff,
+               argLen:         6,
+               clobberFlags:   true,
+               faultOnNilArg0: true,
+               symEffect:      SymWrite,
+               asm:            s390x.ASTMY,
+               reg: regInfo{
+                       inputs: []inputInfo{
+                               {1, 2},     // R1
+                               {2, 4},     // R2
+                               {3, 8},     // R3
+                               {4, 16},    // R4
+                               {0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
+                       },
+               },
        },
        {
-               name:        "Add32",
-               argLen:      2,
-               commutative: true,
-               generic:     true,
+               name:           "LoweredMove",
+               auxType:        auxInt64,
+               argLen:         4,
+               clobberFlags:   true,
+               faultOnNilArg0: true,
+               faultOnNilArg1: true,
+               reg: regInfo{
+                       inputs: []inputInfo{
+                               {0, 2},     // R1
+                               {1, 4},     // R2
+                               {2, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
+                       },
+                       clobbers: 6, // R1 R2
+               },
        },
        {
-               name:        "Add64",
-               argLen:      2,
-               commutative: true,
-               generic:     true,
+               name:           "LoweredZero",
+               auxType:        auxInt64,
+               argLen:         3,
+               clobberFlags:   true,
+               faultOnNilArg0: true,
+               reg: regInfo{
+                       inputs: []inputInfo{
+                               {0, 2},     // R1
+                               {1, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
+                       },
+                       clobbers: 2, // R1
+               },
        },
+
        {
-               name:    "AddPtr",
-               argLen:  2,
-               generic: true,
+               name:    "LoweredStaticCall",
+               auxType: auxCallOff,
+               argLen:  1,
+               call:    true,
+               reg: regInfo{
+                       clobbers: 844424930131967, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 g
+               },
        },
        {
-               name:        "Add32F",
-               argLen:      2,
-               commutative: true,
-               generic:     true,
+               name:     "LoweredTailCall",
+               auxType:  auxCallOff,
+               argLen:   1,
+               call:     true,
+               tailCall: true,
+               reg: regInfo{
+                       clobbers: 844424930131967, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 g
+               },
        },
        {
-               name:        "Add64F",
-               argLen:      2,
-               commutative: true,
-               generic:     true,
+               name:    "LoweredClosureCall",
+               auxType: auxCallOff,
+               argLen:  3,
+               call:    true,
+               reg: regInfo{
+                       inputs: []inputInfo{
+                               {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
+                               {1, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
+                       },
+                       clobbers: 844424930131967, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 g
+               },
        },
        {
-               name:    "Sub8",
+               name:    "LoweredInterCall",
+               auxType: auxCallOff,
                argLen:  2,
-               generic: true,
+               call:    true,
+               reg: regInfo{
+                       inputs: []inputInfo{
+                               {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
+                       },
+                       clobbers: 844424930131967, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 g
+               },
        },
        {
-               name:    "Sub16",
-               argLen:  2,
-               generic: true,
+               name:              "LoweredAddr",
+               auxType:           auxSymOff,
+               argLen:            1,
+               rematerializeable: true,
+               symEffect:         SymAddr,
+               reg: regInfo{
+                       inputs: []inputInfo{
+                               {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
+                       },
+                       outputs: []outputInfo{
+                               {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
+                       },
+               },
        },
        {
-               name:    "Sub32",
-               argLen:  2,
+               name:    "LoweredMove",
+               auxType: auxInt64,
+               argLen:  3,
+               reg: regInfo{
+                       inputs: []inputInfo{
+                               {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
+                               {1, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
+                       },
+               },
+       },
+       {
+               name:    "LoweredZero",
+               auxType: auxInt64,
+               argLen:  2,
+               reg: regInfo{
+                       inputs: []inputInfo{
+                               {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
+                       },
+               },
+       },
+       {
+               name:   "LoweredGetClosurePtr",
+               argLen: 0,
+               reg: regInfo{
+                       outputs: []outputInfo{
+                               {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
+                       },
+               },
+       },
+       {
+               name:              "LoweredGetCallerPC",
+               argLen:            0,
+               rematerializeable: true,
+               reg: regInfo{
+                       outputs: []outputInfo{
+                               {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
+                       },
+               },
+       },
+       {
+               name:              "LoweredGetCallerSP",
+               argLen:            1,
+               rematerializeable: true,
+               reg: regInfo{
+                       outputs: []outputInfo{
+                               {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
+                       },
+               },
+       },
+       {
+               name:           "LoweredNilCheck",
+               argLen:         2,
+               nilCheck:       true,
+               faultOnNilArg0: true,
+               reg: regInfo{
+                       inputs: []inputInfo{
+                               {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
+                       },
+               },
+       },
+       {
+               name:    "LoweredWB",
+               auxType: auxInt64,
+               argLen:  1,
+               reg: regInfo{
+                       clobbers: 844424930131967, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 g
+                       outputs: []outputInfo{
+                               {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
+                       },
+               },
+       },
+       {
+               name:   "LoweredConvert",
+               argLen: 2,
+               reg: regInfo{
+                       inputs: []inputInfo{
+                               {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
+                       },
+                       outputs: []outputInfo{
+                               {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
+                       },
+               },
+       },
+       {
+               name:   "Select",
+               argLen: 3,
+               asm:    wasm.ASelect,
+               reg: regInfo{
+                       inputs: []inputInfo{
+                               {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
+                               {1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
+                               {2, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
+                       },
+                       outputs: []outputInfo{
+                               {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
+                       },
+               },
+       },
+       {
+               name:    "I64Load8U",
+               auxType: auxInt64,
+               argLen:  2,
+               asm:     wasm.AI64Load8U,
+               reg: regInfo{
+                       inputs: []inputInfo{
+                               {0, 1407374883618815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP SB
+                       },
+                       outputs: []outputInfo{
+                               {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
+                       },
+               },
+       },
+       {
+               name:    "I64Load8S",
+               auxType: auxInt64,
+               argLen:  2,
+               asm:     wasm.AI64Load8S,
+               reg: regInfo{
+                       inputs: []inputInfo{
+                               {0, 1407374883618815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP SB
+                       },
+                       outputs: []outputInfo{
+                               {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
+                       },
+               },
+       },
+       {
+               name:    "I64Load16U",
+               auxType: auxInt64,
+               argLen:  2,
+               asm:     wasm.AI64Load16U,
+               reg: regInfo{
+                       inputs: []inputInfo{
+                               {0, 1407374883618815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP SB
+                       },
+                       outputs: []outputInfo{
+                               {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
+                       },
+               },
+       },
+       {
+               name:    "I64Load16S",
+               auxType: auxInt64,
+               argLen:  2,
+               asm:     wasm.AI64Load16S,
+               reg: regInfo{
+                       inputs: []inputInfo{
+                               {0, 1407374883618815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP SB
+                       },
+                       outputs: []outputInfo{
+                               {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
+                       },
+               },
+       },
+       {
+               name:    "I64Load32U",
+               auxType: auxInt64,
+               argLen:  2,
+               asm:     wasm.AI64Load32U,
+               reg: regInfo{
+                       inputs: []inputInfo{
+                               {0, 1407374883618815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP SB
+                       },
+                       outputs: []outputInfo{
+                               {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
+                       },
+               },
+       },
+       {
+               name:    "I64Load32S",
+               auxType: auxInt64,
+               argLen:  2,
+               asm:     wasm.AI64Load32S,
+               reg: regInfo{
+                       inputs: []inputInfo{
+                               {0, 1407374883618815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP SB
+                       },
+                       outputs: []outputInfo{
+                               {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
+                       },
+               },
+       },
+       {
+               name:    "I64Load",
+               auxType: auxInt64,
+               argLen:  2,
+               asm:     wasm.AI64Load,
+               reg: regInfo{
+                       inputs: []inputInfo{
+                               {0, 1407374883618815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP SB
+                       },
+                       outputs: []outputInfo{
+                               {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
+                       },
+               },
+       },
+       {
+               name:    "I64Store8",
+               auxType: auxInt64,
+               argLen:  3,
+               asm:     wasm.AI64Store8,
+               reg: regInfo{
+                       inputs: []inputInfo{
+                               {1, 281474976776191},  // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
+                               {0, 1407374883618815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP SB
+                       },
+               },
+       },
+       {
+               name:    "I64Store16",
+               auxType: auxInt64,
+               argLen:  3,
+               asm:     wasm.AI64Store16,
+               reg: regInfo{
+                       inputs: []inputInfo{
+                               {1, 281474976776191},  // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
+                               {0, 1407374883618815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP SB
+                       },
+               },
+       },
+       {
+               name:    "I64Store32",
+               auxType: auxInt64,
+               argLen:  3,
+               asm:     wasm.AI64Store32,
+               reg: regInfo{
+                       inputs: []inputInfo{
+                               {1, 281474976776191},  // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
+                               {0, 1407374883618815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP SB
+                       },
+               },
+       },
+       {
+               name:    "I64Store",
+               auxType: auxInt64,
+               argLen:  3,
+               asm:     wasm.AI64Store,
+               reg: regInfo{
+                       inputs: []inputInfo{
+                               {1, 281474976776191},  // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
+                               {0, 1407374883618815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP SB
+                       },
+               },
+       },
+       {
+               name:    "F32Load",
+               auxType: auxInt64,
+               argLen:  2,
+               asm:     wasm.AF32Load,
+               reg: regInfo{
+                       inputs: []inputInfo{
+                               {0, 1407374883618815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP SB
+                       },
+                       outputs: []outputInfo{
+                               {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+                       },
+               },
+       },
+       {
+               name:    "F64Load",
+               auxType: auxInt64,
+               argLen:  2,
+               asm:     wasm.AF64Load,
+               reg: regInfo{
+                       inputs: []inputInfo{
+                               {0, 1407374883618815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP SB
+                       },
+                       outputs: []outputInfo{
+                               {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                       },
+               },
+       },
+       {
+               name:    "F32Store",
+               auxType: auxInt64,
+               argLen:  3,
+               asm:     wasm.AF32Store,
+               reg: regInfo{
+                       inputs: []inputInfo{
+                               {1, 4294901760},       // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+                               {0, 1407374883618815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP SB
+                       },
+               },
+       },
+       {
+               name:    "F64Store",
+               auxType: auxInt64,
+               argLen:  3,
+               asm:     wasm.AF64Store,
+               reg: regInfo{
+                       inputs: []inputInfo{
+                               {1, 281470681743360},  // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {0, 1407374883618815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP SB
+                       },
+               },
+       },
+       {
+               name:              "I64Const",
+               auxType:           auxInt64,
+               argLen:            0,
+               rematerializeable: true,
+               reg: regInfo{
+                       outputs: []outputInfo{
+                               {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
+                       },
+               },
+       },
+       {
+               name:              "F32Const",
+               auxType:           auxFloat32,
+               argLen:            0,
+               rematerializeable: true,
+               reg: regInfo{
+                       outputs: []outputInfo{
+                               {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+                       },
+               },
+       },
+       {
+               name:              "F64Const",
+               auxType:           auxFloat64,
+               argLen:            0,
+               rematerializeable: true,
+               reg: regInfo{
+                       outputs: []outputInfo{
+                               {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                       },
+               },
+       },
+       {
+               name:   "I64Eqz",
+               argLen: 1,
+               asm:    wasm.AI64Eqz,
+               reg: regInfo{
+                       inputs: []inputInfo{
+                               {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
+                       },
+                       outputs: []outputInfo{
+                               {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
+                       },
+               },
+       },
+       {
+               name:   "I64Eq",
+               argLen: 2,
+               asm:    wasm.AI64Eq,
+               reg: regInfo{
+                       inputs: []inputInfo{
+                               {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
+                               {1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
+                       },
+                       outputs: []outputInfo{
+                               {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
+                       },
+               },
+       },
+       {
+               name:   "I64Ne",
+               argLen: 2,
+               asm:    wasm.AI64Ne,
+               reg: regInfo{
+                       inputs: []inputInfo{
+                               {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
+                               {1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
+                       },
+                       outputs: []outputInfo{
+                               {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
+                       },
+               },
+       },
+       {
+               name:   "I64LtS",
+               argLen: 2,
+               asm:    wasm.AI64LtS,
+               reg: regInfo{
+                       inputs: []inputInfo{
+                               {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
+                               {1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
+                       },
+                       outputs: []outputInfo{
+                               {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
+                       },
+               },
+       },
+       {
+               name:   "I64LtU",
+               argLen: 2,
+               asm:    wasm.AI64LtU,
+               reg: regInfo{
+                       inputs: []inputInfo{
+                               {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
+                               {1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
+                       },
+                       outputs: []outputInfo{
+                               {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
+                       },
+               },
+       },
+       {
+               name:   "I64GtS",
+               argLen: 2,
+               asm:    wasm.AI64GtS,
+               reg: regInfo{
+                       inputs: []inputInfo{
+                               {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
+                               {1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
+                       },
+                       outputs: []outputInfo{
+                               {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
+                       },
+               },
+       },
+       {
+               name:   "I64GtU",
+               argLen: 2,
+               asm:    wasm.AI64GtU,
+               reg: regInfo{
+                       inputs: []inputInfo{
+                               {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
+                               {1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
+                       },
+                       outputs: []outputInfo{
+                               {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
+                       },
+               },
+       },
+       {
+               name:   "I64LeS",
+               argLen: 2,
+               asm:    wasm.AI64LeS,
+               reg: regInfo{
+                       inputs: []inputInfo{
+                               {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
+                               {1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
+                       },
+                       outputs: []outputInfo{
+                               {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
+                       },
+               },
+       },
+       {
+               name:   "I64LeU",
+               argLen: 2,
+               asm:    wasm.AI64LeU,
+               reg: regInfo{
+                       inputs: []inputInfo{
+                               {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
+                               {1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
+                       },
+                       outputs: []outputInfo{
+                               {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
+                       },
+               },
+       },
+       {
+               name:   "I64GeS",
+               argLen: 2,
+               asm:    wasm.AI64GeS,
+               reg: regInfo{
+                       inputs: []inputInfo{
+                               {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
+                               {1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
+                       },
+                       outputs: []outputInfo{
+                               {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
+                       },
+               },
+       },
+       {
+               name:   "I64GeU",
+               argLen: 2,
+               asm:    wasm.AI64GeU,
+               reg: regInfo{
+                       inputs: []inputInfo{
+                               {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
+                               {1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
+                       },
+                       outputs: []outputInfo{
+                               {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
+                       },
+               },
+       },
+       {
+               name:   "F32Eq",
+               argLen: 2,
+               asm:    wasm.AF32Eq,
+               reg: regInfo{
+                       inputs: []inputInfo{
+                               {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+                               {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+                       },
+                       outputs: []outputInfo{
+                               {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
+                       },
+               },
+       },
+       {
+               name:   "F32Ne",
+               argLen: 2,
+               asm:    wasm.AF32Ne,
+               reg: regInfo{
+                       inputs: []inputInfo{
+                               {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+                               {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+                       },
+                       outputs: []outputInfo{
+                               {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
+                       },
+               },
+       },
+       {
+               name:   "F32Lt",
+               argLen: 2,
+               asm:    wasm.AF32Lt,
+               reg: regInfo{
+                       inputs: []inputInfo{
+                               {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+                               {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+                       },
+                       outputs: []outputInfo{
+                               {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
+                       },
+               },
+       },
+       {
+               name:   "F32Gt",
+               argLen: 2,
+               asm:    wasm.AF32Gt,
+               reg: regInfo{
+                       inputs: []inputInfo{
+                               {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+                               {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+                       },
+                       outputs: []outputInfo{
+                               {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
+                       },
+               },
+       },
+       {
+               name:   "F32Le",
+               argLen: 2,
+               asm:    wasm.AF32Le,
+               reg: regInfo{
+                       inputs: []inputInfo{
+                               {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+                               {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+                       },
+                       outputs: []outputInfo{
+                               {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
+                       },
+               },
+       },
+       {
+               name:   "F32Ge",
+               argLen: 2,
+               asm:    wasm.AF32Ge,
+               reg: regInfo{
+                       inputs: []inputInfo{
+                               {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+                               {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+                       },
+                       outputs: []outputInfo{
+                               {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
+                       },
+               },
+       },
+       {
+               name:   "F64Eq",
+               argLen: 2,
+               asm:    wasm.AF64Eq,
+               reg: regInfo{
+                       inputs: []inputInfo{
+                               {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {1, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                       },
+                       outputs: []outputInfo{
+                               {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
+                       },
+               },
+       },
+       {
+               name:   "F64Ne",
+               argLen: 2,
+               asm:    wasm.AF64Ne,
+               reg: regInfo{
+                       inputs: []inputInfo{
+                               {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {1, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                       },
+                       outputs: []outputInfo{
+                               {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
+                       },
+               },
+       },
+       {
+               name:   "F64Lt",
+               argLen: 2,
+               asm:    wasm.AF64Lt,
+               reg: regInfo{
+                       inputs: []inputInfo{
+                               {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {1, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                       },
+                       outputs: []outputInfo{
+                               {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
+                       },
+               },
+       },
+       {
+               name:   "F64Gt",
+               argLen: 2,
+               asm:    wasm.AF64Gt,
+               reg: regInfo{
+                       inputs: []inputInfo{
+                               {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {1, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                       },
+                       outputs: []outputInfo{
+                               {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
+                       },
+               },
+       },
+       {
+               name:   "F64Le",
+               argLen: 2,
+               asm:    wasm.AF64Le,
+               reg: regInfo{
+                       inputs: []inputInfo{
+                               {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {1, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                       },
+                       outputs: []outputInfo{
+                               {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
+                       },
+               },
+       },
+       {
+               name:   "F64Ge",
+               argLen: 2,
+               asm:    wasm.AF64Ge,
+               reg: regInfo{
+                       inputs: []inputInfo{
+                               {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {1, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                       },
+                       outputs: []outputInfo{
+                               {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
+                       },
+               },
+       },
+       {
+               name:   "I64Add",
+               argLen: 2,
+               asm:    wasm.AI64Add,
+               reg: regInfo{
+                       inputs: []inputInfo{
+                               {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
+                               {1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
+                       },
+                       outputs: []outputInfo{
+                               {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
+                       },
+               },
+       },
+       {
+               name:    "I64AddConst",
+               auxType: auxInt64,
+               argLen:  1,
+               asm:     wasm.AI64Add,
+               reg: regInfo{
+                       inputs: []inputInfo{
+                               {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
+                       },
+                       outputs: []outputInfo{
+                               {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
+                       },
+               },
+       },
+       {
+               name:   "I64Sub",
+               argLen: 2,
+               asm:    wasm.AI64Sub,
+               reg: regInfo{
+                       inputs: []inputInfo{
+                               {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
+                               {1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
+                       },
+                       outputs: []outputInfo{
+                               {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
+                       },
+               },
+       },
+       {
+               name:   "I64Mul",
+               argLen: 2,
+               asm:    wasm.AI64Mul,
+               reg: regInfo{
+                       inputs: []inputInfo{
+                               {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
+                               {1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
+                       },
+                       outputs: []outputInfo{
+                               {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
+                       },
+               },
+       },
+       {
+               name:   "I64DivS",
+               argLen: 2,
+               asm:    wasm.AI64DivS,
+               reg: regInfo{
+                       inputs: []inputInfo{
+                               {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
+                               {1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
+                       },
+                       outputs: []outputInfo{
+                               {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
+                       },
+               },
+       },
+       {
+               name:   "I64DivU",
+               argLen: 2,
+               asm:    wasm.AI64DivU,
+               reg: regInfo{
+                       inputs: []inputInfo{
+                               {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
+                               {1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
+                       },
+                       outputs: []outputInfo{
+                               {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
+                       },
+               },
+       },
+       {
+               name:   "I64RemS",
+               argLen: 2,
+               asm:    wasm.AI64RemS,
+               reg: regInfo{
+                       inputs: []inputInfo{
+                               {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
+                               {1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
+                       },
+                       outputs: []outputInfo{
+                               {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
+                       },
+               },
+       },
+       {
+               name:   "I64RemU",
+               argLen: 2,
+               asm:    wasm.AI64RemU,
+               reg: regInfo{
+                       inputs: []inputInfo{
+                               {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
+                               {1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
+                       },
+                       outputs: []outputInfo{
+                               {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
+                       },
+               },
+       },
+       {
+               name:   "I64And",
+               argLen: 2,
+               asm:    wasm.AI64And,
+               reg: regInfo{
+                       inputs: []inputInfo{
+                               {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
+                               {1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
+                       },
+                       outputs: []outputInfo{
+                               {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
+                       },
+               },
+       },
+       {
+               name:   "I64Or",
+               argLen: 2,
+               asm:    wasm.AI64Or,
+               reg: regInfo{
+                       inputs: []inputInfo{
+                               {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
+                               {1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
+                       },
+                       outputs: []outputInfo{
+                               {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
+                       },
+               },
+       },
+       {
+               name:   "I64Xor",
+               argLen: 2,
+               asm:    wasm.AI64Xor,
+               reg: regInfo{
+                       inputs: []inputInfo{
+                               {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
+                               {1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
+                       },
+                       outputs: []outputInfo{
+                               {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
+                       },
+               },
+       },
+       {
+               name:   "I64Shl",
+               argLen: 2,
+               asm:    wasm.AI64Shl,
+               reg: regInfo{
+                       inputs: []inputInfo{
+                               {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
+                               {1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
+                       },
+                       outputs: []outputInfo{
+                               {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
+                       },
+               },
+       },
+       {
+               name:   "I64ShrS",
+               argLen: 2,
+               asm:    wasm.AI64ShrS,
+               reg: regInfo{
+                       inputs: []inputInfo{
+                               {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
+                               {1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
+                       },
+                       outputs: []outputInfo{
+                               {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
+                       },
+               },
+       },
+       {
+               name:   "I64ShrU",
+               argLen: 2,
+               asm:    wasm.AI64ShrU,
+               reg: regInfo{
+                       inputs: []inputInfo{
+                               {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
+                               {1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
+                       },
+                       outputs: []outputInfo{
+                               {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
+                       },
+               },
+       },
+       {
+               name:   "F32Neg",
+               argLen: 1,
+               asm:    wasm.AF32Neg,
+               reg: regInfo{
+                       inputs: []inputInfo{
+                               {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+                       },
+                       outputs: []outputInfo{
+                               {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+                       },
+               },
+       },
+       {
+               name:   "F32Add",
+               argLen: 2,
+               asm:    wasm.AF32Add,
+               reg: regInfo{
+                       inputs: []inputInfo{
+                               {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+                               {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+                       },
+                       outputs: []outputInfo{
+                               {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+                       },
+               },
+       },
+       {
+               name:   "F32Sub",
+               argLen: 2,
+               asm:    wasm.AF32Sub,
+               reg: regInfo{
+                       inputs: []inputInfo{
+                               {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+                               {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+                       },
+                       outputs: []outputInfo{
+                               {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+                       },
+               },
+       },
+       {
+               name:   "F32Mul",
+               argLen: 2,
+               asm:    wasm.AF32Mul,
+               reg: regInfo{
+                       inputs: []inputInfo{
+                               {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+                               {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+                       },
+                       outputs: []outputInfo{
+                               {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+                       },
+               },
+       },
+       {
+               name:   "F32Div",
+               argLen: 2,
+               asm:    wasm.AF32Div,
+               reg: regInfo{
+                       inputs: []inputInfo{
+                               {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+                               {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+                       },
+                       outputs: []outputInfo{
+                               {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+                       },
+               },
+       },
+       {
+               name:   "F64Neg",
+               argLen: 1,
+               asm:    wasm.AF64Neg,
+               reg: regInfo{
+                       inputs: []inputInfo{
+                               {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                       },
+                       outputs: []outputInfo{
+                               {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                       },
+               },
+       },
+       {
+               name:   "F64Add",
+               argLen: 2,
+               asm:    wasm.AF64Add,
+               reg: regInfo{
+                       inputs: []inputInfo{
+                               {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {1, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                       },
+                       outputs: []outputInfo{
+                               {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                       },
+               },
+       },
+       {
+               name:   "F64Sub",
+               argLen: 2,
+               asm:    wasm.AF64Sub,
+               reg: regInfo{
+                       inputs: []inputInfo{
+                               {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {1, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                       },
+                       outputs: []outputInfo{
+                               {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                       },
+               },
+       },
+       {
+               name:   "F64Mul",
+               argLen: 2,
+               asm:    wasm.AF64Mul,
+               reg: regInfo{
+                       inputs: []inputInfo{
+                               {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {1, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                       },
+                       outputs: []outputInfo{
+                               {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                       },
+               },
+       },
+       {
+               name:   "F64Div",
+               argLen: 2,
+               asm:    wasm.AF64Div,
+               reg: regInfo{
+                       inputs: []inputInfo{
+                               {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {1, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                       },
+                       outputs: []outputInfo{
+                               {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                       },
+               },
+       },
+       {
+               name:   "I64TruncSatF64S",
+               argLen: 1,
+               asm:    wasm.AI64TruncSatF64S,
+               reg: regInfo{
+                       inputs: []inputInfo{
+                               {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                       },
+                       outputs: []outputInfo{
+                               {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
+                       },
+               },
+       },
+       {
+               name:   "I64TruncSatF64U",
+               argLen: 1,
+               asm:    wasm.AI64TruncSatF64U,
+               reg: regInfo{
+                       inputs: []inputInfo{
+                               {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                       },
+                       outputs: []outputInfo{
+                               {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
+                       },
+               },
+       },
+       {
+               name:   "I64TruncSatF32S",
+               argLen: 1,
+               asm:    wasm.AI64TruncSatF32S,
+               reg: regInfo{
+                       inputs: []inputInfo{
+                               {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+                       },
+                       outputs: []outputInfo{
+                               {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
+                       },
+               },
+       },
+       {
+               name:   "I64TruncSatF32U",
+               argLen: 1,
+               asm:    wasm.AI64TruncSatF32U,
+               reg: regInfo{
+                       inputs: []inputInfo{
+                               {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+                       },
+                       outputs: []outputInfo{
+                               {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
+                       },
+               },
+       },
+       {
+               name:   "F32ConvertI64S",
+               argLen: 1,
+               asm:    wasm.AF32ConvertI64S,
+               reg: regInfo{
+                       inputs: []inputInfo{
+                               {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
+                       },
+                       outputs: []outputInfo{
+                               {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+                       },
+               },
+       },
+       {
+               name:   "F32ConvertI64U",
+               argLen: 1,
+               asm:    wasm.AF32ConvertI64U,
+               reg: regInfo{
+                       inputs: []inputInfo{
+                               {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
+                       },
+                       outputs: []outputInfo{
+                               {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+                       },
+               },
+       },
+       {
+               name:   "F64ConvertI64S",
+               argLen: 1,
+               asm:    wasm.AF64ConvertI64S,
+               reg: regInfo{
+                       inputs: []inputInfo{
+                               {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
+                       },
+                       outputs: []outputInfo{
+                               {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                       },
+               },
+       },
+       {
+               name:   "F64ConvertI64U",
+               argLen: 1,
+               asm:    wasm.AF64ConvertI64U,
+               reg: regInfo{
+                       inputs: []inputInfo{
+                               {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
+                       },
+                       outputs: []outputInfo{
+                               {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                       },
+               },
+       },
+       {
+               name:   "F32DemoteF64",
+               argLen: 1,
+               asm:    wasm.AF32DemoteF64,
+               reg: regInfo{
+                       inputs: []inputInfo{
+                               {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                       },
+                       outputs: []outputInfo{
+                               {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+                       },
+               },
+       },
+       {
+               name:   "F64PromoteF32",
+               argLen: 1,
+               asm:    wasm.AF64PromoteF32,
+               reg: regInfo{
+                       inputs: []inputInfo{
+                               {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+                       },
+                       outputs: []outputInfo{
+                               {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                       },
+               },
+       },
+       {
+               name:   "I64Extend8S",
+               argLen: 1,
+               asm:    wasm.AI64Extend8S,
+               reg: regInfo{
+                       inputs: []inputInfo{
+                               {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
+                       },
+                       outputs: []outputInfo{
+                               {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
+                       },
+               },
+       },
+       {
+               name:   "I64Extend16S",
+               argLen: 1,
+               asm:    wasm.AI64Extend16S,
+               reg: regInfo{
+                       inputs: []inputInfo{
+                               {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
+                       },
+                       outputs: []outputInfo{
+                               {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
+                       },
+               },
+       },
+       {
+               name:   "I64Extend32S",
+               argLen: 1,
+               asm:    wasm.AI64Extend32S,
+               reg: regInfo{
+                       inputs: []inputInfo{
+                               {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
+                       },
+                       outputs: []outputInfo{
+                               {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
+                       },
+               },
+       },
+       {
+               name:   "F32Sqrt",
+               argLen: 1,
+               asm:    wasm.AF32Sqrt,
+               reg: regInfo{
+                       inputs: []inputInfo{
+                               {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+                       },
+                       outputs: []outputInfo{
+                               {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+                       },
+               },
+       },
+       {
+               name:   "F32Trunc",
+               argLen: 1,
+               asm:    wasm.AF32Trunc,
+               reg: regInfo{
+                       inputs: []inputInfo{
+                               {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+                       },
+                       outputs: []outputInfo{
+                               {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+                       },
+               },
+       },
+       {
+               name:   "F32Ceil",
+               argLen: 1,
+               asm:    wasm.AF32Ceil,
+               reg: regInfo{
+                       inputs: []inputInfo{
+                               {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+                       },
+                       outputs: []outputInfo{
+                               {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+                       },
+               },
+       },
+       {
+               name:   "F32Floor",
+               argLen: 1,
+               asm:    wasm.AF32Floor,
+               reg: regInfo{
+                       inputs: []inputInfo{
+                               {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+                       },
+                       outputs: []outputInfo{
+                               {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+                       },
+               },
+       },
+       {
+               name:   "F32Nearest",
+               argLen: 1,
+               asm:    wasm.AF32Nearest,
+               reg: regInfo{
+                       inputs: []inputInfo{
+                               {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+                       },
+                       outputs: []outputInfo{
+                               {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+                       },
+               },
+       },
+       {
+               name:   "F32Abs",
+               argLen: 1,
+               asm:    wasm.AF32Abs,
+               reg: regInfo{
+                       inputs: []inputInfo{
+                               {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+                       },
+                       outputs: []outputInfo{
+                               {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+                       },
+               },
+       },
+       {
+               name:   "F32Copysign",
+               argLen: 2,
+               asm:    wasm.AF32Copysign,
+               reg: regInfo{
+                       inputs: []inputInfo{
+                               {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+                               {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+                       },
+                       outputs: []outputInfo{
+                               {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
+                       },
+               },
+       },
+       {
+               name:   "F64Sqrt",
+               argLen: 1,
+               asm:    wasm.AF64Sqrt,
+               reg: regInfo{
+                       inputs: []inputInfo{
+                               {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                       },
+                       outputs: []outputInfo{
+                               {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                       },
+               },
+       },
+       {
+               name:   "F64Trunc",
+               argLen: 1,
+               asm:    wasm.AF64Trunc,
+               reg: regInfo{
+                       inputs: []inputInfo{
+                               {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                       },
+                       outputs: []outputInfo{
+                               {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                       },
+               },
+       },
+       {
+               name:   "F64Ceil",
+               argLen: 1,
+               asm:    wasm.AF64Ceil,
+               reg: regInfo{
+                       inputs: []inputInfo{
+                               {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                       },
+                       outputs: []outputInfo{
+                               {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                       },
+               },
+       },
+       {
+               name:   "F64Floor",
+               argLen: 1,
+               asm:    wasm.AF64Floor,
+               reg: regInfo{
+                       inputs: []inputInfo{
+                               {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                       },
+                       outputs: []outputInfo{
+                               {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                       },
+               },
+       },
+       {
+               name:   "F64Nearest",
+               argLen: 1,
+               asm:    wasm.AF64Nearest,
+               reg: regInfo{
+                       inputs: []inputInfo{
+                               {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                       },
+                       outputs: []outputInfo{
+                               {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                       },
+               },
+       },
+       {
+               name:   "F64Abs",
+               argLen: 1,
+               asm:    wasm.AF64Abs,
+               reg: regInfo{
+                       inputs: []inputInfo{
+                               {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                       },
+                       outputs: []outputInfo{
+                               {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                       },
+               },
+       },
+       {
+               name:   "F64Copysign",
+               argLen: 2,
+               asm:    wasm.AF64Copysign,
+               reg: regInfo{
+                       inputs: []inputInfo{
+                               {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {1, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                       },
+                       outputs: []outputInfo{
+                               {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                       },
+               },
+       },
+       {
+               name:   "I64Ctz",
+               argLen: 1,
+               asm:    wasm.AI64Ctz,
+               reg: regInfo{
+                       inputs: []inputInfo{
+                               {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
+                       },
+                       outputs: []outputInfo{
+                               {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
+                       },
+               },
+       },
+       {
+               name:   "I64Clz",
+               argLen: 1,
+               asm:    wasm.AI64Clz,
+               reg: regInfo{
+                       inputs: []inputInfo{
+                               {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
+                       },
+                       outputs: []outputInfo{
+                               {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
+                       },
+               },
+       },
+       {
+               name:   "I32Rotl",
+               argLen: 2,
+               asm:    wasm.AI32Rotl,
+               reg: regInfo{
+                       inputs: []inputInfo{
+                               {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
+                               {1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
+                       },
+                       outputs: []outputInfo{
+                               {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
+                       },
+               },
+       },
+       {
+               name:   "I64Rotl",
+               argLen: 2,
+               asm:    wasm.AI64Rotl,
+               reg: regInfo{
+                       inputs: []inputInfo{
+                               {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
+                               {1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
+                       },
+                       outputs: []outputInfo{
+                               {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
+                       },
+               },
+       },
+       {
+               name:   "I64Popcnt",
+               argLen: 1,
+               asm:    wasm.AI64Popcnt,
+               reg: regInfo{
+                       inputs: []inputInfo{
+                               {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
+                       },
+                       outputs: []outputInfo{
+                               {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
+                       },
+               },
+       },
+
+       {
+               name:        "Add8",
+               argLen:      2,
+               commutative: true,
+               generic:     true,
+       },
+       {
+               name:        "Add16",
+               argLen:      2,
+               commutative: true,
+               generic:     true,
+       },
+       {
+               name:        "Add32",
+               argLen:      2,
+               commutative: true,
+               generic:     true,
+       },
+       {
+               name:        "Add64",
+               argLen:      2,
+               commutative: true,
+               generic:     true,
+       },
+       {
+               name:    "AddPtr",
+               argLen:  2,
+               generic: true,
+       },
+       {
+               name:        "Add32F",
+               argLen:      2,
+               commutative: true,
+               generic:     true,
+       },
+       {
+               name:        "Add64F",
+               argLen:      2,
+               commutative: true,
+               generic:     true,
+       },
+       {
+               name:    "Sub8",
+               argLen:  2,
+               generic: true,
+       },
+       {
+               name:    "Sub16",
+               argLen:  2,
+               generic: true,
+       },
+       {
+               name:    "Sub32",
+               argLen:  2,
+               generic: true,
+       },
+       {
+               name:    "Sub64",
+               argLen:  2,
+               generic: true,
+       },
+       {
+               name:    "SubPtr",
+               argLen:  2,
+               generic: true,
+       },
+       {
+               name:    "Sub32F",
+               argLen:  2,
+               generic: true,
+       },
+       {
+               name:    "Sub64F",
+               argLen:  2,
+               generic: true,
+       },
+       {
+               name:        "Mul8",
+               argLen:      2,
+               commutative: true,
+               generic:     true,
+       },
+       {
+               name:        "Mul16",
+               argLen:      2,
+               commutative: true,
+               generic:     true,
+       },
+       {
+               name:        "Mul32",
+               argLen:      2,
+               commutative: true,
+               generic:     true,
+       },
+       {
+               name:        "Mul64",
+               argLen:      2,
+               commutative: true,
+               generic:     true,
+       },
+       {
+               name:        "Mul32F",
+               argLen:      2,
+               commutative: true,
+               generic:     true,
+       },
+       {
+               name:        "Mul64F",
+               argLen:      2,
+               commutative: true,
+               generic:     true,
+       },
+       {
+               name:    "Div32F",
+               argLen:  2,
+               generic: true,
+       },
+       {
+               name:    "Div64F",
+               argLen:  2,
+               generic: true,
+       },
+       {
+               name:        "Hmul32",
+               argLen:      2,
+               commutative: true,
+               generic:     true,
+       },
+       {
+               name:        "Hmul32u",
+               argLen:      2,
+               commutative: true,
+               generic:     true,
+       },
+       {
+               name:        "Hmul64",
+               argLen:      2,
+               commutative: true,
+               generic:     true,
+       },
+       {
+               name:        "Hmul64u",
+               argLen:      2,
+               commutative: true,
+               generic:     true,
+       },
+       {
+               name:        "Mul32uhilo",
+               argLen:      2,
+               commutative: true,
+               generic:     true,
+       },
+       {
+               name:        "Mul64uhilo",
+               argLen:      2,
+               commutative: true,
+               generic:     true,
+       },
+       {
+               name:        "Mul32uover",
+               argLen:      2,
+               commutative: true,
+               generic:     true,
+       },
+       {
+               name:        "Mul64uover",
+               argLen:      2,
+               commutative: true,
+               generic:     true,
+       },
+       {
+               name:    "Avg32u",
+               argLen:  2,
+               generic: true,
+       },
+       {
+               name:    "Avg64u",
+               argLen:  2,
+               generic: true,
+       },
+       {
+               name:    "Div8",
+               argLen:  2,
+               generic: true,
+       },
+       {
+               name:    "Div8u",
+               argLen:  2,
+               generic: true,
+       },
+       {
+               name:    "Div16",
+               auxType: auxBool,
+               argLen:  2,
+               generic: true,
+       },
+       {
+               name:    "Div16u",
+               argLen:  2,
+               generic: true,
+       },
+       {
+               name:    "Div32",
+               auxType: auxBool,
+               argLen:  2,
+               generic: true,
+       },
+       {
+               name:    "Div32u",
+               argLen:  2,
+               generic: true,
+       },
+       {
+               name:    "Div64",
+               auxType: auxBool,
+               argLen:  2,
+               generic: true,
+       },
+       {
+               name:    "Div64u",
+               argLen:  2,
+               generic: true,
+       },
+       {
+               name:    "Div128u",
+               argLen:  3,
+               generic: true,
+       },
+       {
+               name:    "Mod8",
+               argLen:  2,
+               generic: true,
+       },
+       {
+               name:    "Mod8u",
+               argLen:  2,
+               generic: true,
+       },
+       {
+               name:    "Mod16",
+               auxType: auxBool,
+               argLen:  2,
+               generic: true,
+       },
+       {
+               name:    "Mod16u",
+               argLen:  2,
+               generic: true,
+       },
+       {
+               name:    "Mod32",
+               auxType: auxBool,
+               argLen:  2,
+               generic: true,
+       },
+       {
+               name:    "Mod32u",
+               argLen:  2,
+               generic: true,
+       },
+       {
+               name:    "Mod64",
+               auxType: auxBool,
+               argLen:  2,
+               generic: true,
+       },
+       {
+               name:    "Mod64u",
+               argLen:  2,
+               generic: true,
+       },
+       {
+               name:        "And8",
+               argLen:      2,
+               commutative: true,
+               generic:     true,
+       },
+       {
+               name:        "And16",
+               argLen:      2,
+               commutative: true,
+               generic:     true,
+       },
+       {
+               name:        "And32",
+               argLen:      2,
+               commutative: true,
+               generic:     true,
+       },
+       {
+               name:        "And64",
+               argLen:      2,
+               commutative: true,
+               generic:     true,
+       },
+       {
+               name:        "Or8",
+               argLen:      2,
+               commutative: true,
+               generic:     true,
+       },
+       {
+               name:        "Or16",
+               argLen:      2,
+               commutative: true,
+               generic:     true,
+       },
+       {
+               name:        "Or32",
+               argLen:      2,
+               commutative: true,
+               generic:     true,
+       },
+       {
+               name:        "Or64",
+               argLen:      2,
+               commutative: true,
+               generic:     true,
+       },
+       {
+               name:        "Xor8",
+               argLen:      2,
+               commutative: true,
+               generic:     true,
+       },
+       {
+               name:        "Xor16",
+               argLen:      2,
+               commutative: true,
+               generic:     true,
+       },
+       {
+               name:        "Xor32",
+               argLen:      2,
+               commutative: true,
+               generic:     true,
+       },
+       {
+               name:        "Xor64",
+               argLen:      2,
+               commutative: true,
+               generic:     true,
+       },
+       {
+               name:    "Lsh8x8",
+               auxType: auxBool,
+               argLen:  2,
+               generic: true,
+       },
+       {
+               name:    "Lsh8x16",
+               auxType: auxBool,
+               argLen:  2,
+               generic: true,
+       },
+       {
+               name:    "Lsh8x32",
+               auxType: auxBool,
+               argLen:  2,
+               generic: true,
+       },
+       {
+               name:    "Lsh8x64",
+               auxType: auxBool,
+               argLen:  2,
+               generic: true,
+       },
+       {
+               name:    "Lsh16x8",
+               auxType: auxBool,
+               argLen:  2,
+               generic: true,
+       },
+       {
+               name:    "Lsh16x16",
+               auxType: auxBool,
+               argLen:  2,
+               generic: true,
+       },
+       {
+               name:    "Lsh16x32",
+               auxType: auxBool,
+               argLen:  2,
+               generic: true,
+       },
+       {
+               name:    "Lsh16x64",
+               auxType: auxBool,
+               argLen:  2,
+               generic: true,
+       },
+       {
+               name:    "Lsh32x8",
+               auxType: auxBool,
+               argLen:  2,
+               generic: true,
+       },
+       {
+               name:    "Lsh32x16",
+               auxType: auxBool,
+               argLen:  2,
+               generic: true,
+       },
+       {
+               name:    "Lsh32x32",
+               auxType: auxBool,
+               argLen:  2,
+               generic: true,
+       },
+       {
+               name:    "Lsh32x64",
+               auxType: auxBool,
+               argLen:  2,
+               generic: true,
+       },
+       {
+               name:    "Lsh64x8",
+               auxType: auxBool,
+               argLen:  2,
+               generic: true,
+       },
+       {
+               name:    "Lsh64x16",
+               auxType: auxBool,
+               argLen:  2,
+               generic: true,
+       },
+       {
+               name:    "Lsh64x32",
+               auxType: auxBool,
+               argLen:  2,
+               generic: true,
+       },
+       {
+               name:    "Lsh64x64",
+               auxType: auxBool,
+               argLen:  2,
+               generic: true,
+       },
+       {
+               name:    "Rsh8x8",
+               auxType: auxBool,
+               argLen:  2,
+               generic: true,
+       },
+       {
+               name:    "Rsh8x16",
+               auxType: auxBool,
+               argLen:  2,
+               generic: true,
+       },
+       {
+               name:    "Rsh8x32",
+               auxType: auxBool,
+               argLen:  2,
+               generic: true,
+       },
+       {
+               name:    "Rsh8x64",
+               auxType: auxBool,
+               argLen:  2,
+               generic: true,
+       },
+       {
+               name:    "Rsh16x8",
+               auxType: auxBool,
+               argLen:  2,
+               generic: true,
+       },
+       {
+               name:    "Rsh16x16",
+               auxType: auxBool,
+               argLen:  2,
+               generic: true,
+       },
+       {
+               name:    "Rsh16x32",
+               auxType: auxBool,
+               argLen:  2,
+               generic: true,
+       },
+       {
+               name:    "Rsh16x64",
+               auxType: auxBool,
+               argLen:  2,
+               generic: true,
+       },
+       {
+               name:    "Rsh32x8",
+               auxType: auxBool,
+               argLen:  2,
+               generic: true,
+       },
+       {
+               name:    "Rsh32x16",
+               auxType: auxBool,
+               argLen:  2,
+               generic: true,
+       },
+       {
+               name:    "Rsh32x32",
+               auxType: auxBool,
+               argLen:  2,
+               generic: true,
+       },
+       {
+               name:    "Rsh32x64",
+               auxType: auxBool,
+               argLen:  2,
+               generic: true,
+       },
+       {
+               name:    "Rsh64x8",
+               auxType: auxBool,
+               argLen:  2,
+               generic: true,
+       },
+       {
+               name:    "Rsh64x16",
+               auxType: auxBool,
+               argLen:  2,
+               generic: true,
+       },
+       {
+               name:    "Rsh64x32",
+               auxType: auxBool,
+               argLen:  2,
+               generic: true,
+       },
+       {
+               name:    "Rsh64x64",
+               auxType: auxBool,
+               argLen:  2,
+               generic: true,
+       },
+       {
+               name:    "Rsh8Ux8",
+               auxType: auxBool,
+               argLen:  2,
+               generic: true,
+       },
+       {
+               name:    "Rsh8Ux16",
+               auxType: auxBool,
+               argLen:  2,
+               generic: true,
+       },
+       {
+               name:    "Rsh8Ux32",
+               auxType: auxBool,
+               argLen:  2,
+               generic: true,
+       },
+       {
+               name:    "Rsh8Ux64",
+               auxType: auxBool,
+               argLen:  2,
+               generic: true,
+       },
+       {
+               name:    "Rsh16Ux8",
+               auxType: auxBool,
+               argLen:  2,
+               generic: true,
+       },
+       {
+               name:    "Rsh16Ux16",
+               auxType: auxBool,
+               argLen:  2,
+               generic: true,
+       },
+       {
+               name:    "Rsh16Ux32",
+               auxType: auxBool,
+               argLen:  2,
+               generic: true,
+       },
+       {
+               name:    "Rsh16Ux64",
+               auxType: auxBool,
+               argLen:  2,
+               generic: true,
+       },
+       {
+               name:    "Rsh32Ux8",
+               auxType: auxBool,
+               argLen:  2,
+               generic: true,
+       },
+       {
+               name:    "Rsh32Ux16",
+               auxType: auxBool,
+               argLen:  2,
+               generic: true,
+       },
+       {
+               name:    "Rsh32Ux32",
+               auxType: auxBool,
+               argLen:  2,
+               generic: true,
+       },
+       {
+               name:    "Rsh32Ux64",
+               auxType: auxBool,
+               argLen:  2,
+               generic: true,
+       },
+       {
+               name:    "Rsh64Ux8",
+               auxType: auxBool,
+               argLen:  2,
+               generic: true,
+       },
+       {
+               name:    "Rsh64Ux16",
+               auxType: auxBool,
+               argLen:  2,
+               generic: true,
+       },
+       {
+               name:    "Rsh64Ux32",
+               auxType: auxBool,
+               argLen:  2,
+               generic: true,
+       },
+       {
+               name:    "Rsh64Ux64",
+               auxType: auxBool,
+               argLen:  2,
+               generic: true,
+       },
+       {
+               name:        "Eq8",
+               argLen:      2,
+               commutative: true,
+               generic:     true,
+       },
+       {
+               name:        "Eq16",
+               argLen:      2,
+               commutative: true,
+               generic:     true,
+       },
+       {
+               name:        "Eq32",
+               argLen:      2,
+               commutative: true,
+               generic:     true,
+       },
+       {
+               name:        "Eq64",
+               argLen:      2,
+               commutative: true,
+               generic:     true,
+       },
+       {
+               name:        "EqPtr",
+               argLen:      2,
+               commutative: true,
+               generic:     true,
+       },
+       {
+               name:    "EqInter",
+               argLen:  2,
+               generic: true,
+       },
+       {
+               name:    "EqSlice",
+               argLen:  2,
+               generic: true,
+       },
+       {
+               name:        "Eq32F",
+               argLen:      2,
+               commutative: true,
+               generic:     true,
+       },
+       {
+               name:        "Eq64F",
+               argLen:      2,
+               commutative: true,
+               generic:     true,
+       },
+       {
+               name:        "Neq8",
+               argLen:      2,
+               commutative: true,
+               generic:     true,
+       },
+       {
+               name:        "Neq16",
+               argLen:      2,
+               commutative: true,
+               generic:     true,
+       },
+       {
+               name:        "Neq32",
+               argLen:      2,
+               commutative: true,
+               generic:     true,
+       },
+       {
+               name:        "Neq64",
+               argLen:      2,
+               commutative: true,
+               generic:     true,
+       },
+       {
+               name:        "NeqPtr",
+               argLen:      2,
+               commutative: true,
+               generic:     true,
+       },
+       {
+               name:    "NeqInter",
+               argLen:  2,
+               generic: true,
+       },
+       {
+               name:    "NeqSlice",
+               argLen:  2,
+               generic: true,
+       },
+       {
+               name:        "Neq32F",
+               argLen:      2,
+               commutative: true,
+               generic:     true,
+       },
+       {
+               name:        "Neq64F",
+               argLen:      2,
+               commutative: true,
+               generic:     true,
+       },
+       {
+               name:    "Less8",
+               argLen:  2,
                generic: true,
        },
        {
-               name:    "Sub64",
+               name:    "Less8U",
                argLen:  2,
                generic: true,
        },
        {
-               name:    "SubPtr",
+               name:    "Less16",
                argLen:  2,
                generic: true,
        },
        {
-               name:    "Sub32F",
+               name:    "Less16U",
                argLen:  2,
                generic: true,
        },
        {
-               name:    "Sub64F",
+               name:    "Less32",
                argLen:  2,
                generic: true,
        },
        {
-               name:        "Mul8",
-               argLen:      2,
-               commutative: true,
-               generic:     true,
+               name:    "Less32U",
+               argLen:  2,
+               generic: true,
        },
        {
-               name:        "Mul16",
-               argLen:      2,
-               commutative: true,
-               generic:     true,
+               name:    "Less64",
+               argLen:  2,
+               generic: true,
        },
        {
-               name:        "Mul32",
-               argLen:      2,
-               commutative: true,
-               generic:     true,
+               name:    "Less64U",
+               argLen:  2,
+               generic: true,
        },
        {
-               name:        "Mul64",
-               argLen:      2,
-               commutative: true,
-               generic:     true,
+               name:    "Less32F",
+               argLen:  2,
+               generic: true,
        },
        {
-               name:        "Mul32F",
-               argLen:      2,
-               commutative: true,
-               generic:     true,
+               name:    "Less64F",
+               argLen:  2,
+               generic: true,
        },
        {
-               name:        "Mul64F",
-               argLen:      2,
-               commutative: true,
-               generic:     true,
+               name:    "Leq8",
+               argLen:  2,
+               generic: true,
        },
        {
-               name:    "Div32F",
+               name:    "Leq8U",
                argLen:  2,
                generic: true,
        },
        {
-               name:    "Div64F",
+               name:    "Leq16",
                argLen:  2,
                generic: true,
        },
        {
-               name:        "Hmul32",
-               argLen:      2,
-               commutative: true,
-               generic:     true,
+               name:    "Leq16U",
+               argLen:  2,
+               generic: true,
        },
        {
-               name:        "Hmul32u",
+               name:    "Leq32",
+               argLen:  2,
+               generic: true,
+       },
+       {
+               name:    "Leq32U",
+               argLen:  2,
+               generic: true,
+       },
+       {
+               name:    "Leq64",
+               argLen:  2,
+               generic: true,
+       },
+       {
+               name:    "Leq64U",
+               argLen:  2,
+               generic: true,
+       },
+       {
+               name:    "Leq32F",
+               argLen:  2,
+               generic: true,
+       },
+       {
+               name:    "Leq64F",
+               argLen:  2,
+               generic: true,
+       },
+       {
+               name:    "CondSelect",
+               argLen:  3,
+               generic: true,
+       },
+       {
+               name:        "AndB",
                argLen:      2,
                commutative: true,
                generic:     true,
        },
        {
-               name:        "Hmul64",
+               name:        "OrB",
                argLen:      2,
                commutative: true,
                generic:     true,
        },
        {
-               name:        "Hmul64u",
+               name:        "EqB",
                argLen:      2,
                commutative: true,
                generic:     true,
        },
        {
-               name:        "Mul32uhilo",
+               name:        "NeqB",
                argLen:      2,
                commutative: true,
                generic:     true,
        },
        {
-               name:        "Mul64uhilo",
-               argLen:      2,
-               commutative: true,
-               generic:     true,
+               name:    "Not",
+               argLen:  1,
+               generic: true,
+       },
+       {
+               name:    "Neg8",
+               argLen:  1,
+               generic: true,
+       },
+       {
+               name:    "Neg16",
+               argLen:  1,
+               generic: true,
+       },
+       {
+               name:    "Neg32",
+               argLen:  1,
+               generic: true,
+       },
+       {
+               name:    "Neg64",
+               argLen:  1,
+               generic: true,
+       },
+       {
+               name:    "Neg32F",
+               argLen:  1,
+               generic: true,
+       },
+       {
+               name:    "Neg64F",
+               argLen:  1,
+               generic: true,
+       },
+       {
+               name:    "Com8",
+               argLen:  1,
+               generic: true,
+       },
+       {
+               name:    "Com16",
+               argLen:  1,
+               generic: true,
+       },
+       {
+               name:    "Com32",
+               argLen:  1,
+               generic: true,
+       },
+       {
+               name:    "Com64",
+               argLen:  1,
+               generic: true,
+       },
+       {
+               name:    "Ctz8",
+               argLen:  1,
+               generic: true,
+       },
+       {
+               name:    "Ctz16",
+               argLen:  1,
+               generic: true,
+       },
+       {
+               name:    "Ctz32",
+               argLen:  1,
+               generic: true,
+       },
+       {
+               name:    "Ctz64",
+               argLen:  1,
+               generic: true,
+       },
+       {
+               name:    "Ctz64On32",
+               argLen:  2,
+               generic: true,
+       },
+       {
+               name:    "Ctz8NonZero",
+               argLen:  1,
+               generic: true,
+       },
+       {
+               name:    "Ctz16NonZero",
+               argLen:  1,
+               generic: true,
+       },
+       {
+               name:    "Ctz32NonZero",
+               argLen:  1,
+               generic: true,
+       },
+       {
+               name:    "Ctz64NonZero",
+               argLen:  1,
+               generic: true,
+       },
+       {
+               name:    "BitLen8",
+               argLen:  1,
+               generic: true,
+       },
+       {
+               name:    "BitLen16",
+               argLen:  1,
+               generic: true,
+       },
+       {
+               name:    "BitLen32",
+               argLen:  1,
+               generic: true,
+       },
+       {
+               name:    "BitLen64",
+               argLen:  1,
+               generic: true,
+       },
+       {
+               name:    "Bswap16",
+               argLen:  1,
+               generic: true,
+       },
+       {
+               name:    "Bswap32",
+               argLen:  1,
+               generic: true,
+       },
+       {
+               name:    "Bswap64",
+               argLen:  1,
+               generic: true,
+       },
+       {
+               name:    "BitRev8",
+               argLen:  1,
+               generic: true,
+       },
+       {
+               name:    "BitRev16",
+               argLen:  1,
+               generic: true,
+       },
+       {
+               name:    "BitRev32",
+               argLen:  1,
+               generic: true,
+       },
+       {
+               name:    "BitRev64",
+               argLen:  1,
+               generic: true,
+       },
+       {
+               name:    "PopCount8",
+               argLen:  1,
+               generic: true,
+       },
+       {
+               name:    "PopCount16",
+               argLen:  1,
+               generic: true,
+       },
+       {
+               name:    "PopCount32",
+               argLen:  1,
+               generic: true,
+       },
+       {
+               name:    "PopCount64",
+               argLen:  1,
+               generic: true,
+       },
+       {
+               name:    "RotateLeft64",
+               argLen:  2,
+               generic: true,
+       },
+       {
+               name:    "RotateLeft32",
+               argLen:  2,
+               generic: true,
+       },
+       {
+               name:    "RotateLeft16",
+               argLen:  2,
+               generic: true,
+       },
+       {
+               name:    "RotateLeft8",
+               argLen:  2,
+               generic: true,
+       },
+       {
+               name:    "Sqrt",
+               argLen:  1,
+               generic: true,
+       },
+       {
+               name:    "Sqrt32",
+               argLen:  1,
+               generic: true,
+       },
+       {
+               name:    "Floor",
+               argLen:  1,
+               generic: true,
+       },
+       {
+               name:    "Ceil",
+               argLen:  1,
+               generic: true,
+       },
+       {
+               name:    "Trunc",
+               argLen:  1,
+               generic: true,
+       },
+       {
+               name:    "Round",
+               argLen:  1,
+               generic: true,
+       },
+       {
+               name:    "RoundToEven",
+               argLen:  1,
+               generic: true,
+       },
+       {
+               name:    "Abs",
+               argLen:  1,
+               generic: true,
+       },
+       {
+               name:    "Copysign",
+               argLen:  2,
+               generic: true,
+       },
+       {
+               name:    "Min64",
+               argLen:  2,
+               generic: true,
+       },
+       {
+               name:    "Max64",
+               argLen:  2,
+               generic: true,
+       },
+       {
+               name:    "Min64u",
+               argLen:  2,
+               generic: true,
+       },
+       {
+               name:    "Max64u",
+               argLen:  2,
+               generic: true,
+       },
+       {
+               name:    "Min64F",
+               argLen:  2,
+               generic: true,
+       },
+       {
+               name:    "Min32F",
+               argLen:  2,
+               generic: true,
+       },
+       {
+               name:    "Max64F",
+               argLen:  2,
+               generic: true,
+       },
+       {
+               name:    "Max32F",
+               argLen:  2,
+               generic: true,
+       },
+       {
+               name:    "FMA",
+               argLen:  3,
+               generic: true,
+       },
+       {
+               name:      "Phi",
+               argLen:    -1,
+               zeroWidth: true,
+               generic:   true,
+       },
+       {
+               name:    "Copy",
+               argLen:  1,
+               generic: true,
+       },
+       {
+               name:         "Convert",
+               argLen:       2,
+               resultInArg0: true,
+               zeroWidth:    true,
+               generic:      true,
+       },
+       {
+               name:    "ConstBool",
+               auxType: auxBool,
+               argLen:  0,
+               generic: true,
+       },
+       {
+               name:    "ConstString",
+               auxType: auxString,
+               argLen:  0,
+               generic: true,
+       },
+       {
+               name:    "ConstNil",
+               argLen:  0,
+               generic: true,
+       },
+       {
+               name:    "Const8",
+               auxType: auxInt8,
+               argLen:  0,
+               generic: true,
+       },
+       {
+               name:    "Const16",
+               auxType: auxInt16,
+               argLen:  0,
+               generic: true,
+       },
+       {
+               name:    "Const32",
+               auxType: auxInt32,
+               argLen:  0,
+               generic: true,
+       },
+       {
+               name:    "Const64",
+               auxType: auxInt64,
+               argLen:  0,
+               generic: true,
+       },
+       {
+               name:    "Const32F",
+               auxType: auxFloat32,
+               argLen:  0,
+               generic: true,
+       },
+       {
+               name:    "Const64F",
+               auxType: auxFloat64,
+               argLen:  0,
+               generic: true,
+       },
+       {
+               name:    "ConstInterface",
+               argLen:  0,
+               generic: true,
+       },
+       {
+               name:    "ConstSlice",
+               argLen:  0,
+               generic: true,
+       },
+       {
+               name:      "InitMem",
+               argLen:    0,
+               zeroWidth: true,
+               generic:   true,
+       },
+       {
+               name:      "Arg",
+               auxType:   auxSymOff,
+               argLen:    0,
+               zeroWidth: true,
+               symEffect: SymRead,
+               generic:   true,
+       },
+       {
+               name:      "ArgIntReg",
+               auxType:   auxNameOffsetInt8,
+               argLen:    0,
+               zeroWidth: true,
+               generic:   true,
+       },
+       {
+               name:      "ArgFloatReg",
+               auxType:   auxNameOffsetInt8,
+               argLen:    0,
+               zeroWidth: true,
+               generic:   true,
+       },
+       {
+               name:      "Addr",
+               auxType:   auxSym,
+               argLen:    1,
+               symEffect: SymAddr,
+               generic:   true,
+       },
+       {
+               name:      "LocalAddr",
+               auxType:   auxSym,
+               argLen:    2,
+               symEffect: SymAddr,
+               generic:   true,
        },
        {
-               name:        "Mul32uover",
-               argLen:      2,
-               commutative: true,
-               generic:     true,
+               name:      "SP",
+               argLen:    0,
+               zeroWidth: true,
+               fixedReg:  true,
+               generic:   true,
        },
        {
-               name:        "Mul64uover",
-               argLen:      2,
-               commutative: true,
-               generic:     true,
+               name:      "SB",
+               argLen:    0,
+               zeroWidth: true,
+               fixedReg:  true,
+               generic:   true,
        },
        {
-               name:    "Avg32u",
+               name:      "SPanchored",
+               argLen:    2,
+               zeroWidth: true,
+               generic:   true,
+       },
+       {
+               name:    "Load",
                argLen:  2,
                generic: true,
        },
        {
-               name:    "Avg64u",
+               name:    "Dereference",
                argLen:  2,
                generic: true,
        },
        {
-               name:    "Div8",
-               argLen:  2,
+               name:    "Store",
+               auxType: auxTyp,
+               argLen:  3,
                generic: true,
        },
        {
-               name:    "Div8u",
-               argLen:  2,
+               name:    "Move",
+               auxType: auxTypSize,
+               argLen:  3,
                generic: true,
        },
        {
-               name:    "Div16",
-               auxType: auxBool,
+               name:    "Zero",
+               auxType: auxTypSize,
                argLen:  2,
                generic: true,
        },
        {
-               name:    "Div16u",
-               argLen:  2,
+               name:    "StoreWB",
+               auxType: auxTyp,
+               argLen:  3,
                generic: true,
        },
        {
-               name:    "Div32",
-               auxType: auxBool,
-               argLen:  2,
+               name:    "MoveWB",
+               auxType: auxTypSize,
+               argLen:  3,
                generic: true,
        },
        {
-               name:    "Div32u",
+               name:    "ZeroWB",
+               auxType: auxTypSize,
                argLen:  2,
                generic: true,
        },
        {
-               name:    "Div64",
-               auxType: auxBool,
-               argLen:  2,
+               name:    "WBend",
+               argLen:  1,
                generic: true,
        },
        {
-               name:    "Div64u",
-               argLen:  2,
+               name:    "WB",
+               auxType: auxInt64,
+               argLen:  1,
                generic: true,
        },
        {
-               name:    "Div128u",
+               name:      "HasCPUFeature",
+               auxType:   auxSym,
+               argLen:    0,
+               symEffect: SymNone,
+               generic:   true,
+       },
+       {
+               name:    "PanicBounds",
+               auxType: auxInt64,
                argLen:  3,
+               call:    true,
                generic: true,
        },
        {
-               name:    "Mod8",
-               argLen:  2,
+               name:    "PanicExtend",
+               auxType: auxInt64,
+               argLen:  4,
+               call:    true,
                generic: true,
        },
        {
-               name:    "Mod8u",
-               argLen:  2,
+               name:    "ClosureCall",
+               auxType: auxCallOff,
+               argLen:  -1,
+               call:    true,
                generic: true,
        },
        {
-               name:    "Mod16",
-               auxType: auxBool,
-               argLen:  2,
+               name:    "StaticCall",
+               auxType: auxCallOff,
+               argLen:  -1,
+               call:    true,
                generic: true,
        },
        {
-               name:    "Mod16u",
-               argLen:  2,
+               name:    "InterCall",
+               auxType: auxCallOff,
+               argLen:  -1,
+               call:    true,
                generic: true,
        },
        {
-               name:    "Mod32",
-               auxType: auxBool,
-               argLen:  2,
+               name:    "TailCall",
+               auxType: auxCallOff,
+               argLen:  -1,
+               call:    true,
                generic: true,
        },
        {
-               name:    "Mod32u",
-               argLen:  2,
+               name:    "ClosureLECall",
+               auxType: auxCallOff,
+               argLen:  -1,
+               call:    true,
                generic: true,
        },
        {
-               name:    "Mod64",
-               auxType: auxBool,
-               argLen:  2,
+               name:    "StaticLECall",
+               auxType: auxCallOff,
+               argLen:  -1,
+               call:    true,
                generic: true,
        },
        {
-               name:    "Mod64u",
-               argLen:  2,
+               name:    "InterLECall",
+               auxType: auxCallOff,
+               argLen:  -1,
+               call:    true,
                generic: true,
        },
        {
-               name:        "And8",
-               argLen:      2,
-               commutative: true,
-               generic:     true,
+               name:    "TailLECall",
+               auxType: auxCallOff,
+               argLen:  -1,
+               call:    true,
+               generic: true,
        },
        {
-               name:        "And16",
-               argLen:      2,
-               commutative: true,
-               generic:     true,
+               name:    "SignExt8to16",
+               argLen:  1,
+               generic: true,
        },
        {
-               name:        "And32",
-               argLen:      2,
-               commutative: true,
-               generic:     true,
+               name:    "SignExt8to32",
+               argLen:  1,
+               generic: true,
        },
        {
-               name:        "And64",
-               argLen:      2,
-               commutative: true,
-               generic:     true,
+               name:    "SignExt8to64",
+               argLen:  1,
+               generic: true,
        },
        {
-               name:        "Or8",
-               argLen:      2,
-               commutative: true,
-               generic:     true,
+               name:    "SignExt16to32",
+               argLen:  1,
+               generic: true,
        },
        {
-               name:        "Or16",
-               argLen:      2,
-               commutative: true,
-               generic:     true,
+               name:    "SignExt16to64",
+               argLen:  1,
+               generic: true,
        },
        {
-               name:        "Or32",
-               argLen:      2,
-               commutative: true,
-               generic:     true,
+               name:    "SignExt32to64",
+               argLen:  1,
+               generic: true,
        },
        {
-               name:        "Or64",
-               argLen:      2,
-               commutative: true,
-               generic:     true,
+               name:    "ZeroExt8to16",
+               argLen:  1,
+               generic: true,
        },
        {
-               name:        "Xor8",
-               argLen:      2,
-               commutative: true,
-               generic:     true,
+               name:    "ZeroExt8to32",
+               argLen:  1,
+               generic: true,
        },
        {
-               name:        "Xor16",
-               argLen:      2,
-               commutative: true,
-               generic:     true,
+               name:    "ZeroExt8to64",
+               argLen:  1,
+               generic: true,
        },
        {
-               name:        "Xor32",
-               argLen:      2,
-               commutative: true,
-               generic:     true,
+               name:    "ZeroExt16to32",
+               argLen:  1,
+               generic: true,
        },
        {
-               name:        "Xor64",
-               argLen:      2,
-               commutative: true,
-               generic:     true,
+               name:    "ZeroExt16to64",
+               argLen:  1,
+               generic: true,
        },
        {
-               name:    "Lsh8x8",
-               auxType: auxBool,
-               argLen:  2,
+               name:    "ZeroExt32to64",
+               argLen:  1,
                generic: true,
        },
        {
-               name:    "Lsh8x16",
-               auxType: auxBool,
-               argLen:  2,
+               name:    "Trunc16to8",
+               argLen:  1,
                generic: true,
        },
        {
-               name:    "Lsh8x32",
-               auxType: auxBool,
-               argLen:  2,
+               name:    "Trunc32to8",
+               argLen:  1,
                generic: true,
        },
        {
-               name:    "Lsh8x64",
-               auxType: auxBool,
-               argLen:  2,
+               name:    "Trunc32to16",
+               argLen:  1,
                generic: true,
        },
        {
-               name:    "Lsh16x8",
-               auxType: auxBool,
-               argLen:  2,
+               name:    "Trunc64to8",
+               argLen:  1,
                generic: true,
        },
        {
-               name:    "Lsh16x16",
-               auxType: auxBool,
-               argLen:  2,
+               name:    "Trunc64to16",
+               argLen:  1,
                generic: true,
        },
        {
-               name:    "Lsh16x32",
-               auxType: auxBool,
-               argLen:  2,
+               name:    "Trunc64to32",
+               argLen:  1,
                generic: true,
        },
        {
-               name:    "Lsh16x64",
-               auxType: auxBool,
-               argLen:  2,
+               name:    "Cvt32to32F",
+               argLen:  1,
                generic: true,
        },
        {
-               name:    "Lsh32x8",
-               auxType: auxBool,
-               argLen:  2,
+               name:    "Cvt32to64F",
+               argLen:  1,
                generic: true,
        },
        {
-               name:    "Lsh32x16",
-               auxType: auxBool,
-               argLen:  2,
+               name:    "Cvt64to32F",
+               argLen:  1,
                generic: true,
        },
        {
-               name:    "Lsh32x32",
-               auxType: auxBool,
-               argLen:  2,
+               name:    "Cvt64to64F",
+               argLen:  1,
                generic: true,
        },
        {
-               name:    "Lsh32x64",
-               auxType: auxBool,
-               argLen:  2,
+               name:    "Cvt32Fto32",
+               argLen:  1,
                generic: true,
        },
        {
-               name:    "Lsh64x8",
-               auxType: auxBool,
-               argLen:  2,
+               name:    "Cvt32Fto64",
+               argLen:  1,
                generic: true,
        },
        {
-               name:    "Lsh64x16",
-               auxType: auxBool,
-               argLen:  2,
+               name:    "Cvt64Fto32",
+               argLen:  1,
                generic: true,
        },
        {
-               name:    "Lsh64x32",
-               auxType: auxBool,
-               argLen:  2,
+               name:    "Cvt64Fto64",
+               argLen:  1,
                generic: true,
        },
        {
-               name:    "Lsh64x64",
-               auxType: auxBool,
-               argLen:  2,
+               name:    "Cvt32Fto64F",
+               argLen:  1,
                generic: true,
        },
        {
-               name:    "Rsh8x8",
-               auxType: auxBool,
-               argLen:  2,
+               name:    "Cvt64Fto32F",
+               argLen:  1,
                generic: true,
        },
        {
-               name:    "Rsh8x16",
-               auxType: auxBool,
-               argLen:  2,
+               name:    "CvtBoolToUint8",
+               argLen:  1,
                generic: true,
        },
        {
-               name:    "Rsh8x32",
-               auxType: auxBool,
-               argLen:  2,
+               name:    "Round32F",
+               argLen:  1,
                generic: true,
        },
        {
-               name:    "Rsh8x64",
-               auxType: auxBool,
-               argLen:  2,
+               name:    "Round64F",
+               argLen:  1,
                generic: true,
        },
        {
-               name:    "Rsh16x8",
-               auxType: auxBool,
-               argLen:  2,
+               name:    "IsNonNil",
+               argLen:  1,
                generic: true,
        },
        {
-               name:    "Rsh16x16",
-               auxType: auxBool,
+               name:    "IsInBounds",
                argLen:  2,
                generic: true,
        },
        {
-               name:    "Rsh16x32",
-               auxType: auxBool,
+               name:    "IsSliceInBounds",
                argLen:  2,
                generic: true,
        },
        {
-               name:    "Rsh16x64",
-               auxType: auxBool,
-               argLen:  2,
+               name:     "NilCheck",
+               argLen:   2,
+               nilCheck: true,
+               generic:  true,
+       },
+       {
+               name:      "GetG",
+               argLen:    1,
+               zeroWidth: true,
+               generic:   true,
+       },
+       {
+               name:    "GetClosurePtr",
+               argLen:  0,
                generic: true,
        },
        {
-               name:    "Rsh32x8",
-               auxType: auxBool,
-               argLen:  2,
+               name:    "GetCallerPC",
+               argLen:  0,
                generic: true,
        },
        {
-               name:    "Rsh32x16",
-               auxType: auxBool,
-               argLen:  2,
+               name:    "GetCallerSP",
+               argLen:  1,
                generic: true,
        },
        {
-               name:    "Rsh32x32",
-               auxType: auxBool,
+               name:    "PtrIndex",
                argLen:  2,
                generic: true,
        },
        {
-               name:    "Rsh32x64",
-               auxType: auxBool,
-               argLen:  2,
+               name:    "OffPtr",
+               auxType: auxInt64,
+               argLen:  1,
                generic: true,
        },
        {
-               name:    "Rsh64x8",
-               auxType: auxBool,
-               argLen:  2,
+               name:    "SliceMake",
+               argLen:  3,
                generic: true,
        },
        {
-               name:    "Rsh64x16",
-               auxType: auxBool,
-               argLen:  2,
+               name:    "SlicePtr",
+               argLen:  1,
                generic: true,
        },
        {
-               name:    "Rsh64x32",
-               auxType: auxBool,
-               argLen:  2,
+               name:    "SliceLen",
+               argLen:  1,
                generic: true,
        },
        {
-               name:    "Rsh64x64",
-               auxType: auxBool,
-               argLen:  2,
+               name:    "SliceCap",
+               argLen:  1,
                generic: true,
        },
        {
-               name:    "Rsh8Ux8",
-               auxType: auxBool,
-               argLen:  2,
+               name:    "SlicePtrUnchecked",
+               argLen:  1,
                generic: true,
        },
        {
-               name:    "Rsh8Ux16",
-               auxType: auxBool,
+               name:    "ComplexMake",
                argLen:  2,
                generic: true,
        },
        {
-               name:    "Rsh8Ux32",
-               auxType: auxBool,
-               argLen:  2,
+               name:    "ComplexReal",
+               argLen:  1,
                generic: true,
        },
        {
-               name:    "Rsh8Ux64",
-               auxType: auxBool,
-               argLen:  2,
+               name:    "ComplexImag",
+               argLen:  1,
                generic: true,
        },
        {
-               name:    "Rsh16Ux8",
-               auxType: auxBool,
+               name:    "StringMake",
                argLen:  2,
                generic: true,
        },
        {
-               name:    "Rsh16Ux16",
-               auxType: auxBool,
-               argLen:  2,
+               name:    "StringPtr",
+               argLen:  1,
                generic: true,
        },
        {
-               name:    "Rsh16Ux32",
-               auxType: auxBool,
-               argLen:  2,
+               name:    "StringLen",
+               argLen:  1,
                generic: true,
        },
        {
-               name:    "Rsh16Ux64",
-               auxType: auxBool,
+               name:    "IMake",
                argLen:  2,
                generic: true,
        },
        {
-               name:    "Rsh32Ux8",
-               auxType: auxBool,
-               argLen:  2,
+               name:    "ITab",
+               argLen:  1,
                generic: true,
        },
        {
-               name:    "Rsh32Ux16",
-               auxType: auxBool,
-               argLen:  2,
+               name:    "IData",
+               argLen:  1,
                generic: true,
        },
        {
-               name:    "Rsh32Ux32",
-               auxType: auxBool,
-               argLen:  2,
+               name:    "StructMake",
+               argLen:  -1,
                generic: true,
        },
        {
-               name:    "Rsh32Ux64",
-               auxType: auxBool,
-               argLen:  2,
+               name:    "StructSelect",
+               auxType: auxInt64,
+               argLen:  1,
                generic: true,
        },
        {
-               name:    "Rsh64Ux8",
-               auxType: auxBool,
-               argLen:  2,
+               name:    "ArrayMake0",
+               argLen:  0,
                generic: true,
        },
        {
-               name:    "Rsh64Ux16",
-               auxType: auxBool,
-               argLen:  2,
+               name:    "ArrayMake1",
+               argLen:  1,
                generic: true,
        },
        {
-               name:    "Rsh64Ux32",
-               auxType: auxBool,
-               argLen:  2,
+               name:    "ArraySelect",
+               auxType: auxInt64,
+               argLen:  1,
                generic: true,
        },
        {
-               name:    "Rsh64Ux64",
-               auxType: auxBool,
-               argLen:  2,
+               name:    "StoreReg",
+               argLen:  1,
                generic: true,
        },
        {
-               name:        "Eq8",
-               argLen:      2,
-               commutative: true,
-               generic:     true,
+               name:    "LoadReg",
+               argLen:  1,
+               generic: true,
        },
        {
-               name:        "Eq16",
-               argLen:      2,
-               commutative: true,
-               generic:     true,
+               name:      "FwdRef",
+               auxType:   auxSym,
+               argLen:    0,
+               symEffect: SymNone,
+               generic:   true,
        },
        {
-               name:        "Eq32",
-               argLen:      2,
-               commutative: true,
-               generic:     true,
+               name:    "Unknown",
+               argLen:  0,
+               generic: true,
        },
        {
-               name:        "Eq64",
-               argLen:      2,
-               commutative: true,
-               generic:     true,
+               name:      "VarDef",
+               auxType:   auxSym,
+               argLen:    1,
+               zeroWidth: true,
+               symEffect: SymNone,
+               generic:   true,
        },
        {
-               name:        "EqPtr",
-               argLen:      2,
-               commutative: true,
-               generic:     true,
+               name:      "VarLive",
+               auxType:   auxSym,
+               argLen:    1,
+               zeroWidth: true,
+               symEffect: SymRead,
+               generic:   true,
+       },
+       {
+               name:      "KeepAlive",
+               argLen:    2,
+               zeroWidth: true,
+               generic:   true,
        },
        {
-               name:    "EqInter",
-               argLen:  2,
+               name:    "InlMark",
+               auxType: auxInt32,
+               argLen:  1,
                generic: true,
        },
        {
-               name:    "EqSlice",
+               name:    "Int64Make",
                argLen:  2,
                generic: true,
        },
        {
-               name:        "Eq32F",
-               argLen:      2,
-               commutative: true,
-               generic:     true,
+               name:    "Int64Hi",
+               argLen:  1,
+               generic: true,
        },
        {
-               name:        "Eq64F",
-               argLen:      2,
-               commutative: true,
-               generic:     true,
+               name:    "Int64Lo",
+               argLen:  1,
+               generic: true,
        },
        {
-               name:        "Neq8",
+               name:        "Add32carry",
                argLen:      2,
                commutative: true,
                generic:     true,
        },
        {
-               name:        "Neq16",
-               argLen:      2,
+               name:        "Add32withcarry",
+               argLen:      3,
                commutative: true,
                generic:     true,
        },
        {
-               name:        "Neq32",
-               argLen:      2,
-               commutative: true,
-               generic:     true,
+               name:    "Sub32carry",
+               argLen:  2,
+               generic: true,
        },
        {
-               name:        "Neq64",
-               argLen:      2,
-               commutative: true,
-               generic:     true,
+               name:    "Sub32withcarry",
+               argLen:  3,
+               generic: true,
        },
        {
-               name:        "NeqPtr",
-               argLen:      2,
+               name:        "Add64carry",
+               argLen:      3,
                commutative: true,
                generic:     true,
        },
        {
-               name:    "NeqInter",
-               argLen:  2,
+               name:    "Sub64borrow",
+               argLen:  3,
                generic: true,
        },
        {
-               name:    "NeqSlice",
-               argLen:  2,
+               name:    "Signmask",
+               argLen:  1,
                generic: true,
        },
        {
-               name:        "Neq32F",
-               argLen:      2,
-               commutative: true,
-               generic:     true,
+               name:    "Zeromask",
+               argLen:  1,
+               generic: true,
        },
        {
-               name:        "Neq64F",
-               argLen:      2,
-               commutative: true,
-               generic:     true,
+               name:    "Slicemask",
+               argLen:  1,
+               generic: true,
        },
        {
-               name:    "Less8",
+               name:    "SpectreIndex",
                argLen:  2,
                generic: true,
        },
        {
-               name:    "Less8U",
+               name:    "SpectreSliceIndex",
                argLen:  2,
                generic: true,
        },
        {
-               name:    "Less16",
-               argLen:  2,
+               name:    "Cvt32Uto32F",
+               argLen:  1,
                generic: true,
        },
        {
-               name:    "Less16U",
-               argLen:  2,
+               name:    "Cvt32Uto64F",
+               argLen:  1,
                generic: true,
        },
        {
-               name:    "Less32",
-               argLen:  2,
+               name:    "Cvt32Fto32U",
+               argLen:  1,
                generic: true,
        },
        {
-               name:    "Less32U",
-               argLen:  2,
+               name:    "Cvt64Fto32U",
+               argLen:  1,
                generic: true,
        },
        {
-               name:    "Less64",
-               argLen:  2,
+               name:    "Cvt64Uto32F",
+               argLen:  1,
                generic: true,
        },
        {
-               name:    "Less64U",
-               argLen:  2,
+               name:    "Cvt64Uto64F",
+               argLen:  1,
                generic: true,
        },
        {
-               name:    "Less32F",
-               argLen:  2,
+               name:    "Cvt32Fto64U",
+               argLen:  1,
                generic: true,
        },
        {
-               name:    "Less64F",
-               argLen:  2,
+               name:    "Cvt64Fto64U",
+               argLen:  1,
                generic: true,
        },
        {
-               name:    "Leq8",
+               name:      "Select0",
+               argLen:    1,
+               zeroWidth: true,
+               generic:   true,
+       },
+       {
+               name:      "Select1",
+               argLen:    1,
+               zeroWidth: true,
+               generic:   true,
+       },
+       {
+               name:    "MakeTuple",
                argLen:  2,
                generic: true,
        },
        {
-               name:    "Leq8U",
-               argLen:  2,
+               name:    "SelectN",
+               auxType: auxInt64,
+               argLen:  1,
                generic: true,
        },
        {
-               name:    "Leq16",
-               argLen:  2,
+               name:    "SelectNAddr",
+               auxType: auxInt64,
+               argLen:  1,
                generic: true,
        },
        {
-               name:    "Leq16U",
-               argLen:  2,
+               name:    "MakeResult",
+               argLen:  -1,
                generic: true,
        },
        {
-               name:    "Leq32",
+               name:    "AtomicLoad8",
                argLen:  2,
                generic: true,
        },
        {
-               name:    "Leq32U",
+               name:    "AtomicLoad32",
                argLen:  2,
                generic: true,
        },
        {
-               name:    "Leq64",
+               name:    "AtomicLoad64",
                argLen:  2,
                generic: true,
        },
        {
-               name:    "Leq64U",
+               name:    "AtomicLoadPtr",
                argLen:  2,
                generic: true,
        },
        {
-               name:    "Leq32F",
+               name:    "AtomicLoadAcq32",
                argLen:  2,
                generic: true,
        },
        {
-               name:    "Leq64F",
+               name:    "AtomicLoadAcq64",
                argLen:  2,
                generic: true,
        },
        {
-               name:    "CondSelect",
-               argLen:  3,
-               generic: true,
+               name:           "AtomicStore8",
+               argLen:         3,
+               hasSideEffects: true,
+               generic:        true,
        },
        {
-               name:        "AndB",
-               argLen:      2,
-               commutative: true,
-               generic:     true,
+               name:           "AtomicStore32",
+               argLen:         3,
+               hasSideEffects: true,
+               generic:        true,
        },
        {
-               name:        "OrB",
-               argLen:      2,
-               commutative: true,
-               generic:     true,
+               name:           "AtomicStore64",
+               argLen:         3,
+               hasSideEffects: true,
+               generic:        true,
        },
        {
-               name:        "EqB",
-               argLen:      2,
-               commutative: true,
-               generic:     true,
+               name:           "AtomicStorePtrNoWB",
+               argLen:         3,
+               hasSideEffects: true,
+               generic:        true,
        },
        {
-               name:        "NeqB",
-               argLen:      2,
-               commutative: true,
-               generic:     true,
+               name:           "AtomicStoreRel32",
+               argLen:         3,
+               hasSideEffects: true,
+               generic:        true,
        },
        {
-               name:    "Not",
-               argLen:  1,
-               generic: true,
+               name:           "AtomicStoreRel64",
+               argLen:         3,
+               hasSideEffects: true,
+               generic:        true,
        },
        {
-               name:    "Neg8",
-               argLen:  1,
-               generic: true,
+               name:           "AtomicExchange8",
+               argLen:         3,
+               hasSideEffects: true,
+               generic:        true,
        },
        {
-               name:    "Neg16",
-               argLen:  1,
-               generic: true,
+               name:           "AtomicExchange32",
+               argLen:         3,
+               hasSideEffects: true,
+               generic:        true,
        },
        {
-               name:    "Neg32",
-               argLen:  1,
-               generic: true,
+               name:           "AtomicExchange64",
+               argLen:         3,
+               hasSideEffects: true,
+               generic:        true,
        },
        {
-               name:    "Neg64",
-               argLen:  1,
-               generic: true,
+               name:           "AtomicAdd32",
+               argLen:         3,
+               hasSideEffects: true,
+               generic:        true,
        },
        {
-               name:    "Neg32F",
-               argLen:  1,
-               generic: true,
+               name:           "AtomicAdd64",
+               argLen:         3,
+               hasSideEffects: true,
+               generic:        true,
        },
        {
-               name:    "Neg64F",
-               argLen:  1,
-               generic: true,
+               name:           "AtomicCompareAndSwap32",
+               argLen:         4,
+               hasSideEffects: true,
+               generic:        true,
        },
        {
-               name:    "Com8",
-               argLen:  1,
-               generic: true,
+               name:           "AtomicCompareAndSwap64",
+               argLen:         4,
+               hasSideEffects: true,
+               generic:        true,
        },
        {
-               name:    "Com16",
-               argLen:  1,
-               generic: true,
+               name:           "AtomicCompareAndSwapRel32",
+               argLen:         4,
+               hasSideEffects: true,
+               generic:        true,
        },
        {
-               name:    "Com32",
-               argLen:  1,
-               generic: true,
+               name:           "AtomicAnd8",
+               argLen:         3,
+               hasSideEffects: true,
+               generic:        true,
        },
        {
-               name:    "Com64",
-               argLen:  1,
-               generic: true,
+               name:           "AtomicOr8",
+               argLen:         3,
+               hasSideEffects: true,
+               generic:        true,
        },
        {
-               name:    "Ctz8",
-               argLen:  1,
-               generic: true,
+               name:           "AtomicAnd32",
+               argLen:         3,
+               hasSideEffects: true,
+               generic:        true,
        },
        {
-               name:    "Ctz16",
-               argLen:  1,
-               generic: true,
+               name:           "AtomicOr32",
+               argLen:         3,
+               hasSideEffects: true,
+               generic:        true,
        },
        {
-               name:    "Ctz32",
-               argLen:  1,
-               generic: true,
+               name:           "AtomicAnd64value",
+               argLen:         3,
+               hasSideEffects: true,
+               generic:        true,
        },
        {
-               name:    "Ctz64",
-               argLen:  1,
-               generic: true,
+               name:           "AtomicAnd32value",
+               argLen:         3,
+               hasSideEffects: true,
+               generic:        true,
        },
        {
-               name:    "Ctz64On32",
-               argLen:  2,
-               generic: true,
+               name:           "AtomicAnd8value",
+               argLen:         3,
+               hasSideEffects: true,
+               generic:        true,
        },
        {
-               name:    "Ctz8NonZero",
-               argLen:  1,
-               generic: true,
+               name:           "AtomicOr64value",
+               argLen:         3,
+               hasSideEffects: true,
+               generic:        true,
        },
        {
-               name:    "Ctz16NonZero",
-               argLen:  1,
-               generic: true,
+               name:           "AtomicOr32value",
+               argLen:         3,
+               hasSideEffects: true,
+               generic:        true,
        },
        {
-               name:    "Ctz32NonZero",
-               argLen:  1,
-               generic: true,
+               name:           "AtomicOr8value",
+               argLen:         3,
+               hasSideEffects: true,
+               generic:        true,
        },
        {
-               name:    "Ctz64NonZero",
-               argLen:  1,
-               generic: true,
+               name:           "AtomicStore8Variant",
+               argLen:         3,
+               hasSideEffects: true,
+               generic:        true,
        },
        {
-               name:    "BitLen8",
-               argLen:  1,
-               generic: true,
+               name:           "AtomicStore32Variant",
+               argLen:         3,
+               hasSideEffects: true,
+               generic:        true,
        },
        {
-               name:    "BitLen16",
-               argLen:  1,
-               generic: true,
+               name:           "AtomicStore64Variant",
+               argLen:         3,
+               hasSideEffects: true,
+               generic:        true,
        },
        {
-               name:    "BitLen32",
-               argLen:  1,
-               generic: true,
+               name:           "AtomicAdd32Variant",
+               argLen:         3,
+               hasSideEffects: true,
+               generic:        true,
        },
        {
-               name:    "BitLen64",
-               argLen:  1,
-               generic: true,
+               name:           "AtomicAdd64Variant",
+               argLen:         3,
+               hasSideEffects: true,
+               generic:        true,
        },
        {
-               name:    "Bswap16",
-               argLen:  1,
-               generic: true,
+               name:           "AtomicExchange8Variant",
+               argLen:         3,
+               hasSideEffects: true,
+               generic:        true,
        },
        {
-               name:    "Bswap32",
-               argLen:  1,
-               generic: true,
+               name:           "AtomicExchange32Variant",
+               argLen:         3,
+               hasSideEffects: true,
+               generic:        true,
        },
        {
-               name:    "Bswap64",
-               argLen:  1,
-               generic: true,
+               name:           "AtomicExchange64Variant",
+               argLen:         3,
+               hasSideEffects: true,
+               generic:        true,
        },
        {
-               name:    "BitRev8",
-               argLen:  1,
-               generic: true,
+               name:           "AtomicCompareAndSwap32Variant",
+               argLen:         4,
+               hasSideEffects: true,
+               generic:        true,
        },
        {
-               name:    "BitRev16",
-               argLen:  1,
-               generic: true,
+               name:           "AtomicCompareAndSwap64Variant",
+               argLen:         4,
+               hasSideEffects: true,
+               generic:        true,
        },
        {
-               name:    "BitRev32",
-               argLen:  1,
-               generic: true,
+               name:           "AtomicAnd64valueVariant",
+               argLen:         3,
+               hasSideEffects: true,
+               generic:        true,
        },
        {
-               name:    "BitRev64",
-               argLen:  1,
-               generic: true,
+               name:           "AtomicOr64valueVariant",
+               argLen:         3,
+               hasSideEffects: true,
+               generic:        true,
        },
        {
-               name:    "PopCount8",
-               argLen:  1,
-               generic: true,
+               name:           "AtomicAnd32valueVariant",
+               argLen:         3,
+               hasSideEffects: true,
+               generic:        true,
        },
        {
-               name:    "PopCount16",
-               argLen:  1,
-               generic: true,
+               name:           "AtomicOr32valueVariant",
+               argLen:         3,
+               hasSideEffects: true,
+               generic:        true,
        },
        {
-               name:    "PopCount32",
-               argLen:  1,
-               generic: true,
+               name:           "AtomicAnd8valueVariant",
+               argLen:         3,
+               hasSideEffects: true,
+               generic:        true,
        },
        {
-               name:    "PopCount64",
-               argLen:  1,
-               generic: true,
+               name:           "AtomicOr8valueVariant",
+               argLen:         3,
+               hasSideEffects: true,
+               generic:        true,
        },
        {
-               name:    "RotateLeft64",
-               argLen:  2,
-               generic: true,
+               name:           "PubBarrier",
+               argLen:         1,
+               hasSideEffects: true,
+               generic:        true,
        },
        {
-               name:    "RotateLeft32",
-               argLen:  2,
-               generic: true,
+               name:      "Clobber",
+               auxType:   auxSymOff,
+               argLen:    0,
+               symEffect: SymNone,
+               generic:   true,
        },
        {
-               name:    "RotateLeft16",
-               argLen:  2,
+               name:    "ClobberReg",
+               argLen:  0,
                generic: true,
        },
        {
-               name:    "RotateLeft8",
-               argLen:  2,
-               generic: true,
+               name:           "PrefetchCache",
+               argLen:         2,
+               hasSideEffects: true,
+               generic:        true,
        },
        {
-               name:    "Sqrt",
-               argLen:  1,
-               generic: true,
+               name:           "PrefetchCacheStreamed",
+               argLen:         2,
+               hasSideEffects: true,
+               generic:        true,
        },
        {
-               name:    "Sqrt32",
-               argLen:  1,
+               name:    "Add32x4",
+               argLen:  2,
                generic: true,
        },
        {
-               name:    "Floor",
-               argLen:  1,
+               name:    "ZeroSIMD",
+               argLen:  0,
                generic: true,
        },
        {
-               name:    "Ceil",
-               argLen:  1,
-               generic: true,
+               name:        "AddFloat32x16",
+               argLen:      2,
+               commutative: true,
+               generic:     true,
        },
        {
-               name:    "Trunc",
-               argLen:  1,
-               generic: true,
+               name:        "AndFloat32x16",
+               argLen:      2,
+               commutative: true,
+               generic:     true,
        },
        {
-               name:    "Round",
-               argLen:  1,
+               name:    "AndNotFloat32x16",
+               argLen:  2,
                generic: true,
        },
        {
-               name:    "RoundToEven",
+               name:    "ApproximateReciprocalFloat32x16",
                argLen:  1,
                generic: true,
        },
        {
-               name:    "Abs",
+               name:    "ApproximateReciprocalOfSqrtFloat32x16",
                argLen:  1,
                generic: true,
        },
        {
-               name:    "Copysign",
+               name:    "DivFloat32x16",
                argLen:  2,
                generic: true,
        },
        {
-               name:    "Min64",
-               argLen:  2,
+               name:        "EqualFloat32x16",
+               argLen:      2,
+               commutative: true,
+               generic:     true,
+       },
+       {
+               name:    "FusedMultiplyAddFloat32x16",
+               argLen:  3,
                generic: true,
        },
        {
-               name:    "Max64",
-               argLen:  2,
+               name:    "FusedMultiplyAddSubFloat32x16",
+               argLen:  3,
                generic: true,
        },
        {
-               name:    "Min64u",
-               argLen:  2,
+               name:    "FusedMultiplySubAddFloat32x16",
+               argLen:  3,
                generic: true,
        },
        {
-               name:    "Max64u",
+               name:    "GreaterFloat32x16",
                argLen:  2,
                generic: true,
        },
        {
-               name:    "Min64F",
+               name:    "GreaterEqualFloat32x16",
                argLen:  2,
                generic: true,
        },
        {
-               name:    "Min32F",
-               argLen:  2,
-               generic: true,
+               name:        "IsNanFloat32x16",
+               argLen:      2,
+               commutative: true,
+               generic:     true,
        },
        {
-               name:    "Max64F",
+               name:    "LessFloat32x16",
                argLen:  2,
                generic: true,
        },
        {
-               name:    "Max32F",
+               name:    "LessEqualFloat32x16",
                argLen:  2,
                generic: true,
        },
        {
-               name:    "FMA",
-               argLen:  3,
-               generic: true,
+               name:        "MaskedAddFloat32x16",
+               argLen:      3,
+               commutative: true,
+               generic:     true,
        },
        {
-               name:      "Phi",
-               argLen:    -1,
-               zeroWidth: true,
-               generic:   true,
+               name:        "MaskedAndFloat32x16",
+               argLen:      3,
+               commutative: true,
+               generic:     true,
        },
        {
-               name:    "Copy",
-               argLen:  1,
+               name:    "MaskedAndNotFloat32x16",
+               argLen:  3,
                generic: true,
        },
        {
-               name:         "Convert",
-               argLen:       2,
-               resultInArg0: true,
-               zeroWidth:    true,
-               generic:      true,
+               name:    "MaskedApproximateReciprocalFloat32x16",
+               argLen:  2,
+               generic: true,
        },
        {
-               name:    "ConstBool",
-               auxType: auxBool,
-               argLen:  0,
+               name:    "MaskedApproximateReciprocalOfSqrtFloat32x16",
+               argLen:  2,
                generic: true,
        },
        {
-               name:    "ConstString",
-               auxType: auxString,
-               argLen:  0,
+               name:    "MaskedDivFloat32x16",
+               argLen:  3,
                generic: true,
        },
        {
-               name:    "ConstNil",
-               argLen:  0,
-               generic: true,
+               name:        "MaskedEqualFloat32x16",
+               argLen:      3,
+               commutative: true,
+               generic:     true,
        },
        {
-               name:    "Const8",
-               auxType: auxInt8,
-               argLen:  0,
+               name:    "MaskedFusedMultiplyAddFloat32x16",
+               argLen:  4,
                generic: true,
        },
        {
-               name:    "Const16",
-               auxType: auxInt16,
-               argLen:  0,
+               name:    "MaskedFusedMultiplyAddSubFloat32x16",
+               argLen:  4,
                generic: true,
        },
        {
-               name:    "Const32",
-               auxType: auxInt32,
-               argLen:  0,
+               name:    "MaskedFusedMultiplySubAddFloat32x16",
+               argLen:  4,
                generic: true,
        },
        {
-               name:    "Const64",
-               auxType: auxInt64,
-               argLen:  0,
+               name:    "MaskedGreaterFloat32x16",
+               argLen:  3,
                generic: true,
        },
        {
-               name:    "Const32F",
-               auxType: auxFloat32,
-               argLen:  0,
+               name:    "MaskedGreaterEqualFloat32x16",
+               argLen:  3,
                generic: true,
        },
        {
-               name:    "Const64F",
-               auxType: auxFloat64,
-               argLen:  0,
-               generic: true,
+               name:        "MaskedIsNanFloat32x16",
+               argLen:      3,
+               commutative: true,
+               generic:     true,
        },
        {
-               name:    "ConstInterface",
-               argLen:  0,
+               name:    "MaskedLessFloat32x16",
+               argLen:  3,
                generic: true,
        },
        {
-               name:    "ConstSlice",
-               argLen:  0,
+               name:    "MaskedLessEqualFloat32x16",
+               argLen:  3,
                generic: true,
        },
        {
-               name:      "InitMem",
-               argLen:    0,
-               zeroWidth: true,
-               generic:   true,
+               name:        "MaskedMaxFloat32x16",
+               argLen:      3,
+               commutative: true,
+               generic:     true,
        },
        {
-               name:      "Arg",
-               auxType:   auxSymOff,
-               argLen:    0,
-               zeroWidth: true,
-               symEffect: SymRead,
-               generic:   true,
+               name:        "MaskedMinFloat32x16",
+               argLen:      3,
+               commutative: true,
+               generic:     true,
        },
        {
-               name:      "ArgIntReg",
-               auxType:   auxNameOffsetInt8,
-               argLen:    0,
-               zeroWidth: true,
-               generic:   true,
+               name:        "MaskedMulFloat32x16",
+               argLen:      3,
+               commutative: true,
+               generic:     true,
        },
        {
-               name:      "ArgFloatReg",
-               auxType:   auxNameOffsetInt8,
-               argLen:    0,
-               zeroWidth: true,
-               generic:   true,
+               name:    "MaskedMulByPowOf2Float32x16",
+               argLen:  3,
+               generic: true,
        },
        {
-               name:      "Addr",
-               auxType:   auxSym,
-               argLen:    1,
-               symEffect: SymAddr,
-               generic:   true,
+               name:        "MaskedNotEqualFloat32x16",
+               argLen:      3,
+               commutative: true,
+               generic:     true,
        },
        {
-               name:      "LocalAddr",
-               auxType:   auxSym,
-               argLen:    2,
-               symEffect: SymAddr,
-               generic:   true,
+               name:        "MaskedOrFloat32x16",
+               argLen:      3,
+               commutative: true,
+               generic:     true,
        },
        {
-               name:      "SP",
-               argLen:    0,
-               zeroWidth: true,
-               fixedReg:  true,
-               generic:   true,
+               name:    "MaskedSqrtFloat32x16",
+               argLen:  2,
+               generic: true,
        },
        {
-               name:      "SB",
-               argLen:    0,
-               zeroWidth: true,
-               fixedReg:  true,
-               generic:   true,
+               name:    "MaskedSubFloat32x16",
+               argLen:  3,
+               generic: true,
        },
        {
-               name:      "SPanchored",
-               argLen:    2,
-               zeroWidth: true,
-               generic:   true,
+               name:        "MaskedXorFloat32x16",
+               argLen:      3,
+               commutative: true,
+               generic:     true,
        },
        {
-               name:    "Load",
-               argLen:  2,
-               generic: true,
+               name:        "MaxFloat32x16",
+               argLen:      2,
+               commutative: true,
+               generic:     true,
        },
        {
-               name:    "Dereference",
-               argLen:  2,
-               generic: true,
+               name:        "MinFloat32x16",
+               argLen:      2,
+               commutative: true,
+               generic:     true,
        },
        {
-               name:    "Store",
-               auxType: auxTyp,
-               argLen:  3,
-               generic: true,
+               name:        "MulFloat32x16",
+               argLen:      2,
+               commutative: true,
+               generic:     true,
        },
        {
-               name:    "Move",
-               auxType: auxTypSize,
-               argLen:  3,
+               name:    "MulByPowOf2Float32x16",
+               argLen:  2,
                generic: true,
        },
        {
-               name:    "Zero",
-               auxType: auxTypSize,
-               argLen:  2,
-               generic: true,
+               name:        "NotEqualFloat32x16",
+               argLen:      2,
+               commutative: true,
+               generic:     true,
        },
        {
-               name:    "StoreWB",
-               auxType: auxTyp,
-               argLen:  3,
-               generic: true,
+               name:        "OrFloat32x16",
+               argLen:      2,
+               commutative: true,
+               generic:     true,
        },
        {
-               name:    "MoveWB",
-               auxType: auxTypSize,
-               argLen:  3,
+               name:    "SqrtFloat32x16",
+               argLen:  1,
                generic: true,
        },
        {
-               name:    "ZeroWB",
-               auxType: auxTypSize,
+               name:    "SubFloat32x16",
                argLen:  2,
                generic: true,
        },
        {
-               name:    "WBend",
-               argLen:  1,
-               generic: true,
+               name:        "XorFloat32x16",
+               argLen:      2,
+               commutative: true,
+               generic:     true,
        },
        {
-               name:    "WB",
-               auxType: auxInt64,
-               argLen:  1,
-               generic: true,
+               name:        "AddFloat32x4",
+               argLen:      2,
+               commutative: true,
+               generic:     true,
        },
        {
-               name:      "HasCPUFeature",
-               auxType:   auxSym,
-               argLen:    0,
-               symEffect: SymNone,
-               generic:   true,
+               name:    "AddSubFloat32x4",
+               argLen:  2,
+               generic: true,
        },
        {
-               name:    "PanicBounds",
-               auxType: auxInt64,
-               argLen:  3,
-               call:    true,
-               generic: true,
+               name:        "AndFloat32x4",
+               argLen:      2,
+               commutative: true,
+               generic:     true,
        },
        {
-               name:    "PanicExtend",
-               auxType: auxInt64,
-               argLen:  4,
-               call:    true,
+               name:    "AndNotFloat32x4",
+               argLen:  2,
                generic: true,
        },
        {
-               name:    "ClosureCall",
-               auxType: auxCallOff,
-               argLen:  -1,
-               call:    true,
+               name:    "ApproximateReciprocalFloat32x4",
+               argLen:  1,
                generic: true,
        },
        {
-               name:    "StaticCall",
-               auxType: auxCallOff,
-               argLen:  -1,
-               call:    true,
+               name:    "ApproximateReciprocalOfSqrtFloat32x4",
+               argLen:  1,
                generic: true,
        },
        {
-               name:    "InterCall",
-               auxType: auxCallOff,
-               argLen:  -1,
-               call:    true,
+               name:    "CeilFloat32x4",
+               argLen:  1,
                generic: true,
        },
        {
-               name:    "TailCall",
-               auxType: auxCallOff,
-               argLen:  -1,
-               call:    true,
+               name:    "DivFloat32x4",
+               argLen:  2,
                generic: true,
        },
        {
-               name:    "ClosureLECall",
-               auxType: auxCallOff,
-               argLen:  -1,
-               call:    true,
-               generic: true,
+               name:        "EqualFloat32x4",
+               argLen:      2,
+               commutative: true,
+               generic:     true,
        },
        {
-               name:    "StaticLECall",
-               auxType: auxCallOff,
-               argLen:  -1,
-               call:    true,
+               name:    "FloorFloat32x4",
+               argLen:  1,
                generic: true,
        },
        {
-               name:    "InterLECall",
-               auxType: auxCallOff,
-               argLen:  -1,
-               call:    true,
+               name:    "FusedMultiplyAddFloat32x4",
+               argLen:  3,
                generic: true,
        },
        {
-               name:    "TailLECall",
-               auxType: auxCallOff,
-               argLen:  -1,
-               call:    true,
+               name:    "FusedMultiplyAddSubFloat32x4",
+               argLen:  3,
                generic: true,
        },
        {
-               name:    "SignExt8to16",
-               argLen:  1,
+               name:    "FusedMultiplySubAddFloat32x4",
+               argLen:  3,
                generic: true,
        },
        {
-               name:    "SignExt8to32",
-               argLen:  1,
+               name:    "GreaterFloat32x4",
+               argLen:  2,
                generic: true,
        },
        {
-               name:    "SignExt8to64",
-               argLen:  1,
+               name:    "GreaterEqualFloat32x4",
+               argLen:  2,
                generic: true,
        },
        {
-               name:    "SignExt16to32",
-               argLen:  1,
-               generic: true,
+               name:        "IsNanFloat32x4",
+               argLen:      2,
+               commutative: true,
+               generic:     true,
        },
        {
-               name:    "SignExt16to64",
-               argLen:  1,
+               name:    "LessFloat32x4",
+               argLen:  2,
                generic: true,
        },
        {
-               name:    "SignExt32to64",
-               argLen:  1,
+               name:    "LessEqualFloat32x4",
+               argLen:  2,
                generic: true,
        },
        {
-               name:    "ZeroExt8to16",
-               argLen:  1,
-               generic: true,
+               name:        "MaskedAddFloat32x4",
+               argLen:      3,
+               commutative: true,
+               generic:     true,
        },
        {
-               name:    "ZeroExt8to32",
-               argLen:  1,
-               generic: true,
+               name:        "MaskedAndFloat32x4",
+               argLen:      3,
+               commutative: true,
+               generic:     true,
        },
        {
-               name:    "ZeroExt8to64",
-               argLen:  1,
+               name:    "MaskedAndNotFloat32x4",
+               argLen:  3,
                generic: true,
        },
        {
-               name:    "ZeroExt16to32",
-               argLen:  1,
+               name:    "MaskedApproximateReciprocalFloat32x4",
+               argLen:  2,
                generic: true,
        },
        {
-               name:    "ZeroExt16to64",
-               argLen:  1,
+               name:    "MaskedApproximateReciprocalOfSqrtFloat32x4",
+               argLen:  2,
                generic: true,
        },
        {
-               name:    "ZeroExt32to64",
-               argLen:  1,
+               name:    "MaskedDivFloat32x4",
+               argLen:  3,
                generic: true,
        },
        {
-               name:    "Trunc16to8",
-               argLen:  1,
-               generic: true,
+               name:        "MaskedEqualFloat32x4",
+               argLen:      3,
+               commutative: true,
+               generic:     true,
        },
        {
-               name:    "Trunc32to8",
-               argLen:  1,
+               name:    "MaskedFusedMultiplyAddFloat32x4",
+               argLen:  4,
                generic: true,
        },
        {
-               name:    "Trunc32to16",
-               argLen:  1,
+               name:    "MaskedFusedMultiplyAddSubFloat32x4",
+               argLen:  4,
                generic: true,
        },
        {
-               name:    "Trunc64to8",
-               argLen:  1,
+               name:    "MaskedFusedMultiplySubAddFloat32x4",
+               argLen:  4,
                generic: true,
        },
        {
-               name:    "Trunc64to16",
-               argLen:  1,
+               name:    "MaskedGreaterFloat32x4",
+               argLen:  3,
                generic: true,
        },
        {
-               name:    "Trunc64to32",
-               argLen:  1,
+               name:    "MaskedGreaterEqualFloat32x4",
+               argLen:  3,
                generic: true,
        },
        {
-               name:    "Cvt32to32F",
-               argLen:  1,
-               generic: true,
+               name:        "MaskedIsNanFloat32x4",
+               argLen:      3,
+               commutative: true,
+               generic:     true,
        },
        {
-               name:    "Cvt32to64F",
-               argLen:  1,
+               name:    "MaskedLessFloat32x4",
+               argLen:  3,
                generic: true,
        },
        {
-               name:    "Cvt64to32F",
-               argLen:  1,
+               name:    "MaskedLessEqualFloat32x4",
+               argLen:  3,
                generic: true,
        },
        {
-               name:    "Cvt64to64F",
-               argLen:  1,
-               generic: true,
+               name:        "MaskedMaxFloat32x4",
+               argLen:      3,
+               commutative: true,
+               generic:     true,
        },
        {
-               name:    "Cvt32Fto32",
-               argLen:  1,
-               generic: true,
+               name:        "MaskedMinFloat32x4",
+               argLen:      3,
+               commutative: true,
+               generic:     true,
        },
        {
-               name:    "Cvt32Fto64",
-               argLen:  1,
-               generic: true,
+               name:        "MaskedMulFloat32x4",
+               argLen:      3,
+               commutative: true,
+               generic:     true,
        },
        {
-               name:    "Cvt64Fto32",
-               argLen:  1,
+               name:    "MaskedMulByPowOf2Float32x4",
+               argLen:  3,
                generic: true,
        },
        {
-               name:    "Cvt64Fto64",
-               argLen:  1,
-               generic: true,
+               name:        "MaskedNotEqualFloat32x4",
+               argLen:      3,
+               commutative: true,
+               generic:     true,
        },
        {
-               name:    "Cvt32Fto64F",
-               argLen:  1,
-               generic: true,
+               name:        "MaskedOrFloat32x4",
+               argLen:      3,
+               commutative: true,
+               generic:     true,
        },
        {
-               name:    "Cvt64Fto32F",
-               argLen:  1,
+               name:    "MaskedSqrtFloat32x4",
+               argLen:  2,
                generic: true,
        },
        {
-               name:    "CvtBoolToUint8",
-               argLen:  1,
+               name:    "MaskedSubFloat32x4",
+               argLen:  3,
                generic: true,
        },
        {
-               name:    "Round32F",
-               argLen:  1,
-               generic: true,
+               name:        "MaskedXorFloat32x4",
+               argLen:      3,
+               commutative: true,
+               generic:     true,
        },
        {
-               name:    "Round64F",
-               argLen:  1,
-               generic: true,
+               name:        "MaxFloat32x4",
+               argLen:      2,
+               commutative: true,
+               generic:     true,
        },
        {
-               name:    "IsNonNil",
-               argLen:  1,
-               generic: true,
+               name:        "MinFloat32x4",
+               argLen:      2,
+               commutative: true,
+               generic:     true,
        },
        {
-               name:    "IsInBounds",
-               argLen:  2,
-               generic: true,
+               name:        "MulFloat32x4",
+               argLen:      2,
+               commutative: true,
+               generic:     true,
        },
        {
-               name:    "IsSliceInBounds",
+               name:    "MulByPowOf2Float32x4",
                argLen:  2,
                generic: true,
        },
        {
-               name:     "NilCheck",
-               argLen:   2,
-               nilCheck: true,
-               generic:  true,
+               name:        "NotEqualFloat32x4",
+               argLen:      2,
+               commutative: true,
+               generic:     true,
        },
        {
-               name:      "GetG",
-               argLen:    1,
-               zeroWidth: true,
-               generic:   true,
+               name:        "OrFloat32x4",
+               argLen:      2,
+               commutative: true,
+               generic:     true,
+       },
+       {
+               name:    "PairwiseAddFloat32x4",
+               argLen:  2,
+               generic: true,
        },
        {
-               name:    "GetClosurePtr",
-               argLen:  0,
+               name:    "PairwiseSubFloat32x4",
+               argLen:  2,
                generic: true,
        },
        {
-               name:    "GetCallerPC",
-               argLen:  0,
+               name:    "RoundFloat32x4",
+               argLen:  1,
                generic: true,
        },
        {
-               name:    "GetCallerSP",
+               name:    "SqrtFloat32x4",
                argLen:  1,
                generic: true,
        },
        {
-               name:    "PtrIndex",
+               name:    "SubFloat32x4",
                argLen:  2,
                generic: true,
        },
        {
-               name:    "OffPtr",
-               auxType: auxInt64,
+               name:    "TruncFloat32x4",
                argLen:  1,
                generic: true,
        },
        {
-               name:    "SliceMake",
-               argLen:  3,
+               name:        "XorFloat32x4",
+               argLen:      2,
+               commutative: true,
+               generic:     true,
+       },
+       {
+               name:        "AddFloat32x8",
+               argLen:      2,
+               commutative: true,
+               generic:     true,
+       },
+       {
+               name:    "AddSubFloat32x8",
+               argLen:  2,
                generic: true,
        },
        {
-               name:    "SlicePtr",
-               argLen:  1,
+               name:        "AndFloat32x8",
+               argLen:      2,
+               commutative: true,
+               generic:     true,
+       },
+       {
+               name:    "AndNotFloat32x8",
+               argLen:  2,
                generic: true,
        },
        {
-               name:    "SliceLen",
+               name:    "ApproximateReciprocalFloat32x8",
                argLen:  1,
                generic: true,
        },
        {
-               name:    "SliceCap",
+               name:    "ApproximateReciprocalOfSqrtFloat32x8",
                argLen:  1,
                generic: true,
        },
        {
-               name:    "SlicePtrUnchecked",
+               name:    "CeilFloat32x8",
                argLen:  1,
                generic: true,
        },
        {
-               name:    "ComplexMake",
+               name:    "DivFloat32x8",
                argLen:  2,
                generic: true,
        },
        {
-               name:    "ComplexReal",
-               argLen:  1,
-               generic: true,
+               name:        "EqualFloat32x8",
+               argLen:      2,
+               commutative: true,
+               generic:     true,
        },
        {
-               name:    "ComplexImag",
+               name:    "FloorFloat32x8",
                argLen:  1,
                generic: true,
        },
        {
-               name:    "StringMake",
-               argLen:  2,
+               name:    "FusedMultiplyAddFloat32x8",
+               argLen:  3,
                generic: true,
        },
        {
-               name:    "StringPtr",
-               argLen:  1,
+               name:    "FusedMultiplyAddSubFloat32x8",
+               argLen:  3,
                generic: true,
        },
        {
-               name:    "StringLen",
-               argLen:  1,
+               name:    "FusedMultiplySubAddFloat32x8",
+               argLen:  3,
                generic: true,
        },
        {
-               name:    "IMake",
+               name:    "GreaterFloat32x8",
                argLen:  2,
                generic: true,
        },
        {
-               name:    "ITab",
-               argLen:  1,
+               name:    "GreaterEqualFloat32x8",
+               argLen:  2,
                generic: true,
        },
        {
-               name:    "IData",
-               argLen:  1,
-               generic: true,
+               name:        "IsNanFloat32x8",
+               argLen:      2,
+               commutative: true,
+               generic:     true,
        },
        {
-               name:    "StructMake",
-               argLen:  -1,
+               name:    "LessFloat32x8",
+               argLen:  2,
                generic: true,
        },
        {
-               name:    "StructSelect",
-               auxType: auxInt64,
-               argLen:  1,
+               name:    "LessEqualFloat32x8",
+               argLen:  2,
                generic: true,
        },
        {
-               name:    "ArrayMake0",
-               argLen:  0,
-               generic: true,
+               name:        "MaskedAddFloat32x8",
+               argLen:      3,
+               commutative: true,
+               generic:     true,
        },
        {
-               name:    "ArrayMake1",
-               argLen:  1,
+               name:        "MaskedAndFloat32x8",
+               argLen:      3,
+               commutative: true,
+               generic:     true,
+       },
+       {
+               name:    "MaskedAndNotFloat32x8",
+               argLen:  3,
                generic: true,
        },
        {
-               name:    "ArraySelect",
-               auxType: auxInt64,
-               argLen:  1,
+               name:    "MaskedApproximateReciprocalFloat32x8",
+               argLen:  2,
                generic: true,
        },
        {
-               name:    "StoreReg",
-               argLen:  1,
+               name:    "MaskedApproximateReciprocalOfSqrtFloat32x8",
+               argLen:  2,
                generic: true,
        },
        {
-               name:    "LoadReg",
-               argLen:  1,
+               name:    "MaskedDivFloat32x8",
+               argLen:  3,
                generic: true,
        },
        {
-               name:      "FwdRef",
-               auxType:   auxSym,
-               argLen:    0,
-               symEffect: SymNone,
-               generic:   true,
+               name:        "MaskedEqualFloat32x8",
+               argLen:      3,
+               commutative: true,
+               generic:     true,
        },
        {
-               name:    "Unknown",
-               argLen:  0,
+               name:    "MaskedFusedMultiplyAddFloat32x8",
+               argLen:  4,
                generic: true,
        },
        {
-               name:      "VarDef",
-               auxType:   auxSym,
-               argLen:    1,
-               zeroWidth: true,
-               symEffect: SymNone,
-               generic:   true,
+               name:    "MaskedFusedMultiplyAddSubFloat32x8",
+               argLen:  4,
+               generic: true,
        },
        {
-               name:      "VarLive",
-               auxType:   auxSym,
-               argLen:    1,
-               zeroWidth: true,
-               symEffect: SymRead,
-               generic:   true,
+               name:    "MaskedFusedMultiplySubAddFloat32x8",
+               argLen:  4,
+               generic: true,
        },
        {
-               name:      "KeepAlive",
-               argLen:    2,
-               zeroWidth: true,
-               generic:   true,
+               name:    "MaskedGreaterFloat32x8",
+               argLen:  3,
+               generic: true,
        },
        {
-               name:    "InlMark",
-               auxType: auxInt32,
-               argLen:  1,
+               name:    "MaskedGreaterEqualFloat32x8",
+               argLen:  3,
                generic: true,
        },
        {
-               name:    "Int64Make",
-               argLen:  2,
-               generic: true,
+               name:        "MaskedIsNanFloat32x8",
+               argLen:      3,
+               commutative: true,
+               generic:     true,
        },
        {
-               name:    "Int64Hi",
-               argLen:  1,
+               name:    "MaskedLessFloat32x8",
+               argLen:  3,
                generic: true,
        },
        {
-               name:    "Int64Lo",
-               argLen:  1,
+               name:    "MaskedLessEqualFloat32x8",
+               argLen:  3,
                generic: true,
        },
        {
-               name:        "Add32carry",
-               argLen:      2,
+               name:        "MaskedMaxFloat32x8",
+               argLen:      3,
                commutative: true,
                generic:     true,
        },
        {
-               name:        "Add32withcarry",
+               name:        "MaskedMinFloat32x8",
                argLen:      3,
                commutative: true,
                generic:     true,
        },
        {
-               name:    "Sub32carry",
-               argLen:  2,
-               generic: true,
+               name:        "MaskedMulFloat32x8",
+               argLen:      3,
+               commutative: true,
+               generic:     true,
        },
        {
-               name:    "Sub32withcarry",
+               name:    "MaskedMulByPowOf2Float32x8",
                argLen:  3,
                generic: true,
        },
        {
-               name:        "Add64carry",
+               name:        "MaskedNotEqualFloat32x8",
                argLen:      3,
                commutative: true,
                generic:     true,
        },
        {
-               name:    "Sub64borrow",
-               argLen:  3,
-               generic: true,
+               name:        "MaskedOrFloat32x8",
+               argLen:      3,
+               commutative: true,
+               generic:     true,
        },
        {
-               name:    "Signmask",
-               argLen:  1,
+               name:    "MaskedSqrtFloat32x8",
+               argLen:  2,
                generic: true,
        },
        {
-               name:    "Zeromask",
-               argLen:  1,
+               name:    "MaskedSubFloat32x8",
+               argLen:  3,
                generic: true,
        },
        {
-               name:    "Slicemask",
-               argLen:  1,
-               generic: true,
+               name:        "MaskedXorFloat32x8",
+               argLen:      3,
+               commutative: true,
+               generic:     true,
        },
        {
-               name:    "SpectreIndex",
-               argLen:  2,
-               generic: true,
+               name:        "MaxFloat32x8",
+               argLen:      2,
+               commutative: true,
+               generic:     true,
        },
        {
-               name:    "SpectreSliceIndex",
-               argLen:  2,
-               generic: true,
+               name:        "MinFloat32x8",
+               argLen:      2,
+               commutative: true,
+               generic:     true,
        },
        {
-               name:    "Cvt32Uto32F",
-               argLen:  1,
-               generic: true,
+               name:        "MulFloat32x8",
+               argLen:      2,
+               commutative: true,
+               generic:     true,
        },
        {
-               name:    "Cvt32Uto64F",
-               argLen:  1,
+               name:    "MulByPowOf2Float32x8",
+               argLen:  2,
                generic: true,
        },
        {
-               name:    "Cvt32Fto32U",
-               argLen:  1,
-               generic: true,
+               name:        "NotEqualFloat32x8",
+               argLen:      2,
+               commutative: true,
+               generic:     true,
        },
        {
-               name:    "Cvt64Fto32U",
-               argLen:  1,
-               generic: true,
+               name:        "OrFloat32x8",
+               argLen:      2,
+               commutative: true,
+               generic:     true,
        },
        {
-               name:    "Cvt64Uto32F",
-               argLen:  1,
+               name:    "PairwiseAddFloat32x8",
+               argLen:  2,
                generic: true,
        },
        {
-               name:    "Cvt64Uto64F",
-               argLen:  1,
+               name:    "PairwiseSubFloat32x8",
+               argLen:  2,
                generic: true,
        },
        {
-               name:    "Cvt32Fto64U",
+               name:    "RoundFloat32x8",
                argLen:  1,
                generic: true,
        },
        {
-               name:    "Cvt64Fto64U",
+               name:    "SqrtFloat32x8",
                argLen:  1,
                generic: true,
        },
        {
-               name:      "Select0",
-               argLen:    1,
-               zeroWidth: true,
-               generic:   true,
-       },
-       {
-               name:      "Select1",
-               argLen:    1,
-               zeroWidth: true,
-               generic:   true,
-       },
-       {
-               name:    "MakeTuple",
+               name:    "SubFloat32x8",
                argLen:  2,
                generic: true,
        },
        {
-               name:    "SelectN",
-               auxType: auxInt64,
+               name:    "TruncFloat32x8",
                argLen:  1,
                generic: true,
        },
        {
-               name:    "SelectNAddr",
-               auxType: auxInt64,
-               argLen:  1,
-               generic: true,
+               name:        "XorFloat32x8",
+               argLen:      2,
+               commutative: true,
+               generic:     true,
        },
        {
-               name:    "MakeResult",
-               argLen:  -1,
-               generic: true,
+               name:        "AddFloat64x2",
+               argLen:      2,
+               commutative: true,
+               generic:     true,
        },
        {
-               name:    "AtomicLoad8",
+               name:    "AddSubFloat64x2",
                argLen:  2,
                generic: true,
        },
        {
-               name:    "AtomicLoad32",
+               name:        "AndFloat64x2",
+               argLen:      2,
+               commutative: true,
+               generic:     true,
+       },
+       {
+               name:    "AndNotFloat64x2",
                argLen:  2,
                generic: true,
        },
        {
-               name:    "AtomicLoad64",
-               argLen:  2,
+               name:    "ApproximateReciprocalFloat64x2",
+               argLen:  1,
                generic: true,
        },
        {
-               name:    "AtomicLoadPtr",
-               argLen:  2,
+               name:    "ApproximateReciprocalOfSqrtFloat64x2",
+               argLen:  1,
                generic: true,
        },
        {
-               name:    "AtomicLoadAcq32",
-               argLen:  2,
+               name:    "CeilFloat64x2",
+               argLen:  1,
                generic: true,
        },
        {
-               name:    "AtomicLoadAcq64",
+               name:    "DivFloat64x2",
                argLen:  2,
                generic: true,
        },
        {
-               name:           "AtomicStore8",
-               argLen:         3,
-               hasSideEffects: true,
-               generic:        true,
+               name:        "DotProdBroadcastFloat64x2",
+               argLen:      2,
+               commutative: true,
+               generic:     true,
        },
        {
-               name:           "AtomicStore32",
-               argLen:         3,
-               hasSideEffects: true,
-               generic:        true,
+               name:        "EqualFloat64x2",
+               argLen:      2,
+               commutative: true,
+               generic:     true,
        },
        {
-               name:           "AtomicStore64",
-               argLen:         3,
-               hasSideEffects: true,
-               generic:        true,
+               name:    "FloorFloat64x2",
+               argLen:  1,
+               generic: true,
        },
        {
-               name:           "AtomicStorePtrNoWB",
-               argLen:         3,
-               hasSideEffects: true,
-               generic:        true,
+               name:    "FusedMultiplyAddFloat64x2",
+               argLen:  3,
+               generic: true,
        },
        {
-               name:           "AtomicStoreRel32",
-               argLen:         3,
-               hasSideEffects: true,
-               generic:        true,
+               name:    "FusedMultiplyAddSubFloat64x2",
+               argLen:  3,
+               generic: true,
        },
        {
-               name:           "AtomicStoreRel64",
-               argLen:         3,
-               hasSideEffects: true,
-               generic:        true,
+               name:    "FusedMultiplySubAddFloat64x2",
+               argLen:  3,
+               generic: true,
        },
        {
-               name:           "AtomicExchange8",
-               argLen:         3,
-               hasSideEffects: true,
-               generic:        true,
+               name:    "GreaterFloat64x2",
+               argLen:  2,
+               generic: true,
        },
        {
-               name:           "AtomicExchange32",
-               argLen:         3,
-               hasSideEffects: true,
-               generic:        true,
+               name:    "GreaterEqualFloat64x2",
+               argLen:  2,
+               generic: true,
        },
        {
-               name:           "AtomicExchange64",
-               argLen:         3,
-               hasSideEffects: true,
-               generic:        true,
+               name:        "IsNanFloat64x2",
+               argLen:      2,
+               commutative: true,
+               generic:     true,
        },
        {
-               name:           "AtomicAdd32",
-               argLen:         3,
-               hasSideEffects: true,
-               generic:        true,
+               name:    "LessFloat64x2",
+               argLen:  2,
+               generic: true,
        },
        {
-               name:           "AtomicAdd64",
-               argLen:         3,
-               hasSideEffects: true,
-               generic:        true,
+               name:    "LessEqualFloat64x2",
+               argLen:  2,
+               generic: true,
        },
        {
-               name:           "AtomicCompareAndSwap32",
-               argLen:         4,
-               hasSideEffects: true,
-               generic:        true,
+               name:        "MaskedAddFloat64x2",
+               argLen:      3,
+               commutative: true,
+               generic:     true,
        },
        {
-               name:           "AtomicCompareAndSwap64",
-               argLen:         4,
-               hasSideEffects: true,
-               generic:        true,
+               name:        "MaskedAndFloat64x2",
+               argLen:      3,
+               commutative: true,
+               generic:     true,
        },
        {
-               name:           "AtomicCompareAndSwapRel32",
-               argLen:         4,
-               hasSideEffects: true,
-               generic:        true,
+               name:    "MaskedAndNotFloat64x2",
+               argLen:  3,
+               generic: true,
        },
        {
-               name:           "AtomicAnd8",
-               argLen:         3,
-               hasSideEffects: true,
-               generic:        true,
+               name:    "MaskedApproximateReciprocalFloat64x2",
+               argLen:  2,
+               generic: true,
        },
        {
-               name:           "AtomicOr8",
-               argLen:         3,
-               hasSideEffects: true,
-               generic:        true,
+               name:    "MaskedApproximateReciprocalOfSqrtFloat64x2",
+               argLen:  2,
+               generic: true,
        },
        {
-               name:           "AtomicAnd32",
-               argLen:         3,
-               hasSideEffects: true,
-               generic:        true,
+               name:    "MaskedDivFloat64x2",
+               argLen:  3,
+               generic: true,
        },
        {
-               name:           "AtomicOr32",
-               argLen:         3,
-               hasSideEffects: true,
-               generic:        true,
+               name:        "MaskedEqualFloat64x2",
+               argLen:      3,
+               commutative: true,
+               generic:     true,
        },
        {
-               name:           "AtomicAnd64value",
-               argLen:         3,
-               hasSideEffects: true,
-               generic:        true,
+               name:    "MaskedFusedMultiplyAddFloat64x2",
+               argLen:  4,
+               generic: true,
        },
        {
-               name:           "AtomicAnd32value",
-               argLen:         3,
-               hasSideEffects: true,
-               generic:        true,
+               name:    "MaskedFusedMultiplyAddSubFloat64x2",
+               argLen:  4,
+               generic: true,
        },
        {
-               name:           "AtomicAnd8value",
-               argLen:         3,
-               hasSideEffects: true,
-               generic:        true,
+               name:    "MaskedFusedMultiplySubAddFloat64x2",
+               argLen:  4,
+               generic: true,
        },
        {
-               name:           "AtomicOr64value",
-               argLen:         3,
-               hasSideEffects: true,
-               generic:        true,
+               name:    "MaskedGreaterFloat64x2",
+               argLen:  3,
+               generic: true,
        },
        {
-               name:           "AtomicOr32value",
-               argLen:         3,
-               hasSideEffects: true,
-               generic:        true,
+               name:    "MaskedGreaterEqualFloat64x2",
+               argLen:  3,
+               generic: true,
        },
        {
-               name:           "AtomicOr8value",
-               argLen:         3,
-               hasSideEffects: true,
-               generic:        true,
+               name:        "MaskedIsNanFloat64x2",
+               argLen:      3,
+               commutative: true,
+               generic:     true,
        },
        {
-               name:           "AtomicStore8Variant",
-               argLen:         3,
-               hasSideEffects: true,
-               generic:        true,
+               name:    "MaskedLessFloat64x2",
+               argLen:  3,
+               generic: true,
        },
        {
-               name:           "AtomicStore32Variant",
-               argLen:         3,
-               hasSideEffects: true,
-               generic:        true,
+               name:    "MaskedLessEqualFloat64x2",
+               argLen:  3,
+               generic: true,
        },
        {
-               name:           "AtomicStore64Variant",
-               argLen:         3,
-               hasSideEffects: true,
-               generic:        true,
+               name:        "MaskedMaxFloat64x2",
+               argLen:      3,
+               commutative: true,
+               generic:     true,
        },
        {
-               name:           "AtomicAdd32Variant",
-               argLen:         3,
-               hasSideEffects: true,
-               generic:        true,
+               name:        "MaskedMinFloat64x2",
+               argLen:      3,
+               commutative: true,
+               generic:     true,
        },
        {
-               name:           "AtomicAdd64Variant",
-               argLen:         3,
-               hasSideEffects: true,
-               generic:        true,
+               name:        "MaskedMulFloat64x2",
+               argLen:      3,
+               commutative: true,
+               generic:     true,
        },
        {
-               name:           "AtomicExchange8Variant",
-               argLen:         3,
-               hasSideEffects: true,
-               generic:        true,
+               name:    "MaskedMulByPowOf2Float64x2",
+               argLen:  3,
+               generic: true,
        },
        {
-               name:           "AtomicExchange32Variant",
-               argLen:         3,
-               hasSideEffects: true,
-               generic:        true,
+               name:        "MaskedNotEqualFloat64x2",
+               argLen:      3,
+               commutative: true,
+               generic:     true,
        },
        {
-               name:           "AtomicExchange64Variant",
-               argLen:         3,
-               hasSideEffects: true,
-               generic:        true,
+               name:        "MaskedOrFloat64x2",
+               argLen:      3,
+               commutative: true,
+               generic:     true,
        },
        {
-               name:           "AtomicCompareAndSwap32Variant",
-               argLen:         4,
-               hasSideEffects: true,
-               generic:        true,
+               name:    "MaskedSqrtFloat64x2",
+               argLen:  2,
+               generic: true,
        },
        {
-               name:           "AtomicCompareAndSwap64Variant",
-               argLen:         4,
-               hasSideEffects: true,
-               generic:        true,
+               name:    "MaskedSubFloat64x2",
+               argLen:  3,
+               generic: true,
        },
        {
-               name:           "AtomicAnd64valueVariant",
-               argLen:         3,
-               hasSideEffects: true,
-               generic:        true,
+               name:        "MaskedXorFloat64x2",
+               argLen:      3,
+               commutative: true,
+               generic:     true,
        },
        {
-               name:           "AtomicOr64valueVariant",
-               argLen:         3,
-               hasSideEffects: true,
-               generic:        true,
+               name:        "MaxFloat64x2",
+               argLen:      2,
+               commutative: true,
+               generic:     true,
        },
        {
-               name:           "AtomicAnd32valueVariant",
-               argLen:         3,
-               hasSideEffects: true,
-               generic:        true,
+               name:        "MinFloat64x2",
+               argLen:      2,
+               commutative: true,
+               generic:     true,
        },
        {
-               name:           "AtomicOr32valueVariant",
-               argLen:         3,
-               hasSideEffects: true,
-               generic:        true,
+               name:        "MulFloat64x2",
+               argLen:      2,
+               commutative: true,
+               generic:     true,
        },
        {
-               name:           "AtomicAnd8valueVariant",
-               argLen:         3,
-               hasSideEffects: true,
-               generic:        true,
+               name:    "MulByPowOf2Float64x2",
+               argLen:  2,
+               generic: true,
        },
        {
-               name:           "AtomicOr8valueVariant",
-               argLen:         3,
-               hasSideEffects: true,
-               generic:        true,
+               name:        "NotEqualFloat64x2",
+               argLen:      2,
+               commutative: true,
+               generic:     true,
        },
        {
-               name:           "PubBarrier",
-               argLen:         1,
-               hasSideEffects: true,
-               generic:        true,
+               name:        "OrFloat64x2",
+               argLen:      2,
+               commutative: true,
+               generic:     true,
        },
        {
-               name:      "Clobber",
-               auxType:   auxSymOff,
-               argLen:    0,
-               symEffect: SymNone,
-               generic:   true,
+               name:    "PairwiseAddFloat64x2",
+               argLen:  2,
+               generic: true,
        },
        {
-               name:    "ClobberReg",
-               argLen:  0,
+               name:    "PairwiseSubFloat64x2",
+               argLen:  2,
                generic: true,
        },
        {
-               name:           "PrefetchCache",
-               argLen:         2,
-               hasSideEffects: true,
-               generic:        true,
+               name:    "RoundFloat64x2",
+               argLen:  1,
+               generic: true,
        },
        {
-               name:           "PrefetchCacheStreamed",
-               argLen:         2,
-               hasSideEffects: true,
-               generic:        true,
+               name:    "SqrtFloat64x2",
+               argLen:  1,
+               generic: true,
        },
        {
-               name:    "Add32x4",
+               name:    "SubFloat64x2",
                argLen:  2,
                generic: true,
        },
        {
-               name:    "ZeroSIMD",
-               argLen:  0,
+               name:    "TruncFloat64x2",
+               argLen:  1,
                generic: true,
        },
        {
-               name:        "AddFloat32x16",
+               name:        "XorFloat64x2",
                argLen:      2,
                commutative: true,
                generic:     true,
        },
        {
-               name:        "AndFloat32x16",
+               name:        "AddFloat64x4",
                argLen:      2,
                commutative: true,
                generic:     true,
        },
        {
-               name:    "AndNotFloat32x16",
+               name:    "AddSubFloat64x4",
                argLen:  2,
                generic: true,
        },
        {
-               name:    "ApproximateReciprocalFloat32x16",
+               name:        "AndFloat64x4",
+               argLen:      2,
+               commutative: true,
+               generic:     true,
+       },
+       {
+               name:    "AndNotFloat64x4",
+               argLen:  2,
+               generic: true,
+       },
+       {
+               name:    "ApproximateReciprocalFloat64x4",
                argLen:  1,
                generic: true,
        },
        {
-               name:    "ApproximateReciprocalOfSqrtFloat32x16",
+               name:    "ApproximateReciprocalOfSqrtFloat64x4",
                argLen:  1,
                generic: true,
        },
        {
-               name:    "DivFloat32x16",
+               name:    "CeilFloat64x4",
+               argLen:  1,
+               generic: true,
+       },
+       {
+               name:    "DivFloat64x4",
                argLen:  2,
                generic: true,
        },
        {
-               name:        "EqualFloat32x16",
+               name:        "EqualFloat64x4",
                argLen:      2,
                commutative: true,
                generic:     true,
        },
        {
-               name:    "FusedMultiplyAddFloat32x16",
+               name:    "FloorFloat64x4",
+               argLen:  1,
+               generic: true,
+       },
+       {
+               name:    "FusedMultiplyAddFloat64x4",
                argLen:  3,
                generic: true,
        },
        {
-               name:    "FusedMultiplyAddSubFloat32x16",
+               name:    "FusedMultiplyAddSubFloat64x4",
                argLen:  3,
                generic: true,
        },
        {
-               name:    "FusedMultiplySubAddFloat32x16",
+               name:    "FusedMultiplySubAddFloat64x4",
                argLen:  3,
                generic: true,
        },
        {
-               name:    "GreaterFloat32x16",
+               name:    "GreaterFloat64x4",
                argLen:  2,
                generic: true,
        },
        {
-               name:    "GreaterEqualFloat32x16",
+               name:    "GreaterEqualFloat64x4",
                argLen:  2,
                generic: true,
        },
        {
-               name:        "IsNanFloat32x16",
+               name:        "IsNanFloat64x4",
                argLen:      2,
                commutative: true,
                generic:     true,
        },
        {
-               name:    "LessFloat32x16",
+               name:    "LessFloat64x4",
                argLen:  2,
                generic: true,
        },
        {
-               name:    "LessEqualFloat32x16",
+               name:    "LessEqualFloat64x4",
                argLen:  2,
                generic: true,
        },
        {
-               name:        "MaskedAddFloat32x16",
+               name:        "MaskedAddFloat64x4",
                argLen:      3,
                commutative: true,
                generic:     true,
        },
        {
-               name:        "MaskedAndFloat32x16",
+               name:        "MaskedAndFloat64x4",
                argLen:      3,
                commutative: true,
                generic:     true,
        },
        {
-               name:    "MaskedAndNotFloat32x16",
+               name:    "MaskedAndNotFloat64x4",
                argLen:  3,
                generic: true,
        },
        {
-               name:    "MaskedApproximateReciprocalFloat32x16",
+               name:    "MaskedApproximateReciprocalFloat64x4",
                argLen:  2,
                generic: true,
        },
        {
-               name:    "MaskedApproximateReciprocalOfSqrtFloat32x16",
+               name:    "MaskedApproximateReciprocalOfSqrtFloat64x4",
                argLen:  2,
                generic: true,
        },
        {
-               name:    "MaskedDivFloat32x16",
+               name:    "MaskedDivFloat64x4",
                argLen:  3,
                generic: true,
        },
        {
-               name:        "MaskedEqualFloat32x16",
+               name:        "MaskedEqualFloat64x4",
                argLen:      3,
                commutative: true,
                generic:     true,
        },
        {
-               name:    "MaskedFusedMultiplyAddFloat32x16",
+               name:    "MaskedFusedMultiplyAddFloat64x4",
                argLen:  4,
                generic: true,
        },
        {
-               name:    "MaskedFusedMultiplyAddSubFloat32x16",
+               name:    "MaskedFusedMultiplyAddSubFloat64x4",
                argLen:  4,
                generic: true,
        },
        {
-               name:    "MaskedFusedMultiplySubAddFloat32x16",
+               name:    "MaskedFusedMultiplySubAddFloat64x4",
                argLen:  4,
                generic: true,
        },
        {
-               name:    "MaskedGreaterFloat32x16",
+               name:    "MaskedGreaterFloat64x4",
                argLen:  3,
                generic: true,
        },
        {
-               name:    "MaskedGreaterEqualFloat32x16",
+               name:    "MaskedGreaterEqualFloat64x4",
                argLen:  3,
                generic: true,
        },
        {
-               name:        "MaskedIsNanFloat32x16",
+               name:        "MaskedIsNanFloat64x4",
                argLen:      3,
                commutative: true,
                generic:     true,
        },
        {
-               name:    "MaskedLessFloat32x16",
+               name:    "MaskedLessFloat64x4",
                argLen:  3,
                generic: true,
        },
        {
-               name:    "MaskedLessEqualFloat32x16",
+               name:    "MaskedLessEqualFloat64x4",
                argLen:  3,
                generic: true,
        },
        {
-               name:        "MaskedMaxFloat32x16",
+               name:        "MaskedMaxFloat64x4",
                argLen:      3,
                commutative: true,
                generic:     true,
        },
        {
-               name:        "MaskedMinFloat32x16",
+               name:        "MaskedMinFloat64x4",
                argLen:      3,
                commutative: true,
                generic:     true,
        },
        {
-               name:        "MaskedMulFloat32x16",
+               name:        "MaskedMulFloat64x4",
                argLen:      3,
                commutative: true,
                generic:     true,
        },
        {
-               name:    "MaskedMulByPowOf2Float32x16",
+               name:    "MaskedMulByPowOf2Float64x4",
                argLen:  3,
                generic: true,
        },
        {
-               name:        "MaskedNotEqualFloat32x16",
+               name:        "MaskedNotEqualFloat64x4",
                argLen:      3,
                commutative: true,
                generic:     true,
        },
        {
-               name:        "MaskedOrFloat32x16",
+               name:        "MaskedOrFloat64x4",
                argLen:      3,
                commutative: true,
                generic:     true,
        },
        {
-               name:    "MaskedSqrtFloat32x16",
+               name:    "MaskedSqrtFloat64x4",
                argLen:  2,
                generic: true,
        },
        {
-               name:    "MaskedSubFloat32x16",
+               name:    "MaskedSubFloat64x4",
                argLen:  3,
                generic: true,
        },
        {
-               name:        "MaskedXorFloat32x16",
+               name:        "MaskedXorFloat64x4",
                argLen:      3,
                commutative: true,
                generic:     true,
        },
        {
-               name:        "MaxFloat32x16",
+               name:        "MaxFloat64x4",
                argLen:      2,
                commutative: true,
                generic:     true,
        },
        {
-               name:        "MinFloat32x16",
+               name:        "MinFloat64x4",
                argLen:      2,
                commutative: true,
                generic:     true,
        },
        {
-               name:        "MulFloat32x16",
+               name:        "MulFloat64x4",
                argLen:      2,
                commutative: true,
                generic:     true,
        },
        {
-               name:    "MulByPowOf2Float32x16",
+               name:    "MulByPowOf2Float64x4",
                argLen:  2,
                generic: true,
        },
        {
-               name:        "NotEqualFloat32x16",
+               name:        "NotEqualFloat64x4",
                argLen:      2,
                commutative: true,
                generic:     true,
        },
        {
-               name:        "OrFloat32x16",
+               name:        "OrFloat64x4",
                argLen:      2,
                commutative: true,
                generic:     true,
        },
        {
-               name:    "SqrtFloat32x16",
+               name:    "PairwiseAddFloat64x4",
+               argLen:  2,
+               generic: true,
+       },
+       {
+               name:    "PairwiseSubFloat64x4",
+               argLen:  2,
+               generic: true,
+       },
+       {
+               name:    "RoundFloat64x4",
                argLen:  1,
                generic: true,
        },
        {
-               name:    "SubFloat32x16",
+               name:    "SqrtFloat64x4",
+               argLen:  1,
+               generic: true,
+       },
+       {
+               name:    "SubFloat64x4",
                argLen:  2,
                generic: true,
        },
        {
-               name:        "XorFloat32x16",
+               name:    "TruncFloat64x4",
+               argLen:  1,
+               generic: true,
+       },
+       {
+               name:        "XorFloat64x4",
                argLen:      2,
                commutative: true,
                generic:     true,
        },
        {
-               name:        "AddFloat32x4",
+               name:        "AddFloat64x8",
                argLen:      2,
                commutative: true,
                generic:     true,
        },
        {
-               name:    "AddSubFloat32x4",
+               name:        "AndFloat64x8",
+               argLen:      2,
+               commutative: true,
+               generic:     true,
+       },
+       {
+               name:    "AndNotFloat64x8",
                argLen:  2,
                generic: true,
        },
        {
-               name:        "AndFloat32x4",
+               name:    "ApproximateReciprocalFloat64x8",
+               argLen:  1,
+               generic: true,
+       },
+       {
+               name:    "ApproximateReciprocalOfSqrtFloat64x8",
+               argLen:  1,
+               generic: true,
+       },
+       {
+               name:    "DivFloat64x8",
+               argLen:  2,
+               generic: true,
+       },
+       {
+               name:        "EqualFloat64x8",
                argLen:      2,
                commutative: true,
                generic:     true,
        },
        {
-               name:    "AndNotFloat32x4",
-               argLen:  2,
+               name:    "FusedMultiplyAddFloat64x8",
+               argLen:  3,
                generic: true,
        },
        {
-               name:    "ApproximateReciprocalFloat32x4",
-               argLen:  1,
+               name:    "FusedMultiplyAddSubFloat64x8",
+               argLen:  3,
                generic: true,
        },
        {
-               name:    "ApproximateReciprocalOfSqrtFloat32x4",
-               argLen:  1,
+               name:    "FusedMultiplySubAddFloat64x8",
+               argLen:  3,
                generic: true,
        },
        {
-               name:    "CeilFloat32x4",
-               argLen:  1,
+               name:    "GreaterFloat64x8",
+               argLen:  2,
                generic: true,
        },
        {
-               name:    "DivFloat32x4",
+               name:    "GreaterEqualFloat64x8",
                argLen:  2,
                generic: true,
        },
        {
-               name:        "EqualFloat32x4",
+               name:        "IsNanFloat64x8",
                argLen:      2,
                commutative: true,
                generic:     true,
        },
        {
-               name:    "FloorFloat32x4",
-               argLen:  1,
+               name:    "LessFloat64x8",
+               argLen:  2,
                generic: true,
        },
        {
-               name:    "FusedMultiplyAddFloat32x4",
+               name:    "LessEqualFloat64x8",
+               argLen:  2,
+               generic: true,
+       },
+       {
+               name:        "MaskedAddFloat64x8",
+               argLen:      3,
+               commutative: true,
+               generic:     true,
+       },
+       {
+               name:        "MaskedAndFloat64x8",
+               argLen:      3,
+               commutative: true,
+               generic:     true,
+       },
+       {
+               name:    "MaskedAndNotFloat64x8",
                argLen:  3,
                generic: true,
        },
        {
-               name:    "FusedMultiplyAddSubFloat32x4",
+               name:    "MaskedApproximateReciprocalFloat64x8",
+               argLen:  2,
+               generic: true,
+       },
+       {
+               name:    "MaskedApproximateReciprocalOfSqrtFloat64x8",
+               argLen:  2,
+               generic: true,
+       },
+       {
+               name:    "MaskedDivFloat64x8",
+               argLen:  3,
+               generic: true,
+       },
+       {
+               name:        "MaskedEqualFloat64x8",
+               argLen:      3,
+               commutative: true,
+               generic:     true,
+       },
+       {
+               name:    "MaskedFusedMultiplyAddFloat64x8",
+               argLen:  4,
+               generic: true,
+       },
+       {
+               name:    "MaskedFusedMultiplyAddSubFloat64x8",
+               argLen:  4,
+               generic: true,
+       },
+       {
+               name:    "MaskedFusedMultiplySubAddFloat64x8",
+               argLen:  4,
+               generic: true,
+       },
+       {
+               name:    "MaskedGreaterFloat64x8",
+               argLen:  3,
+               generic: true,
+       },
+       {
+               name:    "MaskedGreaterEqualFloat64x8",
+               argLen:  3,
+               generic: true,
+       },
+       {
+               name:        "MaskedIsNanFloat64x8",
+               argLen:      3,
+               commutative: true,
+               generic:     true,
+       },
+       {
+               name:    "MaskedLessFloat64x8",
+               argLen:  3,
+               generic: true,
+       },
+       {
+               name:    "MaskedLessEqualFloat64x8",
+               argLen:  3,
+               generic: true,
+       },
+       {
+               name:        "MaskedMaxFloat64x8",
+               argLen:      3,
+               commutative: true,
+               generic:     true,
+       },
+       {
+               name:        "MaskedMinFloat64x8",
+               argLen:      3,
+               commutative: true,
+               generic:     true,
+       },
+       {
+               name:        "MaskedMulFloat64x8",
+               argLen:      3,
+               commutative: true,
+               generic:     true,
+       },
+       {
+               name:    "MaskedMulByPowOf2Float64x8",
+               argLen:  3,
+               generic: true,
+       },
+       {
+               name:        "MaskedNotEqualFloat64x8",
+               argLen:      3,
+               commutative: true,
+               generic:     true,
+       },
+       {
+               name:        "MaskedOrFloat64x8",
+               argLen:      3,
+               commutative: true,
+               generic:     true,
+       },
+       {
+               name:    "MaskedSqrtFloat64x8",
+               argLen:  2,
+               generic: true,
+       },
+       {
+               name:    "MaskedSubFloat64x8",
                argLen:  3,
                generic: true,
        },
        {
-               name:    "FusedMultiplySubAddFloat32x4",
-               argLen:  3,
+               name:        "MaskedXorFloat64x8",
+               argLen:      3,
+               commutative: true,
+               generic:     true,
+       },
+       {
+               name:        "MaxFloat64x8",
+               argLen:      2,
+               commutative: true,
+               generic:     true,
+       },
+       {
+               name:        "MinFloat64x8",
+               argLen:      2,
+               commutative: true,
+               generic:     true,
+       },
+       {
+               name:        "MulFloat64x8",
+               argLen:      2,
+               commutative: true,
+               generic:     true,
+       },
+       {
+               name:    "MulByPowOf2Float64x8",
+               argLen:  2,
+               generic: true,
+       },
+       {
+               name:        "NotEqualFloat64x8",
+               argLen:      2,
+               commutative: true,
+               generic:     true,
+       },
+       {
+               name:        "OrFloat64x8",
+               argLen:      2,
+               commutative: true,
+               generic:     true,
+       },
+       {
+               name:    "SqrtFloat64x8",
+               argLen:  1,
+               generic: true,
+       },
+       {
+               name:    "SubFloat64x8",
+               argLen:  2,
                generic: true,
        },
        {
-               name:    "GreaterFloat32x4",
-               argLen:  2,
-               generic: true,
+               name:        "XorFloat64x8",
+               argLen:      2,
+               commutative: true,
+               generic:     true,
        },
        {
-               name:    "GreaterEqualFloat32x4",
-               argLen:  2,
+               name:    "AbsoluteInt16x16",
+               argLen:  1,
                generic: true,
        },
        {
-               name:        "IsNanFloat32x4",
+               name:        "AddInt16x16",
                argLen:      2,
                commutative: true,
                generic:     true,
        },
        {
-               name:    "LessFloat32x4",
-               argLen:  2,
-               generic: true,
+               name:        "AndInt16x16",
+               argLen:      2,
+               commutative: true,
+               generic:     true,
        },
        {
-               name:    "LessEqualFloat32x4",
+               name:    "AndNotInt16x16",
                argLen:  2,
                generic: true,
        },
        {
-               name:        "MaskedAddFloat32x4",
-               argLen:      3,
+               name:        "EqualInt16x16",
+               argLen:      2,
                commutative: true,
                generic:     true,
        },
        {
-               name:        "MaskedAndFloat32x4",
-               argLen:      3,
-               commutative: true,
-               generic:     true,
+               name:    "GreaterInt16x16",
+               argLen:  2,
+               generic: true,
        },
        {
-               name:    "MaskedAndNotFloat32x4",
-               argLen:  3,
+               name:    "GreaterEqualInt16x16",
+               argLen:  2,
                generic: true,
        },
        {
-               name:    "MaskedApproximateReciprocalFloat32x4",
+               name:    "LessInt16x16",
                argLen:  2,
                generic: true,
        },
        {
-               name:    "MaskedApproximateReciprocalOfSqrtFloat32x4",
+               name:    "LessEqualInt16x16",
                argLen:  2,
                generic: true,
        },
        {
-               name:    "MaskedDivFloat32x4",
-               argLen:  3,
+               name:    "MaskedAbsoluteInt16x16",
+               argLen:  2,
                generic: true,
        },
        {
-               name:        "MaskedEqualFloat32x4",
+               name:        "MaskedAddInt16x16",
                argLen:      3,
                commutative: true,
                generic:     true,
        },
        {
-               name:    "MaskedFusedMultiplyAddFloat32x4",
-               argLen:  4,
-               generic: true,
+               name:        "MaskedEqualInt16x16",
+               argLen:      3,
+               commutative: true,
+               generic:     true,
        },
        {
-               name:    "MaskedFusedMultiplyAddSubFloat32x4",
-               argLen:  4,
+               name:    "MaskedGreaterInt16x16",
+               argLen:  3,
                generic: true,
        },
        {
-               name:    "MaskedFusedMultiplySubAddFloat32x4",
-               argLen:  4,
+               name:    "MaskedGreaterEqualInt16x16",
+               argLen:  3,
                generic: true,
        },
        {
-               name:    "MaskedGreaterFloat32x4",
+               name:    "MaskedLessInt16x16",
                argLen:  3,
                generic: true,
        },
        {
-               name:    "MaskedGreaterEqualFloat32x4",
+               name:    "MaskedLessEqualInt16x16",
                argLen:  3,
                generic: true,
        },
        {
-               name:        "MaskedIsNanFloat32x4",
+               name:        "MaskedMaxInt16x16",
                argLen:      3,
                commutative: true,
                generic:     true,
        },
        {
-               name:    "MaskedLessFloat32x4",
-               argLen:  3,
-               generic: true,
-       },
-       {
-               name:    "MaskedLessEqualFloat32x4",
-               argLen:  3,
-               generic: true,
+               name:        "MaskedMinInt16x16",
+               argLen:      3,
+               commutative: true,
+               generic:     true,
        },
        {
-               name:        "MaskedMaxFloat32x4",
+               name:        "MaskedMulHighInt16x16",
                argLen:      3,
                commutative: true,
                generic:     true,
        },
        {
-               name:        "MaskedMinFloat32x4",
+               name:        "MaskedMulLowInt16x16",
                argLen:      3,
                commutative: true,
                generic:     true,
        },
        {
-               name:        "MaskedMulFloat32x4",
+               name:        "MaskedNotEqualInt16x16",
                argLen:      3,
                commutative: true,
                generic:     true,
        },
        {
-               name:    "MaskedMulByPowOf2Float32x4",
+               name:    "MaskedPairDotProdInt16x16",
                argLen:  3,
                generic: true,
        },
        {
-               name:        "MaskedNotEqualFloat32x4",
-               argLen:      3,
-               commutative: true,
-               generic:     true,
+               name:    "MaskedPopCountInt16x16",
+               argLen:  2,
+               generic: true,
        },
        {
-               name:        "MaskedOrFloat32x4",
+               name:        "MaskedSaturatedAddInt16x16",
                argLen:      3,
                commutative: true,
                generic:     true,
        },
        {
-               name:    "MaskedSqrtFloat32x4",
-               argLen:  2,
+               name:    "MaskedSaturatedSubInt16x16",
+               argLen:  3,
                generic: true,
        },
        {
-               name:    "MaskedSubFloat32x4",
+               name:    "MaskedShiftLeftInt16x16",
                argLen:  3,
                generic: true,
        },
        {
-               name:        "MaskedXorFloat32x4",
-               argLen:      3,
-               commutative: true,
-               generic:     true,
+               name:    "MaskedShiftLeftAndFillUpperFromInt16x16",
+               argLen:  4,
+               generic: true,
        },
        {
-               name:        "MaxFloat32x4",
+               name:    "MaskedShiftRightInt16x16",
+               argLen:  3,
+               generic: true,
+       },
+       {
+               name:    "MaskedShiftRightAndFillUpperFromInt16x16",
+               argLen:  4,
+               generic: true,
+       },
+       {
+               name:    "MaskedShiftRightSignExtendedInt16x16",
+               argLen:  3,
+               generic: true,
+       },
+       {
+               name:    "MaskedSubInt16x16",
+               argLen:  3,
+               generic: true,
+       },
+       {
+               name:        "MaxInt16x16",
                argLen:      2,
                commutative: true,
                generic:     true,
        },
        {
-               name:        "MinFloat32x4",
+               name:        "MinInt16x16",
                argLen:      2,
                commutative: true,
                generic:     true,
        },
        {
-               name:        "MulFloat32x4",
+               name:        "MulHighInt16x16",
                argLen:      2,
                commutative: true,
                generic:     true,
        },
        {
-               name:    "MulByPowOf2Float32x4",
-               argLen:  2,
-               generic: true,
+               name:        "MulLowInt16x16",
+               argLen:      2,
+               commutative: true,
+               generic:     true,
        },
        {
-               name:        "NotEqualFloat32x4",
+               name:        "NotEqualInt16x16",
                argLen:      2,
                commutative: true,
                generic:     true,
        },
        {
-               name:        "OrFloat32x4",
+               name:        "OrInt16x16",
                argLen:      2,
                commutative: true,
                generic:     true,
        },
        {
-               name:    "PairwiseAddFloat32x4",
+               name:    "PairDotProdInt16x16",
                argLen:  2,
                generic: true,
        },
        {
-               name:    "PairwiseSubFloat32x4",
+               name:    "PairwiseAddInt16x16",
                argLen:  2,
                generic: true,
        },
        {
-               name:    "RoundFloat32x4",
-               argLen:  1,
-               generic: true,
-       },
-       {
-               name:    "SqrtFloat32x4",
-               argLen:  1,
-               generic: true,
-       },
-       {
-               name:    "SubFloat32x4",
+               name:    "PairwiseSubInt16x16",
                argLen:  2,
                generic: true,
        },
        {
-               name:    "TruncFloat32x4",
+               name:    "PopCountInt16x16",
                argLen:  1,
                generic: true,
        },
        {
-               name:        "XorFloat32x4",
-               argLen:      2,
-               commutative: true,
-               generic:     true,
-       },
-       {
-               name:        "AddFloat32x8",
+               name:        "SaturatedAddInt16x16",
                argLen:      2,
                commutative: true,
                generic:     true,
        },
        {
-               name:    "AddSubFloat32x8",
+               name:    "SaturatedPairwiseAddInt16x16",
                argLen:  2,
                generic: true,
        },
        {
-               name:        "AndFloat32x8",
-               argLen:      2,
-               commutative: true,
-               generic:     true,
-       },
-       {
-               name:    "AndNotFloat32x8",
+               name:    "SaturatedPairwiseSubInt16x16",
                argLen:  2,
                generic: true,
        },
        {
-               name:    "ApproximateReciprocalFloat32x8",
-               argLen:  1,
+               name:    "SaturatedSubInt16x16",
+               argLen:  2,
                generic: true,
        },
        {
-               name:    "ApproximateReciprocalOfSqrtFloat32x8",
-               argLen:  1,
+               name:    "ShiftAllLeftInt16x16",
+               argLen:  2,
                generic: true,
        },
        {
-               name:    "CeilFloat32x8",
-               argLen:  1,
+               name:    "ShiftAllRightInt16x16",
+               argLen:  2,
                generic: true,
        },
        {
-               name:    "DivFloat32x8",
+               name:    "ShiftAllRightSignExtendedInt16x16",
                argLen:  2,
                generic: true,
        },
        {
-               name:        "EqualFloat32x8",
-               argLen:      2,
-               commutative: true,
-               generic:     true,
+               name:    "ShiftLeftInt16x16",
+               argLen:  2,
+               generic: true,
        },
        {
-               name:    "FloorFloat32x8",
-               argLen:  1,
+               name:    "ShiftLeftAndFillUpperFromInt16x16",
+               argLen:  3,
                generic: true,
        },
        {
-               name:    "FusedMultiplyAddFloat32x8",
-               argLen:  3,
+               name:    "ShiftRightInt16x16",
+               argLen:  2,
                generic: true,
        },
        {
-               name:    "FusedMultiplyAddSubFloat32x8",
+               name:    "ShiftRightAndFillUpperFromInt16x16",
                argLen:  3,
                generic: true,
        },
        {
-               name:    "FusedMultiplySubAddFloat32x8",
-               argLen:  3,
+               name:    "ShiftRightSignExtendedInt16x16",
+               argLen:  2,
                generic: true,
        },
        {
-               name:    "GreaterFloat32x8",
+               name:    "SignInt16x16",
                argLen:  2,
                generic: true,
        },
        {
-               name:    "GreaterEqualFloat32x8",
+               name:    "SubInt16x16",
                argLen:  2,
                generic: true,
        },
        {
-               name:        "IsNanFloat32x8",
+               name:        "XorInt16x16",
                argLen:      2,
                commutative: true,
                generic:     true,
        },
        {
-               name:    "LessFloat32x8",
-               argLen:  2,
-               generic: true,
-       },
-       {
-               name:    "LessEqualFloat32x8",
-               argLen:  2,
+               name:    "AbsoluteInt16x32",
+               argLen:  1,
                generic: true,
        },
        {
-               name:        "MaskedAddFloat32x8",
-               argLen:      3,
+               name:        "AddInt16x32",
+               argLen:      2,
                commutative: true,
                generic:     true,
        },
        {
-               name:        "MaskedAndFloat32x8",
-               argLen:      3,
+               name:        "EqualInt16x32",
+               argLen:      2,
                commutative: true,
                generic:     true,
        },
        {
-               name:    "MaskedAndNotFloat32x8",
-               argLen:  3,
+               name:    "GreaterInt16x32",
+               argLen:  2,
                generic: true,
        },
        {
-               name:    "MaskedApproximateReciprocalFloat32x8",
+               name:    "GreaterEqualInt16x32",
                argLen:  2,
                generic: true,
        },
        {
-               name:    "MaskedApproximateReciprocalOfSqrtFloat32x8",
+               name:    "LessInt16x32",
                argLen:  2,
                generic: true,
        },
        {
-               name:    "MaskedDivFloat32x8",
-               argLen:  3,
+               name:    "LessEqualInt16x32",
+               argLen:  2,
                generic: true,
        },
        {
-               name:        "MaskedEqualFloat32x8",
+               name:    "MaskedAbsoluteInt16x32",
+               argLen:  2,
+               generic: true,
+       },
+       {
+               name:        "MaskedAddInt16x32",
                argLen:      3,
                commutative: true,
                generic:     true,
        },
        {
-               name:    "MaskedFusedMultiplyAddFloat32x8",
-               argLen:  4,
-               generic: true,
+               name:        "MaskedEqualInt16x32",
+               argLen:      3,
+               commutative: true,
+               generic:     true,
        },
        {
-               name:    "MaskedFusedMultiplyAddSubFloat32x8",
-               argLen:  4,
+               name:    "MaskedGreaterInt16x32",
+               argLen:  3,
                generic: true,
        },
        {
-               name:    "MaskedFusedMultiplySubAddFloat32x8",
-               argLen:  4,
+               name:    "MaskedGreaterEqualInt16x32",
+               argLen:  3,
                generic: true,
        },
        {
-               name:    "MaskedGreaterFloat32x8",
+               name:    "MaskedLessInt16x32",
                argLen:  3,
                generic: true,
        },
        {
-               name:    "MaskedGreaterEqualFloat32x8",
+               name:    "MaskedLessEqualInt16x32",
                argLen:  3,
                generic: true,
        },
        {
-               name:        "MaskedIsNanFloat32x8",
+               name:        "MaskedMaxInt16x32",
                argLen:      3,
                commutative: true,
                generic:     true,
        },
        {
-               name:    "MaskedLessFloat32x8",
-               argLen:  3,
-               generic: true,
-       },
-       {
-               name:    "MaskedLessEqualFloat32x8",
-               argLen:  3,
-               generic: true,
+               name:        "MaskedMinInt16x32",
+               argLen:      3,
+               commutative: true,
+               generic:     true,
        },
        {
-               name:        "MaskedMaxFloat32x8",
+               name:        "MaskedMulHighInt16x32",
                argLen:      3,
                commutative: true,
                generic:     true,
        },
        {
-               name:        "MaskedMinFloat32x8",
+               name:        "MaskedMulLowInt16x32",
                argLen:      3,
                commutative: true,
                generic:     true,
        },
        {
-               name:        "MaskedMulFloat32x8",
+               name:        "MaskedNotEqualInt16x32",
                argLen:      3,
                commutative: true,
                generic:     true,
        },
        {
-               name:    "MaskedMulByPowOf2Float32x8",
+               name:    "MaskedPairDotProdInt16x32",
                argLen:  3,
                generic: true,
        },
        {
-               name:        "MaskedNotEqualFloat32x8",
-               argLen:      3,
-               commutative: true,
-               generic:     true,
+               name:    "MaskedPopCountInt16x32",
+               argLen:  2,
+               generic: true,
        },
        {
-               name:        "MaskedOrFloat32x8",
+               name:        "MaskedSaturatedAddInt16x32",
                argLen:      3,
                commutative: true,
                generic:     true,
        },
        {
-               name:    "MaskedSqrtFloat32x8",
-               argLen:  2,
+               name:    "MaskedSaturatedSubInt16x32",
+               argLen:  3,
                generic: true,
        },
        {
-               name:    "MaskedSubFloat32x8",
+               name:    "MaskedShiftLeftInt16x32",
                argLen:  3,
                generic: true,
        },
        {
-               name:        "MaskedXorFloat32x8",
-               argLen:      3,
+               name:    "MaskedShiftLeftAndFillUpperFromInt16x32",
+               argLen:  4,
+               generic: true,
+       },
+       {
+               name:    "MaskedShiftRightInt16x32",
+               argLen:  3,
+               generic: true,
+       },
+       {
+               name:    "MaskedShiftRightAndFillUpperFromInt16x32",
+               argLen:  4,
+               generic: true,
+       },
+       {
+               name:    "MaskedShiftRightSignExtendedInt16x32",
+               argLen:  3,
+               generic: true,
+       },
+       {
+               name:    "MaskedSubInt16x32",
+               argLen:  3,
+               generic: true,
+       },
+       {
+               name:        "MaxInt16x32",
+               argLen:      2,
                commutative: true,
                generic:     true,
        },
        {
-               name:        "MaxFloat32x8",
+               name:        "MinInt16x32",
                argLen:      2,
                commutative: true,
                generic:     true,
        },
        {
-               name:        "MinFloat32x8",
+               name:        "MulHighInt16x32",
                argLen:      2,
                commutative: true,
                generic:     true,
        },
        {
-               name:        "MulFloat32x8",
+               name:        "MulLowInt16x32",
                argLen:      2,
                commutative: true,
                generic:     true,
        },
        {
-               name:    "MulByPowOf2Float32x8",
+               name:        "NotEqualInt16x32",
+               argLen:      2,
+               commutative: true,
+               generic:     true,
+       },
+       {
+               name:    "PairDotProdInt16x32",
                argLen:  2,
                generic: true,
        },
        {
-               name:        "NotEqualFloat32x8",
-               argLen:      2,
-               commutative: true,
-               generic:     true,
+               name:    "PopCountInt16x32",
+               argLen:  1,
+               generic: true,
        },
        {
-               name:        "OrFloat32x8",
+               name:        "SaturatedAddInt16x32",
                argLen:      2,
                commutative: true,
                generic:     true,
        },
        {
-               name:    "PairwiseAddFloat32x8",
+               name:    "SaturatedSubInt16x32",
                argLen:  2,
                generic: true,
        },
        {
-               name:    "PairwiseSubFloat32x8",
+               name:    "ShiftLeftInt16x32",
                argLen:  2,
                generic: true,
        },
        {
-               name:    "RoundFloat32x8",
-               argLen:  1,
+               name:    "ShiftLeftAndFillUpperFromInt16x32",
+               argLen:  3,
                generic: true,
        },
        {
-               name:    "SqrtFloat32x8",
-               argLen:  1,
+               name:    "ShiftRightInt16x32",
+               argLen:  2,
                generic: true,
        },
        {
-               name:    "SubFloat32x8",
+               name:    "ShiftRightAndFillUpperFromInt16x32",
+               argLen:  3,
+               generic: true,
+       },
+       {
+               name:    "ShiftRightSignExtendedInt16x32",
                argLen:  2,
                generic: true,
        },
        {
-               name:    "TruncFloat32x8",
+               name:    "SubInt16x32",
+               argLen:  2,
+               generic: true,
+       },
+       {
+               name:    "AbsoluteInt16x8",
                argLen:  1,
                generic: true,
        },
        {
-               name:        "XorFloat32x8",
+               name:        "AddInt16x8",
                argLen:      2,
                commutative: true,
                generic:     true,
        },
        {
-               name:        "AddFloat64x2",
+               name:        "AndInt16x8",
                argLen:      2,
                commutative: true,
                generic:     true,
        },
        {
-               name:    "AddSubFloat64x2",
+               name:    "AndNotInt16x8",
                argLen:  2,
                generic: true,
        },
        {
-               name:        "AndFloat64x2",
+               name:        "EqualInt16x8",
                argLen:      2,
                commutative: true,
                generic:     true,
        },
        {
-               name:    "AndNotFloat64x2",
+               name:    "GreaterInt16x8",
                argLen:  2,
                generic: true,
        },
        {
-               name:    "ApproximateReciprocalFloat64x2",
-               argLen:  1,
+               name:    "GreaterEqualInt16x8",
+               argLen:  2,
                generic: true,
        },
        {
-               name:    "ApproximateReciprocalOfSqrtFloat64x2",
-               argLen:  1,
+               name:    "LessInt16x8",
+               argLen:  2,
                generic: true,
        },
        {
-               name:    "CeilFloat64x2",
-               argLen:  1,
+               name:    "LessEqualInt16x8",
+               argLen:  2,
                generic: true,
        },
        {
-               name:    "DivFloat64x2",
+               name:    "MaskedAbsoluteInt16x8",
                argLen:  2,
                generic: true,
        },
        {
-               name:        "DotProdBroadcastFloat64x2",
-               argLen:      2,
+               name:        "MaskedAddInt16x8",
+               argLen:      3,
                commutative: true,
                generic:     true,
        },
        {
-               name:        "EqualFloat64x2",
-               argLen:      2,
+               name:        "MaskedEqualInt16x8",
+               argLen:      3,
                commutative: true,
                generic:     true,
        },
        {
-               name:    "FloorFloat64x2",
-               argLen:  1,
-               generic: true,
-       },
-       {
-               name:    "FusedMultiplyAddFloat64x2",
+               name:    "MaskedGreaterInt16x8",
                argLen:  3,
                generic: true,
        },
        {
-               name:    "FusedMultiplyAddSubFloat64x2",
+               name:    "MaskedGreaterEqualInt16x8",
                argLen:  3,
                generic: true,
        },
        {
-               name:    "FusedMultiplySubAddFloat64x2",
+               name:    "MaskedLessInt16x8",
                argLen:  3,
                generic: true,
        },
        {
-               name:    "GreaterFloat64x2",
-               argLen:  2,
-               generic: true,
-       },
-       {
-               name:    "GreaterEqualFloat64x2",
-               argLen:  2,
+               name:    "MaskedLessEqualInt16x8",
+               argLen:  3,
                generic: true,
        },
        {
-               name:        "IsNanFloat64x2",
-               argLen:      2,
+               name:        "MaskedMaxInt16x8",
+               argLen:      3,
                commutative: true,
                generic:     true,
        },
        {
-               name:    "LessFloat64x2",
-               argLen:  2,
-               generic: true,
+               name:        "MaskedMinInt16x8",
+               argLen:      3,
+               commutative: true,
+               generic:     true,
        },
        {
-               name:    "LessEqualFloat64x2",
-               argLen:  2,
-               generic: true,
+               name:        "MaskedMulHighInt16x8",
+               argLen:      3,
+               commutative: true,
+               generic:     true,
        },
        {
-               name:        "MaskedAddFloat64x2",
+               name:        "MaskedMulLowInt16x8",
                argLen:      3,
                commutative: true,
                generic:     true,
        },
        {
-               name:        "MaskedAndFloat64x2",
+               name:        "MaskedNotEqualInt16x8",
                argLen:      3,
                commutative: true,
                generic:     true,
        },
        {
-               name:    "MaskedAndNotFloat64x2",
+               name:    "MaskedPairDotProdInt16x8",
                argLen:  3,
                generic: true,
        },
        {
-               name:    "MaskedApproximateReciprocalFloat64x2",
+               name:    "MaskedPopCountInt16x8",
                argLen:  2,
                generic: true,
        },
        {
-               name:    "MaskedApproximateReciprocalOfSqrtFloat64x2",
-               argLen:  2,
-               generic: true,
+               name:        "MaskedSaturatedAddInt16x8",
+               argLen:      3,
+               commutative: true,
+               generic:     true,
        },
        {
-               name:    "MaskedDivFloat64x2",
+               name:    "MaskedSaturatedSubInt16x8",
                argLen:  3,
                generic: true,
        },
        {
-               name:        "MaskedEqualFloat64x2",
-               argLen:      3,
-               commutative: true,
-               generic:     true,
+               name:    "MaskedShiftLeftInt16x8",
+               argLen:  3,
+               generic: true,
        },
        {
-               name:    "MaskedFusedMultiplyAddFloat64x2",
+               name:    "MaskedShiftLeftAndFillUpperFromInt16x8",
                argLen:  4,
                generic: true,
        },
        {
-               name:    "MaskedFusedMultiplyAddSubFloat64x2",
-               argLen:  4,
+               name:    "MaskedShiftRightInt16x8",
+               argLen:  3,
                generic: true,
        },
        {
-               name:    "MaskedFusedMultiplySubAddFloat64x2",
+               name:    "MaskedShiftRightAndFillUpperFromInt16x8",
                argLen:  4,
                generic: true,
        },
        {
-               name:    "MaskedGreaterFloat64x2",
+               name:    "MaskedShiftRightSignExtendedInt16x8",
                argLen:  3,
                generic: true,
        },
        {
-               name:    "MaskedGreaterEqualFloat64x2",
+               name:    "MaskedSubInt16x8",
                argLen:  3,
                generic: true,
        },
        {
-               name:        "MaskedIsNanFloat64x2",
-               argLen:      3,
+               name:        "MaxInt16x8",
+               argLen:      2,
                commutative: true,
                generic:     true,
        },
        {
-               name:    "MaskedLessFloat64x2",
-               argLen:  3,
-               generic: true,
-       },
-       {
-               name:    "MaskedLessEqualFloat64x2",
-               argLen:  3,
-               generic: true,
-       },
-       {
-               name:        "MaskedMaxFloat64x2",
-               argLen:      3,
+               name:        "MinInt16x8",
+               argLen:      2,
                commutative: true,
                generic:     true,
        },
        {
-               name:        "MaskedMinFloat64x2",
-               argLen:      3,
+               name:        "MulHighInt16x8",
+               argLen:      2,
                commutative: true,
                generic:     true,
        },
        {
-               name:        "MaskedMulFloat64x2",
-               argLen:      3,
+               name:        "MulLowInt16x8",
+               argLen:      2,
                commutative: true,
                generic:     true,
        },
        {
-               name:    "MaskedMulByPowOf2Float64x2",
-               argLen:  3,
-               generic: true,
+               name:        "NotEqualInt16x8",
+               argLen:      2,
+               commutative: true,
+               generic:     true,
        },
        {
-               name:        "MaskedNotEqualFloat64x2",
-               argLen:      3,
+               name:        "OrInt16x8",
+               argLen:      2,
                commutative: true,
                generic:     true,
        },
        {
-               name:        "MaskedOrFloat64x2",
-               argLen:      3,
-               commutative: true,
-               generic:     true,
+               name:    "PairDotProdInt16x8",
+               argLen:  2,
+               generic: true,
        },
        {
-               name:    "MaskedSqrtFloat64x2",
+               name:    "PairwiseAddInt16x8",
                argLen:  2,
                generic: true,
        },
        {
-               name:    "MaskedSubFloat64x2",
-               argLen:  3,
+               name:    "PairwiseSubInt16x8",
+               argLen:  2,
                generic: true,
        },
        {
-               name:        "MaskedXorFloat64x2",
-               argLen:      3,
-               commutative: true,
-               generic:     true,
+               name:    "PopCountInt16x8",
+               argLen:  1,
+               generic: true,
        },
        {
-               name:        "MaxFloat64x2",
+               name:        "SaturatedAddInt16x8",
                argLen:      2,
                commutative: true,
                generic:     true,
        },
        {
-               name:        "MinFloat64x2",
-               argLen:      2,
-               commutative: true,
-               generic:     true,
+               name:    "SaturatedPairwiseAddInt16x8",
+               argLen:  2,
+               generic: true,
        },
        {
-               name:        "MulFloat64x2",
-               argLen:      2,
-               commutative: true,
-               generic:     true,
+               name:    "SaturatedPairwiseSubInt16x8",
+               argLen:  2,
+               generic: true,
        },
        {
-               name:    "MulByPowOf2Float64x2",
+               name:    "SaturatedSubInt16x8",
                argLen:  2,
                generic: true,
        },
        {
-               name:        "NotEqualFloat64x2",
-               argLen:      2,
-               commutative: true,
-               generic:     true,
+               name:    "ShiftAllLeftInt16x8",
+               argLen:  2,
+               generic: true,
        },
        {
-               name:        "OrFloat64x2",
-               argLen:      2,
-               commutative: true,
-               generic:     true,
+               name:    "ShiftAllRightInt16x8",
+               argLen:  2,
+               generic: true,
        },
        {
-               name:    "PairwiseAddFloat64x2",
+               name:    "ShiftAllRightSignExtendedInt16x8",
                argLen:  2,
                generic: true,
        },
        {
-               name:    "PairwiseSubFloat64x2",
+               name:    "ShiftLeftInt16x8",
                argLen:  2,
                generic: true,
        },
        {
-               name:    "RoundFloat64x2",
-               argLen:  1,
+               name:    "ShiftLeftAndFillUpperFromInt16x8",
+               argLen:  3,
                generic: true,
        },
        {
-               name:    "SqrtFloat64x2",
-               argLen:  1,
+               name:    "ShiftRightInt16x8",
+               argLen:  2,
                generic: true,
        },
        {
-               name:    "SubFloat64x2",
+               name:    "ShiftRightAndFillUpperFromInt16x8",
+               argLen:  3,
+               generic: true,
+       },
+       {
+               name:    "ShiftRightSignExtendedInt16x8",
                argLen:  2,
                generic: true,
        },
        {
-               name:    "TruncFloat64x2",
+               name:    "SignInt16x8",
+               argLen:  2,
+               generic: true,
+       },
+       {
+               name:    "SubInt16x8",
+               argLen:  2,
+               generic: true,
+       },
+       {
+               name:        "XorInt16x8",
+               argLen:      2,
+               commutative: true,
+               generic:     true,
+       },
+       {
+               name:    "AbsoluteInt32x16",
                argLen:  1,
                generic: true,
        },
        {
-               name:        "XorFloat64x2",
+               name:        "AddInt32x16",
                argLen:      2,
                commutative: true,
                generic:     true,
        },
        {
-               name:        "AddFloat64x4",
+               name:        "AndInt32x16",
                argLen:      2,
                commutative: true,
                generic:     true,
        },
        {
-               name:    "AddSubFloat64x4",
+               name:    "AndNotInt32x16",
                argLen:  2,
                generic: true,
        },
        {
-               name:        "AndFloat64x4",
+               name:        "EqualInt32x16",
                argLen:      2,
                commutative: true,
                generic:     true,
        },
        {
-               name:    "AndNotFloat64x4",
+               name:    "GreaterInt32x16",
                argLen:  2,
                generic: true,
        },
        {
-               name:    "ApproximateReciprocalFloat64x4",
-               argLen:  1,
+               name:    "GreaterEqualInt32x16",
+               argLen:  2,
                generic: true,
        },
        {
-               name:    "ApproximateReciprocalOfSqrtFloat64x4",
-               argLen:  1,
+               name:    "LessInt32x16",
+               argLen:  2,
                generic: true,
        },
        {
-               name:    "CeilFloat64x4",
-               argLen:  1,
+               name:    "LessEqualInt32x16",
+               argLen:  2,
                generic: true,
        },
        {
-               name:    "DivFloat64x4",
+               name:    "MaskedAbsoluteInt32x16",
                argLen:  2,
                generic: true,
        },
        {
-               name:        "EqualFloat64x4",
-               argLen:      2,
+               name:        "MaskedAddInt32x16",
+               argLen:      3,
                commutative: true,
                generic:     true,
        },
        {
-               name:    "FloorFloat64x4",
-               argLen:  1,
-               generic: true,
+               name:        "MaskedAndInt32x16",
+               argLen:      3,
+               commutative: true,
+               generic:     true,
        },
        {
-               name:    "FusedMultiplyAddFloat64x4",
+               name:    "MaskedAndNotInt32x16",
                argLen:  3,
                generic: true,
        },
        {
-               name:    "FusedMultiplyAddSubFloat64x4",
+               name:        "MaskedEqualInt32x16",
+               argLen:      3,
+               commutative: true,
+               generic:     true,
+       },
+       {
+               name:    "MaskedGreaterInt32x16",
                argLen:  3,
                generic: true,
        },
        {
-               name:    "FusedMultiplySubAddFloat64x4",
+               name:    "MaskedGreaterEqualInt32x16",
                argLen:  3,
                generic: true,
        },
        {
-               name:    "GreaterFloat64x4",
-               argLen:  2,
+               name:    "MaskedLessInt32x16",
+               argLen:  3,
                generic: true,
        },
        {
-               name:    "GreaterEqualFloat64x4",
-               argLen:  2,
+               name:    "MaskedLessEqualInt32x16",
+               argLen:  3,
                generic: true,
        },
        {
-               name:        "IsNanFloat64x4",
-               argLen:      2,
+               name:        "MaskedMaxInt32x16",
+               argLen:      3,
                commutative: true,
                generic:     true,
        },
        {
-               name:    "LessFloat64x4",
-               argLen:  2,
-               generic: true,
+               name:        "MaskedMinInt32x16",
+               argLen:      3,
+               commutative: true,
+               generic:     true,
        },
        {
-               name:    "LessEqualFloat64x4",
-               argLen:  2,
-               generic: true,
+               name:        "MaskedMulLowInt32x16",
+               argLen:      3,
+               commutative: true,
+               generic:     true,
        },
        {
-               name:        "MaskedAddFloat64x4",
+               name:        "MaskedNotEqualInt32x16",
                argLen:      3,
                commutative: true,
                generic:     true,
        },
        {
-               name:        "MaskedAndFloat64x4",
+               name:        "MaskedOrInt32x16",
                argLen:      3,
                commutative: true,
                generic:     true,
        },
        {
-               name:    "MaskedAndNotFloat64x4",
-               argLen:  3,
+               name:    "MaskedPairDotProdAccumulateInt32x16",
+               argLen:  4,
                generic: true,
        },
        {
-               name:    "MaskedApproximateReciprocalFloat64x4",
+               name:    "MaskedPopCountInt32x16",
                argLen:  2,
                generic: true,
        },
        {
-               name:    "MaskedApproximateReciprocalOfSqrtFloat64x4",
-               argLen:  2,
+               name:    "MaskedRotateLeftInt32x16",
+               argLen:  3,
                generic: true,
        },
        {
-               name:    "MaskedDivFloat64x4",
+               name:    "MaskedRotateRightInt32x16",
                argLen:  3,
                generic: true,
        },
        {
-               name:        "MaskedEqualFloat64x4",
-               argLen:      3,
-               commutative: true,
-               generic:     true,
+               name:    "MaskedSaturatedPairDotProdAccumulateInt32x16",
+               argLen:  4,
+               generic: true,
        },
        {
-               name:    "MaskedFusedMultiplyAddFloat64x4",
+               name:    "MaskedSaturatedUnsignedSignedQuadDotProdAccumulateInt32x16",
                argLen:  4,
                generic: true,
        },
        {
-               name:    "MaskedFusedMultiplyAddSubFloat64x4",
-               argLen:  4,
+               name:    "MaskedShiftLeftInt32x16",
+               argLen:  3,
                generic: true,
        },
        {
-               name:    "MaskedFusedMultiplySubAddFloat64x4",
+               name:    "MaskedShiftLeftAndFillUpperFromInt32x16",
                argLen:  4,
                generic: true,
        },
        {
-               name:    "MaskedGreaterFloat64x4",
+               name:    "MaskedShiftRightInt32x16",
                argLen:  3,
                generic: true,
        },
        {
-               name:    "MaskedGreaterEqualFloat64x4",
-               argLen:  3,
+               name:    "MaskedShiftRightAndFillUpperFromInt32x16",
+               argLen:  4,
                generic: true,
        },
        {
-               name:        "MaskedIsNanFloat64x4",
-               argLen:      3,
-               commutative: true,
-               generic:     true,
+               name:    "MaskedShiftRightSignExtendedInt32x16",
+               argLen:  3,
+               generic: true,
        },
        {
-               name:    "MaskedLessFloat64x4",
+               name:    "MaskedSubInt32x16",
                argLen:  3,
                generic: true,
        },
        {
-               name:    "MaskedLessEqualFloat64x4",
-               argLen:  3,
+               name:    "MaskedUnsignedSignedQuadDotProdAccumulateInt32x16",
+               argLen:  4,
                generic: true,
        },
        {
-               name:        "MaskedMaxFloat64x4",
+               name:        "MaskedXorInt32x16",
                argLen:      3,
                commutative: true,
                generic:     true,
        },
        {
-               name:        "MaskedMinFloat64x4",
-               argLen:      3,
+               name:        "MaxInt32x16",
+               argLen:      2,
                commutative: true,
                generic:     true,
        },
        {
-               name:        "MaskedMulFloat64x4",
-               argLen:      3,
+               name:        "MinInt32x16",
+               argLen:      2,
                commutative: true,
                generic:     true,
        },
        {
-               name:    "MaskedMulByPowOf2Float64x4",
-               argLen:  3,
-               generic: true,
+               name:        "MulLowInt32x16",
+               argLen:      2,
+               commutative: true,
+               generic:     true,
        },
        {
-               name:        "MaskedNotEqualFloat64x4",
-               argLen:      3,
+               name:        "NotEqualInt32x16",
+               argLen:      2,
                commutative: true,
                generic:     true,
        },
        {
-               name:        "MaskedOrFloat64x4",
-               argLen:      3,
+               name:        "OrInt32x16",
+               argLen:      2,
                commutative: true,
                generic:     true,
        },
        {
-               name:    "MaskedSqrtFloat64x4",
-               argLen:  2,
+               name:    "PairDotProdAccumulateInt32x16",
+               argLen:  3,
                generic: true,
        },
        {
-               name:    "MaskedSubFloat64x4",
-               argLen:  3,
+               name:    "PopCountInt32x16",
+               argLen:  1,
                generic: true,
        },
        {
-               name:        "MaskedXorFloat64x4",
-               argLen:      3,
-               commutative: true,
-               generic:     true,
+               name:    "RotateLeftInt32x16",
+               argLen:  2,
+               generic: true,
        },
        {
-               name:        "MaxFloat64x4",
-               argLen:      2,
-               commutative: true,
-               generic:     true,
+               name:    "RotateRightInt32x16",
+               argLen:  2,
+               generic: true,
        },
        {
-               name:        "MinFloat64x4",
-               argLen:      2,
-               commutative: true,
-               generic:     true,
+               name:    "SaturatedPairDotProdAccumulateInt32x16",
+               argLen:  3,
+               generic: true,
        },
        {
-               name:        "MulFloat64x4",
-               argLen:      2,
-               commutative: true,
-               generic:     true,
+               name:    "SaturatedUnsignedSignedQuadDotProdAccumulateInt32x16",
+               argLen:  3,
+               generic: true,
        },
        {
-               name:    "MulByPowOf2Float64x4",
+               name:    "ShiftLeftInt32x16",
                argLen:  2,
                generic: true,
        },
        {
-               name:        "NotEqualFloat64x4",
-               argLen:      2,
-               commutative: true,
-               generic:     true,
+               name:    "ShiftLeftAndFillUpperFromInt32x16",
+               argLen:  3,
+               generic: true,
        },
        {
-               name:        "OrFloat64x4",
-               argLen:      2,
-               commutative: true,
-               generic:     true,
+               name:    "ShiftRightInt32x16",
+               argLen:  2,
+               generic: true,
        },
        {
-               name:    "PairwiseAddFloat64x4",
-               argLen:  2,
+               name:    "ShiftRightAndFillUpperFromInt32x16",
+               argLen:  3,
                generic: true,
        },
        {
-               name:    "PairwiseSubFloat64x4",
+               name:    "ShiftRightSignExtendedInt32x16",
                argLen:  2,
                generic: true,
        },
        {
-               name:    "RoundFloat64x4",
-               argLen:  1,
+               name:    "SubInt32x16",
+               argLen:  2,
                generic: true,
        },
        {
-               name:    "SqrtFloat64x4",
-               argLen:  1,
+               name:    "UnsignedSignedQuadDotProdAccumulateInt32x16",
+               argLen:  3,
                generic: true,
        },
        {
-               name:    "SubFloat64x4",
-               argLen:  2,
-               generic: true,
+               name:        "XorInt32x16",
+               argLen:      2,
+               commutative: true,
+               generic:     true,
        },
        {
-               name:    "TruncFloat64x4",
+               name:    "AbsoluteInt32x4",
                argLen:  1,
                generic: true,
        },
        {
-               name:        "XorFloat64x4",
+               name:        "AddInt32x4",
                argLen:      2,
                commutative: true,
                generic:     true,
        },
        {
-               name:        "AddFloat64x8",
+               name:        "AndInt32x4",
                argLen:      2,
                commutative: true,
                generic:     true,
        },
        {
-               name:        "AndFloat64x8",
+               name:    "AndNotInt32x4",
+               argLen:  2,
+               generic: true,
+       },
+       {
+               name:        "EqualInt32x4",
                argLen:      2,
                commutative: true,
                generic:     true,
        },
        {
-               name:    "AndNotFloat64x8",
+               name:    "GreaterInt32x4",
                argLen:  2,
                generic: true,
        },
        {
-               name:    "ApproximateReciprocalFloat64x8",
-               argLen:  1,
+               name:    "GreaterEqualInt32x4",
+               argLen:  2,
                generic: true,
        },
        {
-               name:    "ApproximateReciprocalOfSqrtFloat64x8",
-               argLen:  1,
+               name:    "LessInt32x4",
+               argLen:  2,
                generic: true,
        },
        {
-               name:    "DivFloat64x8",
+               name:    "LessEqualInt32x4",
                argLen:  2,
                generic: true,
        },
        {
-               name:        "EqualFloat64x8",
-               argLen:      2,
+               name:    "MaskedAbsoluteInt32x4",
+               argLen:  2,
+               generic: true,
+       },
+       {
+               name:        "MaskedAddInt32x4",
+               argLen:      3,
                commutative: true,
                generic:     true,
        },
        {
-               name:    "FusedMultiplyAddFloat64x8",
+               name:        "MaskedAndInt32x4",
+               argLen:      3,
+               commutative: true,
+               generic:     true,
+       },
+       {
+               name:    "MaskedAndNotInt32x4",
                argLen:  3,
                generic: true,
        },
        {
-               name:    "FusedMultiplyAddSubFloat64x8",
+               name:        "MaskedEqualInt32x4",
+               argLen:      3,
+               commutative: true,
+               generic:     true,
+       },
+       {
+               name:    "MaskedGreaterInt32x4",
                argLen:  3,
                generic: true,
        },
        {
-               name:    "FusedMultiplySubAddFloat64x8",
+               name:    "MaskedGreaterEqualInt32x4",
                argLen:  3,
                generic: true,
        },
        {
-               name:    "GreaterFloat64x8",
-               argLen:  2,
+               name:    "MaskedLessInt32x4",
+               argLen:  3,
                generic: true,
        },
        {
-               name:    "GreaterEqualFloat64x8",
-               argLen:  2,
+               name:    "MaskedLessEqualInt32x4",
+               argLen:  3,
                generic: true,
        },
        {
-               name:        "IsNanFloat64x8",
-               argLen:      2,
+               name:        "MaskedMaxInt32x4",
+               argLen:      3,
                commutative: true,
                generic:     true,
        },
        {
-               name:    "LessFloat64x8",
-               argLen:  2,
-               generic: true,
+               name:        "MaskedMinInt32x4",
+               argLen:      3,
+               commutative: true,
+               generic:     true,
        },
        {
-               name:    "LessEqualFloat64x8",
-               argLen:  2,
-               generic: true,
+               name:        "MaskedMulLowInt32x4",
+               argLen:      3,
+               commutative: true,
+               generic:     true,
        },
        {
-               name:        "MaskedAddFloat64x8",
+               name:        "MaskedNotEqualInt32x4",
                argLen:      3,
                commutative: true,
                generic:     true,
        },
        {
-               name:        "MaskedAndFloat64x8",
+               name:        "MaskedOrInt32x4",
                argLen:      3,
                commutative: true,
                generic:     true,
        },
        {
-               name:    "MaskedAndNotFloat64x8",
-               argLen:  3,
+               name:    "MaskedPairDotProdAccumulateInt32x4",
+               argLen:  4,
                generic: true,
        },
        {
-               name:    "MaskedApproximateReciprocalFloat64x8",
+               name:    "MaskedPopCountInt32x4",
                argLen:  2,
                generic: true,
        },
        {
-               name:    "MaskedApproximateReciprocalOfSqrtFloat64x8",
-               argLen:  2,
+               name:    "MaskedRotateLeftInt32x4",
+               argLen:  3,
                generic: true,
        },
        {
-               name:    "MaskedDivFloat64x8",
+               name:    "MaskedRotateRightInt32x4",
                argLen:  3,
                generic: true,
        },
        {
-               name:        "MaskedEqualFloat64x8",
-               argLen:      3,
-               commutative: true,
-               generic:     true,
+               name:    "MaskedSaturatedPairDotProdAccumulateInt32x4",
+               argLen:  4,
+               generic: true,
        },
        {
-               name:    "MaskedFusedMultiplyAddFloat64x8",
+               name:    "MaskedSaturatedUnsignedSignedQuadDotProdAccumulateInt32x4",
                argLen:  4,
                generic: true,
        },
        {
-               name:    "MaskedFusedMultiplyAddSubFloat64x8",
-               argLen:  4,
+               name:    "MaskedShiftLeftInt32x4",
+               argLen:  3,
                generic: true,
        },
        {
-               name:    "MaskedFusedMultiplySubAddFloat64x8",
+               name:    "MaskedShiftLeftAndFillUpperFromInt32x4",
                argLen:  4,
                generic: true,
        },
        {
-               name:    "MaskedGreaterFloat64x8",
+               name:    "MaskedShiftRightInt32x4",
                argLen:  3,
                generic: true,
        },
        {
-               name:    "MaskedGreaterEqualFloat64x8",
-               argLen:  3,
+               name:    "MaskedShiftRightAndFillUpperFromInt32x4",
+               argLen:  4,
                generic: true,
        },
        {
-               name:        "MaskedIsNanFloat64x8",
-               argLen:      3,
-               commutative: true,
-               generic:     true,
+               name:    "MaskedShiftRightSignExtendedInt32x4",
+               argLen:  3,
+               generic: true,
        },
        {
-               name:    "MaskedLessFloat64x8",
+               name:    "MaskedSubInt32x4",
                argLen:  3,
                generic: true,
        },
        {
-               name:    "MaskedLessEqualFloat64x8",
-               argLen:  3,
+               name:    "MaskedUnsignedSignedQuadDotProdAccumulateInt32x4",
+               argLen:  4,
                generic: true,
        },
        {
-               name:        "MaskedMaxFloat64x8",
+               name:        "MaskedXorInt32x4",
                argLen:      3,
                commutative: true,
                generic:     true,
        },
        {
-               name:        "MaskedMinFloat64x8",
-               argLen:      3,
+               name:        "MaxInt32x4",
+               argLen:      2,
                commutative: true,
                generic:     true,
        },
        {
-               name:        "MaskedMulFloat64x8",
-               argLen:      3,
+               name:        "MinInt32x4",
+               argLen:      2,
                commutative: true,
                generic:     true,
        },
        {
-               name:    "MaskedMulByPowOf2Float64x8",
-               argLen:  3,
-               generic: true,
+               name:        "MulEvenWidenInt32x4",
+               argLen:      2,
+               commutative: true,
+               generic:     true,
        },
        {
-               name:        "MaskedNotEqualFloat64x8",
-               argLen:      3,
+               name:        "MulLowInt32x4",
+               argLen:      2,
                commutative: true,
                generic:     true,
        },
        {
-               name:        "MaskedOrFloat64x8",
-               argLen:      3,
+               name:        "NotEqualInt32x4",
+               argLen:      2,
                commutative: true,
                generic:     true,
        },
        {
-               name:    "MaskedSqrtFloat64x8",
+               name:        "OrInt32x4",
+               argLen:      2,
+               commutative: true,
+               generic:     true,
+       },
+       {
+               name:    "PairDotProdAccumulateInt32x4",
+               argLen:  3,
+               generic: true,
+       },
+       {
+               name:    "PairwiseAddInt32x4",
                argLen:  2,
                generic: true,
        },
        {
-               name:    "MaskedSubFloat64x8",
+               name:    "PairwiseSubInt32x4",
+               argLen:  2,
+               generic: true,
+       },
+       {
+               name:    "PopCountInt32x4",
+               argLen:  1,
+               generic: true,
+       },
+       {
+               name:    "RotateLeftInt32x4",
+               argLen:  2,
+               generic: true,
+       },
+       {
+               name:    "RotateRightInt32x4",
+               argLen:  2,
+               generic: true,
+       },
+       {
+               name:    "SaturatedPairDotProdAccumulateInt32x4",
                argLen:  3,
                generic: true,
        },
        {
-               name:        "MaskedXorFloat64x8",
-               argLen:      3,
-               commutative: true,
-               generic:     true,
+               name:    "SaturatedUnsignedSignedQuadDotProdAccumulateInt32x4",
+               argLen:  3,
+               generic: true,
        },
        {
-               name:        "MaxFloat64x8",
-               argLen:      2,
-               commutative: true,
-               generic:     true,
+               name:    "ShiftAllLeftInt32x4",
+               argLen:  2,
+               generic: true,
        },
        {
-               name:        "MinFloat64x8",
-               argLen:      2,
-               commutative: true,
-               generic:     true,
+               name:    "ShiftAllRightInt32x4",
+               argLen:  2,
+               generic: true,
        },
        {
-               name:        "MulFloat64x8",
-               argLen:      2,
-               commutative: true,
-               generic:     true,
+               name:    "ShiftAllRightSignExtendedInt32x4",
+               argLen:  2,
+               generic: true,
        },
        {
-               name:    "MulByPowOf2Float64x8",
+               name:    "ShiftLeftInt32x4",
                argLen:  2,
                generic: true,
        },
        {
-               name:        "NotEqualFloat64x8",
-               argLen:      2,
-               commutative: true,
-               generic:     true,
+               name:    "ShiftLeftAndFillUpperFromInt32x4",
+               argLen:  3,
+               generic: true,
        },
        {
-               name:        "OrFloat64x8",
-               argLen:      2,
-               commutative: true,
-               generic:     true,
+               name:    "ShiftRightInt32x4",
+               argLen:  2,
+               generic: true,
+       },
+       {
+               name:    "ShiftRightAndFillUpperFromInt32x4",
+               argLen:  3,
+               generic: true,
+       },
+       {
+               name:    "ShiftRightSignExtendedInt32x4",
+               argLen:  2,
+               generic: true,
        },
        {
-               name:    "SqrtFloat64x8",
-               argLen:  1,
+               name:    "SignInt32x4",
+               argLen:  2,
                generic: true,
        },
        {
-               name:    "SubFloat64x8",
+               name:    "SubInt32x4",
                argLen:  2,
                generic: true,
        },
        {
-               name:        "XorFloat64x8",
+               name:    "UnsignedSignedQuadDotProdAccumulateInt32x4",
+               argLen:  3,
+               generic: true,
+       },
+       {
+               name:        "XorInt32x4",
                argLen:      2,
                commutative: true,
                generic:     true,
        },
        {
-               name:    "AbsoluteInt16x16",
+               name:    "AbsoluteInt32x8",
                argLen:  1,
                generic: true,
        },
        {
-               name:        "AddInt16x16",
+               name:        "AddInt32x8",
                argLen:      2,
                commutative: true,
                generic:     true,
        },
        {
-               name:        "AndInt16x16",
+               name:        "AndInt32x8",
                argLen:      2,
                commutative: true,
                generic:     true,
        },
        {
-               name:    "AndNotInt16x16",
+               name:    "AndNotInt32x8",
                argLen:  2,
                generic: true,
        },
        {
-               name:        "EqualInt16x16",
+               name:        "EqualInt32x8",
                argLen:      2,
                commutative: true,
                generic:     true,
        },
        {
-               name:    "GreaterInt16x16",
+               name:    "GreaterInt32x8",
                argLen:  2,
                generic: true,
        },
        {
-               name:    "GreaterEqualInt16x16",
+               name:    "GreaterEqualInt32x8",
                argLen:  2,
                generic: true,
        },
        {
-               name:    "LessInt16x16",
+               name:    "LessInt32x8",
                argLen:  2,
                generic: true,
        },
        {
-               name:    "LessEqualInt16x16",
+               name:    "LessEqualInt32x8",
                argLen:  2,
                generic: true,
        },
        {
-               name:    "MaskedAbsoluteInt16x16",
+               name:    "MaskedAbsoluteInt32x8",
                argLen:  2,
                generic: true,
        },
        {
-               name:        "MaskedAddInt16x16",
+               name:        "MaskedAddInt32x8",
                argLen:      3,
                commutative: true,
                generic:     true,
        },
        {
-               name:        "MaskedEqualInt16x16",
+               name:        "MaskedAndInt32x8",
                argLen:      3,
                commutative: true,
                generic:     true,
        },
        {
-               name:    "MaskedGreaterInt16x16",
+               name:    "MaskedAndNotInt32x8",
                argLen:  3,
                generic: true,
        },
        {
-               name:    "MaskedGreaterEqualInt16x16",
+               name:        "MaskedEqualInt32x8",
+               argLen:      3,
+               commutative: true,
+               generic:     true,
+       },
+       {
+               name:    "MaskedGreaterInt32x8",
                argLen:  3,
                generic: true,
        },
        {
-               name:    "MaskedLessInt16x16",
+               name:    "MaskedGreaterEqualInt32x8",
                argLen:  3,
                generic: true,
        },
        {
-               name:    "MaskedLessEqualInt16x16",
+               name:    "MaskedLessInt32x8",
                argLen:  3,
                generic: true,
        },
        {
-               name:        "MaskedMaxInt16x16",
+               name:    "MaskedLessEqualInt32x8",
+               argLen:  3,
+               generic: true,
+       },
+       {
+               name:        "MaskedMaxInt32x8",
                argLen:      3,
                commutative: true,
                generic:     true,
        },
        {
-               name:        "MaskedMinInt16x16",
+               name:        "MaskedMinInt32x8",
                argLen:      3,
                commutative: true,
                generic:     true,
        },
        {
-               name:        "MaskedMulHighInt16x16",
+               name:        "MaskedMulLowInt32x8",
                argLen:      3,
                commutative: true,
                generic:     true,
        },
        {
-               name:        "MaskedMulLowInt16x16",
+               name:        "MaskedNotEqualInt32x8",
                argLen:      3,
                commutative: true,
                generic:     true,
        },
        {
-               name:        "MaskedNotEqualInt16x16",
+               name:        "MaskedOrInt32x8",
                argLen:      3,
                commutative: true,
                generic:     true,
        },
        {
-               name:    "MaskedPairDotProdInt16x16",
-               argLen:  3,
+               name:    "MaskedPairDotProdAccumulateInt32x8",
+               argLen:  4,
                generic: true,
        },
        {
-               name:    "MaskedPopCountInt16x16",
+               name:    "MaskedPopCountInt32x8",
                argLen:  2,
                generic: true,
        },
        {
-               name:        "MaskedSaturatedAddInt16x16",
-               argLen:      3,
-               commutative: true,
-               generic:     true,
+               name:    "MaskedRotateLeftInt32x8",
+               argLen:  3,
+               generic: true,
        },
        {
-               name:    "MaskedSaturatedSubInt16x16",
+               name:    "MaskedRotateRightInt32x8",
                argLen:  3,
                generic: true,
        },
        {
-               name:    "MaskedSubInt16x16",
+               name:    "MaskedSaturatedPairDotProdAccumulateInt32x8",
+               argLen:  4,
+               generic: true,
+       },
+       {
+               name:    "MaskedSaturatedUnsignedSignedQuadDotProdAccumulateInt32x8",
+               argLen:  4,
+               generic: true,
+       },
+       {
+               name:    "MaskedShiftLeftInt32x8",
                argLen:  3,
                generic: true,
        },
        {
-               name:        "MaxInt16x16",
+               name:    "MaskedShiftLeftAndFillUpperFromInt32x8",
+               argLen:  4,
+               generic: true,
+       },
+       {
+               name:    "MaskedShiftRightInt32x8",
+               argLen:  3,
+               generic: true,
+       },
+       {
+               name:    "MaskedShiftRightAndFillUpperFromInt32x8",
+               argLen:  4,
+               generic: true,
+       },
+       {
+               name:    "MaskedShiftRightSignExtendedInt32x8",
+               argLen:  3,
+               generic: true,
+       },
+       {
+               name:    "MaskedSubInt32x8",
+               argLen:  3,
+               generic: true,
+       },
+       {
+               name:    "MaskedUnsignedSignedQuadDotProdAccumulateInt32x8",
+               argLen:  4,
+               generic: true,
+       },
+       {
+               name:        "MaskedXorInt32x8",
+               argLen:      3,
+               commutative: true,
+               generic:     true,
+       },
+       {
+               name:        "MaxInt32x8",
                argLen:      2,
                commutative: true,
                generic:     true,
        },
        {
-               name:        "MinInt16x16",
+               name:        "MinInt32x8",
                argLen:      2,
                commutative: true,
                generic:     true,
        },
        {
-               name:        "MulHighInt16x16",
+               name:        "MulEvenWidenInt32x8",
                argLen:      2,
                commutative: true,
                generic:     true,
        },
        {
-               name:        "MulLowInt16x16",
+               name:        "MulLowInt32x8",
                argLen:      2,
                commutative: true,
                generic:     true,
        },
        {
-               name:        "NotEqualInt16x16",
+               name:        "NotEqualInt32x8",
                argLen:      2,
                commutative: true,
                generic:     true,
        },
        {
-               name:        "OrInt16x16",
+               name:        "OrInt32x8",
                argLen:      2,
                commutative: true,
                generic:     true,
        },
        {
-               name:    "PairDotProdInt16x16",
-               argLen:  2,
+               name:    "PairDotProdAccumulateInt32x8",
+               argLen:  3,
                generic: true,
        },
        {
-               name:    "PairwiseAddInt16x16",
+               name:    "PairwiseAddInt32x8",
                argLen:  2,
                generic: true,
        },
        {
-               name:    "PairwiseSubInt16x16",
+               name:    "PairwiseSubInt32x8",
                argLen:  2,
                generic: true,
        },
        {
-               name:    "PopCountInt16x16",
+               name:    "PopCountInt32x8",
                argLen:  1,
                generic: true,
        },
        {
-               name:        "SaturatedAddInt16x16",
-               argLen:      2,
-               commutative: true,
-               generic:     true,
+               name:    "RotateLeftInt32x8",
+               argLen:  2,
+               generic: true,
        },
        {
-               name:    "SaturatedPairwiseAddInt16x16",
+               name:    "RotateRightInt32x8",
                argLen:  2,
                generic: true,
        },
        {
-               name:    "SaturatedPairwiseSubInt16x16",
+               name:    "SaturatedPairDotProdAccumulateInt32x8",
+               argLen:  3,
+               generic: true,
+       },
+       {
+               name:    "SaturatedUnsignedSignedQuadDotProdAccumulateInt32x8",
+               argLen:  3,
+               generic: true,
+       },
+       {
+               name:    "ShiftAllLeftInt32x8",
                argLen:  2,
                generic: true,
        },
        {
-               name:    "SaturatedSubInt16x16",
+               name:    "ShiftAllRightInt32x8",
                argLen:  2,
                generic: true,
        },
        {
-               name:    "SignInt16x16",
+               name:    "ShiftAllRightSignExtendedInt32x8",
                argLen:  2,
                generic: true,
        },
        {
-               name:    "SubInt16x16",
+               name:    "ShiftLeftInt32x8",
                argLen:  2,
                generic: true,
        },
        {
-               name:        "XorInt16x16",
+               name:    "ShiftLeftAndFillUpperFromInt32x8",
+               argLen:  3,
+               generic: true,
+       },
+       {
+               name:    "ShiftRightInt32x8",
+               argLen:  2,
+               generic: true,
+       },
+       {
+               name:    "ShiftRightAndFillUpperFromInt32x8",
+               argLen:  3,
+               generic: true,
+       },
+       {
+               name:    "ShiftRightSignExtendedInt32x8",
+               argLen:  2,
+               generic: true,
+       },
+       {
+               name:    "SignInt32x8",
+               argLen:  2,
+               generic: true,
+       },
+       {
+               name:    "SubInt32x8",
+               argLen:  2,
+               generic: true,
+       },
+       {
+               name:    "UnsignedSignedQuadDotProdAccumulateInt32x8",
+               argLen:  3,
+               generic: true,
+       },
+       {
+               name:        "XorInt32x8",
                argLen:      2,
                commutative: true,
                generic:     true,
        },
        {
-               name:    "AbsoluteInt16x32",
+               name:    "AbsoluteInt64x2",
                argLen:  1,
                generic: true,
        },
        {
-               name:        "AddInt16x32",
+               name:        "AddInt64x2",
                argLen:      2,
                commutative: true,
                generic:     true,
        },
        {
-               name:        "EqualInt16x32",
+               name:        "AndInt64x2",
                argLen:      2,
                commutative: true,
                generic:     true,
        },
        {
-               name:    "GreaterInt16x32",
+               name:    "AndNotInt64x2",
                argLen:  2,
                generic: true,
        },
        {
-               name:    "GreaterEqualInt16x32",
+               name:        "EqualInt64x2",
+               argLen:      2,
+               commutative: true,
+               generic:     true,
+       },
+       {
+               name:    "GreaterInt64x2",
                argLen:  2,
                generic: true,
        },
        {
-               name:    "LessInt16x32",
+               name:    "GreaterEqualInt64x2",
                argLen:  2,
                generic: true,
        },
        {
-               name:    "LessEqualInt16x32",
+               name:    "LessInt64x2",
                argLen:  2,
                generic: true,
        },
        {
-               name:    "MaskedAbsoluteInt16x32",
+               name:    "LessEqualInt64x2",
                argLen:  2,
                generic: true,
        },
        {
-               name:        "MaskedAddInt16x32",
+               name:    "MaskedAbsoluteInt64x2",
+               argLen:  2,
+               generic: true,
+       },
+       {
+               name:        "MaskedAddInt64x2",
                argLen:      3,
                commutative: true,
                generic:     true,
        },
        {
-               name:        "MaskedEqualInt16x32",
+               name:        "MaskedAndInt64x2",
                argLen:      3,
                commutative: true,
                generic:     true,
        },
        {
-               name:    "MaskedGreaterInt16x32",
+               name:    "MaskedAndNotInt64x2",
                argLen:  3,
                generic: true,
        },
        {
-               name:    "MaskedGreaterEqualInt16x32",
+               name:        "MaskedEqualInt64x2",
+               argLen:      3,
+               commutative: true,
+               generic:     true,
+       },
+       {
+               name:    "MaskedGreaterInt64x2",
                argLen:  3,
                generic: true,
        },
        {
-               name:    "MaskedLessInt16x32",
+               name:    "MaskedGreaterEqualInt64x2",
                argLen:  3,
                generic: true,
        },
        {
-               name:    "MaskedLessEqualInt16x32",
+               name:    "MaskedLessInt64x2",
                argLen:  3,
                generic: true,
        },
        {
-               name:        "MaskedMaxInt16x32",
+               name:    "MaskedLessEqualInt64x2",
+               argLen:  3,
+               generic: true,
+       },
+       {
+               name:        "MaskedMaxInt64x2",
                argLen:      3,
                commutative: true,
                generic:     true,
        },
        {
-               name:        "MaskedMinInt16x32",
+               name:        "MaskedMinInt64x2",
                argLen:      3,
                commutative: true,
                generic:     true,
        },
        {
-               name:        "MaskedMulHighInt16x32",
+               name:        "MaskedMulEvenWidenInt64x2",
                argLen:      3,
                commutative: true,
                generic:     true,
        },
        {
-               name:        "MaskedMulLowInt16x32",
+               name:        "MaskedMulLowInt64x2",
                argLen:      3,
                commutative: true,
                generic:     true,
        },
        {
-               name:        "MaskedNotEqualInt16x32",
+               name:        "MaskedNotEqualInt64x2",
                argLen:      3,
                commutative: true,
                generic:     true,
        },
        {
-               name:    "MaskedPairDotProdInt16x32",
+               name:        "MaskedOrInt64x2",
+               argLen:      3,
+               commutative: true,
+               generic:     true,
+       },
+       {
+               name:    "MaskedPopCountInt64x2",
+               argLen:  2,
+               generic: true,
+       },
+       {
+               name:    "MaskedRotateLeftInt64x2",
                argLen:  3,
                generic: true,
        },
        {
-               name:    "MaskedPopCountInt16x32",
-               argLen:  2,
+               name:    "MaskedRotateRightInt64x2",
+               argLen:  3,
                generic: true,
        },
        {
-               name:        "MaskedSaturatedAddInt16x32",
-               argLen:      3,
-               commutative: true,
-               generic:     true,
+               name:    "MaskedShiftAllLeftInt64x2",
+               argLen:  3,
+               generic: true,
        },
        {
-               name:    "MaskedSaturatedSubInt16x32",
+               name:    "MaskedShiftAllRightInt64x2",
                argLen:  3,
                generic: true,
        },
        {
-               name:    "MaskedSubInt16x32",
+               name:    "MaskedShiftAllRightSignExtendedInt64x2",
                argLen:  3,
                generic: true,
        },
        {
-               name:        "MaxInt16x32",
+               name:    "MaskedShiftLeftInt64x2",
+               argLen:  3,
+               generic: true,
+       },
+       {
+               name:    "MaskedShiftLeftAndFillUpperFromInt64x2",
+               argLen:  4,
+               generic: true,
+       },
+       {
+               name:    "MaskedShiftRightInt64x2",
+               argLen:  3,
+               generic: true,
+       },
+       {
+               name:    "MaskedShiftRightAndFillUpperFromInt64x2",
+               argLen:  4,
+               generic: true,
+       },
+       {
+               name:    "MaskedShiftRightSignExtendedInt64x2",
+               argLen:  3,
+               generic: true,
+       },
+       {
+               name:    "MaskedSubInt64x2",
+               argLen:  3,
+               generic: true,
+       },
+       {
+               name:        "MaskedXorInt64x2",
+               argLen:      3,
+               commutative: true,
+               generic:     true,
+       },
+       {
+               name:        "MaxInt64x2",
                argLen:      2,
                commutative: true,
                generic:     true,
        },
        {
-               name:        "MinInt16x32",
+               name:        "MinInt64x2",
                argLen:      2,
                commutative: true,
                generic:     true,
        },
        {
-               name:        "MulHighInt16x32",
+               name:        "MulEvenWidenInt64x2",
                argLen:      2,
                commutative: true,
                generic:     true,
        },
        {
-               name:        "MulLowInt16x32",
+               name:        "MulLowInt64x2",
                argLen:      2,
                commutative: true,
                generic:     true,
        },
        {
-               name:        "NotEqualInt16x32",
+               name:        "NotEqualInt64x2",
                argLen:      2,
                commutative: true,
                generic:     true,
        },
        {
-               name:    "PairDotProdInt16x32",
+               name:        "OrInt64x2",
+               argLen:      2,
+               commutative: true,
+               generic:     true,
+       },
+       {
+               name:    "PopCountInt64x2",
+               argLen:  1,
+               generic: true,
+       },
+       {
+               name:    "RotateLeftInt64x2",
                argLen:  2,
                generic: true,
        },
        {
-               name:    "PopCountInt16x32",
-               argLen:  1,
+               name:    "RotateRightInt64x2",
+               argLen:  2,
                generic: true,
        },
        {
-               name:        "SaturatedAddInt16x32",
-               argLen:      2,
-               commutative: true,
-               generic:     true,
+               name:    "ShiftAllLeftInt64x2",
+               argLen:  2,
+               generic: true,
        },
        {
-               name:    "SaturatedSubInt16x32",
+               name:    "ShiftAllRightInt64x2",
                argLen:  2,
                generic: true,
        },
        {
-               name:    "SubInt16x32",
+               name:    "ShiftAllRightSignExtendedInt64x2",
                argLen:  2,
                generic: true,
        },
        {
-               name:    "AbsoluteInt16x8",
+               name:    "ShiftLeftInt64x2",
+               argLen:  2,
+               generic: true,
+       },
+       {
+               name:    "ShiftLeftAndFillUpperFromInt64x2",
+               argLen:  3,
+               generic: true,
+       },
+       {
+               name:    "ShiftRightInt64x2",
+               argLen:  2,
+               generic: true,
+       },
+       {
+               name:    "ShiftRightAndFillUpperFromInt64x2",
+               argLen:  3,
+               generic: true,
+       },
+       {
+               name:    "ShiftRightSignExtendedInt64x2",
+               argLen:  2,
+               generic: true,
+       },
+       {
+               name:    "SubInt64x2",
+               argLen:  2,
+               generic: true,
+       },
+       {
+               name:        "XorInt64x2",
+               argLen:      2,
+               commutative: true,
+               generic:     true,
+       },
+       {
+               name:    "AbsoluteInt64x4",
                argLen:  1,
                generic: true,
        },
        {
-               name:        "AddInt16x8",
+               name:        "AddInt64x4",
                argLen:      2,
                commutative: true,
                generic:     true,
        },
        {
-               name:        "AndInt16x8",
+               name:        "AndInt64x4",
                argLen:      2,
                commutative: true,
                generic:     true,
        },
        {
-               name:    "AndNotInt16x8",
+               name:    "AndNotInt64x4",
                argLen:  2,
                generic: true,
        },
        {
-               name:        "EqualInt16x8",
+               name:        "EqualInt64x4",
                argLen:      2,
                commutative: true,
                generic:     true,
        },
        {
-               name:    "GreaterInt16x8",
+               name:    "GreaterInt64x4",
                argLen:  2,
                generic: true,
        },
        {
-               name:    "GreaterEqualInt16x8",
+               name:    "GreaterEqualInt64x4",
                argLen:  2,
                generic: true,
        },
        {
-               name:    "LessInt16x8",
+               name:    "LessInt64x4",
                argLen:  2,
                generic: true,
        },
        {
-               name:    "LessEqualInt16x8",
+               name:    "LessEqualInt64x4",
                argLen:  2,
                generic: true,
        },
        {
-               name:    "MaskedAbsoluteInt16x8",
+               name:    "MaskedAbsoluteInt64x4",
                argLen:  2,
                generic: true,
        },
        {
-               name:        "MaskedAddInt16x8",
+               name:        "MaskedAddInt64x4",
                argLen:      3,
                commutative: true,
                generic:     true,
        },
        {
-               name:        "MaskedEqualInt16x8",
+               name:        "MaskedAndInt64x4",
                argLen:      3,
                commutative: true,
                generic:     true,
        },
        {
-               name:    "MaskedGreaterInt16x8",
+               name:    "MaskedAndNotInt64x4",
                argLen:  3,
                generic: true,
        },
        {
-               name:    "MaskedGreaterEqualInt16x8",
+               name:        "MaskedEqualInt64x4",
+               argLen:      3,
+               commutative: true,
+               generic:     true,
+       },
+       {
+               name:    "MaskedGreaterInt64x4",
                argLen:  3,
                generic: true,
        },
        {
-               name:    "MaskedLessInt16x8",
+               name:    "MaskedGreaterEqualInt64x4",
                argLen:  3,
                generic: true,
        },
        {
-               name:    "MaskedLessEqualInt16x8",
+               name:    "MaskedLessInt64x4",
                argLen:  3,
                generic: true,
        },
        {
-               name:        "MaskedMaxInt16x8",
+               name:    "MaskedLessEqualInt64x4",
+               argLen:  3,
+               generic: true,
+       },
+       {
+               name:        "MaskedMaxInt64x4",
                argLen:      3,
                commutative: true,
                generic:     true,
        },
        {
-               name:        "MaskedMinInt16x8",
+               name:        "MaskedMinInt64x4",
                argLen:      3,
                commutative: true,
                generic:     true,
        },
        {
-               name:        "MaskedMulHighInt16x8",
+               name:        "MaskedMulEvenWidenInt64x4",
                argLen:      3,
                commutative: true,
                generic:     true,
        },
        {
-               name:        "MaskedMulLowInt16x8",
+               name:        "MaskedMulLowInt64x4",
                argLen:      3,
                commutative: true,
                generic:     true,
        },
        {
-               name:        "MaskedNotEqualInt16x8",
+               name:        "MaskedNotEqualInt64x4",
                argLen:      3,
                commutative: true,
                generic:     true,
        },
        {
-               name:    "MaskedPairDotProdInt16x8",
+               name:        "MaskedOrInt64x4",
+               argLen:      3,
+               commutative: true,
+               generic:     true,
+       },
+       {
+               name:    "MaskedPopCountInt64x4",
+               argLen:  2,
+               generic: true,
+       },
+       {
+               name:    "MaskedRotateLeftInt64x4",
                argLen:  3,
                generic: true,
        },
        {
-               name:    "MaskedPopCountInt16x8",
-               argLen:  2,
+               name:    "MaskedRotateRightInt64x4",
+               argLen:  3,
                generic: true,
        },
        {
-               name:        "MaskedSaturatedAddInt16x8",
-               argLen:      3,
-               commutative: true,
-               generic:     true,
+               name:    "MaskedShiftAllLeftInt64x4",
+               argLen:  3,
+               generic: true,
        },
        {
-               name:    "MaskedSaturatedSubInt16x8",
+               name:    "MaskedShiftAllRightInt64x4",
                argLen:  3,
                generic: true,
        },
        {
-               name:    "MaskedSubInt16x8",
+               name:    "MaskedShiftAllRightSignExtendedInt64x4",
                argLen:  3,
                generic: true,
        },
        {
-               name:        "MaxInt16x8",
+               name:    "MaskedShiftLeftInt64x4",
+               argLen:  3,
+               generic: true,
+       },
+       {
+               name:    "MaskedShiftLeftAndFillUpperFromInt64x4",
+               argLen:  4,
+               generic: true,
+       },
+       {
+               name:    "MaskedShiftRightInt64x4",
+               argLen:  3,
+               generic: true,
+       },
+       {
+               name:    "MaskedShiftRightAndFillUpperFromInt64x4",
+               argLen:  4,
+               generic: true,
+       },
+       {
+               name:    "MaskedShiftRightSignExtendedInt64x4",
+               argLen:  3,
+               generic: true,
+       },
+       {
+               name:    "MaskedSubInt64x4",
+               argLen:  3,
+               generic: true,
+       },
+       {
+               name:        "MaskedXorInt64x4",
+               argLen:      3,
+               commutative: true,
+               generic:     true,
+       },
+       {
+               name:        "MaxInt64x4",
                argLen:      2,
                commutative: true,
                generic:     true,
        },
        {
-               name:        "MinInt16x8",
+               name:        "MinInt64x4",
                argLen:      2,
                commutative: true,
                generic:     true,
        },
        {
-               name:        "MulHighInt16x8",
+               name:        "MulEvenWidenInt64x4",
                argLen:      2,
                commutative: true,
                generic:     true,
        },
        {
-               name:        "MulLowInt16x8",
+               name:        "MulLowInt64x4",
                argLen:      2,
                commutative: true,
                generic:     true,
        },
        {
-               name:        "NotEqualInt16x8",
+               name:        "NotEqualInt64x4",
                argLen:      2,
                commutative: true,
                generic:     true,
        },
        {
-               name:        "OrInt16x8",
+               name:        "OrInt64x4",
                argLen:      2,
                commutative: true,
                generic:     true,
        },
        {
-               name:    "PairDotProdInt16x8",
-               argLen:  2,
+               name:    "PopCountInt64x4",
+               argLen:  1,
                generic: true,
        },
        {
-               name:    "PairwiseAddInt16x8",
+               name:    "RotateLeftInt64x4",
                argLen:  2,
                generic: true,
        },
        {
-               name:    "PairwiseSubInt16x8",
+               name:    "RotateRightInt64x4",
                argLen:  2,
                generic: true,
        },
        {
-               name:    "PopCountInt16x8",
-               argLen:  1,
+               name:    "ShiftAllLeftInt64x4",
+               argLen:  2,
                generic: true,
        },
        {
-               name:        "SaturatedAddInt16x8",
-               argLen:      2,
-               commutative: true,
-               generic:     true,
+               name:    "ShiftAllRightInt64x4",
+               argLen:  2,
+               generic: true,
        },
        {
-               name:    "SaturatedPairwiseAddInt16x8",
+               name:    "ShiftAllRightSignExtendedInt64x4",
                argLen:  2,
                generic: true,
        },
        {
-               name:    "SaturatedPairwiseSubInt16x8",
+               name:    "ShiftLeftInt64x4",
                argLen:  2,
                generic: true,
        },
        {
-               name:    "SaturatedSubInt16x8",
+               name:    "ShiftLeftAndFillUpperFromInt64x4",
+               argLen:  3,
+               generic: true,
+       },
+       {
+               name:    "ShiftRightInt64x4",
                argLen:  2,
                generic: true,
        },
        {
-               name:    "SignInt16x8",
+               name:    "ShiftRightAndFillUpperFromInt64x4",
+               argLen:  3,
+               generic: true,
+       },
+       {
+               name:    "ShiftRightSignExtendedInt64x4",
                argLen:  2,
                generic: true,
        },
        {
-               name:    "SubInt16x8",
+               name:    "SubInt64x4",
                argLen:  2,
                generic: true,
        },
        {
-               name:        "XorInt16x8",
+               name:        "XorInt64x4",
                argLen:      2,
                commutative: true,
                generic:     true,
        },
        {
-               name:    "AbsoluteInt32x16",
+               name:    "AbsoluteInt64x8",
                argLen:  1,
                generic: true,
        },
        {
-               name:        "AddInt32x16",
+               name:        "AddInt64x8",
                argLen:      2,
                commutative: true,
                generic:     true,
        },
        {
-               name:        "AndInt32x16",
+               name:        "AndInt64x8",
                argLen:      2,
                commutative: true,
                generic:     true,
        },
        {
-               name:    "AndNotInt32x16",
+               name:    "AndNotInt64x8",
                argLen:  2,
                generic: true,
        },
        {
-               name:        "EqualInt32x16",
+               name:        "EqualInt64x8",
                argLen:      2,
                commutative: true,
                generic:     true,
        },
        {
-               name:    "GreaterInt32x16",
+               name:    "GreaterInt64x8",
                argLen:  2,
                generic: true,
        },
        {
-               name:    "GreaterEqualInt32x16",
+               name:    "GreaterEqualInt64x8",
                argLen:  2,
                generic: true,
        },
        {
-               name:    "LessInt32x16",
+               name:    "LessInt64x8",
                argLen:  2,
                generic: true,
        },
        {
-               name:    "LessEqualInt32x16",
+               name:    "LessEqualInt64x8",
                argLen:  2,
                generic: true,
        },
        {
-               name:    "MaskedAbsoluteInt32x16",
+               name:    "MaskedAbsoluteInt64x8",
                argLen:  2,
                generic: true,
        },
        {
-               name:        "MaskedAddInt32x16",
+               name:        "MaskedAddInt64x8",
                argLen:      3,
                commutative: true,
                generic:     true,
        },
        {
-               name:        "MaskedAndInt32x16",
+               name:        "MaskedAndInt64x8",
                argLen:      3,
                commutative: true,
                generic:     true,
        },
        {
-               name:    "MaskedAndNotInt32x16",
+               name:    "MaskedAndNotInt64x8",
                argLen:  3,
                generic: true,
        },
        {
-               name:        "MaskedEqualInt32x16",
+               name:        "MaskedEqualInt64x8",
                argLen:      3,
                commutative: true,
                generic:     true,
        },
        {
-               name:    "MaskedGreaterInt32x16",
+               name:    "MaskedGreaterInt64x8",
                argLen:  3,
                generic: true,
        },
        {
-               name:    "MaskedGreaterEqualInt32x16",
+               name:    "MaskedGreaterEqualInt64x8",
                argLen:  3,
                generic: true,
        },
        {
-               name:    "MaskedLessInt32x16",
+               name:    "MaskedLessInt64x8",
                argLen:  3,
                generic: true,
        },
        {
-               name:    "MaskedLessEqualInt32x16",
+               name:    "MaskedLessEqualInt64x8",
                argLen:  3,
                generic: true,
        },
        {
-               name:        "MaskedMaxInt32x16",
+               name:        "MaskedMaxInt64x8",
                argLen:      3,
                commutative: true,
                generic:     true,
        },
        {
-               name:        "MaskedMinInt32x16",
+               name:        "MaskedMinInt64x8",
                argLen:      3,
                commutative: true,
                generic:     true,
        },
        {
-               name:        "MaskedMulLowInt32x16",
+               name:        "MaskedMulEvenWidenInt64x8",
                argLen:      3,
                commutative: true,
                generic:     true,
        },
        {
-               name:        "MaskedNotEqualInt32x16",
+               name:        "MaskedMulLowInt64x8",
                argLen:      3,
                commutative: true,
                generic:     true,
        },
        {
-               name:        "MaskedOrInt32x16",
+               name:        "MaskedNotEqualInt64x8",
                argLen:      3,
                commutative: true,
                generic:     true,
        },
        {
-               name:    "MaskedPairDotProdAccumulateInt32x16",
-               argLen:  4,
-               generic: true,
+               name:        "MaskedOrInt64x8",
+               argLen:      3,
+               commutative: true,
+               generic:     true,
        },
        {
-               name:    "MaskedPopCountInt32x16",
+               name:    "MaskedPopCountInt64x8",
                argLen:  2,
                generic: true,
        },
        {
-               name:    "MaskedSaturatedPairDotProdAccumulateInt32x16",
-               argLen:  4,
+               name:    "MaskedRotateLeftInt64x8",
+               argLen:  3,
                generic: true,
        },
        {
-               name:    "MaskedSaturatedUnsignedSignedQuadDotProdAccumulateInt32x16",
+               name:    "MaskedRotateRightInt64x8",
+               argLen:  3,
+               generic: true,
+       },
+       {
+               name:    "MaskedShiftAllLeftInt64x8",
+               argLen:  3,
+               generic: true,
+       },
+       {
+               name:    "MaskedShiftAllRightInt64x8",
+               argLen:  3,
+               generic: true,
+       },
+       {
+               name:    "MaskedShiftAllRightSignExtendedInt64x8",
+               argLen:  3,
+               generic: true,
+       },
+       {
+               name:    "MaskedShiftLeftInt64x8",
+               argLen:  3,
+               generic: true,
+       },
+       {
+               name:    "MaskedShiftLeftAndFillUpperFromInt64x8",
                argLen:  4,
                generic: true,
        },
        {
-               name:    "MaskedSubInt32x16",
+               name:    "MaskedShiftRightInt64x8",
                argLen:  3,
                generic: true,
        },
        {
-               name:    "MaskedUnsignedSignedQuadDotProdAccumulateInt32x16",
+               name:    "MaskedShiftRightAndFillUpperFromInt64x8",
                argLen:  4,
                generic: true,
        },
        {
-               name:        "MaskedXorInt32x16",
+               name:    "MaskedShiftRightSignExtendedInt64x8",
+               argLen:  3,
+               generic: true,
+       },
+       {
+               name:    "MaskedSubInt64x8",
+               argLen:  3,
+               generic: true,
+       },
+       {
+               name:        "MaskedXorInt64x8",
                argLen:      3,
                commutative: true,
                generic:     true,
        },
        {
-               name:        "MaxInt32x16",
+               name:        "MaxInt64x8",
                argLen:      2,
                commutative: true,
                generic:     true,
        },
        {
-               name:        "MinInt32x16",
+               name:        "MinInt64x8",
                argLen:      2,
                commutative: true,
                generic:     true,
        },
        {
-               name:        "MulLowInt32x16",
+               name:        "MulEvenWidenInt64x8",
                argLen:      2,
                commutative: true,
                generic:     true,
        },
        {
-               name:        "NotEqualInt32x16",
+               name:        "MulLowInt64x8",
                argLen:      2,
                commutative: true,
                generic:     true,
        },
        {
-               name:        "OrInt32x16",
+               name:        "NotEqualInt64x8",
                argLen:      2,
                commutative: true,
                generic:     true,
        },
        {
-               name:    "PairDotProdAccumulateInt32x16",
-               argLen:  3,
-               generic: true,
+               name:        "OrInt64x8",
+               argLen:      2,
+               commutative: true,
+               generic:     true,
        },
        {
-               name:    "PopCountInt32x16",
+               name:    "PopCountInt64x8",
                argLen:  1,
                generic: true,
        },
        {
-               name:    "SaturatedPairDotProdAccumulateInt32x16",
-               argLen:  3,
+               name:    "RotateLeftInt64x8",
+               argLen:  2,
                generic: true,
        },
        {
-               name:    "SaturatedUnsignedSignedQuadDotProdAccumulateInt32x16",
+               name:    "RotateRightInt64x8",
+               argLen:  2,
+               generic: true,
+       },
+       {
+               name:    "ShiftAllLeftInt64x8",
+               argLen:  2,
+               generic: true,
+       },
+       {
+               name:    "ShiftAllRightInt64x8",
+               argLen:  2,
+               generic: true,
+       },
+       {
+               name:    "ShiftAllRightSignExtendedInt64x8",
+               argLen:  2,
+               generic: true,
+       },
+       {
+               name:    "ShiftLeftInt64x8",
+               argLen:  2,
+               generic: true,
+       },
+       {
+               name:    "ShiftLeftAndFillUpperFromInt64x8",
                argLen:  3,
                generic: true,
        },
        {
-               name:    "SubInt32x16",
+               name:    "ShiftRightInt64x8",
                argLen:  2,
                generic: true,
        },
        {
-               name:    "UnsignedSignedQuadDotProdAccumulateInt32x16",
+               name:    "ShiftRightAndFillUpperFromInt64x8",
                argLen:  3,
                generic: true,
        },
        {
-               name:        "XorInt32x16",
+               name:    "ShiftRightSignExtendedInt64x8",
+               argLen:  2,
+               generic: true,
+       },
+       {
+               name:    "SubInt64x8",
+               argLen:  2,
+               generic: true,
+       },
+       {
+               name:        "XorInt64x8",
                argLen:      2,
                commutative: true,
                generic:     true,
        },
        {
-               name:    "AbsoluteInt32x4",
+               name:    "AbsoluteInt8x16",
                argLen:  1,
                generic: true,
        },
        {
-               name:        "AddInt32x4",
+               name:        "AddInt8x16",
                argLen:      2,
                commutative: true,
                generic:     true,
        },
        {
-               name:        "AndInt32x4",
+               name:        "AndInt8x16",
                argLen:      2,
                commutative: true,
                generic:     true,
        },
        {
-               name:    "AndNotInt32x4",
+               name:    "AndNotInt8x16",
                argLen:  2,
                generic: true,
        },
        {
-               name:        "EqualInt32x4",
+               name:        "EqualInt8x16",
                argLen:      2,
                commutative: true,
                generic:     true,
        },
        {
-               name:    "GreaterInt32x4",
+               name:    "GreaterInt8x16",
                argLen:  2,
                generic: true,
        },
        {
-               name:    "GreaterEqualInt32x4",
+               name:    "GreaterEqualInt8x16",
                argLen:  2,
                generic: true,
        },
        {
-               name:    "LessInt32x4",
+               name:    "LessInt8x16",
                argLen:  2,
                generic: true,
        },
        {
-               name:    "LessEqualInt32x4",
+               name:    "LessEqualInt8x16",
                argLen:  2,
                generic: true,
        },
        {
-               name:    "MaskedAbsoluteInt32x4",
+               name:    "MaskedAbsoluteInt8x16",
                argLen:  2,
                generic: true,
        },
        {
-               name:        "MaskedAddInt32x4",
-               argLen:      3,
-               commutative: true,
-               generic:     true,
-       },
-       {
-               name:        "MaskedAndInt32x4",
+               name:        "MaskedAddInt8x16",
                argLen:      3,
                commutative: true,
                generic:     true,
        },
        {
-               name:    "MaskedAndNotInt32x4",
-               argLen:  3,
-               generic: true,
-       },
-       {
-               name:        "MaskedEqualInt32x4",
+               name:        "MaskedEqualInt8x16",
                argLen:      3,
                commutative: true,
                generic:     true,
        },
        {
-               name:    "MaskedGreaterInt32x4",
+               name:    "MaskedGreaterInt8x16",
                argLen:  3,
                generic: true,
        },
        {
-               name:    "MaskedGreaterEqualInt32x4",
+               name:    "MaskedGreaterEqualInt8x16",
                argLen:  3,
                generic: true,
        },
        {
-               name:    "MaskedLessInt32x4",
+               name:    "MaskedLessInt8x16",
                argLen:  3,
                generic: true,
        },
        {
-               name:    "MaskedLessEqualInt32x4",
+               name:    "MaskedLessEqualInt8x16",
                argLen:  3,
                generic: true,
        },
        {
-               name:        "MaskedMaxInt32x4",
+               name:        "MaskedMaxInt8x16",
                argLen:      3,
                commutative: true,
                generic:     true,
        },
        {
-               name:        "MaskedMinInt32x4",
+               name:        "MaskedMinInt8x16",
                argLen:      3,
                commutative: true,
                generic:     true,
        },
        {
-               name:        "MaskedMulLowInt32x4",
+               name:        "MaskedNotEqualInt8x16",
                argLen:      3,
                commutative: true,
                generic:     true,
        },
        {
-               name:        "MaskedNotEqualInt32x4",
-               argLen:      3,
-               commutative: true,
-               generic:     true,
+               name:    "MaskedPopCountInt8x16",
+               argLen:  2,
+               generic: true,
        },
        {
-               name:        "MaskedOrInt32x4",
+               name:        "MaskedSaturatedAddInt8x16",
                argLen:      3,
                commutative: true,
                generic:     true,
        },
        {
-               name:    "MaskedPairDotProdAccumulateInt32x4",
-               argLen:  4,
-               generic: true,
-       },
-       {
-               name:    "MaskedPopCountInt32x4",
-               argLen:  2,
-               generic: true,
-       },
-       {
-               name:    "MaskedSaturatedPairDotProdAccumulateInt32x4",
-               argLen:  4,
-               generic: true,
-       },
-       {
-               name:    "MaskedSaturatedUnsignedSignedQuadDotProdAccumulateInt32x4",
-               argLen:  4,
-               generic: true,
-       },
-       {
-               name:    "MaskedSubInt32x4",
+               name:    "MaskedSaturatedSubInt8x16",
                argLen:  3,
                generic: true,
        },
        {
-               name:    "MaskedUnsignedSignedQuadDotProdAccumulateInt32x4",
-               argLen:  4,
+               name:    "MaskedSubInt8x16",
+               argLen:  3,
                generic: true,
        },
        {
-               name:        "MaskedXorInt32x4",
-               argLen:      3,
-               commutative: true,
-               generic:     true,
-       },
-       {
-               name:        "MaxInt32x4",
+               name:        "MaxInt8x16",
                argLen:      2,
                commutative: true,
                generic:     true,
        },
        {
-               name:        "MinInt32x4",
+               name:        "MinInt8x16",
                argLen:      2,
                commutative: true,
                generic:     true,
        },
        {
-               name:        "MulEvenWidenInt32x4",
+               name:        "NotEqualInt8x16",
                argLen:      2,
                commutative: true,
                generic:     true,
        },
        {
-               name:        "MulLowInt32x4",
+               name:        "OrInt8x16",
                argLen:      2,
                commutative: true,
                generic:     true,
        },
        {
-               name:        "NotEqualInt32x4",
-               argLen:      2,
-               commutative: true,
-               generic:     true,
+               name:    "PopCountInt8x16",
+               argLen:  1,
+               generic: true,
        },
        {
-               name:        "OrInt32x4",
+               name:        "SaturatedAddInt8x16",
                argLen:      2,
                commutative: true,
                generic:     true,
        },
        {
-               name:    "PairDotProdAccumulateInt32x4",
-               argLen:  3,
-               generic: true,
-       },
-       {
-               name:    "PairwiseAddInt32x4",
-               argLen:  2,
-               generic: true,
-       },
-       {
-               name:    "PairwiseSubInt32x4",
+               name:    "SaturatedSubInt8x16",
                argLen:  2,
                generic: true,
        },
        {
-               name:    "PopCountInt32x4",
-               argLen:  1,
-               generic: true,
-       },
-       {
-               name:    "SaturatedPairDotProdAccumulateInt32x4",
-               argLen:  3,
-               generic: true,
-       },
-       {
-               name:    "SaturatedUnsignedSignedQuadDotProdAccumulateInt32x4",
-               argLen:  3,
-               generic: true,
-       },
-       {
-               name:    "SignInt32x4",
+               name:    "SignInt8x16",
                argLen:  2,
                generic: true,
        },
        {
-               name:    "SubInt32x4",
+               name:    "SubInt8x16",
                argLen:  2,
                generic: true,
        },
        {
-               name:    "UnsignedSignedQuadDotProdAccumulateInt32x4",
-               argLen:  3,
-               generic: true,
-       },
-       {
-               name:        "XorInt32x4",
+               name:        "XorInt8x16",
                argLen:      2,
                commutative: true,
                generic:     true,
        },
        {
-               name:    "AbsoluteInt32x8",
+               name:    "AbsoluteInt8x32",
                argLen:  1,
                generic: true,
        },
        {
-               name:        "AddInt32x8",
+               name:        "AddInt8x32",
                argLen:      2,
                commutative: true,
                generic:     true,
        },
        {
-               name:        "AndInt32x8",
+               name:        "AndInt8x32",
                argLen:      2,
                commutative: true,
                generic:     true,
        },
        {
-               name:    "AndNotInt32x8",
+               name:    "AndNotInt8x32",
                argLen:  2,
                generic: true,
        },
        {
-               name:        "EqualInt32x8",
+               name:        "EqualInt8x32",
                argLen:      2,
                commutative: true,
                generic:     true,
        },
        {
-               name:    "GreaterInt32x8",
+               name:    "GreaterInt8x32",
                argLen:  2,
                generic: true,
        },
        {
-               name:    "GreaterEqualInt32x8",
+               name:    "GreaterEqualInt8x32",
                argLen:  2,
                generic: true,
        },
        {
-               name:    "LessInt32x8",
+               name:    "LessInt8x32",
                argLen:  2,
                generic: true,
        },
        {
-               name:    "LessEqualInt32x8",
+               name:    "LessEqualInt8x32",
                argLen:  2,
                generic: true,
        },
        {
-               name:    "MaskedAbsoluteInt32x8",
+               name:    "MaskedAbsoluteInt8x32",
                argLen:  2,
                generic: true,
        },
        {
-               name:        "MaskedAddInt32x8",
-               argLen:      3,
-               commutative: true,
-               generic:     true,
-       },
-       {
-               name:        "MaskedAndInt32x8",
+               name:        "MaskedAddInt8x32",
                argLen:      3,
                commutative: true,
                generic:     true,
        },
        {
-               name:    "MaskedAndNotInt32x8",
-               argLen:  3,
-               generic: true,
-       },
-       {
-               name:        "MaskedEqualInt32x8",
+               name:        "MaskedEqualInt8x32",
                argLen:      3,
                commutative: true,
                generic:     true,
        },
        {
-               name:    "MaskedGreaterInt32x8",
+               name:    "MaskedGreaterInt8x32",
                argLen:  3,
                generic: true,
        },
        {
-               name:    "MaskedGreaterEqualInt32x8",
+               name:    "MaskedGreaterEqualInt8x32",
                argLen:  3,
                generic: true,
        },
        {
-               name:    "MaskedLessInt32x8",
+               name:    "MaskedLessInt8x32",
                argLen:  3,
                generic: true,
        },
        {
-               name:    "MaskedLessEqualInt32x8",
+               name:    "MaskedLessEqualInt8x32",
                argLen:  3,
                generic: true,
        },
        {
-               name:        "MaskedMaxInt32x8",
+               name:        "MaskedMaxInt8x32",
                argLen:      3,
                commutative: true,
                generic:     true,
        },
        {
-               name:        "MaskedMinInt32x8",
+               name:        "MaskedMinInt8x32",
                argLen:      3,
                commutative: true,
                generic:     true,
        },
        {
-               name:        "MaskedMulLowInt32x8",
+               name:        "MaskedNotEqualInt8x32",
                argLen:      3,
                commutative: true,
                generic:     true,
        },
        {
-               name:        "MaskedNotEqualInt32x8",
-               argLen:      3,
-               commutative: true,
-               generic:     true,
+               name:    "MaskedPopCountInt8x32",
+               argLen:  2,
+               generic: true,
        },
        {
-               name:        "MaskedOrInt32x8",
+               name:        "MaskedSaturatedAddInt8x32",
                argLen:      3,
                commutative: true,
                generic:     true,
        },
        {
-               name:    "MaskedPairDotProdAccumulateInt32x8",
-               argLen:  4,
-               generic: true,
-       },
-       {
-               name:    "MaskedPopCountInt32x8",
-               argLen:  2,
-               generic: true,
-       },
-       {
-               name:    "MaskedSaturatedPairDotProdAccumulateInt32x8",
-               argLen:  4,
-               generic: true,
-       },
-       {
-               name:    "MaskedSaturatedUnsignedSignedQuadDotProdAccumulateInt32x8",
-               argLen:  4,
-               generic: true,
-       },
-       {
-               name:    "MaskedSubInt32x8",
+               name:    "MaskedSaturatedSubInt8x32",
                argLen:  3,
                generic: true,
        },
        {
-               name:    "MaskedUnsignedSignedQuadDotProdAccumulateInt32x8",
-               argLen:  4,
+               name:    "MaskedSubInt8x32",
+               argLen:  3,
                generic: true,
        },
        {
-               name:        "MaskedXorInt32x8",
-               argLen:      3,
-               commutative: true,
-               generic:     true,
-       },
-       {
-               name:        "MaxInt32x8",
+               name:        "MaxInt8x32",
                argLen:      2,
                commutative: true,
                generic:     true,
        },
        {
-               name:        "MinInt32x8",
+               name:        "MinInt8x32",
                argLen:      2,
                commutative: true,
                generic:     true,
        },
        {
-               name:        "MulEvenWidenInt32x8",
+               name:        "NotEqualInt8x32",
                argLen:      2,
                commutative: true,
                generic:     true,
        },
        {
-               name:        "MulLowInt32x8",
+               name:        "OrInt8x32",
                argLen:      2,
                commutative: true,
                generic:     true,
        },
        {
-               name:        "NotEqualInt32x8",
-               argLen:      2,
-               commutative: true,
-               generic:     true,
+               name:    "PopCountInt8x32",
+               argLen:  1,
+               generic: true,
        },
        {
-               name:        "OrInt32x8",
+               name:        "SaturatedAddInt8x32",
                argLen:      2,
                commutative: true,
                generic:     true,
        },
        {
-               name:    "PairDotProdAccumulateInt32x8",
-               argLen:  3,
-               generic: true,
-       },
-       {
-               name:    "PairwiseAddInt32x8",
-               argLen:  2,
-               generic: true,
-       },
-       {
-               name:    "PairwiseSubInt32x8",
+               name:    "SaturatedSubInt8x32",
                argLen:  2,
                generic: true,
        },
        {
-               name:    "PopCountInt32x8",
-               argLen:  1,
-               generic: true,
-       },
-       {
-               name:    "SaturatedPairDotProdAccumulateInt32x8",
-               argLen:  3,
-               generic: true,
-       },
-       {
-               name:    "SaturatedUnsignedSignedQuadDotProdAccumulateInt32x8",
-               argLen:  3,
-               generic: true,
-       },
-       {
-               name:    "SignInt32x8",
+               name:    "SignInt8x32",
                argLen:  2,
                generic: true,
        },
        {
-               name:    "SubInt32x8",
+               name:    "SubInt8x32",
                argLen:  2,
                generic: true,
        },
        {
-               name:    "UnsignedSignedQuadDotProdAccumulateInt32x8",
-               argLen:  3,
-               generic: true,
-       },
-       {
-               name:        "XorInt32x8",
+               name:        "XorInt8x32",
                argLen:      2,
                commutative: true,
                generic:     true,
        },
        {
-               name:    "AbsoluteInt64x2",
+               name:    "AbsoluteInt8x64",
                argLen:  1,
                generic: true,
        },
        {
-               name:        "AddInt64x2",
-               argLen:      2,
-               commutative: true,
-               generic:     true,
-       },
-       {
-               name:        "AndInt64x2",
+               name:        "AddInt8x64",
                argLen:      2,
                commutative: true,
                generic:     true,
        },
        {
-               name:    "AndNotInt64x2",
-               argLen:  2,
-               generic: true,
-       },
-       {
-               name:        "EqualInt64x2",
+               name:        "EqualInt8x64",
                argLen:      2,
                commutative: true,
                generic:     true,
        },
        {
-               name:    "GreaterInt64x2",
+               name:    "GreaterInt8x64",
                argLen:  2,
                generic: true,
        },
        {
-               name:    "GreaterEqualInt64x2",
+               name:    "GreaterEqualInt8x64",
                argLen:  2,
                generic: true,
        },
        {
-               name:    "LessInt64x2",
+               name:    "LessInt8x64",
                argLen:  2,
                generic: true,
        },
        {
-               name:    "LessEqualInt64x2",
+               name:    "LessEqualInt8x64",
                argLen:  2,
                generic: true,
        },
        {
-               name:    "MaskedAbsoluteInt64x2",
+               name:    "MaskedAbsoluteInt8x64",
                argLen:  2,
                generic: true,
        },
        {
-               name:        "MaskedAddInt64x2",
-               argLen:      3,
-               commutative: true,
-               generic:     true,
-       },
-       {
-               name:        "MaskedAndInt64x2",
+               name:        "MaskedAddInt8x64",
                argLen:      3,
                commutative: true,
                generic:     true,
        },
        {
-               name:    "MaskedAndNotInt64x2",
-               argLen:  3,
-               generic: true,
-       },
-       {
-               name:        "MaskedEqualInt64x2",
+               name:        "MaskedEqualInt8x64",
                argLen:      3,
                commutative: true,
                generic:     true,
        },
        {
-               name:    "MaskedGreaterInt64x2",
-               argLen:  3,
-               generic: true,
-       },
-       {
-               name:    "MaskedGreaterEqualInt64x2",
+               name:    "MaskedGreaterInt8x64",
                argLen:  3,
                generic: true,
        },
        {
-               name:    "MaskedLessInt64x2",
+               name:    "MaskedGreaterEqualInt8x64",
                argLen:  3,
                generic: true,
        },
        {
-               name:    "MaskedLessEqualInt64x2",
+               name:    "MaskedLessInt8x64",
                argLen:  3,
                generic: true,
        },
-       {
-               name:        "MaskedMaxInt64x2",
-               argLen:      3,
-               commutative: true,
-               generic:     true,
+       {
+               name:    "MaskedLessEqualInt8x64",
+               argLen:  3,
+               generic: true,
        },
        {
-               name:        "MaskedMinInt64x2",
+               name:        "MaskedMaxInt8x64",
                argLen:      3,
                commutative: true,
                generic:     true,
        },
        {
-               name:        "MaskedMulEvenWidenInt64x2",
+               name:        "MaskedMinInt8x64",
                argLen:      3,
                commutative: true,
                generic:     true,
        },
        {
-               name:        "MaskedMulLowInt64x2",
+               name:        "MaskedNotEqualInt8x64",
                argLen:      3,
                commutative: true,
                generic:     true,
        },
        {
-               name:        "MaskedNotEqualInt64x2",
-               argLen:      3,
-               commutative: true,
-               generic:     true,
+               name:    "MaskedPopCountInt8x64",
+               argLen:  2,
+               generic: true,
        },
        {
-               name:        "MaskedOrInt64x2",
+               name:        "MaskedSaturatedAddInt8x64",
                argLen:      3,
                commutative: true,
                generic:     true,
        },
        {
-               name:    "MaskedPopCountInt64x2",
-               argLen:  2,
+               name:    "MaskedSaturatedSubInt8x64",
+               argLen:  3,
                generic: true,
        },
        {
-               name:    "MaskedSubInt64x2",
+               name:    "MaskedSubInt8x64",
                argLen:  3,
                generic: true,
        },
        {
-               name:        "MaskedXorInt64x2",
-               argLen:      3,
-               commutative: true,
-               generic:     true,
-       },
-       {
-               name:        "MaxInt64x2",
-               argLen:      2,
-               commutative: true,
-               generic:     true,
-       },
-       {
-               name:        "MinInt64x2",
+               name:        "MaxInt8x64",
                argLen:      2,
                commutative: true,
                generic:     true,
        },
        {
-               name:        "MulEvenWidenInt64x2",
+               name:        "MinInt8x64",
                argLen:      2,
                commutative: true,
                generic:     true,
        },
        {
-               name:        "MulLowInt64x2",
+               name:        "NotEqualInt8x64",
                argLen:      2,
                commutative: true,
                generic:     true,
        },
        {
-               name:        "NotEqualInt64x2",
-               argLen:      2,
-               commutative: true,
-               generic:     true,
+               name:    "PopCountInt8x64",
+               argLen:  1,
+               generic: true,
        },
        {
-               name:        "OrInt64x2",
+               name:        "SaturatedAddInt8x64",
                argLen:      2,
                commutative: true,
                generic:     true,
        },
        {
-               name:    "PopCountInt64x2",
-               argLen:  1,
-               generic: true,
-       },
-       {
-               name:    "SubInt64x2",
+               name:    "SaturatedSubInt8x64",
                argLen:  2,
                generic: true,
        },
        {
-               name:        "XorInt64x2",
-               argLen:      2,
-               commutative: true,
-               generic:     true,
-       },
-       {
-               name:    "AbsoluteInt64x4",
-               argLen:  1,
+               name:    "SubInt8x64",
+               argLen:  2,
                generic: true,
        },
        {
-               name:        "AddInt64x4",
+               name:        "AddUint16x16",
                argLen:      2,
                commutative: true,
                generic:     true,
        },
        {
-               name:        "AndInt64x4",
+               name:        "AndUint16x16",
                argLen:      2,
                commutative: true,
                generic:     true,
        },
        {
-               name:    "AndNotInt64x4",
+               name:    "AndNotUint16x16",
                argLen:  2,
                generic: true,
        },
        {
-               name:        "EqualInt64x4",
+               name:        "AverageUint16x16",
                argLen:      2,
                commutative: true,
                generic:     true,
        },
        {
-               name:    "GreaterInt64x4",
-               argLen:  2,
-               generic: true,
+               name:        "EqualUint16x16",
+               argLen:      2,
+               commutative: true,
+               generic:     true,
        },
        {
-               name:    "GreaterEqualInt64x4",
+               name:    "GreaterUint16x16",
                argLen:  2,
                generic: true,
        },
        {
-               name:    "LessInt64x4",
+               name:    "GreaterEqualUint16x16",
                argLen:  2,
                generic: true,
        },
        {
-               name:    "LessEqualInt64x4",
+               name:    "LessUint16x16",
                argLen:  2,
                generic: true,
        },
        {
-               name:    "MaskedAbsoluteInt64x4",
+               name:    "LessEqualUint16x16",
                argLen:  2,
                generic: true,
        },
        {
-               name:        "MaskedAddInt64x4",
+               name:        "MaskedAddUint16x16",
                argLen:      3,
                commutative: true,
                generic:     true,
        },
        {
-               name:        "MaskedAndInt64x4",
+               name:        "MaskedAverageUint16x16",
                argLen:      3,
                commutative: true,
                generic:     true,
        },
        {
-               name:    "MaskedAndNotInt64x4",
-               argLen:  3,
-               generic: true,
-       },
-       {
-               name:        "MaskedEqualInt64x4",
+               name:        "MaskedEqualUint16x16",
                argLen:      3,
                commutative: true,
                generic:     true,
        },
        {
-               name:    "MaskedGreaterInt64x4",
+               name:    "MaskedGreaterUint16x16",
                argLen:  3,
                generic: true,
        },
        {
-               name:    "MaskedGreaterEqualInt64x4",
+               name:    "MaskedGreaterEqualUint16x16",
                argLen:  3,
                generic: true,
        },
        {
-               name:    "MaskedLessInt64x4",
+               name:    "MaskedLessUint16x16",
                argLen:  3,
                generic: true,
        },
        {
-               name:    "MaskedLessEqualInt64x4",
+               name:    "MaskedLessEqualUint16x16",
                argLen:  3,
                generic: true,
        },
        {
-               name:        "MaskedMaxInt64x4",
+               name:        "MaskedMaxUint16x16",
                argLen:      3,
                commutative: true,
                generic:     true,
        },
        {
-               name:        "MaskedMinInt64x4",
+               name:        "MaskedMinUint16x16",
                argLen:      3,
                commutative: true,
                generic:     true,
        },
        {
-               name:        "MaskedMulEvenWidenInt64x4",
+               name:        "MaskedMulHighUint16x16",
                argLen:      3,
                commutative: true,
                generic:     true,
        },
        {
-               name:        "MaskedMulLowInt64x4",
+               name:        "MaskedNotEqualUint16x16",
                argLen:      3,
                commutative: true,
                generic:     true,
        },
        {
-               name:        "MaskedNotEqualInt64x4",
-               argLen:      3,
-               commutative: true,
-               generic:     true,
+               name:    "MaskedPopCountUint16x16",
+               argLen:  2,
+               generic: true,
        },
        {
-               name:        "MaskedOrInt64x4",
+               name:        "MaskedSaturatedAddUint16x16",
                argLen:      3,
                commutative: true,
                generic:     true,
        },
        {
-               name:    "MaskedPopCountInt64x4",
-               argLen:  2,
+               name:    "MaskedSaturatedSubUint16x16",
+               argLen:  3,
                generic: true,
        },
        {
-               name:    "MaskedSubInt64x4",
+               name:    "MaskedShiftLeftUint16x16",
                argLen:  3,
                generic: true,
        },
        {
-               name:        "MaskedXorInt64x4",
-               argLen:      3,
-               commutative: true,
-               generic:     true,
+               name:    "MaskedShiftLeftAndFillUpperFromUint16x16",
+               argLen:  4,
+               generic: true,
        },
        {
-               name:        "MaxInt64x4",
-               argLen:      2,
-               commutative: true,
-               generic:     true,
+               name:    "MaskedShiftRightUint16x16",
+               argLen:  3,
+               generic: true,
        },
        {
-               name:        "MinInt64x4",
+               name:    "MaskedShiftRightAndFillUpperFromUint16x16",
+               argLen:  4,
+               generic: true,
+       },
+       {
+               name:    "MaskedShiftRightSignExtendedUint16x16",
+               argLen:  3,
+               generic: true,
+       },
+       {
+               name:    "MaskedSubUint16x16",
+               argLen:  3,
+               generic: true,
+       },
+       {
+               name:        "MaxUint16x16",
                argLen:      2,
                commutative: true,
                generic:     true,
        },
        {
-               name:        "MulEvenWidenInt64x4",
+               name:        "MinUint16x16",
                argLen:      2,
                commutative: true,
                generic:     true,
        },
        {
-               name:        "MulLowInt64x4",
+               name:        "MulHighUint16x16",
                argLen:      2,
                commutative: true,
                generic:     true,
        },
        {
-               name:        "NotEqualInt64x4",
+               name:        "NotEqualUint16x16",
                argLen:      2,
                commutative: true,
                generic:     true,
        },
        {
-               name:        "OrInt64x4",
+               name:        "OrUint16x16",
                argLen:      2,
                commutative: true,
                generic:     true,
        },
        {
-               name:    "PopCountInt64x4",
-               argLen:  1,
+               name:    "PairwiseAddUint16x16",
+               argLen:  2,
                generic: true,
        },
        {
-               name:    "SubInt64x4",
+               name:    "PairwiseSubUint16x16",
                argLen:  2,
                generic: true,
        },
        {
-               name:        "XorInt64x4",
+               name:    "PopCountUint16x16",
+               argLen:  1,
+               generic: true,
+       },
+       {
+               name:        "SaturatedAddUint16x16",
                argLen:      2,
                commutative: true,
                generic:     true,
        },
        {
-               name:    "AbsoluteInt64x8",
-               argLen:  1,
+               name:    "SaturatedSubUint16x16",
+               argLen:  2,
                generic: true,
        },
        {
-               name:        "AddInt64x8",
+               name:    "ShiftAllLeftUint16x16",
+               argLen:  2,
+               generic: true,
+       },
+       {
+               name:    "ShiftAllRightUint16x16",
+               argLen:  2,
+               generic: true,
+       },
+       {
+               name:    "ShiftLeftUint16x16",
+               argLen:  2,
+               generic: true,
+       },
+       {
+               name:    "ShiftLeftAndFillUpperFromUint16x16",
+               argLen:  3,
+               generic: true,
+       },
+       {
+               name:    "ShiftRightUint16x16",
+               argLen:  2,
+               generic: true,
+       },
+       {
+               name:    "ShiftRightAndFillUpperFromUint16x16",
+               argLen:  3,
+               generic: true,
+       },
+       {
+               name:    "ShiftRightSignExtendedUint16x16",
+               argLen:  2,
+               generic: true,
+       },
+       {
+               name:    "SubUint16x16",
+               argLen:  2,
+               generic: true,
+       },
+       {
+               name:        "XorUint16x16",
                argLen:      2,
                commutative: true,
                generic:     true,
        },
        {
-               name:        "AndInt64x8",
+               name:        "AddUint16x32",
                argLen:      2,
                commutative: true,
                generic:     true,
        },
        {
-               name:    "AndNotInt64x8",
-               argLen:  2,
-               generic: true,
-       },
-       {
-               name:        "EqualInt64x8",
+               name:        "AverageUint16x32",
                argLen:      2,
                commutative: true,
                generic:     true,
        },
        {
-               name:    "GreaterInt64x8",
-               argLen:  2,
-               generic: true,
+               name:        "EqualUint16x32",
+               argLen:      2,
+               commutative: true,
+               generic:     true,
        },
        {
-               name:    "GreaterEqualInt64x8",
+               name:    "GreaterUint16x32",
                argLen:  2,
                generic: true,
        },
        {
-               name:    "LessInt64x8",
+               name:    "GreaterEqualUint16x32",
                argLen:  2,
                generic: true,
        },
        {
-               name:    "LessEqualInt64x8",
+               name:    "LessUint16x32",
                argLen:  2,
                generic: true,
        },
        {
-               name:    "MaskedAbsoluteInt64x8",
+               name:    "LessEqualUint16x32",
                argLen:  2,
                generic: true,
        },
        {
-               name:        "MaskedAddInt64x8",
+               name:        "MaskedAddUint16x32",
                argLen:      3,
                commutative: true,
                generic:     true,
        },
        {
-               name:        "MaskedAndInt64x8",
+               name:        "MaskedAverageUint16x32",
                argLen:      3,
                commutative: true,
                generic:     true,
        },
        {
-               name:    "MaskedAndNotInt64x8",
-               argLen:  3,
-               generic: true,
-       },
-       {
-               name:        "MaskedEqualInt64x8",
+               name:        "MaskedEqualUint16x32",
                argLen:      3,
                commutative: true,
                generic:     true,
        },
        {
-               name:    "MaskedGreaterInt64x8",
+               name:    "MaskedGreaterUint16x32",
                argLen:  3,
                generic: true,
        },
        {
-               name:    "MaskedGreaterEqualInt64x8",
+               name:    "MaskedGreaterEqualUint16x32",
                argLen:  3,
                generic: true,
        },
        {
-               name:    "MaskedLessInt64x8",
+               name:    "MaskedLessUint16x32",
                argLen:  3,
                generic: true,
        },
        {
-               name:    "MaskedLessEqualInt64x8",
+               name:    "MaskedLessEqualUint16x32",
                argLen:  3,
                generic: true,
        },
        {
-               name:        "MaskedMaxInt64x8",
+               name:        "MaskedMaxUint16x32",
                argLen:      3,
                commutative: true,
                generic:     true,
        },
        {
-               name:        "MaskedMinInt64x8",
+               name:        "MaskedMinUint16x32",
                argLen:      3,
                commutative: true,
                generic:     true,
        },
        {
-               name:        "MaskedMulEvenWidenInt64x8",
+               name:        "MaskedMulHighUint16x32",
                argLen:      3,
                commutative: true,
                generic:     true,
        },
        {
-               name:        "MaskedMulLowInt64x8",
+               name:        "MaskedNotEqualUint16x32",
                argLen:      3,
                commutative: true,
                generic:     true,
        },
        {
-               name:        "MaskedNotEqualInt64x8",
-               argLen:      3,
-               commutative: true,
-               generic:     true,
+               name:    "MaskedPopCountUint16x32",
+               argLen:  2,
+               generic: true,
        },
        {
-               name:        "MaskedOrInt64x8",
+               name:        "MaskedSaturatedAddUint16x32",
                argLen:      3,
                commutative: true,
                generic:     true,
        },
        {
-               name:    "MaskedPopCountInt64x8",
-               argLen:  2,
+               name:    "MaskedSaturatedSubUint16x32",
+               argLen:  3,
                generic: true,
        },
        {
-               name:    "MaskedSubInt64x8",
+               name:    "MaskedShiftLeftUint16x32",
                argLen:  3,
                generic: true,
        },
        {
-               name:        "MaskedXorInt64x8",
-               argLen:      3,
-               commutative: true,
-               generic:     true,
+               name:    "MaskedShiftLeftAndFillUpperFromUint16x32",
+               argLen:  4,
+               generic: true,
        },
        {
-               name:        "MaxInt64x8",
-               argLen:      2,
-               commutative: true,
-               generic:     true,
+               name:    "MaskedShiftRightUint16x32",
+               argLen:  3,
+               generic: true,
        },
        {
-               name:        "MinInt64x8",
+               name:    "MaskedShiftRightAndFillUpperFromUint16x32",
+               argLen:  4,
+               generic: true,
+       },
+       {
+               name:    "MaskedShiftRightSignExtendedUint16x32",
+               argLen:  3,
+               generic: true,
+       },
+       {
+               name:    "MaskedSubUint16x32",
+               argLen:  3,
+               generic: true,
+       },
+       {
+               name:        "MaxUint16x32",
                argLen:      2,
                commutative: true,
                generic:     true,
        },
        {
-               name:        "MulEvenWidenInt64x8",
+               name:        "MinUint16x32",
                argLen:      2,
                commutative: true,
                generic:     true,
        },
        {
-               name:        "MulLowInt64x8",
+               name:        "MulHighUint16x32",
                argLen:      2,
                commutative: true,
                generic:     true,
        },
        {
-               name:        "NotEqualInt64x8",
+               name:        "NotEqualUint16x32",
                argLen:      2,
                commutative: true,
                generic:     true,
        },
        {
-               name:        "OrInt64x8",
+               name:    "PopCountUint16x32",
+               argLen:  1,
+               generic: true,
+       },
+       {
+               name:        "SaturatedAddUint16x32",
                argLen:      2,
                commutative: true,
                generic:     true,
        },
        {
-               name:    "PopCountInt64x8",
-               argLen:  1,
+               name:    "SaturatedSubUint16x32",
+               argLen:  2,
                generic: true,
        },
        {
-               name:    "SubInt64x8",
+               name:    "ShiftLeftUint16x32",
                argLen:  2,
                generic: true,
        },
        {
-               name:        "XorInt64x8",
-               argLen:      2,
-               commutative: true,
-               generic:     true,
+               name:    "ShiftLeftAndFillUpperFromUint16x32",
+               argLen:  3,
+               generic: true,
        },
        {
-               name:    "AbsoluteInt8x16",
-               argLen:  1,
+               name:    "ShiftRightUint16x32",
+               argLen:  2,
                generic: true,
        },
        {
-               name:        "AddInt8x16",
+               name:    "ShiftRightAndFillUpperFromUint16x32",
+               argLen:  3,
+               generic: true,
+       },
+       {
+               name:    "ShiftRightSignExtendedUint16x32",
+               argLen:  2,
+               generic: true,
+       },
+       {
+               name:    "SubUint16x32",
+               argLen:  2,
+               generic: true,
+       },
+       {
+               name:        "AddUint16x8",
                argLen:      2,
                commutative: true,
                generic:     true,
        },
        {
-               name:        "AndInt8x16",
+               name:        "AndUint16x8",
                argLen:      2,
                commutative: true,
                generic:     true,
        },
        {
-               name:    "AndNotInt8x16",
+               name:    "AndNotUint16x8",
                argLen:  2,
                generic: true,
        },
        {
-               name:        "EqualInt8x16",
+               name:        "AverageUint16x8",
                argLen:      2,
                commutative: true,
                generic:     true,
        },
        {
-               name:    "GreaterInt8x16",
-               argLen:  2,
-               generic: true,
+               name:        "EqualUint16x8",
+               argLen:      2,
+               commutative: true,
+               generic:     true,
        },
        {
-               name:    "GreaterEqualInt8x16",
+               name:    "GreaterUint16x8",
                argLen:  2,
                generic: true,
        },
        {
-               name:    "LessInt8x16",
+               name:    "GreaterEqualUint16x8",
                argLen:  2,
                generic: true,
        },
        {
-               name:    "LessEqualInt8x16",
+               name:    "LessUint16x8",
                argLen:  2,
                generic: true,
        },
        {
-               name:    "MaskedAbsoluteInt8x16",
+               name:    "LessEqualUint16x8",
                argLen:  2,
                generic: true,
        },
        {
-               name:        "MaskedAddInt8x16",
+               name:        "MaskedAddUint16x8",
                argLen:      3,
                commutative: true,
                generic:     true,
        },
        {
-               name:        "MaskedEqualInt8x16",
+               name:        "MaskedAverageUint16x8",
                argLen:      3,
                commutative: true,
                generic:     true,
        },
        {
-               name:    "MaskedGreaterInt8x16",
+               name:        "MaskedEqualUint16x8",
+               argLen:      3,
+               commutative: true,
+               generic:     true,
+       },
+       {
+               name:    "MaskedGreaterUint16x8",
                argLen:  3,
                generic: true,
        },
        {
-               name:    "MaskedGreaterEqualInt8x16",
+               name:    "MaskedGreaterEqualUint16x8",
                argLen:  3,
                generic: true,
        },
        {
-               name:    "MaskedLessInt8x16",
+               name:    "MaskedLessUint16x8",
                argLen:  3,
                generic: true,
        },
        {
-               name:    "MaskedLessEqualInt8x16",
+               name:    "MaskedLessEqualUint16x8",
                argLen:  3,
                generic: true,
        },
        {
-               name:        "MaskedMaxInt8x16",
+               name:        "MaskedMaxUint16x8",
                argLen:      3,
                commutative: true,
                generic:     true,
        },
        {
-               name:        "MaskedMinInt8x16",
+               name:        "MaskedMinUint16x8",
                argLen:      3,
                commutative: true,
                generic:     true,
        },
        {
-               name:        "MaskedNotEqualInt8x16",
+               name:        "MaskedMulHighUint16x8",
                argLen:      3,
                commutative: true,
                generic:     true,
        },
        {
-               name:    "MaskedPopCountInt8x16",
+               name:        "MaskedNotEqualUint16x8",
+               argLen:      3,
+               commutative: true,
+               generic:     true,
+       },
+       {
+               name:    "MaskedPopCountUint16x8",
                argLen:  2,
                generic: true,
        },
        {
-               name:        "MaskedSaturatedAddInt8x16",
+               name:        "MaskedSaturatedAddUint16x8",
                argLen:      3,
                commutative: true,
                generic:     true,
        },
        {
-               name:    "MaskedSaturatedSubInt8x16",
+               name:    "MaskedSaturatedSubUint16x8",
                argLen:  3,
                generic: true,
        },
        {
-               name:    "MaskedSubInt8x16",
+               name:    "MaskedShiftLeftUint16x8",
                argLen:  3,
                generic: true,
        },
        {
-               name:        "MaxInt8x16",
+               name:    "MaskedShiftLeftAndFillUpperFromUint16x8",
+               argLen:  4,
+               generic: true,
+       },
+       {
+               name:    "MaskedShiftRightUint16x8",
+               argLen:  3,
+               generic: true,
+       },
+       {
+               name:    "MaskedShiftRightAndFillUpperFromUint16x8",
+               argLen:  4,
+               generic: true,
+       },
+       {
+               name:    "MaskedShiftRightSignExtendedUint16x8",
+               argLen:  3,
+               generic: true,
+       },
+       {
+               name:    "MaskedSubUint16x8",
+               argLen:  3,
+               generic: true,
+       },
+       {
+               name:        "MaxUint16x8",
                argLen:      2,
                commutative: true,
                generic:     true,
        },
        {
-               name:        "MinInt8x16",
+               name:        "MinUint16x8",
                argLen:      2,
                commutative: true,
                generic:     true,
        },
        {
-               name:        "NotEqualInt8x16",
+               name:        "MulHighUint16x8",
                argLen:      2,
                commutative: true,
                generic:     true,
        },
        {
-               name:        "OrInt8x16",
+               name:        "NotEqualUint16x8",
                argLen:      2,
                commutative: true,
                generic:     true,
        },
        {
-               name:    "PopCountInt8x16",
-               argLen:  1,
-               generic: true,
-       },
-       {
-               name:        "SaturatedAddInt8x16",
+               name:        "OrUint16x8",
                argLen:      2,
                commutative: true,
                generic:     true,
        },
        {
-               name:    "SaturatedSubInt8x16",
-               argLen:  2,
-               generic: true,
-       },
-       {
-               name:    "SignInt8x16",
+               name:    "PairwiseAddUint16x8",
                argLen:  2,
                generic: true,
        },
        {
-               name:    "SubInt8x16",
+               name:    "PairwiseSubUint16x8",
                argLen:  2,
                generic: true,
        },
        {
-               name:        "XorInt8x16",
-               argLen:      2,
-               commutative: true,
-               generic:     true,
-       },
-       {
-               name:    "AbsoluteInt8x32",
+               name:    "PopCountUint16x8",
                argLen:  1,
                generic: true,
        },
        {
-               name:        "AddInt8x32",
-               argLen:      2,
-               commutative: true,
-               generic:     true,
-       },
-       {
-               name:        "AndInt8x32",
+               name:        "SaturatedAddUint16x8",
                argLen:      2,
                commutative: true,
                generic:     true,
        },
        {
-               name:    "AndNotInt8x32",
+               name:    "SaturatedSubUint16x8",
                argLen:  2,
                generic: true,
        },
        {
-               name:        "EqualInt8x32",
-               argLen:      2,
-               commutative: true,
-               generic:     true,
-       },
-       {
-               name:    "GreaterInt8x32",
+               name:    "ShiftAllLeftUint16x8",
                argLen:  2,
                generic: true,
        },
        {
-               name:    "GreaterEqualInt8x32",
+               name:    "ShiftAllRightUint16x8",
                argLen:  2,
                generic: true,
        },
        {
-               name:    "LessInt8x32",
+               name:    "ShiftLeftUint16x8",
                argLen:  2,
                generic: true,
        },
        {
-               name:    "LessEqualInt8x32",
-               argLen:  2,
+               name:    "ShiftLeftAndFillUpperFromUint16x8",
+               argLen:  3,
                generic: true,
        },
        {
-               name:    "MaskedAbsoluteInt8x32",
+               name:    "ShiftRightUint16x8",
                argLen:  2,
                generic: true,
        },
        {
-               name:        "MaskedAddInt8x32",
-               argLen:      3,
-               commutative: true,
-               generic:     true,
-       },
-       {
-               name:        "MaskedEqualInt8x32",
-               argLen:      3,
-               commutative: true,
-               generic:     true,
-       },
-       {
-               name:    "MaskedGreaterInt8x32",
-               argLen:  3,
-               generic: true,
-       },
-       {
-               name:    "MaskedGreaterEqualInt8x32",
+               name:    "ShiftRightAndFillUpperFromUint16x8",
                argLen:  3,
                generic: true,
        },
        {
-               name:    "MaskedLessInt8x32",
-               argLen:  3,
+               name:    "ShiftRightSignExtendedUint16x8",
+               argLen:  2,
                generic: true,
        },
        {
-               name:    "MaskedLessEqualInt8x32",
-               argLen:  3,
+               name:    "SubUint16x8",
+               argLen:  2,
                generic: true,
        },
        {
-               name:        "MaskedMaxInt8x32",
-               argLen:      3,
+               name:        "XorUint16x8",
+               argLen:      2,
                commutative: true,
                generic:     true,
        },
        {
-               name:        "MaskedMinInt8x32",
-               argLen:      3,
+               name:        "AddUint32x16",
+               argLen:      2,
                commutative: true,
                generic:     true,
        },
        {
-               name:        "MaskedNotEqualInt8x32",
-               argLen:      3,
+               name:        "AndUint32x16",
+               argLen:      2,
                commutative: true,
                generic:     true,
        },
        {
-               name:    "MaskedPopCountInt8x32",
+               name:    "AndNotUint32x16",
                argLen:  2,
                generic: true,
        },
        {
-               name:        "MaskedSaturatedAddInt8x32",
-               argLen:      3,
+               name:        "EqualUint32x16",
+               argLen:      2,
                commutative: true,
                generic:     true,
        },
        {
-               name:    "MaskedSaturatedSubInt8x32",
-               argLen:  3,
+               name:    "GreaterUint32x16",
+               argLen:  2,
                generic: true,
        },
        {
-               name:    "MaskedSubInt8x32",
-               argLen:  3,
+               name:    "GreaterEqualUint32x16",
+               argLen:  2,
                generic: true,
        },
        {
-               name:        "MaxInt8x32",
-               argLen:      2,
-               commutative: true,
-               generic:     true,
+               name:    "LessUint32x16",
+               argLen:  2,
+               generic: true,
        },
        {
-               name:        "MinInt8x32",
-               argLen:      2,
-               commutative: true,
-               generic:     true,
+               name:    "LessEqualUint32x16",
+               argLen:  2,
+               generic: true,
        },
        {
-               name:        "NotEqualInt8x32",
-               argLen:      2,
+               name:        "MaskedAddUint32x16",
+               argLen:      3,
                commutative: true,
                generic:     true,
        },
        {
-               name:        "OrInt8x32",
-               argLen:      2,
+               name:        "MaskedAndUint32x16",
+               argLen:      3,
                commutative: true,
                generic:     true,
        },
        {
-               name:    "PopCountInt8x32",
-               argLen:  1,
+               name:    "MaskedAndNotUint32x16",
+               argLen:  3,
                generic: true,
        },
        {
-               name:        "SaturatedAddInt8x32",
-               argLen:      2,
+               name:        "MaskedEqualUint32x16",
+               argLen:      3,
                commutative: true,
                generic:     true,
        },
        {
-               name:    "SaturatedSubInt8x32",
-               argLen:  2,
+               name:    "MaskedGreaterUint32x16",
+               argLen:  3,
                generic: true,
        },
        {
-               name:    "SignInt8x32",
-               argLen:  2,
+               name:    "MaskedGreaterEqualUint32x16",
+               argLen:  3,
                generic: true,
        },
        {
-               name:    "SubInt8x32",
-               argLen:  2,
+               name:    "MaskedLessUint32x16",
+               argLen:  3,
                generic: true,
        },
        {
-               name:        "XorInt8x32",
-               argLen:      2,
+               name:    "MaskedLessEqualUint32x16",
+               argLen:  3,
+               generic: true,
+       },
+       {
+               name:        "MaskedMaxUint32x16",
+               argLen:      3,
                commutative: true,
                generic:     true,
        },
        {
-               name:    "AbsoluteInt8x64",
-               argLen:  1,
-               generic: true,
+               name:        "MaskedMinUint32x16",
+               argLen:      3,
+               commutative: true,
+               generic:     true,
        },
        {
-               name:        "AddInt8x64",
-               argLen:      2,
+               name:        "MaskedNotEqualUint32x16",
+               argLen:      3,
                commutative: true,
                generic:     true,
        },
        {
-               name:        "EqualInt8x64",
-               argLen:      2,
+               name:        "MaskedOrUint32x16",
+               argLen:      3,
                commutative: true,
                generic:     true,
        },
        {
-               name:    "GreaterInt8x64",
+               name:    "MaskedPopCountUint32x16",
                argLen:  2,
                generic: true,
        },
        {
-               name:    "GreaterEqualInt8x64",
-               argLen:  2,
+               name:    "MaskedRotateLeftUint32x16",
+               argLen:  3,
                generic: true,
        },
        {
-               name:    "LessInt8x64",
-               argLen:  2,
+               name:    "MaskedRotateRightUint32x16",
+               argLen:  3,
                generic: true,
        },
        {
-               name:    "LessEqualInt8x64",
-               argLen:  2,
+               name:    "MaskedSaturatedUnsignedSignedQuadDotProdAccumulateUint32x16",
+               argLen:  4,
                generic: true,
        },
        {
-               name:    "MaskedAbsoluteInt8x64",
-               argLen:  2,
+               name:    "MaskedShiftLeftUint32x16",
+               argLen:  3,
                generic: true,
        },
        {
-               name:        "MaskedAddInt8x64",
-               argLen:      3,
-               commutative: true,
-               generic:     true,
+               name:    "MaskedShiftLeftAndFillUpperFromUint32x16",
+               argLen:  4,
+               generic: true,
        },
        {
-               name:        "MaskedEqualInt8x64",
-               argLen:      3,
-               commutative: true,
-               generic:     true,
+               name:    "MaskedShiftRightUint32x16",
+               argLen:  3,
+               generic: true,
        },
        {
-               name:    "MaskedGreaterInt8x64",
-               argLen:  3,
+               name:    "MaskedShiftRightAndFillUpperFromUint32x16",
+               argLen:  4,
                generic: true,
        },
        {
-               name:    "MaskedGreaterEqualInt8x64",
+               name:    "MaskedShiftRightSignExtendedUint32x16",
                argLen:  3,
                generic: true,
        },
        {
-               name:    "MaskedLessInt8x64",
+               name:    "MaskedSubUint32x16",
                argLen:  3,
                generic: true,
        },
        {
-               name:    "MaskedLessEqualInt8x64",
-               argLen:  3,
+               name:    "MaskedUnsignedSignedQuadDotProdAccumulateUint32x16",
+               argLen:  4,
                generic: true,
        },
        {
-               name:        "MaskedMaxInt8x64",
+               name:        "MaskedXorUint32x16",
                argLen:      3,
                commutative: true,
                generic:     true,
        },
        {
-               name:        "MaskedMinInt8x64",
-               argLen:      3,
+               name:        "MaxUint32x16",
+               argLen:      2,
                commutative: true,
                generic:     true,
        },
        {
-               name:        "MaskedNotEqualInt8x64",
-               argLen:      3,
+               name:        "MinUint32x16",
+               argLen:      2,
                commutative: true,
                generic:     true,
        },
        {
-               name:    "MaskedPopCountInt8x64",
-               argLen:  2,
-               generic: true,
+               name:        "NotEqualUint32x16",
+               argLen:      2,
+               commutative: true,
+               generic:     true,
        },
        {
-               name:        "MaskedSaturatedAddInt8x64",
-               argLen:      3,
+               name:        "OrUint32x16",
+               argLen:      2,
                commutative: true,
                generic:     true,
        },
        {
-               name:    "MaskedSaturatedSubInt8x64",
-               argLen:  3,
+               name:    "PopCountUint32x16",
+               argLen:  1,
                generic: true,
        },
        {
-               name:    "MaskedSubInt8x64",
-               argLen:  3,
+               name:    "RotateLeftUint32x16",
+               argLen:  2,
                generic: true,
        },
        {
-               name:        "MaxInt8x64",
-               argLen:      2,
-               commutative: true,
-               generic:     true,
+               name:    "RotateRightUint32x16",
+               argLen:  2,
+               generic: true,
        },
        {
-               name:        "MinInt8x64",
-               argLen:      2,
-               commutative: true,
-               generic:     true,
+               name:    "SaturatedUnsignedSignedQuadDotProdAccumulateUint32x16",
+               argLen:  3,
+               generic: true,
        },
        {
-               name:        "NotEqualInt8x64",
-               argLen:      2,
-               commutative: true,
-               generic:     true,
+               name:    "ShiftLeftUint32x16",
+               argLen:  2,
+               generic: true,
        },
        {
-               name:    "PopCountInt8x64",
-               argLen:  1,
+               name:    "ShiftLeftAndFillUpperFromUint32x16",
+               argLen:  3,
                generic: true,
        },
        {
-               name:        "SaturatedAddInt8x64",
-               argLen:      2,
-               commutative: true,
-               generic:     true,
+               name:    "ShiftRightUint32x16",
+               argLen:  2,
+               generic: true,
        },
        {
-               name:    "SaturatedSubInt8x64",
+               name:    "ShiftRightAndFillUpperFromUint32x16",
+               argLen:  3,
+               generic: true,
+       },
+       {
+               name:    "ShiftRightSignExtendedUint32x16",
                argLen:  2,
                generic: true,
        },
        {
-               name:    "SubInt8x64",
+               name:    "SubUint32x16",
                argLen:  2,
                generic: true,
        },
        {
-               name:        "AddUint16x16",
+               name:    "UnsignedSignedQuadDotProdAccumulateUint32x16",
+               argLen:  3,
+               generic: true,
+       },
+       {
+               name:        "XorUint32x16",
                argLen:      2,
                commutative: true,
                generic:     true,
        },
        {
-               name:        "AndUint16x16",
+               name:        "AddUint32x4",
                argLen:      2,
                commutative: true,
                generic:     true,
        },
        {
-               name:    "AndNotUint16x16",
-               argLen:  2,
-               generic: true,
-       },
-       {
-               name:        "AverageUint16x16",
+               name:        "AndUint32x4",
                argLen:      2,
                commutative: true,
                generic:     true,
        },
        {
-               name:        "EqualUint16x16",
+               name:    "AndNotUint32x4",
+               argLen:  2,
+               generic: true,
+       },
+       {
+               name:        "EqualUint32x4",
                argLen:      2,
                commutative: true,
                generic:     true,
        },
        {
-               name:    "GreaterUint16x16",
+               name:    "GreaterUint32x4",
                argLen:  2,
                generic: true,
        },
        {
-               name:    "GreaterEqualUint16x16",
+               name:    "GreaterEqualUint32x4",
                argLen:  2,
                generic: true,
        },
        {
-               name:    "LessUint16x16",
+               name:    "LessUint32x4",
                argLen:  2,
                generic: true,
        },
        {
-               name:    "LessEqualUint16x16",
+               name:    "LessEqualUint32x4",
                argLen:  2,
                generic: true,
        },
        {
-               name:        "MaskedAddUint16x16",
+               name:        "MaskedAddUint32x4",
                argLen:      3,
                commutative: true,
                generic:     true,
        },
        {
-               name:        "MaskedAverageUint16x16",
+               name:        "MaskedAndUint32x4",
                argLen:      3,
                commutative: true,
                generic:     true,
        },
        {
-               name:        "MaskedEqualUint16x16",
+               name:    "MaskedAndNotUint32x4",
+               argLen:  3,
+               generic: true,
+       },
+       {
+               name:        "MaskedEqualUint32x4",
                argLen:      3,
                commutative: true,
                generic:     true,
        },
        {
-               name:    "MaskedGreaterUint16x16",
+               name:    "MaskedGreaterUint32x4",
                argLen:  3,
                generic: true,
        },
        {
-               name:    "MaskedGreaterEqualUint16x16",
+               name:    "MaskedGreaterEqualUint32x4",
                argLen:  3,
                generic: true,
        },
        {
-               name:    "MaskedLessUint16x16",
+               name:    "MaskedLessUint32x4",
                argLen:  3,
                generic: true,
        },
        {
-               name:    "MaskedLessEqualUint16x16",
+               name:    "MaskedLessEqualUint32x4",
                argLen:  3,
                generic: true,
        },
        {
-               name:        "MaskedMaxUint16x16",
+               name:        "MaskedMaxUint32x4",
                argLen:      3,
                commutative: true,
                generic:     true,
        },
        {
-               name:        "MaskedMinUint16x16",
+               name:        "MaskedMinUint32x4",
                argLen:      3,
                commutative: true,
                generic:     true,
        },
        {
-               name:        "MaskedMulHighUint16x16",
+               name:        "MaskedNotEqualUint32x4",
                argLen:      3,
                commutative: true,
                generic:     true,
        },
        {
-               name:        "MaskedNotEqualUint16x16",
+               name:        "MaskedOrUint32x4",
                argLen:      3,
                commutative: true,
                generic:     true,
        },
        {
-               name:    "MaskedPopCountUint16x16",
+               name:    "MaskedPopCountUint32x4",
                argLen:  2,
                generic: true,
        },
        {
-               name:        "MaskedSaturatedAddUint16x16",
-               argLen:      3,
-               commutative: true,
-               generic:     true,
+               name:    "MaskedRotateLeftUint32x4",
+               argLen:  3,
+               generic: true,
        },
        {
-               name:    "MaskedSaturatedSubUint16x16",
+               name:    "MaskedRotateRightUint32x4",
                argLen:  3,
                generic: true,
        },
        {
-               name:    "MaskedSubUint16x16",
+               name:    "MaskedSaturatedUnsignedSignedQuadDotProdAccumulateUint32x4",
+               argLen:  4,
+               generic: true,
+       },
+       {
+               name:    "MaskedShiftLeftUint32x4",
                argLen:  3,
                generic: true,
        },
        {
-               name:        "MaxUint16x16",
+               name:    "MaskedShiftLeftAndFillUpperFromUint32x4",
+               argLen:  4,
+               generic: true,
+       },
+       {
+               name:    "MaskedShiftRightUint32x4",
+               argLen:  3,
+               generic: true,
+       },
+       {
+               name:    "MaskedShiftRightAndFillUpperFromUint32x4",
+               argLen:  4,
+               generic: true,
+       },
+       {
+               name:    "MaskedShiftRightSignExtendedUint32x4",
+               argLen:  3,
+               generic: true,
+       },
+       {
+               name:    "MaskedSubUint32x4",
+               argLen:  3,
+               generic: true,
+       },
+       {
+               name:    "MaskedUnsignedSignedQuadDotProdAccumulateUint32x4",
+               argLen:  4,
+               generic: true,
+       },
+       {
+               name:        "MaskedXorUint32x4",
+               argLen:      3,
+               commutative: true,
+               generic:     true,
+       },
+       {
+               name:        "MaxUint32x4",
                argLen:      2,
                commutative: true,
                generic:     true,
        },
        {
-               name:        "MinUint16x16",
+               name:        "MinUint32x4",
                argLen:      2,
                commutative: true,
                generic:     true,
        },
        {
-               name:        "MulHighUint16x16",
+               name:        "MulEvenWidenUint32x4",
                argLen:      2,
                commutative: true,
                generic:     true,
        },
        {
-               name:        "NotEqualUint16x16",
+               name:        "NotEqualUint32x4",
                argLen:      2,
                commutative: true,
                generic:     true,
        },
        {
-               name:        "OrUint16x16",
+               name:        "OrUint32x4",
                argLen:      2,
                commutative: true,
                generic:     true,
        },
        {
-               name:    "PairwiseAddUint16x16",
+               name:    "PairwiseAddUint32x4",
                argLen:  2,
                generic: true,
        },
        {
-               name:    "PairwiseSubUint16x16",
+               name:    "PairwiseSubUint32x4",
                argLen:  2,
                generic: true,
        },
        {
-               name:    "PopCountUint16x16",
+               name:    "PopCountUint32x4",
                argLen:  1,
                generic: true,
        },
        {
-               name:        "SaturatedAddUint16x16",
-               argLen:      2,
-               commutative: true,
-               generic:     true,
+               name:    "RotateLeftUint32x4",
+               argLen:  2,
+               generic: true,
        },
        {
-               name:    "SaturatedSubUint16x16",
+               name:    "RotateRightUint32x4",
                argLen:  2,
                generic: true,
        },
        {
-               name:    "SubUint16x16",
+               name:    "SaturatedUnsignedSignedQuadDotProdAccumulateUint32x4",
+               argLen:  3,
+               generic: true,
+       },
+       {
+               name:    "ShiftAllLeftUint32x4",
                argLen:  2,
                generic: true,
        },
        {
-               name:        "XorUint16x16",
+               name:    "ShiftAllRightUint32x4",
+               argLen:  2,
+               generic: true,
+       },
+       {
+               name:    "ShiftLeftUint32x4",
+               argLen:  2,
+               generic: true,
+       },
+       {
+               name:    "ShiftLeftAndFillUpperFromUint32x4",
+               argLen:  3,
+               generic: true,
+       },
+       {
+               name:    "ShiftRightUint32x4",
+               argLen:  2,
+               generic: true,
+       },
+       {
+               name:    "ShiftRightAndFillUpperFromUint32x4",
+               argLen:  3,
+               generic: true,
+       },
+       {
+               name:    "ShiftRightSignExtendedUint32x4",
+               argLen:  2,
+               generic: true,
+       },
+       {
+               name:    "SubUint32x4",
+               argLen:  2,
+               generic: true,
+       },
+       {
+               name:    "UnsignedSignedQuadDotProdAccumulateUint32x4",
+               argLen:  3,
+               generic: true,
+       },
+       {
+               name:        "XorUint32x4",
                argLen:      2,
                commutative: true,
                generic:     true,
        },
        {
-               name:        "AddUint16x32",
+               name:        "AddUint32x8",
                argLen:      2,
                commutative: true,
                generic:     true,
        },
        {
-               name:        "AverageUint16x32",
+               name:        "AndUint32x8",
                argLen:      2,
                commutative: true,
                generic:     true,
        },
        {
-               name:        "EqualUint16x32",
+               name:    "AndNotUint32x8",
+               argLen:  2,
+               generic: true,
+       },
+       {
+               name:        "EqualUint32x8",
                argLen:      2,
                commutative: true,
                generic:     true,
        },
        {
-               name:    "GreaterUint16x32",
+               name:    "GreaterUint32x8",
                argLen:  2,
                generic: true,
        },
        {
-               name:    "GreaterEqualUint16x32",
+               name:    "GreaterEqualUint32x8",
                argLen:  2,
                generic: true,
        },
        {
-               name:    "LessUint16x32",
+               name:    "LessUint32x8",
                argLen:  2,
                generic: true,
        },
        {
-               name:    "LessEqualUint16x32",
+               name:    "LessEqualUint32x8",
                argLen:  2,
                generic: true,
        },
        {
-               name:        "MaskedAddUint16x32",
+               name:        "MaskedAddUint32x8",
                argLen:      3,
                commutative: true,
                generic:     true,
        },
        {
-               name:        "MaskedAverageUint16x32",
+               name:        "MaskedAndUint32x8",
                argLen:      3,
                commutative: true,
                generic:     true,
        },
        {
-               name:        "MaskedEqualUint16x32",
+               name:    "MaskedAndNotUint32x8",
+               argLen:  3,
+               generic: true,
+       },
+       {
+               name:        "MaskedEqualUint32x8",
                argLen:      3,
                commutative: true,
                generic:     true,
        },
        {
-               name:    "MaskedGreaterUint16x32",
+               name:    "MaskedGreaterUint32x8",
                argLen:  3,
                generic: true,
        },
        {
-               name:    "MaskedGreaterEqualUint16x32",
+               name:    "MaskedGreaterEqualUint32x8",
                argLen:  3,
                generic: true,
        },
        {
-               name:    "MaskedLessUint16x32",
+               name:    "MaskedLessUint32x8",
                argLen:  3,
                generic: true,
        },
        {
-               name:    "MaskedLessEqualUint16x32",
+               name:    "MaskedLessEqualUint32x8",
                argLen:  3,
                generic: true,
        },
        {
-               name:        "MaskedMaxUint16x32",
+               name:        "MaskedMaxUint32x8",
                argLen:      3,
                commutative: true,
                generic:     true,
        },
        {
-               name:        "MaskedMinUint16x32",
+               name:        "MaskedMinUint32x8",
                argLen:      3,
                commutative: true,
                generic:     true,
        },
        {
-               name:        "MaskedMulHighUint16x32",
+               name:        "MaskedNotEqualUint32x8",
                argLen:      3,
                commutative: true,
                generic:     true,
        },
        {
-               name:        "MaskedNotEqualUint16x32",
+               name:        "MaskedOrUint32x8",
                argLen:      3,
                commutative: true,
                generic:     true,
        },
        {
-               name:    "MaskedPopCountUint16x32",
+               name:    "MaskedPopCountUint32x8",
                argLen:  2,
                generic: true,
        },
        {
-               name:        "MaskedSaturatedAddUint16x32",
-               argLen:      3,
-               commutative: true,
-               generic:     true,
+               name:    "MaskedRotateLeftUint32x8",
+               argLen:  3,
+               generic: true,
        },
        {
-               name:    "MaskedSaturatedSubUint16x32",
+               name:    "MaskedRotateRightUint32x8",
                argLen:  3,
                generic: true,
        },
        {
-               name:    "MaskedSubUint16x32",
+               name:    "MaskedSaturatedUnsignedSignedQuadDotProdAccumulateUint32x8",
+               argLen:  4,
+               generic: true,
+       },
+       {
+               name:    "MaskedShiftLeftUint32x8",
                argLen:  3,
                generic: true,
        },
        {
-               name:        "MaxUint16x32",
+               name:    "MaskedShiftLeftAndFillUpperFromUint32x8",
+               argLen:  4,
+               generic: true,
+       },
+       {
+               name:    "MaskedShiftRightUint32x8",
+               argLen:  3,
+               generic: true,
+       },
+       {
+               name:    "MaskedShiftRightAndFillUpperFromUint32x8",
+               argLen:  4,
+               generic: true,
+       },
+       {
+               name:    "MaskedShiftRightSignExtendedUint32x8",
+               argLen:  3,
+               generic: true,
+       },
+       {
+               name:    "MaskedSubUint32x8",
+               argLen:  3,
+               generic: true,
+       },
+       {
+               name:    "MaskedUnsignedSignedQuadDotProdAccumulateUint32x8",
+               argLen:  4,
+               generic: true,
+       },
+       {
+               name:        "MaskedXorUint32x8",
+               argLen:      3,
+               commutative: true,
+               generic:     true,
+       },
+       {
+               name:        "MaxUint32x8",
                argLen:      2,
                commutative: true,
                generic:     true,
        },
        {
-               name:        "MinUint16x32",
+               name:        "MinUint32x8",
                argLen:      2,
                commutative: true,
                generic:     true,
        },
        {
-               name:        "MulHighUint16x32",
+               name:        "MulEvenWidenUint32x8",
+               argLen:      2,
+               commutative: true,
+               generic:     true,
+       },
+       {
+               name:        "NotEqualUint32x8",
+               argLen:      2,
+               commutative: true,
+               generic:     true,
+       },
+       {
+               name:        "OrUint32x8",
                argLen:      2,
                commutative: true,
                generic:     true,
        },
        {
-               name:        "NotEqualUint16x32",
-               argLen:      2,
-               commutative: true,
-               generic:     true,
+               name:    "PairwiseAddUint32x8",
+               argLen:  2,
+               generic: true,
+       },
+       {
+               name:    "PairwiseSubUint32x8",
+               argLen:  2,
+               generic: true,
+       },
+       {
+               name:    "PopCountUint32x8",
+               argLen:  1,
+               generic: true,
+       },
+       {
+               name:    "RotateLeftUint32x8",
+               argLen:  2,
+               generic: true,
+       },
+       {
+               name:    "RotateRightUint32x8",
+               argLen:  2,
+               generic: true,
+       },
+       {
+               name:    "SaturatedUnsignedSignedQuadDotProdAccumulateUint32x8",
+               argLen:  3,
+               generic: true,
+       },
+       {
+               name:    "ShiftAllLeftUint32x8",
+               argLen:  2,
+               generic: true,
+       },
+       {
+               name:    "ShiftAllRightUint32x8",
+               argLen:  2,
+               generic: true,
+       },
+       {
+               name:    "ShiftLeftUint32x8",
+               argLen:  2,
+               generic: true,
+       },
+       {
+               name:    "ShiftLeftAndFillUpperFromUint32x8",
+               argLen:  3,
+               generic: true,
        },
        {
-               name:    "PopCountUint16x32",
-               argLen:  1,
+               name:    "ShiftRightUint32x8",
+               argLen:  2,
                generic: true,
        },
        {
-               name:        "SaturatedAddUint16x32",
-               argLen:      2,
-               commutative: true,
-               generic:     true,
+               name:    "ShiftRightAndFillUpperFromUint32x8",
+               argLen:  3,
+               generic: true,
        },
        {
-               name:    "SaturatedSubUint16x32",
+               name:    "ShiftRightSignExtendedUint32x8",
                argLen:  2,
                generic: true,
        },
        {
-               name:    "SubUint16x32",
+               name:    "SubUint32x8",
                argLen:  2,
                generic: true,
        },
        {
-               name:        "AddUint16x8",
+               name:    "UnsignedSignedQuadDotProdAccumulateUint32x8",
+               argLen:  3,
+               generic: true,
+       },
+       {
+               name:        "XorUint32x8",
                argLen:      2,
                commutative: true,
                generic:     true,
        },
        {
-               name:        "AndUint16x8",
+               name:        "AddUint64x2",
                argLen:      2,
                commutative: true,
                generic:     true,
        },
        {
-               name:    "AndNotUint16x8",
-               argLen:  2,
-               generic: true,
-       },
-       {
-               name:        "AverageUint16x8",
+               name:        "AndUint64x2",
                argLen:      2,
                commutative: true,
                generic:     true,
        },
        {
-               name:        "EqualUint16x8",
+               name:    "AndNotUint64x2",
+               argLen:  2,
+               generic: true,
+       },
+       {
+               name:        "EqualUint64x2",
                argLen:      2,
                commutative: true,
                generic:     true,
        },
        {
-               name:    "GreaterUint16x8",
+               name:    "GreaterUint64x2",
                argLen:  2,
                generic: true,
        },
        {
-               name:    "GreaterEqualUint16x8",
+               name:    "GreaterEqualUint64x2",
                argLen:  2,
                generic: true,
        },
        {
-               name:    "LessUint16x8",
+               name:    "LessUint64x2",
                argLen:  2,
                generic: true,
        },
        {
-               name:    "LessEqualUint16x8",
+               name:    "LessEqualUint64x2",
                argLen:  2,
                generic: true,
        },
        {
-               name:        "MaskedAddUint16x8",
+               name:        "MaskedAddUint64x2",
                argLen:      3,
                commutative: true,
                generic:     true,
        },
        {
-               name:        "MaskedAverageUint16x8",
+               name:        "MaskedAndUint64x2",
                argLen:      3,
                commutative: true,
                generic:     true,
        },
        {
-               name:        "MaskedEqualUint16x8",
+               name:    "MaskedAndNotUint64x2",
+               argLen:  3,
+               generic: true,
+       },
+       {
+               name:        "MaskedEqualUint64x2",
                argLen:      3,
                commutative: true,
                generic:     true,
        },
        {
-               name:    "MaskedGreaterUint16x8",
+               name:    "MaskedGreaterUint64x2",
                argLen:  3,
                generic: true,
        },
        {
-               name:    "MaskedGreaterEqualUint16x8",
+               name:    "MaskedGreaterEqualUint64x2",
                argLen:  3,
                generic: true,
        },
        {
-               name:    "MaskedLessUint16x8",
+               name:    "MaskedLessUint64x2",
                argLen:  3,
                generic: true,
        },
        {
-               name:    "MaskedLessEqualUint16x8",
+               name:    "MaskedLessEqualUint64x2",
                argLen:  3,
                generic: true,
        },
        {
-               name:        "MaskedMaxUint16x8",
+               name:        "MaskedMaxUint64x2",
                argLen:      3,
                commutative: true,
                generic:     true,
        },
        {
-               name:        "MaskedMinUint16x8",
+               name:        "MaskedMinUint64x2",
                argLen:      3,
                commutative: true,
                generic:     true,
        },
        {
-               name:        "MaskedMulHighUint16x8",
+               name:        "MaskedMulEvenWidenUint64x2",
                argLen:      3,
                commutative: true,
                generic:     true,
        },
        {
-               name:        "MaskedNotEqualUint16x8",
+               name:        "MaskedNotEqualUint64x2",
                argLen:      3,
                commutative: true,
                generic:     true,
        },
        {
-               name:    "MaskedPopCountUint16x8",
+               name:        "MaskedOrUint64x2",
+               argLen:      3,
+               commutative: true,
+               generic:     true,
+       },
+       {
+               name:    "MaskedPopCountUint64x2",
                argLen:  2,
                generic: true,
        },
        {
-               name:        "MaskedSaturatedAddUint16x8",
-               argLen:      3,
-               commutative: true,
-               generic:     true,
+               name:    "MaskedRotateLeftUint64x2",
+               argLen:  3,
+               generic: true,
        },
        {
-               name:    "MaskedSaturatedSubUint16x8",
+               name:    "MaskedRotateRightUint64x2",
                argLen:  3,
                generic: true,
        },
        {
-               name:    "MaskedSubUint16x8",
+               name:    "MaskedShiftAllLeftUint64x2",
                argLen:  3,
                generic: true,
        },
        {
-               name:        "MaxUint16x8",
+               name:    "MaskedShiftAllRightUint64x2",
+               argLen:  3,
+               generic: true,
+       },
+       {
+               name:    "MaskedShiftLeftUint64x2",
+               argLen:  3,
+               generic: true,
+       },
+       {
+               name:    "MaskedShiftLeftAndFillUpperFromUint64x2",
+               argLen:  4,
+               generic: true,
+       },
+       {
+               name:    "MaskedShiftRightUint64x2",
+               argLen:  3,
+               generic: true,
+       },
+       {
+               name:    "MaskedShiftRightAndFillUpperFromUint64x2",
+               argLen:  4,
+               generic: true,
+       },
+       {
+               name:    "MaskedShiftRightSignExtendedUint64x2",
+               argLen:  3,
+               generic: true,
+       },
+       {
+               name:    "MaskedSubUint64x2",
+               argLen:  3,
+               generic: true,
+       },
+       {
+               name:        "MaskedXorUint64x2",
+               argLen:      3,
+               commutative: true,
+               generic:     true,
+       },
+       {
+               name:        "MaxUint64x2",
                argLen:      2,
                commutative: true,
                generic:     true,
        },
        {
-               name:        "MinUint16x8",
+               name:        "MinUint64x2",
                argLen:      2,
                commutative: true,
                generic:     true,
        },
        {
-               name:        "MulHighUint16x8",
+               name:        "MulEvenWidenUint64x2",
                argLen:      2,
                commutative: true,
                generic:     true,
        },
        {
-               name:        "NotEqualUint16x8",
+               name:        "NotEqualUint64x2",
                argLen:      2,
                commutative: true,
                generic:     true,
        },
        {
-               name:        "OrUint16x8",
+               name:        "OrUint64x2",
                argLen:      2,
                commutative: true,
                generic:     true,
        },
        {
-               name:    "PairwiseAddUint16x8",
+               name:    "PopCountUint64x2",
+               argLen:  1,
+               generic: true,
+       },
+       {
+               name:    "RotateLeftUint64x2",
                argLen:  2,
                generic: true,
        },
        {
-               name:    "PairwiseSubUint16x8",
+               name:    "RotateRightUint64x2",
                argLen:  2,
                generic: true,
        },
        {
-               name:    "PopCountUint16x8",
-               argLen:  1,
+               name:    "ShiftAllLeftUint64x2",
+               argLen:  2,
                generic: true,
        },
        {
-               name:        "SaturatedAddUint16x8",
-               argLen:      2,
-               commutative: true,
-               generic:     true,
+               name:    "ShiftAllRightUint64x2",
+               argLen:  2,
+               generic: true,
        },
        {
-               name:    "SaturatedSubUint16x8",
+               name:    "ShiftLeftUint64x2",
                argLen:  2,
                generic: true,
        },
        {
-               name:    "SubUint16x8",
+               name:    "ShiftLeftAndFillUpperFromUint64x2",
+               argLen:  3,
+               generic: true,
+       },
+       {
+               name:    "ShiftRightUint64x2",
                argLen:  2,
                generic: true,
        },
        {
-               name:        "XorUint16x8",
+               name:    "ShiftRightAndFillUpperFromUint64x2",
+               argLen:  3,
+               generic: true,
+       },
+       {
+               name:    "ShiftRightSignExtendedUint64x2",
+               argLen:  2,
+               generic: true,
+       },
+       {
+               name:    "SubUint64x2",
+               argLen:  2,
+               generic: true,
+       },
+       {
+               name:        "XorUint64x2",
                argLen:      2,
                commutative: true,
                generic:     true,
        },
        {
-               name:        "AddUint32x16",
+               name:        "AddUint64x4",
                argLen:      2,
                commutative: true,
                generic:     true,
        },
        {
-               name:        "AndUint32x16",
+               name:        "AndUint64x4",
                argLen:      2,
                commutative: true,
                generic:     true,
        },
        {
-               name:    "AndNotUint32x16",
+               name:    "AndNotUint64x4",
                argLen:  2,
                generic: true,
        },
        {
-               name:        "EqualUint32x16",
+               name:        "EqualUint64x4",
                argLen:      2,
                commutative: true,
                generic:     true,
        },
        {
-               name:    "GreaterUint32x16",
+               name:    "GreaterUint64x4",
                argLen:  2,
                generic: true,
        },
        {
-               name:    "GreaterEqualUint32x16",
+               name:    "GreaterEqualUint64x4",
                argLen:  2,
                generic: true,
        },
        {
-               name:    "LessUint32x16",
+               name:    "LessUint64x4",
                argLen:  2,
                generic: true,
        },
        {
-               name:    "LessEqualUint32x16",
+               name:    "LessEqualUint64x4",
                argLen:  2,
                generic: true,
        },
        {
-               name:        "MaskedAddUint32x16",
+               name:        "MaskedAddUint64x4",
                argLen:      3,
                commutative: true,
                generic:     true,
        },
        {
-               name:        "MaskedAndUint32x16",
+               name:        "MaskedAndUint64x4",
                argLen:      3,
                commutative: true,
                generic:     true,
        },
        {
-               name:    "MaskedAndNotUint32x16",
+               name:    "MaskedAndNotUint64x4",
                argLen:  3,
                generic: true,
        },
        {
-               name:        "MaskedEqualUint32x16",
+               name:        "MaskedEqualUint64x4",
                argLen:      3,
                commutative: true,
                generic:     true,
        },
        {
-               name:    "MaskedGreaterUint32x16",
+               name:    "MaskedGreaterUint64x4",
                argLen:  3,
                generic: true,
        },
        {
-               name:    "MaskedGreaterEqualUint32x16",
+               name:    "MaskedGreaterEqualUint64x4",
                argLen:  3,
                generic: true,
        },
        {
-               name:    "MaskedLessUint32x16",
+               name:    "MaskedLessUint64x4",
                argLen:  3,
                generic: true,
        },
        {
-               name:    "MaskedLessEqualUint32x16",
+               name:    "MaskedLessEqualUint64x4",
                argLen:  3,
                generic: true,
        },
        {
-               name:        "MaskedMaxUint32x16",
+               name:        "MaskedMaxUint64x4",
                argLen:      3,
                commutative: true,
                generic:     true,
        },
        {
-               name:        "MaskedMinUint32x16",
+               name:        "MaskedMinUint64x4",
                argLen:      3,
                commutative: true,
                generic:     true,
        },
        {
-               name:        "MaskedNotEqualUint32x16",
+               name:        "MaskedMulEvenWidenUint64x4",
                argLen:      3,
                commutative: true,
                generic:     true,
        },
        {
-               name:        "MaskedOrUint32x16",
+               name:        "MaskedNotEqualUint64x4",
                argLen:      3,
                commutative: true,
                generic:     true,
        },
        {
-               name:    "MaskedPopCountUint32x16",
+               name:        "MaskedOrUint64x4",
+               argLen:      3,
+               commutative: true,
+               generic:     true,
+       },
+       {
+               name:    "MaskedPopCountUint64x4",
                argLen:  2,
                generic: true,
        },
        {
-               name:    "MaskedSaturatedUnsignedSignedQuadDotProdAccumulateUint32x16",
+               name:    "MaskedRotateLeftUint64x4",
+               argLen:  3,
+               generic: true,
+       },
+       {
+               name:    "MaskedRotateRightUint64x4",
+               argLen:  3,
+               generic: true,
+       },
+       {
+               name:    "MaskedShiftAllLeftUint64x4",
+               argLen:  3,
+               generic: true,
+       },
+       {
+               name:    "MaskedShiftAllRightUint64x4",
+               argLen:  3,
+               generic: true,
+       },
+       {
+               name:    "MaskedShiftLeftUint64x4",
+               argLen:  3,
+               generic: true,
+       },
+       {
+               name:    "MaskedShiftLeftAndFillUpperFromUint64x4",
                argLen:  4,
                generic: true,
        },
        {
-               name:    "MaskedSubUint32x16",
+               name:    "MaskedShiftRightUint64x4",
                argLen:  3,
                generic: true,
        },
        {
-               name:    "MaskedUnsignedSignedQuadDotProdAccumulateUint32x16",
+               name:    "MaskedShiftRightAndFillUpperFromUint64x4",
                argLen:  4,
                generic: true,
        },
        {
-               name:        "MaskedXorUint32x16",
+               name:    "MaskedShiftRightSignExtendedUint64x4",
+               argLen:  3,
+               generic: true,
+       },
+       {
+               name:    "MaskedSubUint64x4",
+               argLen:  3,
+               generic: true,
+       },
+       {
+               name:        "MaskedXorUint64x4",
                argLen:      3,
                commutative: true,
                generic:     true,
        },
        {
-               name:        "MaxUint32x16",
+               name:        "MaxUint64x4",
                argLen:      2,
                commutative: true,
                generic:     true,
        },
        {
-               name:        "MinUint32x16",
+               name:        "MinUint64x4",
                argLen:      2,
                commutative: true,
                generic:     true,
        },
        {
-               name:        "NotEqualUint32x16",
+               name:        "MulEvenWidenUint64x4",
                argLen:      2,
                commutative: true,
                generic:     true,
        },
        {
-               name:        "OrUint32x16",
+               name:        "NotEqualUint64x4",
                argLen:      2,
                commutative: true,
                generic:     true,
        },
        {
-               name:    "PopCountUint32x16",
+               name:        "OrUint64x4",
+               argLen:      2,
+               commutative: true,
+               generic:     true,
+       },
+       {
+               name:    "PopCountUint64x4",
                argLen:  1,
                generic: true,
        },
        {
-               name:    "SaturatedUnsignedSignedQuadDotProdAccumulateUint32x16",
+               name:    "RotateLeftUint64x4",
+               argLen:  2,
+               generic: true,
+       },
+       {
+               name:    "RotateRightUint64x4",
+               argLen:  2,
+               generic: true,
+       },
+       {
+               name:    "ShiftAllLeftUint64x4",
+               argLen:  2,
+               generic: true,
+       },
+       {
+               name:    "ShiftAllRightUint64x4",
+               argLen:  2,
+               generic: true,
+       },
+       {
+               name:    "ShiftLeftUint64x4",
+               argLen:  2,
+               generic: true,
+       },
+       {
+               name:    "ShiftLeftAndFillUpperFromUint64x4",
                argLen:  3,
                generic: true,
        },
        {
-               name:    "SubUint32x16",
+               name:    "ShiftRightUint64x4",
                argLen:  2,
                generic: true,
        },
        {
-               name:    "UnsignedSignedQuadDotProdAccumulateUint32x16",
+               name:    "ShiftRightAndFillUpperFromUint64x4",
                argLen:  3,
                generic: true,
        },
        {
-               name:        "XorUint32x16",
+               name:    "ShiftRightSignExtendedUint64x4",
+               argLen:  2,
+               generic: true,
+       },
+       {
+               name:    "SubUint64x4",
+               argLen:  2,
+               generic: true,
+       },
+       {
+               name:        "XorUint64x4",
                argLen:      2,
                commutative: true,
                generic:     true,
        },
        {
-               name:        "AddUint32x4",
+               name:        "AddUint64x8",
                argLen:      2,
                commutative: true,
                generic:     true,
        },
        {
-               name:        "AndUint32x4",
+               name:        "AndUint64x8",
                argLen:      2,
                commutative: true,
                generic:     true,
        },
        {
-               name:    "AndNotUint32x4",
+               name:    "AndNotUint64x8",
                argLen:  2,
                generic: true,
        },
        {
-               name:        "EqualUint32x4",
+               name:        "EqualUint64x8",
                argLen:      2,
                commutative: true,
                generic:     true,
        },
        {
-               name:    "GreaterUint32x4",
+               name:    "GreaterUint64x8",
                argLen:  2,
                generic: true,
        },
        {
-               name:    "GreaterEqualUint32x4",
+               name:    "GreaterEqualUint64x8",
                argLen:  2,
                generic: true,
        },
        {
-               name:    "LessUint32x4",
+               name:    "LessUint64x8",
                argLen:  2,
                generic: true,
        },
        {
-               name:    "LessEqualUint32x4",
+               name:    "LessEqualUint64x8",
                argLen:  2,
                generic: true,
        },
        {
-               name:        "MaskedAddUint32x4",
+               name:        "MaskedAddUint64x8",
                argLen:      3,
                commutative: true,
                generic:     true,
        },
        {
-               name:        "MaskedAndUint32x4",
+               name:        "MaskedAndUint64x8",
                argLen:      3,
                commutative: true,
                generic:     true,
        },
        {
-               name:    "MaskedAndNotUint32x4",
+               name:    "MaskedAndNotUint64x8",
                argLen:  3,
                generic: true,
        },
        {
-               name:        "MaskedEqualUint32x4",
+               name:        "MaskedEqualUint64x8",
                argLen:      3,
                commutative: true,
                generic:     true,
        },
        {
-               name:    "MaskedGreaterUint32x4",
+               name:    "MaskedGreaterUint64x8",
                argLen:  3,
                generic: true,
        },
        {
-               name:    "MaskedGreaterEqualUint32x4",
+               name:    "MaskedGreaterEqualUint64x8",
                argLen:  3,
                generic: true,
        },
        {
-               name:    "MaskedLessUint32x4",
+               name:    "MaskedLessUint64x8",
                argLen:  3,
                generic: true,
        },
        {
-               name:    "MaskedLessEqualUint32x4",
+               name:    "MaskedLessEqualUint64x8",
                argLen:  3,
                generic: true,
        },
        {
-               name:        "MaskedMaxUint32x4",
+               name:        "MaskedMaxUint64x8",
                argLen:      3,
                commutative: true,
                generic:     true,
        },
        {
-               name:        "MaskedMinUint32x4",
+               name:        "MaskedMinUint64x8",
                argLen:      3,
                commutative: true,
                generic:     true,
        },
        {
-               name:        "MaskedNotEqualUint32x4",
+               name:        "MaskedMulEvenWidenUint64x8",
                argLen:      3,
                commutative: true,
                generic:     true,
        },
        {
-               name:        "MaskedOrUint32x4",
+               name:        "MaskedNotEqualUint64x8",
                argLen:      3,
                commutative: true,
                generic:     true,
        },
        {
-               name:    "MaskedPopCountUint32x4",
+               name:        "MaskedOrUint64x8",
+               argLen:      3,
+               commutative: true,
+               generic:     true,
+       },
+       {
+               name:    "MaskedPopCountUint64x8",
                argLen:  2,
                generic: true,
        },
        {
-               name:    "MaskedSaturatedUnsignedSignedQuadDotProdAccumulateUint32x4",
+               name:    "MaskedRotateLeftUint64x8",
+               argLen:  3,
+               generic: true,
+       },
+       {
+               name:    "MaskedRotateRightUint64x8",
+               argLen:  3,
+               generic: true,
+       },
+       {
+               name:    "MaskedShiftAllLeftUint64x8",
+               argLen:  3,
+               generic: true,
+       },
+       {
+               name:    "MaskedShiftAllRightUint64x8",
+               argLen:  3,
+               generic: true,
+       },
+       {
+               name:    "MaskedShiftLeftUint64x8",
+               argLen:  3,
+               generic: true,
+       },
+       {
+               name:    "MaskedShiftLeftAndFillUpperFromUint64x8",
                argLen:  4,
                generic: true,
        },
        {
-               name:    "MaskedSubUint32x4",
+               name:    "MaskedShiftRightUint64x8",
                argLen:  3,
                generic: true,
        },
        {
-               name:    "MaskedUnsignedSignedQuadDotProdAccumulateUint32x4",
+               name:    "MaskedShiftRightAndFillUpperFromUint64x8",
                argLen:  4,
                generic: true,
        },
        {
-               name:        "MaskedXorUint32x4",
+               name:    "MaskedShiftRightSignExtendedUint64x8",
+               argLen:  3,
+               generic: true,
+       },
+       {
+               name:    "MaskedSubUint64x8",
+               argLen:  3,
+               generic: true,
+       },
+       {
+               name:        "MaskedXorUint64x8",
                argLen:      3,
                commutative: true,
                generic:     true,
        },
        {
-               name:        "MaxUint32x4",
+               name:        "MaxUint64x8",
                argLen:      2,
                commutative: true,
                generic:     true,
        },
        {
-               name:        "MinUint32x4",
+               name:        "MinUint64x8",
                argLen:      2,
                commutative: true,
                generic:     true,
        },
        {
-               name:        "MulEvenWidenUint32x4",
+               name:        "MulEvenWidenUint64x8",
                argLen:      2,
                commutative: true,
                generic:     true,
        },
        {
-               name:        "NotEqualUint32x4",
+               name:        "NotEqualUint64x8",
                argLen:      2,
                commutative: true,
                generic:     true,
        },
        {
-               name:        "OrUint32x4",
+               name:        "OrUint64x8",
                argLen:      2,
                commutative: true,
                generic:     true,
        },
        {
-               name:    "PairwiseAddUint32x4",
+               name:    "PopCountUint64x8",
+               argLen:  1,
+               generic: true,
+       },
+       {
+               name:    "RotateLeftUint64x8",
                argLen:  2,
                generic: true,
        },
        {
-               name:    "PairwiseSubUint32x4",
+               name:    "RotateRightUint64x8",
                argLen:  2,
                generic: true,
        },
        {
-               name:    "PopCountUint32x4",
-               argLen:  1,
+               name:    "ShiftAllLeftUint64x8",
+               argLen:  2,
                generic: true,
        },
        {
-               name:    "SaturatedUnsignedSignedQuadDotProdAccumulateUint32x4",
+               name:    "ShiftAllRightUint64x8",
+               argLen:  2,
+               generic: true,
+       },
+       {
+               name:    "ShiftLeftUint64x8",
+               argLen:  2,
+               generic: true,
+       },
+       {
+               name:    "ShiftLeftAndFillUpperFromUint64x8",
                argLen:  3,
                generic: true,
        },
        {
-               name:    "SubUint32x4",
+               name:    "ShiftRightUint64x8",
                argLen:  2,
                generic: true,
        },
        {
-               name:    "UnsignedSignedQuadDotProdAccumulateUint32x4",
+               name:    "ShiftRightAndFillUpperFromUint64x8",
                argLen:  3,
                generic: true,
        },
        {
-               name:        "XorUint32x4",
+               name:    "ShiftRightSignExtendedUint64x8",
+               argLen:  2,
+               generic: true,
+       },
+       {
+               name:    "SubUint64x8",
+               argLen:  2,
+               generic: true,
+       },
+       {
+               name:        "XorUint64x8",
                argLen:      2,
                commutative: true,
                generic:     true,
        },
        {
-               name:        "AddUint32x8",
+               name:        "AddUint8x16",
                argLen:      2,
                commutative: true,
                generic:     true,
        },
        {
-               name:        "AndUint32x8",
+               name:        "AndUint8x16",
                argLen:      2,
                commutative: true,
                generic:     true,
        },
        {
-               name:    "AndNotUint32x8",
+               name:    "AndNotUint8x16",
                argLen:  2,
                generic: true,
        },
        {
-               name:        "EqualUint32x8",
+               name:        "AverageUint8x16",
                argLen:      2,
                commutative: true,
                generic:     true,
        },
        {
-               name:    "GreaterUint32x8",
+               name:        "EqualUint8x16",
+               argLen:      2,
+               commutative: true,
+               generic:     true,
+       },
+       {
+               name:    "GreaterUint8x16",
                argLen:  2,
                generic: true,
        },
        {
-               name:    "GreaterEqualUint32x8",
+               name:    "GreaterEqualUint8x16",
                argLen:  2,
                generic: true,
        },
        {
-               name:    "LessUint32x8",
+               name:    "LessUint8x16",
                argLen:  2,
                generic: true,
        },
        {
-               name:    "LessEqualUint32x8",
+               name:    "LessEqualUint8x16",
                argLen:  2,
                generic: true,
        },
        {
-               name:        "MaskedAddUint32x8",
+               name:        "MaskedAddUint8x16",
                argLen:      3,
                commutative: true,
                generic:     true,
        },
        {
-               name:        "MaskedAndUint32x8",
+               name:        "MaskedAverageUint8x16",
                argLen:      3,
                commutative: true,
                generic:     true,
        },
        {
-               name:    "MaskedAndNotUint32x8",
-               argLen:  3,
-               generic: true,
-       },
-       {
-               name:        "MaskedEqualUint32x8",
+               name:        "MaskedEqualUint8x16",
                argLen:      3,
                commutative: true,
                generic:     true,
        },
        {
-               name:    "MaskedGreaterUint32x8",
+               name:    "MaskedGreaterUint8x16",
                argLen:  3,
                generic: true,
        },
        {
-               name:    "MaskedGreaterEqualUint32x8",
+               name:    "MaskedGreaterEqualUint8x16",
                argLen:  3,
                generic: true,
        },
        {
-               name:    "MaskedLessUint32x8",
+               name:    "MaskedLessUint8x16",
                argLen:  3,
                generic: true,
        },
        {
-               name:    "MaskedLessEqualUint32x8",
+               name:    "MaskedLessEqualUint8x16",
                argLen:  3,
                generic: true,
        },
        {
-               name:        "MaskedMaxUint32x8",
-               argLen:      3,
-               commutative: true,
-               generic:     true,
-       },
-       {
-               name:        "MaskedMinUint32x8",
+               name:        "MaskedMaxUint8x16",
                argLen:      3,
                commutative: true,
                generic:     true,
        },
        {
-               name:        "MaskedNotEqualUint32x8",
+               name:        "MaskedMinUint8x16",
                argLen:      3,
                commutative: true,
                generic:     true,
        },
        {
-               name:        "MaskedOrUint32x8",
+               name:        "MaskedNotEqualUint8x16",
                argLen:      3,
                commutative: true,
                generic:     true,
        },
        {
-               name:    "MaskedPopCountUint32x8",
+               name:    "MaskedPopCountUint8x16",
                argLen:  2,
                generic: true,
        },
        {
-               name:    "MaskedSaturatedUnsignedSignedQuadDotProdAccumulateUint32x8",
-               argLen:  4,
-               generic: true,
+               name:        "MaskedSaturatedAddUint8x16",
+               argLen:      3,
+               commutative: true,
+               generic:     true,
        },
        {
-               name:    "MaskedSubUint32x8",
+               name:    "MaskedSaturatedSubUint8x16",
                argLen:  3,
                generic: true,
        },
        {
-               name:    "MaskedUnsignedSignedQuadDotProdAccumulateUint32x8",
-               argLen:  4,
+               name:    "MaskedSaturatedUnsignedSignedPairDotProdUint8x16",
+               argLen:  3,
                generic: true,
        },
        {
-               name:        "MaskedXorUint32x8",
-               argLen:      3,
-               commutative: true,
-               generic:     true,
-       },
-       {
-               name:        "MaxUint32x8",
-               argLen:      2,
-               commutative: true,
-               generic:     true,
+               name:    "MaskedSubUint8x16",
+               argLen:  3,
+               generic: true,
        },
        {
-               name:        "MinUint32x8",
+               name:        "MaxUint8x16",
                argLen:      2,
                commutative: true,
                generic:     true,
        },
        {
-               name:        "MulEvenWidenUint32x8",
+               name:        "MinUint8x16",
                argLen:      2,
                commutative: true,
                generic:     true,
        },
        {
-               name:        "NotEqualUint32x8",
+               name:        "NotEqualUint8x16",
                argLen:      2,
                commutative: true,
                generic:     true,
        },
        {
-               name:        "OrUint32x8",
+               name:        "OrUint8x16",
                argLen:      2,
                commutative: true,
                generic:     true,
        },
        {
-               name:    "PairwiseAddUint32x8",
-               argLen:  2,
-               generic: true,
-       },
-       {
-               name:    "PairwiseSubUint32x8",
-               argLen:  2,
+               name:    "PopCountUint8x16",
+               argLen:  1,
                generic: true,
        },
        {
-               name:    "PopCountUint32x8",
-               argLen:  1,
-               generic: true,
+               name:        "SaturatedAddUint8x16",
+               argLen:      2,
+               commutative: true,
+               generic:     true,
        },
        {
-               name:    "SaturatedUnsignedSignedQuadDotProdAccumulateUint32x8",
-               argLen:  3,
+               name:    "SaturatedSubUint8x16",
+               argLen:  2,
                generic: true,
        },
        {
-               name:    "SubUint32x8",
+               name:    "SaturatedUnsignedSignedPairDotProdUint8x16",
                argLen:  2,
                generic: true,
        },
        {
-               name:    "UnsignedSignedQuadDotProdAccumulateUint32x8",
-               argLen:  3,
+               name:    "SubUint8x16",
+               argLen:  2,
                generic: true,
        },
        {
-               name:        "XorUint32x8",
+               name:        "XorUint8x16",
                argLen:      2,
                commutative: true,
                generic:     true,
        },
        {
-               name:        "AddUint64x2",
+               name:        "AddUint8x32",
                argLen:      2,
                commutative: true,
                generic:     true,
        },
        {
-               name:        "AndUint64x2",
+               name:        "AndUint8x32",
                argLen:      2,
                commutative: true,
                generic:     true,
        },
        {
-               name:    "AndNotUint64x2",
+               name:    "AndNotUint8x32",
                argLen:  2,
                generic: true,
        },
        {
-               name:        "EqualUint64x2",
+               name:        "AverageUint8x32",
                argLen:      2,
                commutative: true,
                generic:     true,
        },
        {
-               name:    "GreaterUint64x2",
+               name:        "EqualUint8x32",
+               argLen:      2,
+               commutative: true,
+               generic:     true,
+       },
+       {
+               name:    "GreaterUint8x32",
                argLen:  2,
                generic: true,
        },
        {
-               name:    "GreaterEqualUint64x2",
+               name:    "GreaterEqualUint8x32",
                argLen:  2,
                generic: true,
        },
        {
-               name:    "LessUint64x2",
+               name:    "LessUint8x32",
                argLen:  2,
                generic: true,
        },
        {
-               name:    "LessEqualUint64x2",
+               name:    "LessEqualUint8x32",
                argLen:  2,
                generic: true,
        },
        {
-               name:        "MaskedAddUint64x2",
+               name:        "MaskedAddUint8x32",
                argLen:      3,
                commutative: true,
                generic:     true,
        },
        {
-               name:        "MaskedAndUint64x2",
+               name:        "MaskedAverageUint8x32",
                argLen:      3,
                commutative: true,
                generic:     true,
        },
        {
-               name:    "MaskedAndNotUint64x2",
-               argLen:  3,
-               generic: true,
-       },
-       {
-               name:        "MaskedEqualUint64x2",
+               name:        "MaskedEqualUint8x32",
                argLen:      3,
                commutative: true,
                generic:     true,
        },
        {
-               name:    "MaskedGreaterUint64x2",
+               name:    "MaskedGreaterUint8x32",
                argLen:  3,
                generic: true,
        },
        {
-               name:    "MaskedGreaterEqualUint64x2",
+               name:    "MaskedGreaterEqualUint8x32",
                argLen:  3,
                generic: true,
        },
        {
-               name:    "MaskedLessUint64x2",
+               name:    "MaskedLessUint8x32",
                argLen:  3,
                generic: true,
        },
        {
-               name:    "MaskedLessEqualUint64x2",
+               name:    "MaskedLessEqualUint8x32",
                argLen:  3,
                generic: true,
        },
        {
-               name:        "MaskedMaxUint64x2",
+               name:        "MaskedMaxUint8x32",
                argLen:      3,
                commutative: true,
                generic:     true,
        },
        {
-               name:        "MaskedMinUint64x2",
+               name:        "MaskedMinUint8x32",
                argLen:      3,
                commutative: true,
                generic:     true,
        },
        {
-               name:        "MaskedMulEvenWidenUint64x2",
+               name:        "MaskedNotEqualUint8x32",
                argLen:      3,
                commutative: true,
                generic:     true,
        },
        {
-               name:        "MaskedNotEqualUint64x2",
-               argLen:      3,
-               commutative: true,
-               generic:     true,
+               name:    "MaskedPopCountUint8x32",
+               argLen:  2,
+               generic: true,
        },
        {
-               name:        "MaskedOrUint64x2",
+               name:        "MaskedSaturatedAddUint8x32",
                argLen:      3,
                commutative: true,
                generic:     true,
        },
        {
-               name:    "MaskedPopCountUint64x2",
-               argLen:  2,
+               name:    "MaskedSaturatedSubUint8x32",
+               argLen:  3,
                generic: true,
        },
        {
-               name:    "MaskedSubUint64x2",
+               name:    "MaskedSaturatedUnsignedSignedPairDotProdUint8x32",
                argLen:  3,
                generic: true,
        },
        {
-               name:        "MaskedXorUint64x2",
-               argLen:      3,
-               commutative: true,
-               generic:     true,
+               name:    "MaskedSubUint8x32",
+               argLen:  3,
+               generic: true,
        },
        {
-               name:        "MaxUint64x2",
+               name:        "MaxUint8x32",
                argLen:      2,
                commutative: true,
                generic:     true,
        },
        {
-               name:        "MinUint64x2",
+               name:        "MinUint8x32",
                argLen:      2,
                commutative: true,
                generic:     true,
        },
        {
-               name:        "MulEvenWidenUint64x2",
+               name:        "NotEqualUint8x32",
                argLen:      2,
                commutative: true,
                generic:     true,
        },
        {
-               name:        "NotEqualUint64x2",
+               name:        "OrUint8x32",
                argLen:      2,
                commutative: true,
                generic:     true,
        },
        {
-               name:        "OrUint64x2",
+               name:    "PopCountUint8x32",
+               argLen:  1,
+               generic: true,
+       },
+       {
+               name:        "SaturatedAddUint8x32",
                argLen:      2,
                commutative: true,
                generic:     true,
        },
        {
-               name:    "PopCountUint64x2",
-               argLen:  1,
+               name:    "SaturatedSubUint8x32",
+               argLen:  2,
                generic: true,
        },
        {
-               name:    "SubUint64x2",
+               name:    "SaturatedUnsignedSignedPairDotProdUint8x32",
                argLen:  2,
                generic: true,
        },
        {
-               name:        "XorUint64x2",
+               name:    "SubUint8x32",
+               argLen:  2,
+               generic: true,
+       },
+       {
+               name:        "XorUint8x32",
                argLen:      2,
                commutative: true,
                generic:     true,
        },
        {
-               name:        "AddUint64x4",
+               name:        "AddUint8x64",
                argLen:      2,
                commutative: true,
                generic:     true,
        },
        {
-               name:        "AndUint64x4",
+               name:        "AverageUint8x64",
                argLen:      2,
                commutative: true,
                generic:     true,
        },
        {
-               name:    "AndNotUint64x4",
-               argLen:  2,
-               generic: true,
-       },
-       {
-               name:        "EqualUint64x4",
+               name:        "EqualUint8x64",
                argLen:      2,
                commutative: true,
                generic:     true,
        },
        {
-               name:    "GreaterUint64x4",
+               name:    "GreaterUint8x64",
                argLen:  2,
                generic: true,
        },
        {
-               name:    "GreaterEqualUint64x4",
+               name:    "GreaterEqualUint8x64",
                argLen:  2,
                generic: true,
        },
        {
-               name:    "LessUint64x4",
+               name:    "LessUint8x64",
                argLen:  2,
                generic: true,
        },
        {
-               name:    "LessEqualUint64x4",
+               name:    "LessEqualUint8x64",
                argLen:  2,
                generic: true,
        },
        {
-               name:        "MaskedAddUint64x4",
+               name:        "MaskedAddUint8x64",
                argLen:      3,
                commutative: true,
                generic:     true,
        },
        {
-               name:        "MaskedAndUint64x4",
+               name:        "MaskedAverageUint8x64",
                argLen:      3,
                commutative: true,
                generic:     true,
        },
        {
-               name:    "MaskedAndNotUint64x4",
-               argLen:  3,
-               generic: true,
-       },
-       {
-               name:        "MaskedEqualUint64x4",
+               name:        "MaskedEqualUint8x64",
                argLen:      3,
                commutative: true,
                generic:     true,
        },
        {
-               name:    "MaskedGreaterUint64x4",
+               name:    "MaskedGreaterUint8x64",
                argLen:  3,
                generic: true,
        },
        {
-               name:    "MaskedGreaterEqualUint64x4",
+               name:    "MaskedGreaterEqualUint8x64",
                argLen:  3,
                generic: true,
        },
        {
-               name:    "MaskedLessUint64x4",
+               name:    "MaskedLessUint8x64",
                argLen:  3,
                generic: true,
        },
        {
-               name:    "MaskedLessEqualUint64x4",
+               name:    "MaskedLessEqualUint8x64",
                argLen:  3,
                generic: true,
        },
        {
-               name:        "MaskedMaxUint64x4",
+               name:        "MaskedMaxUint8x64",
                argLen:      3,
                commutative: true,
                generic:     true,
        },
        {
-               name:        "MaskedMinUint64x4",
+               name:        "MaskedMinUint8x64",
                argLen:      3,
                commutative: true,
                generic:     true,
        },
        {
-               name:        "MaskedMulEvenWidenUint64x4",
+               name:        "MaskedNotEqualUint8x64",
                argLen:      3,
                commutative: true,
                generic:     true,
        },
        {
-               name:        "MaskedNotEqualUint64x4",
-               argLen:      3,
-               commutative: true,
-               generic:     true,
+               name:    "MaskedPopCountUint8x64",
+               argLen:  2,
+               generic: true,
        },
        {
-               name:        "MaskedOrUint64x4",
+               name:        "MaskedSaturatedAddUint8x64",
                argLen:      3,
                commutative: true,
                generic:     true,
        },
        {
-               name:    "MaskedPopCountUint64x4",
-               argLen:  2,
+               name:    "MaskedSaturatedSubUint8x64",
+               argLen:  3,
                generic: true,
        },
        {
-               name:    "MaskedSubUint64x4",
+               name:    "MaskedSaturatedUnsignedSignedPairDotProdUint8x64",
                argLen:  3,
                generic: true,
        },
        {
-               name:        "MaskedXorUint64x4",
-               argLen:      3,
-               commutative: true,
-               generic:     true,
+               name:    "MaskedSubUint8x64",
+               argLen:  3,
+               generic: true,
        },
        {
-               name:        "MaxUint64x4",
+               name:        "MaxUint8x64",
                argLen:      2,
                commutative: true,
                generic:     true,
        },
        {
-               name:        "MinUint64x4",
+               name:        "MinUint8x64",
                argLen:      2,
                commutative: true,
                generic:     true,
        },
        {
-               name:        "MulEvenWidenUint64x4",
+               name:        "NotEqualUint8x64",
                argLen:      2,
                commutative: true,
                generic:     true,
        },
        {
-               name:        "NotEqualUint64x4",
-               argLen:      2,
-               commutative: true,
-               generic:     true,
+               name:    "PopCountUint8x64",
+               argLen:  1,
+               generic: true,
        },
        {
-               name:        "OrUint64x4",
+               name:        "SaturatedAddUint8x64",
                argLen:      2,
                commutative: true,
                generic:     true,
        },
        {
-               name:    "PopCountUint64x4",
-               argLen:  1,
+               name:    "SaturatedSubUint8x64",
+               argLen:  2,
                generic: true,
        },
        {
-               name:    "SubUint64x4",
+               name:    "SaturatedUnsignedSignedPairDotProdUint8x64",
                argLen:  2,
                generic: true,
        },
        {
-               name:        "XorUint64x4",
-               argLen:      2,
-               commutative: true,
-               generic:     true,
+               name:    "SubUint8x64",
+               argLen:  2,
+               generic: true,
        },
        {
-               name:        "AddUint64x8",
-               argLen:      2,
-               commutative: true,
-               generic:     true,
+               name:    "CeilSuppressExceptionWithPrecisionFloat32x16",
+               auxType: auxInt8,
+               argLen:  1,
+               generic: true,
        },
        {
-               name:        "AndUint64x8",
-               argLen:      2,
-               commutative: true,
-               generic:     true,
+               name:    "CeilWithPrecisionFloat32x16",
+               auxType: auxInt8,
+               argLen:  1,
+               generic: true,
        },
        {
-               name:    "AndNotUint64x8",
-               argLen:  2,
+               name:    "DiffWithCeilSuppressExceptionWithPrecisionFloat32x16",
+               auxType: auxInt8,
+               argLen:  1,
                generic: true,
        },
        {
-               name:        "EqualUint64x8",
-               argLen:      2,
-               commutative: true,
-               generic:     true,
+               name:    "DiffWithCeilWithPrecisionFloat32x16",
+               auxType: auxInt8,
+               argLen:  1,
+               generic: true,
        },
        {
-               name:    "GreaterUint64x8",
-               argLen:  2,
+               name:    "DiffWithFloorSuppressExceptionWithPrecisionFloat32x16",
+               auxType: auxInt8,
+               argLen:  1,
                generic: true,
        },
        {
-               name:    "GreaterEqualUint64x8",
-               argLen:  2,
+               name:    "DiffWithFloorWithPrecisionFloat32x16",
+               auxType: auxInt8,
+               argLen:  1,
                generic: true,
        },
        {
-               name:    "LessUint64x8",
+               name:    "DiffWithRoundSuppressExceptionWithPrecisionFloat32x16",
+               auxType: auxInt8,
+               argLen:  1,
+               generic: true,
+       },
+       {
+               name:    "DiffWithRoundWithPrecisionFloat32x16",
+               auxType: auxInt8,
+               argLen:  1,
+               generic: true,
+       },
+       {
+               name:    "DiffWithTruncSuppressExceptionWithPrecisionFloat32x16",
+               auxType: auxInt8,
+               argLen:  1,
+               generic: true,
+       },
+       {
+               name:    "DiffWithTruncWithPrecisionFloat32x16",
+               auxType: auxInt8,
+               argLen:  1,
+               generic: true,
+       },
+       {
+               name:    "FloorSuppressExceptionWithPrecisionFloat32x16",
+               auxType: auxInt8,
+               argLen:  1,
+               generic: true,
+       },
+       {
+               name:    "FloorWithPrecisionFloat32x16",
+               auxType: auxInt8,
+               argLen:  1,
+               generic: true,
+       },
+       {
+               name:    "MaskedCeilSuppressExceptionWithPrecisionFloat32x16",
+               auxType: auxInt8,
                argLen:  2,
                generic: true,
        },
        {
-               name:    "LessEqualUint64x8",
+               name:    "MaskedCeilWithPrecisionFloat32x16",
+               auxType: auxInt8,
                argLen:  2,
                generic: true,
        },
        {
-               name:        "MaskedAddUint64x8",
-               argLen:      3,
-               commutative: true,
-               generic:     true,
+               name:    "MaskedDiffWithCeilSuppressExceptionWithPrecisionFloat32x16",
+               auxType: auxInt8,
+               argLen:  2,
+               generic: true,
        },
        {
-               name:        "MaskedAndUint64x8",
-               argLen:      3,
-               commutative: true,
-               generic:     true,
+               name:    "MaskedDiffWithCeilWithPrecisionFloat32x16",
+               auxType: auxInt8,
+               argLen:  2,
+               generic: true,
        },
        {
-               name:    "MaskedAndNotUint64x8",
-               argLen:  3,
+               name:    "MaskedDiffWithFloorSuppressExceptionWithPrecisionFloat32x16",
+               auxType: auxInt8,
+               argLen:  2,
                generic: true,
        },
        {
-               name:        "MaskedEqualUint64x8",
-               argLen:      3,
-               commutative: true,
-               generic:     true,
+               name:    "MaskedDiffWithFloorWithPrecisionFloat32x16",
+               auxType: auxInt8,
+               argLen:  2,
+               generic: true,
        },
        {
-               name:    "MaskedGreaterUint64x8",
-               argLen:  3,
+               name:    "MaskedDiffWithRoundSuppressExceptionWithPrecisionFloat32x16",
+               auxType: auxInt8,
+               argLen:  2,
                generic: true,
        },
        {
-               name:    "MaskedGreaterEqualUint64x8",
-               argLen:  3,
+               name:    "MaskedDiffWithRoundWithPrecisionFloat32x16",
+               auxType: auxInt8,
+               argLen:  2,
                generic: true,
        },
        {
-               name:    "MaskedLessUint64x8",
-               argLen:  3,
+               name:    "MaskedDiffWithTruncSuppressExceptionWithPrecisionFloat32x16",
+               auxType: auxInt8,
+               argLen:  2,
                generic: true,
        },
        {
-               name:    "MaskedLessEqualUint64x8",
-               argLen:  3,
+               name:    "MaskedDiffWithTruncWithPrecisionFloat32x16",
+               auxType: auxInt8,
+               argLen:  2,
                generic: true,
        },
        {
-               name:        "MaskedMaxUint64x8",
-               argLen:      3,
-               commutative: true,
-               generic:     true,
+               name:    "MaskedFloorSuppressExceptionWithPrecisionFloat32x16",
+               auxType: auxInt8,
+               argLen:  2,
+               generic: true,
        },
        {
-               name:        "MaskedMinUint64x8",
-               argLen:      3,
-               commutative: true,
-               generic:     true,
+               name:    "MaskedFloorWithPrecisionFloat32x16",
+               auxType: auxInt8,
+               argLen:  2,
+               generic: true,
        },
        {
-               name:        "MaskedMulEvenWidenUint64x8",
-               argLen:      3,
-               commutative: true,
-               generic:     true,
+               name:    "MaskedRoundSuppressExceptionWithPrecisionFloat32x16",
+               auxType: auxInt8,
+               argLen:  2,
+               generic: true,
        },
        {
-               name:        "MaskedNotEqualUint64x8",
-               argLen:      3,
-               commutative: true,
-               generic:     true,
+               name:    "MaskedRoundWithPrecisionFloat32x16",
+               auxType: auxInt8,
+               argLen:  2,
+               generic: true,
        },
        {
-               name:        "MaskedOrUint64x8",
-               argLen:      3,
-               commutative: true,
-               generic:     true,
+               name:    "MaskedTruncSuppressExceptionWithPrecisionFloat32x16",
+               auxType: auxInt8,
+               argLen:  2,
+               generic: true,
        },
        {
-               name:    "MaskedPopCountUint64x8",
+               name:    "MaskedTruncWithPrecisionFloat32x16",
+               auxType: auxInt8,
                argLen:  2,
                generic: true,
        },
        {
-               name:    "MaskedSubUint64x8",
-               argLen:  3,
+               name:    "RoundSuppressExceptionWithPrecisionFloat32x16",
+               auxType: auxInt8,
+               argLen:  1,
                generic: true,
        },
        {
-               name:        "MaskedXorUint64x8",
-               argLen:      3,
-               commutative: true,
-               generic:     true,
+               name:    "RoundWithPrecisionFloat32x16",
+               auxType: auxInt8,
+               argLen:  1,
+               generic: true,
        },
        {
-               name:        "MaxUint64x8",
-               argLen:      2,
-               commutative: true,
-               generic:     true,
+               name:    "TruncSuppressExceptionWithPrecisionFloat32x16",
+               auxType: auxInt8,
+               argLen:  1,
+               generic: true,
        },
        {
-               name:        "MinUint64x8",
-               argLen:      2,
-               commutative: true,
-               generic:     true,
+               name:    "TruncWithPrecisionFloat32x16",
+               auxType: auxInt8,
+               argLen:  1,
+               generic: true,
        },
        {
-               name:        "MulEvenWidenUint64x8",
-               argLen:      2,
-               commutative: true,
-               generic:     true,
+               name:    "CeilSuppressExceptionWithPrecisionFloat32x4",
+               auxType: auxInt8,
+               argLen:  1,
+               generic: true,
        },
        {
-               name:        "NotEqualUint64x8",
-               argLen:      2,
-               commutative: true,
-               generic:     true,
+               name:    "CeilWithPrecisionFloat32x4",
+               auxType: auxInt8,
+               argLen:  1,
+               generic: true,
        },
        {
-               name:        "OrUint64x8",
-               argLen:      2,
-               commutative: true,
-               generic:     true,
+               name:    "DiffWithCeilSuppressExceptionWithPrecisionFloat32x4",
+               auxType: auxInt8,
+               argLen:  1,
+               generic: true,
        },
        {
-               name:    "PopCountUint64x8",
+               name:    "DiffWithCeilWithPrecisionFloat32x4",
+               auxType: auxInt8,
                argLen:  1,
                generic: true,
        },
        {
-               name:    "SubUint64x8",
-               argLen:  2,
+               name:    "DiffWithFloorSuppressExceptionWithPrecisionFloat32x4",
+               auxType: auxInt8,
+               argLen:  1,
                generic: true,
        },
        {
-               name:        "XorUint64x8",
-               argLen:      2,
-               commutative: true,
-               generic:     true,
+               name:    "DiffWithFloorWithPrecisionFloat32x4",
+               auxType: auxInt8,
+               argLen:  1,
+               generic: true,
        },
        {
-               name:        "AddUint8x16",
-               argLen:      2,
-               commutative: true,
-               generic:     true,
+               name:    "DiffWithRoundSuppressExceptionWithPrecisionFloat32x4",
+               auxType: auxInt8,
+               argLen:  1,
+               generic: true,
        },
        {
-               name:        "AndUint8x16",
-               argLen:      2,
-               commutative: true,
-               generic:     true,
+               name:    "DiffWithRoundWithPrecisionFloat32x4",
+               auxType: auxInt8,
+               argLen:  1,
+               generic: true,
        },
        {
-               name:    "AndNotUint8x16",
-               argLen:  2,
+               name:    "DiffWithTruncSuppressExceptionWithPrecisionFloat32x4",
+               auxType: auxInt8,
+               argLen:  1,
                generic: true,
        },
        {
-               name:        "AverageUint8x16",
-               argLen:      2,
-               commutative: true,
-               generic:     true,
+               name:    "DiffWithTruncWithPrecisionFloat32x4",
+               auxType: auxInt8,
+               argLen:  1,
+               generic: true,
        },
        {
-               name:        "EqualUint8x16",
-               argLen:      2,
-               commutative: true,
-               generic:     true,
+               name:    "FloorSuppressExceptionWithPrecisionFloat32x4",
+               auxType: auxInt8,
+               argLen:  1,
+               generic: true,
+       },
+       {
+               name:    "FloorWithPrecisionFloat32x4",
+               auxType: auxInt8,
+               argLen:  1,
+               generic: true,
        },
        {
-               name:    "GreaterUint8x16",
+               name:    "MaskedCeilSuppressExceptionWithPrecisionFloat32x4",
+               auxType: auxInt8,
                argLen:  2,
                generic: true,
        },
        {
-               name:    "GreaterEqualUint8x16",
+               name:    "MaskedCeilWithPrecisionFloat32x4",
+               auxType: auxInt8,
                argLen:  2,
                generic: true,
        },
        {
-               name:    "LessUint8x16",
+               name:    "MaskedDiffWithCeilSuppressExceptionWithPrecisionFloat32x4",
+               auxType: auxInt8,
                argLen:  2,
                generic: true,
        },
        {
-               name:    "LessEqualUint8x16",
+               name:    "MaskedDiffWithCeilWithPrecisionFloat32x4",
+               auxType: auxInt8,
                argLen:  2,
                generic: true,
        },
        {
-               name:        "MaskedAddUint8x16",
-               argLen:      3,
-               commutative: true,
-               generic:     true,
-       },
-       {
-               name:        "MaskedAverageUint8x16",
-               argLen:      3,
-               commutative: true,
-               generic:     true,
-       },
-       {
-               name:        "MaskedEqualUint8x16",
-               argLen:      3,
-               commutative: true,
-               generic:     true,
+               name:    "MaskedDiffWithFloorSuppressExceptionWithPrecisionFloat32x4",
+               auxType: auxInt8,
+               argLen:  2,
+               generic: true,
        },
        {
-               name:    "MaskedGreaterUint8x16",
-               argLen:  3,
+               name:    "MaskedDiffWithFloorWithPrecisionFloat32x4",
+               auxType: auxInt8,
+               argLen:  2,
                generic: true,
        },
        {
-               name:    "MaskedGreaterEqualUint8x16",
-               argLen:  3,
+               name:    "MaskedDiffWithRoundSuppressExceptionWithPrecisionFloat32x4",
+               auxType: auxInt8,
+               argLen:  2,
                generic: true,
        },
        {
-               name:    "MaskedLessUint8x16",
-               argLen:  3,
+               name:    "MaskedDiffWithRoundWithPrecisionFloat32x4",
+               auxType: auxInt8,
+               argLen:  2,
                generic: true,
        },
        {
-               name:    "MaskedLessEqualUint8x16",
-               argLen:  3,
+               name:    "MaskedDiffWithTruncSuppressExceptionWithPrecisionFloat32x4",
+               auxType: auxInt8,
+               argLen:  2,
                generic: true,
        },
        {
-               name:        "MaskedMaxUint8x16",
-               argLen:      3,
-               commutative: true,
-               generic:     true,
+               name:    "MaskedDiffWithTruncWithPrecisionFloat32x4",
+               auxType: auxInt8,
+               argLen:  2,
+               generic: true,
        },
        {
-               name:        "MaskedMinUint8x16",
-               argLen:      3,
-               commutative: true,
-               generic:     true,
+               name:    "MaskedFloorSuppressExceptionWithPrecisionFloat32x4",
+               auxType: auxInt8,
+               argLen:  2,
+               generic: true,
        },
        {
-               name:        "MaskedNotEqualUint8x16",
-               argLen:      3,
-               commutative: true,
-               generic:     true,
+               name:    "MaskedFloorWithPrecisionFloat32x4",
+               auxType: auxInt8,
+               argLen:  2,
+               generic: true,
        },
        {
-               name:    "MaskedPopCountUint8x16",
+               name:    "MaskedRoundSuppressExceptionWithPrecisionFloat32x4",
+               auxType: auxInt8,
                argLen:  2,
                generic: true,
        },
        {
-               name:        "MaskedSaturatedAddUint8x16",
-               argLen:      3,
-               commutative: true,
-               generic:     true,
+               name:    "MaskedRoundWithPrecisionFloat32x4",
+               auxType: auxInt8,
+               argLen:  2,
+               generic: true,
        },
        {
-               name:    "MaskedSaturatedSubUint8x16",
-               argLen:  3,
+               name:    "MaskedTruncSuppressExceptionWithPrecisionFloat32x4",
+               auxType: auxInt8,
+               argLen:  2,
                generic: true,
        },
        {
-               name:    "MaskedSaturatedUnsignedSignedPairDotProdUint8x16",
-               argLen:  3,
+               name:    "MaskedTruncWithPrecisionFloat32x4",
+               auxType: auxInt8,
+               argLen:  2,
                generic: true,
        },
        {
-               name:    "MaskedSubUint8x16",
-               argLen:  3,
+               name:    "RoundSuppressExceptionWithPrecisionFloat32x4",
+               auxType: auxInt8,
+               argLen:  1,
                generic: true,
        },
        {
-               name:        "MaxUint8x16",
-               argLen:      2,
-               commutative: true,
-               generic:     true,
+               name:    "RoundWithPrecisionFloat32x4",
+               auxType: auxInt8,
+               argLen:  1,
+               generic: true,
        },
        {
-               name:        "MinUint8x16",
-               argLen:      2,
-               commutative: true,
-               generic:     true,
+               name:    "TruncSuppressExceptionWithPrecisionFloat32x4",
+               auxType: auxInt8,
+               argLen:  1,
+               generic: true,
        },
        {
-               name:        "NotEqualUint8x16",
-               argLen:      2,
-               commutative: true,
-               generic:     true,
+               name:    "TruncWithPrecisionFloat32x4",
+               auxType: auxInt8,
+               argLen:  1,
+               generic: true,
        },
        {
-               name:        "OrUint8x16",
-               argLen:      2,
-               commutative: true,
-               generic:     true,
+               name:    "CeilSuppressExceptionWithPrecisionFloat32x8",
+               auxType: auxInt8,
+               argLen:  1,
+               generic: true,
        },
        {
-               name:    "PopCountUint8x16",
+               name:    "CeilWithPrecisionFloat32x8",
+               auxType: auxInt8,
                argLen:  1,
                generic: true,
        },
        {
-               name:        "SaturatedAddUint8x16",
-               argLen:      2,
-               commutative: true,
-               generic:     true,
+               name:    "DiffWithCeilSuppressExceptionWithPrecisionFloat32x8",
+               auxType: auxInt8,
+               argLen:  1,
+               generic: true,
        },
        {
-               name:    "SaturatedSubUint8x16",
-               argLen:  2,
+               name:    "DiffWithCeilWithPrecisionFloat32x8",
+               auxType: auxInt8,
+               argLen:  1,
                generic: true,
        },
        {
-               name:    "SaturatedUnsignedSignedPairDotProdUint8x16",
-               argLen:  2,
+               name:    "DiffWithFloorSuppressExceptionWithPrecisionFloat32x8",
+               auxType: auxInt8,
+               argLen:  1,
                generic: true,
        },
        {
-               name:    "SubUint8x16",
-               argLen:  2,
+               name:    "DiffWithFloorWithPrecisionFloat32x8",
+               auxType: auxInt8,
+               argLen:  1,
                generic: true,
        },
        {
-               name:        "XorUint8x16",
-               argLen:      2,
-               commutative: true,
-               generic:     true,
+               name:    "DiffWithRoundSuppressExceptionWithPrecisionFloat32x8",
+               auxType: auxInt8,
+               argLen:  1,
+               generic: true,
        },
        {
-               name:        "AddUint8x32",
-               argLen:      2,
-               commutative: true,
-               generic:     true,
+               name:    "DiffWithRoundWithPrecisionFloat32x8",
+               auxType: auxInt8,
+               argLen:  1,
+               generic: true,
        },
        {
-               name:        "AndUint8x32",
-               argLen:      2,
-               commutative: true,
-               generic:     true,
+               name:    "DiffWithTruncSuppressExceptionWithPrecisionFloat32x8",
+               auxType: auxInt8,
+               argLen:  1,
+               generic: true,
        },
        {
-               name:    "AndNotUint8x32",
-               argLen:  2,
+               name:    "DiffWithTruncWithPrecisionFloat32x8",
+               auxType: auxInt8,
+               argLen:  1,
                generic: true,
        },
        {
-               name:        "AverageUint8x32",
-               argLen:      2,
-               commutative: true,
-               generic:     true,
+               name:    "FloorSuppressExceptionWithPrecisionFloat32x8",
+               auxType: auxInt8,
+               argLen:  1,
+               generic: true,
        },
        {
-               name:        "EqualUint8x32",
-               argLen:      2,
-               commutative: true,
-               generic:     true,
+               name:    "FloorWithPrecisionFloat32x8",
+               auxType: auxInt8,
+               argLen:  1,
+               generic: true,
        },
        {
-               name:    "GreaterUint8x32",
+               name:    "MaskedCeilSuppressExceptionWithPrecisionFloat32x8",
+               auxType: auxInt8,
                argLen:  2,
                generic: true,
        },
        {
-               name:    "GreaterEqualUint8x32",
+               name:    "MaskedCeilWithPrecisionFloat32x8",
+               auxType: auxInt8,
                argLen:  2,
                generic: true,
        },
        {
-               name:    "LessUint8x32",
+               name:    "MaskedDiffWithCeilSuppressExceptionWithPrecisionFloat32x8",
+               auxType: auxInt8,
                argLen:  2,
                generic: true,
        },
        {
-               name:    "LessEqualUint8x32",
+               name:    "MaskedDiffWithCeilWithPrecisionFloat32x8",
+               auxType: auxInt8,
                argLen:  2,
                generic: true,
        },
        {
-               name:        "MaskedAddUint8x32",
-               argLen:      3,
-               commutative: true,
-               generic:     true,
+               name:    "MaskedDiffWithFloorSuppressExceptionWithPrecisionFloat32x8",
+               auxType: auxInt8,
+               argLen:  2,
+               generic: true,
        },
        {
-               name:        "MaskedAverageUint8x32",
-               argLen:      3,
-               commutative: true,
-               generic:     true,
+               name:    "MaskedDiffWithFloorWithPrecisionFloat32x8",
+               auxType: auxInt8,
+               argLen:  2,
+               generic: true,
        },
        {
-               name:        "MaskedEqualUint8x32",
-               argLen:      3,
-               commutative: true,
-               generic:     true,
+               name:    "MaskedDiffWithRoundSuppressExceptionWithPrecisionFloat32x8",
+               auxType: auxInt8,
+               argLen:  2,
+               generic: true,
        },
        {
-               name:    "MaskedGreaterUint8x32",
-               argLen:  3,
+               name:    "MaskedDiffWithRoundWithPrecisionFloat32x8",
+               auxType: auxInt8,
+               argLen:  2,
                generic: true,
        },
        {
-               name:    "MaskedGreaterEqualUint8x32",
-               argLen:  3,
+               name:    "MaskedDiffWithTruncSuppressExceptionWithPrecisionFloat32x8",
+               auxType: auxInt8,
+               argLen:  2,
                generic: true,
        },
        {
-               name:    "MaskedLessUint8x32",
-               argLen:  3,
+               name:    "MaskedDiffWithTruncWithPrecisionFloat32x8",
+               auxType: auxInt8,
+               argLen:  2,
                generic: true,
        },
        {
-               name:    "MaskedLessEqualUint8x32",
-               argLen:  3,
+               name:    "MaskedFloorSuppressExceptionWithPrecisionFloat32x8",
+               auxType: auxInt8,
+               argLen:  2,
                generic: true,
        },
        {
-               name:        "MaskedMaxUint8x32",
-               argLen:      3,
-               commutative: true,
-               generic:     true,
+               name:    "MaskedFloorWithPrecisionFloat32x8",
+               auxType: auxInt8,
+               argLen:  2,
+               generic: true,
        },
        {
-               name:        "MaskedMinUint8x32",
-               argLen:      3,
-               commutative: true,
-               generic:     true,
+               name:    "MaskedRoundSuppressExceptionWithPrecisionFloat32x8",
+               auxType: auxInt8,
+               argLen:  2,
+               generic: true,
        },
        {
-               name:        "MaskedNotEqualUint8x32",
-               argLen:      3,
-               commutative: true,
-               generic:     true,
+               name:    "MaskedRoundWithPrecisionFloat32x8",
+               auxType: auxInt8,
+               argLen:  2,
+               generic: true,
        },
        {
-               name:    "MaskedPopCountUint8x32",
+               name:    "MaskedTruncSuppressExceptionWithPrecisionFloat32x8",
+               auxType: auxInt8,
                argLen:  2,
                generic: true,
        },
        {
-               name:        "MaskedSaturatedAddUint8x32",
-               argLen:      3,
-               commutative: true,
-               generic:     true,
+               name:    "MaskedTruncWithPrecisionFloat32x8",
+               auxType: auxInt8,
+               argLen:  2,
+               generic: true,
        },
        {
-               name:    "MaskedSaturatedSubUint8x32",
-               argLen:  3,
+               name:    "RoundSuppressExceptionWithPrecisionFloat32x8",
+               auxType: auxInt8,
+               argLen:  1,
                generic: true,
        },
        {
-               name:    "MaskedSaturatedUnsignedSignedPairDotProdUint8x32",
-               argLen:  3,
+               name:    "RoundWithPrecisionFloat32x8",
+               auxType: auxInt8,
+               argLen:  1,
                generic: true,
        },
        {
-               name:    "MaskedSubUint8x32",
-               argLen:  3,
+               name:    "TruncSuppressExceptionWithPrecisionFloat32x8",
+               auxType: auxInt8,
+               argLen:  1,
                generic: true,
        },
        {
-               name:        "MaxUint8x32",
-               argLen:      2,
-               commutative: true,
-               generic:     true,
+               name:    "TruncWithPrecisionFloat32x8",
+               auxType: auxInt8,
+               argLen:  1,
+               generic: true,
        },
        {
-               name:        "MinUint8x32",
-               argLen:      2,
-               commutative: true,
-               generic:     true,
+               name:    "CeilSuppressExceptionWithPrecisionFloat64x2",
+               auxType: auxInt8,
+               argLen:  1,
+               generic: true,
        },
        {
-               name:        "NotEqualUint8x32",
-               argLen:      2,
-               commutative: true,
-               generic:     true,
+               name:    "CeilWithPrecisionFloat64x2",
+               auxType: auxInt8,
+               argLen:  1,
+               generic: true,
        },
        {
-               name:        "OrUint8x32",
-               argLen:      2,
-               commutative: true,
-               generic:     true,
+               name:    "DiffWithCeilSuppressExceptionWithPrecisionFloat64x2",
+               auxType: auxInt8,
+               argLen:  1,
+               generic: true,
        },
        {
-               name:    "PopCountUint8x32",
+               name:    "DiffWithCeilWithPrecisionFloat64x2",
+               auxType: auxInt8,
                argLen:  1,
                generic: true,
        },
        {
-               name:        "SaturatedAddUint8x32",
-               argLen:      2,
-               commutative: true,
-               generic:     true,
+               name:    "DiffWithFloorSuppressExceptionWithPrecisionFloat64x2",
+               auxType: auxInt8,
+               argLen:  1,
+               generic: true,
        },
        {
-               name:    "SaturatedSubUint8x32",
-               argLen:  2,
+               name:    "DiffWithFloorWithPrecisionFloat64x2",
+               auxType: auxInt8,
+               argLen:  1,
                generic: true,
        },
        {
-               name:    "SaturatedUnsignedSignedPairDotProdUint8x32",
-               argLen:  2,
+               name:    "DiffWithRoundSuppressExceptionWithPrecisionFloat64x2",
+               auxType: auxInt8,
+               argLen:  1,
                generic: true,
        },
        {
-               name:    "SubUint8x32",
-               argLen:  2,
+               name:    "DiffWithRoundWithPrecisionFloat64x2",
+               auxType: auxInt8,
+               argLen:  1,
                generic: true,
        },
        {
-               name:        "XorUint8x32",
-               argLen:      2,
-               commutative: true,
-               generic:     true,
+               name:    "DiffWithTruncSuppressExceptionWithPrecisionFloat64x2",
+               auxType: auxInt8,
+               argLen:  1,
+               generic: true,
        },
        {
-               name:        "AddUint8x64",
-               argLen:      2,
-               commutative: true,
-               generic:     true,
+               name:    "DiffWithTruncWithPrecisionFloat64x2",
+               auxType: auxInt8,
+               argLen:  1,
+               generic: true,
        },
        {
-               name:        "AverageUint8x64",
-               argLen:      2,
-               commutative: true,
-               generic:     true,
+               name:    "FloorSuppressExceptionWithPrecisionFloat64x2",
+               auxType: auxInt8,
+               argLen:  1,
+               generic: true,
        },
        {
-               name:        "EqualUint8x64",
-               argLen:      2,
-               commutative: true,
-               generic:     true,
+               name:    "FloorWithPrecisionFloat64x2",
+               auxType: auxInt8,
+               argLen:  1,
+               generic: true,
        },
        {
-               name:    "GreaterUint8x64",
+               name:    "MaskedCeilSuppressExceptionWithPrecisionFloat64x2",
+               auxType: auxInt8,
                argLen:  2,
                generic: true,
        },
        {
-               name:    "GreaterEqualUint8x64",
+               name:    "MaskedCeilWithPrecisionFloat64x2",
+               auxType: auxInt8,
                argLen:  2,
                generic: true,
        },
        {
-               name:    "LessUint8x64",
+               name:    "MaskedDiffWithCeilSuppressExceptionWithPrecisionFloat64x2",
+               auxType: auxInt8,
                argLen:  2,
                generic: true,
        },
        {
-               name:    "LessEqualUint8x64",
+               name:    "MaskedDiffWithCeilWithPrecisionFloat64x2",
+               auxType: auxInt8,
                argLen:  2,
                generic: true,
        },
        {
-               name:        "MaskedAddUint8x64",
-               argLen:      3,
-               commutative: true,
-               generic:     true,
-       },
-       {
-               name:        "MaskedAverageUint8x64",
-               argLen:      3,
-               commutative: true,
-               generic:     true,
-       },
-       {
-               name:        "MaskedEqualUint8x64",
-               argLen:      3,
-               commutative: true,
-               generic:     true,
-       },
-       {
-               name:    "MaskedGreaterUint8x64",
-               argLen:  3,
+               name:    "MaskedDiffWithFloorSuppressExceptionWithPrecisionFloat64x2",
+               auxType: auxInt8,
+               argLen:  2,
                generic: true,
        },
        {
-               name:    "MaskedGreaterEqualUint8x64",
-               argLen:  3,
+               name:    "MaskedDiffWithFloorWithPrecisionFloat64x2",
+               auxType: auxInt8,
+               argLen:  2,
                generic: true,
        },
        {
-               name:    "MaskedLessUint8x64",
-               argLen:  3,
+               name:    "MaskedDiffWithRoundSuppressExceptionWithPrecisionFloat64x2",
+               auxType: auxInt8,
+               argLen:  2,
                generic: true,
        },
        {
-               name:    "MaskedLessEqualUint8x64",
-               argLen:  3,
+               name:    "MaskedDiffWithRoundWithPrecisionFloat64x2",
+               auxType: auxInt8,
+               argLen:  2,
                generic: true,
        },
        {
-               name:        "MaskedMaxUint8x64",
-               argLen:      3,
-               commutative: true,
-               generic:     true,
-       },
-       {
-               name:        "MaskedMinUint8x64",
-               argLen:      3,
-               commutative: true,
-               generic:     true,
-       },
-       {
-               name:        "MaskedNotEqualUint8x64",
-               argLen:      3,
-               commutative: true,
-               generic:     true,
-       },
-       {
-               name:    "MaskedPopCountUint8x64",
+               name:    "MaskedDiffWithTruncSuppressExceptionWithPrecisionFloat64x2",
+               auxType: auxInt8,
                argLen:  2,
                generic: true,
        },
        {
-               name:        "MaskedSaturatedAddUint8x64",
-               argLen:      3,
-               commutative: true,
-               generic:     true,
-       },
-       {
-               name:    "MaskedSaturatedSubUint8x64",
-               argLen:  3,
+               name:    "MaskedDiffWithTruncWithPrecisionFloat64x2",
+               auxType: auxInt8,
+               argLen:  2,
                generic: true,
        },
        {
-               name:    "MaskedSaturatedUnsignedSignedPairDotProdUint8x64",
-               argLen:  3,
+               name:    "MaskedFloorSuppressExceptionWithPrecisionFloat64x2",
+               auxType: auxInt8,
+               argLen:  2,
                generic: true,
        },
        {
-               name:    "MaskedSubUint8x64",
-               argLen:  3,
+               name:    "MaskedFloorWithPrecisionFloat64x2",
+               auxType: auxInt8,
+               argLen:  2,
                generic: true,
        },
        {
-               name:        "MaxUint8x64",
-               argLen:      2,
-               commutative: true,
-               generic:     true,
-       },
-       {
-               name:        "MinUint8x64",
-               argLen:      2,
-               commutative: true,
-               generic:     true,
-       },
-       {
-               name:        "NotEqualUint8x64",
-               argLen:      2,
-               commutative: true,
-               generic:     true,
+               name:    "MaskedRoundSuppressExceptionWithPrecisionFloat64x2",
+               auxType: auxInt8,
+               argLen:  2,
+               generic: true,
        },
        {
-               name:    "PopCountUint8x64",
-               argLen:  1,
+               name:    "MaskedRoundWithPrecisionFloat64x2",
+               auxType: auxInt8,
+               argLen:  2,
                generic: true,
        },
        {
-               name:        "SaturatedAddUint8x64",
-               argLen:      2,
-               commutative: true,
-               generic:     true,
+               name:    "MaskedTruncSuppressExceptionWithPrecisionFloat64x2",
+               auxType: auxInt8,
+               argLen:  2,
+               generic: true,
        },
        {
-               name:    "SaturatedSubUint8x64",
+               name:    "MaskedTruncWithPrecisionFloat64x2",
+               auxType: auxInt8,
                argLen:  2,
                generic: true,
        },
        {
-               name:    "SaturatedUnsignedSignedPairDotProdUint8x64",
-               argLen:  2,
+               name:    "RoundSuppressExceptionWithPrecisionFloat64x2",
+               auxType: auxInt8,
+               argLen:  1,
                generic: true,
        },
        {
-               name:    "SubUint8x64",
-               argLen:  2,
+               name:    "RoundWithPrecisionFloat64x2",
+               auxType: auxInt8,
+               argLen:  1,
                generic: true,
        },
        {
-               name:    "CeilSuppressExceptionWithPrecisionFloat32x16",
+               name:    "TruncSuppressExceptionWithPrecisionFloat64x2",
                auxType: auxInt8,
                argLen:  1,
                generic: true,
        },
        {
-               name:    "CeilWithPrecisionFloat32x16",
+               name:    "TruncWithPrecisionFloat64x2",
                auxType: auxInt8,
                argLen:  1,
                generic: true,
        },
        {
-               name:    "DiffWithCeilSuppressExceptionWithPrecisionFloat32x16",
+               name:    "CeilSuppressExceptionWithPrecisionFloat64x4",
                auxType: auxInt8,
                argLen:  1,
                generic: true,
        },
        {
-               name:    "DiffWithCeilWithPrecisionFloat32x16",
+               name:    "CeilWithPrecisionFloat64x4",
                auxType: auxInt8,
                argLen:  1,
                generic: true,
        },
        {
-               name:    "DiffWithFloorSuppressExceptionWithPrecisionFloat32x16",
+               name:    "DiffWithCeilSuppressExceptionWithPrecisionFloat64x4",
                auxType: auxInt8,
                argLen:  1,
                generic: true,
        },
        {
-               name:    "DiffWithFloorWithPrecisionFloat32x16",
+               name:    "DiffWithCeilWithPrecisionFloat64x4",
                auxType: auxInt8,
                argLen:  1,
                generic: true,
        },
        {
-               name:    "DiffWithRoundSuppressExceptionWithPrecisionFloat32x16",
+               name:    "DiffWithFloorSuppressExceptionWithPrecisionFloat64x4",
                auxType: auxInt8,
                argLen:  1,
                generic: true,
        },
        {
-               name:    "DiffWithRoundWithPrecisionFloat32x16",
+               name:    "DiffWithFloorWithPrecisionFloat64x4",
                auxType: auxInt8,
                argLen:  1,
                generic: true,
        },
        {
-               name:    "DiffWithTruncSuppressExceptionWithPrecisionFloat32x16",
+               name:    "DiffWithRoundSuppressExceptionWithPrecisionFloat64x4",
                auxType: auxInt8,
                argLen:  1,
                generic: true,
        },
        {
-               name:    "DiffWithTruncWithPrecisionFloat32x16",
+               name:    "DiffWithRoundWithPrecisionFloat64x4",
                auxType: auxInt8,
                argLen:  1,
                generic: true,
        },
        {
-               name:    "FloorSuppressExceptionWithPrecisionFloat32x16",
+               name:    "DiffWithTruncSuppressExceptionWithPrecisionFloat64x4",
                auxType: auxInt8,
                argLen:  1,
                generic: true,
        },
        {
-               name:    "FloorWithPrecisionFloat32x16",
+               name:    "DiffWithTruncWithPrecisionFloat64x4",
                auxType: auxInt8,
                argLen:  1,
                generic: true,
        },
        {
-               name:    "MaskedCeilSuppressExceptionWithPrecisionFloat32x16",
+               name:    "FloorSuppressExceptionWithPrecisionFloat64x4",
                auxType: auxInt8,
-               argLen:  2,
+               argLen:  1,
                generic: true,
        },
        {
-               name:    "MaskedCeilWithPrecisionFloat32x16",
+               name:    "FloorWithPrecisionFloat64x4",
                auxType: auxInt8,
-               argLen:  2,
+               argLen:  1,
                generic: true,
        },
        {
-               name:    "MaskedDiffWithCeilSuppressExceptionWithPrecisionFloat32x16",
+               name:    "MaskedCeilSuppressExceptionWithPrecisionFloat64x4",
                auxType: auxInt8,
                argLen:  2,
                generic: true,
        },
        {
-               name:    "MaskedDiffWithCeilWithPrecisionFloat32x16",
+               name:    "MaskedCeilWithPrecisionFloat64x4",
                auxType: auxInt8,
                argLen:  2,
                generic: true,
        },
        {
-               name:    "MaskedDiffWithFloorSuppressExceptionWithPrecisionFloat32x16",
+               name:    "MaskedDiffWithCeilSuppressExceptionWithPrecisionFloat64x4",
                auxType: auxInt8,
                argLen:  2,
                generic: true,
        },
        {
-               name:    "MaskedDiffWithFloorWithPrecisionFloat32x16",
+               name:    "MaskedDiffWithCeilWithPrecisionFloat64x4",
                auxType: auxInt8,
                argLen:  2,
                generic: true,
        },
        {
-               name:    "MaskedDiffWithRoundSuppressExceptionWithPrecisionFloat32x16",
+               name:    "MaskedDiffWithFloorSuppressExceptionWithPrecisionFloat64x4",
                auxType: auxInt8,
                argLen:  2,
                generic: true,
        },
        {
-               name:    "MaskedDiffWithRoundWithPrecisionFloat32x16",
+               name:    "MaskedDiffWithFloorWithPrecisionFloat64x4",
                auxType: auxInt8,
                argLen:  2,
                generic: true,
        },
        {
-               name:    "MaskedDiffWithTruncSuppressExceptionWithPrecisionFloat32x16",
+               name:    "MaskedDiffWithRoundSuppressExceptionWithPrecisionFloat64x4",
                auxType: auxInt8,
                argLen:  2,
                generic: true,
        },
        {
-               name:    "MaskedDiffWithTruncWithPrecisionFloat32x16",
+               name:    "MaskedDiffWithRoundWithPrecisionFloat64x4",
                auxType: auxInt8,
                argLen:  2,
                generic: true,
        },
        {
-               name:    "MaskedFloorSuppressExceptionWithPrecisionFloat32x16",
+               name:    "MaskedDiffWithTruncSuppressExceptionWithPrecisionFloat64x4",
                auxType: auxInt8,
                argLen:  2,
                generic: true,
        },
        {
-               name:    "MaskedFloorWithPrecisionFloat32x16",
+               name:    "MaskedDiffWithTruncWithPrecisionFloat64x4",
                auxType: auxInt8,
                argLen:  2,
                generic: true,
        },
        {
-               name:    "MaskedRoundSuppressExceptionWithPrecisionFloat32x16",
+               name:    "MaskedFloorSuppressExceptionWithPrecisionFloat64x4",
                auxType: auxInt8,
                argLen:  2,
                generic: true,
        },
        {
-               name:    "MaskedRoundWithPrecisionFloat32x16",
+               name:    "MaskedFloorWithPrecisionFloat64x4",
                auxType: auxInt8,
                argLen:  2,
                generic: true,
        },
        {
-               name:    "MaskedTruncSuppressExceptionWithPrecisionFloat32x16",
+               name:    "MaskedRoundSuppressExceptionWithPrecisionFloat64x4",
                auxType: auxInt8,
                argLen:  2,
                generic: true,
        },
        {
-               name:    "MaskedTruncWithPrecisionFloat32x16",
+               name:    "MaskedRoundWithPrecisionFloat64x4",
                auxType: auxInt8,
                argLen:  2,
                generic: true,
        },
        {
-               name:    "RoundSuppressExceptionWithPrecisionFloat32x16",
+               name:    "MaskedTruncSuppressExceptionWithPrecisionFloat64x4",
                auxType: auxInt8,
-               argLen:  1,
+               argLen:  2,
                generic: true,
        },
        {
-               name:    "RoundWithPrecisionFloat32x16",
+               name:    "MaskedTruncWithPrecisionFloat64x4",
                auxType: auxInt8,
-               argLen:  1,
+               argLen:  2,
                generic: true,
        },
        {
-               name:    "TruncSuppressExceptionWithPrecisionFloat32x16",
+               name:    "RoundSuppressExceptionWithPrecisionFloat64x4",
                auxType: auxInt8,
                argLen:  1,
                generic: true,
        },
        {
-               name:    "TruncWithPrecisionFloat32x16",
+               name:    "RoundWithPrecisionFloat64x4",
                auxType: auxInt8,
                argLen:  1,
                generic: true,
        },
        {
-               name:    "CeilSuppressExceptionWithPrecisionFloat32x4",
+               name:    "TruncSuppressExceptionWithPrecisionFloat64x4",
                auxType: auxInt8,
                argLen:  1,
                generic: true,
        },
        {
-               name:    "CeilWithPrecisionFloat32x4",
+               name:    "TruncWithPrecisionFloat64x4",
                auxType: auxInt8,
                argLen:  1,
                generic: true,
        },
        {
-               name:    "DiffWithCeilSuppressExceptionWithPrecisionFloat32x4",
+               name:    "CeilSuppressExceptionWithPrecisionFloat64x8",
                auxType: auxInt8,
                argLen:  1,
                generic: true,
        },
        {
-               name:    "DiffWithCeilWithPrecisionFloat32x4",
+               name:    "CeilWithPrecisionFloat64x8",
                auxType: auxInt8,
                argLen:  1,
                generic: true,
        },
        {
-               name:    "DiffWithFloorSuppressExceptionWithPrecisionFloat32x4",
+               name:    "DiffWithCeilSuppressExceptionWithPrecisionFloat64x8",
                auxType: auxInt8,
                argLen:  1,
                generic: true,
        },
        {
-               name:    "DiffWithFloorWithPrecisionFloat32x4",
+               name:    "DiffWithCeilWithPrecisionFloat64x8",
                auxType: auxInt8,
                argLen:  1,
                generic: true,
        },
        {
-               name:    "DiffWithRoundSuppressExceptionWithPrecisionFloat32x4",
+               name:    "DiffWithFloorSuppressExceptionWithPrecisionFloat64x8",
                auxType: auxInt8,
                argLen:  1,
                generic: true,
        },
        {
-               name:    "DiffWithRoundWithPrecisionFloat32x4",
+               name:    "DiffWithFloorWithPrecisionFloat64x8",
                auxType: auxInt8,
                argLen:  1,
                generic: true,
        },
        {
-               name:    "DiffWithTruncSuppressExceptionWithPrecisionFloat32x4",
+               name:    "DiffWithRoundSuppressExceptionWithPrecisionFloat64x8",
                auxType: auxInt8,
                argLen:  1,
                generic: true,
        },
        {
-               name:    "DiffWithTruncWithPrecisionFloat32x4",
+               name:    "DiffWithRoundWithPrecisionFloat64x8",
                auxType: auxInt8,
                argLen:  1,
                generic: true,
        },
        {
-               name:    "FloorSuppressExceptionWithPrecisionFloat32x4",
+               name:    "DiffWithTruncSuppressExceptionWithPrecisionFloat64x8",
                auxType: auxInt8,
                argLen:  1,
                generic: true,
        },
        {
-               name:    "FloorWithPrecisionFloat32x4",
+               name:    "DiffWithTruncWithPrecisionFloat64x8",
                auxType: auxInt8,
                argLen:  1,
                generic: true,
        },
        {
-               name:    "MaskedCeilSuppressExceptionWithPrecisionFloat32x4",
+               name:    "FloorSuppressExceptionWithPrecisionFloat64x8",
                auxType: auxInt8,
-               argLen:  2,
+               argLen:  1,
                generic: true,
        },
        {
-               name:    "MaskedCeilWithPrecisionFloat32x4",
+               name:    "FloorWithPrecisionFloat64x8",
                auxType: auxInt8,
-               argLen:  2,
+               argLen:  1,
                generic: true,
        },
        {
-               name:    "MaskedDiffWithCeilSuppressExceptionWithPrecisionFloat32x4",
+               name:    "MaskedCeilSuppressExceptionWithPrecisionFloat64x8",
                auxType: auxInt8,
                argLen:  2,
                generic: true,
        },
        {
-               name:    "MaskedDiffWithCeilWithPrecisionFloat32x4",
+               name:    "MaskedCeilWithPrecisionFloat64x8",
                auxType: auxInt8,
                argLen:  2,
                generic: true,
        },
        {
-               name:    "MaskedDiffWithFloorSuppressExceptionWithPrecisionFloat32x4",
+               name:    "MaskedDiffWithCeilSuppressExceptionWithPrecisionFloat64x8",
                auxType: auxInt8,
                argLen:  2,
                generic: true,
        },
        {
-               name:    "MaskedDiffWithFloorWithPrecisionFloat32x4",
+               name:    "MaskedDiffWithCeilWithPrecisionFloat64x8",
                auxType: auxInt8,
                argLen:  2,
                generic: true,
        },
        {
-               name:    "MaskedDiffWithRoundSuppressExceptionWithPrecisionFloat32x4",
+               name:    "MaskedDiffWithFloorSuppressExceptionWithPrecisionFloat64x8",
                auxType: auxInt8,
                argLen:  2,
                generic: true,
        },
        {
-               name:    "MaskedDiffWithRoundWithPrecisionFloat32x4",
+               name:    "MaskedDiffWithFloorWithPrecisionFloat64x8",
                auxType: auxInt8,
                argLen:  2,
                generic: true,
        },
        {
-               name:    "MaskedDiffWithTruncSuppressExceptionWithPrecisionFloat32x4",
+               name:    "MaskedDiffWithRoundSuppressExceptionWithPrecisionFloat64x8",
                auxType: auxInt8,
                argLen:  2,
                generic: true,
        },
        {
-               name:    "MaskedDiffWithTruncWithPrecisionFloat32x4",
+               name:    "MaskedDiffWithRoundWithPrecisionFloat64x8",
                auxType: auxInt8,
                argLen:  2,
                generic: true,
        },
        {
-               name:    "MaskedFloorSuppressExceptionWithPrecisionFloat32x4",
+               name:    "MaskedDiffWithTruncSuppressExceptionWithPrecisionFloat64x8",
                auxType: auxInt8,
                argLen:  2,
                generic: true,
        },
        {
-               name:    "MaskedFloorWithPrecisionFloat32x4",
+               name:    "MaskedDiffWithTruncWithPrecisionFloat64x8",
                auxType: auxInt8,
                argLen:  2,
                generic: true,
        },
        {
-               name:    "MaskedRoundSuppressExceptionWithPrecisionFloat32x4",
+               name:    "MaskedFloorSuppressExceptionWithPrecisionFloat64x8",
                auxType: auxInt8,
                argLen:  2,
                generic: true,
        },
        {
-               name:    "MaskedRoundWithPrecisionFloat32x4",
+               name:    "MaskedFloorWithPrecisionFloat64x8",
                auxType: auxInt8,
                argLen:  2,
                generic: true,
        },
        {
-               name:    "MaskedTruncSuppressExceptionWithPrecisionFloat32x4",
+               name:    "MaskedRoundSuppressExceptionWithPrecisionFloat64x8",
                auxType: auxInt8,
                argLen:  2,
                generic: true,
        },
        {
-               name:    "MaskedTruncWithPrecisionFloat32x4",
+               name:    "MaskedRoundWithPrecisionFloat64x8",
                auxType: auxInt8,
                argLen:  2,
                generic: true,
        },
        {
-               name:    "RoundSuppressExceptionWithPrecisionFloat32x4",
+               name:    "MaskedTruncSuppressExceptionWithPrecisionFloat64x8",
                auxType: auxInt8,
-               argLen:  1,
+               argLen:  2,
                generic: true,
        },
        {
-               name:    "RoundWithPrecisionFloat32x4",
+               name:    "MaskedTruncWithPrecisionFloat64x8",
                auxType: auxInt8,
-               argLen:  1,
+               argLen:  2,
                generic: true,
        },
        {
-               name:    "TruncSuppressExceptionWithPrecisionFloat32x4",
+               name:    "RoundSuppressExceptionWithPrecisionFloat64x8",
                auxType: auxInt8,
                argLen:  1,
                generic: true,
        },
        {
-               name:    "TruncWithPrecisionFloat32x4",
+               name:    "RoundWithPrecisionFloat64x8",
                auxType: auxInt8,
                argLen:  1,
                generic: true,
        },
        {
-               name:    "CeilSuppressExceptionWithPrecisionFloat32x8",
+               name:    "TruncSuppressExceptionWithPrecisionFloat64x8",
                auxType: auxInt8,
                argLen:  1,
                generic: true,
        },
        {
-               name:    "CeilWithPrecisionFloat32x8",
+               name:    "TruncWithPrecisionFloat64x8",
                auxType: auxInt8,
                argLen:  1,
                generic: true,
        },
        {
-               name:    "DiffWithCeilSuppressExceptionWithPrecisionFloat32x8",
+               name:    "MaskedShiftAllLeftAndFillUpperFromInt16x16",
                auxType: auxInt8,
-               argLen:  1,
+               argLen:  3,
                generic: true,
        },
        {
-               name:    "DiffWithCeilWithPrecisionFloat32x8",
+               name:    "MaskedShiftAllRightAndFillUpperFromInt16x16",
                auxType: auxInt8,
-               argLen:  1,
+               argLen:  3,
                generic: true,
        },
        {
-               name:    "DiffWithFloorSuppressExceptionWithPrecisionFloat32x8",
+               name:    "ShiftAllLeftAndFillUpperFromInt16x16",
                auxType: auxInt8,
-               argLen:  1,
+               argLen:  2,
                generic: true,
        },
        {
-               name:    "DiffWithFloorWithPrecisionFloat32x8",
+               name:    "ShiftAllRightAndFillUpperFromInt16x16",
                auxType: auxInt8,
-               argLen:  1,
+               argLen:  2,
                generic: true,
        },
        {
-               name:    "DiffWithRoundSuppressExceptionWithPrecisionFloat32x8",
+               name:    "MaskedShiftAllLeftAndFillUpperFromInt16x32",
                auxType: auxInt8,
-               argLen:  1,
+               argLen:  3,
                generic: true,
        },
        {
-               name:    "DiffWithRoundWithPrecisionFloat32x8",
+               name:    "MaskedShiftAllRightAndFillUpperFromInt16x32",
                auxType: auxInt8,
-               argLen:  1,
+               argLen:  3,
                generic: true,
        },
        {
-               name:    "DiffWithTruncSuppressExceptionWithPrecisionFloat32x8",
+               name:    "ShiftAllLeftAndFillUpperFromInt16x32",
                auxType: auxInt8,
-               argLen:  1,
+               argLen:  2,
                generic: true,
        },
        {
-               name:    "DiffWithTruncWithPrecisionFloat32x8",
+               name:    "ShiftAllRightAndFillUpperFromInt16x32",
                auxType: auxInt8,
-               argLen:  1,
+               argLen:  2,
                generic: true,
        },
        {
-               name:    "FloorSuppressExceptionWithPrecisionFloat32x8",
+               name:    "GetElemInt16x8",
                auxType: auxInt8,
                argLen:  1,
                generic: true,
        },
        {
-               name:    "FloorWithPrecisionFloat32x8",
+               name:    "MaskedShiftAllLeftAndFillUpperFromInt16x8",
                auxType: auxInt8,
-               argLen:  1,
+               argLen:  3,
                generic: true,
        },
        {
-               name:    "MaskedCeilSuppressExceptionWithPrecisionFloat32x8",
+               name:    "MaskedShiftAllRightAndFillUpperFromInt16x8",
                auxType: auxInt8,
-               argLen:  2,
+               argLen:  3,
                generic: true,
        },
        {
-               name:    "MaskedCeilWithPrecisionFloat32x8",
+               name:    "SetElemInt16x8",
                auxType: auxInt8,
                argLen:  2,
                generic: true,
        },
        {
-               name:    "MaskedDiffWithCeilSuppressExceptionWithPrecisionFloat32x8",
+               name:    "ShiftAllLeftAndFillUpperFromInt16x8",
                auxType: auxInt8,
                argLen:  2,
                generic: true,
        },
        {
-               name:    "MaskedDiffWithCeilWithPrecisionFloat32x8",
+               name:    "ShiftAllRightAndFillUpperFromInt16x8",
                auxType: auxInt8,
                argLen:  2,
                generic: true,
        },
        {
-               name:    "MaskedDiffWithFloorSuppressExceptionWithPrecisionFloat32x8",
+               name:    "MaskedRotateAllLeftInt32x16",
                auxType: auxInt8,
                argLen:  2,
                generic: true,
        },
        {
-               name:    "MaskedDiffWithFloorWithPrecisionFloat32x8",
+               name:    "MaskedRotateAllRightInt32x16",
                auxType: auxInt8,
                argLen:  2,
                generic: true,
        },
        {
-               name:    "MaskedDiffWithRoundSuppressExceptionWithPrecisionFloat32x8",
+               name:    "MaskedShiftAllLeftAndFillUpperFromInt32x16",
                auxType: auxInt8,
-               argLen:  2,
+               argLen:  3,
                generic: true,
        },
        {
-               name:    "MaskedDiffWithRoundWithPrecisionFloat32x8",
+               name:    "MaskedShiftAllRightAndFillUpperFromInt32x16",
                auxType: auxInt8,
-               argLen:  2,
+               argLen:  3,
                generic: true,
        },
        {
-               name:    "MaskedDiffWithTruncSuppressExceptionWithPrecisionFloat32x8",
+               name:    "RotateAllLeftInt32x16",
                auxType: auxInt8,
-               argLen:  2,
+               argLen:  1,
                generic: true,
        },
        {
-               name:    "MaskedDiffWithTruncWithPrecisionFloat32x8",
+               name:    "RotateAllRightInt32x16",
                auxType: auxInt8,
-               argLen:  2,
+               argLen:  1,
                generic: true,
        },
        {
-               name:    "MaskedFloorSuppressExceptionWithPrecisionFloat32x8",
+               name:    "ShiftAllLeftAndFillUpperFromInt32x16",
                auxType: auxInt8,
                argLen:  2,
                generic: true,
        },
        {
-               name:    "MaskedFloorWithPrecisionFloat32x8",
+               name:    "ShiftAllRightAndFillUpperFromInt32x16",
                auxType: auxInt8,
                argLen:  2,
                generic: true,
        },
        {
-               name:    "MaskedRoundSuppressExceptionWithPrecisionFloat32x8",
+               name:    "GetElemInt32x4",
                auxType: auxInt8,
-               argLen:  2,
+               argLen:  1,
                generic: true,
        },
        {
-               name:    "MaskedRoundWithPrecisionFloat32x8",
+               name:    "MaskedRotateAllLeftInt32x4",
                auxType: auxInt8,
                argLen:  2,
                generic: true,
        },
        {
-               name:    "MaskedTruncSuppressExceptionWithPrecisionFloat32x8",
+               name:    "MaskedRotateAllRightInt32x4",
                auxType: auxInt8,
                argLen:  2,
                generic: true,
        },
        {
-               name:    "MaskedTruncWithPrecisionFloat32x8",
+               name:    "MaskedShiftAllLeftAndFillUpperFromInt32x4",
                auxType: auxInt8,
-               argLen:  2,
+               argLen:  3,
                generic: true,
        },
        {
-               name:    "RoundSuppressExceptionWithPrecisionFloat32x8",
+               name:    "MaskedShiftAllRightAndFillUpperFromInt32x4",
                auxType: auxInt8,
-               argLen:  1,
+               argLen:  3,
                generic: true,
        },
        {
-               name:    "RoundWithPrecisionFloat32x8",
+               name:    "RotateAllLeftInt32x4",
                auxType: auxInt8,
                argLen:  1,
                generic: true,
        },
        {
-               name:    "TruncSuppressExceptionWithPrecisionFloat32x8",
+               name:    "RotateAllRightInt32x4",
                auxType: auxInt8,
                argLen:  1,
                generic: true,
        },
        {
-               name:    "TruncWithPrecisionFloat32x8",
+               name:    "SetElemInt32x4",
                auxType: auxInt8,
-               argLen:  1,
+               argLen:  2,
                generic: true,
        },
        {
-               name:    "CeilSuppressExceptionWithPrecisionFloat64x2",
+               name:    "ShiftAllLeftAndFillUpperFromInt32x4",
                auxType: auxInt8,
-               argLen:  1,
+               argLen:  2,
                generic: true,
        },
        {
-               name:    "CeilWithPrecisionFloat64x2",
+               name:    "ShiftAllRightAndFillUpperFromInt32x4",
                auxType: auxInt8,
-               argLen:  1,
+               argLen:  2,
                generic: true,
        },
        {
-               name:    "DiffWithCeilSuppressExceptionWithPrecisionFloat64x2",
+               name:    "MaskedRotateAllLeftInt32x8",
                auxType: auxInt8,
-               argLen:  1,
+               argLen:  2,
                generic: true,
        },
        {
-               name:    "DiffWithCeilWithPrecisionFloat64x2",
+               name:    "MaskedRotateAllRightInt32x8",
                auxType: auxInt8,
-               argLen:  1,
+               argLen:  2,
                generic: true,
        },
        {
-               name:    "DiffWithFloorSuppressExceptionWithPrecisionFloat64x2",
+               name:    "MaskedShiftAllLeftAndFillUpperFromInt32x8",
                auxType: auxInt8,
-               argLen:  1,
+               argLen:  3,
                generic: true,
        },
        {
-               name:    "DiffWithFloorWithPrecisionFloat64x2",
+               name:    "MaskedShiftAllRightAndFillUpperFromInt32x8",
                auxType: auxInt8,
-               argLen:  1,
+               argLen:  3,
                generic: true,
        },
        {
-               name:    "DiffWithRoundSuppressExceptionWithPrecisionFloat64x2",
+               name:    "RotateAllLeftInt32x8",
                auxType: auxInt8,
                argLen:  1,
                generic: true,
        },
        {
-               name:    "DiffWithRoundWithPrecisionFloat64x2",
+               name:    "RotateAllRightInt32x8",
                auxType: auxInt8,
                argLen:  1,
                generic: true,
        },
        {
-               name:    "DiffWithTruncSuppressExceptionWithPrecisionFloat64x2",
+               name:    "ShiftAllLeftAndFillUpperFromInt32x8",
                auxType: auxInt8,
-               argLen:  1,
+               argLen:  2,
                generic: true,
        },
        {
-               name:    "DiffWithTruncWithPrecisionFloat64x2",
+               name:    "ShiftAllRightAndFillUpperFromInt32x8",
                auxType: auxInt8,
-               argLen:  1,
+               argLen:  2,
                generic: true,
        },
        {
-               name:    "FloorSuppressExceptionWithPrecisionFloat64x2",
+               name:    "GetElemInt64x2",
                auxType: auxInt8,
                argLen:  1,
                generic: true,
        },
        {
-               name:    "FloorWithPrecisionFloat64x2",
+               name:    "MaskedRotateAllLeftInt64x2",
                auxType: auxInt8,
-               argLen:  1,
+               argLen:  2,
                generic: true,
        },
        {
-               name:    "MaskedCeilSuppressExceptionWithPrecisionFloat64x2",
+               name:    "MaskedRotateAllRightInt64x2",
                auxType: auxInt8,
                argLen:  2,
                generic: true,
        },
        {
-               name:    "MaskedCeilWithPrecisionFloat64x2",
+               name:    "MaskedShiftAllLeftAndFillUpperFromInt64x2",
                auxType: auxInt8,
-               argLen:  2,
+               argLen:  3,
                generic: true,
        },
        {
-               name:    "MaskedDiffWithCeilSuppressExceptionWithPrecisionFloat64x2",
+               name:    "MaskedShiftAllRightAndFillUpperFromInt64x2",
                auxType: auxInt8,
-               argLen:  2,
+               argLen:  3,
                generic: true,
        },
        {
-               name:    "MaskedDiffWithCeilWithPrecisionFloat64x2",
+               name:    "RotateAllLeftInt64x2",
                auxType: auxInt8,
-               argLen:  2,
+               argLen:  1,
                generic: true,
        },
        {
-               name:    "MaskedDiffWithFloorSuppressExceptionWithPrecisionFloat64x2",
+               name:    "RotateAllRightInt64x2",
                auxType: auxInt8,
-               argLen:  2,
+               argLen:  1,
                generic: true,
        },
        {
-               name:    "MaskedDiffWithFloorWithPrecisionFloat64x2",
+               name:    "SetElemInt64x2",
                auxType: auxInt8,
                argLen:  2,
                generic: true,
        },
        {
-               name:    "MaskedDiffWithRoundSuppressExceptionWithPrecisionFloat64x2",
+               name:    "ShiftAllLeftAndFillUpperFromInt64x2",
                auxType: auxInt8,
                argLen:  2,
                generic: true,
        },
        {
-               name:    "MaskedDiffWithRoundWithPrecisionFloat64x2",
+               name:    "ShiftAllRightAndFillUpperFromInt64x2",
                auxType: auxInt8,
                argLen:  2,
                generic: true,
        },
        {
-               name:    "MaskedDiffWithTruncSuppressExceptionWithPrecisionFloat64x2",
+               name:    "MaskedRotateAllLeftInt64x4",
                auxType: auxInt8,
                argLen:  2,
                generic: true,
        },
        {
-               name:    "MaskedDiffWithTruncWithPrecisionFloat64x2",
+               name:    "MaskedRotateAllRightInt64x4",
                auxType: auxInt8,
                argLen:  2,
                generic: true,
        },
        {
-               name:    "MaskedFloorSuppressExceptionWithPrecisionFloat64x2",
+               name:    "MaskedShiftAllLeftAndFillUpperFromInt64x4",
                auxType: auxInt8,
-               argLen:  2,
+               argLen:  3,
                generic: true,
        },
        {
-               name:    "MaskedFloorWithPrecisionFloat64x2",
+               name:    "MaskedShiftAllRightAndFillUpperFromInt64x4",
                auxType: auxInt8,
-               argLen:  2,
+               argLen:  3,
                generic: true,
        },
        {
-               name:    "MaskedRoundSuppressExceptionWithPrecisionFloat64x2",
+               name:    "RotateAllLeftInt64x4",
                auxType: auxInt8,
-               argLen:  2,
+               argLen:  1,
                generic: true,
        },
        {
-               name:    "MaskedRoundWithPrecisionFloat64x2",
+               name:    "RotateAllRightInt64x4",
                auxType: auxInt8,
-               argLen:  2,
+               argLen:  1,
                generic: true,
        },
        {
-               name:    "MaskedTruncSuppressExceptionWithPrecisionFloat64x2",
+               name:    "ShiftAllLeftAndFillUpperFromInt64x4",
                auxType: auxInt8,
                argLen:  2,
                generic: true,
        },
        {
-               name:    "MaskedTruncWithPrecisionFloat64x2",
+               name:    "ShiftAllRightAndFillUpperFromInt64x4",
                auxType: auxInt8,
                argLen:  2,
                generic: true,
        },
        {
-               name:    "RoundSuppressExceptionWithPrecisionFloat64x2",
+               name:    "MaskedRotateAllLeftInt64x8",
                auxType: auxInt8,
-               argLen:  1,
+               argLen:  2,
                generic: true,
        },
        {
-               name:    "RoundWithPrecisionFloat64x2",
+               name:    "MaskedRotateAllRightInt64x8",
                auxType: auxInt8,
-               argLen:  1,
+               argLen:  2,
                generic: true,
        },
        {
-               name:    "TruncSuppressExceptionWithPrecisionFloat64x2",
+               name:    "MaskedShiftAllLeftAndFillUpperFromInt64x8",
                auxType: auxInt8,
-               argLen:  1,
+               argLen:  3,
                generic: true,
        },
        {
-               name:    "TruncWithPrecisionFloat64x2",
+               name:    "MaskedShiftAllRightAndFillUpperFromInt64x8",
                auxType: auxInt8,
-               argLen:  1,
+               argLen:  3,
                generic: true,
        },
        {
-               name:    "CeilSuppressExceptionWithPrecisionFloat64x4",
+               name:    "RotateAllLeftInt64x8",
                auxType: auxInt8,
                argLen:  1,
                generic: true,
        },
        {
-               name:    "CeilWithPrecisionFloat64x4",
+               name:    "RotateAllRightInt64x8",
                auxType: auxInt8,
                argLen:  1,
                generic: true,
        },
        {
-               name:    "DiffWithCeilSuppressExceptionWithPrecisionFloat64x4",
+               name:    "ShiftAllLeftAndFillUpperFromInt64x8",
                auxType: auxInt8,
-               argLen:  1,
+               argLen:  2,
                generic: true,
        },
        {
-               name:    "DiffWithCeilWithPrecisionFloat64x4",
+               name:    "ShiftAllRightAndFillUpperFromInt64x8",
                auxType: auxInt8,
-               argLen:  1,
+               argLen:  2,
                generic: true,
        },
        {
-               name:    "DiffWithFloorSuppressExceptionWithPrecisionFloat64x4",
+               name:    "GetElemInt8x16",
                auxType: auxInt8,
                argLen:  1,
                generic: true,
        },
        {
-               name:    "DiffWithFloorWithPrecisionFloat64x4",
+               name:    "SetElemInt8x16",
                auxType: auxInt8,
-               argLen:  1,
+               argLen:  2,
                generic: true,
        },
        {
-               name:    "DiffWithRoundSuppressExceptionWithPrecisionFloat64x4",
+               name:    "MaskedShiftAllLeftAndFillUpperFromUint16x16",
                auxType: auxInt8,
-               argLen:  1,
+               argLen:  3,
                generic: true,
        },
        {
-               name:    "DiffWithRoundWithPrecisionFloat64x4",
+               name:    "MaskedShiftAllRightAndFillUpperFromUint16x16",
                auxType: auxInt8,
-               argLen:  1,
+               argLen:  3,
                generic: true,
        },
        {
-               name:    "DiffWithTruncSuppressExceptionWithPrecisionFloat64x4",
+               name:    "ShiftAllLeftAndFillUpperFromUint16x16",
                auxType: auxInt8,
-               argLen:  1,
+               argLen:  2,
                generic: true,
        },
        {
-               name:    "DiffWithTruncWithPrecisionFloat64x4",
+               name:    "ShiftAllRightAndFillUpperFromUint16x16",
                auxType: auxInt8,
-               argLen:  1,
+               argLen:  2,
                generic: true,
        },
        {
-               name:    "FloorSuppressExceptionWithPrecisionFloat64x4",
+               name:    "MaskedShiftAllLeftAndFillUpperFromUint16x32",
                auxType: auxInt8,
-               argLen:  1,
+               argLen:  3,
                generic: true,
        },
        {
-               name:    "FloorWithPrecisionFloat64x4",
+               name:    "MaskedShiftAllRightAndFillUpperFromUint16x32",
                auxType: auxInt8,
-               argLen:  1,
+               argLen:  3,
                generic: true,
        },
        {
-               name:    "MaskedCeilSuppressExceptionWithPrecisionFloat64x4",
+               name:    "ShiftAllLeftAndFillUpperFromUint16x32",
                auxType: auxInt8,
                argLen:  2,
                generic: true,
        },
        {
-               name:    "MaskedCeilWithPrecisionFloat64x4",
+               name:    "ShiftAllRightAndFillUpperFromUint16x32",
                auxType: auxInt8,
                argLen:  2,
                generic: true,
        },
        {
-               name:    "MaskedDiffWithCeilSuppressExceptionWithPrecisionFloat64x4",
+               name:    "GetElemUint16x8",
                auxType: auxInt8,
-               argLen:  2,
+               argLen:  1,
                generic: true,
        },
        {
-               name:    "MaskedDiffWithCeilWithPrecisionFloat64x4",
+               name:    "MaskedShiftAllLeftAndFillUpperFromUint16x8",
                auxType: auxInt8,
-               argLen:  2,
+               argLen:  3,
                generic: true,
        },
        {
-               name:    "MaskedDiffWithFloorSuppressExceptionWithPrecisionFloat64x4",
+               name:    "MaskedShiftAllRightAndFillUpperFromUint16x8",
                auxType: auxInt8,
-               argLen:  2,
+               argLen:  3,
                generic: true,
        },
        {
-               name:    "MaskedDiffWithFloorWithPrecisionFloat64x4",
+               name:    "SetElemUint16x8",
                auxType: auxInt8,
                argLen:  2,
                generic: true,
        },
        {
-               name:    "MaskedDiffWithRoundSuppressExceptionWithPrecisionFloat64x4",
+               name:    "ShiftAllLeftAndFillUpperFromUint16x8",
                auxType: auxInt8,
                argLen:  2,
                generic: true,
        },
        {
-               name:    "MaskedDiffWithRoundWithPrecisionFloat64x4",
+               name:    "ShiftAllRightAndFillUpperFromUint16x8",
                auxType: auxInt8,
                argLen:  2,
                generic: true,
        },
        {
-               name:    "MaskedDiffWithTruncSuppressExceptionWithPrecisionFloat64x4",
+               name:    "MaskedRotateAllLeftUint32x16",
                auxType: auxInt8,
                argLen:  2,
                generic: true,
        },
        {
-               name:    "MaskedDiffWithTruncWithPrecisionFloat64x4",
+               name:    "MaskedRotateAllRightUint32x16",
                auxType: auxInt8,
                argLen:  2,
                generic: true,
        },
        {
-               name:    "MaskedFloorSuppressExceptionWithPrecisionFloat64x4",
+               name:    "MaskedShiftAllLeftAndFillUpperFromUint32x16",
                auxType: auxInt8,
-               argLen:  2,
+               argLen:  3,
                generic: true,
        },
        {
-               name:    "MaskedFloorWithPrecisionFloat64x4",
+               name:    "MaskedShiftAllRightAndFillUpperFromUint32x16",
                auxType: auxInt8,
-               argLen:  2,
+               argLen:  3,
                generic: true,
        },
        {
-               name:    "MaskedRoundSuppressExceptionWithPrecisionFloat64x4",
+               name:    "RotateAllLeftUint32x16",
                auxType: auxInt8,
-               argLen:  2,
+               argLen:  1,
                generic: true,
        },
        {
-               name:    "MaskedRoundWithPrecisionFloat64x4",
+               name:    "RotateAllRightUint32x16",
                auxType: auxInt8,
-               argLen:  2,
+               argLen:  1,
                generic: true,
        },
        {
-               name:    "MaskedTruncSuppressExceptionWithPrecisionFloat64x4",
+               name:    "ShiftAllLeftAndFillUpperFromUint32x16",
                auxType: auxInt8,
                argLen:  2,
                generic: true,
        },
        {
-               name:    "MaskedTruncWithPrecisionFloat64x4",
+               name:    "ShiftAllRightAndFillUpperFromUint32x16",
                auxType: auxInt8,
                argLen:  2,
                generic: true,
        },
        {
-               name:    "RoundSuppressExceptionWithPrecisionFloat64x4",
+               name:    "GetElemUint32x4",
                auxType: auxInt8,
                argLen:  1,
                generic: true,
        },
        {
-               name:    "RoundWithPrecisionFloat64x4",
+               name:    "MaskedRotateAllLeftUint32x4",
                auxType: auxInt8,
-               argLen:  1,
+               argLen:  2,
                generic: true,
        },
        {
-               name:    "TruncSuppressExceptionWithPrecisionFloat64x4",
+               name:    "MaskedRotateAllRightUint32x4",
                auxType: auxInt8,
-               argLen:  1,
+               argLen:  2,
                generic: true,
        },
        {
-               name:    "TruncWithPrecisionFloat64x4",
+               name:    "MaskedShiftAllLeftAndFillUpperFromUint32x4",
                auxType: auxInt8,
-               argLen:  1,
+               argLen:  3,
                generic: true,
        },
        {
-               name:    "CeilSuppressExceptionWithPrecisionFloat64x8",
+               name:    "MaskedShiftAllRightAndFillUpperFromUint32x4",
                auxType: auxInt8,
-               argLen:  1,
+               argLen:  3,
                generic: true,
        },
        {
-               name:    "CeilWithPrecisionFloat64x8",
+               name:    "RotateAllLeftUint32x4",
                auxType: auxInt8,
                argLen:  1,
                generic: true,
        },
        {
-               name:    "DiffWithCeilSuppressExceptionWithPrecisionFloat64x8",
+               name:    "RotateAllRightUint32x4",
                auxType: auxInt8,
                argLen:  1,
                generic: true,
        },
        {
-               name:    "DiffWithCeilWithPrecisionFloat64x8",
+               name:    "SetElemUint32x4",
                auxType: auxInt8,
-               argLen:  1,
+               argLen:  2,
                generic: true,
        },
        {
-               name:    "DiffWithFloorSuppressExceptionWithPrecisionFloat64x8",
+               name:    "ShiftAllLeftAndFillUpperFromUint32x4",
                auxType: auxInt8,
-               argLen:  1,
+               argLen:  2,
                generic: true,
        },
        {
-               name:    "DiffWithFloorWithPrecisionFloat64x8",
+               name:    "ShiftAllRightAndFillUpperFromUint32x4",
                auxType: auxInt8,
-               argLen:  1,
+               argLen:  2,
                generic: true,
        },
        {
-               name:    "DiffWithRoundSuppressExceptionWithPrecisionFloat64x8",
+               name:    "MaskedRotateAllLeftUint32x8",
                auxType: auxInt8,
-               argLen:  1,
+               argLen:  2,
                generic: true,
        },
        {
-               name:    "DiffWithRoundWithPrecisionFloat64x8",
+               name:    "MaskedRotateAllRightUint32x8",
                auxType: auxInt8,
-               argLen:  1,
+               argLen:  2,
                generic: true,
        },
        {
-               name:    "DiffWithTruncSuppressExceptionWithPrecisionFloat64x8",
+               name:    "MaskedShiftAllLeftAndFillUpperFromUint32x8",
                auxType: auxInt8,
-               argLen:  1,
+               argLen:  3,
                generic: true,
        },
        {
-               name:    "DiffWithTruncWithPrecisionFloat64x8",
+               name:    "MaskedShiftAllRightAndFillUpperFromUint32x8",
                auxType: auxInt8,
-               argLen:  1,
+               argLen:  3,
                generic: true,
        },
        {
-               name:    "FloorSuppressExceptionWithPrecisionFloat64x8",
+               name:    "RotateAllLeftUint32x8",
                auxType: auxInt8,
                argLen:  1,
                generic: true,
        },
        {
-               name:    "FloorWithPrecisionFloat64x8",
+               name:    "RotateAllRightUint32x8",
                auxType: auxInt8,
                argLen:  1,
                generic: true,
        },
        {
-               name:    "MaskedCeilSuppressExceptionWithPrecisionFloat64x8",
-               auxType: auxInt8,
-               argLen:  2,
-               generic: true,
-       },
-       {
-               name:    "MaskedCeilWithPrecisionFloat64x8",
-               auxType: auxInt8,
-               argLen:  2,
-               generic: true,
-       },
-       {
-               name:    "MaskedDiffWithCeilSuppressExceptionWithPrecisionFloat64x8",
+               name:    "ShiftAllLeftAndFillUpperFromUint32x8",
                auxType: auxInt8,
                argLen:  2,
                generic: true,
        },
        {
-               name:    "MaskedDiffWithCeilWithPrecisionFloat64x8",
+               name:    "ShiftAllRightAndFillUpperFromUint32x8",
                auxType: auxInt8,
                argLen:  2,
                generic: true,
        },
        {
-               name:    "MaskedDiffWithFloorSuppressExceptionWithPrecisionFloat64x8",
+               name:    "GetElemUint64x2",
                auxType: auxInt8,
-               argLen:  2,
+               argLen:  1,
                generic: true,
        },
        {
-               name:    "MaskedDiffWithFloorWithPrecisionFloat64x8",
+               name:    "MaskedRotateAllLeftUint64x2",
                auxType: auxInt8,
                argLen:  2,
                generic: true,
        },
        {
-               name:    "MaskedDiffWithRoundSuppressExceptionWithPrecisionFloat64x8",
+               name:    "MaskedRotateAllRightUint64x2",
                auxType: auxInt8,
                argLen:  2,
                generic: true,
        },
        {
-               name:    "MaskedDiffWithRoundWithPrecisionFloat64x8",
+               name:    "MaskedShiftAllLeftAndFillUpperFromUint64x2",
                auxType: auxInt8,
-               argLen:  2,
+               argLen:  3,
                generic: true,
        },
        {
-               name:    "MaskedDiffWithTruncSuppressExceptionWithPrecisionFloat64x8",
+               name:    "MaskedShiftAllRightAndFillUpperFromUint64x2",
                auxType: auxInt8,
-               argLen:  2,
+               argLen:  3,
                generic: true,
        },
        {
-               name:    "MaskedDiffWithTruncWithPrecisionFloat64x8",
+               name:    "RotateAllLeftUint64x2",
                auxType: auxInt8,
-               argLen:  2,
+               argLen:  1,
                generic: true,
        },
        {
-               name:    "MaskedFloorSuppressExceptionWithPrecisionFloat64x8",
+               name:    "RotateAllRightUint64x2",
                auxType: auxInt8,
-               argLen:  2,
+               argLen:  1,
                generic: true,
        },
        {
-               name:    "MaskedFloorWithPrecisionFloat64x8",
+               name:    "SetElemUint64x2",
                auxType: auxInt8,
                argLen:  2,
                generic: true,
        },
        {
-               name:    "MaskedRoundSuppressExceptionWithPrecisionFloat64x8",
+               name:    "ShiftAllLeftAndFillUpperFromUint64x2",
                auxType: auxInt8,
                argLen:  2,
                generic: true,
        },
        {
-               name:    "MaskedRoundWithPrecisionFloat64x8",
+               name:    "ShiftAllRightAndFillUpperFromUint64x2",
                auxType: auxInt8,
                argLen:  2,
                generic: true,
        },
        {
-               name:    "MaskedTruncSuppressExceptionWithPrecisionFloat64x8",
+               name:    "MaskedRotateAllLeftUint64x4",
                auxType: auxInt8,
                argLen:  2,
                generic: true,
        },
        {
-               name:    "MaskedTruncWithPrecisionFloat64x8",
+               name:    "MaskedRotateAllRightUint64x4",
                auxType: auxInt8,
                argLen:  2,
                generic: true,
        },
        {
-               name:    "RoundSuppressExceptionWithPrecisionFloat64x8",
-               auxType: auxInt8,
-               argLen:  1,
-               generic: true,
-       },
-       {
-               name:    "RoundWithPrecisionFloat64x8",
+               name:    "MaskedShiftAllLeftAndFillUpperFromUint64x4",
                auxType: auxInt8,
-               argLen:  1,
+               argLen:  3,
                generic: true,
        },
        {
-               name:    "TruncSuppressExceptionWithPrecisionFloat64x8",
+               name:    "MaskedShiftAllRightAndFillUpperFromUint64x4",
                auxType: auxInt8,
-               argLen:  1,
+               argLen:  3,
                generic: true,
        },
        {
-               name:    "TruncWithPrecisionFloat64x8",
+               name:    "RotateAllLeftUint64x4",
                auxType: auxInt8,
                argLen:  1,
                generic: true,
        },
        {
-               name:    "GetElemInt16x8",
+               name:    "RotateAllRightUint64x4",
                auxType: auxInt8,
                argLen:  1,
                generic: true,
        },
        {
-               name:    "SetElemInt16x8",
+               name:    "ShiftAllLeftAndFillUpperFromUint64x4",
                auxType: auxInt8,
                argLen:  2,
                generic: true,
        },
        {
-               name:    "GetElemInt32x4",
-               auxType: auxInt8,
-               argLen:  1,
-               generic: true,
-       },
-       {
-               name:    "SetElemInt32x4",
+               name:    "ShiftAllRightAndFillUpperFromUint64x4",
                auxType: auxInt8,
                argLen:  2,
                generic: true,
        },
        {
-               name:    "GetElemInt64x2",
+               name:    "MaskedRotateAllLeftUint64x8",
                auxType: auxInt8,
-               argLen:  1,
+               argLen:  2,
                generic: true,
        },
        {
-               name:    "SetElemInt64x2",
+               name:    "MaskedRotateAllRightUint64x8",
                auxType: auxInt8,
                argLen:  2,
                generic: true,
        },
        {
-               name:    "GetElemInt8x16",
+               name:    "MaskedShiftAllLeftAndFillUpperFromUint64x8",
                auxType: auxInt8,
-               argLen:  1,
+               argLen:  3,
                generic: true,
        },
        {
-               name:    "SetElemInt8x16",
+               name:    "MaskedShiftAllRightAndFillUpperFromUint64x8",
                auxType: auxInt8,
-               argLen:  2,
+               argLen:  3,
                generic: true,
        },
        {
-               name:    "GetElemUint16x8",
+               name:    "RotateAllLeftUint64x8",
                auxType: auxInt8,
                argLen:  1,
                generic: true,
        },
        {
-               name:    "SetElemUint16x8",
-               auxType: auxInt8,
-               argLen:  2,
-               generic: true,
-       },
-       {
-               name:    "GetElemUint32x4",
+               name:    "RotateAllRightUint64x8",
                auxType: auxInt8,
                argLen:  1,
                generic: true,
        },
        {
-               name:    "SetElemUint32x4",
+               name:    "ShiftAllLeftAndFillUpperFromUint64x8",
                auxType: auxInt8,
                argLen:  2,
                generic: true,
        },
        {
-               name:    "GetElemUint64x2",
-               auxType: auxInt8,
-               argLen:  1,
-               generic: true,
-       },
-       {
-               name:    "SetElemUint64x2",
+               name:    "ShiftAllRightAndFillUpperFromUint64x8",
                auxType: auxInt8,
                argLen:  2,
                generic: true,

diff --git a/src/cmd/compile/internal/ssa/rewriteAMD64.go b/src/cmd/compile/internal/ssa/rewriteAMD64.go
index 668024a00fb52b2ff968ca6d3124b52cff96d41b..d7aa0339e7c8c0061743a78c6fbeae85707b14bb 100644 (file)
--- a/src/cmd/compile/internal/ssa/rewriteAMD64.go
+++ b/src/cmd/compile/internal/ssa/rewriteAMD64.go
@@ -2862,6 +2862,102 @@ func rewriteValueAMD64(v *Value) bool {
                return rewriteValueAMD64_OpMaskedPopCountUint8x32(v)
        case OpMaskedPopCountUint8x64:
                return rewriteValueAMD64_OpMaskedPopCountUint8x64(v)
+       case OpMaskedRotateAllLeftInt32x16:
+               return rewriteValueAMD64_OpMaskedRotateAllLeftInt32x16(v)
+       case OpMaskedRotateAllLeftInt32x4:
+               return rewriteValueAMD64_OpMaskedRotateAllLeftInt32x4(v)
+       case OpMaskedRotateAllLeftInt32x8:
+               return rewriteValueAMD64_OpMaskedRotateAllLeftInt32x8(v)
+       case OpMaskedRotateAllLeftInt64x2:
+               return rewriteValueAMD64_OpMaskedRotateAllLeftInt64x2(v)
+       case OpMaskedRotateAllLeftInt64x4:
+               return rewriteValueAMD64_OpMaskedRotateAllLeftInt64x4(v)
+       case OpMaskedRotateAllLeftInt64x8:
+               return rewriteValueAMD64_OpMaskedRotateAllLeftInt64x8(v)
+       case OpMaskedRotateAllLeftUint32x16:
+               return rewriteValueAMD64_OpMaskedRotateAllLeftUint32x16(v)
+       case OpMaskedRotateAllLeftUint32x4:
+               return rewriteValueAMD64_OpMaskedRotateAllLeftUint32x4(v)
+       case OpMaskedRotateAllLeftUint32x8:
+               return rewriteValueAMD64_OpMaskedRotateAllLeftUint32x8(v)
+       case OpMaskedRotateAllLeftUint64x2:
+               return rewriteValueAMD64_OpMaskedRotateAllLeftUint64x2(v)
+       case OpMaskedRotateAllLeftUint64x4:
+               return rewriteValueAMD64_OpMaskedRotateAllLeftUint64x4(v)
+       case OpMaskedRotateAllLeftUint64x8:
+               return rewriteValueAMD64_OpMaskedRotateAllLeftUint64x8(v)
+       case OpMaskedRotateAllRightInt32x16:
+               return rewriteValueAMD64_OpMaskedRotateAllRightInt32x16(v)
+       case OpMaskedRotateAllRightInt32x4:
+               return rewriteValueAMD64_OpMaskedRotateAllRightInt32x4(v)
+       case OpMaskedRotateAllRightInt32x8:
+               return rewriteValueAMD64_OpMaskedRotateAllRightInt32x8(v)
+       case OpMaskedRotateAllRightInt64x2:
+               return rewriteValueAMD64_OpMaskedRotateAllRightInt64x2(v)
+       case OpMaskedRotateAllRightInt64x4:
+               return rewriteValueAMD64_OpMaskedRotateAllRightInt64x4(v)
+       case OpMaskedRotateAllRightInt64x8:
+               return rewriteValueAMD64_OpMaskedRotateAllRightInt64x8(v)
+       case OpMaskedRotateAllRightUint32x16:
+               return rewriteValueAMD64_OpMaskedRotateAllRightUint32x16(v)
+       case OpMaskedRotateAllRightUint32x4:
+               return rewriteValueAMD64_OpMaskedRotateAllRightUint32x4(v)
+       case OpMaskedRotateAllRightUint32x8:
+               return rewriteValueAMD64_OpMaskedRotateAllRightUint32x8(v)
+       case OpMaskedRotateAllRightUint64x2:
+               return rewriteValueAMD64_OpMaskedRotateAllRightUint64x2(v)
+       case OpMaskedRotateAllRightUint64x4:
+               return rewriteValueAMD64_OpMaskedRotateAllRightUint64x4(v)
+       case OpMaskedRotateAllRightUint64x8:
+               return rewriteValueAMD64_OpMaskedRotateAllRightUint64x8(v)
+       case OpMaskedRotateLeftInt32x16:
+               return rewriteValueAMD64_OpMaskedRotateLeftInt32x16(v)
+       case OpMaskedRotateLeftInt32x4:
+               return rewriteValueAMD64_OpMaskedRotateLeftInt32x4(v)
+       case OpMaskedRotateLeftInt32x8:
+               return rewriteValueAMD64_OpMaskedRotateLeftInt32x8(v)
+       case OpMaskedRotateLeftInt64x2:
+               return rewriteValueAMD64_OpMaskedRotateLeftInt64x2(v)
+       case OpMaskedRotateLeftInt64x4:
+               return rewriteValueAMD64_OpMaskedRotateLeftInt64x4(v)
+       case OpMaskedRotateLeftInt64x8:
+               return rewriteValueAMD64_OpMaskedRotateLeftInt64x8(v)
+       case OpMaskedRotateLeftUint32x16:
+               return rewriteValueAMD64_OpMaskedRotateLeftUint32x16(v)
+       case OpMaskedRotateLeftUint32x4:
+               return rewriteValueAMD64_OpMaskedRotateLeftUint32x4(v)
+       case OpMaskedRotateLeftUint32x8:
+               return rewriteValueAMD64_OpMaskedRotateLeftUint32x8(v)
+       case OpMaskedRotateLeftUint64x2:
+               return rewriteValueAMD64_OpMaskedRotateLeftUint64x2(v)
+       case OpMaskedRotateLeftUint64x4:
+               return rewriteValueAMD64_OpMaskedRotateLeftUint64x4(v)
+       case OpMaskedRotateLeftUint64x8:
+               return rewriteValueAMD64_OpMaskedRotateLeftUint64x8(v)
+       case OpMaskedRotateRightInt32x16:
+               return rewriteValueAMD64_OpMaskedRotateRightInt32x16(v)
+       case OpMaskedRotateRightInt32x4:
+               return rewriteValueAMD64_OpMaskedRotateRightInt32x4(v)
+       case OpMaskedRotateRightInt32x8:
+               return rewriteValueAMD64_OpMaskedRotateRightInt32x8(v)
+       case OpMaskedRotateRightInt64x2:
+               return rewriteValueAMD64_OpMaskedRotateRightInt64x2(v)
+       case OpMaskedRotateRightInt64x4:
+               return rewriteValueAMD64_OpMaskedRotateRightInt64x4(v)
+       case OpMaskedRotateRightInt64x8:
+               return rewriteValueAMD64_OpMaskedRotateRightInt64x8(v)
+       case OpMaskedRotateRightUint32x16:
+               return rewriteValueAMD64_OpMaskedRotateRightUint32x16(v)
+       case OpMaskedRotateRightUint32x4:
+               return rewriteValueAMD64_OpMaskedRotateRightUint32x4(v)
+       case OpMaskedRotateRightUint32x8:
+               return rewriteValueAMD64_OpMaskedRotateRightUint32x8(v)
+       case OpMaskedRotateRightUint64x2:
+               return rewriteValueAMD64_OpMaskedRotateRightUint64x2(v)
+       case OpMaskedRotateRightUint64x4:
+               return rewriteValueAMD64_OpMaskedRotateRightUint64x4(v)
+       case OpMaskedRotateRightUint64x8:
+               return rewriteValueAMD64_OpMaskedRotateRightUint64x8(v)
        case OpMaskedRoundSuppressExceptionWithPrecisionFloat32x16:
                return rewriteValueAMD64_OpMaskedRoundSuppressExceptionWithPrecisionFloat32x16(v)
        case OpMaskedRoundSuppressExceptionWithPrecisionFloat32x4:
@@ -2958,6 +3054,288 @@ func rewriteValueAMD64(v *Value) bool {
                return rewriteValueAMD64_OpMaskedSaturatedUnsignedSignedQuadDotProdAccumulateUint32x4(v)
        case OpMaskedSaturatedUnsignedSignedQuadDotProdAccumulateUint32x8:
                return rewriteValueAMD64_OpMaskedSaturatedUnsignedSignedQuadDotProdAccumulateUint32x8(v)
+       case OpMaskedShiftAllLeftAndFillUpperFromInt16x16:
+               return rewriteValueAMD64_OpMaskedShiftAllLeftAndFillUpperFromInt16x16(v)
+       case OpMaskedShiftAllLeftAndFillUpperFromInt16x32:
+               return rewriteValueAMD64_OpMaskedShiftAllLeftAndFillUpperFromInt16x32(v)
+       case OpMaskedShiftAllLeftAndFillUpperFromInt16x8:
+               return rewriteValueAMD64_OpMaskedShiftAllLeftAndFillUpperFromInt16x8(v)
+       case OpMaskedShiftAllLeftAndFillUpperFromInt32x16:
+               return rewriteValueAMD64_OpMaskedShiftAllLeftAndFillUpperFromInt32x16(v)
+       case OpMaskedShiftAllLeftAndFillUpperFromInt32x4:
+               return rewriteValueAMD64_OpMaskedShiftAllLeftAndFillUpperFromInt32x4(v)
+       case OpMaskedShiftAllLeftAndFillUpperFromInt32x8:
+               return rewriteValueAMD64_OpMaskedShiftAllLeftAndFillUpperFromInt32x8(v)
+       case OpMaskedShiftAllLeftAndFillUpperFromInt64x2:
+               return rewriteValueAMD64_OpMaskedShiftAllLeftAndFillUpperFromInt64x2(v)
+       case OpMaskedShiftAllLeftAndFillUpperFromInt64x4:
+               return rewriteValueAMD64_OpMaskedShiftAllLeftAndFillUpperFromInt64x4(v)
+       case OpMaskedShiftAllLeftAndFillUpperFromInt64x8:
+               return rewriteValueAMD64_OpMaskedShiftAllLeftAndFillUpperFromInt64x8(v)
+       case OpMaskedShiftAllLeftAndFillUpperFromUint16x16:
+               return rewriteValueAMD64_OpMaskedShiftAllLeftAndFillUpperFromUint16x16(v)
+       case OpMaskedShiftAllLeftAndFillUpperFromUint16x32:
+               return rewriteValueAMD64_OpMaskedShiftAllLeftAndFillUpperFromUint16x32(v)
+       case OpMaskedShiftAllLeftAndFillUpperFromUint16x8:
+               return rewriteValueAMD64_OpMaskedShiftAllLeftAndFillUpperFromUint16x8(v)
+       case OpMaskedShiftAllLeftAndFillUpperFromUint32x16:
+               return rewriteValueAMD64_OpMaskedShiftAllLeftAndFillUpperFromUint32x16(v)
+       case OpMaskedShiftAllLeftAndFillUpperFromUint32x4:
+               return rewriteValueAMD64_OpMaskedShiftAllLeftAndFillUpperFromUint32x4(v)
+       case OpMaskedShiftAllLeftAndFillUpperFromUint32x8:
+               return rewriteValueAMD64_OpMaskedShiftAllLeftAndFillUpperFromUint32x8(v)
+       case OpMaskedShiftAllLeftAndFillUpperFromUint64x2:
+               return rewriteValueAMD64_OpMaskedShiftAllLeftAndFillUpperFromUint64x2(v)
+       case OpMaskedShiftAllLeftAndFillUpperFromUint64x4:
+               return rewriteValueAMD64_OpMaskedShiftAllLeftAndFillUpperFromUint64x4(v)
+       case OpMaskedShiftAllLeftAndFillUpperFromUint64x8:
+               return rewriteValueAMD64_OpMaskedShiftAllLeftAndFillUpperFromUint64x8(v)
+       case OpMaskedShiftAllLeftInt64x2:
+               return rewriteValueAMD64_OpMaskedShiftAllLeftInt64x2(v)
+       case OpMaskedShiftAllLeftInt64x4:
+               return rewriteValueAMD64_OpMaskedShiftAllLeftInt64x4(v)
+       case OpMaskedShiftAllLeftInt64x8:
+               return rewriteValueAMD64_OpMaskedShiftAllLeftInt64x8(v)
+       case OpMaskedShiftAllLeftUint64x2:
+               return rewriteValueAMD64_OpMaskedShiftAllLeftUint64x2(v)
+       case OpMaskedShiftAllLeftUint64x4:
+               return rewriteValueAMD64_OpMaskedShiftAllLeftUint64x4(v)
+       case OpMaskedShiftAllLeftUint64x8:
+               return rewriteValueAMD64_OpMaskedShiftAllLeftUint64x8(v)
+       case OpMaskedShiftAllRightAndFillUpperFromInt16x16:
+               return rewriteValueAMD64_OpMaskedShiftAllRightAndFillUpperFromInt16x16(v)
+       case OpMaskedShiftAllRightAndFillUpperFromInt16x32:
+               return rewriteValueAMD64_OpMaskedShiftAllRightAndFillUpperFromInt16x32(v)
+       case OpMaskedShiftAllRightAndFillUpperFromInt16x8:
+               return rewriteValueAMD64_OpMaskedShiftAllRightAndFillUpperFromInt16x8(v)
+       case OpMaskedShiftAllRightAndFillUpperFromInt32x16:
+               return rewriteValueAMD64_OpMaskedShiftAllRightAndFillUpperFromInt32x16(v)
+       case OpMaskedShiftAllRightAndFillUpperFromInt32x4:
+               return rewriteValueAMD64_OpMaskedShiftAllRightAndFillUpperFromInt32x4(v)
+       case OpMaskedShiftAllRightAndFillUpperFromInt32x8:
+               return rewriteValueAMD64_OpMaskedShiftAllRightAndFillUpperFromInt32x8(v)
+       case OpMaskedShiftAllRightAndFillUpperFromInt64x2:
+               return rewriteValueAMD64_OpMaskedShiftAllRightAndFillUpperFromInt64x2(v)
+       case OpMaskedShiftAllRightAndFillUpperFromInt64x4:
+               return rewriteValueAMD64_OpMaskedShiftAllRightAndFillUpperFromInt64x4(v)
+       case OpMaskedShiftAllRightAndFillUpperFromInt64x8:
+               return rewriteValueAMD64_OpMaskedShiftAllRightAndFillUpperFromInt64x8(v)
+       case OpMaskedShiftAllRightAndFillUpperFromUint16x16:
+               return rewriteValueAMD64_OpMaskedShiftAllRightAndFillUpperFromUint16x16(v)
+       case OpMaskedShiftAllRightAndFillUpperFromUint16x32:
+               return rewriteValueAMD64_OpMaskedShiftAllRightAndFillUpperFromUint16x32(v)
+       case OpMaskedShiftAllRightAndFillUpperFromUint16x8:
+               return rewriteValueAMD64_OpMaskedShiftAllRightAndFillUpperFromUint16x8(v)
+       case OpMaskedShiftAllRightAndFillUpperFromUint32x16:
+               return rewriteValueAMD64_OpMaskedShiftAllRightAndFillUpperFromUint32x16(v)
+       case OpMaskedShiftAllRightAndFillUpperFromUint32x4:
+               return rewriteValueAMD64_OpMaskedShiftAllRightAndFillUpperFromUint32x4(v)
+       case OpMaskedShiftAllRightAndFillUpperFromUint32x8:
+               return rewriteValueAMD64_OpMaskedShiftAllRightAndFillUpperFromUint32x8(v)
+       case OpMaskedShiftAllRightAndFillUpperFromUint64x2:
+               return rewriteValueAMD64_OpMaskedShiftAllRightAndFillUpperFromUint64x2(v)
+       case OpMaskedShiftAllRightAndFillUpperFromUint64x4:
+               return rewriteValueAMD64_OpMaskedShiftAllRightAndFillUpperFromUint64x4(v)
+       case OpMaskedShiftAllRightAndFillUpperFromUint64x8:
+               return rewriteValueAMD64_OpMaskedShiftAllRightAndFillUpperFromUint64x8(v)
+       case OpMaskedShiftAllRightInt64x2:
+               return rewriteValueAMD64_OpMaskedShiftAllRightInt64x2(v)
+       case OpMaskedShiftAllRightInt64x4:
+               return rewriteValueAMD64_OpMaskedShiftAllRightInt64x4(v)
+       case OpMaskedShiftAllRightInt64x8:
+               return rewriteValueAMD64_OpMaskedShiftAllRightInt64x8(v)
+       case OpMaskedShiftAllRightSignExtendedInt64x2:
+               return rewriteValueAMD64_OpMaskedShiftAllRightSignExtendedInt64x2(v)
+       case OpMaskedShiftAllRightSignExtendedInt64x4:
+               return rewriteValueAMD64_OpMaskedShiftAllRightSignExtendedInt64x4(v)
+       case OpMaskedShiftAllRightSignExtendedInt64x8:
+               return rewriteValueAMD64_OpMaskedShiftAllRightSignExtendedInt64x8(v)
+       case OpMaskedShiftAllRightUint64x2:
+               return rewriteValueAMD64_OpMaskedShiftAllRightUint64x2(v)
+       case OpMaskedShiftAllRightUint64x4:
+               return rewriteValueAMD64_OpMaskedShiftAllRightUint64x4(v)
+       case OpMaskedShiftAllRightUint64x8:
+               return rewriteValueAMD64_OpMaskedShiftAllRightUint64x8(v)
+       case OpMaskedShiftLeftAndFillUpperFromInt16x16:
+               return rewriteValueAMD64_OpMaskedShiftLeftAndFillUpperFromInt16x16(v)
+       case OpMaskedShiftLeftAndFillUpperFromInt16x32:
+               return rewriteValueAMD64_OpMaskedShiftLeftAndFillUpperFromInt16x32(v)
+       case OpMaskedShiftLeftAndFillUpperFromInt16x8:
+               return rewriteValueAMD64_OpMaskedShiftLeftAndFillUpperFromInt16x8(v)
+       case OpMaskedShiftLeftAndFillUpperFromInt32x16:
+               return rewriteValueAMD64_OpMaskedShiftLeftAndFillUpperFromInt32x16(v)
+       case OpMaskedShiftLeftAndFillUpperFromInt32x4:
+               return rewriteValueAMD64_OpMaskedShiftLeftAndFillUpperFromInt32x4(v)
+       case OpMaskedShiftLeftAndFillUpperFromInt32x8:
+               return rewriteValueAMD64_OpMaskedShiftLeftAndFillUpperFromInt32x8(v)
+       case OpMaskedShiftLeftAndFillUpperFromInt64x2:
+               return rewriteValueAMD64_OpMaskedShiftLeftAndFillUpperFromInt64x2(v)
+       case OpMaskedShiftLeftAndFillUpperFromInt64x4:
+               return rewriteValueAMD64_OpMaskedShiftLeftAndFillUpperFromInt64x4(v)
+       case OpMaskedShiftLeftAndFillUpperFromInt64x8:
+               return rewriteValueAMD64_OpMaskedShiftLeftAndFillUpperFromInt64x8(v)
+       case OpMaskedShiftLeftAndFillUpperFromUint16x16:
+               return rewriteValueAMD64_OpMaskedShiftLeftAndFillUpperFromUint16x16(v)
+       case OpMaskedShiftLeftAndFillUpperFromUint16x32:
+               return rewriteValueAMD64_OpMaskedShiftLeftAndFillUpperFromUint16x32(v)
+       case OpMaskedShiftLeftAndFillUpperFromUint16x8:
+               return rewriteValueAMD64_OpMaskedShiftLeftAndFillUpperFromUint16x8(v)
+       case OpMaskedShiftLeftAndFillUpperFromUint32x16:
+               return rewriteValueAMD64_OpMaskedShiftLeftAndFillUpperFromUint32x16(v)
+       case OpMaskedShiftLeftAndFillUpperFromUint32x4:
+               return rewriteValueAMD64_OpMaskedShiftLeftAndFillUpperFromUint32x4(v)
+       case OpMaskedShiftLeftAndFillUpperFromUint32x8:
+               return rewriteValueAMD64_OpMaskedShiftLeftAndFillUpperFromUint32x8(v)
+       case OpMaskedShiftLeftAndFillUpperFromUint64x2:
+               return rewriteValueAMD64_OpMaskedShiftLeftAndFillUpperFromUint64x2(v)
+       case OpMaskedShiftLeftAndFillUpperFromUint64x4:
+               return rewriteValueAMD64_OpMaskedShiftLeftAndFillUpperFromUint64x4(v)
+       case OpMaskedShiftLeftAndFillUpperFromUint64x8:
+               return rewriteValueAMD64_OpMaskedShiftLeftAndFillUpperFromUint64x8(v)
+       case OpMaskedShiftLeftInt16x16:
+               return rewriteValueAMD64_OpMaskedShiftLeftInt16x16(v)
+       case OpMaskedShiftLeftInt16x32:
+               return rewriteValueAMD64_OpMaskedShiftLeftInt16x32(v)
+       case OpMaskedShiftLeftInt16x8:
+               return rewriteValueAMD64_OpMaskedShiftLeftInt16x8(v)
+       case OpMaskedShiftLeftInt32x16:
+               return rewriteValueAMD64_OpMaskedShiftLeftInt32x16(v)
+       case OpMaskedShiftLeftInt32x4:
+               return rewriteValueAMD64_OpMaskedShiftLeftInt32x4(v)
+       case OpMaskedShiftLeftInt32x8:
+               return rewriteValueAMD64_OpMaskedShiftLeftInt32x8(v)
+       case OpMaskedShiftLeftInt64x2:
+               return rewriteValueAMD64_OpMaskedShiftLeftInt64x2(v)
+       case OpMaskedShiftLeftInt64x4:
+               return rewriteValueAMD64_OpMaskedShiftLeftInt64x4(v)
+       case OpMaskedShiftLeftInt64x8:
+               return rewriteValueAMD64_OpMaskedShiftLeftInt64x8(v)
+       case OpMaskedShiftLeftUint16x16:
+               return rewriteValueAMD64_OpMaskedShiftLeftUint16x16(v)
+       case OpMaskedShiftLeftUint16x32:
+               return rewriteValueAMD64_OpMaskedShiftLeftUint16x32(v)
+       case OpMaskedShiftLeftUint16x8:
+               return rewriteValueAMD64_OpMaskedShiftLeftUint16x8(v)
+       case OpMaskedShiftLeftUint32x16:
+               return rewriteValueAMD64_OpMaskedShiftLeftUint32x16(v)
+       case OpMaskedShiftLeftUint32x4:
+               return rewriteValueAMD64_OpMaskedShiftLeftUint32x4(v)
+       case OpMaskedShiftLeftUint32x8:
+               return rewriteValueAMD64_OpMaskedShiftLeftUint32x8(v)
+       case OpMaskedShiftLeftUint64x2:
+               return rewriteValueAMD64_OpMaskedShiftLeftUint64x2(v)
+       case OpMaskedShiftLeftUint64x4:
+               return rewriteValueAMD64_OpMaskedShiftLeftUint64x4(v)
+       case OpMaskedShiftLeftUint64x8:
+               return rewriteValueAMD64_OpMaskedShiftLeftUint64x8(v)
+       case OpMaskedShiftRightAndFillUpperFromInt16x16:
+               return rewriteValueAMD64_OpMaskedShiftRightAndFillUpperFromInt16x16(v)
+       case OpMaskedShiftRightAndFillUpperFromInt16x32:
+               return rewriteValueAMD64_OpMaskedShiftRightAndFillUpperFromInt16x32(v)
+       case OpMaskedShiftRightAndFillUpperFromInt16x8:
+               return rewriteValueAMD64_OpMaskedShiftRightAndFillUpperFromInt16x8(v)
+       case OpMaskedShiftRightAndFillUpperFromInt32x16:
+               return rewriteValueAMD64_OpMaskedShiftRightAndFillUpperFromInt32x16(v)
+       case OpMaskedShiftRightAndFillUpperFromInt32x4:
+               return rewriteValueAMD64_OpMaskedShiftRightAndFillUpperFromInt32x4(v)
+       case OpMaskedShiftRightAndFillUpperFromInt32x8:
+               return rewriteValueAMD64_OpMaskedShiftRightAndFillUpperFromInt32x8(v)
+       case OpMaskedShiftRightAndFillUpperFromInt64x2:
+               return rewriteValueAMD64_OpMaskedShiftRightAndFillUpperFromInt64x2(v)
+       case OpMaskedShiftRightAndFillUpperFromInt64x4:
+               return rewriteValueAMD64_OpMaskedShiftRightAndFillUpperFromInt64x4(v)
+       case OpMaskedShiftRightAndFillUpperFromInt64x8:
+               return rewriteValueAMD64_OpMaskedShiftRightAndFillUpperFromInt64x8(v)
+       case OpMaskedShiftRightAndFillUpperFromUint16x16:
+               return rewriteValueAMD64_OpMaskedShiftRightAndFillUpperFromUint16x16(v)
+       case OpMaskedShiftRightAndFillUpperFromUint16x32:
+               return rewriteValueAMD64_OpMaskedShiftRightAndFillUpperFromUint16x32(v)
+       case OpMaskedShiftRightAndFillUpperFromUint16x8:
+               return rewriteValueAMD64_OpMaskedShiftRightAndFillUpperFromUint16x8(v)
+       case OpMaskedShiftRightAndFillUpperFromUint32x16:
+               return rewriteValueAMD64_OpMaskedShiftRightAndFillUpperFromUint32x16(v)
+       case OpMaskedShiftRightAndFillUpperFromUint32x4:
+               return rewriteValueAMD64_OpMaskedShiftRightAndFillUpperFromUint32x4(v)
+       case OpMaskedShiftRightAndFillUpperFromUint32x8:
+               return rewriteValueAMD64_OpMaskedShiftRightAndFillUpperFromUint32x8(v)
+       case OpMaskedShiftRightAndFillUpperFromUint64x2:
+               return rewriteValueAMD64_OpMaskedShiftRightAndFillUpperFromUint64x2(v)
+       case OpMaskedShiftRightAndFillUpperFromUint64x4:
+               return rewriteValueAMD64_OpMaskedShiftRightAndFillUpperFromUint64x4(v)
+       case OpMaskedShiftRightAndFillUpperFromUint64x8:
+               return rewriteValueAMD64_OpMaskedShiftRightAndFillUpperFromUint64x8(v)
+       case OpMaskedShiftRightInt16x16:
+               return rewriteValueAMD64_OpMaskedShiftRightInt16x16(v)
+       case OpMaskedShiftRightInt16x32:
+               return rewriteValueAMD64_OpMaskedShiftRightInt16x32(v)
+       case OpMaskedShiftRightInt16x8:
+               return rewriteValueAMD64_OpMaskedShiftRightInt16x8(v)
+       case OpMaskedShiftRightInt32x16:
+               return rewriteValueAMD64_OpMaskedShiftRightInt32x16(v)
+       case OpMaskedShiftRightInt32x4:
+               return rewriteValueAMD64_OpMaskedShiftRightInt32x4(v)
+       case OpMaskedShiftRightInt32x8:
+               return rewriteValueAMD64_OpMaskedShiftRightInt32x8(v)
+       case OpMaskedShiftRightInt64x2:
+               return rewriteValueAMD64_OpMaskedShiftRightInt64x2(v)
+       case OpMaskedShiftRightInt64x4:
+               return rewriteValueAMD64_OpMaskedShiftRightInt64x4(v)
+       case OpMaskedShiftRightInt64x8:
+               return rewriteValueAMD64_OpMaskedShiftRightInt64x8(v)
+       case OpMaskedShiftRightSignExtendedInt16x16:
+               return rewriteValueAMD64_OpMaskedShiftRightSignExtendedInt16x16(v)
+       case OpMaskedShiftRightSignExtendedInt16x32:
+               return rewriteValueAMD64_OpMaskedShiftRightSignExtendedInt16x32(v)
+       case OpMaskedShiftRightSignExtendedInt16x8:
+               return rewriteValueAMD64_OpMaskedShiftRightSignExtendedInt16x8(v)
+       case OpMaskedShiftRightSignExtendedInt32x16:
+               return rewriteValueAMD64_OpMaskedShiftRightSignExtendedInt32x16(v)
+       case OpMaskedShiftRightSignExtendedInt32x4:
+               return rewriteValueAMD64_OpMaskedShiftRightSignExtendedInt32x4(v)
+       case OpMaskedShiftRightSignExtendedInt32x8:
+               return rewriteValueAMD64_OpMaskedShiftRightSignExtendedInt32x8(v)
+       case OpMaskedShiftRightSignExtendedInt64x2:
+               return rewriteValueAMD64_OpMaskedShiftRightSignExtendedInt64x2(v)
+       case OpMaskedShiftRightSignExtendedInt64x4:
+               return rewriteValueAMD64_OpMaskedShiftRightSignExtendedInt64x4(v)
+       case OpMaskedShiftRightSignExtendedInt64x8:
+               return rewriteValueAMD64_OpMaskedShiftRightSignExtendedInt64x8(v)
+       case OpMaskedShiftRightSignExtendedUint16x16:
+               return rewriteValueAMD64_OpMaskedShiftRightSignExtendedUint16x16(v)
+       case OpMaskedShiftRightSignExtendedUint16x32:
+               return rewriteValueAMD64_OpMaskedShiftRightSignExtendedUint16x32(v)
+       case OpMaskedShiftRightSignExtendedUint16x8:
+               return rewriteValueAMD64_OpMaskedShiftRightSignExtendedUint16x8(v)
+       case OpMaskedShiftRightSignExtendedUint32x16:
+               return rewriteValueAMD64_OpMaskedShiftRightSignExtendedUint32x16(v)
+       case OpMaskedShiftRightSignExtendedUint32x4:
+               return rewriteValueAMD64_OpMaskedShiftRightSignExtendedUint32x4(v)
+       case OpMaskedShiftRightSignExtendedUint32x8:
+               return rewriteValueAMD64_OpMaskedShiftRightSignExtendedUint32x8(v)
+       case OpMaskedShiftRightSignExtendedUint64x2:
+               return rewriteValueAMD64_OpMaskedShiftRightSignExtendedUint64x2(v)
+       case OpMaskedShiftRightSignExtendedUint64x4:
+               return rewriteValueAMD64_OpMaskedShiftRightSignExtendedUint64x4(v)
+       case OpMaskedShiftRightSignExtendedUint64x8:
+               return rewriteValueAMD64_OpMaskedShiftRightSignExtendedUint64x8(v)
+       case OpMaskedShiftRightUint16x16:
+               return rewriteValueAMD64_OpMaskedShiftRightUint16x16(v)
+       case OpMaskedShiftRightUint16x32:
+               return rewriteValueAMD64_OpMaskedShiftRightUint16x32(v)
+       case OpMaskedShiftRightUint16x8:
+               return rewriteValueAMD64_OpMaskedShiftRightUint16x8(v)
+       case OpMaskedShiftRightUint32x16:
+               return rewriteValueAMD64_OpMaskedShiftRightUint32x16(v)
+       case OpMaskedShiftRightUint32x4:
+               return rewriteValueAMD64_OpMaskedShiftRightUint32x4(v)
+       case OpMaskedShiftRightUint32x8:
+               return rewriteValueAMD64_OpMaskedShiftRightUint32x8(v)
+       case OpMaskedShiftRightUint64x2:
+               return rewriteValueAMD64_OpMaskedShiftRightUint64x2(v)
+       case OpMaskedShiftRightUint64x4:
+               return rewriteValueAMD64_OpMaskedShiftRightUint64x4(v)
+       case OpMaskedShiftRightUint64x8:
+               return rewriteValueAMD64_OpMaskedShiftRightUint64x8(v)
        case OpMaskedSqrtFloat32x16:
                return rewriteValueAMD64_OpMaskedSqrtFloat32x16(v)
        case OpMaskedSqrtFloat32x4:
@@ -3812,6 +4190,54 @@ func rewriteValueAMD64(v *Value) bool {
        case OpPrefetchCacheStreamed:
                v.Op = OpAMD64PrefetchNTA
                return true
+       case OpRotateAllLeftInt32x16:
+               return rewriteValueAMD64_OpRotateAllLeftInt32x16(v)
+       case OpRotateAllLeftInt32x4:
+               return rewriteValueAMD64_OpRotateAllLeftInt32x4(v)
+       case OpRotateAllLeftInt32x8:
+               return rewriteValueAMD64_OpRotateAllLeftInt32x8(v)
+       case OpRotateAllLeftInt64x2:
+               return rewriteValueAMD64_OpRotateAllLeftInt64x2(v)
+       case OpRotateAllLeftInt64x4:
+               return rewriteValueAMD64_OpRotateAllLeftInt64x4(v)
+       case OpRotateAllLeftInt64x8:
+               return rewriteValueAMD64_OpRotateAllLeftInt64x8(v)
+       case OpRotateAllLeftUint32x16:
+               return rewriteValueAMD64_OpRotateAllLeftUint32x16(v)
+       case OpRotateAllLeftUint32x4:
+               return rewriteValueAMD64_OpRotateAllLeftUint32x4(v)
+       case OpRotateAllLeftUint32x8:
+               return rewriteValueAMD64_OpRotateAllLeftUint32x8(v)
+       case OpRotateAllLeftUint64x2:
+               return rewriteValueAMD64_OpRotateAllLeftUint64x2(v)
+       case OpRotateAllLeftUint64x4:
+               return rewriteValueAMD64_OpRotateAllLeftUint64x4(v)
+       case OpRotateAllLeftUint64x8:
+               return rewriteValueAMD64_OpRotateAllLeftUint64x8(v)
+       case OpRotateAllRightInt32x16:
+               return rewriteValueAMD64_OpRotateAllRightInt32x16(v)
+       case OpRotateAllRightInt32x4:
+               return rewriteValueAMD64_OpRotateAllRightInt32x4(v)
+       case OpRotateAllRightInt32x8:
+               return rewriteValueAMD64_OpRotateAllRightInt32x8(v)
+       case OpRotateAllRightInt64x2:
+               return rewriteValueAMD64_OpRotateAllRightInt64x2(v)
+       case OpRotateAllRightInt64x4:
+               return rewriteValueAMD64_OpRotateAllRightInt64x4(v)
+       case OpRotateAllRightInt64x8:
+               return rewriteValueAMD64_OpRotateAllRightInt64x8(v)
+       case OpRotateAllRightUint32x16:
+               return rewriteValueAMD64_OpRotateAllRightUint32x16(v)
+       case OpRotateAllRightUint32x4:
+               return rewriteValueAMD64_OpRotateAllRightUint32x4(v)
+       case OpRotateAllRightUint32x8:
+               return rewriteValueAMD64_OpRotateAllRightUint32x8(v)
+       case OpRotateAllRightUint64x2:
+               return rewriteValueAMD64_OpRotateAllRightUint64x2(v)
+       case OpRotateAllRightUint64x4:
+               return rewriteValueAMD64_OpRotateAllRightUint64x4(v)
+       case OpRotateAllRightUint64x8:
+               return rewriteValueAMD64_OpRotateAllRightUint64x8(v)
        case OpRotateLeft16:
                v.Op = OpAMD64ROLW
                return true
@@ -3824,6 +4250,78 @@ func rewriteValueAMD64(v *Value) bool {
        case OpRotateLeft8:
                v.Op = OpAMD64ROLB
                return true
+       case OpRotateLeftInt32x16:
+               v.Op = OpAMD64VPROLVD512
+               return true
+       case OpRotateLeftInt32x4:
+               v.Op = OpAMD64VPROLVD128
+               return true
+       case OpRotateLeftInt32x8:
+               v.Op = OpAMD64VPROLVD256
+               return true
+       case OpRotateLeftInt64x2:
+               v.Op = OpAMD64VPROLVQ128
+               return true
+       case OpRotateLeftInt64x4:
+               v.Op = OpAMD64VPROLVQ256
+               return true
+       case OpRotateLeftInt64x8:
+               v.Op = OpAMD64VPROLVQ512
+               return true
+       case OpRotateLeftUint32x16:
+               v.Op = OpAMD64VPROLVD512
+               return true
+       case OpRotateLeftUint32x4:
+               v.Op = OpAMD64VPROLVD128
+               return true
+       case OpRotateLeftUint32x8:
+               v.Op = OpAMD64VPROLVD256
+               return true
+       case OpRotateLeftUint64x2:
+               v.Op = OpAMD64VPROLVQ128
+               return true
+       case OpRotateLeftUint64x4:
+               v.Op = OpAMD64VPROLVQ256
+               return true
+       case OpRotateLeftUint64x8:
+               v.Op = OpAMD64VPROLVQ512
+               return true
+       case OpRotateRightInt32x16:
+               v.Op = OpAMD64VPRORVD512
+               return true
+       case OpRotateRightInt32x4:
+               v.Op = OpAMD64VPRORVD128
+               return true
+       case OpRotateRightInt32x8:
+               v.Op = OpAMD64VPRORVD256
+               return true
+       case OpRotateRightInt64x2:
+               v.Op = OpAMD64VPRORVQ128
+               return true
+       case OpRotateRightInt64x4:
+               v.Op = OpAMD64VPRORVQ256
+               return true
+       case OpRotateRightInt64x8:
+               v.Op = OpAMD64VPRORVQ512
+               return true
+       case OpRotateRightUint32x16:
+               v.Op = OpAMD64VPRORVD512
+               return true
+       case OpRotateRightUint32x4:
+               v.Op = OpAMD64VPRORVD128
+               return true
+       case OpRotateRightUint32x8:
+               v.Op = OpAMD64VPRORVD256
+               return true
+       case OpRotateRightUint64x2:
+               v.Op = OpAMD64VPRORVQ128
+               return true
+       case OpRotateRightUint64x4:
+               v.Op = OpAMD64VPRORVQ256
+               return true
+       case OpRotateRightUint64x8:
+               v.Op = OpAMD64VPRORVQ512
+               return true
        case OpRound32F:
                v.Op = OpAMD64LoweredRound32F
                return true
@@ -4070,6 +4568,453 @@ func rewriteValueAMD64(v *Value) bool {
                return rewriteValueAMD64_OpSetElemUint64x2(v)
        case OpSetElemUint8x16:
                return rewriteValueAMD64_OpSetElemUint8x16(v)
+       case OpShiftAllLeftAndFillUpperFromInt16x16:
+               return rewriteValueAMD64_OpShiftAllLeftAndFillUpperFromInt16x16(v)
+       case OpShiftAllLeftAndFillUpperFromInt16x32:
+               return rewriteValueAMD64_OpShiftAllLeftAndFillUpperFromInt16x32(v)
+       case OpShiftAllLeftAndFillUpperFromInt16x8:
+               return rewriteValueAMD64_OpShiftAllLeftAndFillUpperFromInt16x8(v)
+       case OpShiftAllLeftAndFillUpperFromInt32x16:
+               return rewriteValueAMD64_OpShiftAllLeftAndFillUpperFromInt32x16(v)
+       case OpShiftAllLeftAndFillUpperFromInt32x4:
+               return rewriteValueAMD64_OpShiftAllLeftAndFillUpperFromInt32x4(v)
+       case OpShiftAllLeftAndFillUpperFromInt32x8:
+               return rewriteValueAMD64_OpShiftAllLeftAndFillUpperFromInt32x8(v)
+       case OpShiftAllLeftAndFillUpperFromInt64x2:
+               return rewriteValueAMD64_OpShiftAllLeftAndFillUpperFromInt64x2(v)
+       case OpShiftAllLeftAndFillUpperFromInt64x4:
+               return rewriteValueAMD64_OpShiftAllLeftAndFillUpperFromInt64x4(v)
+       case OpShiftAllLeftAndFillUpperFromInt64x8:
+               return rewriteValueAMD64_OpShiftAllLeftAndFillUpperFromInt64x8(v)
+       case OpShiftAllLeftAndFillUpperFromUint16x16:
+               return rewriteValueAMD64_OpShiftAllLeftAndFillUpperFromUint16x16(v)
+       case OpShiftAllLeftAndFillUpperFromUint16x32:
+               return rewriteValueAMD64_OpShiftAllLeftAndFillUpperFromUint16x32(v)
+       case OpShiftAllLeftAndFillUpperFromUint16x8:
+               return rewriteValueAMD64_OpShiftAllLeftAndFillUpperFromUint16x8(v)
+       case OpShiftAllLeftAndFillUpperFromUint32x16:
+               return rewriteValueAMD64_OpShiftAllLeftAndFillUpperFromUint32x16(v)
+       case OpShiftAllLeftAndFillUpperFromUint32x4:
+               return rewriteValueAMD64_OpShiftAllLeftAndFillUpperFromUint32x4(v)
+       case OpShiftAllLeftAndFillUpperFromUint32x8:
+               return rewriteValueAMD64_OpShiftAllLeftAndFillUpperFromUint32x8(v)
+       case OpShiftAllLeftAndFillUpperFromUint64x2:
+               return rewriteValueAMD64_OpShiftAllLeftAndFillUpperFromUint64x2(v)
+       case OpShiftAllLeftAndFillUpperFromUint64x4:
+               return rewriteValueAMD64_OpShiftAllLeftAndFillUpperFromUint64x4(v)
+       case OpShiftAllLeftAndFillUpperFromUint64x8:
+               return rewriteValueAMD64_OpShiftAllLeftAndFillUpperFromUint64x8(v)
+       case OpShiftAllLeftInt16x16:
+               v.Op = OpAMD64VPSLLW256
+               return true
+       case OpShiftAllLeftInt16x8:
+               v.Op = OpAMD64VPSLLW128
+               return true
+       case OpShiftAllLeftInt32x4:
+               v.Op = OpAMD64VPSLLD128
+               return true
+       case OpShiftAllLeftInt32x8:
+               v.Op = OpAMD64VPSLLD256
+               return true
+       case OpShiftAllLeftInt64x2:
+               v.Op = OpAMD64VPSLLQ128
+               return true
+       case OpShiftAllLeftInt64x4:
+               v.Op = OpAMD64VPSLLQ256
+               return true
+       case OpShiftAllLeftInt64x8:
+               v.Op = OpAMD64VPSLLQ512
+               return true
+       case OpShiftAllLeftUint16x16:
+               v.Op = OpAMD64VPSLLW256
+               return true
+       case OpShiftAllLeftUint16x8:
+               v.Op = OpAMD64VPSLLW128
+               return true
+       case OpShiftAllLeftUint32x4:
+               v.Op = OpAMD64VPSLLD128
+               return true
+       case OpShiftAllLeftUint32x8:
+               v.Op = OpAMD64VPSLLD256
+               return true
+       case OpShiftAllLeftUint64x2:
+               v.Op = OpAMD64VPSLLQ128
+               return true
+       case OpShiftAllLeftUint64x4:
+               v.Op = OpAMD64VPSLLQ256
+               return true
+       case OpShiftAllLeftUint64x8:
+               v.Op = OpAMD64VPSLLQ512
+               return true
+       case OpShiftAllRightAndFillUpperFromInt16x16:
+               return rewriteValueAMD64_OpShiftAllRightAndFillUpperFromInt16x16(v)
+       case OpShiftAllRightAndFillUpperFromInt16x32:
+               return rewriteValueAMD64_OpShiftAllRightAndFillUpperFromInt16x32(v)
+       case OpShiftAllRightAndFillUpperFromInt16x8:
+               return rewriteValueAMD64_OpShiftAllRightAndFillUpperFromInt16x8(v)
+       case OpShiftAllRightAndFillUpperFromInt32x16:
+               return rewriteValueAMD64_OpShiftAllRightAndFillUpperFromInt32x16(v)
+       case OpShiftAllRightAndFillUpperFromInt32x4:
+               return rewriteValueAMD64_OpShiftAllRightAndFillUpperFromInt32x4(v)
+       case OpShiftAllRightAndFillUpperFromInt32x8:
+               return rewriteValueAMD64_OpShiftAllRightAndFillUpperFromInt32x8(v)
+       case OpShiftAllRightAndFillUpperFromInt64x2:
+               return rewriteValueAMD64_OpShiftAllRightAndFillUpperFromInt64x2(v)
+       case OpShiftAllRightAndFillUpperFromInt64x4:
+               return rewriteValueAMD64_OpShiftAllRightAndFillUpperFromInt64x4(v)
+       case OpShiftAllRightAndFillUpperFromInt64x8:
+               return rewriteValueAMD64_OpShiftAllRightAndFillUpperFromInt64x8(v)
+       case OpShiftAllRightAndFillUpperFromUint16x16:
+               return rewriteValueAMD64_OpShiftAllRightAndFillUpperFromUint16x16(v)
+       case OpShiftAllRightAndFillUpperFromUint16x32:
+               return rewriteValueAMD64_OpShiftAllRightAndFillUpperFromUint16x32(v)
+       case OpShiftAllRightAndFillUpperFromUint16x8:
+               return rewriteValueAMD64_OpShiftAllRightAndFillUpperFromUint16x8(v)
+       case OpShiftAllRightAndFillUpperFromUint32x16:
+               return rewriteValueAMD64_OpShiftAllRightAndFillUpperFromUint32x16(v)
+       case OpShiftAllRightAndFillUpperFromUint32x4:
+               return rewriteValueAMD64_OpShiftAllRightAndFillUpperFromUint32x4(v)
+       case OpShiftAllRightAndFillUpperFromUint32x8:
+               return rewriteValueAMD64_OpShiftAllRightAndFillUpperFromUint32x8(v)
+       case OpShiftAllRightAndFillUpperFromUint64x2:
+               return rewriteValueAMD64_OpShiftAllRightAndFillUpperFromUint64x2(v)
+       case OpShiftAllRightAndFillUpperFromUint64x4:
+               return rewriteValueAMD64_OpShiftAllRightAndFillUpperFromUint64x4(v)
+       case OpShiftAllRightAndFillUpperFromUint64x8:
+               return rewriteValueAMD64_OpShiftAllRightAndFillUpperFromUint64x8(v)
+       case OpShiftAllRightInt16x16:
+               v.Op = OpAMD64VPSRLW256
+               return true
+       case OpShiftAllRightInt16x8:
+               v.Op = OpAMD64VPSRLW128
+               return true
+       case OpShiftAllRightInt32x4:
+               v.Op = OpAMD64VPSRLD128
+               return true
+       case OpShiftAllRightInt32x8:
+               v.Op = OpAMD64VPSRLD256
+               return true
+       case OpShiftAllRightInt64x2:
+               v.Op = OpAMD64VPSRLQ128
+               return true
+       case OpShiftAllRightInt64x4:
+               v.Op = OpAMD64VPSRLQ256
+               return true
+       case OpShiftAllRightInt64x8:
+               v.Op = OpAMD64VPSRLQ512
+               return true
+       case OpShiftAllRightSignExtendedInt16x16:
+               v.Op = OpAMD64VPSRAW256
+               return true
+       case OpShiftAllRightSignExtendedInt16x8:
+               v.Op = OpAMD64VPSRAW128
+               return true
+       case OpShiftAllRightSignExtendedInt32x4:
+               v.Op = OpAMD64VPSRAD128
+               return true
+       case OpShiftAllRightSignExtendedInt32x8:
+               v.Op = OpAMD64VPSRAD256
+               return true
+       case OpShiftAllRightSignExtendedInt64x2:
+               v.Op = OpAMD64VPSRAQ128
+               return true
+       case OpShiftAllRightSignExtendedInt64x4:
+               v.Op = OpAMD64VPSRAQ256
+               return true
+       case OpShiftAllRightSignExtendedInt64x8:
+               v.Op = OpAMD64VPSRAQ512
+               return true
+       case OpShiftAllRightUint16x16:
+               v.Op = OpAMD64VPSRLW256
+               return true
+       case OpShiftAllRightUint16x8:
+               v.Op = OpAMD64VPSRLW128
+               return true
+       case OpShiftAllRightUint32x4:
+               v.Op = OpAMD64VPSRLD128
+               return true
+       case OpShiftAllRightUint32x8:
+               v.Op = OpAMD64VPSRLD256
+               return true
+       case OpShiftAllRightUint64x2:
+               v.Op = OpAMD64VPSRLQ128
+               return true
+       case OpShiftAllRightUint64x4:
+               v.Op = OpAMD64VPSRLQ256
+               return true
+       case OpShiftAllRightUint64x8:
+               v.Op = OpAMD64VPSRLQ512
+               return true
+       case OpShiftLeftAndFillUpperFromInt16x16:
+               v.Op = OpAMD64VPSHLDVW256
+               return true
+       case OpShiftLeftAndFillUpperFromInt16x32:
+               v.Op = OpAMD64VPSHLDVW512
+               return true
+       case OpShiftLeftAndFillUpperFromInt16x8:
+               v.Op = OpAMD64VPSHLDVW128
+               return true
+       case OpShiftLeftAndFillUpperFromInt32x16:
+               v.Op = OpAMD64VPSHLDVD512
+               return true
+       case OpShiftLeftAndFillUpperFromInt32x4:
+               v.Op = OpAMD64VPSHLDVD128
+               return true
+       case OpShiftLeftAndFillUpperFromInt32x8:
+               v.Op = OpAMD64VPSHLDVD256
+               return true
+       case OpShiftLeftAndFillUpperFromInt64x2:
+               v.Op = OpAMD64VPSHLDVQ128
+               return true
+       case OpShiftLeftAndFillUpperFromInt64x4:
+               v.Op = OpAMD64VPSHLDVQ256
+               return true
+       case OpShiftLeftAndFillUpperFromInt64x8:
+               v.Op = OpAMD64VPSHLDVQ512
+               return true
+       case OpShiftLeftAndFillUpperFromUint16x16:
+               v.Op = OpAMD64VPSHLDVW256
+               return true
+       case OpShiftLeftAndFillUpperFromUint16x32:
+               v.Op = OpAMD64VPSHLDVW512
+               return true
+       case OpShiftLeftAndFillUpperFromUint16x8:
+               v.Op = OpAMD64VPSHLDVW128
+               return true
+       case OpShiftLeftAndFillUpperFromUint32x16:
+               v.Op = OpAMD64VPSHLDVD512
+               return true
+       case OpShiftLeftAndFillUpperFromUint32x4:
+               v.Op = OpAMD64VPSHLDVD128
+               return true
+       case OpShiftLeftAndFillUpperFromUint32x8:
+               v.Op = OpAMD64VPSHLDVD256
+               return true
+       case OpShiftLeftAndFillUpperFromUint64x2:
+               v.Op = OpAMD64VPSHLDVQ128
+               return true
+       case OpShiftLeftAndFillUpperFromUint64x4:
+               v.Op = OpAMD64VPSHLDVQ256
+               return true
+       case OpShiftLeftAndFillUpperFromUint64x8:
+               v.Op = OpAMD64VPSHLDVQ512
+               return true
+       case OpShiftLeftInt16x16:
+               v.Op = OpAMD64VPSLLVW256
+               return true
+       case OpShiftLeftInt16x32:
+               v.Op = OpAMD64VPSLLVW512
+               return true
+       case OpShiftLeftInt16x8:
+               v.Op = OpAMD64VPSLLVW128
+               return true
+       case OpShiftLeftInt32x16:
+               v.Op = OpAMD64VPSLLVD512
+               return true
+       case OpShiftLeftInt32x4:
+               v.Op = OpAMD64VPSLLVD128
+               return true
+       case OpShiftLeftInt32x8:
+               v.Op = OpAMD64VPSLLVD256
+               return true
+       case OpShiftLeftInt64x2:
+               v.Op = OpAMD64VPSLLVQ128
+               return true
+       case OpShiftLeftInt64x4:
+               v.Op = OpAMD64VPSLLVQ256
+               return true
+       case OpShiftLeftInt64x8:
+               v.Op = OpAMD64VPSLLVQ512
+               return true
+       case OpShiftLeftUint16x16:
+               v.Op = OpAMD64VPSLLVW256
+               return true
+       case OpShiftLeftUint16x32:
+               v.Op = OpAMD64VPSLLVW512
+               return true
+       case OpShiftLeftUint16x8:
+               v.Op = OpAMD64VPSLLVW128
+               return true
+       case OpShiftLeftUint32x16:
+               v.Op = OpAMD64VPSLLVD512
+               return true
+       case OpShiftLeftUint32x4:
+               v.Op = OpAMD64VPSLLVD128
+               return true
+       case OpShiftLeftUint32x8:
+               v.Op = OpAMD64VPSLLVD256
+               return true
+       case OpShiftLeftUint64x2:
+               v.Op = OpAMD64VPSLLVQ128
+               return true
+       case OpShiftLeftUint64x4:
+               v.Op = OpAMD64VPSLLVQ256
+               return true
+       case OpShiftLeftUint64x8:
+               v.Op = OpAMD64VPSLLVQ512
+               return true
+       case OpShiftRightAndFillUpperFromInt16x16:
+               v.Op = OpAMD64VPSHRDVW256
+               return true
+       case OpShiftRightAndFillUpperFromInt16x32:
+               v.Op = OpAMD64VPSHRDVW512
+               return true
+       case OpShiftRightAndFillUpperFromInt16x8:
+               v.Op = OpAMD64VPSHRDVW128
+               return true
+       case OpShiftRightAndFillUpperFromInt32x16:
+               v.Op = OpAMD64VPSHRDVD512
+               return true
+       case OpShiftRightAndFillUpperFromInt32x4:
+               v.Op = OpAMD64VPSHRDVD128
+               return true
+       case OpShiftRightAndFillUpperFromInt32x8:
+               v.Op = OpAMD64VPSHRDVD256
+               return true
+       case OpShiftRightAndFillUpperFromInt64x2:
+               v.Op = OpAMD64VPSHRDVQ128
+               return true
+       case OpShiftRightAndFillUpperFromInt64x4:
+               v.Op = OpAMD64VPSHRDVQ256
+               return true
+       case OpShiftRightAndFillUpperFromInt64x8:
+               v.Op = OpAMD64VPSHRDVQ512
+               return true
+       case OpShiftRightAndFillUpperFromUint16x16:
+               v.Op = OpAMD64VPSHRDVW256
+               return true
+       case OpShiftRightAndFillUpperFromUint16x32:
+               v.Op = OpAMD64VPSHRDVW512
+               return true
+       case OpShiftRightAndFillUpperFromUint16x8:
+               v.Op = OpAMD64VPSHRDVW128
+               return true
+       case OpShiftRightAndFillUpperFromUint32x16:
+               v.Op = OpAMD64VPSHRDVD512
+               return true
+       case OpShiftRightAndFillUpperFromUint32x4:
+               v.Op = OpAMD64VPSHRDVD128
+               return true
+       case OpShiftRightAndFillUpperFromUint32x8:
+               v.Op = OpAMD64VPSHRDVD256
+               return true
+       case OpShiftRightAndFillUpperFromUint64x2:
+               v.Op = OpAMD64VPSHRDVQ128
+               return true
+       case OpShiftRightAndFillUpperFromUint64x4:
+               v.Op = OpAMD64VPSHRDVQ256
+               return true
+       case OpShiftRightAndFillUpperFromUint64x8:
+               v.Op = OpAMD64VPSHRDVQ512
+               return true
+       case OpShiftRightInt16x16:
+               v.Op = OpAMD64VPSRLVW256
+               return true
+       case OpShiftRightInt16x32:
+               v.Op = OpAMD64VPSRLVW512
+               return true
+       case OpShiftRightInt16x8:
+               v.Op = OpAMD64VPSRLVW128
+               return true
+       case OpShiftRightInt32x16:
+               v.Op = OpAMD64VPSRLVD512
+               return true
+       case OpShiftRightInt32x4:
+               v.Op = OpAMD64VPSRLVD128
+               return true
+       case OpShiftRightInt32x8:
+               v.Op = OpAMD64VPSRLVD256
+               return true
+       case OpShiftRightInt64x2:
+               v.Op = OpAMD64VPSRLVQ128
+               return true
+       case OpShiftRightInt64x4:
+               v.Op = OpAMD64VPSRLVQ256
+               return true
+       case OpShiftRightInt64x8:
+               v.Op = OpAMD64VPSRLVQ512
+               return true
+       case OpShiftRightSignExtendedInt16x16:
+               v.Op = OpAMD64VPSRAVW256
+               return true
+       case OpShiftRightSignExtendedInt16x32:
+               v.Op = OpAMD64VPSRAVW512
+               return true
+       case OpShiftRightSignExtendedInt16x8:
+               v.Op = OpAMD64VPSRAVW128
+               return true
+       case OpShiftRightSignExtendedInt32x16:
+               v.Op = OpAMD64VPSRAVD512
+               return true
+       case OpShiftRightSignExtendedInt32x4:
+               v.Op = OpAMD64VPSRAVD128
+               return true
+       case OpShiftRightSignExtendedInt32x8:
+               v.Op = OpAMD64VPSRAVD256
+               return true
+       case OpShiftRightSignExtendedInt64x2:
+               v.Op = OpAMD64VPSRAVQ128
+               return true
+       case OpShiftRightSignExtendedInt64x4:
+               v.Op = OpAMD64VPSRAVQ256
+               return true
+       case OpShiftRightSignExtendedInt64x8:
+               v.Op = OpAMD64VPSRAVQ512
+               return true
+       case OpShiftRightSignExtendedUint16x16:
+               v.Op = OpAMD64VPSRAVW256
+               return true
+       case OpShiftRightSignExtendedUint16x32:
+               v.Op = OpAMD64VPSRAVW512
+               return true
+       case OpShiftRightSignExtendedUint16x8:
+               v.Op = OpAMD64VPSRAVW128
+               return true
+       case OpShiftRightSignExtendedUint32x16:
+               v.Op = OpAMD64VPSRAVD512
+               return true
+       case OpShiftRightSignExtendedUint32x4:
+               v.Op = OpAMD64VPSRAVD128
+               return true
+       case OpShiftRightSignExtendedUint32x8:
+               v.Op = OpAMD64VPSRAVD256
+               return true
+       case OpShiftRightSignExtendedUint64x2:
+               v.Op = OpAMD64VPSRAVQ128
+               return true
+       case OpShiftRightSignExtendedUint64x4:
+               v.Op = OpAMD64VPSRAVQ256
+               return true
+       case OpShiftRightSignExtendedUint64x8:
+               v.Op = OpAMD64VPSRAVQ512
+               return true
+       case OpShiftRightUint16x16:
+               v.Op = OpAMD64VPSRLVW256
+               return true
+       case OpShiftRightUint16x32:
+               v.Op = OpAMD64VPSRLVW512
+               return true
+       case OpShiftRightUint16x8:
+               v.Op = OpAMD64VPSRLVW128
+               return true
+       case OpShiftRightUint32x16:
+               v.Op = OpAMD64VPSRLVD512
+               return true
+       case OpShiftRightUint32x4:
+               v.Op = OpAMD64VPSRLVD128
+               return true
+       case OpShiftRightUint32x8:
+               v.Op = OpAMD64VPSRLVD256
+               return true
+       case OpShiftRightUint64x2:
+               v.Op = OpAMD64VPSRLVQ128
+               return true
+       case OpShiftRightUint64x4:
+               v.Op = OpAMD64VPSRLVQ256
+               return true
+       case OpShiftRightUint64x8:
+               v.Op = OpAMD64VPSRLVQ512
+               return true
        case OpSignExt16to32:
                v.Op = OpAMD64MOVWQSX
                return true
@@ -43973,885 +44918,4431 @@ func rewriteValueAMD64_OpMaskedPopCountUint8x64(v *Value) bool {
                return true
        }
 }
-func rewriteValueAMD64_OpMaskedRoundSuppressExceptionWithPrecisionFloat32x16(v *Value) bool {
+func rewriteValueAMD64_OpMaskedRotateAllLeftInt32x16(v *Value) bool {
        v_1 := v.Args[1]
        v_0 := v.Args[0]
        b := v.Block
-       // match: (MaskedRoundSuppressExceptionWithPrecisionFloat32x16 [a] x mask)
-       // result: (VRNDSCALEPSMasked512 [a+8] x (VPMOVVec32x16ToM <types.TypeMask> mask))
+       // match: (MaskedRotateAllLeftInt32x16 [a] x mask)
+       // result: (VPROLDMasked512 [a] x (VPMOVVec32x16ToM <types.TypeMask> mask))
        for {
                a := auxIntToInt8(v.AuxInt)
                x := v_0
                mask := v_1
-               v.reset(OpAMD64VRNDSCALEPSMasked512)
-               v.AuxInt = int8ToAuxInt(a + 8)
+               v.reset(OpAMD64VPROLDMasked512)
+               v.AuxInt = int8ToAuxInt(a)
                v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x16ToM, types.TypeMask)
                v0.AddArg(mask)
                v.AddArg2(x, v0)
                return true
        }
 }
-func rewriteValueAMD64_OpMaskedRoundSuppressExceptionWithPrecisionFloat32x4(v *Value) bool {
+func rewriteValueAMD64_OpMaskedRotateAllLeftInt32x4(v *Value) bool {
        v_1 := v.Args[1]
        v_0 := v.Args[0]
        b := v.Block
-       // match: (MaskedRoundSuppressExceptionWithPrecisionFloat32x4 [a] x mask)
-       // result: (VRNDSCALEPSMasked128 [a+8] x (VPMOVVec32x4ToM <types.TypeMask> mask))
+       // match: (MaskedRotateAllLeftInt32x4 [a] x mask)
+       // result: (VPROLDMasked128 [a] x (VPMOVVec32x4ToM <types.TypeMask> mask))
        for {
                a := auxIntToInt8(v.AuxInt)
                x := v_0
                mask := v_1
-               v.reset(OpAMD64VRNDSCALEPSMasked128)
-               v.AuxInt = int8ToAuxInt(a + 8)
+               v.reset(OpAMD64VPROLDMasked128)
+               v.AuxInt = int8ToAuxInt(a)
                v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x4ToM, types.TypeMask)
                v0.AddArg(mask)
                v.AddArg2(x, v0)
                return true
        }
 }
-func rewriteValueAMD64_OpMaskedRoundSuppressExceptionWithPrecisionFloat32x8(v *Value) bool {
+func rewriteValueAMD64_OpMaskedRotateAllLeftInt32x8(v *Value) bool {
        v_1 := v.Args[1]
        v_0 := v.Args[0]
        b := v.Block
-       // match: (MaskedRoundSuppressExceptionWithPrecisionFloat32x8 [a] x mask)
-       // result: (VRNDSCALEPSMasked256 [a+8] x (VPMOVVec32x8ToM <types.TypeMask> mask))
+       // match: (MaskedRotateAllLeftInt32x8 [a] x mask)
+       // result: (VPROLDMasked256 [a] x (VPMOVVec32x8ToM <types.TypeMask> mask))
        for {
                a := auxIntToInt8(v.AuxInt)
                x := v_0
                mask := v_1
-               v.reset(OpAMD64VRNDSCALEPSMasked256)
-               v.AuxInt = int8ToAuxInt(a + 8)
+               v.reset(OpAMD64VPROLDMasked256)
+               v.AuxInt = int8ToAuxInt(a)
                v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x8ToM, types.TypeMask)
                v0.AddArg(mask)
                v.AddArg2(x, v0)
                return true
        }
 }
-func rewriteValueAMD64_OpMaskedRoundSuppressExceptionWithPrecisionFloat64x2(v *Value) bool {
+func rewriteValueAMD64_OpMaskedRotateAllLeftInt64x2(v *Value) bool {
        v_1 := v.Args[1]
        v_0 := v.Args[0]
        b := v.Block
-       // match: (MaskedRoundSuppressExceptionWithPrecisionFloat64x2 [a] x mask)
-       // result: (VRNDSCALEPDMasked128 [a+8] x (VPMOVVec64x2ToM <types.TypeMask> mask))
+       // match: (MaskedRotateAllLeftInt64x2 [a] x mask)
+       // result: (VPROLQMasked128 [a] x (VPMOVVec64x2ToM <types.TypeMask> mask))
        for {
                a := auxIntToInt8(v.AuxInt)
                x := v_0
                mask := v_1
-               v.reset(OpAMD64VRNDSCALEPDMasked128)
-               v.AuxInt = int8ToAuxInt(a + 8)
+               v.reset(OpAMD64VPROLQMasked128)
+               v.AuxInt = int8ToAuxInt(a)
                v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x2ToM, types.TypeMask)
                v0.AddArg(mask)
                v.AddArg2(x, v0)
                return true
        }
 }
-func rewriteValueAMD64_OpMaskedRoundSuppressExceptionWithPrecisionFloat64x4(v *Value) bool {
+func rewriteValueAMD64_OpMaskedRotateAllLeftInt64x4(v *Value) bool {
        v_1 := v.Args[1]
        v_0 := v.Args[0]
        b := v.Block
-       // match: (MaskedRoundSuppressExceptionWithPrecisionFloat64x4 [a] x mask)
-       // result: (VRNDSCALEPDMasked256 [a+8] x (VPMOVVec64x4ToM <types.TypeMask> mask))
+       // match: (MaskedRotateAllLeftInt64x4 [a] x mask)
+       // result: (VPROLQMasked256 [a] x (VPMOVVec64x4ToM <types.TypeMask> mask))
        for {
                a := auxIntToInt8(v.AuxInt)
                x := v_0
                mask := v_1
-               v.reset(OpAMD64VRNDSCALEPDMasked256)
-               v.AuxInt = int8ToAuxInt(a + 8)
+               v.reset(OpAMD64VPROLQMasked256)
+               v.AuxInt = int8ToAuxInt(a)
                v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x4ToM, types.TypeMask)
                v0.AddArg(mask)
                v.AddArg2(x, v0)
                return true
        }
 }
-func rewriteValueAMD64_OpMaskedRoundSuppressExceptionWithPrecisionFloat64x8(v *Value) bool {
+func rewriteValueAMD64_OpMaskedRotateAllLeftInt64x8(v *Value) bool {
        v_1 := v.Args[1]
        v_0 := v.Args[0]
        b := v.Block
-       // match: (MaskedRoundSuppressExceptionWithPrecisionFloat64x8 [a] x mask)
-       // result: (VRNDSCALEPDMasked512 [a+8] x (VPMOVVec64x8ToM <types.TypeMask> mask))
+       // match: (MaskedRotateAllLeftInt64x8 [a] x mask)
+       // result: (VPROLQMasked512 [a] x (VPMOVVec64x8ToM <types.TypeMask> mask))
        for {
                a := auxIntToInt8(v.AuxInt)
                x := v_0
                mask := v_1
-               v.reset(OpAMD64VRNDSCALEPDMasked512)
-               v.AuxInt = int8ToAuxInt(a + 8)
+               v.reset(OpAMD64VPROLQMasked512)
+               v.AuxInt = int8ToAuxInt(a)
                v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x8ToM, types.TypeMask)
                v0.AddArg(mask)
                v.AddArg2(x, v0)
                return true
        }
 }
-func rewriteValueAMD64_OpMaskedRoundWithPrecisionFloat32x16(v *Value) bool {
+func rewriteValueAMD64_OpMaskedRotateAllLeftUint32x16(v *Value) bool {
        v_1 := v.Args[1]
        v_0 := v.Args[0]
        b := v.Block
-       // match: (MaskedRoundWithPrecisionFloat32x16 [a] x mask)
-       // result: (VRNDSCALEPSMasked512 [a+0] x (VPMOVVec32x16ToM <types.TypeMask> mask))
+       // match: (MaskedRotateAllLeftUint32x16 [a] x mask)
+       // result: (VPROLDMasked512 [a] x (VPMOVVec32x16ToM <types.TypeMask> mask))
        for {
                a := auxIntToInt8(v.AuxInt)
                x := v_0
                mask := v_1
-               v.reset(OpAMD64VRNDSCALEPSMasked512)
-               v.AuxInt = int8ToAuxInt(a + 0)
+               v.reset(OpAMD64VPROLDMasked512)
+               v.AuxInt = int8ToAuxInt(a)
                v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x16ToM, types.TypeMask)
                v0.AddArg(mask)
                v.AddArg2(x, v0)
                return true
        }
 }
-func rewriteValueAMD64_OpMaskedRoundWithPrecisionFloat32x4(v *Value) bool {
+func rewriteValueAMD64_OpMaskedRotateAllLeftUint32x4(v *Value) bool {
        v_1 := v.Args[1]
        v_0 := v.Args[0]
        b := v.Block
-       // match: (MaskedRoundWithPrecisionFloat32x4 [a] x mask)
-       // result: (VRNDSCALEPSMasked128 [a+0] x (VPMOVVec32x4ToM <types.TypeMask> mask))
+       // match: (MaskedRotateAllLeftUint32x4 [a] x mask)
+       // result: (VPROLDMasked128 [a] x (VPMOVVec32x4ToM <types.TypeMask> mask))
        for {
                a := auxIntToInt8(v.AuxInt)
                x := v_0
                mask := v_1
-               v.reset(OpAMD64VRNDSCALEPSMasked128)
-               v.AuxInt = int8ToAuxInt(a + 0)
+               v.reset(OpAMD64VPROLDMasked128)
+               v.AuxInt = int8ToAuxInt(a)
                v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x4ToM, types.TypeMask)
                v0.AddArg(mask)
                v.AddArg2(x, v0)
                return true
        }
 }
-func rewriteValueAMD64_OpMaskedRoundWithPrecisionFloat32x8(v *Value) bool {
+func rewriteValueAMD64_OpMaskedRotateAllLeftUint32x8(v *Value) bool {
        v_1 := v.Args[1]
        v_0 := v.Args[0]
        b := v.Block
-       // match: (MaskedRoundWithPrecisionFloat32x8 [a] x mask)
-       // result: (VRNDSCALEPSMasked256 [a+0] x (VPMOVVec32x8ToM <types.TypeMask> mask))
+       // match: (MaskedRotateAllLeftUint32x8 [a] x mask)
+       // result: (VPROLDMasked256 [a] x (VPMOVVec32x8ToM <types.TypeMask> mask))
        for {
                a := auxIntToInt8(v.AuxInt)
                x := v_0
                mask := v_1
-               v.reset(OpAMD64VRNDSCALEPSMasked256)
-               v.AuxInt = int8ToAuxInt(a + 0)
+               v.reset(OpAMD64VPROLDMasked256)
+               v.AuxInt = int8ToAuxInt(a)
                v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x8ToM, types.TypeMask)
                v0.AddArg(mask)
                v.AddArg2(x, v0)
                return true
        }
 }
-func rewriteValueAMD64_OpMaskedRoundWithPrecisionFloat64x2(v *Value) bool {
+func rewriteValueAMD64_OpMaskedRotateAllLeftUint64x2(v *Value) bool {
        v_1 := v.Args[1]
        v_0 := v.Args[0]
        b := v.Block
-       // match: (MaskedRoundWithPrecisionFloat64x2 [a] x mask)
-       // result: (VRNDSCALEPDMasked128 [a+0] x (VPMOVVec64x2ToM <types.TypeMask> mask))
+       // match: (MaskedRotateAllLeftUint64x2 [a] x mask)
+       // result: (VPROLQMasked128 [a] x (VPMOVVec64x2ToM <types.TypeMask> mask))
        for {
                a := auxIntToInt8(v.AuxInt)
                x := v_0
                mask := v_1
-               v.reset(OpAMD64VRNDSCALEPDMasked128)
-               v.AuxInt = int8ToAuxInt(a + 0)
+               v.reset(OpAMD64VPROLQMasked128)
+               v.AuxInt = int8ToAuxInt(a)
                v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x2ToM, types.TypeMask)
                v0.AddArg(mask)
                v.AddArg2(x, v0)
                return true
        }
 }
-func rewriteValueAMD64_OpMaskedRoundWithPrecisionFloat64x4(v *Value) bool {
+func rewriteValueAMD64_OpMaskedRotateAllLeftUint64x4(v *Value) bool {
        v_1 := v.Args[1]
        v_0 := v.Args[0]
        b := v.Block
-       // match: (MaskedRoundWithPrecisionFloat64x4 [a] x mask)
-       // result: (VRNDSCALEPDMasked256 [a+0] x (VPMOVVec64x4ToM <types.TypeMask> mask))
+       // match: (MaskedRotateAllLeftUint64x4 [a] x mask)
+       // result: (VPROLQMasked256 [a] x (VPMOVVec64x4ToM <types.TypeMask> mask))
        for {
                a := auxIntToInt8(v.AuxInt)
                x := v_0
                mask := v_1
-               v.reset(OpAMD64VRNDSCALEPDMasked256)
-               v.AuxInt = int8ToAuxInt(a + 0)
+               v.reset(OpAMD64VPROLQMasked256)
+               v.AuxInt = int8ToAuxInt(a)
                v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x4ToM, types.TypeMask)
                v0.AddArg(mask)
                v.AddArg2(x, v0)
                return true
        }
 }
-func rewriteValueAMD64_OpMaskedRoundWithPrecisionFloat64x8(v *Value) bool {
+func rewriteValueAMD64_OpMaskedRotateAllLeftUint64x8(v *Value) bool {
        v_1 := v.Args[1]
        v_0 := v.Args[0]
        b := v.Block
-       // match: (MaskedRoundWithPrecisionFloat64x8 [a] x mask)
-       // result: (VRNDSCALEPDMasked512 [a+0] x (VPMOVVec64x8ToM <types.TypeMask> mask))
+       // match: (MaskedRotateAllLeftUint64x8 [a] x mask)
+       // result: (VPROLQMasked512 [a] x (VPMOVVec64x8ToM <types.TypeMask> mask))
        for {
                a := auxIntToInt8(v.AuxInt)
                x := v_0
                mask := v_1
-               v.reset(OpAMD64VRNDSCALEPDMasked512)
-               v.AuxInt = int8ToAuxInt(a + 0)
+               v.reset(OpAMD64VPROLQMasked512)
+               v.AuxInt = int8ToAuxInt(a)
                v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x8ToM, types.TypeMask)
                v0.AddArg(mask)
                v.AddArg2(x, v0)
                return true
        }
 }
-func rewriteValueAMD64_OpMaskedSaturatedAddInt16x16(v *Value) bool {
-       v_2 := v.Args[2]
+func rewriteValueAMD64_OpMaskedRotateAllRightInt32x16(v *Value) bool {
        v_1 := v.Args[1]
        v_0 := v.Args[0]
        b := v.Block
-       // match: (MaskedSaturatedAddInt16x16 x y mask)
-       // result: (VPADDSWMasked256 x y (VPMOVVec16x16ToM <types.TypeMask> mask))
+       // match: (MaskedRotateAllRightInt32x16 [a] x mask)
+       // result: (VPRORDMasked512 [a] x (VPMOVVec32x16ToM <types.TypeMask> mask))
        for {
+               a := auxIntToInt8(v.AuxInt)
                x := v_0
-               y := v_1
-               mask := v_2
-               v.reset(OpAMD64VPADDSWMasked256)
-               v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x16ToM, types.TypeMask)
+               mask := v_1
+               v.reset(OpAMD64VPRORDMasked512)
+               v.AuxInt = int8ToAuxInt(a)
+               v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x16ToM, types.TypeMask)
                v0.AddArg(mask)
-               v.AddArg3(x, y, v0)
+               v.AddArg2(x, v0)
                return true
        }
 }
-func rewriteValueAMD64_OpMaskedSaturatedAddInt16x32(v *Value) bool {
-       v_2 := v.Args[2]
+func rewriteValueAMD64_OpMaskedRotateAllRightInt32x4(v *Value) bool {
        v_1 := v.Args[1]
        v_0 := v.Args[0]
        b := v.Block
-       // match: (MaskedSaturatedAddInt16x32 x y mask)
-       // result: (VPADDSWMasked512 x y (VPMOVVec16x32ToM <types.TypeMask> mask))
+       // match: (MaskedRotateAllRightInt32x4 [a] x mask)
+       // result: (VPRORDMasked128 [a] x (VPMOVVec32x4ToM <types.TypeMask> mask))
        for {
+               a := auxIntToInt8(v.AuxInt)
                x := v_0
-               y := v_1
-               mask := v_2
-               v.reset(OpAMD64VPADDSWMasked512)
-               v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x32ToM, types.TypeMask)
+               mask := v_1
+               v.reset(OpAMD64VPRORDMasked128)
+               v.AuxInt = int8ToAuxInt(a)
+               v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x4ToM, types.TypeMask)
                v0.AddArg(mask)
-               v.AddArg3(x, y, v0)
+               v.AddArg2(x, v0)
                return true
        }
 }
-func rewriteValueAMD64_OpMaskedSaturatedAddInt16x8(v *Value) bool {
-       v_2 := v.Args[2]
+func rewriteValueAMD64_OpMaskedRotateAllRightInt32x8(v *Value) bool {
        v_1 := v.Args[1]
        v_0 := v.Args[0]
        b := v.Block
-       // match: (MaskedSaturatedAddInt16x8 x y mask)
-       // result: (VPADDSWMasked128 x y (VPMOVVec16x8ToM <types.TypeMask> mask))
+       // match: (MaskedRotateAllRightInt32x8 [a] x mask)
+       // result: (VPRORDMasked256 [a] x (VPMOVVec32x8ToM <types.TypeMask> mask))
        for {
+               a := auxIntToInt8(v.AuxInt)
                x := v_0
-               y := v_1
-               mask := v_2
-               v.reset(OpAMD64VPADDSWMasked128)
-               v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x8ToM, types.TypeMask)
+               mask := v_1
+               v.reset(OpAMD64VPRORDMasked256)
+               v.AuxInt = int8ToAuxInt(a)
+               v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x8ToM, types.TypeMask)
                v0.AddArg(mask)
-               v.AddArg3(x, y, v0)
+               v.AddArg2(x, v0)
                return true
        }
 }
-func rewriteValueAMD64_OpMaskedSaturatedAddInt8x16(v *Value) bool {
-       v_2 := v.Args[2]
+func rewriteValueAMD64_OpMaskedRotateAllRightInt64x2(v *Value) bool {
        v_1 := v.Args[1]
        v_0 := v.Args[0]
        b := v.Block
-       // match: (MaskedSaturatedAddInt8x16 x y mask)
-       // result: (VPADDSBMasked128 x y (VPMOVVec8x16ToM <types.TypeMask> mask))
+       // match: (MaskedRotateAllRightInt64x2 [a] x mask)
+       // result: (VPRORQMasked128 [a] x (VPMOVVec64x2ToM <types.TypeMask> mask))
        for {
+               a := auxIntToInt8(v.AuxInt)
                x := v_0
-               y := v_1
-               mask := v_2
-               v.reset(OpAMD64VPADDSBMasked128)
-               v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec8x16ToM, types.TypeMask)
+               mask := v_1
+               v.reset(OpAMD64VPRORQMasked128)
+               v.AuxInt = int8ToAuxInt(a)
+               v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x2ToM, types.TypeMask)
                v0.AddArg(mask)
-               v.AddArg3(x, y, v0)
+               v.AddArg2(x, v0)
                return true
        }
 }
-func rewriteValueAMD64_OpMaskedSaturatedAddInt8x32(v *Value) bool {
-       v_2 := v.Args[2]
+func rewriteValueAMD64_OpMaskedRotateAllRightInt64x4(v *Value) bool {
        v_1 := v.Args[1]
        v_0 := v.Args[0]
        b := v.Block
-       // match: (MaskedSaturatedAddInt8x32 x y mask)
-       // result: (VPADDSBMasked256 x y (VPMOVVec8x32ToM <types.TypeMask> mask))
+       // match: (MaskedRotateAllRightInt64x4 [a] x mask)
+       // result: (VPRORQMasked256 [a] x (VPMOVVec64x4ToM <types.TypeMask> mask))
        for {
+               a := auxIntToInt8(v.AuxInt)
                x := v_0
-               y := v_1
-               mask := v_2
-               v.reset(OpAMD64VPADDSBMasked256)
-               v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec8x32ToM, types.TypeMask)
+               mask := v_1
+               v.reset(OpAMD64VPRORQMasked256)
+               v.AuxInt = int8ToAuxInt(a)
+               v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x4ToM, types.TypeMask)
                v0.AddArg(mask)
-               v.AddArg3(x, y, v0)
+               v.AddArg2(x, v0)
                return true
        }
 }
-func rewriteValueAMD64_OpMaskedSaturatedAddInt8x64(v *Value) bool {
-       v_2 := v.Args[2]
+func rewriteValueAMD64_OpMaskedRotateAllRightInt64x8(v *Value) bool {
        v_1 := v.Args[1]
        v_0 := v.Args[0]
        b := v.Block
-       // match: (MaskedSaturatedAddInt8x64 x y mask)
-       // result: (VPADDSBMasked512 x y (VPMOVVec8x64ToM <types.TypeMask> mask))
+       // match: (MaskedRotateAllRightInt64x8 [a] x mask)
+       // result: (VPRORQMasked512 [a] x (VPMOVVec64x8ToM <types.TypeMask> mask))
        for {
+               a := auxIntToInt8(v.AuxInt)
                x := v_0
-               y := v_1
-               mask := v_2
-               v.reset(OpAMD64VPADDSBMasked512)
-               v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec8x64ToM, types.TypeMask)
+               mask := v_1
+               v.reset(OpAMD64VPRORQMasked512)
+               v.AuxInt = int8ToAuxInt(a)
+               v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x8ToM, types.TypeMask)
                v0.AddArg(mask)
-               v.AddArg3(x, y, v0)
+               v.AddArg2(x, v0)
                return true
        }
 }
-func rewriteValueAMD64_OpMaskedSaturatedAddUint16x16(v *Value) bool {
-       v_2 := v.Args[2]
+func rewriteValueAMD64_OpMaskedRotateAllRightUint32x16(v *Value) bool {
        v_1 := v.Args[1]
        v_0 := v.Args[0]
        b := v.Block
-       // match: (MaskedSaturatedAddUint16x16 x y mask)
-       // result: (VPADDSWMasked256 x y (VPMOVVec16x16ToM <types.TypeMask> mask))
+       // match: (MaskedRotateAllRightUint32x16 [a] x mask)
+       // result: (VPRORDMasked512 [a] x (VPMOVVec32x16ToM <types.TypeMask> mask))
        for {
+               a := auxIntToInt8(v.AuxInt)
                x := v_0
-               y := v_1
-               mask := v_2
-               v.reset(OpAMD64VPADDSWMasked256)
-               v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x16ToM, types.TypeMask)
+               mask := v_1
+               v.reset(OpAMD64VPRORDMasked512)
+               v.AuxInt = int8ToAuxInt(a)
+               v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x16ToM, types.TypeMask)
                v0.AddArg(mask)
-               v.AddArg3(x, y, v0)
+               v.AddArg2(x, v0)
                return true
        }
 }
-func rewriteValueAMD64_OpMaskedSaturatedAddUint16x32(v *Value) bool {
-       v_2 := v.Args[2]
+func rewriteValueAMD64_OpMaskedRotateAllRightUint32x4(v *Value) bool {
        v_1 := v.Args[1]
        v_0 := v.Args[0]
        b := v.Block
-       // match: (MaskedSaturatedAddUint16x32 x y mask)
-       // result: (VPADDSWMasked512 x y (VPMOVVec16x32ToM <types.TypeMask> mask))
+       // match: (MaskedRotateAllRightUint32x4 [a] x mask)
+       // result: (VPRORDMasked128 [a] x (VPMOVVec32x4ToM <types.TypeMask> mask))
        for {
+               a := auxIntToInt8(v.AuxInt)
                x := v_0
-               y := v_1
-               mask := v_2
-               v.reset(OpAMD64VPADDSWMasked512)
-               v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x32ToM, types.TypeMask)
+               mask := v_1
+               v.reset(OpAMD64VPRORDMasked128)
+               v.AuxInt = int8ToAuxInt(a)
+               v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x4ToM, types.TypeMask)
                v0.AddArg(mask)
-               v.AddArg3(x, y, v0)
+               v.AddArg2(x, v0)
                return true
        }
 }
-func rewriteValueAMD64_OpMaskedSaturatedAddUint16x8(v *Value) bool {
-       v_2 := v.Args[2]
+func rewriteValueAMD64_OpMaskedRotateAllRightUint32x8(v *Value) bool {
        v_1 := v.Args[1]
        v_0 := v.Args[0]
        b := v.Block
-       // match: (MaskedSaturatedAddUint16x8 x y mask)
-       // result: (VPADDSWMasked128 x y (VPMOVVec16x8ToM <types.TypeMask> mask))
+       // match: (MaskedRotateAllRightUint32x8 [a] x mask)
+       // result: (VPRORDMasked256 [a] x (VPMOVVec32x8ToM <types.TypeMask> mask))
        for {
+               a := auxIntToInt8(v.AuxInt)
                x := v_0
-               y := v_1
-               mask := v_2
-               v.reset(OpAMD64VPADDSWMasked128)
-               v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x8ToM, types.TypeMask)
+               mask := v_1
+               v.reset(OpAMD64VPRORDMasked256)
+               v.AuxInt = int8ToAuxInt(a)
+               v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x8ToM, types.TypeMask)
                v0.AddArg(mask)
-               v.AddArg3(x, y, v0)
+               v.AddArg2(x, v0)
                return true
        }
 }
-func rewriteValueAMD64_OpMaskedSaturatedAddUint8x16(v *Value) bool {
-       v_2 := v.Args[2]
+func rewriteValueAMD64_OpMaskedRotateAllRightUint64x2(v *Value) bool {
        v_1 := v.Args[1]
        v_0 := v.Args[0]
        b := v.Block
-       // match: (MaskedSaturatedAddUint8x16 x y mask)
-       // result: (VPADDSBMasked128 x y (VPMOVVec8x16ToM <types.TypeMask> mask))
+       // match: (MaskedRotateAllRightUint64x2 [a] x mask)
+       // result: (VPRORQMasked128 [a] x (VPMOVVec64x2ToM <types.TypeMask> mask))
        for {
+               a := auxIntToInt8(v.AuxInt)
                x := v_0
-               y := v_1
-               mask := v_2
-               v.reset(OpAMD64VPADDSBMasked128)
-               v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec8x16ToM, types.TypeMask)
+               mask := v_1
+               v.reset(OpAMD64VPRORQMasked128)
+               v.AuxInt = int8ToAuxInt(a)
+               v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x2ToM, types.TypeMask)
                v0.AddArg(mask)
-               v.AddArg3(x, y, v0)
+               v.AddArg2(x, v0)
                return true
        }
 }
-func rewriteValueAMD64_OpMaskedSaturatedAddUint8x32(v *Value) bool {
-       v_2 := v.Args[2]
+func rewriteValueAMD64_OpMaskedRotateAllRightUint64x4(v *Value) bool {
        v_1 := v.Args[1]
        v_0 := v.Args[0]
        b := v.Block
-       // match: (MaskedSaturatedAddUint8x32 x y mask)
-       // result: (VPADDSBMasked256 x y (VPMOVVec8x32ToM <types.TypeMask> mask))
+       // match: (MaskedRotateAllRightUint64x4 [a] x mask)
+       // result: (VPRORQMasked256 [a] x (VPMOVVec64x4ToM <types.TypeMask> mask))
        for {
+               a := auxIntToInt8(v.AuxInt)
                x := v_0
-               y := v_1
-               mask := v_2
-               v.reset(OpAMD64VPADDSBMasked256)
-               v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec8x32ToM, types.TypeMask)
+               mask := v_1
+               v.reset(OpAMD64VPRORQMasked256)
+               v.AuxInt = int8ToAuxInt(a)
+               v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x4ToM, types.TypeMask)
                v0.AddArg(mask)
-               v.AddArg3(x, y, v0)
+               v.AddArg2(x, v0)
                return true
        }
 }
-func rewriteValueAMD64_OpMaskedSaturatedAddUint8x64(v *Value) bool {
-       v_2 := v.Args[2]
+func rewriteValueAMD64_OpMaskedRotateAllRightUint64x8(v *Value) bool {
        v_1 := v.Args[1]
        v_0 := v.Args[0]
        b := v.Block
-       // match: (MaskedSaturatedAddUint8x64 x y mask)
-       // result: (VPADDSBMasked512 x y (VPMOVVec8x64ToM <types.TypeMask> mask))
+       // match: (MaskedRotateAllRightUint64x8 [a] x mask)
+       // result: (VPRORQMasked512 [a] x (VPMOVVec64x8ToM <types.TypeMask> mask))
        for {
+               a := auxIntToInt8(v.AuxInt)
                x := v_0
-               y := v_1
-               mask := v_2
-               v.reset(OpAMD64VPADDSBMasked512)
-               v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec8x64ToM, types.TypeMask)
+               mask := v_1
+               v.reset(OpAMD64VPRORQMasked512)
+               v.AuxInt = int8ToAuxInt(a)
+               v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x8ToM, types.TypeMask)
                v0.AddArg(mask)
-               v.AddArg3(x, y, v0)
+               v.AddArg2(x, v0)
                return true
        }
 }
-func rewriteValueAMD64_OpMaskedSaturatedPairDotProdAccumulateInt32x16(v *Value) bool {
-       v_3 := v.Args[3]
+func rewriteValueAMD64_OpMaskedRotateLeftInt32x16(v *Value) bool {
        v_2 := v.Args[2]
        v_1 := v.Args[1]
        v_0 := v.Args[0]
        b := v.Block
-       // match: (MaskedSaturatedPairDotProdAccumulateInt32x16 x y z mask)
-       // result: (VPDPWSSDSMasked512 x y z (VPMOVVec32x16ToM <types.TypeMask> mask))
+       // match: (MaskedRotateLeftInt32x16 x y mask)
+       // result: (VPROLVDMasked512 x y (VPMOVVec32x16ToM <types.TypeMask> mask))
        for {
                x := v_0
                y := v_1
-               z := v_2
-               mask := v_3
-               v.reset(OpAMD64VPDPWSSDSMasked512)
+               mask := v_2
+               v.reset(OpAMD64VPROLVDMasked512)
                v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x16ToM, types.TypeMask)
                v0.AddArg(mask)
-               v.AddArg4(x, y, z, v0)
+               v.AddArg3(x, y, v0)
                return true
        }
 }
-func rewriteValueAMD64_OpMaskedSaturatedPairDotProdAccumulateInt32x4(v *Value) bool {
-       v_3 := v.Args[3]
+func rewriteValueAMD64_OpMaskedRotateLeftInt32x4(v *Value) bool {
        v_2 := v.Args[2]
        v_1 := v.Args[1]
        v_0 := v.Args[0]
        b := v.Block
-       // match: (MaskedSaturatedPairDotProdAccumulateInt32x4 x y z mask)
-       // result: (VPDPWSSDSMasked128 x y z (VPMOVVec32x4ToM <types.TypeMask> mask))
+       // match: (MaskedRotateLeftInt32x4 x y mask)
+       // result: (VPROLVDMasked128 x y (VPMOVVec32x4ToM <types.TypeMask> mask))
        for {
                x := v_0
                y := v_1
-               z := v_2
-               mask := v_3
-               v.reset(OpAMD64VPDPWSSDSMasked128)
+               mask := v_2
+               v.reset(OpAMD64VPROLVDMasked128)
                v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x4ToM, types.TypeMask)
                v0.AddArg(mask)
-               v.AddArg4(x, y, z, v0)
+               v.AddArg3(x, y, v0)
                return true
        }
 }
-func rewriteValueAMD64_OpMaskedSaturatedPairDotProdAccumulateInt32x8(v *Value) bool {
-       v_3 := v.Args[3]
+func rewriteValueAMD64_OpMaskedRotateLeftInt32x8(v *Value) bool {
        v_2 := v.Args[2]
        v_1 := v.Args[1]
        v_0 := v.Args[0]
        b := v.Block
-       // match: (MaskedSaturatedPairDotProdAccumulateInt32x8 x y z mask)
-       // result: (VPDPWSSDSMasked256 x y z (VPMOVVec32x8ToM <types.TypeMask> mask))
+       // match: (MaskedRotateLeftInt32x8 x y mask)
+       // result: (VPROLVDMasked256 x y (VPMOVVec32x8ToM <types.TypeMask> mask))
        for {
                x := v_0
                y := v_1
-               z := v_2
-               mask := v_3
-               v.reset(OpAMD64VPDPWSSDSMasked256)
+               mask := v_2
+               v.reset(OpAMD64VPROLVDMasked256)
                v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x8ToM, types.TypeMask)
                v0.AddArg(mask)
-               v.AddArg4(x, y, z, v0)
+               v.AddArg3(x, y, v0)
                return true
        }
 }
-func rewriteValueAMD64_OpMaskedSaturatedSubInt16x16(v *Value) bool {
+func rewriteValueAMD64_OpMaskedRotateLeftInt64x2(v *Value) bool {
        v_2 := v.Args[2]
        v_1 := v.Args[1]
        v_0 := v.Args[0]
        b := v.Block
-       // match: (MaskedSaturatedSubInt16x16 x y mask)
-       // result: (VPSUBSWMasked256 x y (VPMOVVec16x16ToM <types.TypeMask> mask))
+       // match: (MaskedRotateLeftInt64x2 x y mask)
+       // result: (VPROLVQMasked128 x y (VPMOVVec64x2ToM <types.TypeMask> mask))
        for {
                x := v_0
                y := v_1
                mask := v_2
-               v.reset(OpAMD64VPSUBSWMasked256)
-               v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x16ToM, types.TypeMask)
+               v.reset(OpAMD64VPROLVQMasked128)
+               v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x2ToM, types.TypeMask)
                v0.AddArg(mask)
                v.AddArg3(x, y, v0)
                return true
        }
 }
-func rewriteValueAMD64_OpMaskedSaturatedSubInt16x32(v *Value) bool {
+func rewriteValueAMD64_OpMaskedRotateLeftInt64x4(v *Value) bool {
        v_2 := v.Args[2]
        v_1 := v.Args[1]
        v_0 := v.Args[0]
        b := v.Block
-       // match: (MaskedSaturatedSubInt16x32 x y mask)
-       // result: (VPSUBSWMasked512 x y (VPMOVVec16x32ToM <types.TypeMask> mask))
+       // match: (MaskedRotateLeftInt64x4 x y mask)
+       // result: (VPROLVQMasked256 x y (VPMOVVec64x4ToM <types.TypeMask> mask))
        for {
                x := v_0
                y := v_1
                mask := v_2
-               v.reset(OpAMD64VPSUBSWMasked512)
-               v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x32ToM, types.TypeMask)
+               v.reset(OpAMD64VPROLVQMasked256)
+               v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x4ToM, types.TypeMask)
                v0.AddArg(mask)
                v.AddArg3(x, y, v0)
                return true
        }
 }
-func rewriteValueAMD64_OpMaskedSaturatedSubInt16x8(v *Value) bool {
+func rewriteValueAMD64_OpMaskedRotateLeftInt64x8(v *Value) bool {
        v_2 := v.Args[2]
        v_1 := v.Args[1]
        v_0 := v.Args[0]
        b := v.Block
-       // match: (MaskedSaturatedSubInt16x8 x y mask)
-       // result: (VPSUBSWMasked128 x y (VPMOVVec16x8ToM <types.TypeMask> mask))
+       // match: (MaskedRotateLeftInt64x8 x y mask)
+       // result: (VPROLVQMasked512 x y (VPMOVVec64x8ToM <types.TypeMask> mask))
        for {
                x := v_0
                y := v_1
                mask := v_2
-               v.reset(OpAMD64VPSUBSWMasked128)
-               v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x8ToM, types.TypeMask)
+               v.reset(OpAMD64VPROLVQMasked512)
+               v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x8ToM, types.TypeMask)
                v0.AddArg(mask)
                v.AddArg3(x, y, v0)
                return true
        }
 }
-func rewriteValueAMD64_OpMaskedSaturatedSubInt8x16(v *Value) bool {
+func rewriteValueAMD64_OpMaskedRotateLeftUint32x16(v *Value) bool {
        v_2 := v.Args[2]
        v_1 := v.Args[1]
        v_0 := v.Args[0]
        b := v.Block
-       // match: (MaskedSaturatedSubInt8x16 x y mask)
-       // result: (VPSUBSBMasked128 x y (VPMOVVec8x16ToM <types.TypeMask> mask))
+       // match: (MaskedRotateLeftUint32x16 x y mask)
+       // result: (VPROLVDMasked512 x y (VPMOVVec32x16ToM <types.TypeMask> mask))
        for {
                x := v_0
                y := v_1
                mask := v_2
-               v.reset(OpAMD64VPSUBSBMasked128)
-               v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec8x16ToM, types.TypeMask)
+               v.reset(OpAMD64VPROLVDMasked512)
+               v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x16ToM, types.TypeMask)
                v0.AddArg(mask)
                v.AddArg3(x, y, v0)
                return true
        }
 }
-func rewriteValueAMD64_OpMaskedSaturatedSubInt8x32(v *Value) bool {
+func rewriteValueAMD64_OpMaskedRotateLeftUint32x4(v *Value) bool {
        v_2 := v.Args[2]
        v_1 := v.Args[1]
        v_0 := v.Args[0]
        b := v.Block
-       // match: (MaskedSaturatedSubInt8x32 x y mask)
-       // result: (VPSUBSBMasked256 x y (VPMOVVec8x32ToM <types.TypeMask> mask))
+       // match: (MaskedRotateLeftUint32x4 x y mask)
+       // result: (VPROLVDMasked128 x y (VPMOVVec32x4ToM <types.TypeMask> mask))
        for {
                x := v_0
                y := v_1
                mask := v_2
-               v.reset(OpAMD64VPSUBSBMasked256)
-               v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec8x32ToM, types.TypeMask)
+               v.reset(OpAMD64VPROLVDMasked128)
+               v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x4ToM, types.TypeMask)
                v0.AddArg(mask)
                v.AddArg3(x, y, v0)
                return true
        }
 }
-func rewriteValueAMD64_OpMaskedSaturatedSubInt8x64(v *Value) bool {
+func rewriteValueAMD64_OpMaskedRotateLeftUint32x8(v *Value) bool {
        v_2 := v.Args[2]
        v_1 := v.Args[1]
        v_0 := v.Args[0]
        b := v.Block
-       // match: (MaskedSaturatedSubInt8x64 x y mask)
-       // result: (VPSUBSBMasked512 x y (VPMOVVec8x64ToM <types.TypeMask> mask))
+       // match: (MaskedRotateLeftUint32x8 x y mask)
+       // result: (VPROLVDMasked256 x y (VPMOVVec32x8ToM <types.TypeMask> mask))
        for {
                x := v_0
                y := v_1
                mask := v_2
-               v.reset(OpAMD64VPSUBSBMasked512)
-               v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec8x64ToM, types.TypeMask)
+               v.reset(OpAMD64VPROLVDMasked256)
+               v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x8ToM, types.TypeMask)
                v0.AddArg(mask)
                v.AddArg3(x, y, v0)
                return true
        }
 }
-func rewriteValueAMD64_OpMaskedSaturatedSubUint16x16(v *Value) bool {
+func rewriteValueAMD64_OpMaskedRotateLeftUint64x2(v *Value) bool {
        v_2 := v.Args[2]
        v_1 := v.Args[1]
        v_0 := v.Args[0]
        b := v.Block
-       // match: (MaskedSaturatedSubUint16x16 x y mask)
-       // result: (VPSUBSWMasked256 x y (VPMOVVec16x16ToM <types.TypeMask> mask))
+       // match: (MaskedRotateLeftUint64x2 x y mask)
+       // result: (VPROLVQMasked128 x y (VPMOVVec64x2ToM <types.TypeMask> mask))
        for {
                x := v_0
                y := v_1
                mask := v_2
-               v.reset(OpAMD64VPSUBSWMasked256)
-               v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x16ToM, types.TypeMask)
+               v.reset(OpAMD64VPROLVQMasked128)
+               v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x2ToM, types.TypeMask)
                v0.AddArg(mask)
                v.AddArg3(x, y, v0)
                return true
        }
 }
-func rewriteValueAMD64_OpMaskedSaturatedSubUint16x32(v *Value) bool {
+func rewriteValueAMD64_OpMaskedRotateLeftUint64x4(v *Value) bool {
        v_2 := v.Args[2]
        v_1 := v.Args[1]
        v_0 := v.Args[0]
        b := v.Block
-       // match: (MaskedSaturatedSubUint16x32 x y mask)
-       // result: (VPSUBSWMasked512 x y (VPMOVVec16x32ToM <types.TypeMask> mask))
+       // match: (MaskedRotateLeftUint64x4 x y mask)
+       // result: (VPROLVQMasked256 x y (VPMOVVec64x4ToM <types.TypeMask> mask))
        for {
                x := v_0
                y := v_1
                mask := v_2
-               v.reset(OpAMD64VPSUBSWMasked512)
-               v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x32ToM, types.TypeMask)
+               v.reset(OpAMD64VPROLVQMasked256)
+               v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x4ToM, types.TypeMask)
                v0.AddArg(mask)
                v.AddArg3(x, y, v0)
                return true
        }
 }
-func rewriteValueAMD64_OpMaskedSaturatedSubUint16x8(v *Value) bool {
+func rewriteValueAMD64_OpMaskedRotateLeftUint64x8(v *Value) bool {
        v_2 := v.Args[2]
        v_1 := v.Args[1]
        v_0 := v.Args[0]
        b := v.Block
-       // match: (MaskedSaturatedSubUint16x8 x y mask)
-       // result: (VPSUBSWMasked128 x y (VPMOVVec16x8ToM <types.TypeMask> mask))
+       // match: (MaskedRotateLeftUint64x8 x y mask)
+       // result: (VPROLVQMasked512 x y (VPMOVVec64x8ToM <types.TypeMask> mask))
        for {
                x := v_0
                y := v_1
                mask := v_2
-               v.reset(OpAMD64VPSUBSWMasked128)
-               v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x8ToM, types.TypeMask)
+               v.reset(OpAMD64VPROLVQMasked512)
+               v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x8ToM, types.TypeMask)
                v0.AddArg(mask)
                v.AddArg3(x, y, v0)
                return true
        }
 }
-func rewriteValueAMD64_OpMaskedSaturatedSubUint8x16(v *Value) bool {
+func rewriteValueAMD64_OpMaskedRotateRightInt32x16(v *Value) bool {
        v_2 := v.Args[2]
        v_1 := v.Args[1]
        v_0 := v.Args[0]
        b := v.Block
-       // match: (MaskedSaturatedSubUint8x16 x y mask)
-       // result: (VPSUBSBMasked128 x y (VPMOVVec8x16ToM <types.TypeMask> mask))
+       // match: (MaskedRotateRightInt32x16 x y mask)
+       // result: (VPRORVDMasked512 x y (VPMOVVec32x16ToM <types.TypeMask> mask))
        for {
                x := v_0
                y := v_1
                mask := v_2
-               v.reset(OpAMD64VPSUBSBMasked128)
-               v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec8x16ToM, types.TypeMask)
+               v.reset(OpAMD64VPRORVDMasked512)
+               v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x16ToM, types.TypeMask)
                v0.AddArg(mask)
                v.AddArg3(x, y, v0)
                return true
        }
 }
-func rewriteValueAMD64_OpMaskedSaturatedSubUint8x32(v *Value) bool {
+func rewriteValueAMD64_OpMaskedRotateRightInt32x4(v *Value) bool {
        v_2 := v.Args[2]
        v_1 := v.Args[1]
        v_0 := v.Args[0]
        b := v.Block
-       // match: (MaskedSaturatedSubUint8x32 x y mask)
-       // result: (VPSUBSBMasked256 x y (VPMOVVec8x32ToM <types.TypeMask> mask))
+       // match: (MaskedRotateRightInt32x4 x y mask)
+       // result: (VPRORVDMasked128 x y (VPMOVVec32x4ToM <types.TypeMask> mask))
        for {
                x := v_0
                y := v_1
                mask := v_2
-               v.reset(OpAMD64VPSUBSBMasked256)
-               v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec8x32ToM, types.TypeMask)
+               v.reset(OpAMD64VPRORVDMasked128)
+               v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x4ToM, types.TypeMask)
                v0.AddArg(mask)
                v.AddArg3(x, y, v0)
                return true
        }
 }
-func rewriteValueAMD64_OpMaskedSaturatedSubUint8x64(v *Value) bool {
+func rewriteValueAMD64_OpMaskedRotateRightInt32x8(v *Value) bool {
        v_2 := v.Args[2]
        v_1 := v.Args[1]
        v_0 := v.Args[0]
        b := v.Block
-       // match: (MaskedSaturatedSubUint8x64 x y mask)
-       // result: (VPSUBSBMasked512 x y (VPMOVVec8x64ToM <types.TypeMask> mask))
+       // match: (MaskedRotateRightInt32x8 x y mask)
+       // result: (VPRORVDMasked256 x y (VPMOVVec32x8ToM <types.TypeMask> mask))
        for {
                x := v_0
                y := v_1
                mask := v_2
-               v.reset(OpAMD64VPSUBSBMasked512)
-               v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec8x64ToM, types.TypeMask)
+               v.reset(OpAMD64VPRORVDMasked256)
+               v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x8ToM, types.TypeMask)
                v0.AddArg(mask)
                v.AddArg3(x, y, v0)
                return true
        }
 }
-func rewriteValueAMD64_OpMaskedSaturatedUnsignedSignedPairDotProdUint8x16(v *Value) bool {
+func rewriteValueAMD64_OpMaskedRotateRightInt64x2(v *Value) bool {
        v_2 := v.Args[2]
        v_1 := v.Args[1]
        v_0 := v.Args[0]
        b := v.Block
-       // match: (MaskedSaturatedUnsignedSignedPairDotProdUint8x16 x y mask)
-       // result: (VPMADDUBSWMasked128 x y (VPMOVVec16x8ToM <types.TypeMask> mask))
+       // match: (MaskedRotateRightInt64x2 x y mask)
+       // result: (VPRORVQMasked128 x y (VPMOVVec64x2ToM <types.TypeMask> mask))
        for {
                x := v_0
                y := v_1
                mask := v_2
-               v.reset(OpAMD64VPMADDUBSWMasked128)
-               v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x8ToM, types.TypeMask)
+               v.reset(OpAMD64VPRORVQMasked128)
+               v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x2ToM, types.TypeMask)
                v0.AddArg(mask)
                v.AddArg3(x, y, v0)
                return true
        }
 }
-func rewriteValueAMD64_OpMaskedSaturatedUnsignedSignedPairDotProdUint8x32(v *Value) bool {
+func rewriteValueAMD64_OpMaskedRotateRightInt64x4(v *Value) bool {
        v_2 := v.Args[2]
        v_1 := v.Args[1]
        v_0 := v.Args[0]
        b := v.Block
-       // match: (MaskedSaturatedUnsignedSignedPairDotProdUint8x32 x y mask)
-       // result: (VPMADDUBSWMasked256 x y (VPMOVVec16x16ToM <types.TypeMask> mask))
+       // match: (MaskedRotateRightInt64x4 x y mask)
+       // result: (VPRORVQMasked256 x y (VPMOVVec64x4ToM <types.TypeMask> mask))
        for {
                x := v_0
                y := v_1
                mask := v_2
-               v.reset(OpAMD64VPMADDUBSWMasked256)
-               v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x16ToM, types.TypeMask)
+               v.reset(OpAMD64VPRORVQMasked256)
+               v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x4ToM, types.TypeMask)
                v0.AddArg(mask)
                v.AddArg3(x, y, v0)
                return true
        }
 }
-func rewriteValueAMD64_OpMaskedSaturatedUnsignedSignedPairDotProdUint8x64(v *Value) bool {
+func rewriteValueAMD64_OpMaskedRotateRightInt64x8(v *Value) bool {
        v_2 := v.Args[2]
        v_1 := v.Args[1]
        v_0 := v.Args[0]
        b := v.Block
-       // match: (MaskedSaturatedUnsignedSignedPairDotProdUint8x64 x y mask)
-       // result: (VPMADDUBSWMasked512 x y (VPMOVVec16x32ToM <types.TypeMask> mask))
+       // match: (MaskedRotateRightInt64x8 x y mask)
+       // result: (VPRORVQMasked512 x y (VPMOVVec64x8ToM <types.TypeMask> mask))
        for {
                x := v_0
                y := v_1
                mask := v_2
-               v.reset(OpAMD64VPMADDUBSWMasked512)
-               v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x32ToM, types.TypeMask)
+               v.reset(OpAMD64VPRORVQMasked512)
+               v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x8ToM, types.TypeMask)
                v0.AddArg(mask)
                v.AddArg3(x, y, v0)
                return true
        }
 }
-func rewriteValueAMD64_OpMaskedSaturatedUnsignedSignedQuadDotProdAccumulateInt32x16(v *Value) bool {
-       v_3 := v.Args[3]
+func rewriteValueAMD64_OpMaskedRotateRightUint32x16(v *Value) bool {
        v_2 := v.Args[2]
        v_1 := v.Args[1]
        v_0 := v.Args[0]
        b := v.Block
-       // match: (MaskedSaturatedUnsignedSignedQuadDotProdAccumulateInt32x16 x y z mask)
-       // result: (VPDPBUSDSMasked512 x y z (VPMOVVec32x16ToM <types.TypeMask> mask))
+       // match: (MaskedRotateRightUint32x16 x y mask)
+       // result: (VPRORVDMasked512 x y (VPMOVVec32x16ToM <types.TypeMask> mask))
        for {
                x := v_0
                y := v_1
-               z := v_2
-               mask := v_3
-               v.reset(OpAMD64VPDPBUSDSMasked512)
+               mask := v_2
+               v.reset(OpAMD64VPRORVDMasked512)
                v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x16ToM, types.TypeMask)
                v0.AddArg(mask)
-               v.AddArg4(x, y, z, v0)
+               v.AddArg3(x, y, v0)
                return true
        }
 }
-func rewriteValueAMD64_OpMaskedSaturatedUnsignedSignedQuadDotProdAccumulateInt32x4(v *Value) bool {
-       v_3 := v.Args[3]
+func rewriteValueAMD64_OpMaskedRotateRightUint32x4(v *Value) bool {
        v_2 := v.Args[2]
        v_1 := v.Args[1]
        v_0 := v.Args[0]
        b := v.Block
-       // match: (MaskedSaturatedUnsignedSignedQuadDotProdAccumulateInt32x4 x y z mask)
-       // result: (VPDPBUSDSMasked128 x y z (VPMOVVec32x4ToM <types.TypeMask> mask))
+       // match: (MaskedRotateRightUint32x4 x y mask)
+       // result: (VPRORVDMasked128 x y (VPMOVVec32x4ToM <types.TypeMask> mask))
        for {
                x := v_0
                y := v_1
-               z := v_2
-               mask := v_3
-               v.reset(OpAMD64VPDPBUSDSMasked128)
+               mask := v_2
+               v.reset(OpAMD64VPRORVDMasked128)
                v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x4ToM, types.TypeMask)
                v0.AddArg(mask)
-               v.AddArg4(x, y, z, v0)
+               v.AddArg3(x, y, v0)
+               return true
+       }
+}
+func rewriteValueAMD64_OpMaskedRotateRightUint32x8(v *Value) bool {
+       v_2 := v.Args[2]
+       v_1 := v.Args[1]
+       v_0 := v.Args[0]
+       b := v.Block
+       // match: (MaskedRotateRightUint32x8 x y mask)
+       // result: (VPRORVDMasked256 x y (VPMOVVec32x8ToM <types.TypeMask> mask))
+       for {
+               x := v_0
+               y := v_1
+               mask := v_2
+               v.reset(OpAMD64VPRORVDMasked256)
+               v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x8ToM, types.TypeMask)
+               v0.AddArg(mask)
+               v.AddArg3(x, y, v0)
+               return true
+       }
+}
+func rewriteValueAMD64_OpMaskedRotateRightUint64x2(v *Value) bool {
+       v_2 := v.Args[2]
+       v_1 := v.Args[1]
+       v_0 := v.Args[0]
+       b := v.Block
+       // match: (MaskedRotateRightUint64x2 x y mask)
+       // result: (VPRORVQMasked128 x y (VPMOVVec64x2ToM <types.TypeMask> mask))
+       for {
+               x := v_0
+               y := v_1
+               mask := v_2
+               v.reset(OpAMD64VPRORVQMasked128)
+               v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x2ToM, types.TypeMask)
+               v0.AddArg(mask)
+               v.AddArg3(x, y, v0)
+               return true
+       }
+}
+func rewriteValueAMD64_OpMaskedRotateRightUint64x4(v *Value) bool {
+       v_2 := v.Args[2]
+       v_1 := v.Args[1]
+       v_0 := v.Args[0]
+       b := v.Block
+       // match: (MaskedRotateRightUint64x4 x y mask)
+       // result: (VPRORVQMasked256 x y (VPMOVVec64x4ToM <types.TypeMask> mask))
+       for {
+               x := v_0
+               y := v_1
+               mask := v_2
+               v.reset(OpAMD64VPRORVQMasked256)
+               v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x4ToM, types.TypeMask)
+               v0.AddArg(mask)
+               v.AddArg3(x, y, v0)
+               return true
+       }
+}
+func rewriteValueAMD64_OpMaskedRotateRightUint64x8(v *Value) bool {
+       v_2 := v.Args[2]
+       v_1 := v.Args[1]
+       v_0 := v.Args[0]
+       b := v.Block
+       // match: (MaskedRotateRightUint64x8 x y mask)
+       // result: (VPRORVQMasked512 x y (VPMOVVec64x8ToM <types.TypeMask> mask))
+       for {
+               x := v_0
+               y := v_1
+               mask := v_2
+               v.reset(OpAMD64VPRORVQMasked512)
+               v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x8ToM, types.TypeMask)
+               v0.AddArg(mask)
+               v.AddArg3(x, y, v0)
+               return true
+       }
+}
+func rewriteValueAMD64_OpMaskedRoundSuppressExceptionWithPrecisionFloat32x16(v *Value) bool {
+       v_1 := v.Args[1]
+       v_0 := v.Args[0]
+       b := v.Block
+       // match: (MaskedRoundSuppressExceptionWithPrecisionFloat32x16 [a] x mask)
+       // result: (VRNDSCALEPSMasked512 [a+8] x (VPMOVVec32x16ToM <types.TypeMask> mask))
+       for {
+               a := auxIntToInt8(v.AuxInt)
+               x := v_0
+               mask := v_1
+               v.reset(OpAMD64VRNDSCALEPSMasked512)
+               v.AuxInt = int8ToAuxInt(a + 8)
+               v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x16ToM, types.TypeMask)
+               v0.AddArg(mask)
+               v.AddArg2(x, v0)
+               return true
+       }
+}
+func rewriteValueAMD64_OpMaskedRoundSuppressExceptionWithPrecisionFloat32x4(v *Value) bool {
+       v_1 := v.Args[1]
+       v_0 := v.Args[0]
+       b := v.Block
+       // match: (MaskedRoundSuppressExceptionWithPrecisionFloat32x4 [a] x mask)
+       // result: (VRNDSCALEPSMasked128 [a+8] x (VPMOVVec32x4ToM <types.TypeMask> mask))
+       for {
+               a := auxIntToInt8(v.AuxInt)
+               x := v_0
+               mask := v_1
+               v.reset(OpAMD64VRNDSCALEPSMasked128)
+               v.AuxInt = int8ToAuxInt(a + 8)
+               v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x4ToM, types.TypeMask)
+               v0.AddArg(mask)
+               v.AddArg2(x, v0)
+               return true
+       }
+}
+func rewriteValueAMD64_OpMaskedRoundSuppressExceptionWithPrecisionFloat32x8(v *Value) bool {
+       v_1 := v.Args[1]
+       v_0 := v.Args[0]
+       b := v.Block
+       // match: (MaskedRoundSuppressExceptionWithPrecisionFloat32x8 [a] x mask)
+       // result: (VRNDSCALEPSMasked256 [a+8] x (VPMOVVec32x8ToM <types.TypeMask> mask))
+       for {
+               a := auxIntToInt8(v.AuxInt)
+               x := v_0
+               mask := v_1
+               v.reset(OpAMD64VRNDSCALEPSMasked256)
+               v.AuxInt = int8ToAuxInt(a + 8)
+               v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x8ToM, types.TypeMask)
+               v0.AddArg(mask)
+               v.AddArg2(x, v0)
+               return true
+       }
+}
+func rewriteValueAMD64_OpMaskedRoundSuppressExceptionWithPrecisionFloat64x2(v *Value) bool {
+       v_1 := v.Args[1]
+       v_0 := v.Args[0]
+       b := v.Block
+       // match: (MaskedRoundSuppressExceptionWithPrecisionFloat64x2 [a] x mask)
+       // result: (VRNDSCALEPDMasked128 [a+8] x (VPMOVVec64x2ToM <types.TypeMask> mask))
+       for {
+               a := auxIntToInt8(v.AuxInt)
+               x := v_0
+               mask := v_1
+               v.reset(OpAMD64VRNDSCALEPDMasked128)
+               v.AuxInt = int8ToAuxInt(a + 8)
+               v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x2ToM, types.TypeMask)
+               v0.AddArg(mask)
+               v.AddArg2(x, v0)
+               return true
+       }
+}
+func rewriteValueAMD64_OpMaskedRoundSuppressExceptionWithPrecisionFloat64x4(v *Value) bool {
+       v_1 := v.Args[1]
+       v_0 := v.Args[0]
+       b := v.Block
+       // match: (MaskedRoundSuppressExceptionWithPrecisionFloat64x4 [a] x mask)
+       // result: (VRNDSCALEPDMasked256 [a+8] x (VPMOVVec64x4ToM <types.TypeMask> mask))
+       for {
+               a := auxIntToInt8(v.AuxInt)
+               x := v_0
+               mask := v_1
+               v.reset(OpAMD64VRNDSCALEPDMasked256)
+               v.AuxInt = int8ToAuxInt(a + 8)
+               v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x4ToM, types.TypeMask)
+               v0.AddArg(mask)
+               v.AddArg2(x, v0)
+               return true
+       }
+}
+func rewriteValueAMD64_OpMaskedRoundSuppressExceptionWithPrecisionFloat64x8(v *Value) bool {
+       v_1 := v.Args[1]
+       v_0 := v.Args[0]
+       b := v.Block
+       // match: (MaskedRoundSuppressExceptionWithPrecisionFloat64x8 [a] x mask)
+       // result: (VRNDSCALEPDMasked512 [a+8] x (VPMOVVec64x8ToM <types.TypeMask> mask))
+       for {
+               a := auxIntToInt8(v.AuxInt)
+               x := v_0
+               mask := v_1
+               v.reset(OpAMD64VRNDSCALEPDMasked512)
+               v.AuxInt = int8ToAuxInt(a + 8)
+               v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x8ToM, types.TypeMask)
+               v0.AddArg(mask)
+               v.AddArg2(x, v0)
+               return true
+       }
+}
+func rewriteValueAMD64_OpMaskedRoundWithPrecisionFloat32x16(v *Value) bool {
+       v_1 := v.Args[1]
+       v_0 := v.Args[0]
+       b := v.Block
+       // match: (MaskedRoundWithPrecisionFloat32x16 [a] x mask)
+       // result: (VRNDSCALEPSMasked512 [a+0] x (VPMOVVec32x16ToM <types.TypeMask> mask))
+       for {
+               a := auxIntToInt8(v.AuxInt)
+               x := v_0
+               mask := v_1
+               v.reset(OpAMD64VRNDSCALEPSMasked512)
+               v.AuxInt = int8ToAuxInt(a + 0)
+               v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x16ToM, types.TypeMask)
+               v0.AddArg(mask)
+               v.AddArg2(x, v0)
+               return true
+       }
+}
+func rewriteValueAMD64_OpMaskedRoundWithPrecisionFloat32x4(v *Value) bool {
+       v_1 := v.Args[1]
+       v_0 := v.Args[0]
+       b := v.Block
+       // match: (MaskedRoundWithPrecisionFloat32x4 [a] x mask)
+       // result: (VRNDSCALEPSMasked128 [a+0] x (VPMOVVec32x4ToM <types.TypeMask> mask))
+       for {
+               a := auxIntToInt8(v.AuxInt)
+               x := v_0
+               mask := v_1
+               v.reset(OpAMD64VRNDSCALEPSMasked128)
+               v.AuxInt = int8ToAuxInt(a + 0)
+               v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x4ToM, types.TypeMask)
+               v0.AddArg(mask)
+               v.AddArg2(x, v0)
+               return true
+       }
+}
+func rewriteValueAMD64_OpMaskedRoundWithPrecisionFloat32x8(v *Value) bool {
+       v_1 := v.Args[1]
+       v_0 := v.Args[0]
+       b := v.Block
+       // match: (MaskedRoundWithPrecisionFloat32x8 [a] x mask)
+       // result: (VRNDSCALEPSMasked256 [a+0] x (VPMOVVec32x8ToM <types.TypeMask> mask))
+       for {
+               a := auxIntToInt8(v.AuxInt)
+               x := v_0
+               mask := v_1
+               v.reset(OpAMD64VRNDSCALEPSMasked256)
+               v.AuxInt = int8ToAuxInt(a + 0)
+               v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x8ToM, types.TypeMask)
+               v0.AddArg(mask)
+               v.AddArg2(x, v0)
+               return true
+       }
+}
+func rewriteValueAMD64_OpMaskedRoundWithPrecisionFloat64x2(v *Value) bool {
+       v_1 := v.Args[1]
+       v_0 := v.Args[0]
+       b := v.Block
+       // match: (MaskedRoundWithPrecisionFloat64x2 [a] x mask)
+       // result: (VRNDSCALEPDMasked128 [a+0] x (VPMOVVec64x2ToM <types.TypeMask> mask))
+       for {
+               a := auxIntToInt8(v.AuxInt)
+               x := v_0
+               mask := v_1
+               v.reset(OpAMD64VRNDSCALEPDMasked128)
+               v.AuxInt = int8ToAuxInt(a + 0)
+               v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x2ToM, types.TypeMask)
+               v0.AddArg(mask)
+               v.AddArg2(x, v0)
+               return true
+       }
+}
+func rewriteValueAMD64_OpMaskedRoundWithPrecisionFloat64x4(v *Value) bool {
+       v_1 := v.Args[1]
+       v_0 := v.Args[0]
+       b := v.Block
+       // match: (MaskedRoundWithPrecisionFloat64x4 [a] x mask)
+       // result: (VRNDSCALEPDMasked256 [a+0] x (VPMOVVec64x4ToM <types.TypeMask> mask))
+       for {
+               a := auxIntToInt8(v.AuxInt)
+               x := v_0
+               mask := v_1
+               v.reset(OpAMD64VRNDSCALEPDMasked256)
+               v.AuxInt = int8ToAuxInt(a + 0)
+               v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x4ToM, types.TypeMask)
+               v0.AddArg(mask)
+               v.AddArg2(x, v0)
+               return true
+       }
+}
+func rewriteValueAMD64_OpMaskedRoundWithPrecisionFloat64x8(v *Value) bool {
+       v_1 := v.Args[1]
+       v_0 := v.Args[0]
+       b := v.Block
+       // match: (MaskedRoundWithPrecisionFloat64x8 [a] x mask)
+       // result: (VRNDSCALEPDMasked512 [a+0] x (VPMOVVec64x8ToM <types.TypeMask> mask))
+       for {
+               a := auxIntToInt8(v.AuxInt)
+               x := v_0
+               mask := v_1
+               v.reset(OpAMD64VRNDSCALEPDMasked512)
+               v.AuxInt = int8ToAuxInt(a + 0)
+               v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x8ToM, types.TypeMask)
+               v0.AddArg(mask)
+               v.AddArg2(x, v0)
+               return true
+       }
+}
+func rewriteValueAMD64_OpMaskedSaturatedAddInt16x16(v *Value) bool {
+       v_2 := v.Args[2]
+       v_1 := v.Args[1]
+       v_0 := v.Args[0]
+       b := v.Block
+       // match: (MaskedSaturatedAddInt16x16 x y mask)
+       // result: (VPADDSWMasked256 x y (VPMOVVec16x16ToM <types.TypeMask> mask))
+       for {
+               x := v_0
+               y := v_1
+               mask := v_2
+               v.reset(OpAMD64VPADDSWMasked256)
+               v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x16ToM, types.TypeMask)
+               v0.AddArg(mask)
+               v.AddArg3(x, y, v0)
+               return true
+       }
+}
+func rewriteValueAMD64_OpMaskedSaturatedAddInt16x32(v *Value) bool {
+       v_2 := v.Args[2]
+       v_1 := v.Args[1]
+       v_0 := v.Args[0]
+       b := v.Block
+       // match: (MaskedSaturatedAddInt16x32 x y mask)
+       // result: (VPADDSWMasked512 x y (VPMOVVec16x32ToM <types.TypeMask> mask))
+       for {
+               x := v_0
+               y := v_1
+               mask := v_2
+               v.reset(OpAMD64VPADDSWMasked512)
+               v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x32ToM, types.TypeMask)
+               v0.AddArg(mask)
+               v.AddArg3(x, y, v0)
+               return true
+       }
+}
+func rewriteValueAMD64_OpMaskedSaturatedAddInt16x8(v *Value) bool {
+       v_2 := v.Args[2]
+       v_1 := v.Args[1]
+       v_0 := v.Args[0]
+       b := v.Block
+       // match: (MaskedSaturatedAddInt16x8 x y mask)
+       // result: (VPADDSWMasked128 x y (VPMOVVec16x8ToM <types.TypeMask> mask))
+       for {
+               x := v_0
+               y := v_1
+               mask := v_2
+               v.reset(OpAMD64VPADDSWMasked128)
+               v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x8ToM, types.TypeMask)
+               v0.AddArg(mask)
+               v.AddArg3(x, y, v0)
+               return true
+       }
+}
+func rewriteValueAMD64_OpMaskedSaturatedAddInt8x16(v *Value) bool {
+       v_2 := v.Args[2]
+       v_1 := v.Args[1]
+       v_0 := v.Args[0]
+       b := v.Block
+       // match: (MaskedSaturatedAddInt8x16 x y mask)
+       // result: (VPADDSBMasked128 x y (VPMOVVec8x16ToM <types.TypeMask> mask))
+       for {
+               x := v_0
+               y := v_1
+               mask := v_2
+               v.reset(OpAMD64VPADDSBMasked128)
+               v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec8x16ToM, types.TypeMask)
+               v0.AddArg(mask)
+               v.AddArg3(x, y, v0)
+               return true
+       }
+}
+func rewriteValueAMD64_OpMaskedSaturatedAddInt8x32(v *Value) bool {
+       v_2 := v.Args[2]
+       v_1 := v.Args[1]
+       v_0 := v.Args[0]
+       b := v.Block
+       // match: (MaskedSaturatedAddInt8x32 x y mask)
+       // result: (VPADDSBMasked256 x y (VPMOVVec8x32ToM <types.TypeMask> mask))
+       for {
+               x := v_0
+               y := v_1
+               mask := v_2
+               v.reset(OpAMD64VPADDSBMasked256)
+               v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec8x32ToM, types.TypeMask)
+               v0.AddArg(mask)
+               v.AddArg3(x, y, v0)
+               return true
+       }
+}
+func rewriteValueAMD64_OpMaskedSaturatedAddInt8x64(v *Value) bool {
+       v_2 := v.Args[2]
+       v_1 := v.Args[1]
+       v_0 := v.Args[0]
+       b := v.Block
+       // match: (MaskedSaturatedAddInt8x64 x y mask)
+       // result: (VPADDSBMasked512 x y (VPMOVVec8x64ToM <types.TypeMask> mask))
+       for {
+               x := v_0
+               y := v_1
+               mask := v_2
+               v.reset(OpAMD64VPADDSBMasked512)
+               v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec8x64ToM, types.TypeMask)
+               v0.AddArg(mask)
+               v.AddArg3(x, y, v0)
+               return true
+       }
+}
+func rewriteValueAMD64_OpMaskedSaturatedAddUint16x16(v *Value) bool {
+       v_2 := v.Args[2]
+       v_1 := v.Args[1]
+       v_0 := v.Args[0]
+       b := v.Block
+       // match: (MaskedSaturatedAddUint16x16 x y mask)
+       // result: (VPADDSWMasked256 x y (VPMOVVec16x16ToM <types.TypeMask> mask))
+       for {
+               x := v_0
+               y := v_1
+               mask := v_2
+               v.reset(OpAMD64VPADDSWMasked256)
+               v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x16ToM, types.TypeMask)
+               v0.AddArg(mask)
+               v.AddArg3(x, y, v0)
+               return true
+       }
+}
+func rewriteValueAMD64_OpMaskedSaturatedAddUint16x32(v *Value) bool {
+       v_2 := v.Args[2]
+       v_1 := v.Args[1]
+       v_0 := v.Args[0]
+       b := v.Block
+       // match: (MaskedSaturatedAddUint16x32 x y mask)
+       // result: (VPADDSWMasked512 x y (VPMOVVec16x32ToM <types.TypeMask> mask))
+       for {
+               x := v_0
+               y := v_1
+               mask := v_2
+               v.reset(OpAMD64VPADDSWMasked512)
+               v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x32ToM, types.TypeMask)
+               v0.AddArg(mask)
+               v.AddArg3(x, y, v0)
+               return true
+       }
+}
+func rewriteValueAMD64_OpMaskedSaturatedAddUint16x8(v *Value) bool {
+       v_2 := v.Args[2]
+       v_1 := v.Args[1]
+       v_0 := v.Args[0]
+       b := v.Block
+       // match: (MaskedSaturatedAddUint16x8 x y mask)
+       // result: (VPADDSWMasked128 x y (VPMOVVec16x8ToM <types.TypeMask> mask))
+       for {
+               x := v_0
+               y := v_1
+               mask := v_2
+               v.reset(OpAMD64VPADDSWMasked128)
+               v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x8ToM, types.TypeMask)
+               v0.AddArg(mask)
+               v.AddArg3(x, y, v0)
+               return true
+       }
+}
+func rewriteValueAMD64_OpMaskedSaturatedAddUint8x16(v *Value) bool {
+       v_2 := v.Args[2]
+       v_1 := v.Args[1]
+       v_0 := v.Args[0]
+       b := v.Block
+       // match: (MaskedSaturatedAddUint8x16 x y mask)
+       // result: (VPADDSBMasked128 x y (VPMOVVec8x16ToM <types.TypeMask> mask))
+       for {
+               x := v_0
+               y := v_1
+               mask := v_2
+               v.reset(OpAMD64VPADDSBMasked128)
+               v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec8x16ToM, types.TypeMask)
+               v0.AddArg(mask)
+               v.AddArg3(x, y, v0)
+               return true
+       }
+}
+func rewriteValueAMD64_OpMaskedSaturatedAddUint8x32(v *Value) bool {
+       v_2 := v.Args[2]
+       v_1 := v.Args[1]
+       v_0 := v.Args[0]
+       b := v.Block
+       // match: (MaskedSaturatedAddUint8x32 x y mask)
+       // result: (VPADDSBMasked256 x y (VPMOVVec8x32ToM <types.TypeMask> mask))
+       for {
+               x := v_0
+               y := v_1
+               mask := v_2
+               v.reset(OpAMD64VPADDSBMasked256)
+               v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec8x32ToM, types.TypeMask)
+               v0.AddArg(mask)
+               v.AddArg3(x, y, v0)
+               return true
+       }
+}
+func rewriteValueAMD64_OpMaskedSaturatedAddUint8x64(v *Value) bool {
+       v_2 := v.Args[2]
+       v_1 := v.Args[1]
+       v_0 := v.Args[0]
+       b := v.Block
+       // match: (MaskedSaturatedAddUint8x64 x y mask)
+       // result: (VPADDSBMasked512 x y (VPMOVVec8x64ToM <types.TypeMask> mask))
+       for {
+               x := v_0
+               y := v_1
+               mask := v_2
+               v.reset(OpAMD64VPADDSBMasked512)
+               v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec8x64ToM, types.TypeMask)
+               v0.AddArg(mask)
+               v.AddArg3(x, y, v0)
+               return true
+       }
+}
+func rewriteValueAMD64_OpMaskedSaturatedPairDotProdAccumulateInt32x16(v *Value) bool {
+       v_3 := v.Args[3]
+       v_2 := v.Args[2]
+       v_1 := v.Args[1]
+       v_0 := v.Args[0]
+       b := v.Block
+       // match: (MaskedSaturatedPairDotProdAccumulateInt32x16 x y z mask)
+       // result: (VPDPWSSDSMasked512 x y z (VPMOVVec32x16ToM <types.TypeMask> mask))
+       for {
+               x := v_0
+               y := v_1
+               z := v_2
+               mask := v_3
+               v.reset(OpAMD64VPDPWSSDSMasked512)
+               v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x16ToM, types.TypeMask)
+               v0.AddArg(mask)
+               v.AddArg4(x, y, z, v0)
+               return true
+       }
+}
+func rewriteValueAMD64_OpMaskedSaturatedPairDotProdAccumulateInt32x4(v *Value) bool {
+       v_3 := v.Args[3]
+       v_2 := v.Args[2]
+       v_1 := v.Args[1]
+       v_0 := v.Args[0]
+       b := v.Block
+       // match: (MaskedSaturatedPairDotProdAccumulateInt32x4 x y z mask)
+       // result: (VPDPWSSDSMasked128 x y z (VPMOVVec32x4ToM <types.TypeMask> mask))
+       for {
+               x := v_0
+               y := v_1
+               z := v_2
+               mask := v_3
+               v.reset(OpAMD64VPDPWSSDSMasked128)
+               v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x4ToM, types.TypeMask)
+               v0.AddArg(mask)
+               v.AddArg4(x, y, z, v0)
+               return true
+       }
+}
+func rewriteValueAMD64_OpMaskedSaturatedPairDotProdAccumulateInt32x8(v *Value) bool {
+       v_3 := v.Args[3]
+       v_2 := v.Args[2]
+       v_1 := v.Args[1]
+       v_0 := v.Args[0]
+       b := v.Block
+       // match: (MaskedSaturatedPairDotProdAccumulateInt32x8 x y z mask)
+       // result: (VPDPWSSDSMasked256 x y z (VPMOVVec32x8ToM <types.TypeMask> mask))
+       for {
+               x := v_0
+               y := v_1
+               z := v_2
+               mask := v_3
+               v.reset(OpAMD64VPDPWSSDSMasked256)
+               v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x8ToM, types.TypeMask)
+               v0.AddArg(mask)
+               v.AddArg4(x, y, z, v0)
+               return true
+       }
+}
+func rewriteValueAMD64_OpMaskedSaturatedSubInt16x16(v *Value) bool {
+       v_2 := v.Args[2]
+       v_1 := v.Args[1]
+       v_0 := v.Args[0]
+       b := v.Block
+       // match: (MaskedSaturatedSubInt16x16 x y mask)
+       // result: (VPSUBSWMasked256 x y (VPMOVVec16x16ToM <types.TypeMask> mask))
+       for {
+               x := v_0
+               y := v_1
+               mask := v_2
+               v.reset(OpAMD64VPSUBSWMasked256)
+               v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x16ToM, types.TypeMask)
+               v0.AddArg(mask)
+               v.AddArg3(x, y, v0)
+               return true
+       }
+}
+func rewriteValueAMD64_OpMaskedSaturatedSubInt16x32(v *Value) bool {
+       v_2 := v.Args[2]
+       v_1 := v.Args[1]
+       v_0 := v.Args[0]
+       b := v.Block
+       // match: (MaskedSaturatedSubInt16x32 x y mask)
+       // result: (VPSUBSWMasked512 x y (VPMOVVec16x32ToM <types.TypeMask> mask))
+       for {
+               x := v_0
+               y := v_1
+               mask := v_2
+               v.reset(OpAMD64VPSUBSWMasked512)
+               v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x32ToM, types.TypeMask)
+               v0.AddArg(mask)
+               v.AddArg3(x, y, v0)
+               return true
+       }
+}
+func rewriteValueAMD64_OpMaskedSaturatedSubInt16x8(v *Value) bool {
+       v_2 := v.Args[2]
+       v_1 := v.Args[1]
+       v_0 := v.Args[0]
+       b := v.Block
+       // match: (MaskedSaturatedSubInt16x8 x y mask)
+       // result: (VPSUBSWMasked128 x y (VPMOVVec16x8ToM <types.TypeMask> mask))
+       for {
+               x := v_0
+               y := v_1
+               mask := v_2
+               v.reset(OpAMD64VPSUBSWMasked128)
+               v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x8ToM, types.TypeMask)
+               v0.AddArg(mask)
+               v.AddArg3(x, y, v0)
+               return true
+       }
+}
+func rewriteValueAMD64_OpMaskedSaturatedSubInt8x16(v *Value) bool {
+       v_2 := v.Args[2]
+       v_1 := v.Args[1]
+       v_0 := v.Args[0]
+       b := v.Block
+       // match: (MaskedSaturatedSubInt8x16 x y mask)
+       // result: (VPSUBSBMasked128 x y (VPMOVVec8x16ToM <types.TypeMask> mask))
+       for {
+               x := v_0
+               y := v_1
+               mask := v_2
+               v.reset(OpAMD64VPSUBSBMasked128)
+               v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec8x16ToM, types.TypeMask)
+               v0.AddArg(mask)
+               v.AddArg3(x, y, v0)
+               return true
+       }
+}
+func rewriteValueAMD64_OpMaskedSaturatedSubInt8x32(v *Value) bool {
+       v_2 := v.Args[2]
+       v_1 := v.Args[1]
+       v_0 := v.Args[0]
+       b := v.Block
+       // match: (MaskedSaturatedSubInt8x32 x y mask)
+       // result: (VPSUBSBMasked256 x y (VPMOVVec8x32ToM <types.TypeMask> mask))
+       for {
+               x := v_0
+               y := v_1
+               mask := v_2
+               v.reset(OpAMD64VPSUBSBMasked256)
+               v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec8x32ToM, types.TypeMask)
+               v0.AddArg(mask)
+               v.AddArg3(x, y, v0)
+               return true
+       }
+}
+func rewriteValueAMD64_OpMaskedSaturatedSubInt8x64(v *Value) bool {
+       v_2 := v.Args[2]
+       v_1 := v.Args[1]
+       v_0 := v.Args[0]
+       b := v.Block
+       // match: (MaskedSaturatedSubInt8x64 x y mask)
+       // result: (VPSUBSBMasked512 x y (VPMOVVec8x64ToM <types.TypeMask> mask))
+       for {
+               x := v_0
+               y := v_1
+               mask := v_2
+               v.reset(OpAMD64VPSUBSBMasked512)
+               v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec8x64ToM, types.TypeMask)
+               v0.AddArg(mask)
+               v.AddArg3(x, y, v0)
+               return true
+       }
+}
+func rewriteValueAMD64_OpMaskedSaturatedSubUint16x16(v *Value) bool {
+       v_2 := v.Args[2]
+       v_1 := v.Args[1]
+       v_0 := v.Args[0]
+       b := v.Block
+       // match: (MaskedSaturatedSubUint16x16 x y mask)
+       // result: (VPSUBSWMasked256 x y (VPMOVVec16x16ToM <types.TypeMask> mask))
+       for {
+               x := v_0
+               y := v_1
+               mask := v_2
+               v.reset(OpAMD64VPSUBSWMasked256)
+               v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x16ToM, types.TypeMask)
+               v0.AddArg(mask)
+               v.AddArg3(x, y, v0)
+               return true
+       }
+}
+func rewriteValueAMD64_OpMaskedSaturatedSubUint16x32(v *Value) bool {
+       v_2 := v.Args[2]
+       v_1 := v.Args[1]
+       v_0 := v.Args[0]
+       b := v.Block
+       // match: (MaskedSaturatedSubUint16x32 x y mask)
+       // result: (VPSUBSWMasked512 x y (VPMOVVec16x32ToM <types.TypeMask> mask))
+       for {
+               x := v_0
+               y := v_1
+               mask := v_2
+               v.reset(OpAMD64VPSUBSWMasked512)
+               v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x32ToM, types.TypeMask)
+               v0.AddArg(mask)
+               v.AddArg3(x, y, v0)
+               return true
+       }
+}
+func rewriteValueAMD64_OpMaskedSaturatedSubUint16x8(v *Value) bool {
+       v_2 := v.Args[2]
+       v_1 := v.Args[1]
+       v_0 := v.Args[0]
+       b := v.Block
+       // match: (MaskedSaturatedSubUint16x8 x y mask)
+       // result: (VPSUBSWMasked128 x y (VPMOVVec16x8ToM <types.TypeMask> mask))
+       for {
+               x := v_0
+               y := v_1
+               mask := v_2
+               v.reset(OpAMD64VPSUBSWMasked128)
+               v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x8ToM, types.TypeMask)
+               v0.AddArg(mask)
+               v.AddArg3(x, y, v0)
+               return true
+       }
+}
+func rewriteValueAMD64_OpMaskedSaturatedSubUint8x16(v *Value) bool {
+       v_2 := v.Args[2]
+       v_1 := v.Args[1]
+       v_0 := v.Args[0]
+       b := v.Block
+       // match: (MaskedSaturatedSubUint8x16 x y mask)
+       // result: (VPSUBSBMasked128 x y (VPMOVVec8x16ToM <types.TypeMask> mask))
+       for {
+               x := v_0
+               y := v_1
+               mask := v_2
+               v.reset(OpAMD64VPSUBSBMasked128)
+               v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec8x16ToM, types.TypeMask)
+               v0.AddArg(mask)
+               v.AddArg3(x, y, v0)
+               return true
+       }
+}
+func rewriteValueAMD64_OpMaskedSaturatedSubUint8x32(v *Value) bool {
+       v_2 := v.Args[2]
+       v_1 := v.Args[1]
+       v_0 := v.Args[0]
+       b := v.Block
+       // match: (MaskedSaturatedSubUint8x32 x y mask)
+       // result: (VPSUBSBMasked256 x y (VPMOVVec8x32ToM <types.TypeMask> mask))
+       for {
+               x := v_0
+               y := v_1
+               mask := v_2
+               v.reset(OpAMD64VPSUBSBMasked256)
+               v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec8x32ToM, types.TypeMask)
+               v0.AddArg(mask)
+               v.AddArg3(x, y, v0)
+               return true
+       }
+}
+func rewriteValueAMD64_OpMaskedSaturatedSubUint8x64(v *Value) bool {
+       v_2 := v.Args[2]
+       v_1 := v.Args[1]
+       v_0 := v.Args[0]
+       b := v.Block
+       // match: (MaskedSaturatedSubUint8x64 x y mask)
+       // result: (VPSUBSBMasked512 x y (VPMOVVec8x64ToM <types.TypeMask> mask))
+       for {
+               x := v_0
+               y := v_1
+               mask := v_2
+               v.reset(OpAMD64VPSUBSBMasked512)
+               v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec8x64ToM, types.TypeMask)
+               v0.AddArg(mask)
+               v.AddArg3(x, y, v0)
+               return true
+       }
+}
+func rewriteValueAMD64_OpMaskedSaturatedUnsignedSignedPairDotProdUint8x16(v *Value) bool {
+       v_2 := v.Args[2]
+       v_1 := v.Args[1]
+       v_0 := v.Args[0]
+       b := v.Block
+       // match: (MaskedSaturatedUnsignedSignedPairDotProdUint8x16 x y mask)
+       // result: (VPMADDUBSWMasked128 x y (VPMOVVec16x8ToM <types.TypeMask> mask))
+       for {
+               x := v_0
+               y := v_1
+               mask := v_2
+               v.reset(OpAMD64VPMADDUBSWMasked128)
+               v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x8ToM, types.TypeMask)
+               v0.AddArg(mask)
+               v.AddArg3(x, y, v0)
+               return true
+       }
+}
+func rewriteValueAMD64_OpMaskedSaturatedUnsignedSignedPairDotProdUint8x32(v *Value) bool {
+       v_2 := v.Args[2]
+       v_1 := v.Args[1]
+       v_0 := v.Args[0]
+       b := v.Block
+       // match: (MaskedSaturatedUnsignedSignedPairDotProdUint8x32 x y mask)
+       // result: (VPMADDUBSWMasked256 x y (VPMOVVec16x16ToM <types.TypeMask> mask))
+       for {
+               x := v_0
+               y := v_1
+               mask := v_2
+               v.reset(OpAMD64VPMADDUBSWMasked256)
+               v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x16ToM, types.TypeMask)
+               v0.AddArg(mask)
+               v.AddArg3(x, y, v0)
+               return true
+       }
+}
+func rewriteValueAMD64_OpMaskedSaturatedUnsignedSignedPairDotProdUint8x64(v *Value) bool {
+       v_2 := v.Args[2]
+       v_1 := v.Args[1]
+       v_0 := v.Args[0]
+       b := v.Block
+       // match: (MaskedSaturatedUnsignedSignedPairDotProdUint8x64 x y mask)
+       // result: (VPMADDUBSWMasked512 x y (VPMOVVec16x32ToM <types.TypeMask> mask))
+       for {
+               x := v_0
+               y := v_1
+               mask := v_2
+               v.reset(OpAMD64VPMADDUBSWMasked512)
+               v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x32ToM, types.TypeMask)
+               v0.AddArg(mask)
+               v.AddArg3(x, y, v0)
+               return true
+       }
+}
+func rewriteValueAMD64_OpMaskedSaturatedUnsignedSignedQuadDotProdAccumulateInt32x16(v *Value) bool {
+       v_3 := v.Args[3]
+       v_2 := v.Args[2]
+       v_1 := v.Args[1]
+       v_0 := v.Args[0]
+       b := v.Block
+       // match: (MaskedSaturatedUnsignedSignedQuadDotProdAccumulateInt32x16 x y z mask)
+       // result: (VPDPBUSDSMasked512 x y z (VPMOVVec32x16ToM <types.TypeMask> mask))
+       for {
+               x := v_0
+               y := v_1
+               z := v_2
+               mask := v_3
+               v.reset(OpAMD64VPDPBUSDSMasked512)
+               v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x16ToM, types.TypeMask)
+               v0.AddArg(mask)
+               v.AddArg4(x, y, z, v0)
+               return true
+       }
+}
+func rewriteValueAMD64_OpMaskedSaturatedUnsignedSignedQuadDotProdAccumulateInt32x4(v *Value) bool {
+       v_3 := v.Args[3]
+       v_2 := v.Args[2]
+       v_1 := v.Args[1]
+       v_0 := v.Args[0]
+       b := v.Block
+       // match: (MaskedSaturatedUnsignedSignedQuadDotProdAccumulateInt32x4 x y z mask)
+       // result: (VPDPBUSDSMasked128 x y z (VPMOVVec32x4ToM <types.TypeMask> mask))
+       for {
+               x := v_0
+               y := v_1
+               z := v_2
+               mask := v_3
+               v.reset(OpAMD64VPDPBUSDSMasked128)
+               v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x4ToM, types.TypeMask)
+               v0.AddArg(mask)
+               v.AddArg4(x, y, z, v0)
+               return true
+       }
+}
+func rewriteValueAMD64_OpMaskedSaturatedUnsignedSignedQuadDotProdAccumulateInt32x8(v *Value) bool {
+       v_3 := v.Args[3]
+       v_2 := v.Args[2]
+       v_1 := v.Args[1]
+       v_0 := v.Args[0]
+       b := v.Block
+       // match: (MaskedSaturatedUnsignedSignedQuadDotProdAccumulateInt32x8 x y z mask)
+       // result: (VPDPBUSDSMasked256 x y z (VPMOVVec32x8ToM <types.TypeMask> mask))
+       for {
+               x := v_0
+               y := v_1
+               z := v_2
+               mask := v_3
+               v.reset(OpAMD64VPDPBUSDSMasked256)
+               v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x8ToM, types.TypeMask)
+               v0.AddArg(mask)
+               v.AddArg4(x, y, z, v0)
+               return true
+       }
+}
+func rewriteValueAMD64_OpMaskedSaturatedUnsignedSignedQuadDotProdAccumulateUint32x16(v *Value) bool {
+       v_3 := v.Args[3]
+       v_2 := v.Args[2]
+       v_1 := v.Args[1]
+       v_0 := v.Args[0]
+       b := v.Block
+       // match: (MaskedSaturatedUnsignedSignedQuadDotProdAccumulateUint32x16 x y z mask)
+       // result: (VPDPBUSDSMasked512 x y z (VPMOVVec32x16ToM <types.TypeMask> mask))
+       for {
+               x := v_0
+               y := v_1
+               z := v_2
+               mask := v_3
+               v.reset(OpAMD64VPDPBUSDSMasked512)
+               v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x16ToM, types.TypeMask)
+               v0.AddArg(mask)
+               v.AddArg4(x, y, z, v0)
+               return true
+       }
+}
+func rewriteValueAMD64_OpMaskedSaturatedUnsignedSignedQuadDotProdAccumulateUint32x4(v *Value) bool {
+       v_3 := v.Args[3]
+       v_2 := v.Args[2]
+       v_1 := v.Args[1]
+       v_0 := v.Args[0]
+       b := v.Block
+       // match: (MaskedSaturatedUnsignedSignedQuadDotProdAccumulateUint32x4 x y z mask)
+       // result: (VPDPBUSDSMasked128 x y z (VPMOVVec32x4ToM <types.TypeMask> mask))
+       for {
+               x := v_0
+               y := v_1
+               z := v_2
+               mask := v_3
+               v.reset(OpAMD64VPDPBUSDSMasked128)
+               v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x4ToM, types.TypeMask)
+               v0.AddArg(mask)
+               v.AddArg4(x, y, z, v0)
+               return true
+       }
+}
+func rewriteValueAMD64_OpMaskedSaturatedUnsignedSignedQuadDotProdAccumulateUint32x8(v *Value) bool {
+       v_3 := v.Args[3]
+       v_2 := v.Args[2]
+       v_1 := v.Args[1]
+       v_0 := v.Args[0]
+       b := v.Block
+       // match: (MaskedSaturatedUnsignedSignedQuadDotProdAccumulateUint32x8 x y z mask)
+       // result: (VPDPBUSDSMasked256 x y z (VPMOVVec32x8ToM <types.TypeMask> mask))
+       for {
+               x := v_0
+               y := v_1
+               z := v_2
+               mask := v_3
+               v.reset(OpAMD64VPDPBUSDSMasked256)
+               v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x8ToM, types.TypeMask)
+               v0.AddArg(mask)
+               v.AddArg4(x, y, z, v0)
+               return true
+       }
+}
+func rewriteValueAMD64_OpMaskedShiftAllLeftAndFillUpperFromInt16x16(v *Value) bool {
+       v_2 := v.Args[2]
+       v_1 := v.Args[1]
+       v_0 := v.Args[0]
+       b := v.Block
+       // match: (MaskedShiftAllLeftAndFillUpperFromInt16x16 [a] x y mask)
+       // result: (VPSHLDWMasked256 [a] x y (VPMOVVec16x16ToM <types.TypeMask> mask))
+       for {
+               a := auxIntToInt8(v.AuxInt)
+               x := v_0
+               y := v_1
+               mask := v_2
+               v.reset(OpAMD64VPSHLDWMasked256)
+               v.AuxInt = int8ToAuxInt(a)
+               v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x16ToM, types.TypeMask)
+               v0.AddArg(mask)
+               v.AddArg3(x, y, v0)
+               return true
+       }
+}
+func rewriteValueAMD64_OpMaskedShiftAllLeftAndFillUpperFromInt16x32(v *Value) bool {
+       v_2 := v.Args[2]
+       v_1 := v.Args[1]
+       v_0 := v.Args[0]
+       b := v.Block
+       // match: (MaskedShiftAllLeftAndFillUpperFromInt16x32 [a] x y mask)
+       // result: (VPSHLDWMasked512 [a] x y (VPMOVVec16x32ToM <types.TypeMask> mask))
+       for {
+               a := auxIntToInt8(v.AuxInt)
+               x := v_0
+               y := v_1
+               mask := v_2
+               v.reset(OpAMD64VPSHLDWMasked512)
+               v.AuxInt = int8ToAuxInt(a)
+               v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x32ToM, types.TypeMask)
+               v0.AddArg(mask)
+               v.AddArg3(x, y, v0)
+               return true
+       }
+}
+func rewriteValueAMD64_OpMaskedShiftAllLeftAndFillUpperFromInt16x8(v *Value) bool {
+       v_2 := v.Args[2]
+       v_1 := v.Args[1]
+       v_0 := v.Args[0]
+       b := v.Block
+       // match: (MaskedShiftAllLeftAndFillUpperFromInt16x8 [a] x y mask)
+       // result: (VPSHLDWMasked128 [a] x y (VPMOVVec16x8ToM <types.TypeMask> mask))
+       for {
+               a := auxIntToInt8(v.AuxInt)
+               x := v_0
+               y := v_1
+               mask := v_2
+               v.reset(OpAMD64VPSHLDWMasked128)
+               v.AuxInt = int8ToAuxInt(a)
+               v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x8ToM, types.TypeMask)
+               v0.AddArg(mask)
+               v.AddArg3(x, y, v0)
+               return true
+       }
+}
+func rewriteValueAMD64_OpMaskedShiftAllLeftAndFillUpperFromInt32x16(v *Value) bool {
+       v_2 := v.Args[2]
+       v_1 := v.Args[1]
+       v_0 := v.Args[0]
+       b := v.Block
+       // match: (MaskedShiftAllLeftAndFillUpperFromInt32x16 [a] x y mask)
+       // result: (VPSHLDDMasked512 [a] x y (VPMOVVec32x16ToM <types.TypeMask> mask))
+       for {
+               a := auxIntToInt8(v.AuxInt)
+               x := v_0
+               y := v_1
+               mask := v_2
+               v.reset(OpAMD64VPSHLDDMasked512)
+               v.AuxInt = int8ToAuxInt(a)
+               v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x16ToM, types.TypeMask)
+               v0.AddArg(mask)
+               v.AddArg3(x, y, v0)
+               return true
+       }
+}
+func rewriteValueAMD64_OpMaskedShiftAllLeftAndFillUpperFromInt32x4(v *Value) bool {
+       v_2 := v.Args[2]
+       v_1 := v.Args[1]
+       v_0 := v.Args[0]
+       b := v.Block
+       // match: (MaskedShiftAllLeftAndFillUpperFromInt32x4 [a] x y mask)
+       // result: (VPSHLDDMasked128 [a] x y (VPMOVVec32x4ToM <types.TypeMask> mask))
+       for {
+               a := auxIntToInt8(v.AuxInt)
+               x := v_0
+               y := v_1
+               mask := v_2
+               v.reset(OpAMD64VPSHLDDMasked128)
+               v.AuxInt = int8ToAuxInt(a)
+               v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x4ToM, types.TypeMask)
+               v0.AddArg(mask)
+               v.AddArg3(x, y, v0)
+               return true
+       }
+}
+func rewriteValueAMD64_OpMaskedShiftAllLeftAndFillUpperFromInt32x8(v *Value) bool {
+       v_2 := v.Args[2]
+       v_1 := v.Args[1]
+       v_0 := v.Args[0]
+       b := v.Block
+       // match: (MaskedShiftAllLeftAndFillUpperFromInt32x8 [a] x y mask)
+       // result: (VPSHLDDMasked256 [a] x y (VPMOVVec32x8ToM <types.TypeMask> mask))
+       for {
+               a := auxIntToInt8(v.AuxInt)
+               x := v_0
+               y := v_1
+               mask := v_2
+               v.reset(OpAMD64VPSHLDDMasked256)
+               v.AuxInt = int8ToAuxInt(a)
+               v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x8ToM, types.TypeMask)
+               v0.AddArg(mask)
+               v.AddArg3(x, y, v0)
+               return true
+       }
+}
+func rewriteValueAMD64_OpMaskedShiftAllLeftAndFillUpperFromInt64x2(v *Value) bool {
+       v_2 := v.Args[2]
+       v_1 := v.Args[1]
+       v_0 := v.Args[0]
+       b := v.Block
+       // match: (MaskedShiftAllLeftAndFillUpperFromInt64x2 [a] x y mask)
+       // result: (VPSHLDQMasked128 [a] x y (VPMOVVec64x2ToM <types.TypeMask> mask))
+       for {
+               a := auxIntToInt8(v.AuxInt)
+               x := v_0
+               y := v_1
+               mask := v_2
+               v.reset(OpAMD64VPSHLDQMasked128)
+               v.AuxInt = int8ToAuxInt(a)
+               v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x2ToM, types.TypeMask)
+               v0.AddArg(mask)
+               v.AddArg3(x, y, v0)
+               return true
+       }
+}
+func rewriteValueAMD64_OpMaskedShiftAllLeftAndFillUpperFromInt64x4(v *Value) bool {
+       v_2 := v.Args[2]
+       v_1 := v.Args[1]
+       v_0 := v.Args[0]
+       b := v.Block
+       // match: (MaskedShiftAllLeftAndFillUpperFromInt64x4 [a] x y mask)
+       // result: (VPSHLDQMasked256 [a] x y (VPMOVVec64x4ToM <types.TypeMask> mask))
+       for {
+               a := auxIntToInt8(v.AuxInt)
+               x := v_0
+               y := v_1
+               mask := v_2
+               v.reset(OpAMD64VPSHLDQMasked256)
+               v.AuxInt = int8ToAuxInt(a)
+               v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x4ToM, types.TypeMask)
+               v0.AddArg(mask)
+               v.AddArg3(x, y, v0)
+               return true
+       }
+}
+func rewriteValueAMD64_OpMaskedShiftAllLeftAndFillUpperFromInt64x8(v *Value) bool {
+       v_2 := v.Args[2]
+       v_1 := v.Args[1]
+       v_0 := v.Args[0]
+       b := v.Block
+       // match: (MaskedShiftAllLeftAndFillUpperFromInt64x8 [a] x y mask)
+       // result: (VPSHLDQMasked512 [a] x y (VPMOVVec64x8ToM <types.TypeMask> mask))
+       for {
+               a := auxIntToInt8(v.AuxInt)
+               x := v_0
+               y := v_1
+               mask := v_2
+               v.reset(OpAMD64VPSHLDQMasked512)
+               v.AuxInt = int8ToAuxInt(a)
+               v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x8ToM, types.TypeMask)
+               v0.AddArg(mask)
+               v.AddArg3(x, y, v0)
+               return true
+       }
+}
+func rewriteValueAMD64_OpMaskedShiftAllLeftAndFillUpperFromUint16x16(v *Value) bool {
+       v_2 := v.Args[2]
+       v_1 := v.Args[1]
+       v_0 := v.Args[0]
+       b := v.Block
+       // match: (MaskedShiftAllLeftAndFillUpperFromUint16x16 [a] x y mask)
+       // result: (VPSHLDWMasked256 [a] x y (VPMOVVec16x16ToM <types.TypeMask> mask))
+       for {
+               a := auxIntToInt8(v.AuxInt)
+               x := v_0
+               y := v_1
+               mask := v_2
+               v.reset(OpAMD64VPSHLDWMasked256)
+               v.AuxInt = int8ToAuxInt(a)
+               v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x16ToM, types.TypeMask)
+               v0.AddArg(mask)
+               v.AddArg3(x, y, v0)
+               return true
+       }
+}
+func rewriteValueAMD64_OpMaskedShiftAllLeftAndFillUpperFromUint16x32(v *Value) bool {
+       v_2 := v.Args[2]
+       v_1 := v.Args[1]
+       v_0 := v.Args[0]
+       b := v.Block
+       // match: (MaskedShiftAllLeftAndFillUpperFromUint16x32 [a] x y mask)
+       // result: (VPSHLDWMasked512 [a] x y (VPMOVVec16x32ToM <types.TypeMask> mask))
+       for {
+               a := auxIntToInt8(v.AuxInt)
+               x := v_0
+               y := v_1
+               mask := v_2
+               v.reset(OpAMD64VPSHLDWMasked512)
+               v.AuxInt = int8ToAuxInt(a)
+               v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x32ToM, types.TypeMask)
+               v0.AddArg(mask)
+               v.AddArg3(x, y, v0)
+               return true
+       }
+}
+func rewriteValueAMD64_OpMaskedShiftAllLeftAndFillUpperFromUint16x8(v *Value) bool {
+       v_2 := v.Args[2]
+       v_1 := v.Args[1]
+       v_0 := v.Args[0]
+       b := v.Block
+       // match: (MaskedShiftAllLeftAndFillUpperFromUint16x8 [a] x y mask)
+       // result: (VPSHLDWMasked128 [a] x y (VPMOVVec16x8ToM <types.TypeMask> mask))
+       for {
+               a := auxIntToInt8(v.AuxInt)
+               x := v_0
+               y := v_1
+               mask := v_2
+               v.reset(OpAMD64VPSHLDWMasked128)
+               v.AuxInt = int8ToAuxInt(a)
+               v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x8ToM, types.TypeMask)
+               v0.AddArg(mask)
+               v.AddArg3(x, y, v0)
+               return true
+       }
+}
+func rewriteValueAMD64_OpMaskedShiftAllLeftAndFillUpperFromUint32x16(v *Value) bool {
+       v_2 := v.Args[2]
+       v_1 := v.Args[1]
+       v_0 := v.Args[0]
+       b := v.Block
+       // match: (MaskedShiftAllLeftAndFillUpperFromUint32x16 [a] x y mask)
+       // result: (VPSHLDDMasked512 [a] x y (VPMOVVec32x16ToM <types.TypeMask> mask))
+       for {
+               a := auxIntToInt8(v.AuxInt)
+               x := v_0
+               y := v_1
+               mask := v_2
+               v.reset(OpAMD64VPSHLDDMasked512)
+               v.AuxInt = int8ToAuxInt(a)
+               v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x16ToM, types.TypeMask)
+               v0.AddArg(mask)
+               v.AddArg3(x, y, v0)
+               return true
+       }
+}
+func rewriteValueAMD64_OpMaskedShiftAllLeftAndFillUpperFromUint32x4(v *Value) bool {
+       v_2 := v.Args[2]
+       v_1 := v.Args[1]
+       v_0 := v.Args[0]
+       b := v.Block
+       // match: (MaskedShiftAllLeftAndFillUpperFromUint32x4 [a] x y mask)
+       // result: (VPSHLDDMasked128 [a] x y (VPMOVVec32x4ToM <types.TypeMask> mask))
+       for {
+               a := auxIntToInt8(v.AuxInt)
+               x := v_0
+               y := v_1
+               mask := v_2
+               v.reset(OpAMD64VPSHLDDMasked128)
+               v.AuxInt = int8ToAuxInt(a)
+               v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x4ToM, types.TypeMask)
+               v0.AddArg(mask)
+               v.AddArg3(x, y, v0)
+               return true
+       }
+}
+func rewriteValueAMD64_OpMaskedShiftAllLeftAndFillUpperFromUint32x8(v *Value) bool {
+       v_2 := v.Args[2]
+       v_1 := v.Args[1]
+       v_0 := v.Args[0]
+       b := v.Block
+       // match: (MaskedShiftAllLeftAndFillUpperFromUint32x8 [a] x y mask)
+       // result: (VPSHLDDMasked256 [a] x y (VPMOVVec32x8ToM <types.TypeMask> mask))
+       for {
+               a := auxIntToInt8(v.AuxInt)
+               x := v_0
+               y := v_1
+               mask := v_2
+               v.reset(OpAMD64VPSHLDDMasked256)
+               v.AuxInt = int8ToAuxInt(a)
+               v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x8ToM, types.TypeMask)
+               v0.AddArg(mask)
+               v.AddArg3(x, y, v0)
+               return true
+       }
+}
+func rewriteValueAMD64_OpMaskedShiftAllLeftAndFillUpperFromUint64x2(v *Value) bool {
+       v_2 := v.Args[2]
+       v_1 := v.Args[1]
+       v_0 := v.Args[0]
+       b := v.Block
+       // match: (MaskedShiftAllLeftAndFillUpperFromUint64x2 [a] x y mask)
+       // result: (VPSHLDQMasked128 [a] x y (VPMOVVec64x2ToM <types.TypeMask> mask))
+       for {
+               a := auxIntToInt8(v.AuxInt)
+               x := v_0
+               y := v_1
+               mask := v_2
+               v.reset(OpAMD64VPSHLDQMasked128)
+               v.AuxInt = int8ToAuxInt(a)
+               v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x2ToM, types.TypeMask)
+               v0.AddArg(mask)
+               v.AddArg3(x, y, v0)
+               return true
+       }
+}
+func rewriteValueAMD64_OpMaskedShiftAllLeftAndFillUpperFromUint64x4(v *Value) bool {
+       v_2 := v.Args[2]
+       v_1 := v.Args[1]
+       v_0 := v.Args[0]
+       b := v.Block
+       // match: (MaskedShiftAllLeftAndFillUpperFromUint64x4 [a] x y mask)
+       // result: (VPSHLDQMasked256 [a] x y (VPMOVVec64x4ToM <types.TypeMask> mask))
+       for {
+               a := auxIntToInt8(v.AuxInt)
+               x := v_0
+               y := v_1
+               mask := v_2
+               v.reset(OpAMD64VPSHLDQMasked256)
+               v.AuxInt = int8ToAuxInt(a)
+               v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x4ToM, types.TypeMask)
+               v0.AddArg(mask)
+               v.AddArg3(x, y, v0)
+               return true
+       }
+}
+func rewriteValueAMD64_OpMaskedShiftAllLeftAndFillUpperFromUint64x8(v *Value) bool {
+       v_2 := v.Args[2]
+       v_1 := v.Args[1]
+       v_0 := v.Args[0]
+       b := v.Block
+       // match: (MaskedShiftAllLeftAndFillUpperFromUint64x8 [a] x y mask)
+       // result: (VPSHLDQMasked512 [a] x y (VPMOVVec64x8ToM <types.TypeMask> mask))
+       for {
+               a := auxIntToInt8(v.AuxInt)
+               x := v_0
+               y := v_1
+               mask := v_2
+               v.reset(OpAMD64VPSHLDQMasked512)
+               v.AuxInt = int8ToAuxInt(a)
+               v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x8ToM, types.TypeMask)
+               v0.AddArg(mask)
+               v.AddArg3(x, y, v0)
+               return true
+       }
+}
+func rewriteValueAMD64_OpMaskedShiftAllLeftInt64x2(v *Value) bool {
+       v_2 := v.Args[2]
+       v_1 := v.Args[1]
+       v_0 := v.Args[0]
+       b := v.Block
+       // match: (MaskedShiftAllLeftInt64x2 x y mask)
+       // result: (VPSLLQMasked128 x y (VPMOVVec64x2ToM <types.TypeMask> mask))
+       for {
+               x := v_0
+               y := v_1
+               mask := v_2
+               v.reset(OpAMD64VPSLLQMasked128)
+               v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x2ToM, types.TypeMask)
+               v0.AddArg(mask)
+               v.AddArg3(x, y, v0)
+               return true
+       }
+}
+func rewriteValueAMD64_OpMaskedShiftAllLeftInt64x4(v *Value) bool {
+       v_2 := v.Args[2]
+       v_1 := v.Args[1]
+       v_0 := v.Args[0]
+       b := v.Block
+       // match: (MaskedShiftAllLeftInt64x4 x y mask)
+       // result: (VPSLLQMasked256 x y (VPMOVVec64x4ToM <types.TypeMask> mask))
+       for {
+               x := v_0
+               y := v_1
+               mask := v_2
+               v.reset(OpAMD64VPSLLQMasked256)
+               v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x4ToM, types.TypeMask)
+               v0.AddArg(mask)
+               v.AddArg3(x, y, v0)
+               return true
+       }
+}
+func rewriteValueAMD64_OpMaskedShiftAllLeftInt64x8(v *Value) bool {
+       v_2 := v.Args[2]
+       v_1 := v.Args[1]
+       v_0 := v.Args[0]
+       b := v.Block
+       // match: (MaskedShiftAllLeftInt64x8 x y mask)
+       // result: (VPSLLQMasked512 x y (VPMOVVec64x8ToM <types.TypeMask> mask))
+       for {
+               x := v_0
+               y := v_1
+               mask := v_2
+               v.reset(OpAMD64VPSLLQMasked512)
+               v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x8ToM, types.TypeMask)
+               v0.AddArg(mask)
+               v.AddArg3(x, y, v0)
+               return true
+       }
+}
+func rewriteValueAMD64_OpMaskedShiftAllLeftUint64x2(v *Value) bool {
+       v_2 := v.Args[2]
+       v_1 := v.Args[1]
+       v_0 := v.Args[0]
+       b := v.Block
+       // match: (MaskedShiftAllLeftUint64x2 x y mask)
+       // result: (VPSLLQMasked128 x y (VPMOVVec64x2ToM <types.TypeMask> mask))
+       for {
+               x := v_0
+               y := v_1
+               mask := v_2
+               v.reset(OpAMD64VPSLLQMasked128)
+               v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x2ToM, types.TypeMask)
+               v0.AddArg(mask)
+               v.AddArg3(x, y, v0)
+               return true
+       }
+}
+func rewriteValueAMD64_OpMaskedShiftAllLeftUint64x4(v *Value) bool {
+       v_2 := v.Args[2]
+       v_1 := v.Args[1]
+       v_0 := v.Args[0]
+       b := v.Block
+       // match: (MaskedShiftAllLeftUint64x4 x y mask)
+       // result: (VPSLLQMasked256 x y (VPMOVVec64x4ToM <types.TypeMask> mask))
+       for {
+               x := v_0
+               y := v_1
+               mask := v_2
+               v.reset(OpAMD64VPSLLQMasked256)
+               v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x4ToM, types.TypeMask)
+               v0.AddArg(mask)
+               v.AddArg3(x, y, v0)
+               return true
+       }
+}
+func rewriteValueAMD64_OpMaskedShiftAllLeftUint64x8(v *Value) bool {
+       v_2 := v.Args[2]
+       v_1 := v.Args[1]
+       v_0 := v.Args[0]
+       b := v.Block
+       // match: (MaskedShiftAllLeftUint64x8 x y mask)
+       // result: (VPSLLQMasked512 x y (VPMOVVec64x8ToM <types.TypeMask> mask))
+       for {
+               x := v_0
+               y := v_1
+               mask := v_2
+               v.reset(OpAMD64VPSLLQMasked512)
+               v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x8ToM, types.TypeMask)
+               v0.AddArg(mask)
+               v.AddArg3(x, y, v0)
+               return true
+       }
+}
+func rewriteValueAMD64_OpMaskedShiftAllRightAndFillUpperFromInt16x16(v *Value) bool {
+       v_2 := v.Args[2]
+       v_1 := v.Args[1]
+       v_0 := v.Args[0]
+       b := v.Block
+       // match: (MaskedShiftAllRightAndFillUpperFromInt16x16 [a] x y mask)
+       // result: (VPSHRDWMasked256 [a] x y (VPMOVVec16x16ToM <types.TypeMask> mask))
+       for {
+               a := auxIntToInt8(v.AuxInt)
+               x := v_0
+               y := v_1
+               mask := v_2
+               v.reset(OpAMD64VPSHRDWMasked256)
+               v.AuxInt = int8ToAuxInt(a)
+               v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x16ToM, types.TypeMask)
+               v0.AddArg(mask)
+               v.AddArg3(x, y, v0)
+               return true
+       }
+}
+func rewriteValueAMD64_OpMaskedShiftAllRightAndFillUpperFromInt16x32(v *Value) bool {
+       v_2 := v.Args[2]
+       v_1 := v.Args[1]
+       v_0 := v.Args[0]
+       b := v.Block
+       // match: (MaskedShiftAllRightAndFillUpperFromInt16x32 [a] x y mask)
+       // result: (VPSHRDWMasked512 [a] x y (VPMOVVec16x32ToM <types.TypeMask> mask))
+       for {
+               a := auxIntToInt8(v.AuxInt)
+               x := v_0
+               y := v_1
+               mask := v_2
+               v.reset(OpAMD64VPSHRDWMasked512)
+               v.AuxInt = int8ToAuxInt(a)
+               v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x32ToM, types.TypeMask)
+               v0.AddArg(mask)
+               v.AddArg3(x, y, v0)
+               return true
+       }
+}
+func rewriteValueAMD64_OpMaskedShiftAllRightAndFillUpperFromInt16x8(v *Value) bool {
+       v_2 := v.Args[2]
+       v_1 := v.Args[1]
+       v_0 := v.Args[0]
+       b := v.Block
+       // match: (MaskedShiftAllRightAndFillUpperFromInt16x8 [a] x y mask)
+       // result: (VPSHRDWMasked128 [a] x y (VPMOVVec16x8ToM <types.TypeMask> mask))
+       for {
+               a := auxIntToInt8(v.AuxInt)
+               x := v_0
+               y := v_1
+               mask := v_2
+               v.reset(OpAMD64VPSHRDWMasked128)
+               v.AuxInt = int8ToAuxInt(a)
+               v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x8ToM, types.TypeMask)
+               v0.AddArg(mask)
+               v.AddArg3(x, y, v0)
+               return true
+       }
+}
+func rewriteValueAMD64_OpMaskedShiftAllRightAndFillUpperFromInt32x16(v *Value) bool {
+       v_2 := v.Args[2]
+       v_1 := v.Args[1]
+       v_0 := v.Args[0]
+       b := v.Block
+       // match: (MaskedShiftAllRightAndFillUpperFromInt32x16 [a] x y mask)
+       // result: (VPSHRDDMasked512 [a] x y (VPMOVVec32x16ToM <types.TypeMask> mask))
+       for {
+               a := auxIntToInt8(v.AuxInt)
+               x := v_0
+               y := v_1
+               mask := v_2
+               v.reset(OpAMD64VPSHRDDMasked512)
+               v.AuxInt = int8ToAuxInt(a)
+               v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x16ToM, types.TypeMask)
+               v0.AddArg(mask)
+               v.AddArg3(x, y, v0)
+               return true
+       }
+}
+func rewriteValueAMD64_OpMaskedShiftAllRightAndFillUpperFromInt32x4(v *Value) bool {
+       v_2 := v.Args[2]
+       v_1 := v.Args[1]
+       v_0 := v.Args[0]
+       b := v.Block
+       // match: (MaskedShiftAllRightAndFillUpperFromInt32x4 [a] x y mask)
+       // result: (VPSHRDDMasked128 [a] x y (VPMOVVec32x4ToM <types.TypeMask> mask))
+       for {
+               a := auxIntToInt8(v.AuxInt)
+               x := v_0
+               y := v_1
+               mask := v_2
+               v.reset(OpAMD64VPSHRDDMasked128)
+               v.AuxInt = int8ToAuxInt(a)
+               v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x4ToM, types.TypeMask)
+               v0.AddArg(mask)
+               v.AddArg3(x, y, v0)
+               return true
+       }
+}
+func rewriteValueAMD64_OpMaskedShiftAllRightAndFillUpperFromInt32x8(v *Value) bool {
+       v_2 := v.Args[2]
+       v_1 := v.Args[1]
+       v_0 := v.Args[0]
+       b := v.Block
+       // match: (MaskedShiftAllRightAndFillUpperFromInt32x8 [a] x y mask)
+       // result: (VPSHRDDMasked256 [a] x y (VPMOVVec32x8ToM <types.TypeMask> mask))
+       for {
+               a := auxIntToInt8(v.AuxInt)
+               x := v_0
+               y := v_1
+               mask := v_2
+               v.reset(OpAMD64VPSHRDDMasked256)
+               v.AuxInt = int8ToAuxInt(a)
+               v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x8ToM, types.TypeMask)
+               v0.AddArg(mask)
+               v.AddArg3(x, y, v0)
+               return true
+       }
+}
+func rewriteValueAMD64_OpMaskedShiftAllRightAndFillUpperFromInt64x2(v *Value) bool {
+       v_2 := v.Args[2]
+       v_1 := v.Args[1]
+       v_0 := v.Args[0]
+       b := v.Block
+       // match: (MaskedShiftAllRightAndFillUpperFromInt64x2 [a] x y mask)
+       // result: (VPSHRDQMasked128 [a] x y (VPMOVVec64x2ToM <types.TypeMask> mask))
+       for {
+               a := auxIntToInt8(v.AuxInt)
+               x := v_0
+               y := v_1
+               mask := v_2
+               v.reset(OpAMD64VPSHRDQMasked128)
+               v.AuxInt = int8ToAuxInt(a)
+               v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x2ToM, types.TypeMask)
+               v0.AddArg(mask)
+               v.AddArg3(x, y, v0)
+               return true
+       }
+}
+func rewriteValueAMD64_OpMaskedShiftAllRightAndFillUpperFromInt64x4(v *Value) bool {
+       v_2 := v.Args[2]
+       v_1 := v.Args[1]
+       v_0 := v.Args[0]
+       b := v.Block
+       // match: (MaskedShiftAllRightAndFillUpperFromInt64x4 [a] x y mask)
+       // result: (VPSHRDQMasked256 [a] x y (VPMOVVec64x4ToM <types.TypeMask> mask))
+       for {
+               a := auxIntToInt8(v.AuxInt)
+               x := v_0
+               y := v_1
+               mask := v_2
+               v.reset(OpAMD64VPSHRDQMasked256)
+               v.AuxInt = int8ToAuxInt(a)
+               v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x4ToM, types.TypeMask)
+               v0.AddArg(mask)
+               v.AddArg3(x, y, v0)
+               return true
+       }
+}
+func rewriteValueAMD64_OpMaskedShiftAllRightAndFillUpperFromInt64x8(v *Value) bool {
+       v_2 := v.Args[2]
+       v_1 := v.Args[1]
+       v_0 := v.Args[0]
+       b := v.Block
+       // match: (MaskedShiftAllRightAndFillUpperFromInt64x8 [a] x y mask)
+       // result: (VPSHRDQMasked512 [a] x y (VPMOVVec64x8ToM <types.TypeMask> mask))
+       for {
+               a := auxIntToInt8(v.AuxInt)
+               x := v_0
+               y := v_1
+               mask := v_2
+               v.reset(OpAMD64VPSHRDQMasked512)
+               v.AuxInt = int8ToAuxInt(a)
+               v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x8ToM, types.TypeMask)
+               v0.AddArg(mask)
+               v.AddArg3(x, y, v0)
+               return true
+       }
+}
+func rewriteValueAMD64_OpMaskedShiftAllRightAndFillUpperFromUint16x16(v *Value) bool {
+       v_2 := v.Args[2]
+       v_1 := v.Args[1]
+       v_0 := v.Args[0]
+       b := v.Block
+       // match: (MaskedShiftAllRightAndFillUpperFromUint16x16 [a] x y mask)
+       // result: (VPSHRDWMasked256 [a] x y (VPMOVVec16x16ToM <types.TypeMask> mask))
+       for {
+               a := auxIntToInt8(v.AuxInt)
+               x := v_0
+               y := v_1
+               mask := v_2
+               v.reset(OpAMD64VPSHRDWMasked256)
+               v.AuxInt = int8ToAuxInt(a)
+               v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x16ToM, types.TypeMask)
+               v0.AddArg(mask)
+               v.AddArg3(x, y, v0)
+               return true
+       }
+}
+func rewriteValueAMD64_OpMaskedShiftAllRightAndFillUpperFromUint16x32(v *Value) bool {
+       v_2 := v.Args[2]
+       v_1 := v.Args[1]
+       v_0 := v.Args[0]
+       b := v.Block
+       // match: (MaskedShiftAllRightAndFillUpperFromUint16x32 [a] x y mask)
+       // result: (VPSHRDWMasked512 [a] x y (VPMOVVec16x32ToM <types.TypeMask> mask))
+       for {
+               a := auxIntToInt8(v.AuxInt)
+               x := v_0
+               y := v_1
+               mask := v_2
+               v.reset(OpAMD64VPSHRDWMasked512)
+               v.AuxInt = int8ToAuxInt(a)
+               v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x32ToM, types.TypeMask)
+               v0.AddArg(mask)
+               v.AddArg3(x, y, v0)
+               return true
+       }
+}
+func rewriteValueAMD64_OpMaskedShiftAllRightAndFillUpperFromUint16x8(v *Value) bool {
+       v_2 := v.Args[2]
+       v_1 := v.Args[1]
+       v_0 := v.Args[0]
+       b := v.Block
+       // match: (MaskedShiftAllRightAndFillUpperFromUint16x8 [a] x y mask)
+       // result: (VPSHRDWMasked128 [a] x y (VPMOVVec16x8ToM <types.TypeMask> mask))
+       for {
+               a := auxIntToInt8(v.AuxInt)
+               x := v_0
+               y := v_1
+               mask := v_2
+               v.reset(OpAMD64VPSHRDWMasked128)
+               v.AuxInt = int8ToAuxInt(a)
+               v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x8ToM, types.TypeMask)
+               v0.AddArg(mask)
+               v.AddArg3(x, y, v0)
+               return true
+       }
+}
+func rewriteValueAMD64_OpMaskedShiftAllRightAndFillUpperFromUint32x16(v *Value) bool {
+       v_2 := v.Args[2]
+       v_1 := v.Args[1]
+       v_0 := v.Args[0]
+       b := v.Block
+       // match: (MaskedShiftAllRightAndFillUpperFromUint32x16 [a] x y mask)
+       // result: (VPSHRDDMasked512 [a] x y (VPMOVVec32x16ToM <types.TypeMask> mask))
+       for {
+               a := auxIntToInt8(v.AuxInt)
+               x := v_0
+               y := v_1
+               mask := v_2
+               v.reset(OpAMD64VPSHRDDMasked512)
+               v.AuxInt = int8ToAuxInt(a)
+               v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x16ToM, types.TypeMask)
+               v0.AddArg(mask)
+               v.AddArg3(x, y, v0)
+               return true
+       }
+}
+func rewriteValueAMD64_OpMaskedShiftAllRightAndFillUpperFromUint32x4(v *Value) bool {
+       v_2 := v.Args[2]
+       v_1 := v.Args[1]
+       v_0 := v.Args[0]
+       b := v.Block
+       // match: (MaskedShiftAllRightAndFillUpperFromUint32x4 [a] x y mask)
+       // result: (VPSHRDDMasked128 [a] x y (VPMOVVec32x4ToM <types.TypeMask> mask))
+       for {
+               a := auxIntToInt8(v.AuxInt)
+               x := v_0
+               y := v_1
+               mask := v_2
+               v.reset(OpAMD64VPSHRDDMasked128)
+               v.AuxInt = int8ToAuxInt(a)
+               v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x4ToM, types.TypeMask)
+               v0.AddArg(mask)
+               v.AddArg3(x, y, v0)
+               return true
+       }
+}
+func rewriteValueAMD64_OpMaskedShiftAllRightAndFillUpperFromUint32x8(v *Value) bool {
+       v_2 := v.Args[2]
+       v_1 := v.Args[1]
+       v_0 := v.Args[0]
+       b := v.Block
+       // match: (MaskedShiftAllRightAndFillUpperFromUint32x8 [a] x y mask)
+       // result: (VPSHRDDMasked256 [a] x y (VPMOVVec32x8ToM <types.TypeMask> mask))
+       for {
+               a := auxIntToInt8(v.AuxInt)
+               x := v_0
+               y := v_1
+               mask := v_2
+               v.reset(OpAMD64VPSHRDDMasked256)
+               v.AuxInt = int8ToAuxInt(a)
+               v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x8ToM, types.TypeMask)
+               v0.AddArg(mask)
+               v.AddArg3(x, y, v0)
+               return true
+       }
+}
+func rewriteValueAMD64_OpMaskedShiftAllRightAndFillUpperFromUint64x2(v *Value) bool {
+       v_2 := v.Args[2]
+       v_1 := v.Args[1]
+       v_0 := v.Args[0]
+       b := v.Block
+       // match: (MaskedShiftAllRightAndFillUpperFromUint64x2 [a] x y mask)
+       // result: (VPSHRDQMasked128 [a] x y (VPMOVVec64x2ToM <types.TypeMask> mask))
+       for {
+               a := auxIntToInt8(v.AuxInt)
+               x := v_0
+               y := v_1
+               mask := v_2
+               v.reset(OpAMD64VPSHRDQMasked128)
+               v.AuxInt = int8ToAuxInt(a)
+               v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x2ToM, types.TypeMask)
+               v0.AddArg(mask)
+               v.AddArg3(x, y, v0)
+               return true
+       }
+}
+func rewriteValueAMD64_OpMaskedShiftAllRightAndFillUpperFromUint64x4(v *Value) bool {
+       v_2 := v.Args[2]
+       v_1 := v.Args[1]
+       v_0 := v.Args[0]
+       b := v.Block
+       // match: (MaskedShiftAllRightAndFillUpperFromUint64x4 [a] x y mask)
+       // result: (VPSHRDQMasked256 [a] x y (VPMOVVec64x4ToM <types.TypeMask> mask))
+       for {
+               a := auxIntToInt8(v.AuxInt)
+               x := v_0
+               y := v_1
+               mask := v_2
+               v.reset(OpAMD64VPSHRDQMasked256)
+               v.AuxInt = int8ToAuxInt(a)
+               v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x4ToM, types.TypeMask)
+               v0.AddArg(mask)
+               v.AddArg3(x, y, v0)
+               return true
+       }
+}
+func rewriteValueAMD64_OpMaskedShiftAllRightAndFillUpperFromUint64x8(v *Value) bool {
+       v_2 := v.Args[2]
+       v_1 := v.Args[1]
+       v_0 := v.Args[0]
+       b := v.Block
+       // match: (MaskedShiftAllRightAndFillUpperFromUint64x8 [a] x y mask)
+       // result: (VPSHRDQMasked512 [a] x y (VPMOVVec64x8ToM <types.TypeMask> mask))
+       for {
+               a := auxIntToInt8(v.AuxInt)
+               x := v_0
+               y := v_1
+               mask := v_2
+               v.reset(OpAMD64VPSHRDQMasked512)
+               v.AuxInt = int8ToAuxInt(a)
+               v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x8ToM, types.TypeMask)
+               v0.AddArg(mask)
+               v.AddArg3(x, y, v0)
+               return true
+       }
+}
+func rewriteValueAMD64_OpMaskedShiftAllRightInt64x2(v *Value) bool {
+       v_2 := v.Args[2]
+       v_1 := v.Args[1]
+       v_0 := v.Args[0]
+       b := v.Block
+       // match: (MaskedShiftAllRightInt64x2 x y mask)
+       // result: (VPSRLQMasked128 x y (VPMOVVec64x2ToM <types.TypeMask> mask))
+       for {
+               x := v_0
+               y := v_1
+               mask := v_2
+               v.reset(OpAMD64VPSRLQMasked128)
+               v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x2ToM, types.TypeMask)
+               v0.AddArg(mask)
+               v.AddArg3(x, y, v0)
+               return true
+       }
+}
+func rewriteValueAMD64_OpMaskedShiftAllRightInt64x4(v *Value) bool {
+       v_2 := v.Args[2]
+       v_1 := v.Args[1]
+       v_0 := v.Args[0]
+       b := v.Block
+       // match: (MaskedShiftAllRightInt64x4 x y mask)
+       // result: (VPSRLQMasked256 x y (VPMOVVec64x4ToM <types.TypeMask> mask))
+       for {
+               x := v_0
+               y := v_1
+               mask := v_2
+               v.reset(OpAMD64VPSRLQMasked256)
+               v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x4ToM, types.TypeMask)
+               v0.AddArg(mask)
+               v.AddArg3(x, y, v0)
+               return true
+       }
+}
+func rewriteValueAMD64_OpMaskedShiftAllRightInt64x8(v *Value) bool {
+       v_2 := v.Args[2]
+       v_1 := v.Args[1]
+       v_0 := v.Args[0]
+       b := v.Block
+       // match: (MaskedShiftAllRightInt64x8 x y mask)
+       // result: (VPSRLQMasked512 x y (VPMOVVec64x8ToM <types.TypeMask> mask))
+       for {
+               x := v_0
+               y := v_1
+               mask := v_2
+               v.reset(OpAMD64VPSRLQMasked512)
+               v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x8ToM, types.TypeMask)
+               v0.AddArg(mask)
+               v.AddArg3(x, y, v0)
+               return true
+       }
+}
+func rewriteValueAMD64_OpMaskedShiftAllRightSignExtendedInt64x2(v *Value) bool {
+       v_2 := v.Args[2]
+       v_1 := v.Args[1]
+       v_0 := v.Args[0]
+       b := v.Block
+       // match: (MaskedShiftAllRightSignExtendedInt64x2 x y mask)
+       // result: (VPSRAQMasked128 x y (VPMOVVec64x2ToM <types.TypeMask> mask))
+       for {
+               x := v_0
+               y := v_1
+               mask := v_2
+               v.reset(OpAMD64VPSRAQMasked128)
+               v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x2ToM, types.TypeMask)
+               v0.AddArg(mask)
+               v.AddArg3(x, y, v0)
+               return true
+       }
+}
+func rewriteValueAMD64_OpMaskedShiftAllRightSignExtendedInt64x4(v *Value) bool {
+       v_2 := v.Args[2]
+       v_1 := v.Args[1]
+       v_0 := v.Args[0]
+       b := v.Block
+       // match: (MaskedShiftAllRightSignExtendedInt64x4 x y mask)
+       // result: (VPSRAQMasked256 x y (VPMOVVec64x4ToM <types.TypeMask> mask))
+       for {
+               x := v_0
+               y := v_1
+               mask := v_2
+               v.reset(OpAMD64VPSRAQMasked256)
+               v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x4ToM, types.TypeMask)
+               v0.AddArg(mask)
+               v.AddArg3(x, y, v0)
+               return true
+       }
+}
+func rewriteValueAMD64_OpMaskedShiftAllRightSignExtendedInt64x8(v *Value) bool {
+       v_2 := v.Args[2]
+       v_1 := v.Args[1]
+       v_0 := v.Args[0]
+       b := v.Block
+       // match: (MaskedShiftAllRightSignExtendedInt64x8 x y mask)
+       // result: (VPSRAQMasked512 x y (VPMOVVec64x8ToM <types.TypeMask> mask))
+       for {
+               x := v_0
+               y := v_1
+               mask := v_2
+               v.reset(OpAMD64VPSRAQMasked512)
+               v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x8ToM, types.TypeMask)
+               v0.AddArg(mask)
+               v.AddArg3(x, y, v0)
+               return true
+       }
+}
+func rewriteValueAMD64_OpMaskedShiftAllRightUint64x2(v *Value) bool {
+       v_2 := v.Args[2]
+       v_1 := v.Args[1]
+       v_0 := v.Args[0]
+       b := v.Block
+       // match: (MaskedShiftAllRightUint64x2 x y mask)
+       // result: (VPSRLQMasked128 x y (VPMOVVec64x2ToM <types.TypeMask> mask))
+       for {
+               x := v_0
+               y := v_1
+               mask := v_2
+               v.reset(OpAMD64VPSRLQMasked128)
+               v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x2ToM, types.TypeMask)
+               v0.AddArg(mask)
+               v.AddArg3(x, y, v0)
+               return true
+       }
+}
+func rewriteValueAMD64_OpMaskedShiftAllRightUint64x4(v *Value) bool {
+       v_2 := v.Args[2]
+       v_1 := v.Args[1]
+       v_0 := v.Args[0]
+       b := v.Block
+       // match: (MaskedShiftAllRightUint64x4 x y mask)
+       // result: (VPSRLQMasked256 x y (VPMOVVec64x4ToM <types.TypeMask> mask))
+       for {
+               x := v_0
+               y := v_1
+               mask := v_2
+               v.reset(OpAMD64VPSRLQMasked256)
+               v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x4ToM, types.TypeMask)
+               v0.AddArg(mask)
+               v.AddArg3(x, y, v0)
+               return true
+       }
+}
+func rewriteValueAMD64_OpMaskedShiftAllRightUint64x8(v *Value) bool {
+       v_2 := v.Args[2]
+       v_1 := v.Args[1]
+       v_0 := v.Args[0]
+       b := v.Block
+       // match: (MaskedShiftAllRightUint64x8 x y mask)
+       // result: (VPSRLQMasked512 x y (VPMOVVec64x8ToM <types.TypeMask> mask))
+       for {
+               x := v_0
+               y := v_1
+               mask := v_2
+               v.reset(OpAMD64VPSRLQMasked512)
+               v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x8ToM, types.TypeMask)
+               v0.AddArg(mask)
+               v.AddArg3(x, y, v0)
+               return true
+       }
+}
+func rewriteValueAMD64_OpMaskedShiftLeftAndFillUpperFromInt16x16(v *Value) bool {
+       v_3 := v.Args[3]
+       v_2 := v.Args[2]
+       v_1 := v.Args[1]
+       v_0 := v.Args[0]
+       b := v.Block
+       // match: (MaskedShiftLeftAndFillUpperFromInt16x16 x y z mask)
+       // result: (VPSHLDVWMasked256 x y z (VPMOVVec16x16ToM <types.TypeMask> mask))
+       for {
+               x := v_0
+               y := v_1
+               z := v_2
+               mask := v_3
+               v.reset(OpAMD64VPSHLDVWMasked256)
+               v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x16ToM, types.TypeMask)
+               v0.AddArg(mask)
+               v.AddArg4(x, y, z, v0)
+               return true
+       }
+}
+func rewriteValueAMD64_OpMaskedShiftLeftAndFillUpperFromInt16x32(v *Value) bool {
+       v_3 := v.Args[3]
+       v_2 := v.Args[2]
+       v_1 := v.Args[1]
+       v_0 := v.Args[0]
+       b := v.Block
+       // match: (MaskedShiftLeftAndFillUpperFromInt16x32 x y z mask)
+       // result: (VPSHLDVWMasked512 x y z (VPMOVVec16x32ToM <types.TypeMask> mask))
+       for {
+               x := v_0
+               y := v_1
+               z := v_2
+               mask := v_3
+               v.reset(OpAMD64VPSHLDVWMasked512)
+               v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x32ToM, types.TypeMask)
+               v0.AddArg(mask)
+               v.AddArg4(x, y, z, v0)
+               return true
+       }
+}
+func rewriteValueAMD64_OpMaskedShiftLeftAndFillUpperFromInt16x8(v *Value) bool {
+       v_3 := v.Args[3]
+       v_2 := v.Args[2]
+       v_1 := v.Args[1]
+       v_0 := v.Args[0]
+       b := v.Block
+       // match: (MaskedShiftLeftAndFillUpperFromInt16x8 x y z mask)
+       // result: (VPSHLDVWMasked128 x y z (VPMOVVec16x8ToM <types.TypeMask> mask))
+       for {
+               x := v_0
+               y := v_1
+               z := v_2
+               mask := v_3
+               v.reset(OpAMD64VPSHLDVWMasked128)
+               v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x8ToM, types.TypeMask)
+               v0.AddArg(mask)
+               v.AddArg4(x, y, z, v0)
+               return true
+       }
+}
+func rewriteValueAMD64_OpMaskedShiftLeftAndFillUpperFromInt32x16(v *Value) bool {
+       v_3 := v.Args[3]
+       v_2 := v.Args[2]
+       v_1 := v.Args[1]
+       v_0 := v.Args[0]
+       b := v.Block
+       // match: (MaskedShiftLeftAndFillUpperFromInt32x16 x y z mask)
+       // result: (VPSHLDVDMasked512 x y z (VPMOVVec32x16ToM <types.TypeMask> mask))
+       for {
+               x := v_0
+               y := v_1
+               z := v_2
+               mask := v_3
+               v.reset(OpAMD64VPSHLDVDMasked512)
+               v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x16ToM, types.TypeMask)
+               v0.AddArg(mask)
+               v.AddArg4(x, y, z, v0)
+               return true
+       }
+}
+func rewriteValueAMD64_OpMaskedShiftLeftAndFillUpperFromInt32x4(v *Value) bool {
+       v_3 := v.Args[3]
+       v_2 := v.Args[2]
+       v_1 := v.Args[1]
+       v_0 := v.Args[0]
+       b := v.Block
+       // match: (MaskedShiftLeftAndFillUpperFromInt32x4 x y z mask)
+       // result: (VPSHLDVDMasked128 x y z (VPMOVVec32x4ToM <types.TypeMask> mask))
+       for {
+               x := v_0
+               y := v_1
+               z := v_2
+               mask := v_3
+               v.reset(OpAMD64VPSHLDVDMasked128)
+               v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x4ToM, types.TypeMask)
+               v0.AddArg(mask)
+               v.AddArg4(x, y, z, v0)
+               return true
+       }
+}
+func rewriteValueAMD64_OpMaskedShiftLeftAndFillUpperFromInt32x8(v *Value) bool {
+       v_3 := v.Args[3]
+       v_2 := v.Args[2]
+       v_1 := v.Args[1]
+       v_0 := v.Args[0]
+       b := v.Block
+       // match: (MaskedShiftLeftAndFillUpperFromInt32x8 x y z mask)
+       // result: (VPSHLDVDMasked256 x y z (VPMOVVec32x8ToM <types.TypeMask> mask))
+       for {
+               x := v_0
+               y := v_1
+               z := v_2
+               mask := v_3
+               v.reset(OpAMD64VPSHLDVDMasked256)
+               v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x8ToM, types.TypeMask)
+               v0.AddArg(mask)
+               v.AddArg4(x, y, z, v0)
+               return true
+       }
+}
+func rewriteValueAMD64_OpMaskedShiftLeftAndFillUpperFromInt64x2(v *Value) bool {
+       v_3 := v.Args[3]
+       v_2 := v.Args[2]
+       v_1 := v.Args[1]
+       v_0 := v.Args[0]
+       b := v.Block
+       // match: (MaskedShiftLeftAndFillUpperFromInt64x2 x y z mask)
+       // result: (VPSHLDVQMasked128 x y z (VPMOVVec64x2ToM <types.TypeMask> mask))
+       for {
+               x := v_0
+               y := v_1
+               z := v_2
+               mask := v_3
+               v.reset(OpAMD64VPSHLDVQMasked128)
+               v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x2ToM, types.TypeMask)
+               v0.AddArg(mask)
+               v.AddArg4(x, y, z, v0)
+               return true
+       }
+}
+func rewriteValueAMD64_OpMaskedShiftLeftAndFillUpperFromInt64x4(v *Value) bool {
+       v_3 := v.Args[3]
+       v_2 := v.Args[2]
+       v_1 := v.Args[1]
+       v_0 := v.Args[0]
+       b := v.Block
+       // match: (MaskedShiftLeftAndFillUpperFromInt64x4 x y z mask)
+       // result: (VPSHLDVQMasked256 x y z (VPMOVVec64x4ToM <types.TypeMask> mask))
+       for {
+               x := v_0
+               y := v_1
+               z := v_2
+               mask := v_3
+               v.reset(OpAMD64VPSHLDVQMasked256)
+               v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x4ToM, types.TypeMask)
+               v0.AddArg(mask)
+               v.AddArg4(x, y, z, v0)
+               return true
+       }
+}
+func rewriteValueAMD64_OpMaskedShiftLeftAndFillUpperFromInt64x8(v *Value) bool {
+       v_3 := v.Args[3]
+       v_2 := v.Args[2]
+       v_1 := v.Args[1]
+       v_0 := v.Args[0]
+       b := v.Block
+       // match: (MaskedShiftLeftAndFillUpperFromInt64x8 x y z mask)
+       // result: (VPSHLDVQMasked512 x y z (VPMOVVec64x8ToM <types.TypeMask> mask))
+       for {
+               x := v_0
+               y := v_1
+               z := v_2
+               mask := v_3
+               v.reset(OpAMD64VPSHLDVQMasked512)
+               v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x8ToM, types.TypeMask)
+               v0.AddArg(mask)
+               v.AddArg4(x, y, z, v0)
+               return true
+       }
+}
+func rewriteValueAMD64_OpMaskedShiftLeftAndFillUpperFromUint16x16(v *Value) bool {
+       v_3 := v.Args[3]
+       v_2 := v.Args[2]
+       v_1 := v.Args[1]
+       v_0 := v.Args[0]
+       b := v.Block
+       // match: (MaskedShiftLeftAndFillUpperFromUint16x16 x y z mask)
+       // result: (VPSHLDVWMasked256 x y z (VPMOVVec16x16ToM <types.TypeMask> mask))
+       for {
+               x := v_0
+               y := v_1
+               z := v_2
+               mask := v_3
+               v.reset(OpAMD64VPSHLDVWMasked256)
+               v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x16ToM, types.TypeMask)
+               v0.AddArg(mask)
+               v.AddArg4(x, y, z, v0)
+               return true
+       }
+}
+func rewriteValueAMD64_OpMaskedShiftLeftAndFillUpperFromUint16x32(v *Value) bool {
+       v_3 := v.Args[3]
+       v_2 := v.Args[2]
+       v_1 := v.Args[1]
+       v_0 := v.Args[0]
+       b := v.Block
+       // match: (MaskedShiftLeftAndFillUpperFromUint16x32 x y z mask)
+       // result: (VPSHLDVWMasked512 x y z (VPMOVVec16x32ToM <types.TypeMask> mask))
+       for {
+               x := v_0
+               y := v_1
+               z := v_2
+               mask := v_3
+               v.reset(OpAMD64VPSHLDVWMasked512)
+               v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x32ToM, types.TypeMask)
+               v0.AddArg(mask)
+               v.AddArg4(x, y, z, v0)
+               return true
+       }
+}
+func rewriteValueAMD64_OpMaskedShiftLeftAndFillUpperFromUint16x8(v *Value) bool {
+       v_3 := v.Args[3]
+       v_2 := v.Args[2]
+       v_1 := v.Args[1]
+       v_0 := v.Args[0]
+       b := v.Block
+       // match: (MaskedShiftLeftAndFillUpperFromUint16x8 x y z mask)
+       // result: (VPSHLDVWMasked128 x y z (VPMOVVec16x8ToM <types.TypeMask> mask))
+       for {
+               x := v_0
+               y := v_1
+               z := v_2
+               mask := v_3
+               v.reset(OpAMD64VPSHLDVWMasked128)
+               v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x8ToM, types.TypeMask)
+               v0.AddArg(mask)
+               v.AddArg4(x, y, z, v0)
+               return true
+       }
+}
+func rewriteValueAMD64_OpMaskedShiftLeftAndFillUpperFromUint32x16(v *Value) bool {
+       v_3 := v.Args[3]
+       v_2 := v.Args[2]
+       v_1 := v.Args[1]
+       v_0 := v.Args[0]
+       b := v.Block
+       // match: (MaskedShiftLeftAndFillUpperFromUint32x16 x y z mask)
+       // result: (VPSHLDVDMasked512 x y z (VPMOVVec32x16ToM <types.TypeMask> mask))
+       for {
+               x := v_0
+               y := v_1
+               z := v_2
+               mask := v_3
+               v.reset(OpAMD64VPSHLDVDMasked512)
+               v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x16ToM, types.TypeMask)
+               v0.AddArg(mask)
+               v.AddArg4(x, y, z, v0)
+               return true
+       }
+}
+func rewriteValueAMD64_OpMaskedShiftLeftAndFillUpperFromUint32x4(v *Value) bool {
+       v_3 := v.Args[3]
+       v_2 := v.Args[2]
+       v_1 := v.Args[1]
+       v_0 := v.Args[0]
+       b := v.Block
+       // match: (MaskedShiftLeftAndFillUpperFromUint32x4 x y z mask)
+       // result: (VPSHLDVDMasked128 x y z (VPMOVVec32x4ToM <types.TypeMask> mask))
+       for {
+               x := v_0
+               y := v_1
+               z := v_2
+               mask := v_3
+               v.reset(OpAMD64VPSHLDVDMasked128)
+               v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x4ToM, types.TypeMask)
+               v0.AddArg(mask)
+               v.AddArg4(x, y, z, v0)
+               return true
+       }
+}
+func rewriteValueAMD64_OpMaskedShiftLeftAndFillUpperFromUint32x8(v *Value) bool {
+       v_3 := v.Args[3]
+       v_2 := v.Args[2]
+       v_1 := v.Args[1]
+       v_0 := v.Args[0]
+       b := v.Block
+       // match: (MaskedShiftLeftAndFillUpperFromUint32x8 x y z mask)
+       // result: (VPSHLDVDMasked256 x y z (VPMOVVec32x8ToM <types.TypeMask> mask))
+       for {
+               x := v_0
+               y := v_1
+               z := v_2
+               mask := v_3
+               v.reset(OpAMD64VPSHLDVDMasked256)
+               v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x8ToM, types.TypeMask)
+               v0.AddArg(mask)
+               v.AddArg4(x, y, z, v0)
+               return true
+       }
+}
+func rewriteValueAMD64_OpMaskedShiftLeftAndFillUpperFromUint64x2(v *Value) bool {
+       v_3 := v.Args[3]
+       v_2 := v.Args[2]
+       v_1 := v.Args[1]
+       v_0 := v.Args[0]
+       b := v.Block
+       // match: (MaskedShiftLeftAndFillUpperFromUint64x2 x y z mask)
+       // result: (VPSHLDVQMasked128 x y z (VPMOVVec64x2ToM <types.TypeMask> mask))
+       for {
+               x := v_0
+               y := v_1
+               z := v_2
+               mask := v_3
+               v.reset(OpAMD64VPSHLDVQMasked128)
+               v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x2ToM, types.TypeMask)
+               v0.AddArg(mask)
+               v.AddArg4(x, y, z, v0)
+               return true
+       }
+}
+func rewriteValueAMD64_OpMaskedShiftLeftAndFillUpperFromUint64x4(v *Value) bool {
+       v_3 := v.Args[3]
+       v_2 := v.Args[2]
+       v_1 := v.Args[1]
+       v_0 := v.Args[0]
+       b := v.Block
+       // match: (MaskedShiftLeftAndFillUpperFromUint64x4 x y z mask)
+       // result: (VPSHLDVQMasked256 x y z (VPMOVVec64x4ToM <types.TypeMask> mask))
+       for {
+               x := v_0
+               y := v_1
+               z := v_2
+               mask := v_3
+               v.reset(OpAMD64VPSHLDVQMasked256)
+               v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x4ToM, types.TypeMask)
+               v0.AddArg(mask)
+               v.AddArg4(x, y, z, v0)
+               return true
+       }
+}
+func rewriteValueAMD64_OpMaskedShiftLeftAndFillUpperFromUint64x8(v *Value) bool {
+       v_3 := v.Args[3]
+       v_2 := v.Args[2]
+       v_1 := v.Args[1]
+       v_0 := v.Args[0]
+       b := v.Block
+       // match: (MaskedShiftLeftAndFillUpperFromUint64x8 x y z mask)
+       // result: (VPSHLDVQMasked512 x y z (VPMOVVec64x8ToM <types.TypeMask> mask))
+       for {
+               x := v_0
+               y := v_1
+               z := v_2
+               mask := v_3
+               v.reset(OpAMD64VPSHLDVQMasked512)
+               v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x8ToM, types.TypeMask)
+               v0.AddArg(mask)
+               v.AddArg4(x, y, z, v0)
+               return true
+       }
+}
+func rewriteValueAMD64_OpMaskedShiftLeftInt16x16(v *Value) bool {
+       v_2 := v.Args[2]
+       v_1 := v.Args[1]
+       v_0 := v.Args[0]
+       b := v.Block
+       // match: (MaskedShiftLeftInt16x16 x y mask)
+       // result: (VPSLLVWMasked256 x y (VPMOVVec16x16ToM <types.TypeMask> mask))
+       for {
+               x := v_0
+               y := v_1
+               mask := v_2
+               v.reset(OpAMD64VPSLLVWMasked256)
+               v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x16ToM, types.TypeMask)
+               v0.AddArg(mask)
+               v.AddArg3(x, y, v0)
+               return true
+       }
+}
+func rewriteValueAMD64_OpMaskedShiftLeftInt16x32(v *Value) bool {
+       v_2 := v.Args[2]
+       v_1 := v.Args[1]
+       v_0 := v.Args[0]
+       b := v.Block
+       // match: (MaskedShiftLeftInt16x32 x y mask)
+       // result: (VPSLLVWMasked512 x y (VPMOVVec16x32ToM <types.TypeMask> mask))
+       for {
+               x := v_0
+               y := v_1
+               mask := v_2
+               v.reset(OpAMD64VPSLLVWMasked512)
+               v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x32ToM, types.TypeMask)
+               v0.AddArg(mask)
+               v.AddArg3(x, y, v0)
+               return true
+       }
+}
+func rewriteValueAMD64_OpMaskedShiftLeftInt16x8(v *Value) bool {
+       v_2 := v.Args[2]
+       v_1 := v.Args[1]
+       v_0 := v.Args[0]
+       b := v.Block
+       // match: (MaskedShiftLeftInt16x8 x y mask)
+       // result: (VPSLLVWMasked128 x y (VPMOVVec16x8ToM <types.TypeMask> mask))
+       for {
+               x := v_0
+               y := v_1
+               mask := v_2
+               v.reset(OpAMD64VPSLLVWMasked128)
+               v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x8ToM, types.TypeMask)
+               v0.AddArg(mask)
+               v.AddArg3(x, y, v0)
+               return true
+       }
+}
+func rewriteValueAMD64_OpMaskedShiftLeftInt32x16(v *Value) bool {
+       v_2 := v.Args[2]
+       v_1 := v.Args[1]
+       v_0 := v.Args[0]
+       b := v.Block
+       // match: (MaskedShiftLeftInt32x16 x y mask)
+       // result: (VPSLLVDMasked512 x y (VPMOVVec32x16ToM <types.TypeMask> mask))
+       for {
+               x := v_0
+               y := v_1
+               mask := v_2
+               v.reset(OpAMD64VPSLLVDMasked512)
+               v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x16ToM, types.TypeMask)
+               v0.AddArg(mask)
+               v.AddArg3(x, y, v0)
+               return true
+       }
+}
+func rewriteValueAMD64_OpMaskedShiftLeftInt32x4(v *Value) bool {
+       v_2 := v.Args[2]
+       v_1 := v.Args[1]
+       v_0 := v.Args[0]
+       b := v.Block
+       // match: (MaskedShiftLeftInt32x4 x y mask)
+       // result: (VPSLLVDMasked128 x y (VPMOVVec32x4ToM <types.TypeMask> mask))
+       for {
+               x := v_0
+               y := v_1
+               mask := v_2
+               v.reset(OpAMD64VPSLLVDMasked128)
+               v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x4ToM, types.TypeMask)
+               v0.AddArg(mask)
+               v.AddArg3(x, y, v0)
+               return true
+       }
+}
+func rewriteValueAMD64_OpMaskedShiftLeftInt32x8(v *Value) bool {
+       v_2 := v.Args[2]
+       v_1 := v.Args[1]
+       v_0 := v.Args[0]
+       b := v.Block
+       // match: (MaskedShiftLeftInt32x8 x y mask)
+       // result: (VPSLLVDMasked256 x y (VPMOVVec32x8ToM <types.TypeMask> mask))
+       for {
+               x := v_0
+               y := v_1
+               mask := v_2
+               v.reset(OpAMD64VPSLLVDMasked256)
+               v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x8ToM, types.TypeMask)
+               v0.AddArg(mask)
+               v.AddArg3(x, y, v0)
+               return true
+       }
+}
+func rewriteValueAMD64_OpMaskedShiftLeftInt64x2(v *Value) bool {
+       v_2 := v.Args[2]
+       v_1 := v.Args[1]
+       v_0 := v.Args[0]
+       b := v.Block
+       // match: (MaskedShiftLeftInt64x2 x y mask)
+       // result: (VPSLLVQMasked128 x y (VPMOVVec64x2ToM <types.TypeMask> mask))
+       for {
+               x := v_0
+               y := v_1
+               mask := v_2
+               v.reset(OpAMD64VPSLLVQMasked128)
+               v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x2ToM, types.TypeMask)
+               v0.AddArg(mask)
+               v.AddArg3(x, y, v0)
+               return true
+       }
+}
+func rewriteValueAMD64_OpMaskedShiftLeftInt64x4(v *Value) bool {
+       v_2 := v.Args[2]
+       v_1 := v.Args[1]
+       v_0 := v.Args[0]
+       b := v.Block
+       // match: (MaskedShiftLeftInt64x4 x y mask)
+       // result: (VPSLLVQMasked256 x y (VPMOVVec64x4ToM <types.TypeMask> mask))
+       for {
+               x := v_0
+               y := v_1
+               mask := v_2
+               v.reset(OpAMD64VPSLLVQMasked256)
+               v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x4ToM, types.TypeMask)
+               v0.AddArg(mask)
+               v.AddArg3(x, y, v0)
+               return true
+       }
+}
+func rewriteValueAMD64_OpMaskedShiftLeftInt64x8(v *Value) bool {
+       v_2 := v.Args[2]
+       v_1 := v.Args[1]
+       v_0 := v.Args[0]
+       b := v.Block
+       // match: (MaskedShiftLeftInt64x8 x y mask)
+       // result: (VPSLLVQMasked512 x y (VPMOVVec64x8ToM <types.TypeMask> mask))
+       for {
+               x := v_0
+               y := v_1
+               mask := v_2
+               v.reset(OpAMD64VPSLLVQMasked512)
+               v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x8ToM, types.TypeMask)
+               v0.AddArg(mask)
+               v.AddArg3(x, y, v0)
+               return true
+       }
+}
+func rewriteValueAMD64_OpMaskedShiftLeftUint16x16(v *Value) bool {
+       v_2 := v.Args[2]
+       v_1 := v.Args[1]
+       v_0 := v.Args[0]
+       b := v.Block
+       // match: (MaskedShiftLeftUint16x16 x y mask)
+       // result: (VPSLLVWMasked256 x y (VPMOVVec16x16ToM <types.TypeMask> mask))
+       for {
+               x := v_0
+               y := v_1
+               mask := v_2
+               v.reset(OpAMD64VPSLLVWMasked256)
+               v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x16ToM, types.TypeMask)
+               v0.AddArg(mask)
+               v.AddArg3(x, y, v0)
+               return true
+       }
+}
+func rewriteValueAMD64_OpMaskedShiftLeftUint16x32(v *Value) bool {
+       v_2 := v.Args[2]
+       v_1 := v.Args[1]
+       v_0 := v.Args[0]
+       b := v.Block
+       // match: (MaskedShiftLeftUint16x32 x y mask)
+       // result: (VPSLLVWMasked512 x y (VPMOVVec16x32ToM <types.TypeMask> mask))
+       for {
+               x := v_0
+               y := v_1
+               mask := v_2
+               v.reset(OpAMD64VPSLLVWMasked512)
+               v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x32ToM, types.TypeMask)
+               v0.AddArg(mask)
+               v.AddArg3(x, y, v0)
+               return true
+       }
+}
+func rewriteValueAMD64_OpMaskedShiftLeftUint16x8(v *Value) bool {
+       v_2 := v.Args[2]
+       v_1 := v.Args[1]
+       v_0 := v.Args[0]
+       b := v.Block
+       // match: (MaskedShiftLeftUint16x8 x y mask)
+       // result: (VPSLLVWMasked128 x y (VPMOVVec16x8ToM <types.TypeMask> mask))
+       for {
+               x := v_0
+               y := v_1
+               mask := v_2
+               v.reset(OpAMD64VPSLLVWMasked128)
+               v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x8ToM, types.TypeMask)
+               v0.AddArg(mask)
+               v.AddArg3(x, y, v0)
+               return true
+       }
+}
+func rewriteValueAMD64_OpMaskedShiftLeftUint32x16(v *Value) bool {
+       v_2 := v.Args[2]
+       v_1 := v.Args[1]
+       v_0 := v.Args[0]
+       b := v.Block
+       // match: (MaskedShiftLeftUint32x16 x y mask)
+       // result: (VPSLLVDMasked512 x y (VPMOVVec32x16ToM <types.TypeMask> mask))
+       for {
+               x := v_0
+               y := v_1
+               mask := v_2
+               v.reset(OpAMD64VPSLLVDMasked512)
+               v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x16ToM, types.TypeMask)
+               v0.AddArg(mask)
+               v.AddArg3(x, y, v0)
+               return true
+       }
+}
+func rewriteValueAMD64_OpMaskedShiftLeftUint32x4(v *Value) bool {
+       v_2 := v.Args[2]
+       v_1 := v.Args[1]
+       v_0 := v.Args[0]
+       b := v.Block
+       // match: (MaskedShiftLeftUint32x4 x y mask)
+       // result: (VPSLLVDMasked128 x y (VPMOVVec32x4ToM <types.TypeMask> mask))
+       for {
+               x := v_0
+               y := v_1
+               mask := v_2
+               v.reset(OpAMD64VPSLLVDMasked128)
+               v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x4ToM, types.TypeMask)
+               v0.AddArg(mask)
+               v.AddArg3(x, y, v0)
+               return true
+       }
+}
+func rewriteValueAMD64_OpMaskedShiftLeftUint32x8(v *Value) bool {
+       v_2 := v.Args[2]
+       v_1 := v.Args[1]
+       v_0 := v.Args[0]
+       b := v.Block
+       // match: (MaskedShiftLeftUint32x8 x y mask)
+       // result: (VPSLLVDMasked256 x y (VPMOVVec32x8ToM <types.TypeMask> mask))
+       for {
+               x := v_0
+               y := v_1
+               mask := v_2
+               v.reset(OpAMD64VPSLLVDMasked256)
+               v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x8ToM, types.TypeMask)
+               v0.AddArg(mask)
+               v.AddArg3(x, y, v0)
+               return true
+       }
+}
+func rewriteValueAMD64_OpMaskedShiftLeftUint64x2(v *Value) bool {
+       v_2 := v.Args[2]
+       v_1 := v.Args[1]
+       v_0 := v.Args[0]
+       b := v.Block
+       // match: (MaskedShiftLeftUint64x2 x y mask)
+       // result: (VPSLLVQMasked128 x y (VPMOVVec64x2ToM <types.TypeMask> mask))
+       for {
+               x := v_0
+               y := v_1
+               mask := v_2
+               v.reset(OpAMD64VPSLLVQMasked128)
+               v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x2ToM, types.TypeMask)
+               v0.AddArg(mask)
+               v.AddArg3(x, y, v0)
+               return true
+       }
+}
+func rewriteValueAMD64_OpMaskedShiftLeftUint64x4(v *Value) bool {
+       v_2 := v.Args[2]
+       v_1 := v.Args[1]
+       v_0 := v.Args[0]
+       b := v.Block
+       // match: (MaskedShiftLeftUint64x4 x y mask)
+       // result: (VPSLLVQMasked256 x y (VPMOVVec64x4ToM <types.TypeMask> mask))
+       for {
+               x := v_0
+               y := v_1
+               mask := v_2
+               v.reset(OpAMD64VPSLLVQMasked256)
+               v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x4ToM, types.TypeMask)
+               v0.AddArg(mask)
+               v.AddArg3(x, y, v0)
+               return true
+       }
+}
+func rewriteValueAMD64_OpMaskedShiftLeftUint64x8(v *Value) bool {
+       v_2 := v.Args[2]
+       v_1 := v.Args[1]
+       v_0 := v.Args[0]
+       b := v.Block
+       // match: (MaskedShiftLeftUint64x8 x y mask)
+       // result: (VPSLLVQMasked512 x y (VPMOVVec64x8ToM <types.TypeMask> mask))
+       for {
+               x := v_0
+               y := v_1
+               mask := v_2
+               v.reset(OpAMD64VPSLLVQMasked512)
+               v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x8ToM, types.TypeMask)
+               v0.AddArg(mask)
+               v.AddArg3(x, y, v0)
+               return true
+       }
+}
+func rewriteValueAMD64_OpMaskedShiftRightAndFillUpperFromInt16x16(v *Value) bool {
+       v_3 := v.Args[3]
+       v_2 := v.Args[2]
+       v_1 := v.Args[1]
+       v_0 := v.Args[0]
+       b := v.Block
+       // match: (MaskedShiftRightAndFillUpperFromInt16x16 x y z mask)
+       // result: (VPSHRDVWMasked256 x y z (VPMOVVec16x16ToM <types.TypeMask> mask))
+       for {
+               x := v_0
+               y := v_1
+               z := v_2
+               mask := v_3
+               v.reset(OpAMD64VPSHRDVWMasked256)
+               v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x16ToM, types.TypeMask)
+               v0.AddArg(mask)
+               v.AddArg4(x, y, z, v0)
+               return true
+       }
+}
+func rewriteValueAMD64_OpMaskedShiftRightAndFillUpperFromInt16x32(v *Value) bool {
+       v_3 := v.Args[3]
+       v_2 := v.Args[2]
+       v_1 := v.Args[1]
+       v_0 := v.Args[0]
+       b := v.Block
+       // match: (MaskedShiftRightAndFillUpperFromInt16x32 x y z mask)
+       // result: (VPSHRDVWMasked512 x y z (VPMOVVec16x32ToM <types.TypeMask> mask))
+       for {
+               x := v_0
+               y := v_1
+               z := v_2
+               mask := v_3
+               v.reset(OpAMD64VPSHRDVWMasked512)
+               v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x32ToM, types.TypeMask)
+               v0.AddArg(mask)
+               v.AddArg4(x, y, z, v0)
+               return true
+       }
+}
+func rewriteValueAMD64_OpMaskedShiftRightAndFillUpperFromInt16x8(v *Value) bool {
+       v_3 := v.Args[3]
+       v_2 := v.Args[2]
+       v_1 := v.Args[1]
+       v_0 := v.Args[0]
+       b := v.Block
+       // match: (MaskedShiftRightAndFillUpperFromInt16x8 x y z mask)
+       // result: (VPSHRDVWMasked128 x y z (VPMOVVec16x8ToM <types.TypeMask> mask))
+       for {
+               x := v_0
+               y := v_1
+               z := v_2
+               mask := v_3
+               v.reset(OpAMD64VPSHRDVWMasked128)
+               v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x8ToM, types.TypeMask)
+               v0.AddArg(mask)
+               v.AddArg4(x, y, z, v0)
+               return true
+       }
+}
+func rewriteValueAMD64_OpMaskedShiftRightAndFillUpperFromInt32x16(v *Value) bool {
+       v_3 := v.Args[3]
+       v_2 := v.Args[2]
+       v_1 := v.Args[1]
+       v_0 := v.Args[0]
+       b := v.Block
+       // match: (MaskedShiftRightAndFillUpperFromInt32x16 x y z mask)
+       // result: (VPSHRDVDMasked512 x y z (VPMOVVec32x16ToM <types.TypeMask> mask))
+       for {
+               x := v_0
+               y := v_1
+               z := v_2
+               mask := v_3
+               v.reset(OpAMD64VPSHRDVDMasked512)
+               v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x16ToM, types.TypeMask)
+               v0.AddArg(mask)
+               v.AddArg4(x, y, z, v0)
+               return true
+       }
+}
+func rewriteValueAMD64_OpMaskedShiftRightAndFillUpperFromInt32x4(v *Value) bool {
+       v_3 := v.Args[3]
+       v_2 := v.Args[2]
+       v_1 := v.Args[1]
+       v_0 := v.Args[0]
+       b := v.Block
+       // match: (MaskedShiftRightAndFillUpperFromInt32x4 x y z mask)
+       // result: (VPSHRDVDMasked128 x y z (VPMOVVec32x4ToM <types.TypeMask> mask))
+       for {
+               x := v_0
+               y := v_1
+               z := v_2
+               mask := v_3
+               v.reset(OpAMD64VPSHRDVDMasked128)
+               v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x4ToM, types.TypeMask)
+               v0.AddArg(mask)
+               v.AddArg4(x, y, z, v0)
+               return true
+       }
+}
+func rewriteValueAMD64_OpMaskedShiftRightAndFillUpperFromInt32x8(v *Value) bool {
+       v_3 := v.Args[3]
+       v_2 := v.Args[2]
+       v_1 := v.Args[1]
+       v_0 := v.Args[0]
+       b := v.Block
+       // match: (MaskedShiftRightAndFillUpperFromInt32x8 x y z mask)
+       // result: (VPSHRDVDMasked256 x y z (VPMOVVec32x8ToM <types.TypeMask> mask))
+       for {
+               x := v_0
+               y := v_1
+               z := v_2
+               mask := v_3
+               v.reset(OpAMD64VPSHRDVDMasked256)
+               v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x8ToM, types.TypeMask)
+               v0.AddArg(mask)
+               v.AddArg4(x, y, z, v0)
+               return true
+       }
+}
+func rewriteValueAMD64_OpMaskedShiftRightAndFillUpperFromInt64x2(v *Value) bool {
+       v_3 := v.Args[3]
+       v_2 := v.Args[2]
+       v_1 := v.Args[1]
+       v_0 := v.Args[0]
+       b := v.Block
+       // match: (MaskedShiftRightAndFillUpperFromInt64x2 x y z mask)
+       // result: (VPSHRDVQMasked128 x y z (VPMOVVec64x2ToM <types.TypeMask> mask))
+       for {
+               x := v_0
+               y := v_1
+               z := v_2
+               mask := v_3
+               v.reset(OpAMD64VPSHRDVQMasked128)
+               v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x2ToM, types.TypeMask)
+               v0.AddArg(mask)
+               v.AddArg4(x, y, z, v0)
+               return true
+       }
+}
+func rewriteValueAMD64_OpMaskedShiftRightAndFillUpperFromInt64x4(v *Value) bool {
+       v_3 := v.Args[3]
+       v_2 := v.Args[2]
+       v_1 := v.Args[1]
+       v_0 := v.Args[0]
+       b := v.Block
+       // match: (MaskedShiftRightAndFillUpperFromInt64x4 x y z mask)
+       // result: (VPSHRDVQMasked256 x y z (VPMOVVec64x4ToM <types.TypeMask> mask))
+       for {
+               x := v_0
+               y := v_1
+               z := v_2
+               mask := v_3
+               v.reset(OpAMD64VPSHRDVQMasked256)
+               v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x4ToM, types.TypeMask)
+               v0.AddArg(mask)
+               v.AddArg4(x, y, z, v0)
+               return true
+       }
+}
+func rewriteValueAMD64_OpMaskedShiftRightAndFillUpperFromInt64x8(v *Value) bool {
+       v_3 := v.Args[3]
+       v_2 := v.Args[2]
+       v_1 := v.Args[1]
+       v_0 := v.Args[0]
+       b := v.Block
+       // match: (MaskedShiftRightAndFillUpperFromInt64x8 x y z mask)
+       // result: (VPSHRDVQMasked512 x y z (VPMOVVec64x8ToM <types.TypeMask> mask))
+       for {
+               x := v_0
+               y := v_1
+               z := v_2
+               mask := v_3
+               v.reset(OpAMD64VPSHRDVQMasked512)
+               v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x8ToM, types.TypeMask)
+               v0.AddArg(mask)
+               v.AddArg4(x, y, z, v0)
+               return true
+       }
+}
+func rewriteValueAMD64_OpMaskedShiftRightAndFillUpperFromUint16x16(v *Value) bool {
+       v_3 := v.Args[3]
+       v_2 := v.Args[2]
+       v_1 := v.Args[1]
+       v_0 := v.Args[0]
+       b := v.Block
+       // match: (MaskedShiftRightAndFillUpperFromUint16x16 x y z mask)
+       // result: (VPSHRDVWMasked256 x y z (VPMOVVec16x16ToM <types.TypeMask> mask))
+       for {
+               x := v_0
+               y := v_1
+               z := v_2
+               mask := v_3
+               v.reset(OpAMD64VPSHRDVWMasked256)
+               v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x16ToM, types.TypeMask)
+               v0.AddArg(mask)
+               v.AddArg4(x, y, z, v0)
+               return true
+       }
+}
+func rewriteValueAMD64_OpMaskedShiftRightAndFillUpperFromUint16x32(v *Value) bool {
+       v_3 := v.Args[3]
+       v_2 := v.Args[2]
+       v_1 := v.Args[1]
+       v_0 := v.Args[0]
+       b := v.Block
+       // match: (MaskedShiftRightAndFillUpperFromUint16x32 x y z mask)
+       // result: (VPSHRDVWMasked512 x y z (VPMOVVec16x32ToM <types.TypeMask> mask))
+       for {
+               x := v_0
+               y := v_1
+               z := v_2
+               mask := v_3
+               v.reset(OpAMD64VPSHRDVWMasked512)
+               v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x32ToM, types.TypeMask)
+               v0.AddArg(mask)
+               v.AddArg4(x, y, z, v0)
+               return true
+       }
+}
+func rewriteValueAMD64_OpMaskedShiftRightAndFillUpperFromUint16x8(v *Value) bool {
+       v_3 := v.Args[3]
+       v_2 := v.Args[2]
+       v_1 := v.Args[1]
+       v_0 := v.Args[0]
+       b := v.Block
+       // match: (MaskedShiftRightAndFillUpperFromUint16x8 x y z mask)
+       // result: (VPSHRDVWMasked128 x y z (VPMOVVec16x8ToM <types.TypeMask> mask))
+       for {
+               x := v_0
+               y := v_1
+               z := v_2
+               mask := v_3
+               v.reset(OpAMD64VPSHRDVWMasked128)
+               v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x8ToM, types.TypeMask)
+               v0.AddArg(mask)
+               v.AddArg4(x, y, z, v0)
+               return true
+       }
+}
+func rewriteValueAMD64_OpMaskedShiftRightAndFillUpperFromUint32x16(v *Value) bool {
+       v_3 := v.Args[3]
+       v_2 := v.Args[2]
+       v_1 := v.Args[1]
+       v_0 := v.Args[0]
+       b := v.Block
+       // match: (MaskedShiftRightAndFillUpperFromUint32x16 x y z mask)
+       // result: (VPSHRDVDMasked512 x y z (VPMOVVec32x16ToM <types.TypeMask> mask))
+       for {
+               x := v_0
+               y := v_1
+               z := v_2
+               mask := v_3
+               v.reset(OpAMD64VPSHRDVDMasked512)
+               v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x16ToM, types.TypeMask)
+               v0.AddArg(mask)
+               v.AddArg4(x, y, z, v0)
+               return true
+       }
+}
+func rewriteValueAMD64_OpMaskedShiftRightAndFillUpperFromUint32x4(v *Value) bool {
+       v_3 := v.Args[3]
+       v_2 := v.Args[2]
+       v_1 := v.Args[1]
+       v_0 := v.Args[0]
+       b := v.Block
+       // match: (MaskedShiftRightAndFillUpperFromUint32x4 x y z mask)
+       // result: (VPSHRDVDMasked128 x y z (VPMOVVec32x4ToM <types.TypeMask> mask))
+       for {
+               x := v_0
+               y := v_1
+               z := v_2
+               mask := v_3
+               v.reset(OpAMD64VPSHRDVDMasked128)
+               v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x4ToM, types.TypeMask)
+               v0.AddArg(mask)
+               v.AddArg4(x, y, z, v0)
+               return true
+       }
+}
+func rewriteValueAMD64_OpMaskedShiftRightAndFillUpperFromUint32x8(v *Value) bool {
+       v_3 := v.Args[3]
+       v_2 := v.Args[2]
+       v_1 := v.Args[1]
+       v_0 := v.Args[0]
+       b := v.Block
+       // match: (MaskedShiftRightAndFillUpperFromUint32x8 x y z mask)
+       // result: (VPSHRDVDMasked256 x y z (VPMOVVec32x8ToM <types.TypeMask> mask))
+       for {
+               x := v_0
+               y := v_1
+               z := v_2
+               mask := v_3
+               v.reset(OpAMD64VPSHRDVDMasked256)
+               v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x8ToM, types.TypeMask)
+               v0.AddArg(mask)
+               v.AddArg4(x, y, z, v0)
+               return true
+       }
+}
+func rewriteValueAMD64_OpMaskedShiftRightAndFillUpperFromUint64x2(v *Value) bool {
+       v_3 := v.Args[3]
+       v_2 := v.Args[2]
+       v_1 := v.Args[1]
+       v_0 := v.Args[0]
+       b := v.Block
+       // match: (MaskedShiftRightAndFillUpperFromUint64x2 x y z mask)
+       // result: (VPSHRDVQMasked128 x y z (VPMOVVec64x2ToM <types.TypeMask> mask))
+       for {
+               x := v_0
+               y := v_1
+               z := v_2
+               mask := v_3
+               v.reset(OpAMD64VPSHRDVQMasked128)
+               v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x2ToM, types.TypeMask)
+               v0.AddArg(mask)
+               v.AddArg4(x, y, z, v0)
+               return true
+       }
+}
+func rewriteValueAMD64_OpMaskedShiftRightAndFillUpperFromUint64x4(v *Value) bool {
+       v_3 := v.Args[3]
+       v_2 := v.Args[2]
+       v_1 := v.Args[1]
+       v_0 := v.Args[0]
+       b := v.Block
+       // match: (MaskedShiftRightAndFillUpperFromUint64x4 x y z mask)
+       // result: (VPSHRDVQMasked256 x y z (VPMOVVec64x4ToM <types.TypeMask> mask))
+       for {
+               x := v_0
+               y := v_1
+               z := v_2
+               mask := v_3
+               v.reset(OpAMD64VPSHRDVQMasked256)
+               v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x4ToM, types.TypeMask)
+               v0.AddArg(mask)
+               v.AddArg4(x, y, z, v0)
+               return true
+       }
+}
+func rewriteValueAMD64_OpMaskedShiftRightAndFillUpperFromUint64x8(v *Value) bool {
+       v_3 := v.Args[3]
+       v_2 := v.Args[2]
+       v_1 := v.Args[1]
+       v_0 := v.Args[0]
+       b := v.Block
+       // match: (MaskedShiftRightAndFillUpperFromUint64x8 x y z mask)
+       // result: (VPSHRDVQMasked512 x y z (VPMOVVec64x8ToM <types.TypeMask> mask))
+       for {
+               x := v_0
+               y := v_1
+               z := v_2
+               mask := v_3
+               v.reset(OpAMD64VPSHRDVQMasked512)
+               v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x8ToM, types.TypeMask)
+               v0.AddArg(mask)
+               v.AddArg4(x, y, z, v0)
+               return true
+       }
+}
+func rewriteValueAMD64_OpMaskedShiftRightInt16x16(v *Value) bool {
+       v_2 := v.Args[2]
+       v_1 := v.Args[1]
+       v_0 := v.Args[0]
+       b := v.Block
+       // match: (MaskedShiftRightInt16x16 x y mask)
+       // result: (VPSRLVWMasked256 x y (VPMOVVec16x16ToM <types.TypeMask> mask))
+       for {
+               x := v_0
+               y := v_1
+               mask := v_2
+               v.reset(OpAMD64VPSRLVWMasked256)
+               v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x16ToM, types.TypeMask)
+               v0.AddArg(mask)
+               v.AddArg3(x, y, v0)
+               return true
+       }
+}
+func rewriteValueAMD64_OpMaskedShiftRightInt16x32(v *Value) bool {
+       v_2 := v.Args[2]
+       v_1 := v.Args[1]
+       v_0 := v.Args[0]
+       b := v.Block
+       // match: (MaskedShiftRightInt16x32 x y mask)
+       // result: (VPSRLVWMasked512 x y (VPMOVVec16x32ToM <types.TypeMask> mask))
+       for {
+               x := v_0
+               y := v_1
+               mask := v_2
+               v.reset(OpAMD64VPSRLVWMasked512)
+               v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x32ToM, types.TypeMask)
+               v0.AddArg(mask)
+               v.AddArg3(x, y, v0)
+               return true
+       }
+}
+func rewriteValueAMD64_OpMaskedShiftRightInt16x8(v *Value) bool {
+       v_2 := v.Args[2]
+       v_1 := v.Args[1]
+       v_0 := v.Args[0]
+       b := v.Block
+       // match: (MaskedShiftRightInt16x8 x y mask)
+       // result: (VPSRLVWMasked128 x y (VPMOVVec16x8ToM <types.TypeMask> mask))
+       for {
+               x := v_0
+               y := v_1
+               mask := v_2
+               v.reset(OpAMD64VPSRLVWMasked128)
+               v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x8ToM, types.TypeMask)
+               v0.AddArg(mask)
+               v.AddArg3(x, y, v0)
+               return true
+       }
+}
+func rewriteValueAMD64_OpMaskedShiftRightInt32x16(v *Value) bool {
+       v_2 := v.Args[2]
+       v_1 := v.Args[1]
+       v_0 := v.Args[0]
+       b := v.Block
+       // match: (MaskedShiftRightInt32x16 x y mask)
+       // result: (VPSRLVDMasked512 x y (VPMOVVec32x16ToM <types.TypeMask> mask))
+       for {
+               x := v_0
+               y := v_1
+               mask := v_2
+               v.reset(OpAMD64VPSRLVDMasked512)
+               v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x16ToM, types.TypeMask)
+               v0.AddArg(mask)
+               v.AddArg3(x, y, v0)
+               return true
+       }
+}
+func rewriteValueAMD64_OpMaskedShiftRightInt32x4(v *Value) bool {
+       v_2 := v.Args[2]
+       v_1 := v.Args[1]
+       v_0 := v.Args[0]
+       b := v.Block
+       // match: (MaskedShiftRightInt32x4 x y mask)
+       // result: (VPSRLVDMasked128 x y (VPMOVVec32x4ToM <types.TypeMask> mask))
+       for {
+               x := v_0
+               y := v_1
+               mask := v_2
+               v.reset(OpAMD64VPSRLVDMasked128)
+               v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x4ToM, types.TypeMask)
+               v0.AddArg(mask)
+               v.AddArg3(x, y, v0)
+               return true
+       }
+}
+func rewriteValueAMD64_OpMaskedShiftRightInt32x8(v *Value) bool {
+       v_2 := v.Args[2]
+       v_1 := v.Args[1]
+       v_0 := v.Args[0]
+       b := v.Block
+       // match: (MaskedShiftRightInt32x8 x y mask)
+       // result: (VPSRLVDMasked256 x y (VPMOVVec32x8ToM <types.TypeMask> mask))
+       for {
+               x := v_0
+               y := v_1
+               mask := v_2
+               v.reset(OpAMD64VPSRLVDMasked256)
+               v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x8ToM, types.TypeMask)
+               v0.AddArg(mask)
+               v.AddArg3(x, y, v0)
+               return true
+       }
+}
+func rewriteValueAMD64_OpMaskedShiftRightInt64x2(v *Value) bool {
+       v_2 := v.Args[2]
+       v_1 := v.Args[1]
+       v_0 := v.Args[0]
+       b := v.Block
+       // match: (MaskedShiftRightInt64x2 x y mask)
+       // result: (VPSRLVQMasked128 x y (VPMOVVec64x2ToM <types.TypeMask> mask))
+       for {
+               x := v_0
+               y := v_1
+               mask := v_2
+               v.reset(OpAMD64VPSRLVQMasked128)
+               v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x2ToM, types.TypeMask)
+               v0.AddArg(mask)
+               v.AddArg3(x, y, v0)
+               return true
+       }
+}
+func rewriteValueAMD64_OpMaskedShiftRightInt64x4(v *Value) bool {
+       v_2 := v.Args[2]
+       v_1 := v.Args[1]
+       v_0 := v.Args[0]
+       b := v.Block
+       // match: (MaskedShiftRightInt64x4 x y mask)
+       // result: (VPSRLVQMasked256 x y (VPMOVVec64x4ToM <types.TypeMask> mask))
+       for {
+               x := v_0
+               y := v_1
+               mask := v_2
+               v.reset(OpAMD64VPSRLVQMasked256)
+               v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x4ToM, types.TypeMask)
+               v0.AddArg(mask)
+               v.AddArg3(x, y, v0)
+               return true
+       }
+}
+func rewriteValueAMD64_OpMaskedShiftRightInt64x8(v *Value) bool {
+       v_2 := v.Args[2]
+       v_1 := v.Args[1]
+       v_0 := v.Args[0]
+       b := v.Block
+       // match: (MaskedShiftRightInt64x8 x y mask)
+       // result: (VPSRLVQMasked512 x y (VPMOVVec64x8ToM <types.TypeMask> mask))
+       for {
+               x := v_0
+               y := v_1
+               mask := v_2
+               v.reset(OpAMD64VPSRLVQMasked512)
+               v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x8ToM, types.TypeMask)
+               v0.AddArg(mask)
+               v.AddArg3(x, y, v0)
+               return true
+       }
+}
+func rewriteValueAMD64_OpMaskedShiftRightSignExtendedInt16x16(v *Value) bool {
+       v_2 := v.Args[2]
+       v_1 := v.Args[1]
+       v_0 := v.Args[0]
+       b := v.Block
+       // match: (MaskedShiftRightSignExtendedInt16x16 x y mask)
+       // result: (VPSRAVWMasked256 x y (VPMOVVec16x16ToM <types.TypeMask> mask))
+       for {
+               x := v_0
+               y := v_1
+               mask := v_2
+               v.reset(OpAMD64VPSRAVWMasked256)
+               v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x16ToM, types.TypeMask)
+               v0.AddArg(mask)
+               v.AddArg3(x, y, v0)
+               return true
+       }
+}
+func rewriteValueAMD64_OpMaskedShiftRightSignExtendedInt16x32(v *Value) bool {
+       v_2 := v.Args[2]
+       v_1 := v.Args[1]
+       v_0 := v.Args[0]
+       b := v.Block
+       // match: (MaskedShiftRightSignExtendedInt16x32 x y mask)
+       // result: (VPSRAVWMasked512 x y (VPMOVVec16x32ToM <types.TypeMask> mask))
+       for {
+               x := v_0
+               y := v_1
+               mask := v_2
+               v.reset(OpAMD64VPSRAVWMasked512)
+               v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x32ToM, types.TypeMask)
+               v0.AddArg(mask)
+               v.AddArg3(x, y, v0)
+               return true
+       }
+}
+func rewriteValueAMD64_OpMaskedShiftRightSignExtendedInt16x8(v *Value) bool {
+       v_2 := v.Args[2]
+       v_1 := v.Args[1]
+       v_0 := v.Args[0]
+       b := v.Block
+       // match: (MaskedShiftRightSignExtendedInt16x8 x y mask)
+       // result: (VPSRAVWMasked128 x y (VPMOVVec16x8ToM <types.TypeMask> mask))
+       for {
+               x := v_0
+               y := v_1
+               mask := v_2
+               v.reset(OpAMD64VPSRAVWMasked128)
+               v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x8ToM, types.TypeMask)
+               v0.AddArg(mask)
+               v.AddArg3(x, y, v0)
+               return true
+       }
+}
+func rewriteValueAMD64_OpMaskedShiftRightSignExtendedInt32x16(v *Value) bool {
+       v_2 := v.Args[2]
+       v_1 := v.Args[1]
+       v_0 := v.Args[0]
+       b := v.Block
+       // match: (MaskedShiftRightSignExtendedInt32x16 x y mask)
+       // result: (VPSRAVDMasked512 x y (VPMOVVec32x16ToM <types.TypeMask> mask))
+       for {
+               x := v_0
+               y := v_1
+               mask := v_2
+               v.reset(OpAMD64VPSRAVDMasked512)
+               v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x16ToM, types.TypeMask)
+               v0.AddArg(mask)
+               v.AddArg3(x, y, v0)
+               return true
+       }
+}
+func rewriteValueAMD64_OpMaskedShiftRightSignExtendedInt32x4(v *Value) bool {
+       v_2 := v.Args[2]
+       v_1 := v.Args[1]
+       v_0 := v.Args[0]
+       b := v.Block
+       // match: (MaskedShiftRightSignExtendedInt32x4 x y mask)
+       // result: (VPSRAVDMasked128 x y (VPMOVVec32x4ToM <types.TypeMask> mask))
+       for {
+               x := v_0
+               y := v_1
+               mask := v_2
+               v.reset(OpAMD64VPSRAVDMasked128)
+               v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x4ToM, types.TypeMask)
+               v0.AddArg(mask)
+               v.AddArg3(x, y, v0)
                return true
        }
 }
-func rewriteValueAMD64_OpMaskedSaturatedUnsignedSignedQuadDotProdAccumulateInt32x8(v *Value) bool {
-       v_3 := v.Args[3]
+func rewriteValueAMD64_OpMaskedShiftRightSignExtendedInt32x8(v *Value) bool {
        v_2 := v.Args[2]
        v_1 := v.Args[1]
        v_0 := v.Args[0]
        b := v.Block
-       // match: (MaskedSaturatedUnsignedSignedQuadDotProdAccumulateInt32x8 x y z mask)
-       // result: (VPDPBUSDSMasked256 x y z (VPMOVVec32x8ToM <types.TypeMask> mask))
+       // match: (MaskedShiftRightSignExtendedInt32x8 x y mask)
+       // result: (VPSRAVDMasked256 x y (VPMOVVec32x8ToM <types.TypeMask> mask))
        for {
                x := v_0
                y := v_1
-               z := v_2
-               mask := v_3
-               v.reset(OpAMD64VPDPBUSDSMasked256)
+               mask := v_2
+               v.reset(OpAMD64VPSRAVDMasked256)
                v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x8ToM, types.TypeMask)
                v0.AddArg(mask)
-               v.AddArg4(x, y, z, v0)
+               v.AddArg3(x, y, v0)
                return true
        }
 }
-func rewriteValueAMD64_OpMaskedSaturatedUnsignedSignedQuadDotProdAccumulateUint32x16(v *Value) bool {
-       v_3 := v.Args[3]
+func rewriteValueAMD64_OpMaskedShiftRightSignExtendedInt64x2(v *Value) bool {
        v_2 := v.Args[2]
        v_1 := v.Args[1]
        v_0 := v.Args[0]
        b := v.Block
-       // match: (MaskedSaturatedUnsignedSignedQuadDotProdAccumulateUint32x16 x y z mask)
-       // result: (VPDPBUSDSMasked512 x y z (VPMOVVec32x16ToM <types.TypeMask> mask))
+       // match: (MaskedShiftRightSignExtendedInt64x2 x y mask)
+       // result: (VPSRAVQMasked128 x y (VPMOVVec64x2ToM <types.TypeMask> mask))
        for {
                x := v_0
                y := v_1
-               z := v_2
-               mask := v_3
-               v.reset(OpAMD64VPDPBUSDSMasked512)
+               mask := v_2
+               v.reset(OpAMD64VPSRAVQMasked128)
+               v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x2ToM, types.TypeMask)
+               v0.AddArg(mask)
+               v.AddArg3(x, y, v0)
+               return true
+       }
+}
+func rewriteValueAMD64_OpMaskedShiftRightSignExtendedInt64x4(v *Value) bool {
+       v_2 := v.Args[2]
+       v_1 := v.Args[1]
+       v_0 := v.Args[0]
+       b := v.Block
+       // match: (MaskedShiftRightSignExtendedInt64x4 x y mask)
+       // result: (VPSRAVQMasked256 x y (VPMOVVec64x4ToM <types.TypeMask> mask))
+       for {
+               x := v_0
+               y := v_1
+               mask := v_2
+               v.reset(OpAMD64VPSRAVQMasked256)
+               v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x4ToM, types.TypeMask)
+               v0.AddArg(mask)
+               v.AddArg3(x, y, v0)
+               return true
+       }
+}
+func rewriteValueAMD64_OpMaskedShiftRightSignExtendedInt64x8(v *Value) bool {
+       v_2 := v.Args[2]
+       v_1 := v.Args[1]
+       v_0 := v.Args[0]
+       b := v.Block
+       // match: (MaskedShiftRightSignExtendedInt64x8 x y mask)
+       // result: (VPSRAVQMasked512 x y (VPMOVVec64x8ToM <types.TypeMask> mask))
+       for {
+               x := v_0
+               y := v_1
+               mask := v_2
+               v.reset(OpAMD64VPSRAVQMasked512)
+               v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x8ToM, types.TypeMask)
+               v0.AddArg(mask)
+               v.AddArg3(x, y, v0)
+               return true
+       }
+}
+func rewriteValueAMD64_OpMaskedShiftRightSignExtendedUint16x16(v *Value) bool {
+       v_2 := v.Args[2]
+       v_1 := v.Args[1]
+       v_0 := v.Args[0]
+       b := v.Block
+       // match: (MaskedShiftRightSignExtendedUint16x16 x y mask)
+       // result: (VPSRAVWMasked256 x y (VPMOVVec16x16ToM <types.TypeMask> mask))
+       for {
+               x := v_0
+               y := v_1
+               mask := v_2
+               v.reset(OpAMD64VPSRAVWMasked256)
+               v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x16ToM, types.TypeMask)
+               v0.AddArg(mask)
+               v.AddArg3(x, y, v0)
+               return true
+       }
+}
+func rewriteValueAMD64_OpMaskedShiftRightSignExtendedUint16x32(v *Value) bool {
+       v_2 := v.Args[2]
+       v_1 := v.Args[1]
+       v_0 := v.Args[0]
+       b := v.Block
+       // match: (MaskedShiftRightSignExtendedUint16x32 x y mask)
+       // result: (VPSRAVWMasked512 x y (VPMOVVec16x32ToM <types.TypeMask> mask))
+       for {
+               x := v_0
+               y := v_1
+               mask := v_2
+               v.reset(OpAMD64VPSRAVWMasked512)
+               v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x32ToM, types.TypeMask)
+               v0.AddArg(mask)
+               v.AddArg3(x, y, v0)
+               return true
+       }
+}
+func rewriteValueAMD64_OpMaskedShiftRightSignExtendedUint16x8(v *Value) bool {
+       v_2 := v.Args[2]
+       v_1 := v.Args[1]
+       v_0 := v.Args[0]
+       b := v.Block
+       // match: (MaskedShiftRightSignExtendedUint16x8 x y mask)
+       // result: (VPSRAVWMasked128 x y (VPMOVVec16x8ToM <types.TypeMask> mask))
+       for {
+               x := v_0
+               y := v_1
+               mask := v_2
+               v.reset(OpAMD64VPSRAVWMasked128)
+               v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x8ToM, types.TypeMask)
+               v0.AddArg(mask)
+               v.AddArg3(x, y, v0)
+               return true
+       }
+}
+func rewriteValueAMD64_OpMaskedShiftRightSignExtendedUint32x16(v *Value) bool {
+       v_2 := v.Args[2]
+       v_1 := v.Args[1]
+       v_0 := v.Args[0]
+       b := v.Block
+       // match: (MaskedShiftRightSignExtendedUint32x16 x y mask)
+       // result: (VPSRAVDMasked512 x y (VPMOVVec32x16ToM <types.TypeMask> mask))
+       for {
+               x := v_0
+               y := v_1
+               mask := v_2
+               v.reset(OpAMD64VPSRAVDMasked512)
                v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x16ToM, types.TypeMask)
                v0.AddArg(mask)
-               v.AddArg4(x, y, z, v0)
+               v.AddArg3(x, y, v0)
                return true
        }
 }
-func rewriteValueAMD64_OpMaskedSaturatedUnsignedSignedQuadDotProdAccumulateUint32x4(v *Value) bool {
-       v_3 := v.Args[3]
+func rewriteValueAMD64_OpMaskedShiftRightSignExtendedUint32x4(v *Value) bool {
        v_2 := v.Args[2]
        v_1 := v.Args[1]
        v_0 := v.Args[0]
        b := v.Block
-       // match: (MaskedSaturatedUnsignedSignedQuadDotProdAccumulateUint32x4 x y z mask)
-       // result: (VPDPBUSDSMasked128 x y z (VPMOVVec32x4ToM <types.TypeMask> mask))
+       // match: (MaskedShiftRightSignExtendedUint32x4 x y mask)
+       // result: (VPSRAVDMasked128 x y (VPMOVVec32x4ToM <types.TypeMask> mask))
        for {
                x := v_0
                y := v_1
-               z := v_2
-               mask := v_3
-               v.reset(OpAMD64VPDPBUSDSMasked128)
+               mask := v_2
+               v.reset(OpAMD64VPSRAVDMasked128)
                v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x4ToM, types.TypeMask)
                v0.AddArg(mask)
-               v.AddArg4(x, y, z, v0)
+               v.AddArg3(x, y, v0)
                return true
        }
 }
-func rewriteValueAMD64_OpMaskedSaturatedUnsignedSignedQuadDotProdAccumulateUint32x8(v *Value) bool {
-       v_3 := v.Args[3]
+func rewriteValueAMD64_OpMaskedShiftRightSignExtendedUint32x8(v *Value) bool {
        v_2 := v.Args[2]
        v_1 := v.Args[1]
        v_0 := v.Args[0]
        b := v.Block
-       // match: (MaskedSaturatedUnsignedSignedQuadDotProdAccumulateUint32x8 x y z mask)
-       // result: (VPDPBUSDSMasked256 x y z (VPMOVVec32x8ToM <types.TypeMask> mask))
+       // match: (MaskedShiftRightSignExtendedUint32x8 x y mask)
+       // result: (VPSRAVDMasked256 x y (VPMOVVec32x8ToM <types.TypeMask> mask))
        for {
                x := v_0
                y := v_1
-               z := v_2
-               mask := v_3
-               v.reset(OpAMD64VPDPBUSDSMasked256)
+               mask := v_2
+               v.reset(OpAMD64VPSRAVDMasked256)
                v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x8ToM, types.TypeMask)
                v0.AddArg(mask)
-               v.AddArg4(x, y, z, v0)
+               v.AddArg3(x, y, v0)
+               return true
+       }
+}
+func rewriteValueAMD64_OpMaskedShiftRightSignExtendedUint64x2(v *Value) bool {
+       v_2 := v.Args[2]
+       v_1 := v.Args[1]
+       v_0 := v.Args[0]
+       b := v.Block
+       // match: (MaskedShiftRightSignExtendedUint64x2 x y mask)
+       // result: (VPSRAVQMasked128 x y (VPMOVVec64x2ToM <types.TypeMask> mask))
+       for {
+               x := v_0
+               y := v_1
+               mask := v_2
+               v.reset(OpAMD64VPSRAVQMasked128)
+               v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x2ToM, types.TypeMask)
+               v0.AddArg(mask)
+               v.AddArg3(x, y, v0)
+               return true
+       }
+}
+func rewriteValueAMD64_OpMaskedShiftRightSignExtendedUint64x4(v *Value) bool {
+       v_2 := v.Args[2]
+       v_1 := v.Args[1]
+       v_0 := v.Args[0]
+       b := v.Block
+       // match: (MaskedShiftRightSignExtendedUint64x4 x y mask)
+       // result: (VPSRAVQMasked256 x y (VPMOVVec64x4ToM <types.TypeMask> mask))
+       for {
+               x := v_0
+               y := v_1
+               mask := v_2
+               v.reset(OpAMD64VPSRAVQMasked256)
+               v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x4ToM, types.TypeMask)
+               v0.AddArg(mask)
+               v.AddArg3(x, y, v0)
+               return true
+       }
+}
+func rewriteValueAMD64_OpMaskedShiftRightSignExtendedUint64x8(v *Value) bool {
+       v_2 := v.Args[2]
+       v_1 := v.Args[1]
+       v_0 := v.Args[0]
+       b := v.Block
+       // match: (MaskedShiftRightSignExtendedUint64x8 x y mask)
+       // result: (VPSRAVQMasked512 x y (VPMOVVec64x8ToM <types.TypeMask> mask))
+       for {
+               x := v_0
+               y := v_1
+               mask := v_2
+               v.reset(OpAMD64VPSRAVQMasked512)
+               v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x8ToM, types.TypeMask)
+               v0.AddArg(mask)
+               v.AddArg3(x, y, v0)
+               return true
+       }
+}
+func rewriteValueAMD64_OpMaskedShiftRightUint16x16(v *Value) bool {
+       v_2 := v.Args[2]
+       v_1 := v.Args[1]
+       v_0 := v.Args[0]
+       b := v.Block
+       // match: (MaskedShiftRightUint16x16 x y mask)
+       // result: (VPSRLVWMasked256 x y (VPMOVVec16x16ToM <types.TypeMask> mask))
+       for {
+               x := v_0
+               y := v_1
+               mask := v_2
+               v.reset(OpAMD64VPSRLVWMasked256)
+               v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x16ToM, types.TypeMask)
+               v0.AddArg(mask)
+               v.AddArg3(x, y, v0)
+               return true
+       }
+}
+func rewriteValueAMD64_OpMaskedShiftRightUint16x32(v *Value) bool {
+       v_2 := v.Args[2]
+       v_1 := v.Args[1]
+       v_0 := v.Args[0]
+       b := v.Block
+       // match: (MaskedShiftRightUint16x32 x y mask)
+       // result: (VPSRLVWMasked512 x y (VPMOVVec16x32ToM <types.TypeMask> mask))
+       for {
+               x := v_0
+               y := v_1
+               mask := v_2
+               v.reset(OpAMD64VPSRLVWMasked512)
+               v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x32ToM, types.TypeMask)
+               v0.AddArg(mask)
+               v.AddArg3(x, y, v0)
+               return true
+       }
+}
+func rewriteValueAMD64_OpMaskedShiftRightUint16x8(v *Value) bool {
+       v_2 := v.Args[2]
+       v_1 := v.Args[1]
+       v_0 := v.Args[0]
+       b := v.Block
+       // match: (MaskedShiftRightUint16x8 x y mask)
+       // result: (VPSRLVWMasked128 x y (VPMOVVec16x8ToM <types.TypeMask> mask))
+       for {
+               x := v_0
+               y := v_1
+               mask := v_2
+               v.reset(OpAMD64VPSRLVWMasked128)
+               v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x8ToM, types.TypeMask)
+               v0.AddArg(mask)
+               v.AddArg3(x, y, v0)
+               return true
+       }
+}
+func rewriteValueAMD64_OpMaskedShiftRightUint32x16(v *Value) bool {
+       v_2 := v.Args[2]
+       v_1 := v.Args[1]
+       v_0 := v.Args[0]
+       b := v.Block
+       // match: (MaskedShiftRightUint32x16 x y mask)
+       // result: (VPSRLVDMasked512 x y (VPMOVVec32x16ToM <types.TypeMask> mask))
+       for {
+               x := v_0
+               y := v_1
+               mask := v_2
+               v.reset(OpAMD64VPSRLVDMasked512)
+               v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x16ToM, types.TypeMask)
+               v0.AddArg(mask)
+               v.AddArg3(x, y, v0)
+               return true
+       }
+}
+func rewriteValueAMD64_OpMaskedShiftRightUint32x4(v *Value) bool {
+       v_2 := v.Args[2]
+       v_1 := v.Args[1]
+       v_0 := v.Args[0]
+       b := v.Block
+       // match: (MaskedShiftRightUint32x4 x y mask)
+       // result: (VPSRLVDMasked128 x y (VPMOVVec32x4ToM <types.TypeMask> mask))
+       for {
+               x := v_0
+               y := v_1
+               mask := v_2
+               v.reset(OpAMD64VPSRLVDMasked128)
+               v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x4ToM, types.TypeMask)
+               v0.AddArg(mask)
+               v.AddArg3(x, y, v0)
+               return true
+       }
+}
+func rewriteValueAMD64_OpMaskedShiftRightUint32x8(v *Value) bool {
+       v_2 := v.Args[2]
+       v_1 := v.Args[1]
+       v_0 := v.Args[0]
+       b := v.Block
+       // match: (MaskedShiftRightUint32x8 x y mask)
+       // result: (VPSRLVDMasked256 x y (VPMOVVec32x8ToM <types.TypeMask> mask))
+       for {
+               x := v_0
+               y := v_1
+               mask := v_2
+               v.reset(OpAMD64VPSRLVDMasked256)
+               v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x8ToM, types.TypeMask)
+               v0.AddArg(mask)
+               v.AddArg3(x, y, v0)
+               return true
+       }
+}
+func rewriteValueAMD64_OpMaskedShiftRightUint64x2(v *Value) bool {
+       v_2 := v.Args[2]
+       v_1 := v.Args[1]
+       v_0 := v.Args[0]
+       b := v.Block
+       // match: (MaskedShiftRightUint64x2 x y mask)
+       // result: (VPSRLVQMasked128 x y (VPMOVVec64x2ToM <types.TypeMask> mask))
+       for {
+               x := v_0
+               y := v_1
+               mask := v_2
+               v.reset(OpAMD64VPSRLVQMasked128)
+               v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x2ToM, types.TypeMask)
+               v0.AddArg(mask)
+               v.AddArg3(x, y, v0)
+               return true
+       }
+}
+func rewriteValueAMD64_OpMaskedShiftRightUint64x4(v *Value) bool {
+       v_2 := v.Args[2]
+       v_1 := v.Args[1]
+       v_0 := v.Args[0]
+       b := v.Block
+       // match: (MaskedShiftRightUint64x4 x y mask)
+       // result: (VPSRLVQMasked256 x y (VPMOVVec64x4ToM <types.TypeMask> mask))
+       for {
+               x := v_0
+               y := v_1
+               mask := v_2
+               v.reset(OpAMD64VPSRLVQMasked256)
+               v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x4ToM, types.TypeMask)
+               v0.AddArg(mask)
+               v.AddArg3(x, y, v0)
+               return true
+       }
+}
+func rewriteValueAMD64_OpMaskedShiftRightUint64x8(v *Value) bool {
+       v_2 := v.Args[2]
+       v_1 := v.Args[1]
+       v_0 := v.Args[0]
+       b := v.Block
+       // match: (MaskedShiftRightUint64x8 x y mask)
+       // result: (VPSRLVQMasked512 x y (VPMOVVec64x8ToM <types.TypeMask> mask))
+       for {
+               x := v_0
+               y := v_1
+               mask := v_2
+               v.reset(OpAMD64VPSRLVQMasked512)
+               v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x8ToM, types.TypeMask)
+               v0.AddArg(mask)
+               v.AddArg3(x, y, v0)
                return true
        }
 }
@@ -47629,6 +52120,318 @@ func rewriteValueAMD64_OpPopCount8(v *Value) bool {
                return true
        }
 }
+func rewriteValueAMD64_OpRotateAllLeftInt32x16(v *Value) bool {
+       v_0 := v.Args[0]
+       // match: (RotateAllLeftInt32x16 [a] x)
+       // result: (VPROLD512 [a] x)
+       for {
+               a := auxIntToInt8(v.AuxInt)
+               x := v_0
+               v.reset(OpAMD64VPROLD512)
+               v.AuxInt = int8ToAuxInt(a)
+               v.AddArg(x)
+               return true
+       }
+}
+func rewriteValueAMD64_OpRotateAllLeftInt32x4(v *Value) bool {
+       v_0 := v.Args[0]
+       // match: (RotateAllLeftInt32x4 [a] x)
+       // result: (VPROLD128 [a] x)
+       for {
+               a := auxIntToInt8(v.AuxInt)
+               x := v_0
+               v.reset(OpAMD64VPROLD128)
+               v.AuxInt = int8ToAuxInt(a)
+               v.AddArg(x)
+               return true
+       }
+}
+func rewriteValueAMD64_OpRotateAllLeftInt32x8(v *Value) bool {
+       v_0 := v.Args[0]
+       // match: (RotateAllLeftInt32x8 [a] x)
+       // result: (VPROLD256 [a] x)
+       for {
+               a := auxIntToInt8(v.AuxInt)
+               x := v_0
+               v.reset(OpAMD64VPROLD256)
+               v.AuxInt = int8ToAuxInt(a)
+               v.AddArg(x)
+               return true
+       }
+}
+func rewriteValueAMD64_OpRotateAllLeftInt64x2(v *Value) bool {
+       v_0 := v.Args[0]
+       // match: (RotateAllLeftInt64x2 [a] x)
+       // result: (VPROLQ128 [a] x)
+       for {
+               a := auxIntToInt8(v.AuxInt)
+               x := v_0
+               v.reset(OpAMD64VPROLQ128)
+               v.AuxInt = int8ToAuxInt(a)
+               v.AddArg(x)
+               return true
+       }
+}
+func rewriteValueAMD64_OpRotateAllLeftInt64x4(v *Value) bool {
+       v_0 := v.Args[0]
+       // match: (RotateAllLeftInt64x4 [a] x)
+       // result: (VPROLQ256 [a] x)
+       for {
+               a := auxIntToInt8(v.AuxInt)
+               x := v_0
+               v.reset(OpAMD64VPROLQ256)
+               v.AuxInt = int8ToAuxInt(a)
+               v.AddArg(x)
+               return true
+       }
+}
+func rewriteValueAMD64_OpRotateAllLeftInt64x8(v *Value) bool {
+       v_0 := v.Args[0]
+       // match: (RotateAllLeftInt64x8 [a] x)
+       // result: (VPROLQ512 [a] x)
+       for {
+               a := auxIntToInt8(v.AuxInt)
+               x := v_0
+               v.reset(OpAMD64VPROLQ512)
+               v.AuxInt = int8ToAuxInt(a)
+               v.AddArg(x)
+               return true
+       }
+}
+func rewriteValueAMD64_OpRotateAllLeftUint32x16(v *Value) bool {
+       v_0 := v.Args[0]
+       // match: (RotateAllLeftUint32x16 [a] x)
+       // result: (VPROLD512 [a] x)
+       for {
+               a := auxIntToInt8(v.AuxInt)
+               x := v_0
+               v.reset(OpAMD64VPROLD512)
+               v.AuxInt = int8ToAuxInt(a)
+               v.AddArg(x)
+               return true
+       }
+}
+func rewriteValueAMD64_OpRotateAllLeftUint32x4(v *Value) bool {
+       v_0 := v.Args[0]
+       // match: (RotateAllLeftUint32x4 [a] x)
+       // result: (VPROLD128 [a] x)
+       for {
+               a := auxIntToInt8(v.AuxInt)
+               x := v_0
+               v.reset(OpAMD64VPROLD128)
+               v.AuxInt = int8ToAuxInt(a)
+               v.AddArg(x)
+               return true
+       }
+}
+func rewriteValueAMD64_OpRotateAllLeftUint32x8(v *Value) bool {
+       v_0 := v.Args[0]
+       // match: (RotateAllLeftUint32x8 [a] x)
+       // result: (VPROLD256 [a] x)
+       for {
+               a := auxIntToInt8(v.AuxInt)
+               x := v_0
+               v.reset(OpAMD64VPROLD256)
+               v.AuxInt = int8ToAuxInt(a)
+               v.AddArg(x)
+               return true
+       }
+}
+func rewriteValueAMD64_OpRotateAllLeftUint64x2(v *Value) bool {
+       v_0 := v.Args[0]
+       // match: (RotateAllLeftUint64x2 [a] x)
+       // result: (VPROLQ128 [a] x)
+       for {
+               a := auxIntToInt8(v.AuxInt)
+               x := v_0
+               v.reset(OpAMD64VPROLQ128)
+               v.AuxInt = int8ToAuxInt(a)
+               v.AddArg(x)
+               return true
+       }
+}
+func rewriteValueAMD64_OpRotateAllLeftUint64x4(v *Value) bool {
+       v_0 := v.Args[0]
+       // match: (RotateAllLeftUint64x4 [a] x)
+       // result: (VPROLQ256 [a] x)
+       for {
+               a := auxIntToInt8(v.AuxInt)
+               x := v_0
+               v.reset(OpAMD64VPROLQ256)
+               v.AuxInt = int8ToAuxInt(a)
+               v.AddArg(x)
+               return true
+       }
+}
+func rewriteValueAMD64_OpRotateAllLeftUint64x8(v *Value) bool {
+       v_0 := v.Args[0]
+       // match: (RotateAllLeftUint64x8 [a] x)
+       // result: (VPROLQ512 [a] x)
+       for {
+               a := auxIntToInt8(v.AuxInt)
+               x := v_0
+               v.reset(OpAMD64VPROLQ512)
+               v.AuxInt = int8ToAuxInt(a)
+               v.AddArg(x)
+               return true
+       }
+}
+func rewriteValueAMD64_OpRotateAllRightInt32x16(v *Value) bool {
+       v_0 := v.Args[0]
+       // match: (RotateAllRightInt32x16 [a] x)
+       // result: (VPRORD512 [a] x)
+       for {
+               a := auxIntToInt8(v.AuxInt)
+               x := v_0
+               v.reset(OpAMD64VPRORD512)
+               v.AuxInt = int8ToAuxInt(a)
+               v.AddArg(x)
+               return true
+       }
+}
+func rewriteValueAMD64_OpRotateAllRightInt32x4(v *Value) bool {
+       v_0 := v.Args[0]
+       // match: (RotateAllRightInt32x4 [a] x)
+       // result: (VPRORD128 [a] x)
+       for {
+               a := auxIntToInt8(v.AuxInt)
+               x := v_0
+               v.reset(OpAMD64VPRORD128)
+               v.AuxInt = int8ToAuxInt(a)
+               v.AddArg(x)
+               return true
+       }
+}
+func rewriteValueAMD64_OpRotateAllRightInt32x8(v *Value) bool {
+       v_0 := v.Args[0]
+       // match: (RotateAllRightInt32x8 [a] x)
+       // result: (VPRORD256 [a] x)
+       for {
+               a := auxIntToInt8(v.AuxInt)
+               x := v_0
+               v.reset(OpAMD64VPRORD256)
+               v.AuxInt = int8ToAuxInt(a)
+               v.AddArg(x)
+               return true
+       }
+}
+func rewriteValueAMD64_OpRotateAllRightInt64x2(v *Value) bool {
+       v_0 := v.Args[0]
+       // match: (RotateAllRightInt64x2 [a] x)
+       // result: (VPRORQ128 [a] x)
+       for {
+               a := auxIntToInt8(v.AuxInt)
+               x := v_0
+               v.reset(OpAMD64VPRORQ128)
+               v.AuxInt = int8ToAuxInt(a)
+               v.AddArg(x)
+               return true
+       }
+}
+func rewriteValueAMD64_OpRotateAllRightInt64x4(v *Value) bool {
+       v_0 := v.Args[0]
+       // match: (RotateAllRightInt64x4 [a] x)
+       // result: (VPRORQ256 [a] x)
+       for {
+               a := auxIntToInt8(v.AuxInt)
+               x := v_0
+               v.reset(OpAMD64VPRORQ256)
+               v.AuxInt = int8ToAuxInt(a)
+               v.AddArg(x)
+               return true
+       }
+}
+func rewriteValueAMD64_OpRotateAllRightInt64x8(v *Value) bool {
+       v_0 := v.Args[0]
+       // match: (RotateAllRightInt64x8 [a] x)
+       // result: (VPRORQ512 [a] x)
+       for {
+               a := auxIntToInt8(v.AuxInt)
+               x := v_0
+               v.reset(OpAMD64VPRORQ512)
+               v.AuxInt = int8ToAuxInt(a)
+               v.AddArg(x)
+               return true
+       }
+}
+func rewriteValueAMD64_OpRotateAllRightUint32x16(v *Value) bool {
+       v_0 := v.Args[0]
+       // match: (RotateAllRightUint32x16 [a] x)
+       // result: (VPRORD512 [a] x)
+       for {
+               a := auxIntToInt8(v.AuxInt)
+               x := v_0
+               v.reset(OpAMD64VPRORD512)
+               v.AuxInt = int8ToAuxInt(a)
+               v.AddArg(x)
+               return true
+       }
+}
+func rewriteValueAMD64_OpRotateAllRightUint32x4(v *Value) bool {
+       v_0 := v.Args[0]
+       // match: (RotateAllRightUint32x4 [a] x)
+       // result: (VPRORD128 [a] x)
+       for {
+               a := auxIntToInt8(v.AuxInt)
+               x := v_0
+               v.reset(OpAMD64VPRORD128)
+               v.AuxInt = int8ToAuxInt(a)
+               v.AddArg(x)
+               return true
+       }
+}
+func rewriteValueAMD64_OpRotateAllRightUint32x8(v *Value) bool {
+       v_0 := v.Args[0]
+       // match: (RotateAllRightUint32x8 [a] x)
+       // result: (VPRORD256 [a] x)
+       for {
+               a := auxIntToInt8(v.AuxInt)
+               x := v_0
+               v.reset(OpAMD64VPRORD256)
+               v.AuxInt = int8ToAuxInt(a)
+               v.AddArg(x)
+               return true
+       }
+}
+func rewriteValueAMD64_OpRotateAllRightUint64x2(v *Value) bool {
+       v_0 := v.Args[0]
+       // match: (RotateAllRightUint64x2 [a] x)
+       // result: (VPRORQ128 [a] x)
+       for {
+               a := auxIntToInt8(v.AuxInt)
+               x := v_0
+               v.reset(OpAMD64VPRORQ128)
+               v.AuxInt = int8ToAuxInt(a)
+               v.AddArg(x)
+               return true
+       }
+}
+func rewriteValueAMD64_OpRotateAllRightUint64x4(v *Value) bool {
+       v_0 := v.Args[0]
+       // match: (RotateAllRightUint64x4 [a] x)
+       // result: (VPRORQ256 [a] x)
+       for {
+               a := auxIntToInt8(v.AuxInt)
+               x := v_0
+               v.reset(OpAMD64VPRORQ256)
+               v.AuxInt = int8ToAuxInt(a)
+               v.AddArg(x)
+               return true
+       }
+}
+func rewriteValueAMD64_OpRotateAllRightUint64x8(v *Value) bool {
+       v_0 := v.Args[0]
+       // match: (RotateAllRightUint64x8 [a] x)
+       // result: (VPRORQ512 [a] x)
+       for {
+               a := auxIntToInt8(v.AuxInt)
+               x := v_0
+               v.reset(OpAMD64VPRORQ512)
+               v.AuxInt = int8ToAuxInt(a)
+               v.AddArg(x)
+               return true
+       }
+}
 func rewriteValueAMD64_OpRoundFloat32x4(v *Value) bool {
        v_0 := v.Args[0]
        // match: (RoundFloat32x4 x)
@@ -49718,6 +54521,546 @@ func rewriteValueAMD64_OpSetElemUint8x16(v *Value) bool {
                return true
        }
 }
+func rewriteValueAMD64_OpShiftAllLeftAndFillUpperFromInt16x16(v *Value) bool {
+       v_1 := v.Args[1]
+       v_0 := v.Args[0]
+       // match: (ShiftAllLeftAndFillUpperFromInt16x16 [a] x y)
+       // result: (VPSHLDW256 [a] x y)
+       for {
+               a := auxIntToInt8(v.AuxInt)
+               x := v_0
+               y := v_1
+               v.reset(OpAMD64VPSHLDW256)
+               v.AuxInt = int8ToAuxInt(a)
+               v.AddArg2(x, y)
+               return true
+       }
+}
+func rewriteValueAMD64_OpShiftAllLeftAndFillUpperFromInt16x32(v *Value) bool {
+       v_1 := v.Args[1]
+       v_0 := v.Args[0]
+       // match: (ShiftAllLeftAndFillUpperFromInt16x32 [a] x y)
+       // result: (VPSHLDW512 [a] x y)
+       for {
+               a := auxIntToInt8(v.AuxInt)
+               x := v_0
+               y := v_1
+               v.reset(OpAMD64VPSHLDW512)
+               v.AuxInt = int8ToAuxInt(a)
+               v.AddArg2(x, y)
+               return true
+       }
+}
+func rewriteValueAMD64_OpShiftAllLeftAndFillUpperFromInt16x8(v *Value) bool {
+       v_1 := v.Args[1]
+       v_0 := v.Args[0]
+       // match: (ShiftAllLeftAndFillUpperFromInt16x8 [a] x y)
+       // result: (VPSHLDW128 [a] x y)
+       for {
+               a := auxIntToInt8(v.AuxInt)
+               x := v_0
+               y := v_1
+               v.reset(OpAMD64VPSHLDW128)
+               v.AuxInt = int8ToAuxInt(a)
+               v.AddArg2(x, y)
+               return true
+       }
+}
+func rewriteValueAMD64_OpShiftAllLeftAndFillUpperFromInt32x16(v *Value) bool {
+       v_1 := v.Args[1]
+       v_0 := v.Args[0]
+       // match: (ShiftAllLeftAndFillUpperFromInt32x16 [a] x y)
+       // result: (VPSHLDD512 [a] x y)
+       for {
+               a := auxIntToInt8(v.AuxInt)
+               x := v_0
+               y := v_1
+               v.reset(OpAMD64VPSHLDD512)
+               v.AuxInt = int8ToAuxInt(a)
+               v.AddArg2(x, y)
+               return true
+       }
+}
+func rewriteValueAMD64_OpShiftAllLeftAndFillUpperFromInt32x4(v *Value) bool {
+       v_1 := v.Args[1]
+       v_0 := v.Args[0]
+       // match: (ShiftAllLeftAndFillUpperFromInt32x4 [a] x y)
+       // result: (VPSHLDD128 [a] x y)
+       for {
+               a := auxIntToInt8(v.AuxInt)
+               x := v_0
+               y := v_1
+               v.reset(OpAMD64VPSHLDD128)
+               v.AuxInt = int8ToAuxInt(a)
+               v.AddArg2(x, y)
+               return true
+       }
+}
+func rewriteValueAMD64_OpShiftAllLeftAndFillUpperFromInt32x8(v *Value) bool {
+       v_1 := v.Args[1]
+       v_0 := v.Args[0]
+       // match: (ShiftAllLeftAndFillUpperFromInt32x8 [a] x y)
+       // result: (VPSHLDD256 [a] x y)
+       for {
+               a := auxIntToInt8(v.AuxInt)
+               x := v_0
+               y := v_1
+               v.reset(OpAMD64VPSHLDD256)
+               v.AuxInt = int8ToAuxInt(a)
+               v.AddArg2(x, y)
+               return true
+       }
+}
+func rewriteValueAMD64_OpShiftAllLeftAndFillUpperFromInt64x2(v *Value) bool {
+       v_1 := v.Args[1]
+       v_0 := v.Args[0]
+       // match: (ShiftAllLeftAndFillUpperFromInt64x2 [a] x y)
+       // result: (VPSHLDQ128 [a] x y)
+       for {
+               a := auxIntToInt8(v.AuxInt)
+               x := v_0
+               y := v_1
+               v.reset(OpAMD64VPSHLDQ128)
+               v.AuxInt = int8ToAuxInt(a)
+               v.AddArg2(x, y)
+               return true
+       }
+}
+func rewriteValueAMD64_OpShiftAllLeftAndFillUpperFromInt64x4(v *Value) bool {
+       v_1 := v.Args[1]
+       v_0 := v.Args[0]
+       // match: (ShiftAllLeftAndFillUpperFromInt64x4 [a] x y)
+       // result: (VPSHLDQ256 [a] x y)
+       for {
+               a := auxIntToInt8(v.AuxInt)
+               x := v_0
+               y := v_1
+               v.reset(OpAMD64VPSHLDQ256)
+               v.AuxInt = int8ToAuxInt(a)
+               v.AddArg2(x, y)
+               return true
+       }
+}
+func rewriteValueAMD64_OpShiftAllLeftAndFillUpperFromInt64x8(v *Value) bool {
+       v_1 := v.Args[1]
+       v_0 := v.Args[0]
+       // match: (ShiftAllLeftAndFillUpperFromInt64x8 [a] x y)
+       // result: (VPSHLDQ512 [a] x y)
+       for {
+               a := auxIntToInt8(v.AuxInt)
+               x := v_0
+               y := v_1
+               v.reset(OpAMD64VPSHLDQ512)
+               v.AuxInt = int8ToAuxInt(a)
+               v.AddArg2(x, y)
+               return true
+       }
+}
+func rewriteValueAMD64_OpShiftAllLeftAndFillUpperFromUint16x16(v *Value) bool {
+       v_1 := v.Args[1]
+       v_0 := v.Args[0]
+       // match: (ShiftAllLeftAndFillUpperFromUint16x16 [a] x y)
+       // result: (VPSHLDW256 [a] x y)
+       for {
+               a := auxIntToInt8(v.AuxInt)
+               x := v_0
+               y := v_1
+               v.reset(OpAMD64VPSHLDW256)
+               v.AuxInt = int8ToAuxInt(a)
+               v.AddArg2(x, y)
+               return true
+       }
+}
+func rewriteValueAMD64_OpShiftAllLeftAndFillUpperFromUint16x32(v *Value) bool {
+       v_1 := v.Args[1]
+       v_0 := v.Args[0]
+       // match: (ShiftAllLeftAndFillUpperFromUint16x32 [a] x y)
+       // result: (VPSHLDW512 [a] x y)
+       for {
+               a := auxIntToInt8(v.AuxInt)
+               x := v_0
+               y := v_1
+               v.reset(OpAMD64VPSHLDW512)
+               v.AuxInt = int8ToAuxInt(a)
+               v.AddArg2(x, y)
+               return true
+       }
+}
+func rewriteValueAMD64_OpShiftAllLeftAndFillUpperFromUint16x8(v *Value) bool {
+       v_1 := v.Args[1]
+       v_0 := v.Args[0]
+       // match: (ShiftAllLeftAndFillUpperFromUint16x8 [a] x y)
+       // result: (VPSHLDW128 [a] x y)
+       for {
+               a := auxIntToInt8(v.AuxInt)
+               x := v_0
+               y := v_1
+               v.reset(OpAMD64VPSHLDW128)
+               v.AuxInt = int8ToAuxInt(a)
+               v.AddArg2(x, y)
+               return true
+       }
+}
+func rewriteValueAMD64_OpShiftAllLeftAndFillUpperFromUint32x16(v *Value) bool {
+       v_1 := v.Args[1]
+       v_0 := v.Args[0]
+       // match: (ShiftAllLeftAndFillUpperFromUint32x16 [a] x y)
+       // result: (VPSHLDD512 [a] x y)
+       for {
+               a := auxIntToInt8(v.AuxInt)
+               x := v_0
+               y := v_1
+               v.reset(OpAMD64VPSHLDD512)
+               v.AuxInt = int8ToAuxInt(a)
+               v.AddArg2(x, y)
+               return true
+       }
+}
+func rewriteValueAMD64_OpShiftAllLeftAndFillUpperFromUint32x4(v *Value) bool {
+       v_1 := v.Args[1]
+       v_0 := v.Args[0]
+       // match: (ShiftAllLeftAndFillUpperFromUint32x4 [a] x y)
+       // result: (VPSHLDD128 [a] x y)
+       for {
+               a := auxIntToInt8(v.AuxInt)
+               x := v_0
+               y := v_1
+               v.reset(OpAMD64VPSHLDD128)
+               v.AuxInt = int8ToAuxInt(a)
+               v.AddArg2(x, y)
+               return true
+       }
+}
+func rewriteValueAMD64_OpShiftAllLeftAndFillUpperFromUint32x8(v *Value) bool {
+       v_1 := v.Args[1]
+       v_0 := v.Args[0]
+       // match: (ShiftAllLeftAndFillUpperFromUint32x8 [a] x y)
+       // result: (VPSHLDD256 [a] x y)
+       for {
+               a := auxIntToInt8(v.AuxInt)
+               x := v_0
+               y := v_1
+               v.reset(OpAMD64VPSHLDD256)
+               v.AuxInt = int8ToAuxInt(a)
+               v.AddArg2(x, y)
+               return true
+       }
+}
+func rewriteValueAMD64_OpShiftAllLeftAndFillUpperFromUint64x2(v *Value) bool {
+       v_1 := v.Args[1]
+       v_0 := v.Args[0]
+       // match: (ShiftAllLeftAndFillUpperFromUint64x2 [a] x y)
+       // result: (VPSHLDQ128 [a] x y)
+       for {
+               a := auxIntToInt8(v.AuxInt)
+               x := v_0
+               y := v_1
+               v.reset(OpAMD64VPSHLDQ128)
+               v.AuxInt = int8ToAuxInt(a)
+               v.AddArg2(x, y)
+               return true
+       }
+}
+func rewriteValueAMD64_OpShiftAllLeftAndFillUpperFromUint64x4(v *Value) bool {
+       v_1 := v.Args[1]
+       v_0 := v.Args[0]
+       // match: (ShiftAllLeftAndFillUpperFromUint64x4 [a] x y)
+       // result: (VPSHLDQ256 [a] x y)
+       for {
+               a := auxIntToInt8(v.AuxInt)
+               x := v_0
+               y := v_1
+               v.reset(OpAMD64VPSHLDQ256)
+               v.AuxInt = int8ToAuxInt(a)
+               v.AddArg2(x, y)
+               return true
+       }
+}
+func rewriteValueAMD64_OpShiftAllLeftAndFillUpperFromUint64x8(v *Value) bool {
+       v_1 := v.Args[1]
+       v_0 := v.Args[0]
+       // match: (ShiftAllLeftAndFillUpperFromUint64x8 [a] x y)
+       // result: (VPSHLDQ512 [a] x y)
+       for {
+               a := auxIntToInt8(v.AuxInt)
+               x := v_0
+               y := v_1
+               v.reset(OpAMD64VPSHLDQ512)
+               v.AuxInt = int8ToAuxInt(a)
+               v.AddArg2(x, y)
+               return true
+       }
+}
+func rewriteValueAMD64_OpShiftAllRightAndFillUpperFromInt16x16(v *Value) bool {
+       v_1 := v.Args[1]
+       v_0 := v.Args[0]
+       // match: (ShiftAllRightAndFillUpperFromInt16x16 [a] x y)
+       // result: (VPSHRDW256 [a] x y)
+       for {
+               a := auxIntToInt8(v.AuxInt)
+               x := v_0
+               y := v_1
+               v.reset(OpAMD64VPSHRDW256)
+               v.AuxInt = int8ToAuxInt(a)
+               v.AddArg2(x, y)
+               return true
+       }
+}
+func rewriteValueAMD64_OpShiftAllRightAndFillUpperFromInt16x32(v *Value) bool {
+       v_1 := v.Args[1]
+       v_0 := v.Args[0]
+       // match: (ShiftAllRightAndFillUpperFromInt16x32 [a] x y)
+       // result: (VPSHRDW512 [a] x y)
+       for {
+               a := auxIntToInt8(v.AuxInt)
+               x := v_0
+               y := v_1
+               v.reset(OpAMD64VPSHRDW512)
+               v.AuxInt = int8ToAuxInt(a)
+               v.AddArg2(x, y)
+               return true
+       }
+}
+func rewriteValueAMD64_OpShiftAllRightAndFillUpperFromInt16x8(v *Value) bool {
+       v_1 := v.Args[1]
+       v_0 := v.Args[0]
+       // match: (ShiftAllRightAndFillUpperFromInt16x8 [a] x y)
+       // result: (VPSHRDW128 [a] x y)
+       for {
+               a := auxIntToInt8(v.AuxInt)
+               x := v_0
+               y := v_1
+               v.reset(OpAMD64VPSHRDW128)
+               v.AuxInt = int8ToAuxInt(a)
+               v.AddArg2(x, y)
+               return true
+       }
+}
+func rewriteValueAMD64_OpShiftAllRightAndFillUpperFromInt32x16(v *Value) bool {
+       v_1 := v.Args[1]
+       v_0 := v.Args[0]
+       // match: (ShiftAllRightAndFillUpperFromInt32x16 [a] x y)
+       // result: (VPSHRDD512 [a] x y)
+       for {
+               a := auxIntToInt8(v.AuxInt)
+               x := v_0
+               y := v_1
+               v.reset(OpAMD64VPSHRDD512)
+               v.AuxInt = int8ToAuxInt(a)
+               v.AddArg2(x, y)
+               return true
+       }
+}
+func rewriteValueAMD64_OpShiftAllRightAndFillUpperFromInt32x4(v *Value) bool {
+       v_1 := v.Args[1]
+       v_0 := v.Args[0]
+       // match: (ShiftAllRightAndFillUpperFromInt32x4 [a] x y)
+       // result: (VPSHRDD128 [a] x y)
+       for {
+               a := auxIntToInt8(v.AuxInt)
+               x := v_0
+               y := v_1
+               v.reset(OpAMD64VPSHRDD128)
+               v.AuxInt = int8ToAuxInt(a)
+               v.AddArg2(x, y)
+               return true
+       }
+}
+func rewriteValueAMD64_OpShiftAllRightAndFillUpperFromInt32x8(v *Value) bool {
+       v_1 := v.Args[1]
+       v_0 := v.Args[0]
+       // match: (ShiftAllRightAndFillUpperFromInt32x8 [a] x y)
+       // result: (VPSHRDD256 [a] x y)
+       for {
+               a := auxIntToInt8(v.AuxInt)
+               x := v_0
+               y := v_1
+               v.reset(OpAMD64VPSHRDD256)
+               v.AuxInt = int8ToAuxInt(a)
+               v.AddArg2(x, y)
+               return true
+       }
+}
+func rewriteValueAMD64_OpShiftAllRightAndFillUpperFromInt64x2(v *Value) bool {
+       v_1 := v.Args[1]
+       v_0 := v.Args[0]
+       // match: (ShiftAllRightAndFillUpperFromInt64x2 [a] x y)
+       // result: (VPSHRDQ128 [a] x y)
+       for {
+               a := auxIntToInt8(v.AuxInt)
+               x := v_0
+               y := v_1
+               v.reset(OpAMD64VPSHRDQ128)
+               v.AuxInt = int8ToAuxInt(a)
+               v.AddArg2(x, y)
+               return true
+       }
+}
+func rewriteValueAMD64_OpShiftAllRightAndFillUpperFromInt64x4(v *Value) bool {
+       v_1 := v.Args[1]
+       v_0 := v.Args[0]
+       // match: (ShiftAllRightAndFillUpperFromInt64x4 [a] x y)
+       // result: (VPSHRDQ256 [a] x y)
+       for {
+               a := auxIntToInt8(v.AuxInt)
+               x := v_0
+               y := v_1
+               v.reset(OpAMD64VPSHRDQ256)
+               v.AuxInt = int8ToAuxInt(a)
+               v.AddArg2(x, y)
+               return true
+       }
+}
+func rewriteValueAMD64_OpShiftAllRightAndFillUpperFromInt64x8(v *Value) bool {
+       v_1 := v.Args[1]
+       v_0 := v.Args[0]
+       // match: (ShiftAllRightAndFillUpperFromInt64x8 [a] x y)
+       // result: (VPSHRDQ512 [a] x y)
+       for {
+               a := auxIntToInt8(v.AuxInt)
+               x := v_0
+               y := v_1
+               v.reset(OpAMD64VPSHRDQ512)
+               v.AuxInt = int8ToAuxInt(a)
+               v.AddArg2(x, y)
+               return true
+       }
+}
+func rewriteValueAMD64_OpShiftAllRightAndFillUpperFromUint16x16(v *Value) bool {
+       v_1 := v.Args[1]
+       v_0 := v.Args[0]
+       // match: (ShiftAllRightAndFillUpperFromUint16x16 [a] x y)
+       // result: (VPSHRDW256 [a] x y)
+       for {
+               a := auxIntToInt8(v.AuxInt)
+               x := v_0
+               y := v_1
+               v.reset(OpAMD64VPSHRDW256)
+               v.AuxInt = int8ToAuxInt(a)
+               v.AddArg2(x, y)
+               return true
+       }
+}
+func rewriteValueAMD64_OpShiftAllRightAndFillUpperFromUint16x32(v *Value) bool {
+       v_1 := v.Args[1]
+       v_0 := v.Args[0]
+       // match: (ShiftAllRightAndFillUpperFromUint16x32 [a] x y)
+       // result: (VPSHRDW512 [a] x y)
+       for {
+               a := auxIntToInt8(v.AuxInt)
+               x := v_0
+               y := v_1
+               v.reset(OpAMD64VPSHRDW512)
+               v.AuxInt = int8ToAuxInt(a)
+               v.AddArg2(x, y)
+               return true
+       }
+}
+func rewriteValueAMD64_OpShiftAllRightAndFillUpperFromUint16x8(v *Value) bool {
+       v_1 := v.Args[1]
+       v_0 := v.Args[0]
+       // match: (ShiftAllRightAndFillUpperFromUint16x8 [a] x y)
+       // result: (VPSHRDW128 [a] x y)
+       for {
+               a := auxIntToInt8(v.AuxInt)
+               x := v_0
+               y := v_1
+               v.reset(OpAMD64VPSHRDW128)
+               v.AuxInt = int8ToAuxInt(a)
+               v.AddArg2(x, y)
+               return true
+       }
+}
+func rewriteValueAMD64_OpShiftAllRightAndFillUpperFromUint32x16(v *Value) bool {
+       v_1 := v.Args[1]
+       v_0 := v.Args[0]
+       // match: (ShiftAllRightAndFillUpperFromUint32x16 [a] x y)
+       // result: (VPSHRDD512 [a] x y)
+       for {
+               a := auxIntToInt8(v.AuxInt)
+               x := v_0
+               y := v_1
+               v.reset(OpAMD64VPSHRDD512)
+               v.AuxInt = int8ToAuxInt(a)
+               v.AddArg2(x, y)
+               return true
+       }
+}
+func rewriteValueAMD64_OpShiftAllRightAndFillUpperFromUint32x4(v *Value) bool {
+       v_1 := v.Args[1]
+       v_0 := v.Args[0]
+       // match: (ShiftAllRightAndFillUpperFromUint32x4 [a] x y)
+       // result: (VPSHRDD128 [a] x y)
+       for {
+               a := auxIntToInt8(v.AuxInt)
+               x := v_0
+               y := v_1
+               v.reset(OpAMD64VPSHRDD128)
+               v.AuxInt = int8ToAuxInt(a)
+               v.AddArg2(x, y)
+               return true
+       }
+}
+func rewriteValueAMD64_OpShiftAllRightAndFillUpperFromUint32x8(v *Value) bool {
+       v_1 := v.Args[1]
+       v_0 := v.Args[0]
+       // match: (ShiftAllRightAndFillUpperFromUint32x8 [a] x y)
+       // result: (VPSHRDD256 [a] x y)
+       for {
+               a := auxIntToInt8(v.AuxInt)
+               x := v_0
+               y := v_1
+               v.reset(OpAMD64VPSHRDD256)
+               v.AuxInt = int8ToAuxInt(a)
+               v.AddArg2(x, y)
+               return true
+       }
+}
+func rewriteValueAMD64_OpShiftAllRightAndFillUpperFromUint64x2(v *Value) bool {
+       v_1 := v.Args[1]
+       v_0 := v.Args[0]
+       // match: (ShiftAllRightAndFillUpperFromUint64x2 [a] x y)
+       // result: (VPSHRDQ128 [a] x y)
+       for {
+               a := auxIntToInt8(v.AuxInt)
+               x := v_0
+               y := v_1
+               v.reset(OpAMD64VPSHRDQ128)
+               v.AuxInt = int8ToAuxInt(a)
+               v.AddArg2(x, y)
+               return true
+       }
+}
+func rewriteValueAMD64_OpShiftAllRightAndFillUpperFromUint64x4(v *Value) bool {
+       v_1 := v.Args[1]
+       v_0 := v.Args[0]
+       // match: (ShiftAllRightAndFillUpperFromUint64x4 [a] x y)
+       // result: (VPSHRDQ256 [a] x y)
+       for {
+               a := auxIntToInt8(v.AuxInt)
+               x := v_0
+               y := v_1
+               v.reset(OpAMD64VPSHRDQ256)
+               v.AuxInt = int8ToAuxInt(a)
+               v.AddArg2(x, y)
+               return true
+       }
+}
+func rewriteValueAMD64_OpShiftAllRightAndFillUpperFromUint64x8(v *Value) bool {
+       v_1 := v.Args[1]
+       v_0 := v.Args[0]
+       // match: (ShiftAllRightAndFillUpperFromUint64x8 [a] x y)
+       // result: (VPSHRDQ512 [a] x y)
+       for {
+               a := auxIntToInt8(v.AuxInt)
+               x := v_0
+               y := v_1
+               v.reset(OpAMD64VPSHRDQ512)
+               v.AuxInt = int8ToAuxInt(a)
+               v.AddArg2(x, y)
+               return true
+       }
+}
 func rewriteValueAMD64_OpSlicemask(v *Value) bool {
        v_0 := v.Args[0]
        b := v.Block

diff --git a/src/cmd/compile/internal/ssagen/simdintrinsics.go b/src/cmd/compile/internal/ssagen/simdintrinsics.go
index 5d6ae7e3c06b7aad348cf60bab4e4bae72a5a797..d20c9392936be5bd99a79a5a0ac3fd668bee997b 100644 (file)
--- a/src/cmd/compile/internal/ssagen/simdintrinsics.go
+++ b/src/cmd/compile/internal/ssagen/simdintrinsics.go
@@ -915,6 +915,54 @@ func simdIntrinsics(addF func(pkg, fn string, b intrinsicBuilder, archFamilies .
        addF(simdPackage, "Uint64x2.MaskedPopCount", opLen2(ssa.OpMaskedPopCountUint64x2, types.TypeVec128), sys.AMD64)
        addF(simdPackage, "Uint64x4.MaskedPopCount", opLen2(ssa.OpMaskedPopCountUint64x4, types.TypeVec256), sys.AMD64)
        addF(simdPackage, "Uint64x8.MaskedPopCount", opLen2(ssa.OpMaskedPopCountUint64x8, types.TypeVec512), sys.AMD64)
+       addF(simdPackage, "Int32x4.MaskedRotateAllLeft", opLen2Imm8(ssa.OpMaskedRotateAllLeftInt32x4, types.TypeVec128, 0), sys.AMD64)
+       addF(simdPackage, "Int32x8.MaskedRotateAllLeft", opLen2Imm8(ssa.OpMaskedRotateAllLeftInt32x8, types.TypeVec256, 0), sys.AMD64)
+       addF(simdPackage, "Int32x16.MaskedRotateAllLeft", opLen2Imm8(ssa.OpMaskedRotateAllLeftInt32x16, types.TypeVec512, 0), sys.AMD64)
+       addF(simdPackage, "Int64x2.MaskedRotateAllLeft", opLen2Imm8(ssa.OpMaskedRotateAllLeftInt64x2, types.TypeVec128, 0), sys.AMD64)
+       addF(simdPackage, "Int64x4.MaskedRotateAllLeft", opLen2Imm8(ssa.OpMaskedRotateAllLeftInt64x4, types.TypeVec256, 0), sys.AMD64)
+       addF(simdPackage, "Int64x8.MaskedRotateAllLeft", opLen2Imm8(ssa.OpMaskedRotateAllLeftInt64x8, types.TypeVec512, 0), sys.AMD64)
+       addF(simdPackage, "Uint32x4.MaskedRotateAllLeft", opLen2Imm8(ssa.OpMaskedRotateAllLeftUint32x4, types.TypeVec128, 0), sys.AMD64)
+       addF(simdPackage, "Uint32x8.MaskedRotateAllLeft", opLen2Imm8(ssa.OpMaskedRotateAllLeftUint32x8, types.TypeVec256, 0), sys.AMD64)
+       addF(simdPackage, "Uint32x16.MaskedRotateAllLeft", opLen2Imm8(ssa.OpMaskedRotateAllLeftUint32x16, types.TypeVec512, 0), sys.AMD64)
+       addF(simdPackage, "Uint64x2.MaskedRotateAllLeft", opLen2Imm8(ssa.OpMaskedRotateAllLeftUint64x2, types.TypeVec128, 0), sys.AMD64)
+       addF(simdPackage, "Uint64x4.MaskedRotateAllLeft", opLen2Imm8(ssa.OpMaskedRotateAllLeftUint64x4, types.TypeVec256, 0), sys.AMD64)
+       addF(simdPackage, "Uint64x8.MaskedRotateAllLeft", opLen2Imm8(ssa.OpMaskedRotateAllLeftUint64x8, types.TypeVec512, 0), sys.AMD64)
+       addF(simdPackage, "Int32x4.MaskedRotateAllRight", opLen2Imm8(ssa.OpMaskedRotateAllRightInt32x4, types.TypeVec128, 0), sys.AMD64)
+       addF(simdPackage, "Int32x8.MaskedRotateAllRight", opLen2Imm8(ssa.OpMaskedRotateAllRightInt32x8, types.TypeVec256, 0), sys.AMD64)
+       addF(simdPackage, "Int32x16.MaskedRotateAllRight", opLen2Imm8(ssa.OpMaskedRotateAllRightInt32x16, types.TypeVec512, 0), sys.AMD64)
+       addF(simdPackage, "Int64x2.MaskedRotateAllRight", opLen2Imm8(ssa.OpMaskedRotateAllRightInt64x2, types.TypeVec128, 0), sys.AMD64)
+       addF(simdPackage, "Int64x4.MaskedRotateAllRight", opLen2Imm8(ssa.OpMaskedRotateAllRightInt64x4, types.TypeVec256, 0), sys.AMD64)
+       addF(simdPackage, "Int64x8.MaskedRotateAllRight", opLen2Imm8(ssa.OpMaskedRotateAllRightInt64x8, types.TypeVec512, 0), sys.AMD64)
+       addF(simdPackage, "Uint32x4.MaskedRotateAllRight", opLen2Imm8(ssa.OpMaskedRotateAllRightUint32x4, types.TypeVec128, 0), sys.AMD64)
+       addF(simdPackage, "Uint32x8.MaskedRotateAllRight", opLen2Imm8(ssa.OpMaskedRotateAllRightUint32x8, types.TypeVec256, 0), sys.AMD64)
+       addF(simdPackage, "Uint32x16.MaskedRotateAllRight", opLen2Imm8(ssa.OpMaskedRotateAllRightUint32x16, types.TypeVec512, 0), sys.AMD64)
+       addF(simdPackage, "Uint64x2.MaskedRotateAllRight", opLen2Imm8(ssa.OpMaskedRotateAllRightUint64x2, types.TypeVec128, 0), sys.AMD64)
+       addF(simdPackage, "Uint64x4.MaskedRotateAllRight", opLen2Imm8(ssa.OpMaskedRotateAllRightUint64x4, types.TypeVec256, 0), sys.AMD64)
+       addF(simdPackage, "Uint64x8.MaskedRotateAllRight", opLen2Imm8(ssa.OpMaskedRotateAllRightUint64x8, types.TypeVec512, 0), sys.AMD64)
+       addF(simdPackage, "Int32x4.MaskedRotateLeft", opLen3(ssa.OpMaskedRotateLeftInt32x4, types.TypeVec128), sys.AMD64)
+       addF(simdPackage, "Int32x8.MaskedRotateLeft", opLen3(ssa.OpMaskedRotateLeftInt32x8, types.TypeVec256), sys.AMD64)
+       addF(simdPackage, "Int32x16.MaskedRotateLeft", opLen3(ssa.OpMaskedRotateLeftInt32x16, types.TypeVec512), sys.AMD64)
+       addF(simdPackage, "Int64x2.MaskedRotateLeft", opLen3(ssa.OpMaskedRotateLeftInt64x2, types.TypeVec128), sys.AMD64)
+       addF(simdPackage, "Int64x4.MaskedRotateLeft", opLen3(ssa.OpMaskedRotateLeftInt64x4, types.TypeVec256), sys.AMD64)
+       addF(simdPackage, "Int64x8.MaskedRotateLeft", opLen3(ssa.OpMaskedRotateLeftInt64x8, types.TypeVec512), sys.AMD64)
+       addF(simdPackage, "Uint32x4.MaskedRotateLeft", opLen3(ssa.OpMaskedRotateLeftUint32x4, types.TypeVec128), sys.AMD64)
+       addF(simdPackage, "Uint32x8.MaskedRotateLeft", opLen3(ssa.OpMaskedRotateLeftUint32x8, types.TypeVec256), sys.AMD64)
+       addF(simdPackage, "Uint32x16.MaskedRotateLeft", opLen3(ssa.OpMaskedRotateLeftUint32x16, types.TypeVec512), sys.AMD64)
+       addF(simdPackage, "Uint64x2.MaskedRotateLeft", opLen3(ssa.OpMaskedRotateLeftUint64x2, types.TypeVec128), sys.AMD64)
+       addF(simdPackage, "Uint64x4.MaskedRotateLeft", opLen3(ssa.OpMaskedRotateLeftUint64x4, types.TypeVec256), sys.AMD64)
+       addF(simdPackage, "Uint64x8.MaskedRotateLeft", opLen3(ssa.OpMaskedRotateLeftUint64x8, types.TypeVec512), sys.AMD64)
+       addF(simdPackage, "Int32x4.MaskedRotateRight", opLen3(ssa.OpMaskedRotateRightInt32x4, types.TypeVec128), sys.AMD64)
+       addF(simdPackage, "Int32x8.MaskedRotateRight", opLen3(ssa.OpMaskedRotateRightInt32x8, types.TypeVec256), sys.AMD64)
+       addF(simdPackage, "Int32x16.MaskedRotateRight", opLen3(ssa.OpMaskedRotateRightInt32x16, types.TypeVec512), sys.AMD64)
+       addF(simdPackage, "Int64x2.MaskedRotateRight", opLen3(ssa.OpMaskedRotateRightInt64x2, types.TypeVec128), sys.AMD64)
+       addF(simdPackage, "Int64x4.MaskedRotateRight", opLen3(ssa.OpMaskedRotateRightInt64x4, types.TypeVec256), sys.AMD64)
+       addF(simdPackage, "Int64x8.MaskedRotateRight", opLen3(ssa.OpMaskedRotateRightInt64x8, types.TypeVec512), sys.AMD64)
+       addF(simdPackage, "Uint32x4.MaskedRotateRight", opLen3(ssa.OpMaskedRotateRightUint32x4, types.TypeVec128), sys.AMD64)
+       addF(simdPackage, "Uint32x8.MaskedRotateRight", opLen3(ssa.OpMaskedRotateRightUint32x8, types.TypeVec256), sys.AMD64)
+       addF(simdPackage, "Uint32x16.MaskedRotateRight", opLen3(ssa.OpMaskedRotateRightUint32x16, types.TypeVec512), sys.AMD64)
+       addF(simdPackage, "Uint64x2.MaskedRotateRight", opLen3(ssa.OpMaskedRotateRightUint64x2, types.TypeVec128), sys.AMD64)
+       addF(simdPackage, "Uint64x4.MaskedRotateRight", opLen3(ssa.OpMaskedRotateRightUint64x4, types.TypeVec256), sys.AMD64)
+       addF(simdPackage, "Uint64x8.MaskedRotateRight", opLen3(ssa.OpMaskedRotateRightUint64x8, types.TypeVec512), sys.AMD64)
        addF(simdPackage, "Float32x4.MaskedRoundSuppressExceptionWithPrecision", opLen2Imm8(ssa.OpMaskedRoundSuppressExceptionWithPrecisionFloat32x4, types.TypeVec128, 4), sys.AMD64)
        addF(simdPackage, "Float32x8.MaskedRoundSuppressExceptionWithPrecision", opLen2Imm8(ssa.OpMaskedRoundSuppressExceptionWithPrecisionFloat32x8, types.TypeVec256, 4), sys.AMD64)
        addF(simdPackage, "Float32x16.MaskedRoundSuppressExceptionWithPrecision", opLen2Imm8(ssa.OpMaskedRoundSuppressExceptionWithPrecisionFloat32x16, types.TypeVec512, 4), sys.AMD64)
@@ -963,6 +1011,147 @@ func simdIntrinsics(addF func(pkg, fn string, b intrinsicBuilder, archFamilies .
        addF(simdPackage, "Uint32x4.MaskedSaturatedUnsignedSignedQuadDotProdAccumulate", opLen4(ssa.OpMaskedSaturatedUnsignedSignedQuadDotProdAccumulateUint32x4, types.TypeVec128), sys.AMD64)
        addF(simdPackage, "Uint32x8.MaskedSaturatedUnsignedSignedQuadDotProdAccumulate", opLen4(ssa.OpMaskedSaturatedUnsignedSignedQuadDotProdAccumulateUint32x8, types.TypeVec256), sys.AMD64)
        addF(simdPackage, "Uint32x16.MaskedSaturatedUnsignedSignedQuadDotProdAccumulate", opLen4(ssa.OpMaskedSaturatedUnsignedSignedQuadDotProdAccumulateUint32x16, types.TypeVec512), sys.AMD64)
+       addF(simdPackage, "Int64x2.MaskedShiftAllLeft", opLen3(ssa.OpMaskedShiftAllLeftInt64x2, types.TypeVec128), sys.AMD64)
+       addF(simdPackage, "Int64x4.MaskedShiftAllLeft", opLen3(ssa.OpMaskedShiftAllLeftInt64x4, types.TypeVec256), sys.AMD64)
+       addF(simdPackage, "Int64x8.MaskedShiftAllLeft", opLen3(ssa.OpMaskedShiftAllLeftInt64x8, types.TypeVec512), sys.AMD64)
+       addF(simdPackage, "Uint64x2.MaskedShiftAllLeft", opLen3(ssa.OpMaskedShiftAllLeftUint64x2, types.TypeVec128), sys.AMD64)
+       addF(simdPackage, "Uint64x4.MaskedShiftAllLeft", opLen3(ssa.OpMaskedShiftAllLeftUint64x4, types.TypeVec256), sys.AMD64)
+       addF(simdPackage, "Uint64x8.MaskedShiftAllLeft", opLen3(ssa.OpMaskedShiftAllLeftUint64x8, types.TypeVec512), sys.AMD64)
+       addF(simdPackage, "Int16x8.MaskedShiftAllLeftAndFillUpperFrom", opLen3Imm8(ssa.OpMaskedShiftAllLeftAndFillUpperFromInt16x8, types.TypeVec128, 0), sys.AMD64)
+       addF(simdPackage, "Int16x16.MaskedShiftAllLeftAndFillUpperFrom", opLen3Imm8(ssa.OpMaskedShiftAllLeftAndFillUpperFromInt16x16, types.TypeVec256, 0), sys.AMD64)
+       addF(simdPackage, "Int16x32.MaskedShiftAllLeftAndFillUpperFrom", opLen3Imm8(ssa.OpMaskedShiftAllLeftAndFillUpperFromInt16x32, types.TypeVec512, 0), sys.AMD64)
+       addF(simdPackage, "Int32x4.MaskedShiftAllLeftAndFillUpperFrom", opLen3Imm8(ssa.OpMaskedShiftAllLeftAndFillUpperFromInt32x4, types.TypeVec128, 0), sys.AMD64)
+       addF(simdPackage, "Int32x8.MaskedShiftAllLeftAndFillUpperFrom", opLen3Imm8(ssa.OpMaskedShiftAllLeftAndFillUpperFromInt32x8, types.TypeVec256, 0), sys.AMD64)
+       addF(simdPackage, "Int32x16.MaskedShiftAllLeftAndFillUpperFrom", opLen3Imm8(ssa.OpMaskedShiftAllLeftAndFillUpperFromInt32x16, types.TypeVec512, 0), sys.AMD64)
+       addF(simdPackage, "Int64x2.MaskedShiftAllLeftAndFillUpperFrom", opLen3Imm8(ssa.OpMaskedShiftAllLeftAndFillUpperFromInt64x2, types.TypeVec128, 0), sys.AMD64)
+       addF(simdPackage, "Int64x4.MaskedShiftAllLeftAndFillUpperFrom", opLen3Imm8(ssa.OpMaskedShiftAllLeftAndFillUpperFromInt64x4, types.TypeVec256, 0), sys.AMD64)
+       addF(simdPackage, "Int64x8.MaskedShiftAllLeftAndFillUpperFrom", opLen3Imm8(ssa.OpMaskedShiftAllLeftAndFillUpperFromInt64x8, types.TypeVec512, 0), sys.AMD64)
+       addF(simdPackage, "Uint16x8.MaskedShiftAllLeftAndFillUpperFrom", opLen3Imm8(ssa.OpMaskedShiftAllLeftAndFillUpperFromUint16x8, types.TypeVec128, 0), sys.AMD64)
+       addF(simdPackage, "Uint16x16.MaskedShiftAllLeftAndFillUpperFrom", opLen3Imm8(ssa.OpMaskedShiftAllLeftAndFillUpperFromUint16x16, types.TypeVec256, 0), sys.AMD64)
+       addF(simdPackage, "Uint16x32.MaskedShiftAllLeftAndFillUpperFrom", opLen3Imm8(ssa.OpMaskedShiftAllLeftAndFillUpperFromUint16x32, types.TypeVec512, 0), sys.AMD64)
+       addF(simdPackage, "Uint32x4.MaskedShiftAllLeftAndFillUpperFrom", opLen3Imm8(ssa.OpMaskedShiftAllLeftAndFillUpperFromUint32x4, types.TypeVec128, 0), sys.AMD64)
+       addF(simdPackage, "Uint32x8.MaskedShiftAllLeftAndFillUpperFrom", opLen3Imm8(ssa.OpMaskedShiftAllLeftAndFillUpperFromUint32x8, types.TypeVec256, 0), sys.AMD64)
+       addF(simdPackage, "Uint32x16.MaskedShiftAllLeftAndFillUpperFrom", opLen3Imm8(ssa.OpMaskedShiftAllLeftAndFillUpperFromUint32x16, types.TypeVec512, 0), sys.AMD64)
+       addF(simdPackage, "Uint64x2.MaskedShiftAllLeftAndFillUpperFrom", opLen3Imm8(ssa.OpMaskedShiftAllLeftAndFillUpperFromUint64x2, types.TypeVec128, 0), sys.AMD64)
+       addF(simdPackage, "Uint64x4.MaskedShiftAllLeftAndFillUpperFrom", opLen3Imm8(ssa.OpMaskedShiftAllLeftAndFillUpperFromUint64x4, types.TypeVec256, 0), sys.AMD64)
+       addF(simdPackage, "Uint64x8.MaskedShiftAllLeftAndFillUpperFrom", opLen3Imm8(ssa.OpMaskedShiftAllLeftAndFillUpperFromUint64x8, types.TypeVec512, 0), sys.AMD64)
+       addF(simdPackage, "Int64x2.MaskedShiftAllRight", opLen3(ssa.OpMaskedShiftAllRightInt64x2, types.TypeVec128), sys.AMD64)
+       addF(simdPackage, "Int64x4.MaskedShiftAllRight", opLen3(ssa.OpMaskedShiftAllRightInt64x4, types.TypeVec256), sys.AMD64)
+       addF(simdPackage, "Int64x8.MaskedShiftAllRight", opLen3(ssa.OpMaskedShiftAllRightInt64x8, types.TypeVec512), sys.AMD64)
+       addF(simdPackage, "Uint64x2.MaskedShiftAllRight", opLen3(ssa.OpMaskedShiftAllRightUint64x2, types.TypeVec128), sys.AMD64)
+       addF(simdPackage, "Uint64x4.MaskedShiftAllRight", opLen3(ssa.OpMaskedShiftAllRightUint64x4, types.TypeVec256), sys.AMD64)
+       addF(simdPackage, "Uint64x8.MaskedShiftAllRight", opLen3(ssa.OpMaskedShiftAllRightUint64x8, types.TypeVec512), sys.AMD64)
+       addF(simdPackage, "Int16x8.MaskedShiftAllRightAndFillUpperFrom", opLen3Imm8(ssa.OpMaskedShiftAllRightAndFillUpperFromInt16x8, types.TypeVec128, 0), sys.AMD64)
+       addF(simdPackage, "Int16x16.MaskedShiftAllRightAndFillUpperFrom", opLen3Imm8(ssa.OpMaskedShiftAllRightAndFillUpperFromInt16x16, types.TypeVec256, 0), sys.AMD64)
+       addF(simdPackage, "Int16x32.MaskedShiftAllRightAndFillUpperFrom", opLen3Imm8(ssa.OpMaskedShiftAllRightAndFillUpperFromInt16x32, types.TypeVec512, 0), sys.AMD64)
+       addF(simdPackage, "Int32x4.MaskedShiftAllRightAndFillUpperFrom", opLen3Imm8(ssa.OpMaskedShiftAllRightAndFillUpperFromInt32x4, types.TypeVec128, 0), sys.AMD64)
+       addF(simdPackage, "Int32x8.MaskedShiftAllRightAndFillUpperFrom", opLen3Imm8(ssa.OpMaskedShiftAllRightAndFillUpperFromInt32x8, types.TypeVec256, 0), sys.AMD64)
+       addF(simdPackage, "Int32x16.MaskedShiftAllRightAndFillUpperFrom", opLen3Imm8(ssa.OpMaskedShiftAllRightAndFillUpperFromInt32x16, types.TypeVec512, 0), sys.AMD64)
+       addF(simdPackage, "Int64x2.MaskedShiftAllRightAndFillUpperFrom", opLen3Imm8(ssa.OpMaskedShiftAllRightAndFillUpperFromInt64x2, types.TypeVec128, 0), sys.AMD64)
+       addF(simdPackage, "Int64x4.MaskedShiftAllRightAndFillUpperFrom", opLen3Imm8(ssa.OpMaskedShiftAllRightAndFillUpperFromInt64x4, types.TypeVec256, 0), sys.AMD64)
+       addF(simdPackage, "Int64x8.MaskedShiftAllRightAndFillUpperFrom", opLen3Imm8(ssa.OpMaskedShiftAllRightAndFillUpperFromInt64x8, types.TypeVec512, 0), sys.AMD64)
+       addF(simdPackage, "Uint16x8.MaskedShiftAllRightAndFillUpperFrom", opLen3Imm8(ssa.OpMaskedShiftAllRightAndFillUpperFromUint16x8, types.TypeVec128, 0), sys.AMD64)
+       addF(simdPackage, "Uint16x16.MaskedShiftAllRightAndFillUpperFrom", opLen3Imm8(ssa.OpMaskedShiftAllRightAndFillUpperFromUint16x16, types.TypeVec256, 0), sys.AMD64)
+       addF(simdPackage, "Uint16x32.MaskedShiftAllRightAndFillUpperFrom", opLen3Imm8(ssa.OpMaskedShiftAllRightAndFillUpperFromUint16x32, types.TypeVec512, 0), sys.AMD64)
+       addF(simdPackage, "Uint32x4.MaskedShiftAllRightAndFillUpperFrom", opLen3Imm8(ssa.OpMaskedShiftAllRightAndFillUpperFromUint32x4, types.TypeVec128, 0), sys.AMD64)
+       addF(simdPackage, "Uint32x8.MaskedShiftAllRightAndFillUpperFrom", opLen3Imm8(ssa.OpMaskedShiftAllRightAndFillUpperFromUint32x8, types.TypeVec256, 0), sys.AMD64)
+       addF(simdPackage, "Uint32x16.MaskedShiftAllRightAndFillUpperFrom", opLen3Imm8(ssa.OpMaskedShiftAllRightAndFillUpperFromUint32x16, types.TypeVec512, 0), sys.AMD64)
+       addF(simdPackage, "Uint64x2.MaskedShiftAllRightAndFillUpperFrom", opLen3Imm8(ssa.OpMaskedShiftAllRightAndFillUpperFromUint64x2, types.TypeVec128, 0), sys.AMD64)
+       addF(simdPackage, "Uint64x4.MaskedShiftAllRightAndFillUpperFrom", opLen3Imm8(ssa.OpMaskedShiftAllRightAndFillUpperFromUint64x4, types.TypeVec256, 0), sys.AMD64)
+       addF(simdPackage, "Uint64x8.MaskedShiftAllRightAndFillUpperFrom", opLen3Imm8(ssa.OpMaskedShiftAllRightAndFillUpperFromUint64x8, types.TypeVec512, 0), sys.AMD64)
+       addF(simdPackage, "Int64x2.MaskedShiftAllRightSignExtended", opLen3(ssa.OpMaskedShiftAllRightSignExtendedInt64x2, types.TypeVec128), sys.AMD64)
+       addF(simdPackage, "Int64x4.MaskedShiftAllRightSignExtended", opLen3(ssa.OpMaskedShiftAllRightSignExtendedInt64x4, types.TypeVec256), sys.AMD64)
+       addF(simdPackage, "Int64x8.MaskedShiftAllRightSignExtended", opLen3(ssa.OpMaskedShiftAllRightSignExtendedInt64x8, types.TypeVec512), sys.AMD64)
+       addF(simdPackage, "Int16x8.MaskedShiftLeft", opLen3(ssa.OpMaskedShiftLeftInt16x8, types.TypeVec128), sys.AMD64)
+       addF(simdPackage, "Int16x16.MaskedShiftLeft", opLen3(ssa.OpMaskedShiftLeftInt16x16, types.TypeVec256), sys.AMD64)
+       addF(simdPackage, "Int16x32.MaskedShiftLeft", opLen3(ssa.OpMaskedShiftLeftInt16x32, types.TypeVec512), sys.AMD64)
+       addF(simdPackage, "Int32x4.MaskedShiftLeft", opLen3(ssa.OpMaskedShiftLeftInt32x4, types.TypeVec128), sys.AMD64)
+       addF(simdPackage, "Int32x8.MaskedShiftLeft", opLen3(ssa.OpMaskedShiftLeftInt32x8, types.TypeVec256), sys.AMD64)
+       addF(simdPackage, "Int32x16.MaskedShiftLeft", opLen3(ssa.OpMaskedShiftLeftInt32x16, types.TypeVec512), sys.AMD64)
+       addF(simdPackage, "Int64x2.MaskedShiftLeft", opLen3(ssa.OpMaskedShiftLeftInt64x2, types.TypeVec128), sys.AMD64)
+       addF(simdPackage, "Int64x4.MaskedShiftLeft", opLen3(ssa.OpMaskedShiftLeftInt64x4, types.TypeVec256), sys.AMD64)
+       addF(simdPackage, "Int64x8.MaskedShiftLeft", opLen3(ssa.OpMaskedShiftLeftInt64x8, types.TypeVec512), sys.AMD64)
+       addF(simdPackage, "Uint16x8.MaskedShiftLeft", opLen3(ssa.OpMaskedShiftLeftUint16x8, types.TypeVec128), sys.AMD64)
+       addF(simdPackage, "Uint16x16.MaskedShiftLeft", opLen3(ssa.OpMaskedShiftLeftUint16x16, types.TypeVec256), sys.AMD64)
+       addF(simdPackage, "Uint16x32.MaskedShiftLeft", opLen3(ssa.OpMaskedShiftLeftUint16x32, types.TypeVec512), sys.AMD64)
+       addF(simdPackage, "Uint32x4.MaskedShiftLeft", opLen3(ssa.OpMaskedShiftLeftUint32x4, types.TypeVec128), sys.AMD64)
+       addF(simdPackage, "Uint32x8.MaskedShiftLeft", opLen3(ssa.OpMaskedShiftLeftUint32x8, types.TypeVec256), sys.AMD64)
+       addF(simdPackage, "Uint32x16.MaskedShiftLeft", opLen3(ssa.OpMaskedShiftLeftUint32x16, types.TypeVec512), sys.AMD64)
+       addF(simdPackage, "Uint64x2.MaskedShiftLeft", opLen3(ssa.OpMaskedShiftLeftUint64x2, types.TypeVec128), sys.AMD64)
+       addF(simdPackage, "Uint64x4.MaskedShiftLeft", opLen3(ssa.OpMaskedShiftLeftUint64x4, types.TypeVec256), sys.AMD64)
+       addF(simdPackage, "Uint64x8.MaskedShiftLeft", opLen3(ssa.OpMaskedShiftLeftUint64x8, types.TypeVec512), sys.AMD64)
+       addF(simdPackage, "Int16x8.MaskedShiftLeftAndFillUpperFrom", opLen4(ssa.OpMaskedShiftLeftAndFillUpperFromInt16x8, types.TypeVec128), sys.AMD64)
+       addF(simdPackage, "Int16x16.MaskedShiftLeftAndFillUpperFrom", opLen4(ssa.OpMaskedShiftLeftAndFillUpperFromInt16x16, types.TypeVec256), sys.AMD64)
+       addF(simdPackage, "Int16x32.MaskedShiftLeftAndFillUpperFrom", opLen4(ssa.OpMaskedShiftLeftAndFillUpperFromInt16x32, types.TypeVec512), sys.AMD64)
+       addF(simdPackage, "Int32x4.MaskedShiftLeftAndFillUpperFrom", opLen4(ssa.OpMaskedShiftLeftAndFillUpperFromInt32x4, types.TypeVec128), sys.AMD64)
+       addF(simdPackage, "Int32x8.MaskedShiftLeftAndFillUpperFrom", opLen4(ssa.OpMaskedShiftLeftAndFillUpperFromInt32x8, types.TypeVec256), sys.AMD64)
+       addF(simdPackage, "Int32x16.MaskedShiftLeftAndFillUpperFrom", opLen4(ssa.OpMaskedShiftLeftAndFillUpperFromInt32x16, types.TypeVec512), sys.AMD64)
+       addF(simdPackage, "Int64x2.MaskedShiftLeftAndFillUpperFrom", opLen4(ssa.OpMaskedShiftLeftAndFillUpperFromInt64x2, types.TypeVec128), sys.AMD64)
+       addF(simdPackage, "Int64x4.MaskedShiftLeftAndFillUpperFrom", opLen4(ssa.OpMaskedShiftLeftAndFillUpperFromInt64x4, types.TypeVec256), sys.AMD64)
+       addF(simdPackage, "Int64x8.MaskedShiftLeftAndFillUpperFrom", opLen4(ssa.OpMaskedShiftLeftAndFillUpperFromInt64x8, types.TypeVec512), sys.AMD64)
+       addF(simdPackage, "Uint16x8.MaskedShiftLeftAndFillUpperFrom", opLen4(ssa.OpMaskedShiftLeftAndFillUpperFromUint16x8, types.TypeVec128), sys.AMD64)
+       addF(simdPackage, "Uint16x16.MaskedShiftLeftAndFillUpperFrom", opLen4(ssa.OpMaskedShiftLeftAndFillUpperFromUint16x16, types.TypeVec256), sys.AMD64)
+       addF(simdPackage, "Uint16x32.MaskedShiftLeftAndFillUpperFrom", opLen4(ssa.OpMaskedShiftLeftAndFillUpperFromUint16x32, types.TypeVec512), sys.AMD64)
+       addF(simdPackage, "Uint32x4.MaskedShiftLeftAndFillUpperFrom", opLen4(ssa.OpMaskedShiftLeftAndFillUpperFromUint32x4, types.TypeVec128), sys.AMD64)
+       addF(simdPackage, "Uint32x8.MaskedShiftLeftAndFillUpperFrom", opLen4(ssa.OpMaskedShiftLeftAndFillUpperFromUint32x8, types.TypeVec256), sys.AMD64)
+       addF(simdPackage, "Uint32x16.MaskedShiftLeftAndFillUpperFrom", opLen4(ssa.OpMaskedShiftLeftAndFillUpperFromUint32x16, types.TypeVec512), sys.AMD64)
+       addF(simdPackage, "Uint64x2.MaskedShiftLeftAndFillUpperFrom", opLen4(ssa.OpMaskedShiftLeftAndFillUpperFromUint64x2, types.TypeVec128), sys.AMD64)
+       addF(simdPackage, "Uint64x4.MaskedShiftLeftAndFillUpperFrom", opLen4(ssa.OpMaskedShiftLeftAndFillUpperFromUint64x4, types.TypeVec256), sys.AMD64)
+       addF(simdPackage, "Uint64x8.MaskedShiftLeftAndFillUpperFrom", opLen4(ssa.OpMaskedShiftLeftAndFillUpperFromUint64x8, types.TypeVec512), sys.AMD64)
+       addF(simdPackage, "Int16x8.MaskedShiftRight", opLen3(ssa.OpMaskedShiftRightInt16x8, types.TypeVec128), sys.AMD64)
+       addF(simdPackage, "Int16x16.MaskedShiftRight", opLen3(ssa.OpMaskedShiftRightInt16x16, types.TypeVec256), sys.AMD64)
+       addF(simdPackage, "Int16x32.MaskedShiftRight", opLen3(ssa.OpMaskedShiftRightInt16x32, types.TypeVec512), sys.AMD64)
+       addF(simdPackage, "Int32x4.MaskedShiftRight", opLen3(ssa.OpMaskedShiftRightInt32x4, types.TypeVec128), sys.AMD64)
+       addF(simdPackage, "Int32x8.MaskedShiftRight", opLen3(ssa.OpMaskedShiftRightInt32x8, types.TypeVec256), sys.AMD64)
+       addF(simdPackage, "Int32x16.MaskedShiftRight", opLen3(ssa.OpMaskedShiftRightInt32x16, types.TypeVec512), sys.AMD64)
+       addF(simdPackage, "Int64x2.MaskedShiftRight", opLen3(ssa.OpMaskedShiftRightInt64x2, types.TypeVec128), sys.AMD64)
+       addF(simdPackage, "Int64x4.MaskedShiftRight", opLen3(ssa.OpMaskedShiftRightInt64x4, types.TypeVec256), sys.AMD64)
+       addF(simdPackage, "Int64x8.MaskedShiftRight", opLen3(ssa.OpMaskedShiftRightInt64x8, types.TypeVec512), sys.AMD64)
+       addF(simdPackage, "Uint16x8.MaskedShiftRight", opLen3(ssa.OpMaskedShiftRightUint16x8, types.TypeVec128), sys.AMD64)
+       addF(simdPackage, "Uint16x16.MaskedShiftRight", opLen3(ssa.OpMaskedShiftRightUint16x16, types.TypeVec256), sys.AMD64)
+       addF(simdPackage, "Uint16x32.MaskedShiftRight", opLen3(ssa.OpMaskedShiftRightUint16x32, types.TypeVec512), sys.AMD64)
+       addF(simdPackage, "Uint32x4.MaskedShiftRight", opLen3(ssa.OpMaskedShiftRightUint32x4, types.TypeVec128), sys.AMD64)
+       addF(simdPackage, "Uint32x8.MaskedShiftRight", opLen3(ssa.OpMaskedShiftRightUint32x8, types.TypeVec256), sys.AMD64)
+       addF(simdPackage, "Uint32x16.MaskedShiftRight", opLen3(ssa.OpMaskedShiftRightUint32x16, types.TypeVec512), sys.AMD64)
+       addF(simdPackage, "Uint64x2.MaskedShiftRight", opLen3(ssa.OpMaskedShiftRightUint64x2, types.TypeVec128), sys.AMD64)
+       addF(simdPackage, "Uint64x4.MaskedShiftRight", opLen3(ssa.OpMaskedShiftRightUint64x4, types.TypeVec256), sys.AMD64)
+       addF(simdPackage, "Uint64x8.MaskedShiftRight", opLen3(ssa.OpMaskedShiftRightUint64x8, types.TypeVec512), sys.AMD64)
+       addF(simdPackage, "Int16x8.MaskedShiftRightAndFillUpperFrom", opLen4(ssa.OpMaskedShiftRightAndFillUpperFromInt16x8, types.TypeVec128), sys.AMD64)
+       addF(simdPackage, "Int16x16.MaskedShiftRightAndFillUpperFrom", opLen4(ssa.OpMaskedShiftRightAndFillUpperFromInt16x16, types.TypeVec256), sys.AMD64)
+       addF(simdPackage, "Int16x32.MaskedShiftRightAndFillUpperFrom", opLen4(ssa.OpMaskedShiftRightAndFillUpperFromInt16x32, types.TypeVec512), sys.AMD64)
+       addF(simdPackage, "Int32x4.MaskedShiftRightAndFillUpperFrom", opLen4(ssa.OpMaskedShiftRightAndFillUpperFromInt32x4, types.TypeVec128), sys.AMD64)
+       addF(simdPackage, "Int32x8.MaskedShiftRightAndFillUpperFrom", opLen4(ssa.OpMaskedShiftRightAndFillUpperFromInt32x8, types.TypeVec256), sys.AMD64)
+       addF(simdPackage, "Int32x16.MaskedShiftRightAndFillUpperFrom", opLen4(ssa.OpMaskedShiftRightAndFillUpperFromInt32x16, types.TypeVec512), sys.AMD64)
+       addF(simdPackage, "Int64x2.MaskedShiftRightAndFillUpperFrom", opLen4(ssa.OpMaskedShiftRightAndFillUpperFromInt64x2, types.TypeVec128), sys.AMD64)
+       addF(simdPackage, "Int64x4.MaskedShiftRightAndFillUpperFrom", opLen4(ssa.OpMaskedShiftRightAndFillUpperFromInt64x4, types.TypeVec256), sys.AMD64)
+       addF(simdPackage, "Int64x8.MaskedShiftRightAndFillUpperFrom", opLen4(ssa.OpMaskedShiftRightAndFillUpperFromInt64x8, types.TypeVec512), sys.AMD64)
+       addF(simdPackage, "Uint16x8.MaskedShiftRightAndFillUpperFrom", opLen4(ssa.OpMaskedShiftRightAndFillUpperFromUint16x8, types.TypeVec128), sys.AMD64)
+       addF(simdPackage, "Uint16x16.MaskedShiftRightAndFillUpperFrom", opLen4(ssa.OpMaskedShiftRightAndFillUpperFromUint16x16, types.TypeVec256), sys.AMD64)
+       addF(simdPackage, "Uint16x32.MaskedShiftRightAndFillUpperFrom", opLen4(ssa.OpMaskedShiftRightAndFillUpperFromUint16x32, types.TypeVec512), sys.AMD64)
+       addF(simdPackage, "Uint32x4.MaskedShiftRightAndFillUpperFrom", opLen4(ssa.OpMaskedShiftRightAndFillUpperFromUint32x4, types.TypeVec128), sys.AMD64)
+       addF(simdPackage, "Uint32x8.MaskedShiftRightAndFillUpperFrom", opLen4(ssa.OpMaskedShiftRightAndFillUpperFromUint32x8, types.TypeVec256), sys.AMD64)
+       addF(simdPackage, "Uint32x16.MaskedShiftRightAndFillUpperFrom", opLen4(ssa.OpMaskedShiftRightAndFillUpperFromUint32x16, types.TypeVec512), sys.AMD64)
+       addF(simdPackage, "Uint64x2.MaskedShiftRightAndFillUpperFrom", opLen4(ssa.OpMaskedShiftRightAndFillUpperFromUint64x2, types.TypeVec128), sys.AMD64)
+       addF(simdPackage, "Uint64x4.MaskedShiftRightAndFillUpperFrom", opLen4(ssa.OpMaskedShiftRightAndFillUpperFromUint64x4, types.TypeVec256), sys.AMD64)
+       addF(simdPackage, "Uint64x8.MaskedShiftRightAndFillUpperFrom", opLen4(ssa.OpMaskedShiftRightAndFillUpperFromUint64x8, types.TypeVec512), sys.AMD64)
+       addF(simdPackage, "Int16x8.MaskedShiftRightSignExtended", opLen3(ssa.OpMaskedShiftRightSignExtendedInt16x8, types.TypeVec128), sys.AMD64)
+       addF(simdPackage, "Int16x16.MaskedShiftRightSignExtended", opLen3(ssa.OpMaskedShiftRightSignExtendedInt16x16, types.TypeVec256), sys.AMD64)
+       addF(simdPackage, "Int16x32.MaskedShiftRightSignExtended", opLen3(ssa.OpMaskedShiftRightSignExtendedInt16x32, types.TypeVec512), sys.AMD64)
+       addF(simdPackage, "Int32x4.MaskedShiftRightSignExtended", opLen3(ssa.OpMaskedShiftRightSignExtendedInt32x4, types.TypeVec128), sys.AMD64)
+       addF(simdPackage, "Int32x8.MaskedShiftRightSignExtended", opLen3(ssa.OpMaskedShiftRightSignExtendedInt32x8, types.TypeVec256), sys.AMD64)
+       addF(simdPackage, "Int32x16.MaskedShiftRightSignExtended", opLen3(ssa.OpMaskedShiftRightSignExtendedInt32x16, types.TypeVec512), sys.AMD64)
+       addF(simdPackage, "Int64x2.MaskedShiftRightSignExtended", opLen3(ssa.OpMaskedShiftRightSignExtendedInt64x2, types.TypeVec128), sys.AMD64)
+       addF(simdPackage, "Int64x4.MaskedShiftRightSignExtended", opLen3(ssa.OpMaskedShiftRightSignExtendedInt64x4, types.TypeVec256), sys.AMD64)
+       addF(simdPackage, "Int64x8.MaskedShiftRightSignExtended", opLen3(ssa.OpMaskedShiftRightSignExtendedInt64x8, types.TypeVec512), sys.AMD64)
+       addF(simdPackage, "Uint16x8.MaskedShiftRightSignExtended", opLen3(ssa.OpMaskedShiftRightSignExtendedUint16x8, types.TypeVec128), sys.AMD64)
+       addF(simdPackage, "Uint16x16.MaskedShiftRightSignExtended", opLen3(ssa.OpMaskedShiftRightSignExtendedUint16x16, types.TypeVec256), sys.AMD64)
+       addF(simdPackage, "Uint16x32.MaskedShiftRightSignExtended", opLen3(ssa.OpMaskedShiftRightSignExtendedUint16x32, types.TypeVec512), sys.AMD64)
+       addF(simdPackage, "Uint32x4.MaskedShiftRightSignExtended", opLen3(ssa.OpMaskedShiftRightSignExtendedUint32x4, types.TypeVec128), sys.AMD64)
+       addF(simdPackage, "Uint32x8.MaskedShiftRightSignExtended", opLen3(ssa.OpMaskedShiftRightSignExtendedUint32x8, types.TypeVec256), sys.AMD64)
+       addF(simdPackage, "Uint32x16.MaskedShiftRightSignExtended", opLen3(ssa.OpMaskedShiftRightSignExtendedUint32x16, types.TypeVec512), sys.AMD64)
+       addF(simdPackage, "Uint64x2.MaskedShiftRightSignExtended", opLen3(ssa.OpMaskedShiftRightSignExtendedUint64x2, types.TypeVec128), sys.AMD64)
+       addF(simdPackage, "Uint64x4.MaskedShiftRightSignExtended", opLen3(ssa.OpMaskedShiftRightSignExtendedUint64x4, types.TypeVec256), sys.AMD64)
+       addF(simdPackage, "Uint64x8.MaskedShiftRightSignExtended", opLen3(ssa.OpMaskedShiftRightSignExtendedUint64x8, types.TypeVec512), sys.AMD64)
        addF(simdPackage, "Float32x4.MaskedSqrt", opLen2(ssa.OpMaskedSqrtFloat32x4, types.TypeVec128), sys.AMD64)
        addF(simdPackage, "Float32x8.MaskedSqrt", opLen2(ssa.OpMaskedSqrtFloat32x8, types.TypeVec256), sys.AMD64)
        addF(simdPackage, "Float32x16.MaskedSqrt", opLen2(ssa.OpMaskedSqrtFloat32x16, types.TypeVec512), sys.AMD64)
@@ -1242,6 +1431,54 @@ func simdIntrinsics(addF func(pkg, fn string, b intrinsicBuilder, archFamilies .
        addF(simdPackage, "Uint64x2.PopCount", opLen1(ssa.OpPopCountUint64x2, types.TypeVec128), sys.AMD64)
        addF(simdPackage, "Uint64x4.PopCount", opLen1(ssa.OpPopCountUint64x4, types.TypeVec256), sys.AMD64)
        addF(simdPackage, "Uint64x8.PopCount", opLen1(ssa.OpPopCountUint64x8, types.TypeVec512), sys.AMD64)
+       addF(simdPackage, "Int32x4.RotateAllLeft", opLen1Imm8(ssa.OpRotateAllLeftInt32x4, types.TypeVec128, 0), sys.AMD64)
+       addF(simdPackage, "Int32x8.RotateAllLeft", opLen1Imm8(ssa.OpRotateAllLeftInt32x8, types.TypeVec256, 0), sys.AMD64)
+       addF(simdPackage, "Int32x16.RotateAllLeft", opLen1Imm8(ssa.OpRotateAllLeftInt32x16, types.TypeVec512, 0), sys.AMD64)
+       addF(simdPackage, "Int64x2.RotateAllLeft", opLen1Imm8(ssa.OpRotateAllLeftInt64x2, types.TypeVec128, 0), sys.AMD64)
+       addF(simdPackage, "Int64x4.RotateAllLeft", opLen1Imm8(ssa.OpRotateAllLeftInt64x4, types.TypeVec256, 0), sys.AMD64)
+       addF(simdPackage, "Int64x8.RotateAllLeft", opLen1Imm8(ssa.OpRotateAllLeftInt64x8, types.TypeVec512, 0), sys.AMD64)
+       addF(simdPackage, "Uint32x4.RotateAllLeft", opLen1Imm8(ssa.OpRotateAllLeftUint32x4, types.TypeVec128, 0), sys.AMD64)
+       addF(simdPackage, "Uint32x8.RotateAllLeft", opLen1Imm8(ssa.OpRotateAllLeftUint32x8, types.TypeVec256, 0), sys.AMD64)
+       addF(simdPackage, "Uint32x16.RotateAllLeft", opLen1Imm8(ssa.OpRotateAllLeftUint32x16, types.TypeVec512, 0), sys.AMD64)
+       addF(simdPackage, "Uint64x2.RotateAllLeft", opLen1Imm8(ssa.OpRotateAllLeftUint64x2, types.TypeVec128, 0), sys.AMD64)
+       addF(simdPackage, "Uint64x4.RotateAllLeft", opLen1Imm8(ssa.OpRotateAllLeftUint64x4, types.TypeVec256, 0), sys.AMD64)
+       addF(simdPackage, "Uint64x8.RotateAllLeft", opLen1Imm8(ssa.OpRotateAllLeftUint64x8, types.TypeVec512, 0), sys.AMD64)
+       addF(simdPackage, "Int32x4.RotateAllRight", opLen1Imm8(ssa.OpRotateAllRightInt32x4, types.TypeVec128, 0), sys.AMD64)
+       addF(simdPackage, "Int32x8.RotateAllRight", opLen1Imm8(ssa.OpRotateAllRightInt32x8, types.TypeVec256, 0), sys.AMD64)
+       addF(simdPackage, "Int32x16.RotateAllRight", opLen1Imm8(ssa.OpRotateAllRightInt32x16, types.TypeVec512, 0), sys.AMD64)
+       addF(simdPackage, "Int64x2.RotateAllRight", opLen1Imm8(ssa.OpRotateAllRightInt64x2, types.TypeVec128, 0), sys.AMD64)
+       addF(simdPackage, "Int64x4.RotateAllRight", opLen1Imm8(ssa.OpRotateAllRightInt64x4, types.TypeVec256, 0), sys.AMD64)
+       addF(simdPackage, "Int64x8.RotateAllRight", opLen1Imm8(ssa.OpRotateAllRightInt64x8, types.TypeVec512, 0), sys.AMD64)
+       addF(simdPackage, "Uint32x4.RotateAllRight", opLen1Imm8(ssa.OpRotateAllRightUint32x4, types.TypeVec128, 0), sys.AMD64)
+       addF(simdPackage, "Uint32x8.RotateAllRight", opLen1Imm8(ssa.OpRotateAllRightUint32x8, types.TypeVec256, 0), sys.AMD64)
+       addF(simdPackage, "Uint32x16.RotateAllRight", opLen1Imm8(ssa.OpRotateAllRightUint32x16, types.TypeVec512, 0), sys.AMD64)
+       addF(simdPackage, "Uint64x2.RotateAllRight", opLen1Imm8(ssa.OpRotateAllRightUint64x2, types.TypeVec128, 0), sys.AMD64)
+       addF(simdPackage, "Uint64x4.RotateAllRight", opLen1Imm8(ssa.OpRotateAllRightUint64x4, types.TypeVec256, 0), sys.AMD64)
+       addF(simdPackage, "Uint64x8.RotateAllRight", opLen1Imm8(ssa.OpRotateAllRightUint64x8, types.TypeVec512, 0), sys.AMD64)
+       addF(simdPackage, "Int32x4.RotateLeft", opLen2(ssa.OpRotateLeftInt32x4, types.TypeVec128), sys.AMD64)
+       addF(simdPackage, "Int32x8.RotateLeft", opLen2(ssa.OpRotateLeftInt32x8, types.TypeVec256), sys.AMD64)
+       addF(simdPackage, "Int32x16.RotateLeft", opLen2(ssa.OpRotateLeftInt32x16, types.TypeVec512), sys.AMD64)
+       addF(simdPackage, "Int64x2.RotateLeft", opLen2(ssa.OpRotateLeftInt64x2, types.TypeVec128), sys.AMD64)
+       addF(simdPackage, "Int64x4.RotateLeft", opLen2(ssa.OpRotateLeftInt64x4, types.TypeVec256), sys.AMD64)
+       addF(simdPackage, "Int64x8.RotateLeft", opLen2(ssa.OpRotateLeftInt64x8, types.TypeVec512), sys.AMD64)
+       addF(simdPackage, "Uint32x4.RotateLeft", opLen2(ssa.OpRotateLeftUint32x4, types.TypeVec128), sys.AMD64)
+       addF(simdPackage, "Uint32x8.RotateLeft", opLen2(ssa.OpRotateLeftUint32x8, types.TypeVec256), sys.AMD64)
+       addF(simdPackage, "Uint32x16.RotateLeft", opLen2(ssa.OpRotateLeftUint32x16, types.TypeVec512), sys.AMD64)
+       addF(simdPackage, "Uint64x2.RotateLeft", opLen2(ssa.OpRotateLeftUint64x2, types.TypeVec128), sys.AMD64)
+       addF(simdPackage, "Uint64x4.RotateLeft", opLen2(ssa.OpRotateLeftUint64x4, types.TypeVec256), sys.AMD64)
+       addF(simdPackage, "Uint64x8.RotateLeft", opLen2(ssa.OpRotateLeftUint64x8, types.TypeVec512), sys.AMD64)
+       addF(simdPackage, "Int32x4.RotateRight", opLen2(ssa.OpRotateRightInt32x4, types.TypeVec128), sys.AMD64)
+       addF(simdPackage, "Int32x8.RotateRight", opLen2(ssa.OpRotateRightInt32x8, types.TypeVec256), sys.AMD64)
+       addF(simdPackage, "Int32x16.RotateRight", opLen2(ssa.OpRotateRightInt32x16, types.TypeVec512), sys.AMD64)
+       addF(simdPackage, "Int64x2.RotateRight", opLen2(ssa.OpRotateRightInt64x2, types.TypeVec128), sys.AMD64)
+       addF(simdPackage, "Int64x4.RotateRight", opLen2(ssa.OpRotateRightInt64x4, types.TypeVec256), sys.AMD64)
+       addF(simdPackage, "Int64x8.RotateRight", opLen2(ssa.OpRotateRightInt64x8, types.TypeVec512), sys.AMD64)
+       addF(simdPackage, "Uint32x4.RotateRight", opLen2(ssa.OpRotateRightUint32x4, types.TypeVec128), sys.AMD64)
+       addF(simdPackage, "Uint32x8.RotateRight", opLen2(ssa.OpRotateRightUint32x8, types.TypeVec256), sys.AMD64)
+       addF(simdPackage, "Uint32x16.RotateRight", opLen2(ssa.OpRotateRightUint32x16, types.TypeVec512), sys.AMD64)
+       addF(simdPackage, "Uint64x2.RotateRight", opLen2(ssa.OpRotateRightUint64x2, types.TypeVec128), sys.AMD64)
+       addF(simdPackage, "Uint64x4.RotateRight", opLen2(ssa.OpRotateRightUint64x4, types.TypeVec256), sys.AMD64)
+       addF(simdPackage, "Uint64x8.RotateRight", opLen2(ssa.OpRotateRightUint64x8, types.TypeVec512), sys.AMD64)
        addF(simdPackage, "Float32x4.Round", opLen1(ssa.OpRoundFloat32x4, types.TypeVec128), sys.AMD64)
        addF(simdPackage, "Float32x8.Round", opLen1(ssa.OpRoundFloat32x8, types.TypeVec256), sys.AMD64)
        addF(simdPackage, "Float64x2.Round", opLen1(ssa.OpRoundFloat64x2, types.TypeVec128), sys.AMD64)
@@ -1306,6 +1543,167 @@ func simdIntrinsics(addF func(pkg, fn string, b intrinsicBuilder, archFamilies .
        addF(simdPackage, "Uint16x8.SetElem", opLen2Imm8(ssa.OpSetElemUint16x8, types.TypeVec128, 0), sys.AMD64)
        addF(simdPackage, "Uint32x4.SetElem", opLen2Imm8(ssa.OpSetElemUint32x4, types.TypeVec128, 0), sys.AMD64)
        addF(simdPackage, "Uint64x2.SetElem", opLen2Imm8(ssa.OpSetElemUint64x2, types.TypeVec128, 0), sys.AMD64)
+       addF(simdPackage, "Int16x8.ShiftAllLeft", opLen2(ssa.OpShiftAllLeftInt16x8, types.TypeVec128), sys.AMD64)
+       addF(simdPackage, "Int16x16.ShiftAllLeft", opLen2(ssa.OpShiftAllLeftInt16x16, types.TypeVec256), sys.AMD64)
+       addF(simdPackage, "Int32x4.ShiftAllLeft", opLen2(ssa.OpShiftAllLeftInt32x4, types.TypeVec128), sys.AMD64)
+       addF(simdPackage, "Int32x8.ShiftAllLeft", opLen2(ssa.OpShiftAllLeftInt32x8, types.TypeVec256), sys.AMD64)
+       addF(simdPackage, "Int64x2.ShiftAllLeft", opLen2(ssa.OpShiftAllLeftInt64x2, types.TypeVec128), sys.AMD64)
+       addF(simdPackage, "Int64x4.ShiftAllLeft", opLen2(ssa.OpShiftAllLeftInt64x4, types.TypeVec256), sys.AMD64)
+       addF(simdPackage, "Int64x8.ShiftAllLeft", opLen2(ssa.OpShiftAllLeftInt64x8, types.TypeVec512), sys.AMD64)
+       addF(simdPackage, "Uint16x8.ShiftAllLeft", opLen2(ssa.OpShiftAllLeftUint16x8, types.TypeVec128), sys.AMD64)
+       addF(simdPackage, "Uint16x16.ShiftAllLeft", opLen2(ssa.OpShiftAllLeftUint16x16, types.TypeVec256), sys.AMD64)
+       addF(simdPackage, "Uint32x4.ShiftAllLeft", opLen2(ssa.OpShiftAllLeftUint32x4, types.TypeVec128), sys.AMD64)
+       addF(simdPackage, "Uint32x8.ShiftAllLeft", opLen2(ssa.OpShiftAllLeftUint32x8, types.TypeVec256), sys.AMD64)
+       addF(simdPackage, "Uint64x2.ShiftAllLeft", opLen2(ssa.OpShiftAllLeftUint64x2, types.TypeVec128), sys.AMD64)
+       addF(simdPackage, "Uint64x4.ShiftAllLeft", opLen2(ssa.OpShiftAllLeftUint64x4, types.TypeVec256), sys.AMD64)
+       addF(simdPackage, "Uint64x8.ShiftAllLeft", opLen2(ssa.OpShiftAllLeftUint64x8, types.TypeVec512), sys.AMD64)
+       addF(simdPackage, "Int16x8.ShiftAllLeftAndFillUpperFrom", opLen2Imm8(ssa.OpShiftAllLeftAndFillUpperFromInt16x8, types.TypeVec128, 0), sys.AMD64)
+       addF(simdPackage, "Int16x16.ShiftAllLeftAndFillUpperFrom", opLen2Imm8(ssa.OpShiftAllLeftAndFillUpperFromInt16x16, types.TypeVec256, 0), sys.AMD64)
+       addF(simdPackage, "Int16x32.ShiftAllLeftAndFillUpperFrom", opLen2Imm8(ssa.OpShiftAllLeftAndFillUpperFromInt16x32, types.TypeVec512, 0), sys.AMD64)
+       addF(simdPackage, "Int32x4.ShiftAllLeftAndFillUpperFrom", opLen2Imm8(ssa.OpShiftAllLeftAndFillUpperFromInt32x4, types.TypeVec128, 0), sys.AMD64)
+       addF(simdPackage, "Int32x8.ShiftAllLeftAndFillUpperFrom", opLen2Imm8(ssa.OpShiftAllLeftAndFillUpperFromInt32x8, types.TypeVec256, 0), sys.AMD64)
+       addF(simdPackage, "Int32x16.ShiftAllLeftAndFillUpperFrom", opLen2Imm8(ssa.OpShiftAllLeftAndFillUpperFromInt32x16, types.TypeVec512, 0), sys.AMD64)
+       addF(simdPackage, "Int64x2.ShiftAllLeftAndFillUpperFrom", opLen2Imm8(ssa.OpShiftAllLeftAndFillUpperFromInt64x2, types.TypeVec128, 0), sys.AMD64)
+       addF(simdPackage, "Int64x4.ShiftAllLeftAndFillUpperFrom", opLen2Imm8(ssa.OpShiftAllLeftAndFillUpperFromInt64x4, types.TypeVec256, 0), sys.AMD64)
+       addF(simdPackage, "Int64x8.ShiftAllLeftAndFillUpperFrom", opLen2Imm8(ssa.OpShiftAllLeftAndFillUpperFromInt64x8, types.TypeVec512, 0), sys.AMD64)
+       addF(simdPackage, "Uint16x8.ShiftAllLeftAndFillUpperFrom", opLen2Imm8(ssa.OpShiftAllLeftAndFillUpperFromUint16x8, types.TypeVec128, 0), sys.AMD64)
+       addF(simdPackage, "Uint16x16.ShiftAllLeftAndFillUpperFrom", opLen2Imm8(ssa.OpShiftAllLeftAndFillUpperFromUint16x16, types.TypeVec256, 0), sys.AMD64)
+       addF(simdPackage, "Uint16x32.ShiftAllLeftAndFillUpperFrom", opLen2Imm8(ssa.OpShiftAllLeftAndFillUpperFromUint16x32, types.TypeVec512, 0), sys.AMD64)
+       addF(simdPackage, "Uint32x4.ShiftAllLeftAndFillUpperFrom", opLen2Imm8(ssa.OpShiftAllLeftAndFillUpperFromUint32x4, types.TypeVec128, 0), sys.AMD64)
+       addF(simdPackage, "Uint32x8.ShiftAllLeftAndFillUpperFrom", opLen2Imm8(ssa.OpShiftAllLeftAndFillUpperFromUint32x8, types.TypeVec256, 0), sys.AMD64)
+       addF(simdPackage, "Uint32x16.ShiftAllLeftAndFillUpperFrom", opLen2Imm8(ssa.OpShiftAllLeftAndFillUpperFromUint32x16, types.TypeVec512, 0), sys.AMD64)
+       addF(simdPackage, "Uint64x2.ShiftAllLeftAndFillUpperFrom", opLen2Imm8(ssa.OpShiftAllLeftAndFillUpperFromUint64x2, types.TypeVec128, 0), sys.AMD64)
+       addF(simdPackage, "Uint64x4.ShiftAllLeftAndFillUpperFrom", opLen2Imm8(ssa.OpShiftAllLeftAndFillUpperFromUint64x4, types.TypeVec256, 0), sys.AMD64)
+       addF(simdPackage, "Uint64x8.ShiftAllLeftAndFillUpperFrom", opLen2Imm8(ssa.OpShiftAllLeftAndFillUpperFromUint64x8, types.TypeVec512, 0), sys.AMD64)
+       addF(simdPackage, "Int16x8.ShiftAllRight", opLen2(ssa.OpShiftAllRightInt16x8, types.TypeVec128), sys.AMD64)
+       addF(simdPackage, "Int16x16.ShiftAllRight", opLen2(ssa.OpShiftAllRightInt16x16, types.TypeVec256), sys.AMD64)
+       addF(simdPackage, "Int32x4.ShiftAllRight", opLen2(ssa.OpShiftAllRightInt32x4, types.TypeVec128), sys.AMD64)
+       addF(simdPackage, "Int32x8.ShiftAllRight", opLen2(ssa.OpShiftAllRightInt32x8, types.TypeVec256), sys.AMD64)
+       addF(simdPackage, "Int64x2.ShiftAllRight", opLen2(ssa.OpShiftAllRightInt64x2, types.TypeVec128), sys.AMD64)
+       addF(simdPackage, "Int64x4.ShiftAllRight", opLen2(ssa.OpShiftAllRightInt64x4, types.TypeVec256), sys.AMD64)
+       addF(simdPackage, "Int64x8.ShiftAllRight", opLen2(ssa.OpShiftAllRightInt64x8, types.TypeVec512), sys.AMD64)
+       addF(simdPackage, "Uint16x8.ShiftAllRight", opLen2(ssa.OpShiftAllRightUint16x8, types.TypeVec128), sys.AMD64)
+       addF(simdPackage, "Uint16x16.ShiftAllRight", opLen2(ssa.OpShiftAllRightUint16x16, types.TypeVec256), sys.AMD64)
+       addF(simdPackage, "Uint32x4.ShiftAllRight", opLen2(ssa.OpShiftAllRightUint32x4, types.TypeVec128), sys.AMD64)
+       addF(simdPackage, "Uint32x8.ShiftAllRight", opLen2(ssa.OpShiftAllRightUint32x8, types.TypeVec256), sys.AMD64)
+       addF(simdPackage, "Uint64x2.ShiftAllRight", opLen2(ssa.OpShiftAllRightUint64x2, types.TypeVec128), sys.AMD64)
+       addF(simdPackage, "Uint64x4.ShiftAllRight", opLen2(ssa.OpShiftAllRightUint64x4, types.TypeVec256), sys.AMD64)
+       addF(simdPackage, "Uint64x8.ShiftAllRight", opLen2(ssa.OpShiftAllRightUint64x8, types.TypeVec512), sys.AMD64)
+       addF(simdPackage, "Int16x8.ShiftAllRightAndFillUpperFrom", opLen2Imm8(ssa.OpShiftAllRightAndFillUpperFromInt16x8, types.TypeVec128, 0), sys.AMD64)
+       addF(simdPackage, "Int16x16.ShiftAllRightAndFillUpperFrom", opLen2Imm8(ssa.OpShiftAllRightAndFillUpperFromInt16x16, types.TypeVec256, 0), sys.AMD64)
+       addF(simdPackage, "Int16x32.ShiftAllRightAndFillUpperFrom", opLen2Imm8(ssa.OpShiftAllRightAndFillUpperFromInt16x32, types.TypeVec512, 0), sys.AMD64)
+       addF(simdPackage, "Int32x4.ShiftAllRightAndFillUpperFrom", opLen2Imm8(ssa.OpShiftAllRightAndFillUpperFromInt32x4, types.TypeVec128, 0), sys.AMD64)
+       addF(simdPackage, "Int32x8.ShiftAllRightAndFillUpperFrom", opLen2Imm8(ssa.OpShiftAllRightAndFillUpperFromInt32x8, types.TypeVec256, 0), sys.AMD64)
+       addF(simdPackage, "Int32x16.ShiftAllRightAndFillUpperFrom", opLen2Imm8(ssa.OpShiftAllRightAndFillUpperFromInt32x16, types.TypeVec512, 0), sys.AMD64)
+       addF(simdPackage, "Int64x2.ShiftAllRightAndFillUpperFrom", opLen2Imm8(ssa.OpShiftAllRightAndFillUpperFromInt64x2, types.TypeVec128, 0), sys.AMD64)
+       addF(simdPackage, "Int64x4.ShiftAllRightAndFillUpperFrom", opLen2Imm8(ssa.OpShiftAllRightAndFillUpperFromInt64x4, types.TypeVec256, 0), sys.AMD64)
+       addF(simdPackage, "Int64x8.ShiftAllRightAndFillUpperFrom", opLen2Imm8(ssa.OpShiftAllRightAndFillUpperFromInt64x8, types.TypeVec512, 0), sys.AMD64)
+       addF(simdPackage, "Uint16x8.ShiftAllRightAndFillUpperFrom", opLen2Imm8(ssa.OpShiftAllRightAndFillUpperFromUint16x8, types.TypeVec128, 0), sys.AMD64)
+       addF(simdPackage, "Uint16x16.ShiftAllRightAndFillUpperFrom", opLen2Imm8(ssa.OpShiftAllRightAndFillUpperFromUint16x16, types.TypeVec256, 0), sys.AMD64)
+       addF(simdPackage, "Uint16x32.ShiftAllRightAndFillUpperFrom", opLen2Imm8(ssa.OpShiftAllRightAndFillUpperFromUint16x32, types.TypeVec512, 0), sys.AMD64)
+       addF(simdPackage, "Uint32x4.ShiftAllRightAndFillUpperFrom", opLen2Imm8(ssa.OpShiftAllRightAndFillUpperFromUint32x4, types.TypeVec128, 0), sys.AMD64)
+       addF(simdPackage, "Uint32x8.ShiftAllRightAndFillUpperFrom", opLen2Imm8(ssa.OpShiftAllRightAndFillUpperFromUint32x8, types.TypeVec256, 0), sys.AMD64)
+       addF(simdPackage, "Uint32x16.ShiftAllRightAndFillUpperFrom", opLen2Imm8(ssa.OpShiftAllRightAndFillUpperFromUint32x16, types.TypeVec512, 0), sys.AMD64)
+       addF(simdPackage, "Uint64x2.ShiftAllRightAndFillUpperFrom", opLen2Imm8(ssa.OpShiftAllRightAndFillUpperFromUint64x2, types.TypeVec128, 0), sys.AMD64)
+       addF(simdPackage, "Uint64x4.ShiftAllRightAndFillUpperFrom", opLen2Imm8(ssa.OpShiftAllRightAndFillUpperFromUint64x4, types.TypeVec256, 0), sys.AMD64)
+       addF(simdPackage, "Uint64x8.ShiftAllRightAndFillUpperFrom", opLen2Imm8(ssa.OpShiftAllRightAndFillUpperFromUint64x8, types.TypeVec512, 0), sys.AMD64)
+       addF(simdPackage, "Int16x8.ShiftAllRightSignExtended", opLen2(ssa.OpShiftAllRightSignExtendedInt16x8, types.TypeVec128), sys.AMD64)
+       addF(simdPackage, "Int16x16.ShiftAllRightSignExtended", opLen2(ssa.OpShiftAllRightSignExtendedInt16x16, types.TypeVec256), sys.AMD64)
+       addF(simdPackage, "Int32x4.ShiftAllRightSignExtended", opLen2(ssa.OpShiftAllRightSignExtendedInt32x4, types.TypeVec128), sys.AMD64)
+       addF(simdPackage, "Int32x8.ShiftAllRightSignExtended", opLen2(ssa.OpShiftAllRightSignExtendedInt32x8, types.TypeVec256), sys.AMD64)
+       addF(simdPackage, "Int64x2.ShiftAllRightSignExtended", opLen2(ssa.OpShiftAllRightSignExtendedInt64x2, types.TypeVec128), sys.AMD64)
+       addF(simdPackage, "Int64x4.ShiftAllRightSignExtended", opLen2(ssa.OpShiftAllRightSignExtendedInt64x4, types.TypeVec256), sys.AMD64)
+       addF(simdPackage, "Int64x8.ShiftAllRightSignExtended", opLen2(ssa.OpShiftAllRightSignExtendedInt64x8, types.TypeVec512), sys.AMD64)
+       addF(simdPackage, "Int16x8.ShiftLeft", opLen2(ssa.OpShiftLeftInt16x8, types.TypeVec128), sys.AMD64)
+       addF(simdPackage, "Int16x16.ShiftLeft", opLen2(ssa.OpShiftLeftInt16x16, types.TypeVec256), sys.AMD64)
+       addF(simdPackage, "Int16x32.ShiftLeft", opLen2(ssa.OpShiftLeftInt16x32, types.TypeVec512), sys.AMD64)
+       addF(simdPackage, "Int32x4.ShiftLeft", opLen2(ssa.OpShiftLeftInt32x4, types.TypeVec128), sys.AMD64)
+       addF(simdPackage, "Int32x8.ShiftLeft", opLen2(ssa.OpShiftLeftInt32x8, types.TypeVec256), sys.AMD64)
+       addF(simdPackage, "Int32x16.ShiftLeft", opLen2(ssa.OpShiftLeftInt32x16, types.TypeVec512), sys.AMD64)
+       addF(simdPackage, "Int64x2.ShiftLeft", opLen2(ssa.OpShiftLeftInt64x2, types.TypeVec128), sys.AMD64)
+       addF(simdPackage, "Int64x4.ShiftLeft", opLen2(ssa.OpShiftLeftInt64x4, types.TypeVec256), sys.AMD64)
+       addF(simdPackage, "Int64x8.ShiftLeft", opLen2(ssa.OpShiftLeftInt64x8, types.TypeVec512), sys.AMD64)
+       addF(simdPackage, "Uint16x8.ShiftLeft", opLen2(ssa.OpShiftLeftUint16x8, types.TypeVec128), sys.AMD64)
+       addF(simdPackage, "Uint16x16.ShiftLeft", opLen2(ssa.OpShiftLeftUint16x16, types.TypeVec256), sys.AMD64)
+       addF(simdPackage, "Uint16x32.ShiftLeft", opLen2(ssa.OpShiftLeftUint16x32, types.TypeVec512), sys.AMD64)
+       addF(simdPackage, "Uint32x4.ShiftLeft", opLen2(ssa.OpShiftLeftUint32x4, types.TypeVec128), sys.AMD64)
+       addF(simdPackage, "Uint32x8.ShiftLeft", opLen2(ssa.OpShiftLeftUint32x8, types.TypeVec256), sys.AMD64)
+       addF(simdPackage, "Uint32x16.ShiftLeft", opLen2(ssa.OpShiftLeftUint32x16, types.TypeVec512), sys.AMD64)
+       addF(simdPackage, "Uint64x2.ShiftLeft", opLen2(ssa.OpShiftLeftUint64x2, types.TypeVec128), sys.AMD64)
+       addF(simdPackage, "Uint64x4.ShiftLeft", opLen2(ssa.OpShiftLeftUint64x4, types.TypeVec256), sys.AMD64)
+       addF(simdPackage, "Uint64x8.ShiftLeft", opLen2(ssa.OpShiftLeftUint64x8, types.TypeVec512), sys.AMD64)
+       addF(simdPackage, "Int16x8.ShiftLeftAndFillUpperFrom", opLen3(ssa.OpShiftLeftAndFillUpperFromInt16x8, types.TypeVec128), sys.AMD64)
+       addF(simdPackage, "Int16x16.ShiftLeftAndFillUpperFrom", opLen3(ssa.OpShiftLeftAndFillUpperFromInt16x16, types.TypeVec256), sys.AMD64)
+       addF(simdPackage, "Int16x32.ShiftLeftAndFillUpperFrom", opLen3(ssa.OpShiftLeftAndFillUpperFromInt16x32, types.TypeVec512), sys.AMD64)
+       addF(simdPackage, "Int32x4.ShiftLeftAndFillUpperFrom", opLen3(ssa.OpShiftLeftAndFillUpperFromInt32x4, types.TypeVec128), sys.AMD64)
+       addF(simdPackage, "Int32x8.ShiftLeftAndFillUpperFrom", opLen3(ssa.OpShiftLeftAndFillUpperFromInt32x8, types.TypeVec256), sys.AMD64)
+       addF(simdPackage, "Int32x16.ShiftLeftAndFillUpperFrom", opLen3(ssa.OpShiftLeftAndFillUpperFromInt32x16, types.TypeVec512), sys.AMD64)
+       addF(simdPackage, "Int64x2.ShiftLeftAndFillUpperFrom", opLen3(ssa.OpShiftLeftAndFillUpperFromInt64x2, types.TypeVec128), sys.AMD64)
+       addF(simdPackage, "Int64x4.ShiftLeftAndFillUpperFrom", opLen3(ssa.OpShiftLeftAndFillUpperFromInt64x4, types.TypeVec256), sys.AMD64)
+       addF(simdPackage, "Int64x8.ShiftLeftAndFillUpperFrom", opLen3(ssa.OpShiftLeftAndFillUpperFromInt64x8, types.TypeVec512), sys.AMD64)
+       addF(simdPackage, "Uint16x8.ShiftLeftAndFillUpperFrom", opLen3(ssa.OpShiftLeftAndFillUpperFromUint16x8, types.TypeVec128), sys.AMD64)
+       addF(simdPackage, "Uint16x16.ShiftLeftAndFillUpperFrom", opLen3(ssa.OpShiftLeftAndFillUpperFromUint16x16, types.TypeVec256), sys.AMD64)
+       addF(simdPackage, "Uint16x32.ShiftLeftAndFillUpperFrom", opLen3(ssa.OpShiftLeftAndFillUpperFromUint16x32, types.TypeVec512), sys.AMD64)
+       addF(simdPackage, "Uint32x4.ShiftLeftAndFillUpperFrom", opLen3(ssa.OpShiftLeftAndFillUpperFromUint32x4, types.TypeVec128), sys.AMD64)
+       addF(simdPackage, "Uint32x8.ShiftLeftAndFillUpperFrom", opLen3(ssa.OpShiftLeftAndFillUpperFromUint32x8, types.TypeVec256), sys.AMD64)
+       addF(simdPackage, "Uint32x16.ShiftLeftAndFillUpperFrom", opLen3(ssa.OpShiftLeftAndFillUpperFromUint32x16, types.TypeVec512), sys.AMD64)
+       addF(simdPackage, "Uint64x2.ShiftLeftAndFillUpperFrom", opLen3(ssa.OpShiftLeftAndFillUpperFromUint64x2, types.TypeVec128), sys.AMD64)
+       addF(simdPackage, "Uint64x4.ShiftLeftAndFillUpperFrom", opLen3(ssa.OpShiftLeftAndFillUpperFromUint64x4, types.TypeVec256), sys.AMD64)
+       addF(simdPackage, "Uint64x8.ShiftLeftAndFillUpperFrom", opLen3(ssa.OpShiftLeftAndFillUpperFromUint64x8, types.TypeVec512), sys.AMD64)
+       addF(simdPackage, "Int16x8.ShiftRight", opLen2(ssa.OpShiftRightInt16x8, types.TypeVec128), sys.AMD64)
+       addF(simdPackage, "Int16x16.ShiftRight", opLen2(ssa.OpShiftRightInt16x16, types.TypeVec256), sys.AMD64)
+       addF(simdPackage, "Int16x32.ShiftRight", opLen2(ssa.OpShiftRightInt16x32, types.TypeVec512), sys.AMD64)
+       addF(simdPackage, "Int32x4.ShiftRight", opLen2(ssa.OpShiftRightInt32x4, types.TypeVec128), sys.AMD64)
+       addF(simdPackage, "Int32x8.ShiftRight", opLen2(ssa.OpShiftRightInt32x8, types.TypeVec256), sys.AMD64)
+       addF(simdPackage, "Int32x16.ShiftRight", opLen2(ssa.OpShiftRightInt32x16, types.TypeVec512), sys.AMD64)
+       addF(simdPackage, "Int64x2.ShiftRight", opLen2(ssa.OpShiftRightInt64x2, types.TypeVec128), sys.AMD64)
+       addF(simdPackage, "Int64x4.ShiftRight", opLen2(ssa.OpShiftRightInt64x4, types.TypeVec256), sys.AMD64)
+       addF(simdPackage, "Int64x8.ShiftRight", opLen2(ssa.OpShiftRightInt64x8, types.TypeVec512), sys.AMD64)
+       addF(simdPackage, "Uint16x8.ShiftRight", opLen2(ssa.OpShiftRightUint16x8, types.TypeVec128), sys.AMD64)
+       addF(simdPackage, "Uint16x16.ShiftRight", opLen2(ssa.OpShiftRightUint16x16, types.TypeVec256), sys.AMD64)
+       addF(simdPackage, "Uint16x32.ShiftRight", opLen2(ssa.OpShiftRightUint16x32, types.TypeVec512), sys.AMD64)
+       addF(simdPackage, "Uint32x4.ShiftRight", opLen2(ssa.OpShiftRightUint32x4, types.TypeVec128), sys.AMD64)
+       addF(simdPackage, "Uint32x8.ShiftRight", opLen2(ssa.OpShiftRightUint32x8, types.TypeVec256), sys.AMD64)
+       addF(simdPackage, "Uint32x16.ShiftRight", opLen2(ssa.OpShiftRightUint32x16, types.TypeVec512), sys.AMD64)
+       addF(simdPackage, "Uint64x2.ShiftRight", opLen2(ssa.OpShiftRightUint64x2, types.TypeVec128), sys.AMD64)
+       addF(simdPackage, "Uint64x4.ShiftRight", opLen2(ssa.OpShiftRightUint64x4, types.TypeVec256), sys.AMD64)
+       addF(simdPackage, "Uint64x8.ShiftRight", opLen2(ssa.OpShiftRightUint64x8, types.TypeVec512), sys.AMD64)
+       addF(simdPackage, "Int16x8.ShiftRightAndFillUpperFrom", opLen3(ssa.OpShiftRightAndFillUpperFromInt16x8, types.TypeVec128), sys.AMD64)
+       addF(simdPackage, "Int16x16.ShiftRightAndFillUpperFrom", opLen3(ssa.OpShiftRightAndFillUpperFromInt16x16, types.TypeVec256), sys.AMD64)
+       addF(simdPackage, "Int16x32.ShiftRightAndFillUpperFrom", opLen3(ssa.OpShiftRightAndFillUpperFromInt16x32, types.TypeVec512), sys.AMD64)
+       addF(simdPackage, "Int32x4.ShiftRightAndFillUpperFrom", opLen3(ssa.OpShiftRightAndFillUpperFromInt32x4, types.TypeVec128), sys.AMD64)
+       addF(simdPackage, "Int32x8.ShiftRightAndFillUpperFrom", opLen3(ssa.OpShiftRightAndFillUpperFromInt32x8, types.TypeVec256), sys.AMD64)
+       addF(simdPackage, "Int32x16.ShiftRightAndFillUpperFrom", opLen3(ssa.OpShiftRightAndFillUpperFromInt32x16, types.TypeVec512), sys.AMD64)
+       addF(simdPackage, "Int64x2.ShiftRightAndFillUpperFrom", opLen3(ssa.OpShiftRightAndFillUpperFromInt64x2, types.TypeVec128), sys.AMD64)
+       addF(simdPackage, "Int64x4.ShiftRightAndFillUpperFrom", opLen3(ssa.OpShiftRightAndFillUpperFromInt64x4, types.TypeVec256), sys.AMD64)
+       addF(simdPackage, "Int64x8.ShiftRightAndFillUpperFrom", opLen3(ssa.OpShiftRightAndFillUpperFromInt64x8, types.TypeVec512), sys.AMD64)
+       addF(simdPackage, "Uint16x8.ShiftRightAndFillUpperFrom", opLen3(ssa.OpShiftRightAndFillUpperFromUint16x8, types.TypeVec128), sys.AMD64)
+       addF(simdPackage, "Uint16x16.ShiftRightAndFillUpperFrom", opLen3(ssa.OpShiftRightAndFillUpperFromUint16x16, types.TypeVec256), sys.AMD64)
+       addF(simdPackage, "Uint16x32.ShiftRightAndFillUpperFrom", opLen3(ssa.OpShiftRightAndFillUpperFromUint16x32, types.TypeVec512), sys.AMD64)
+       addF(simdPackage, "Uint32x4.ShiftRightAndFillUpperFrom", opLen3(ssa.OpShiftRightAndFillUpperFromUint32x4, types.TypeVec128), sys.AMD64)
+       addF(simdPackage, "Uint32x8.ShiftRightAndFillUpperFrom", opLen3(ssa.OpShiftRightAndFillUpperFromUint32x8, types.TypeVec256), sys.AMD64)
+       addF(simdPackage, "Uint32x16.ShiftRightAndFillUpperFrom", opLen3(ssa.OpShiftRightAndFillUpperFromUint32x16, types.TypeVec512), sys.AMD64)
+       addF(simdPackage, "Uint64x2.ShiftRightAndFillUpperFrom", opLen3(ssa.OpShiftRightAndFillUpperFromUint64x2, types.TypeVec128), sys.AMD64)
+       addF(simdPackage, "Uint64x4.ShiftRightAndFillUpperFrom", opLen3(ssa.OpShiftRightAndFillUpperFromUint64x4, types.TypeVec256), sys.AMD64)
+       addF(simdPackage, "Uint64x8.ShiftRightAndFillUpperFrom", opLen3(ssa.OpShiftRightAndFillUpperFromUint64x8, types.TypeVec512), sys.AMD64)
+       addF(simdPackage, "Int16x8.ShiftRightSignExtended", opLen2(ssa.OpShiftRightSignExtendedInt16x8, types.TypeVec128), sys.AMD64)
+       addF(simdPackage, "Int16x16.ShiftRightSignExtended", opLen2(ssa.OpShiftRightSignExtendedInt16x16, types.TypeVec256), sys.AMD64)
+       addF(simdPackage, "Int16x32.ShiftRightSignExtended", opLen2(ssa.OpShiftRightSignExtendedInt16x32, types.TypeVec512), sys.AMD64)
+       addF(simdPackage, "Int32x4.ShiftRightSignExtended", opLen2(ssa.OpShiftRightSignExtendedInt32x4, types.TypeVec128), sys.AMD64)
+       addF(simdPackage, "Int32x8.ShiftRightSignExtended", opLen2(ssa.OpShiftRightSignExtendedInt32x8, types.TypeVec256), sys.AMD64)
+       addF(simdPackage, "Int32x16.ShiftRightSignExtended", opLen2(ssa.OpShiftRightSignExtendedInt32x16, types.TypeVec512), sys.AMD64)
+       addF(simdPackage, "Int64x2.ShiftRightSignExtended", opLen2(ssa.OpShiftRightSignExtendedInt64x2, types.TypeVec128), sys.AMD64)
+       addF(simdPackage, "Int64x4.ShiftRightSignExtended", opLen2(ssa.OpShiftRightSignExtendedInt64x4, types.TypeVec256), sys.AMD64)
+       addF(simdPackage, "Int64x8.ShiftRightSignExtended", opLen2(ssa.OpShiftRightSignExtendedInt64x8, types.TypeVec512), sys.AMD64)
+       addF(simdPackage, "Uint16x8.ShiftRightSignExtended", opLen2(ssa.OpShiftRightSignExtendedUint16x8, types.TypeVec128), sys.AMD64)
+       addF(simdPackage, "Uint16x16.ShiftRightSignExtended", opLen2(ssa.OpShiftRightSignExtendedUint16x16, types.TypeVec256), sys.AMD64)
+       addF(simdPackage, "Uint16x32.ShiftRightSignExtended", opLen2(ssa.OpShiftRightSignExtendedUint16x32, types.TypeVec512), sys.AMD64)
+       addF(simdPackage, "Uint32x4.ShiftRightSignExtended", opLen2(ssa.OpShiftRightSignExtendedUint32x4, types.TypeVec128), sys.AMD64)
+       addF(simdPackage, "Uint32x8.ShiftRightSignExtended", opLen2(ssa.OpShiftRightSignExtendedUint32x8, types.TypeVec256), sys.AMD64)
+       addF(simdPackage, "Uint32x16.ShiftRightSignExtended", opLen2(ssa.OpShiftRightSignExtendedUint32x16, types.TypeVec512), sys.AMD64)
+       addF(simdPackage, "Uint64x2.ShiftRightSignExtended", opLen2(ssa.OpShiftRightSignExtendedUint64x2, types.TypeVec128), sys.AMD64)
+       addF(simdPackage, "Uint64x4.ShiftRightSignExtended", opLen2(ssa.OpShiftRightSignExtendedUint64x4, types.TypeVec256), sys.AMD64)
+       addF(simdPackage, "Uint64x8.ShiftRightSignExtended", opLen2(ssa.OpShiftRightSignExtendedUint64x8, types.TypeVec512), sys.AMD64)
        addF(simdPackage, "Int8x16.Sign", opLen2(ssa.OpSignInt8x16, types.TypeVec128), sys.AMD64)
        addF(simdPackage, "Int8x32.Sign", opLen2(ssa.OpSignInt8x32, types.TypeVec256), sys.AMD64)
        addF(simdPackage, "Int16x8.Sign", opLen2(ssa.OpSignInt16x8, types.TypeVec128), sys.AMD64)

diff --git a/src/simd/simd_wrapped_test.go b/src/simd/simd_wrapped_test.go
index b5f6bb517a318f83dfe9b3175b0c5a3b2274b2ab..ad828e9d3f81c32585df78ef11c0d989fe2ef89b 100644 (file)
--- a/src/simd/simd_wrapped_test.go
+++ b/src/simd/simd_wrapped_test.go
@@ -2147,6 +2147,12 @@ func testInt16x8Binary(t *testing.T, v0 []int16, v1 []int16, want []int16, which
                gotv = vec0.SaturatedPairwiseSub(vec1)
        case "SaturatedSub":
                gotv = vec0.SaturatedSub(vec1)
+       case "ShiftLeft":
+               gotv = vec0.ShiftLeft(vec1)
+       case "ShiftRight":
+               gotv = vec0.ShiftRight(vec1)
+       case "ShiftRightSignExtended":
+               gotv = vec0.ShiftRightSignExtended(vec1)
        case "Sign":
                gotv = vec0.Sign(vec1)
        case "Sub":
@@ -2187,6 +2193,12 @@ func testInt16x8BinaryMasked(t *testing.T, v0 []int16, v1 []int16, v2 []int16, w
                gotv = vec0.MaskedSaturatedAdd(vec1, vec2.AsMask16x8())
        case "MaskedSaturatedSub":
                gotv = vec0.MaskedSaturatedSub(vec1, vec2.AsMask16x8())
+       case "MaskedShiftLeft":
+               gotv = vec0.MaskedShiftLeft(vec1, vec2.AsMask16x8())
+       case "MaskedShiftRight":
+               gotv = vec0.MaskedShiftRight(vec1, vec2.AsMask16x8())
+       case "MaskedShiftRightSignExtended":
+               gotv = vec0.MaskedShiftRightSignExtended(vec1, vec2.AsMask16x8())
        case "MaskedSub":
                gotv = vec0.MaskedSub(vec1, vec2.AsMask16x8())
 
@@ -2307,6 +2319,55 @@ func testInt16x8MaskedCompare(t *testing.T, v0 []int16, v1 []int16, v2 []int16,
        }
 }
 
+func testInt16x8Ternary(t *testing.T, v0 []int16, v1 []int16, v2 []int16, want []int16, which string) {
+       t.Helper()
+       var gotv simd.Int16x8
+       got := make([]int16, len(want))
+       vec0 := simd.LoadInt16x8Slice(v0)
+       vec1 := simd.LoadInt16x8Slice(v1)
+       vec2 := simd.LoadInt16x8Slice(v2)
+       switch which {
+       case "ShiftLeftAndFillUpperFrom":
+               gotv = vec0.ShiftLeftAndFillUpperFrom(vec1, vec2)
+       case "ShiftRightAndFillUpperFrom":
+               gotv = vec0.ShiftRightAndFillUpperFrom(vec1, vec2)
+
+       default:
+               t.Errorf("Unknown method: Int16x8.%s", which)
+       }
+       gotv.StoreSlice(got)
+       for i := range len(want) {
+               if got[i] != want[i] {
+                       t.Errorf("Result at %d incorrect: want %v, got %v", i, want[i], got[i])
+               }
+       }
+}
+
+func testInt16x8TernaryMasked(t *testing.T, v0 []int16, v1 []int16, v2 []int16, v3 []int16, want []int16, which string) {
+       t.Helper()
+       var gotv simd.Int16x8
+       got := make([]int16, len(want))
+       vec0 := simd.LoadInt16x8Slice(v0)
+       vec1 := simd.LoadInt16x8Slice(v1)
+       vec2 := simd.LoadInt16x8Slice(v2)
+       vec3 := simd.LoadInt16x8Slice(v3)
+       switch which {
+       case "MaskedShiftLeftAndFillUpperFrom":
+               gotv = vec0.MaskedShiftLeftAndFillUpperFrom(vec1, vec2, vec3.AsMask16x8())
+       case "MaskedShiftRightAndFillUpperFrom":
+               gotv = vec0.MaskedShiftRightAndFillUpperFrom(vec1, vec2, vec3.AsMask16x8())
+
+       default:
+               t.Errorf("Unknown method: Int16x8.%s", which)
+       }
+       gotv.StoreSlice(got)
+       for i := range len(want) {
+               if got[i] != want[i] {
+                       t.Errorf("Result at %d incorrect: want %v, got %v", i, want[i], got[i])
+               }
+       }
+}
+
 func testInt16x8Unary(t *testing.T, v0 []int16, want []int16, which string) {
        t.Helper()
        var gotv simd.Int16x8
@@ -2387,6 +2448,12 @@ func testInt16x16Binary(t *testing.T, v0 []int16, v1 []int16, want []int16, whic
                gotv = vec0.SaturatedPairwiseSub(vec1)
        case "SaturatedSub":
                gotv = vec0.SaturatedSub(vec1)
+       case "ShiftLeft":
+               gotv = vec0.ShiftLeft(vec1)
+       case "ShiftRight":
+               gotv = vec0.ShiftRight(vec1)
+       case "ShiftRightSignExtended":
+               gotv = vec0.ShiftRightSignExtended(vec1)
        case "Sign":
                gotv = vec0.Sign(vec1)
        case "Sub":
@@ -2427,6 +2494,12 @@ func testInt16x16BinaryMasked(t *testing.T, v0 []int16, v1 []int16, v2 []int16,
                gotv = vec0.MaskedSaturatedAdd(vec1, vec2.AsMask16x16())
        case "MaskedSaturatedSub":
                gotv = vec0.MaskedSaturatedSub(vec1, vec2.AsMask16x16())
+       case "MaskedShiftLeft":
+               gotv = vec0.MaskedShiftLeft(vec1, vec2.AsMask16x16())
+       case "MaskedShiftRight":
+               gotv = vec0.MaskedShiftRight(vec1, vec2.AsMask16x16())
+       case "MaskedShiftRightSignExtended":
+               gotv = vec0.MaskedShiftRightSignExtended(vec1, vec2.AsMask16x16())
        case "MaskedSub":
                gotv = vec0.MaskedSub(vec1, vec2.AsMask16x16())
 
@@ -2547,6 +2620,55 @@ func testInt16x16MaskedCompare(t *testing.T, v0 []int16, v1 []int16, v2 []int16,
        }
 }
 
+func testInt16x16Ternary(t *testing.T, v0 []int16, v1 []int16, v2 []int16, want []int16, which string) {
+       t.Helper()
+       var gotv simd.Int16x16
+       got := make([]int16, len(want))
+       vec0 := simd.LoadInt16x16Slice(v0)
+       vec1 := simd.LoadInt16x16Slice(v1)
+       vec2 := simd.LoadInt16x16Slice(v2)
+       switch which {
+       case "ShiftLeftAndFillUpperFrom":
+               gotv = vec0.ShiftLeftAndFillUpperFrom(vec1, vec2)
+       case "ShiftRightAndFillUpperFrom":
+               gotv = vec0.ShiftRightAndFillUpperFrom(vec1, vec2)
+
+       default:
+               t.Errorf("Unknown method: Int16x16.%s", which)
+       }
+       gotv.StoreSlice(got)
+       for i := range len(want) {
+               if got[i] != want[i] {
+                       t.Errorf("Result at %d incorrect: want %v, got %v", i, want[i], got[i])
+               }
+       }
+}
+
+func testInt16x16TernaryMasked(t *testing.T, v0 []int16, v1 []int16, v2 []int16, v3 []int16, want []int16, which string) {
+       t.Helper()
+       var gotv simd.Int16x16
+       got := make([]int16, len(want))
+       vec0 := simd.LoadInt16x16Slice(v0)
+       vec1 := simd.LoadInt16x16Slice(v1)
+       vec2 := simd.LoadInt16x16Slice(v2)
+       vec3 := simd.LoadInt16x16Slice(v3)
+       switch which {
+       case "MaskedShiftLeftAndFillUpperFrom":
+               gotv = vec0.MaskedShiftLeftAndFillUpperFrom(vec1, vec2, vec3.AsMask16x16())
+       case "MaskedShiftRightAndFillUpperFrom":
+               gotv = vec0.MaskedShiftRightAndFillUpperFrom(vec1, vec2, vec3.AsMask16x16())
+
+       default:
+               t.Errorf("Unknown method: Int16x16.%s", which)
+       }
+       gotv.StoreSlice(got)
+       for i := range len(want) {
+               if got[i] != want[i] {
+                       t.Errorf("Result at %d incorrect: want %v, got %v", i, want[i], got[i])
+               }
+       }
+}
+
 func testInt16x16Unary(t *testing.T, v0 []int16, want []int16, which string) {
        t.Helper()
        var gotv simd.Int16x16
@@ -2613,6 +2735,12 @@ func testInt16x32Binary(t *testing.T, v0 []int16, v1 []int16, want []int16, whic
                gotv = vec0.SaturatedAdd(vec1)
        case "SaturatedSub":
                gotv = vec0.SaturatedSub(vec1)
+       case "ShiftLeft":
+               gotv = vec0.ShiftLeft(vec1)
+       case "ShiftRight":
+               gotv = vec0.ShiftRight(vec1)
+       case "ShiftRightSignExtended":
+               gotv = vec0.ShiftRightSignExtended(vec1)
        case "Sub":
                gotv = vec0.Sub(vec1)
 
@@ -2649,6 +2777,12 @@ func testInt16x32BinaryMasked(t *testing.T, v0 []int16, v1 []int16, v2 []int16,
                gotv = vec0.MaskedSaturatedAdd(vec1, vec2.AsMask16x32())
        case "MaskedSaturatedSub":
                gotv = vec0.MaskedSaturatedSub(vec1, vec2.AsMask16x32())
+       case "MaskedShiftLeft":
+               gotv = vec0.MaskedShiftLeft(vec1, vec2.AsMask16x32())
+       case "MaskedShiftRight":
+               gotv = vec0.MaskedShiftRight(vec1, vec2.AsMask16x32())
+       case "MaskedShiftRightSignExtended":
+               gotv = vec0.MaskedShiftRightSignExtended(vec1, vec2.AsMask16x32())
        case "MaskedSub":
                gotv = vec0.MaskedSub(vec1, vec2.AsMask16x32())
 
@@ -2769,6 +2903,55 @@ func testInt16x32MaskedCompare(t *testing.T, v0 []int16, v1 []int16, v2 []int16,
        }
 }
 
+func testInt16x32Ternary(t *testing.T, v0 []int16, v1 []int16, v2 []int16, want []int16, which string) {
+       t.Helper()
+       var gotv simd.Int16x32
+       got := make([]int16, len(want))
+       vec0 := simd.LoadInt16x32Slice(v0)
+       vec1 := simd.LoadInt16x32Slice(v1)
+       vec2 := simd.LoadInt16x32Slice(v2)
+       switch which {
+       case "ShiftLeftAndFillUpperFrom":
+               gotv = vec0.ShiftLeftAndFillUpperFrom(vec1, vec2)
+       case "ShiftRightAndFillUpperFrom":
+               gotv = vec0.ShiftRightAndFillUpperFrom(vec1, vec2)
+
+       default:
+               t.Errorf("Unknown method: Int16x32.%s", which)
+       }
+       gotv.StoreSlice(got)
+       for i := range len(want) {
+               if got[i] != want[i] {
+                       t.Errorf("Result at %d incorrect: want %v, got %v", i, want[i], got[i])
+               }
+       }
+}
+
+func testInt16x32TernaryMasked(t *testing.T, v0 []int16, v1 []int16, v2 []int16, v3 []int16, want []int16, which string) {
+       t.Helper()
+       var gotv simd.Int16x32
+       got := make([]int16, len(want))
+       vec0 := simd.LoadInt16x32Slice(v0)
+       vec1 := simd.LoadInt16x32Slice(v1)
+       vec2 := simd.LoadInt16x32Slice(v2)
+       vec3 := simd.LoadInt16x32Slice(v3)
+       switch which {
+       case "MaskedShiftLeftAndFillUpperFrom":
+               gotv = vec0.MaskedShiftLeftAndFillUpperFrom(vec1, vec2, vec3.AsMask16x32())
+       case "MaskedShiftRightAndFillUpperFrom":
+               gotv = vec0.MaskedShiftRightAndFillUpperFrom(vec1, vec2, vec3.AsMask16x32())
+
+       default:
+               t.Errorf("Unknown method: Int16x32.%s", which)
+       }
+       gotv.StoreSlice(got)
+       for i := range len(want) {
+               if got[i] != want[i] {
+                       t.Errorf("Result at %d incorrect: want %v, got %v", i, want[i], got[i])
+               }
+       }
+}
+
 func testInt16x32Unary(t *testing.T, v0 []int16, want []int16, which string) {
        t.Helper()
        var gotv simd.Int16x32
@@ -2839,6 +3022,16 @@ func testInt32x4Binary(t *testing.T, v0 []int32, v1 []int32, want []int32, which
                gotv = vec0.PairwiseAdd(vec1)
        case "PairwiseSub":
                gotv = vec0.PairwiseSub(vec1)
+       case "RotateLeft":
+               gotv = vec0.RotateLeft(vec1)
+       case "RotateRight":
+               gotv = vec0.RotateRight(vec1)
+       case "ShiftLeft":
+               gotv = vec0.ShiftLeft(vec1)
+       case "ShiftRight":
+               gotv = vec0.ShiftRight(vec1)
+       case "ShiftRightSignExtended":
+               gotv = vec0.ShiftRightSignExtended(vec1)
        case "Sign":
                gotv = vec0.Sign(vec1)
        case "Sub":
@@ -2879,6 +3072,16 @@ func testInt32x4BinaryMasked(t *testing.T, v0 []int32, v1 []int32, v2 []int32, w
                gotv = vec0.MaskedMulLow(vec1, vec2.AsMask32x4())
        case "MaskedOr":
                gotv = vec0.MaskedOr(vec1, vec2.AsMask32x4())
+       case "MaskedRotateLeft":
+               gotv = vec0.MaskedRotateLeft(vec1, vec2.AsMask32x4())
+       case "MaskedRotateRight":
+               gotv = vec0.MaskedRotateRight(vec1, vec2.AsMask32x4())
+       case "MaskedShiftLeft":
+               gotv = vec0.MaskedShiftLeft(vec1, vec2.AsMask32x4())
+       case "MaskedShiftRight":
+               gotv = vec0.MaskedShiftRight(vec1, vec2.AsMask32x4())
+       case "MaskedShiftRightSignExtended":
+               gotv = vec0.MaskedShiftRightSignExtended(vec1, vec2.AsMask32x4())
        case "MaskedSub":
                gotv = vec0.MaskedSub(vec1, vec2.AsMask32x4())
        case "MaskedXor":
@@ -3028,6 +3231,55 @@ func testInt32x4MaskedCompare(t *testing.T, v0 []int32, v1 []int32, v2 []int32,
        }
 }
 
+func testInt32x4Ternary(t *testing.T, v0 []int32, v1 []int32, v2 []int32, want []int32, which string) {
+       t.Helper()
+       var gotv simd.Int32x4
+       got := make([]int32, len(want))
+       vec0 := simd.LoadInt32x4Slice(v0)
+       vec1 := simd.LoadInt32x4Slice(v1)
+       vec2 := simd.LoadInt32x4Slice(v2)
+       switch which {
+       case "ShiftLeftAndFillUpperFrom":
+               gotv = vec0.ShiftLeftAndFillUpperFrom(vec1, vec2)
+       case "ShiftRightAndFillUpperFrom":
+               gotv = vec0.ShiftRightAndFillUpperFrom(vec1, vec2)
+
+       default:
+               t.Errorf("Unknown method: Int32x4.%s", which)
+       }
+       gotv.StoreSlice(got)
+       for i := range len(want) {
+               if got[i] != want[i] {
+                       t.Errorf("Result at %d incorrect: want %v, got %v", i, want[i], got[i])
+               }
+       }
+}
+
+func testInt32x4TernaryMasked(t *testing.T, v0 []int32, v1 []int32, v2 []int32, v3 []int32, want []int32, which string) {
+       t.Helper()
+       var gotv simd.Int32x4
+       got := make([]int32, len(want))
+       vec0 := simd.LoadInt32x4Slice(v0)
+       vec1 := simd.LoadInt32x4Slice(v1)
+       vec2 := simd.LoadInt32x4Slice(v2)
+       vec3 := simd.LoadInt32x4Slice(v3)
+       switch which {
+       case "MaskedShiftLeftAndFillUpperFrom":
+               gotv = vec0.MaskedShiftLeftAndFillUpperFrom(vec1, vec2, vec3.AsMask32x4())
+       case "MaskedShiftRightAndFillUpperFrom":
+               gotv = vec0.MaskedShiftRightAndFillUpperFrom(vec1, vec2, vec3.AsMask32x4())
+
+       default:
+               t.Errorf("Unknown method: Int32x4.%s", which)
+       }
+       gotv.StoreSlice(got)
+       for i := range len(want) {
+               if got[i] != want[i] {
+                       t.Errorf("Result at %d incorrect: want %v, got %v", i, want[i], got[i])
+               }
+       }
+}
+
 func testInt32x4Uint8x16Int8x16Int32x4(t *testing.T, v0 []int32, v1 []uint8, v2 []int8, want []int32, which string) {
        t.Helper()
        var gotv simd.Int32x4
@@ -3147,6 +3399,16 @@ func testInt32x8Binary(t *testing.T, v0 []int32, v1 []int32, want []int32, which
                gotv = vec0.PairwiseAdd(vec1)
        case "PairwiseSub":
                gotv = vec0.PairwiseSub(vec1)
+       case "RotateLeft":
+               gotv = vec0.RotateLeft(vec1)
+       case "RotateRight":
+               gotv = vec0.RotateRight(vec1)
+       case "ShiftLeft":
+               gotv = vec0.ShiftLeft(vec1)
+       case "ShiftRight":
+               gotv = vec0.ShiftRight(vec1)
+       case "ShiftRightSignExtended":
+               gotv = vec0.ShiftRightSignExtended(vec1)
        case "Sign":
                gotv = vec0.Sign(vec1)
        case "Sub":
@@ -3187,6 +3449,16 @@ func testInt32x8BinaryMasked(t *testing.T, v0 []int32, v1 []int32, v2 []int32, w
                gotv = vec0.MaskedMulLow(vec1, vec2.AsMask32x8())
        case "MaskedOr":
                gotv = vec0.MaskedOr(vec1, vec2.AsMask32x8())
+       case "MaskedRotateLeft":
+               gotv = vec0.MaskedRotateLeft(vec1, vec2.AsMask32x8())
+       case "MaskedRotateRight":
+               gotv = vec0.MaskedRotateRight(vec1, vec2.AsMask32x8())
+       case "MaskedShiftLeft":
+               gotv = vec0.MaskedShiftLeft(vec1, vec2.AsMask32x8())
+       case "MaskedShiftRight":
+               gotv = vec0.MaskedShiftRight(vec1, vec2.AsMask32x8())
+       case "MaskedShiftRightSignExtended":
+               gotv = vec0.MaskedShiftRightSignExtended(vec1, vec2.AsMask32x8())
        case "MaskedSub":
                gotv = vec0.MaskedSub(vec1, vec2.AsMask32x8())
        case "MaskedXor":
@@ -3336,6 +3608,55 @@ func testInt32x8MaskedCompare(t *testing.T, v0 []int32, v1 []int32, v2 []int32,
        }
 }
 
+func testInt32x8Ternary(t *testing.T, v0 []int32, v1 []int32, v2 []int32, want []int32, which string) {
+       t.Helper()
+       var gotv simd.Int32x8
+       got := make([]int32, len(want))
+       vec0 := simd.LoadInt32x8Slice(v0)
+       vec1 := simd.LoadInt32x8Slice(v1)
+       vec2 := simd.LoadInt32x8Slice(v2)
+       switch which {
+       case "ShiftLeftAndFillUpperFrom":
+               gotv = vec0.ShiftLeftAndFillUpperFrom(vec1, vec2)
+       case "ShiftRightAndFillUpperFrom":
+               gotv = vec0.ShiftRightAndFillUpperFrom(vec1, vec2)
+
+       default:
+               t.Errorf("Unknown method: Int32x8.%s", which)
+       }
+       gotv.StoreSlice(got)
+       for i := range len(want) {
+               if got[i] != want[i] {
+                       t.Errorf("Result at %d incorrect: want %v, got %v", i, want[i], got[i])
+               }
+       }
+}
+
+func testInt32x8TernaryMasked(t *testing.T, v0 []int32, v1 []int32, v2 []int32, v3 []int32, want []int32, which string) {
+       t.Helper()
+       var gotv simd.Int32x8
+       got := make([]int32, len(want))
+       vec0 := simd.LoadInt32x8Slice(v0)
+       vec1 := simd.LoadInt32x8Slice(v1)
+       vec2 := simd.LoadInt32x8Slice(v2)
+       vec3 := simd.LoadInt32x8Slice(v3)
+       switch which {
+       case "MaskedShiftLeftAndFillUpperFrom":
+               gotv = vec0.MaskedShiftLeftAndFillUpperFrom(vec1, vec2, vec3.AsMask32x8())
+       case "MaskedShiftRightAndFillUpperFrom":
+               gotv = vec0.MaskedShiftRightAndFillUpperFrom(vec1, vec2, vec3.AsMask32x8())
+
+       default:
+               t.Errorf("Unknown method: Int32x8.%s", which)
+       }
+       gotv.StoreSlice(got)
+       for i := range len(want) {
+               if got[i] != want[i] {
+                       t.Errorf("Result at %d incorrect: want %v, got %v", i, want[i], got[i])
+               }
+       }
+}
+
 func testInt32x8Uint8x32Int8x32Int32x8(t *testing.T, v0 []int32, v1 []uint8, v2 []int8, want []int32, which string) {
        t.Helper()
        var gotv simd.Int32x8
@@ -3451,6 +3772,16 @@ func testInt32x16Binary(t *testing.T, v0 []int32, v1 []int32, want []int32, whic
                gotv = vec0.MulLow(vec1)
        case "Or":
                gotv = vec0.Or(vec1)
+       case "RotateLeft":
+               gotv = vec0.RotateLeft(vec1)
+       case "RotateRight":
+               gotv = vec0.RotateRight(vec1)
+       case "ShiftLeft":
+               gotv = vec0.ShiftLeft(vec1)
+       case "ShiftRight":
+               gotv = vec0.ShiftRight(vec1)
+       case "ShiftRightSignExtended":
+               gotv = vec0.ShiftRightSignExtended(vec1)
        case "Sub":
                gotv = vec0.Sub(vec1)
        case "Xor":
@@ -3489,6 +3820,16 @@ func testInt32x16BinaryMasked(t *testing.T, v0 []int32, v1 []int32, v2 []int32,
                gotv = vec0.MaskedMulLow(vec1, vec2.AsMask32x16())
        case "MaskedOr":
                gotv = vec0.MaskedOr(vec1, vec2.AsMask32x16())
+       case "MaskedRotateLeft":
+               gotv = vec0.MaskedRotateLeft(vec1, vec2.AsMask32x16())
+       case "MaskedRotateRight":
+               gotv = vec0.MaskedRotateRight(vec1, vec2.AsMask32x16())
+       case "MaskedShiftLeft":
+               gotv = vec0.MaskedShiftLeft(vec1, vec2.AsMask32x16())
+       case "MaskedShiftRight":
+               gotv = vec0.MaskedShiftRight(vec1, vec2.AsMask32x16())
+       case "MaskedShiftRightSignExtended":
+               gotv = vec0.MaskedShiftRightSignExtended(vec1, vec2.AsMask32x16())
        case "MaskedSub":
                gotv = vec0.MaskedSub(vec1, vec2.AsMask32x16())
        case "MaskedXor":
@@ -3617,6 +3958,55 @@ func testInt32x16MaskedCompare(t *testing.T, v0 []int32, v1 []int32, v2 []int32,
        }
 }
 
+func testInt32x16Ternary(t *testing.T, v0 []int32, v1 []int32, v2 []int32, want []int32, which string) {
+       t.Helper()
+       var gotv simd.Int32x16
+       got := make([]int32, len(want))
+       vec0 := simd.LoadInt32x16Slice(v0)
+       vec1 := simd.LoadInt32x16Slice(v1)
+       vec2 := simd.LoadInt32x16Slice(v2)
+       switch which {
+       case "ShiftLeftAndFillUpperFrom":
+               gotv = vec0.ShiftLeftAndFillUpperFrom(vec1, vec2)
+       case "ShiftRightAndFillUpperFrom":
+               gotv = vec0.ShiftRightAndFillUpperFrom(vec1, vec2)
+
+       default:
+               t.Errorf("Unknown method: Int32x16.%s", which)
+       }
+       gotv.StoreSlice(got)
+       for i := range len(want) {
+               if got[i] != want[i] {
+                       t.Errorf("Result at %d incorrect: want %v, got %v", i, want[i], got[i])
+               }
+       }
+}
+
+func testInt32x16TernaryMasked(t *testing.T, v0 []int32, v1 []int32, v2 []int32, v3 []int32, want []int32, which string) {
+       t.Helper()
+       var gotv simd.Int32x16
+       got := make([]int32, len(want))
+       vec0 := simd.LoadInt32x16Slice(v0)
+       vec1 := simd.LoadInt32x16Slice(v1)
+       vec2 := simd.LoadInt32x16Slice(v2)
+       vec3 := simd.LoadInt32x16Slice(v3)
+       switch which {
+       case "MaskedShiftLeftAndFillUpperFrom":
+               gotv = vec0.MaskedShiftLeftAndFillUpperFrom(vec1, vec2, vec3.AsMask32x16())
+       case "MaskedShiftRightAndFillUpperFrom":
+               gotv = vec0.MaskedShiftRightAndFillUpperFrom(vec1, vec2, vec3.AsMask32x16())
+
+       default:
+               t.Errorf("Unknown method: Int32x16.%s", which)
+       }
+       gotv.StoreSlice(got)
+       for i := range len(want) {
+               if got[i] != want[i] {
+                       t.Errorf("Result at %d incorrect: want %v, got %v", i, want[i], got[i])
+               }
+       }
+}
+
 func testInt32x16Uint8x64Int8x64Int32x16(t *testing.T, v0 []int32, v1 []uint8, v2 []int8, want []int32, which string) {
        t.Helper()
        var gotv simd.Int32x16
@@ -3734,6 +4124,16 @@ func testInt64x2Binary(t *testing.T, v0 []int64, v1 []int64, want []int64, which
                gotv = vec0.MulLow(vec1)
        case "Or":
                gotv = vec0.Or(vec1)
+       case "RotateLeft":
+               gotv = vec0.RotateLeft(vec1)
+       case "RotateRight":
+               gotv = vec0.RotateRight(vec1)
+       case "ShiftLeft":
+               gotv = vec0.ShiftLeft(vec1)
+       case "ShiftRight":
+               gotv = vec0.ShiftRight(vec1)
+       case "ShiftRightSignExtended":
+               gotv = vec0.ShiftRightSignExtended(vec1)
        case "Sub":
                gotv = vec0.Sub(vec1)
        case "Xor":
@@ -3774,6 +4174,16 @@ func testInt64x2BinaryMasked(t *testing.T, v0 []int64, v1 []int64, v2 []int64, w
                gotv = vec0.MaskedMulLow(vec1, vec2.AsMask64x2())
        case "MaskedOr":
                gotv = vec0.MaskedOr(vec1, vec2.AsMask64x2())
+       case "MaskedRotateLeft":
+               gotv = vec0.MaskedRotateLeft(vec1, vec2.AsMask64x2())
+       case "MaskedRotateRight":
+               gotv = vec0.MaskedRotateRight(vec1, vec2.AsMask64x2())
+       case "MaskedShiftLeft":
+               gotv = vec0.MaskedShiftLeft(vec1, vec2.AsMask64x2())
+       case "MaskedShiftRight":
+               gotv = vec0.MaskedShiftRight(vec1, vec2.AsMask64x2())
+       case "MaskedShiftRightSignExtended":
+               gotv = vec0.MaskedShiftRightSignExtended(vec1, vec2.AsMask64x2())
        case "MaskedSub":
                gotv = vec0.MaskedSub(vec1, vec2.AsMask64x2())
        case "MaskedXor":
@@ -3853,16 +4263,18 @@ func testInt64x2MaskedCompare(t *testing.T, v0 []int64, v1 []int64, v2 []int64,
        }
 }
 
-func testInt64x2Unary(t *testing.T, v0 []int64, want []int64, which string) {
+func testInt64x2Ternary(t *testing.T, v0 []int64, v1 []int64, v2 []int64, want []int64, which string) {
        t.Helper()
        var gotv simd.Int64x2
        got := make([]int64, len(want))
        vec0 := simd.LoadInt64x2Slice(v0)
+       vec1 := simd.LoadInt64x2Slice(v1)
+       vec2 := simd.LoadInt64x2Slice(v2)
        switch which {
-       case "Absolute":
-               gotv = vec0.Absolute()
-       case "PopCount":
-               gotv = vec0.PopCount()
+       case "ShiftLeftAndFillUpperFrom":
+               gotv = vec0.ShiftLeftAndFillUpperFrom(vec1, vec2)
+       case "ShiftRightAndFillUpperFrom":
+               gotv = vec0.ShiftRightAndFillUpperFrom(vec1, vec2)
 
        default:
                t.Errorf("Unknown method: Int64x2.%s", which)
@@ -3875,17 +4287,19 @@ func testInt64x2Unary(t *testing.T, v0 []int64, want []int64, which string) {
        }
 }
 
-func testInt64x2UnaryMasked(t *testing.T, v0 []int64, v1 []int64, want []int64, which string) {
+func testInt64x2TernaryMasked(t *testing.T, v0 []int64, v1 []int64, v2 []int64, v3 []int64, want []int64, which string) {
        t.Helper()
        var gotv simd.Int64x2
        got := make([]int64, len(want))
        vec0 := simd.LoadInt64x2Slice(v0)
        vec1 := simd.LoadInt64x2Slice(v1)
+       vec2 := simd.LoadInt64x2Slice(v2)
+       vec3 := simd.LoadInt64x2Slice(v3)
        switch which {
-       case "MaskedAbsolute":
-               gotv = vec0.MaskedAbsolute(vec1.AsMask64x2())
-       case "MaskedPopCount":
-               gotv = vec0.MaskedPopCount(vec1.AsMask64x2())
+       case "MaskedShiftLeftAndFillUpperFrom":
+               gotv = vec0.MaskedShiftLeftAndFillUpperFrom(vec1, vec2, vec3.AsMask64x2())
+       case "MaskedShiftRightAndFillUpperFrom":
+               gotv = vec0.MaskedShiftRightAndFillUpperFrom(vec1, vec2, vec3.AsMask64x2())
 
        default:
                t.Errorf("Unknown method: Int64x2.%s", which)
@@ -3898,17 +4312,62 @@ func testInt64x2UnaryMasked(t *testing.T, v0 []int64, v1 []int64, want []int64,
        }
 }
 
-func testInt64x4Binary(t *testing.T, v0 []int64, v1 []int64, want []int64, which string) {
+func testInt64x2Unary(t *testing.T, v0 []int64, want []int64, which string) {
        t.Helper()
-       var gotv simd.Int64x4
+       var gotv simd.Int64x2
        got := make([]int64, len(want))
-       vec0 := simd.LoadInt64x4Slice(v0)
-       vec1 := simd.LoadInt64x4Slice(v1)
+       vec0 := simd.LoadInt64x2Slice(v0)
        switch which {
-       case "Add":
-               gotv = vec0.Add(vec1)
-       case "And":
-               gotv = vec0.And(vec1)
+       case "Absolute":
+               gotv = vec0.Absolute()
+       case "PopCount":
+               gotv = vec0.PopCount()
+
+       default:
+               t.Errorf("Unknown method: Int64x2.%s", which)
+       }
+       gotv.StoreSlice(got)
+       for i := range len(want) {
+               if got[i] != want[i] {
+                       t.Errorf("Result at %d incorrect: want %v, got %v", i, want[i], got[i])
+               }
+       }
+}
+
+func testInt64x2UnaryMasked(t *testing.T, v0 []int64, v1 []int64, want []int64, which string) {
+       t.Helper()
+       var gotv simd.Int64x2
+       got := make([]int64, len(want))
+       vec0 := simd.LoadInt64x2Slice(v0)
+       vec1 := simd.LoadInt64x2Slice(v1)
+       switch which {
+       case "MaskedAbsolute":
+               gotv = vec0.MaskedAbsolute(vec1.AsMask64x2())
+       case "MaskedPopCount":
+               gotv = vec0.MaskedPopCount(vec1.AsMask64x2())
+
+       default:
+               t.Errorf("Unknown method: Int64x2.%s", which)
+       }
+       gotv.StoreSlice(got)
+       for i := range len(want) {
+               if got[i] != want[i] {
+                       t.Errorf("Result at %d incorrect: want %v, got %v", i, want[i], got[i])
+               }
+       }
+}
+
+func testInt64x4Binary(t *testing.T, v0 []int64, v1 []int64, want []int64, which string) {
+       t.Helper()
+       var gotv simd.Int64x4
+       got := make([]int64, len(want))
+       vec0 := simd.LoadInt64x4Slice(v0)
+       vec1 := simd.LoadInt64x4Slice(v1)
+       switch which {
+       case "Add":
+               gotv = vec0.Add(vec1)
+       case "And":
+               gotv = vec0.And(vec1)
        case "AndNot":
                gotv = vec0.AndNot(vec1)
        case "Max":
@@ -3921,6 +4380,16 @@ func testInt64x4Binary(t *testing.T, v0 []int64, v1 []int64, want []int64, which
                gotv = vec0.MulLow(vec1)
        case "Or":
                gotv = vec0.Or(vec1)
+       case "RotateLeft":
+               gotv = vec0.RotateLeft(vec1)
+       case "RotateRight":
+               gotv = vec0.RotateRight(vec1)
+       case "ShiftLeft":
+               gotv = vec0.ShiftLeft(vec1)
+       case "ShiftRight":
+               gotv = vec0.ShiftRight(vec1)
+       case "ShiftRightSignExtended":
+               gotv = vec0.ShiftRightSignExtended(vec1)
        case "Sub":
                gotv = vec0.Sub(vec1)
        case "Xor":
@@ -3961,6 +4430,16 @@ func testInt64x4BinaryMasked(t *testing.T, v0 []int64, v1 []int64, v2 []int64, w
                gotv = vec0.MaskedMulLow(vec1, vec2.AsMask64x4())
        case "MaskedOr":
                gotv = vec0.MaskedOr(vec1, vec2.AsMask64x4())
+       case "MaskedRotateLeft":
+               gotv = vec0.MaskedRotateLeft(vec1, vec2.AsMask64x4())
+       case "MaskedRotateRight":
+               gotv = vec0.MaskedRotateRight(vec1, vec2.AsMask64x4())
+       case "MaskedShiftLeft":
+               gotv = vec0.MaskedShiftLeft(vec1, vec2.AsMask64x4())
+       case "MaskedShiftRight":
+               gotv = vec0.MaskedShiftRight(vec1, vec2.AsMask64x4())
+       case "MaskedShiftRightSignExtended":
+               gotv = vec0.MaskedShiftRightSignExtended(vec1, vec2.AsMask64x4())
        case "MaskedSub":
                gotv = vec0.MaskedSub(vec1, vec2.AsMask64x4())
        case "MaskedXor":
@@ -4040,6 +4519,55 @@ func testInt64x4MaskedCompare(t *testing.T, v0 []int64, v1 []int64, v2 []int64,
        }
 }
 
+func testInt64x4Ternary(t *testing.T, v0 []int64, v1 []int64, v2 []int64, want []int64, which string) {
+       t.Helper()
+       var gotv simd.Int64x4
+       got := make([]int64, len(want))
+       vec0 := simd.LoadInt64x4Slice(v0)
+       vec1 := simd.LoadInt64x4Slice(v1)
+       vec2 := simd.LoadInt64x4Slice(v2)
+       switch which {
+       case "ShiftLeftAndFillUpperFrom":
+               gotv = vec0.ShiftLeftAndFillUpperFrom(vec1, vec2)
+       case "ShiftRightAndFillUpperFrom":
+               gotv = vec0.ShiftRightAndFillUpperFrom(vec1, vec2)
+
+       default:
+               t.Errorf("Unknown method: Int64x4.%s", which)
+       }
+       gotv.StoreSlice(got)
+       for i := range len(want) {
+               if got[i] != want[i] {
+                       t.Errorf("Result at %d incorrect: want %v, got %v", i, want[i], got[i])
+               }
+       }
+}
+
+func testInt64x4TernaryMasked(t *testing.T, v0 []int64, v1 []int64, v2 []int64, v3 []int64, want []int64, which string) {
+       t.Helper()
+       var gotv simd.Int64x4
+       got := make([]int64, len(want))
+       vec0 := simd.LoadInt64x4Slice(v0)
+       vec1 := simd.LoadInt64x4Slice(v1)
+       vec2 := simd.LoadInt64x4Slice(v2)
+       vec3 := simd.LoadInt64x4Slice(v3)
+       switch which {
+       case "MaskedShiftLeftAndFillUpperFrom":
+               gotv = vec0.MaskedShiftLeftAndFillUpperFrom(vec1, vec2, vec3.AsMask64x4())
+       case "MaskedShiftRightAndFillUpperFrom":
+               gotv = vec0.MaskedShiftRightAndFillUpperFrom(vec1, vec2, vec3.AsMask64x4())
+
+       default:
+               t.Errorf("Unknown method: Int64x4.%s", which)
+       }
+       gotv.StoreSlice(got)
+       for i := range len(want) {
+               if got[i] != want[i] {
+                       t.Errorf("Result at %d incorrect: want %v, got %v", i, want[i], got[i])
+               }
+       }
+}
+
 func testInt64x4Unary(t *testing.T, v0 []int64, want []int64, which string) {
        t.Helper()
        var gotv simd.Int64x4
@@ -4108,6 +4636,16 @@ func testInt64x8Binary(t *testing.T, v0 []int64, v1 []int64, want []int64, which
                gotv = vec0.MulLow(vec1)
        case "Or":
                gotv = vec0.Or(vec1)
+       case "RotateLeft":
+               gotv = vec0.RotateLeft(vec1)
+       case "RotateRight":
+               gotv = vec0.RotateRight(vec1)
+       case "ShiftLeft":
+               gotv = vec0.ShiftLeft(vec1)
+       case "ShiftRight":
+               gotv = vec0.ShiftRight(vec1)
+       case "ShiftRightSignExtended":
+               gotv = vec0.ShiftRightSignExtended(vec1)
        case "Sub":
                gotv = vec0.Sub(vec1)
        case "Xor":
@@ -4148,6 +4686,16 @@ func testInt64x8BinaryMasked(t *testing.T, v0 []int64, v1 []int64, v2 []int64, w
                gotv = vec0.MaskedMulLow(vec1, vec2.AsMask64x8())
        case "MaskedOr":
                gotv = vec0.MaskedOr(vec1, vec2.AsMask64x8())
+       case "MaskedRotateLeft":
+               gotv = vec0.MaskedRotateLeft(vec1, vec2.AsMask64x8())
+       case "MaskedRotateRight":
+               gotv = vec0.MaskedRotateRight(vec1, vec2.AsMask64x8())
+       case "MaskedShiftLeft":
+               gotv = vec0.MaskedShiftLeft(vec1, vec2.AsMask64x8())
+       case "MaskedShiftRight":
+               gotv = vec0.MaskedShiftRight(vec1, vec2.AsMask64x8())
+       case "MaskedShiftRightSignExtended":
+               gotv = vec0.MaskedShiftRightSignExtended(vec1, vec2.AsMask64x8())
        case "MaskedSub":
                gotv = vec0.MaskedSub(vec1, vec2.AsMask64x8())
        case "MaskedXor":
@@ -4227,6 +4775,55 @@ func testInt64x8MaskedCompare(t *testing.T, v0 []int64, v1 []int64, v2 []int64,
        }
 }
 
+func testInt64x8Ternary(t *testing.T, v0 []int64, v1 []int64, v2 []int64, want []int64, which string) {
+       t.Helper()
+       var gotv simd.Int64x8
+       got := make([]int64, len(want))
+       vec0 := simd.LoadInt64x8Slice(v0)
+       vec1 := simd.LoadInt64x8Slice(v1)
+       vec2 := simd.LoadInt64x8Slice(v2)
+       switch which {
+       case "ShiftLeftAndFillUpperFrom":
+               gotv = vec0.ShiftLeftAndFillUpperFrom(vec1, vec2)
+       case "ShiftRightAndFillUpperFrom":
+               gotv = vec0.ShiftRightAndFillUpperFrom(vec1, vec2)
+
+       default:
+               t.Errorf("Unknown method: Int64x8.%s", which)
+       }
+       gotv.StoreSlice(got)
+       for i := range len(want) {
+               if got[i] != want[i] {
+                       t.Errorf("Result at %d incorrect: want %v, got %v", i, want[i], got[i])
+               }
+       }
+}
+
+func testInt64x8TernaryMasked(t *testing.T, v0 []int64, v1 []int64, v2 []int64, v3 []int64, want []int64, which string) {
+       t.Helper()
+       var gotv simd.Int64x8
+       got := make([]int64, len(want))
+       vec0 := simd.LoadInt64x8Slice(v0)
+       vec1 := simd.LoadInt64x8Slice(v1)
+       vec2 := simd.LoadInt64x8Slice(v2)
+       vec3 := simd.LoadInt64x8Slice(v3)
+       switch which {
+       case "MaskedShiftLeftAndFillUpperFrom":
+               gotv = vec0.MaskedShiftLeftAndFillUpperFrom(vec1, vec2, vec3.AsMask64x8())
+       case "MaskedShiftRightAndFillUpperFrom":
+               gotv = vec0.MaskedShiftRightAndFillUpperFrom(vec1, vec2, vec3.AsMask64x8())
+
+       default:
+               t.Errorf("Unknown method: Int64x8.%s", which)
+       }
+       gotv.StoreSlice(got)
+       for i := range len(want) {
+               if got[i] != want[i] {
+                       t.Errorf("Result at %d incorrect: want %v, got %v", i, want[i], got[i])
+               }
+       }
+}
+
 func testInt64x8Unary(t *testing.T, v0 []int64, want []int64, which string) {
        t.Helper()
        var gotv simd.Int64x8
@@ -4961,6 +5558,12 @@ func testUint16x8Binary(t *testing.T, v0 []uint16, v1 []uint16, want []uint16, w
                gotv = vec0.SaturatedAdd(vec1)
        case "SaturatedSub":
                gotv = vec0.SaturatedSub(vec1)
+       case "ShiftLeft":
+               gotv = vec0.ShiftLeft(vec1)
+       case "ShiftRight":
+               gotv = vec0.ShiftRight(vec1)
+       case "ShiftRightSignExtended":
+               gotv = vec0.ShiftRightSignExtended(vec1)
        case "Sub":
                gotv = vec0.Sub(vec1)
        case "Xor":
@@ -4999,6 +5602,12 @@ func testUint16x8BinaryMasked(t *testing.T, v0 []uint16, v1 []uint16, v2 []int16
                gotv = vec0.MaskedSaturatedAdd(vec1, vec2.AsMask16x8())
        case "MaskedSaturatedSub":
                gotv = vec0.MaskedSaturatedSub(vec1, vec2.AsMask16x8())
+       case "MaskedShiftLeft":
+               gotv = vec0.MaskedShiftLeft(vec1, vec2.AsMask16x8())
+       case "MaskedShiftRight":
+               gotv = vec0.MaskedShiftRight(vec1, vec2.AsMask16x8())
+       case "MaskedShiftRightSignExtended":
+               gotv = vec0.MaskedShiftRightSignExtended(vec1, vec2.AsMask16x8())
        case "MaskedSub":
                gotv = vec0.MaskedSub(vec1, vec2.AsMask16x8())
 
@@ -5076,6 +5685,55 @@ func testUint16x8MaskedCompare(t *testing.T, v0 []uint16, v1 []uint16, v2 []int1
        }
 }
 
+func testUint16x8Ternary(t *testing.T, v0 []uint16, v1 []uint16, v2 []uint16, want []uint16, which string) {
+       t.Helper()
+       var gotv simd.Uint16x8
+       got := make([]uint16, len(want))
+       vec0 := simd.LoadUint16x8Slice(v0)
+       vec1 := simd.LoadUint16x8Slice(v1)
+       vec2 := simd.LoadUint16x8Slice(v2)
+       switch which {
+       case "ShiftLeftAndFillUpperFrom":
+               gotv = vec0.ShiftLeftAndFillUpperFrom(vec1, vec2)
+       case "ShiftRightAndFillUpperFrom":
+               gotv = vec0.ShiftRightAndFillUpperFrom(vec1, vec2)
+
+       default:
+               t.Errorf("Unknown method: Uint16x8.%s", which)
+       }
+       gotv.StoreSlice(got)
+       for i := range len(want) {
+               if got[i] != want[i] {
+                       t.Errorf("Result at %d incorrect: want %v, got %v", i, want[i], got[i])
+               }
+       }
+}
+
+func testUint16x8TernaryMasked(t *testing.T, v0 []uint16, v1 []uint16, v2 []uint16, v3 []int16, want []uint16, which string) {
+       t.Helper()
+       var gotv simd.Uint16x8
+       got := make([]uint16, len(want))
+       vec0 := simd.LoadUint16x8Slice(v0)
+       vec1 := simd.LoadUint16x8Slice(v1)
+       vec2 := simd.LoadUint16x8Slice(v2)
+       vec3 := simd.LoadInt16x8Slice(v3)
+       switch which {
+       case "MaskedShiftLeftAndFillUpperFrom":
+               gotv = vec0.MaskedShiftLeftAndFillUpperFrom(vec1, vec2, vec3.AsMask16x8())
+       case "MaskedShiftRightAndFillUpperFrom":
+               gotv = vec0.MaskedShiftRightAndFillUpperFrom(vec1, vec2, vec3.AsMask16x8())
+
+       default:
+               t.Errorf("Unknown method: Uint16x8.%s", which)
+       }
+       gotv.StoreSlice(got)
+       for i := range len(want) {
+               if got[i] != want[i] {
+                       t.Errorf("Result at %d incorrect: want %v, got %v", i, want[i], got[i])
+               }
+       }
+}
+
 func testUint16x8Unary(t *testing.T, v0 []uint16, want []uint16, which string) {
        t.Helper()
        var gotv simd.Uint16x8
@@ -5148,6 +5806,12 @@ func testUint16x16Binary(t *testing.T, v0 []uint16, v1 []uint16, want []uint16,
                gotv = vec0.SaturatedAdd(vec1)
        case "SaturatedSub":
                gotv = vec0.SaturatedSub(vec1)
+       case "ShiftLeft":
+               gotv = vec0.ShiftLeft(vec1)
+       case "ShiftRight":
+               gotv = vec0.ShiftRight(vec1)
+       case "ShiftRightSignExtended":
+               gotv = vec0.ShiftRightSignExtended(vec1)
        case "Sub":
                gotv = vec0.Sub(vec1)
        case "Xor":
@@ -5186,6 +5850,12 @@ func testUint16x16BinaryMasked(t *testing.T, v0 []uint16, v1 []uint16, v2 []int1
                gotv = vec0.MaskedSaturatedAdd(vec1, vec2.AsMask16x16())
        case "MaskedSaturatedSub":
                gotv = vec0.MaskedSaturatedSub(vec1, vec2.AsMask16x16())
+       case "MaskedShiftLeft":
+               gotv = vec0.MaskedShiftLeft(vec1, vec2.AsMask16x16())
+       case "MaskedShiftRight":
+               gotv = vec0.MaskedShiftRight(vec1, vec2.AsMask16x16())
+       case "MaskedShiftRightSignExtended":
+               gotv = vec0.MaskedShiftRightSignExtended(vec1, vec2.AsMask16x16())
        case "MaskedSub":
                gotv = vec0.MaskedSub(vec1, vec2.AsMask16x16())
 
@@ -5263,6 +5933,55 @@ func testUint16x16MaskedCompare(t *testing.T, v0 []uint16, v1 []uint16, v2 []int
        }
 }
 
+func testUint16x16Ternary(t *testing.T, v0 []uint16, v1 []uint16, v2 []uint16, want []uint16, which string) {
+       t.Helper()
+       var gotv simd.Uint16x16
+       got := make([]uint16, len(want))
+       vec0 := simd.LoadUint16x16Slice(v0)
+       vec1 := simd.LoadUint16x16Slice(v1)
+       vec2 := simd.LoadUint16x16Slice(v2)
+       switch which {
+       case "ShiftLeftAndFillUpperFrom":
+               gotv = vec0.ShiftLeftAndFillUpperFrom(vec1, vec2)
+       case "ShiftRightAndFillUpperFrom":
+               gotv = vec0.ShiftRightAndFillUpperFrom(vec1, vec2)
+
+       default:
+               t.Errorf("Unknown method: Uint16x16.%s", which)
+       }
+       gotv.StoreSlice(got)
+       for i := range len(want) {
+               if got[i] != want[i] {
+                       t.Errorf("Result at %d incorrect: want %v, got %v", i, want[i], got[i])
+               }
+       }
+}
+
+func testUint16x16TernaryMasked(t *testing.T, v0 []uint16, v1 []uint16, v2 []uint16, v3 []int16, want []uint16, which string) {
+       t.Helper()
+       var gotv simd.Uint16x16
+       got := make([]uint16, len(want))
+       vec0 := simd.LoadUint16x16Slice(v0)
+       vec1 := simd.LoadUint16x16Slice(v1)
+       vec2 := simd.LoadUint16x16Slice(v2)
+       vec3 := simd.LoadInt16x16Slice(v3)
+       switch which {
+       case "MaskedShiftLeftAndFillUpperFrom":
+               gotv = vec0.MaskedShiftLeftAndFillUpperFrom(vec1, vec2, vec3.AsMask16x16())
+       case "MaskedShiftRightAndFillUpperFrom":
+               gotv = vec0.MaskedShiftRightAndFillUpperFrom(vec1, vec2, vec3.AsMask16x16())
+
+       default:
+               t.Errorf("Unknown method: Uint16x16.%s", which)
+       }
+       gotv.StoreSlice(got)
+       for i := range len(want) {
+               if got[i] != want[i] {
+                       t.Errorf("Result at %d incorrect: want %v, got %v", i, want[i], got[i])
+               }
+       }
+}
+
 func testUint16x16Unary(t *testing.T, v0 []uint16, want []uint16, which string) {
        t.Helper()
        var gotv simd.Uint16x16
@@ -5325,6 +6044,12 @@ func testUint16x32Binary(t *testing.T, v0 []uint16, v1 []uint16, want []uint16,
                gotv = vec0.SaturatedAdd(vec1)
        case "SaturatedSub":
                gotv = vec0.SaturatedSub(vec1)
+       case "ShiftLeft":
+               gotv = vec0.ShiftLeft(vec1)
+       case "ShiftRight":
+               gotv = vec0.ShiftRight(vec1)
+       case "ShiftRightSignExtended":
+               gotv = vec0.ShiftRightSignExtended(vec1)
        case "Sub":
                gotv = vec0.Sub(vec1)
 
@@ -5361,6 +6086,12 @@ func testUint16x32BinaryMasked(t *testing.T, v0 []uint16, v1 []uint16, v2 []int1
                gotv = vec0.MaskedSaturatedAdd(vec1, vec2.AsMask16x32())
        case "MaskedSaturatedSub":
                gotv = vec0.MaskedSaturatedSub(vec1, vec2.AsMask16x32())
+       case "MaskedShiftLeft":
+               gotv = vec0.MaskedShiftLeft(vec1, vec2.AsMask16x32())
+       case "MaskedShiftRight":
+               gotv = vec0.MaskedShiftRight(vec1, vec2.AsMask16x32())
+       case "MaskedShiftRightSignExtended":
+               gotv = vec0.MaskedShiftRightSignExtended(vec1, vec2.AsMask16x32())
        case "MaskedSub":
                gotv = vec0.MaskedSub(vec1, vec2.AsMask16x32())
 
@@ -5438,6 +6169,55 @@ func testUint16x32MaskedCompare(t *testing.T, v0 []uint16, v1 []uint16, v2 []int
        }
 }
 
+func testUint16x32Ternary(t *testing.T, v0 []uint16, v1 []uint16, v2 []uint16, want []uint16, which string) {
+       t.Helper()
+       var gotv simd.Uint16x32
+       got := make([]uint16, len(want))
+       vec0 := simd.LoadUint16x32Slice(v0)
+       vec1 := simd.LoadUint16x32Slice(v1)
+       vec2 := simd.LoadUint16x32Slice(v2)
+       switch which {
+       case "ShiftLeftAndFillUpperFrom":
+               gotv = vec0.ShiftLeftAndFillUpperFrom(vec1, vec2)
+       case "ShiftRightAndFillUpperFrom":
+               gotv = vec0.ShiftRightAndFillUpperFrom(vec1, vec2)
+
+       default:
+               t.Errorf("Unknown method: Uint16x32.%s", which)
+       }
+       gotv.StoreSlice(got)
+       for i := range len(want) {
+               if got[i] != want[i] {
+                       t.Errorf("Result at %d incorrect: want %v, got %v", i, want[i], got[i])
+               }
+       }
+}
+
+func testUint16x32TernaryMasked(t *testing.T, v0 []uint16, v1 []uint16, v2 []uint16, v3 []int16, want []uint16, which string) {
+       t.Helper()
+       var gotv simd.Uint16x32
+       got := make([]uint16, len(want))
+       vec0 := simd.LoadUint16x32Slice(v0)
+       vec1 := simd.LoadUint16x32Slice(v1)
+       vec2 := simd.LoadUint16x32Slice(v2)
+       vec3 := simd.LoadInt16x32Slice(v3)
+       switch which {
+       case "MaskedShiftLeftAndFillUpperFrom":
+               gotv = vec0.MaskedShiftLeftAndFillUpperFrom(vec1, vec2, vec3.AsMask16x32())
+       case "MaskedShiftRightAndFillUpperFrom":
+               gotv = vec0.MaskedShiftRightAndFillUpperFrom(vec1, vec2, vec3.AsMask16x32())
+
+       default:
+               t.Errorf("Unknown method: Uint16x32.%s", which)
+       }
+       gotv.StoreSlice(got)
+       for i := range len(want) {
+               if got[i] != want[i] {
+                       t.Errorf("Result at %d incorrect: want %v, got %v", i, want[i], got[i])
+               }
+       }
+}
+
 func testUint16x32Unary(t *testing.T, v0 []uint16, want []uint16, which string) {
        t.Helper()
        var gotv simd.Uint16x32
@@ -5502,6 +6282,16 @@ func testUint32x4Binary(t *testing.T, v0 []uint32, v1 []uint32, want []uint32, w
                gotv = vec0.PairwiseAdd(vec1)
        case "PairwiseSub":
                gotv = vec0.PairwiseSub(vec1)
+       case "RotateLeft":
+               gotv = vec0.RotateLeft(vec1)
+       case "RotateRight":
+               gotv = vec0.RotateRight(vec1)
+       case "ShiftLeft":
+               gotv = vec0.ShiftLeft(vec1)
+       case "ShiftRight":
+               gotv = vec0.ShiftRight(vec1)
+       case "ShiftRightSignExtended":
+               gotv = vec0.ShiftRightSignExtended(vec1)
        case "Sub":
                gotv = vec0.Sub(vec1)
        case "Xor":
@@ -5538,6 +6328,16 @@ func testUint32x4BinaryMasked(t *testing.T, v0 []uint32, v1 []uint32, v2 []int32
                gotv = vec0.MaskedMin(vec1, vec2.AsMask32x4())
        case "MaskedOr":
                gotv = vec0.MaskedOr(vec1, vec2.AsMask32x4())
+       case "MaskedRotateLeft":
+               gotv = vec0.MaskedRotateLeft(vec1, vec2.AsMask32x4())
+       case "MaskedRotateRight":
+               gotv = vec0.MaskedRotateRight(vec1, vec2.AsMask32x4())
+       case "MaskedShiftLeft":
+               gotv = vec0.MaskedShiftLeft(vec1, vec2.AsMask32x4())
+       case "MaskedShiftRight":
+               gotv = vec0.MaskedShiftRight(vec1, vec2.AsMask32x4())
+       case "MaskedShiftRightSignExtended":
+               gotv = vec0.MaskedShiftRightSignExtended(vec1, vec2.AsMask32x4())
        case "MaskedSub":
                gotv = vec0.MaskedSub(vec1, vec2.AsMask32x4())
        case "MaskedXor":
@@ -5638,6 +6438,55 @@ func testUint32x4MaskedCompare(t *testing.T, v0 []uint32, v1 []uint32, v2 []int3
        }
 }
 
+func testUint32x4Ternary(t *testing.T, v0 []uint32, v1 []uint32, v2 []uint32, want []uint32, which string) {
+       t.Helper()
+       var gotv simd.Uint32x4
+       got := make([]uint32, len(want))
+       vec0 := simd.LoadUint32x4Slice(v0)
+       vec1 := simd.LoadUint32x4Slice(v1)
+       vec2 := simd.LoadUint32x4Slice(v2)
+       switch which {
+       case "ShiftLeftAndFillUpperFrom":
+               gotv = vec0.ShiftLeftAndFillUpperFrom(vec1, vec2)
+       case "ShiftRightAndFillUpperFrom":
+               gotv = vec0.ShiftRightAndFillUpperFrom(vec1, vec2)
+
+       default:
+               t.Errorf("Unknown method: Uint32x4.%s", which)
+       }
+       gotv.StoreSlice(got)
+       for i := range len(want) {
+               if got[i] != want[i] {
+                       t.Errorf("Result at %d incorrect: want %v, got %v", i, want[i], got[i])
+               }
+       }
+}
+
+func testUint32x4TernaryMasked(t *testing.T, v0 []uint32, v1 []uint32, v2 []uint32, v3 []int32, want []uint32, which string) {
+       t.Helper()
+       var gotv simd.Uint32x4
+       got := make([]uint32, len(want))
+       vec0 := simd.LoadUint32x4Slice(v0)
+       vec1 := simd.LoadUint32x4Slice(v1)
+       vec2 := simd.LoadUint32x4Slice(v2)
+       vec3 := simd.LoadInt32x4Slice(v3)
+       switch which {
+       case "MaskedShiftLeftAndFillUpperFrom":
+               gotv = vec0.MaskedShiftLeftAndFillUpperFrom(vec1, vec2, vec3.AsMask32x4())
+       case "MaskedShiftRightAndFillUpperFrom":
+               gotv = vec0.MaskedShiftRightAndFillUpperFrom(vec1, vec2, vec3.AsMask32x4())
+
+       default:
+               t.Errorf("Unknown method: Uint32x4.%s", which)
+       }
+       gotv.StoreSlice(got)
+       for i := range len(want) {
+               if got[i] != want[i] {
+                       t.Errorf("Result at %d incorrect: want %v, got %v", i, want[i], got[i])
+               }
+       }
+}
+
 func testUint32x4Uint8x16Int8x16Mask32x4Uint32x4(t *testing.T, v0 []uint32, v1 []uint8, v2 []int8, v3 []int32, want []uint32, which string) {
        t.Helper()
        var gotv simd.Uint32x4
@@ -5751,6 +6600,16 @@ func testUint32x8Binary(t *testing.T, v0 []uint32, v1 []uint32, want []uint32, w
                gotv = vec0.PairwiseAdd(vec1)
        case "PairwiseSub":
                gotv = vec0.PairwiseSub(vec1)
+       case "RotateLeft":
+               gotv = vec0.RotateLeft(vec1)
+       case "RotateRight":
+               gotv = vec0.RotateRight(vec1)
+       case "ShiftLeft":
+               gotv = vec0.ShiftLeft(vec1)
+       case "ShiftRight":
+               gotv = vec0.ShiftRight(vec1)
+       case "ShiftRightSignExtended":
+               gotv = vec0.ShiftRightSignExtended(vec1)
        case "Sub":
                gotv = vec0.Sub(vec1)
        case "Xor":
@@ -5787,6 +6646,16 @@ func testUint32x8BinaryMasked(t *testing.T, v0 []uint32, v1 []uint32, v2 []int32
                gotv = vec0.MaskedMin(vec1, vec2.AsMask32x8())
        case "MaskedOr":
                gotv = vec0.MaskedOr(vec1, vec2.AsMask32x8())
+       case "MaskedRotateLeft":
+               gotv = vec0.MaskedRotateLeft(vec1, vec2.AsMask32x8())
+       case "MaskedRotateRight":
+               gotv = vec0.MaskedRotateRight(vec1, vec2.AsMask32x8())
+       case "MaskedShiftLeft":
+               gotv = vec0.MaskedShiftLeft(vec1, vec2.AsMask32x8())
+       case "MaskedShiftRight":
+               gotv = vec0.MaskedShiftRight(vec1, vec2.AsMask32x8())
+       case "MaskedShiftRightSignExtended":
+               gotv = vec0.MaskedShiftRightSignExtended(vec1, vec2.AsMask32x8())
        case "MaskedSub":
                gotv = vec0.MaskedSub(vec1, vec2.AsMask32x8())
        case "MaskedXor":
@@ -5887,6 +6756,55 @@ func testUint32x8MaskedCompare(t *testing.T, v0 []uint32, v1 []uint32, v2 []int3
        }
 }
 
+func testUint32x8Ternary(t *testing.T, v0 []uint32, v1 []uint32, v2 []uint32, want []uint32, which string) {
+       t.Helper()
+       var gotv simd.Uint32x8
+       got := make([]uint32, len(want))
+       vec0 := simd.LoadUint32x8Slice(v0)
+       vec1 := simd.LoadUint32x8Slice(v1)
+       vec2 := simd.LoadUint32x8Slice(v2)
+       switch which {
+       case "ShiftLeftAndFillUpperFrom":
+               gotv = vec0.ShiftLeftAndFillUpperFrom(vec1, vec2)
+       case "ShiftRightAndFillUpperFrom":
+               gotv = vec0.ShiftRightAndFillUpperFrom(vec1, vec2)
+
+       default:
+               t.Errorf("Unknown method: Uint32x8.%s", which)
+       }
+       gotv.StoreSlice(got)
+       for i := range len(want) {
+               if got[i] != want[i] {
+                       t.Errorf("Result at %d incorrect: want %v, got %v", i, want[i], got[i])
+               }
+       }
+}
+
+func testUint32x8TernaryMasked(t *testing.T, v0 []uint32, v1 []uint32, v2 []uint32, v3 []int32, want []uint32, which string) {
+       t.Helper()
+       var gotv simd.Uint32x8
+       got := make([]uint32, len(want))
+       vec0 := simd.LoadUint32x8Slice(v0)
+       vec1 := simd.LoadUint32x8Slice(v1)
+       vec2 := simd.LoadUint32x8Slice(v2)
+       vec3 := simd.LoadInt32x8Slice(v3)
+       switch which {
+       case "MaskedShiftLeftAndFillUpperFrom":
+               gotv = vec0.MaskedShiftLeftAndFillUpperFrom(vec1, vec2, vec3.AsMask32x8())
+       case "MaskedShiftRightAndFillUpperFrom":
+               gotv = vec0.MaskedShiftRightAndFillUpperFrom(vec1, vec2, vec3.AsMask32x8())
+
+       default:
+               t.Errorf("Unknown method: Uint32x8.%s", which)
+       }
+       gotv.StoreSlice(got)
+       for i := range len(want) {
+               if got[i] != want[i] {
+                       t.Errorf("Result at %d incorrect: want %v, got %v", i, want[i], got[i])
+               }
+       }
+}
+
 func testUint32x8Uint8x32Int8x32Mask32x8Uint32x8(t *testing.T, v0 []uint32, v1 []uint8, v2 []int8, v3 []int32, want []uint32, which string) {
        t.Helper()
        var gotv simd.Uint32x8
@@ -5996,6 +6914,16 @@ func testUint32x16Binary(t *testing.T, v0 []uint32, v1 []uint32, want []uint32,
                gotv = vec0.Min(vec1)
        case "Or":
                gotv = vec0.Or(vec1)
+       case "RotateLeft":
+               gotv = vec0.RotateLeft(vec1)
+       case "RotateRight":
+               gotv = vec0.RotateRight(vec1)
+       case "ShiftLeft":
+               gotv = vec0.ShiftLeft(vec1)
+       case "ShiftRight":
+               gotv = vec0.ShiftRight(vec1)
+       case "ShiftRightSignExtended":
+               gotv = vec0.ShiftRightSignExtended(vec1)
        case "Sub":
                gotv = vec0.Sub(vec1)
        case "Xor":
@@ -6032,6 +6960,16 @@ func testUint32x16BinaryMasked(t *testing.T, v0 []uint32, v1 []uint32, v2 []int3
                gotv = vec0.MaskedMin(vec1, vec2.AsMask32x16())
        case "MaskedOr":
                gotv = vec0.MaskedOr(vec1, vec2.AsMask32x16())
+       case "MaskedRotateLeft":
+               gotv = vec0.MaskedRotateLeft(vec1, vec2.AsMask32x16())
+       case "MaskedRotateRight":
+               gotv = vec0.MaskedRotateRight(vec1, vec2.AsMask32x16())
+       case "MaskedShiftLeft":
+               gotv = vec0.MaskedShiftLeft(vec1, vec2.AsMask32x16())
+       case "MaskedShiftRight":
+               gotv = vec0.MaskedShiftRight(vec1, vec2.AsMask32x16())
+       case "MaskedShiftRightSignExtended":
+               gotv = vec0.MaskedShiftRightSignExtended(vec1, vec2.AsMask32x16())
        case "MaskedSub":
                gotv = vec0.MaskedSub(vec1, vec2.AsMask32x16())
        case "MaskedXor":
@@ -6111,6 +7049,55 @@ func testUint32x16MaskedCompare(t *testing.T, v0 []uint32, v1 []uint32, v2 []int
        }
 }
 
+func testUint32x16Ternary(t *testing.T, v0 []uint32, v1 []uint32, v2 []uint32, want []uint32, which string) {
+       t.Helper()
+       var gotv simd.Uint32x16
+       got := make([]uint32, len(want))
+       vec0 := simd.LoadUint32x16Slice(v0)
+       vec1 := simd.LoadUint32x16Slice(v1)
+       vec2 := simd.LoadUint32x16Slice(v2)
+       switch which {
+       case "ShiftLeftAndFillUpperFrom":
+               gotv = vec0.ShiftLeftAndFillUpperFrom(vec1, vec2)
+       case "ShiftRightAndFillUpperFrom":
+               gotv = vec0.ShiftRightAndFillUpperFrom(vec1, vec2)
+
+       default:
+               t.Errorf("Unknown method: Uint32x16.%s", which)
+       }
+       gotv.StoreSlice(got)
+       for i := range len(want) {
+               if got[i] != want[i] {
+                       t.Errorf("Result at %d incorrect: want %v, got %v", i, want[i], got[i])
+               }
+       }
+}
+
+func testUint32x16TernaryMasked(t *testing.T, v0 []uint32, v1 []uint32, v2 []uint32, v3 []int32, want []uint32, which string) {
+       t.Helper()
+       var gotv simd.Uint32x16
+       got := make([]uint32, len(want))
+       vec0 := simd.LoadUint32x16Slice(v0)
+       vec1 := simd.LoadUint32x16Slice(v1)
+       vec2 := simd.LoadUint32x16Slice(v2)
+       vec3 := simd.LoadInt32x16Slice(v3)
+       switch which {
+       case "MaskedShiftLeftAndFillUpperFrom":
+               gotv = vec0.MaskedShiftLeftAndFillUpperFrom(vec1, vec2, vec3.AsMask32x16())
+       case "MaskedShiftRightAndFillUpperFrom":
+               gotv = vec0.MaskedShiftRightAndFillUpperFrom(vec1, vec2, vec3.AsMask32x16())
+
+       default:
+               t.Errorf("Unknown method: Uint32x16.%s", which)
+       }
+       gotv.StoreSlice(got)
+       for i := range len(want) {
+               if got[i] != want[i] {
+                       t.Errorf("Result at %d incorrect: want %v, got %v", i, want[i], got[i])
+               }
+       }
+}
+
 func testUint32x16Uint8x64Int8x64Mask32x16Uint32x16(t *testing.T, v0 []uint32, v1 []uint8, v2 []int8, v3 []int32, want []uint32, which string) {
        t.Helper()
        var gotv simd.Uint32x16
@@ -6222,6 +7209,16 @@ func testUint64x2Binary(t *testing.T, v0 []uint64, v1 []uint64, want []uint64, w
                gotv = vec0.MulEvenWiden(vec1)
        case "Or":
                gotv = vec0.Or(vec1)
+       case "RotateLeft":
+               gotv = vec0.RotateLeft(vec1)
+       case "RotateRight":
+               gotv = vec0.RotateRight(vec1)
+       case "ShiftLeft":
+               gotv = vec0.ShiftLeft(vec1)
+       case "ShiftRight":
+               gotv = vec0.ShiftRight(vec1)
+       case "ShiftRightSignExtended":
+               gotv = vec0.ShiftRightSignExtended(vec1)
        case "Sub":
                gotv = vec0.Sub(vec1)
        case "Xor":
@@ -6260,6 +7257,16 @@ func testUint64x2BinaryMasked(t *testing.T, v0 []uint64, v1 []uint64, v2 []int64
                gotv = vec0.MaskedMulEvenWiden(vec1, vec2.AsMask64x2())
        case "MaskedOr":
                gotv = vec0.MaskedOr(vec1, vec2.AsMask64x2())
+       case "MaskedRotateLeft":
+               gotv = vec0.MaskedRotateLeft(vec1, vec2.AsMask64x2())
+       case "MaskedRotateRight":
+               gotv = vec0.MaskedRotateRight(vec1, vec2.AsMask64x2())
+       case "MaskedShiftLeft":
+               gotv = vec0.MaskedShiftLeft(vec1, vec2.AsMask64x2())
+       case "MaskedShiftRight":
+               gotv = vec0.MaskedShiftRight(vec1, vec2.AsMask64x2())
+       case "MaskedShiftRightSignExtended":
+               gotv = vec0.MaskedShiftRightSignExtended(vec1, vec2.AsMask64x2())
        case "MaskedSub":
                gotv = vec0.MaskedSub(vec1, vec2.AsMask64x2())
        case "MaskedXor":
@@ -6339,6 +7346,55 @@ func testUint64x2MaskedCompare(t *testing.T, v0 []uint64, v1 []uint64, v2 []int6
        }
 }
 
+func testUint64x2Ternary(t *testing.T, v0 []uint64, v1 []uint64, v2 []uint64, want []uint64, which string) {
+       t.Helper()
+       var gotv simd.Uint64x2
+       got := make([]uint64, len(want))
+       vec0 := simd.LoadUint64x2Slice(v0)
+       vec1 := simd.LoadUint64x2Slice(v1)
+       vec2 := simd.LoadUint64x2Slice(v2)
+       switch which {
+       case "ShiftLeftAndFillUpperFrom":
+               gotv = vec0.ShiftLeftAndFillUpperFrom(vec1, vec2)
+       case "ShiftRightAndFillUpperFrom":
+               gotv = vec0.ShiftRightAndFillUpperFrom(vec1, vec2)
+
+       default:
+               t.Errorf("Unknown method: Uint64x2.%s", which)
+       }
+       gotv.StoreSlice(got)
+       for i := range len(want) {
+               if got[i] != want[i] {
+                       t.Errorf("Result at %d incorrect: want %v, got %v", i, want[i], got[i])
+               }
+       }
+}
+
+func testUint64x2TernaryMasked(t *testing.T, v0 []uint64, v1 []uint64, v2 []uint64, v3 []int64, want []uint64, which string) {
+       t.Helper()
+       var gotv simd.Uint64x2
+       got := make([]uint64, len(want))
+       vec0 := simd.LoadUint64x2Slice(v0)
+       vec1 := simd.LoadUint64x2Slice(v1)
+       vec2 := simd.LoadUint64x2Slice(v2)
+       vec3 := simd.LoadInt64x2Slice(v3)
+       switch which {
+       case "MaskedShiftLeftAndFillUpperFrom":
+               gotv = vec0.MaskedShiftLeftAndFillUpperFrom(vec1, vec2, vec3.AsMask64x2())
+       case "MaskedShiftRightAndFillUpperFrom":
+               gotv = vec0.MaskedShiftRightAndFillUpperFrom(vec1, vec2, vec3.AsMask64x2())
+
+       default:
+               t.Errorf("Unknown method: Uint64x2.%s", which)
+       }
+       gotv.StoreSlice(got)
+       for i := range len(want) {
+               if got[i] != want[i] {
+                       t.Errorf("Result at %d incorrect: want %v, got %v", i, want[i], got[i])
+               }
+       }
+}
+
 func testUint64x2Unary(t *testing.T, v0 []uint64, want []uint64, which string) {
        t.Helper()
        var gotv simd.Uint64x2
@@ -6401,6 +7457,16 @@ func testUint64x4Binary(t *testing.T, v0 []uint64, v1 []uint64, want []uint64, w
                gotv = vec0.MulEvenWiden(vec1)
        case "Or":
                gotv = vec0.Or(vec1)
+       case "RotateLeft":
+               gotv = vec0.RotateLeft(vec1)
+       case "RotateRight":
+               gotv = vec0.RotateRight(vec1)
+       case "ShiftLeft":
+               gotv = vec0.ShiftLeft(vec1)
+       case "ShiftRight":
+               gotv = vec0.ShiftRight(vec1)
+       case "ShiftRightSignExtended":
+               gotv = vec0.ShiftRightSignExtended(vec1)
        case "Sub":
                gotv = vec0.Sub(vec1)
        case "Xor":
@@ -6439,6 +7505,16 @@ func testUint64x4BinaryMasked(t *testing.T, v0 []uint64, v1 []uint64, v2 []int64
                gotv = vec0.MaskedMulEvenWiden(vec1, vec2.AsMask64x4())
        case "MaskedOr":
                gotv = vec0.MaskedOr(vec1, vec2.AsMask64x4())
+       case "MaskedRotateLeft":
+               gotv = vec0.MaskedRotateLeft(vec1, vec2.AsMask64x4())
+       case "MaskedRotateRight":
+               gotv = vec0.MaskedRotateRight(vec1, vec2.AsMask64x4())
+       case "MaskedShiftLeft":
+               gotv = vec0.MaskedShiftLeft(vec1, vec2.AsMask64x4())
+       case "MaskedShiftRight":
+               gotv = vec0.MaskedShiftRight(vec1, vec2.AsMask64x4())
+       case "MaskedShiftRightSignExtended":
+               gotv = vec0.MaskedShiftRightSignExtended(vec1, vec2.AsMask64x4())
        case "MaskedSub":
                gotv = vec0.MaskedSub(vec1, vec2.AsMask64x4())
        case "MaskedXor":
@@ -6518,6 +7594,55 @@ func testUint64x4MaskedCompare(t *testing.T, v0 []uint64, v1 []uint64, v2 []int6
        }
 }
 
+func testUint64x4Ternary(t *testing.T, v0 []uint64, v1 []uint64, v2 []uint64, want []uint64, which string) {
+       t.Helper()
+       var gotv simd.Uint64x4
+       got := make([]uint64, len(want))
+       vec0 := simd.LoadUint64x4Slice(v0)
+       vec1 := simd.LoadUint64x4Slice(v1)
+       vec2 := simd.LoadUint64x4Slice(v2)
+       switch which {
+       case "ShiftLeftAndFillUpperFrom":
+               gotv = vec0.ShiftLeftAndFillUpperFrom(vec1, vec2)
+       case "ShiftRightAndFillUpperFrom":
+               gotv = vec0.ShiftRightAndFillUpperFrom(vec1, vec2)
+
+       default:
+               t.Errorf("Unknown method: Uint64x4.%s", which)
+       }
+       gotv.StoreSlice(got)
+       for i := range len(want) {
+               if got[i] != want[i] {
+                       t.Errorf("Result at %d incorrect: want %v, got %v", i, want[i], got[i])
+               }
+       }
+}
+
+func testUint64x4TernaryMasked(t *testing.T, v0 []uint64, v1 []uint64, v2 []uint64, v3 []int64, want []uint64, which string) {
+       t.Helper()
+       var gotv simd.Uint64x4
+       got := make([]uint64, len(want))
+       vec0 := simd.LoadUint64x4Slice(v0)
+       vec1 := simd.LoadUint64x4Slice(v1)
+       vec2 := simd.LoadUint64x4Slice(v2)
+       vec3 := simd.LoadInt64x4Slice(v3)
+       switch which {
+       case "MaskedShiftLeftAndFillUpperFrom":
+               gotv = vec0.MaskedShiftLeftAndFillUpperFrom(vec1, vec2, vec3.AsMask64x4())
+       case "MaskedShiftRightAndFillUpperFrom":
+               gotv = vec0.MaskedShiftRightAndFillUpperFrom(vec1, vec2, vec3.AsMask64x4())
+
+       default:
+               t.Errorf("Unknown method: Uint64x4.%s", which)
+       }
+       gotv.StoreSlice(got)
+       for i := range len(want) {
+               if got[i] != want[i] {
+                       t.Errorf("Result at %d incorrect: want %v, got %v", i, want[i], got[i])
+               }
+       }
+}
+
 func testUint64x4Unary(t *testing.T, v0 []uint64, want []uint64, which string) {
        t.Helper()
        var gotv simd.Uint64x4
@@ -6580,6 +7705,16 @@ func testUint64x8Binary(t *testing.T, v0 []uint64, v1 []uint64, want []uint64, w
                gotv = vec0.MulEvenWiden(vec1)
        case "Or":
                gotv = vec0.Or(vec1)
+       case "RotateLeft":
+               gotv = vec0.RotateLeft(vec1)
+       case "RotateRight":
+               gotv = vec0.RotateRight(vec1)
+       case "ShiftLeft":
+               gotv = vec0.ShiftLeft(vec1)
+       case "ShiftRight":
+               gotv = vec0.ShiftRight(vec1)
+       case "ShiftRightSignExtended":
+               gotv = vec0.ShiftRightSignExtended(vec1)
        case "Sub":
                gotv = vec0.Sub(vec1)
        case "Xor":
@@ -6618,6 +7753,16 @@ func testUint64x8BinaryMasked(t *testing.T, v0 []uint64, v1 []uint64, v2 []int64
                gotv = vec0.MaskedMulEvenWiden(vec1, vec2.AsMask64x8())
        case "MaskedOr":
                gotv = vec0.MaskedOr(vec1, vec2.AsMask64x8())
+       case "MaskedRotateLeft":
+               gotv = vec0.MaskedRotateLeft(vec1, vec2.AsMask64x8())
+       case "MaskedRotateRight":
+               gotv = vec0.MaskedRotateRight(vec1, vec2.AsMask64x8())
+       case "MaskedShiftLeft":
+               gotv = vec0.MaskedShiftLeft(vec1, vec2.AsMask64x8())
+       case "MaskedShiftRight":
+               gotv = vec0.MaskedShiftRight(vec1, vec2.AsMask64x8())
+       case "MaskedShiftRightSignExtended":
+               gotv = vec0.MaskedShiftRightSignExtended(vec1, vec2.AsMask64x8())
        case "MaskedSub":
                gotv = vec0.MaskedSub(vec1, vec2.AsMask64x8())
        case "MaskedXor":
@@ -6697,6 +7842,55 @@ func testUint64x8MaskedCompare(t *testing.T, v0 []uint64, v1 []uint64, v2 []int6
        }
 }
 
+func testUint64x8Ternary(t *testing.T, v0 []uint64, v1 []uint64, v2 []uint64, want []uint64, which string) {
+       t.Helper()
+       var gotv simd.Uint64x8
+       got := make([]uint64, len(want))
+       vec0 := simd.LoadUint64x8Slice(v0)
+       vec1 := simd.LoadUint64x8Slice(v1)
+       vec2 := simd.LoadUint64x8Slice(v2)
+       switch which {
+       case "ShiftLeftAndFillUpperFrom":
+               gotv = vec0.ShiftLeftAndFillUpperFrom(vec1, vec2)
+       case "ShiftRightAndFillUpperFrom":
+               gotv = vec0.ShiftRightAndFillUpperFrom(vec1, vec2)
+
+       default:
+               t.Errorf("Unknown method: Uint64x8.%s", which)
+       }
+       gotv.StoreSlice(got)
+       for i := range len(want) {
+               if got[i] != want[i] {
+                       t.Errorf("Result at %d incorrect: want %v, got %v", i, want[i], got[i])
+               }
+       }
+}
+
+func testUint64x8TernaryMasked(t *testing.T, v0 []uint64, v1 []uint64, v2 []uint64, v3 []int64, want []uint64, which string) {
+       t.Helper()
+       var gotv simd.Uint64x8
+       got := make([]uint64, len(want))
+       vec0 := simd.LoadUint64x8Slice(v0)
+       vec1 := simd.LoadUint64x8Slice(v1)
+       vec2 := simd.LoadUint64x8Slice(v2)
+       vec3 := simd.LoadInt64x8Slice(v3)
+       switch which {
+       case "MaskedShiftLeftAndFillUpperFrom":
+               gotv = vec0.MaskedShiftLeftAndFillUpperFrom(vec1, vec2, vec3.AsMask64x8())
+       case "MaskedShiftRightAndFillUpperFrom":
+               gotv = vec0.MaskedShiftRightAndFillUpperFrom(vec1, vec2, vec3.AsMask64x8())
+
+       default:
+               t.Errorf("Unknown method: Uint64x8.%s", which)
+       }
+       gotv.StoreSlice(got)
+       for i := range len(want) {
+               if got[i] != want[i] {
+                       t.Errorf("Result at %d incorrect: want %v, got %v", i, want[i], got[i])
+               }
+       }
+}
+
 func testUint64x8Unary(t *testing.T, v0 []uint64, want []uint64, which string) {
        t.Helper()
        var gotv simd.Uint64x8
@@ -6737,3 +7931,54 @@ func testUint64x8UnaryMasked(t *testing.T, v0 []uint64, v1 []int64, want []uint6
                }
        }
 }
+
+/* The operations below cannot be tested via wrappers, please test them directly */
+
+// CeilSuppressExceptionWithPrecision
+// CeilWithPrecision
+// DiffWithCeilSuppressExceptionWithPrecision
+// DiffWithCeilWithPrecision
+// DiffWithFloorSuppressExceptionWithPrecision
+// DiffWithFloorWithPrecision
+// DiffWithRoundSuppressExceptionWithPrecision
+// DiffWithRoundWithPrecision
+// DiffWithTruncSuppressExceptionWithPrecision
+// DiffWithTruncWithPrecision
+// FloorSuppressExceptionWithPrecision
+// FloorWithPrecision
+// GetElem
+// MaskedCeilSuppressExceptionWithPrecision
+// MaskedCeilWithPrecision
+// MaskedDiffWithCeilSuppressExceptionWithPrecision
+// MaskedDiffWithCeilWithPrecision
+// MaskedDiffWithFloorSuppressExceptionWithPrecision
+// MaskedDiffWithFloorWithPrecision
+// MaskedDiffWithRoundSuppressExceptionWithPrecision
+// MaskedDiffWithRoundWithPrecision
+// MaskedDiffWithTruncSuppressExceptionWithPrecision
+// MaskedDiffWithTruncWithPrecision
+// MaskedFloorSuppressExceptionWithPrecision
+// MaskedFloorWithPrecision
+// MaskedRotateAllLeft
+// MaskedRotateAllRight
+// MaskedRoundSuppressExceptionWithPrecision
+// MaskedRoundWithPrecision
+// MaskedShiftAllLeft
+// MaskedShiftAllLeftAndFillUpperFrom
+// MaskedShiftAllRight
+// MaskedShiftAllRightAndFillUpperFrom
+// MaskedShiftAllRightSignExtended
+// MaskedTruncSuppressExceptionWithPrecision
+// MaskedTruncWithPrecision
+// RotateAllLeft
+// RotateAllRight
+// RoundSuppressExceptionWithPrecision
+// RoundWithPrecision
+// SetElem
+// ShiftAllLeft
+// ShiftAllLeftAndFillUpperFrom
+// ShiftAllRight
+// ShiftAllRightAndFillUpperFrom
+// ShiftAllRightSignExtended
+// TruncSuppressExceptionWithPrecision
+// TruncWithPrecision

diff --git a/src/simd/stubs_amd64.go b/src/simd/stubs_amd64.go
index 5037e4e024e1c93aa531b686776cf934594275d4..330ad6aca2a7030767ec2e4c2c734e0d19dc279e 100644 (file)
--- a/src/simd/stubs_amd64.go
+++ b/src/simd/stubs_amd64.go
@@ -5178,6 +5178,254 @@ func (x Uint64x4) MaskedPopCount(y Mask64x4) Uint64x4
 // Asm: VPOPCNTQ, CPU Feature: AVX512EVEX
 func (x Uint64x8) MaskedPopCount(y Mask64x8) Uint64x8
 
+/* MaskedRotateAllLeft */
+
+// RotateAllLeft rotates each element to the left by the number of bits specified by the immediate.
+//
+// Asm: VPROLD, CPU Feature: AVX512EVEX
+func (x Int32x4) MaskedRotateAllLeft(imm uint8, y Mask32x4) Int32x4
+
+// RotateAllLeft rotates each element to the left by the number of bits specified by the immediate.
+//
+// Asm: VPROLD, CPU Feature: AVX512EVEX
+func (x Int32x8) MaskedRotateAllLeft(imm uint8, y Mask32x8) Int32x8
+
+// RotateAllLeft rotates each element to the left by the number of bits specified by the immediate.
+//
+// Asm: VPROLD, CPU Feature: AVX512EVEX
+func (x Int32x16) MaskedRotateAllLeft(imm uint8, y Mask32x16) Int32x16
+
+// RotateAllLeft rotates each element to the left by the number of bits specified by the immediate.
+//
+// Asm: VPROLQ, CPU Feature: AVX512EVEX
+func (x Int64x2) MaskedRotateAllLeft(imm uint8, y Mask64x2) Int64x2
+
+// RotateAllLeft rotates each element to the left by the number of bits specified by the immediate.
+//
+// Asm: VPROLQ, CPU Feature: AVX512EVEX
+func (x Int64x4) MaskedRotateAllLeft(imm uint8, y Mask64x4) Int64x4
+
+// RotateAllLeft rotates each element to the left by the number of bits specified by the immediate.
+//
+// Asm: VPROLQ, CPU Feature: AVX512EVEX
+func (x Int64x8) MaskedRotateAllLeft(imm uint8, y Mask64x8) Int64x8
+
+// RotateAllLeft rotates each element to the left by the number of bits specified by the immediate.
+//
+// Asm: VPROLD, CPU Feature: AVX512EVEX
+func (x Uint32x4) MaskedRotateAllLeft(imm uint8, y Mask32x4) Uint32x4
+
+// RotateAllLeft rotates each element to the left by the number of bits specified by the immediate.
+//
+// Asm: VPROLD, CPU Feature: AVX512EVEX
+func (x Uint32x8) MaskedRotateAllLeft(imm uint8, y Mask32x8) Uint32x8
+
+// RotateAllLeft rotates each element to the left by the number of bits specified by the immediate.
+//
+// Asm: VPROLD, CPU Feature: AVX512EVEX
+func (x Uint32x16) MaskedRotateAllLeft(imm uint8, y Mask32x16) Uint32x16
+
+// RotateAllLeft rotates each element to the left by the number of bits specified by the immediate.
+//
+// Asm: VPROLQ, CPU Feature: AVX512EVEX
+func (x Uint64x2) MaskedRotateAllLeft(imm uint8, y Mask64x2) Uint64x2
+
+// RotateAllLeft rotates each element to the left by the number of bits specified by the immediate.
+//
+// Asm: VPROLQ, CPU Feature: AVX512EVEX
+func (x Uint64x4) MaskedRotateAllLeft(imm uint8, y Mask64x4) Uint64x4
+
+// RotateAllLeft rotates each element to the left by the number of bits specified by the immediate.
+//
+// Asm: VPROLQ, CPU Feature: AVX512EVEX
+func (x Uint64x8) MaskedRotateAllLeft(imm uint8, y Mask64x8) Uint64x8
+
+/* MaskedRotateAllRight */
+
+// RotateAllRight rotates each element to the right by the number of bits specified by the immediate.
+//
+// Asm: VPRORD, CPU Feature: AVX512EVEX
+func (x Int32x4) MaskedRotateAllRight(imm uint8, y Mask32x4) Int32x4
+
+// RotateAllRight rotates each element to the right by the number of bits specified by the immediate.
+//
+// Asm: VPRORD, CPU Feature: AVX512EVEX
+func (x Int32x8) MaskedRotateAllRight(imm uint8, y Mask32x8) Int32x8
+
+// RotateAllRight rotates each element to the right by the number of bits specified by the immediate.
+//
+// Asm: VPRORD, CPU Feature: AVX512EVEX
+func (x Int32x16) MaskedRotateAllRight(imm uint8, y Mask32x16) Int32x16
+
+// RotateAllRight rotates each element to the right by the number of bits specified by the immediate.
+//
+// Asm: VPRORQ, CPU Feature: AVX512EVEX
+func (x Int64x2) MaskedRotateAllRight(imm uint8, y Mask64x2) Int64x2
+
+// RotateAllRight rotates each element to the right by the number of bits specified by the immediate.
+//
+// Asm: VPRORQ, CPU Feature: AVX512EVEX
+func (x Int64x4) MaskedRotateAllRight(imm uint8, y Mask64x4) Int64x4
+
+// RotateAllRight rotates each element to the right by the number of bits specified by the immediate.
+//
+// Asm: VPRORQ, CPU Feature: AVX512EVEX
+func (x Int64x8) MaskedRotateAllRight(imm uint8, y Mask64x8) Int64x8
+
+// RotateAllRight rotates each element to the right by the number of bits specified by the immediate.
+//
+// Asm: VPRORD, CPU Feature: AVX512EVEX
+func (x Uint32x4) MaskedRotateAllRight(imm uint8, y Mask32x4) Uint32x4
+
+// RotateAllRight rotates each element to the right by the number of bits specified by the immediate.
+//
+// Asm: VPRORD, CPU Feature: AVX512EVEX
+func (x Uint32x8) MaskedRotateAllRight(imm uint8, y Mask32x8) Uint32x8
+
+// RotateAllRight rotates each element to the right by the number of bits specified by the immediate.
+//
+// Asm: VPRORD, CPU Feature: AVX512EVEX
+func (x Uint32x16) MaskedRotateAllRight(imm uint8, y Mask32x16) Uint32x16
+
+// RotateAllRight rotates each element to the right by the number of bits specified by the immediate.
+//
+// Asm: VPRORQ, CPU Feature: AVX512EVEX
+func (x Uint64x2) MaskedRotateAllRight(imm uint8, y Mask64x2) Uint64x2
+
+// RotateAllRight rotates each element to the right by the number of bits specified by the immediate.
+//
+// Asm: VPRORQ, CPU Feature: AVX512EVEX
+func (x Uint64x4) MaskedRotateAllRight(imm uint8, y Mask64x4) Uint64x4
+
+// RotateAllRight rotates each element to the right by the number of bits specified by the immediate.
+//
+// Asm: VPRORQ, CPU Feature: AVX512EVEX
+func (x Uint64x8) MaskedRotateAllRight(imm uint8, y Mask64x8) Uint64x8
+
+/* MaskedRotateLeft */
+
+// RotateLeft rotates each element in x to the left by the number of bits specified by y's corresponding elements.
+//
+// Asm: VPROLVD, CPU Feature: AVX512EVEX
+func (x Int32x4) MaskedRotateLeft(y Int32x4, z Mask32x4) Int32x4
+
+// RotateLeft rotates each element in x to the left by the number of bits specified by y's corresponding elements.
+//
+// Asm: VPROLVD, CPU Feature: AVX512EVEX
+func (x Int32x8) MaskedRotateLeft(y Int32x8, z Mask32x8) Int32x8
+
+// RotateLeft rotates each element in x to the left by the number of bits specified by y's corresponding elements.
+//
+// Asm: VPROLVD, CPU Feature: AVX512EVEX
+func (x Int32x16) MaskedRotateLeft(y Int32x16, z Mask32x16) Int32x16
+
+// RotateLeft rotates each element in x to the left by the number of bits specified by y's corresponding elements.
+//
+// Asm: VPROLVQ, CPU Feature: AVX512EVEX
+func (x Int64x2) MaskedRotateLeft(y Int64x2, z Mask64x2) Int64x2
+
+// RotateLeft rotates each element in x to the left by the number of bits specified by y's corresponding elements.
+//
+// Asm: VPROLVQ, CPU Feature: AVX512EVEX
+func (x Int64x4) MaskedRotateLeft(y Int64x4, z Mask64x4) Int64x4
+
+// RotateLeft rotates each element in x to the left by the number of bits specified by y's corresponding elements.
+//
+// Asm: VPROLVQ, CPU Feature: AVX512EVEX
+func (x Int64x8) MaskedRotateLeft(y Int64x8, z Mask64x8) Int64x8
+
+// RotateLeft rotates each element in x to the left by the number of bits specified by y's corresponding elements.
+//
+// Asm: VPROLVD, CPU Feature: AVX512EVEX
+func (x Uint32x4) MaskedRotateLeft(y Uint32x4, z Mask32x4) Uint32x4
+
+// RotateLeft rotates each element in x to the left by the number of bits specified by y's corresponding elements.
+//
+// Asm: VPROLVD, CPU Feature: AVX512EVEX
+func (x Uint32x8) MaskedRotateLeft(y Uint32x8, z Mask32x8) Uint32x8
+
+// RotateLeft rotates each element in x to the left by the number of bits specified by y's corresponding elements.
+//
+// Asm: VPROLVD, CPU Feature: AVX512EVEX
+func (x Uint32x16) MaskedRotateLeft(y Uint32x16, z Mask32x16) Uint32x16
+
+// RotateLeft rotates each element in x to the left by the number of bits specified by y's corresponding elements.
+//
+// Asm: VPROLVQ, CPU Feature: AVX512EVEX
+func (x Uint64x2) MaskedRotateLeft(y Uint64x2, z Mask64x2) Uint64x2
+
+// RotateLeft rotates each element in x to the left by the number of bits specified by y's corresponding elements.
+//
+// Asm: VPROLVQ, CPU Feature: AVX512EVEX
+func (x Uint64x4) MaskedRotateLeft(y Uint64x4, z Mask64x4) Uint64x4
+
+// RotateLeft rotates each element in x to the left by the number of bits specified by y's corresponding elements.
+//
+// Asm: VPROLVQ, CPU Feature: AVX512EVEX
+func (x Uint64x8) MaskedRotateLeft(y Uint64x8, z Mask64x8) Uint64x8
+
+/* MaskedRotateRight */
+
+// RotateRight rotates each element in x to the right by the number of bits specified by y's corresponding elements.
+//
+// Asm: VPRORVD, CPU Feature: AVX512EVEX
+func (x Int32x4) MaskedRotateRight(y Int32x4, z Mask32x4) Int32x4
+
+// RotateRight rotates each element in x to the right by the number of bits specified by y's corresponding elements.
+//
+// Asm: VPRORVD, CPU Feature: AVX512EVEX
+func (x Int32x8) MaskedRotateRight(y Int32x8, z Mask32x8) Int32x8
+
+// RotateRight rotates each element in x to the right by the number of bits specified by y's corresponding elements.
+//
+// Asm: VPRORVD, CPU Feature: AVX512EVEX
+func (x Int32x16) MaskedRotateRight(y Int32x16, z Mask32x16) Int32x16
+
+// RotateRight rotates each element in x to the right by the number of bits specified by y's corresponding elements.
+//
+// Asm: VPRORVQ, CPU Feature: AVX512EVEX
+func (x Int64x2) MaskedRotateRight(y Int64x2, z Mask64x2) Int64x2
+
+// RotateRight rotates each element in x to the right by the number of bits specified by y's corresponding elements.
+//
+// Asm: VPRORVQ, CPU Feature: AVX512EVEX
+func (x Int64x4) MaskedRotateRight(y Int64x4, z Mask64x4) Int64x4
+
+// RotateRight rotates each element in x to the right by the number of bits specified by y's corresponding elements.
+//
+// Asm: VPRORVQ, CPU Feature: AVX512EVEX
+func (x Int64x8) MaskedRotateRight(y Int64x8, z Mask64x8) Int64x8
+
+// RotateRight rotates each element in x to the right by the number of bits specified by y's corresponding elements.
+//
+// Asm: VPRORVD, CPU Feature: AVX512EVEX
+func (x Uint32x4) MaskedRotateRight(y Uint32x4, z Mask32x4) Uint32x4
+
+// RotateRight rotates each element in x to the right by the number of bits specified by y's corresponding elements.
+//
+// Asm: VPRORVD, CPU Feature: AVX512EVEX
+func (x Uint32x8) MaskedRotateRight(y Uint32x8, z Mask32x8) Uint32x8
+
+// RotateRight rotates each element in x to the right by the number of bits specified by y's corresponding elements.
+//
+// Asm: VPRORVD, CPU Feature: AVX512EVEX
+func (x Uint32x16) MaskedRotateRight(y Uint32x16, z Mask32x16) Uint32x16
+
+// RotateRight rotates each element in x to the right by the number of bits specified by y's corresponding elements.
+//
+// Asm: VPRORVQ, CPU Feature: AVX512EVEX
+func (x Uint64x2) MaskedRotateRight(y Uint64x2, z Mask64x2) Uint64x2
+
+// RotateRight rotates each element in x to the right by the number of bits specified by y's corresponding elements.
+//
+// Asm: VPRORVQ, CPU Feature: AVX512EVEX
+func (x Uint64x4) MaskedRotateRight(y Uint64x4, z Mask64x4) Uint64x4
+
+// RotateRight rotates each element in x to the right by the number of bits specified by y's corresponding elements.
+//
+// Asm: VPRORVQ, CPU Feature: AVX512EVEX
+func (x Uint64x8) MaskedRotateRight(y Uint64x8, z Mask64x8) Uint64x8
+
 /* MaskedRoundSuppressExceptionWithPrecision */
 
 // RoundSuppressExceptionWithPrecision rounds elements with specified precision, suppressing exceptions.
@@ -5447,1884 +5695,3826 @@ func (x Uint32x8) MaskedSaturatedUnsignedSignedQuadDotProdAccumulate(y Uint8x32,
 // Asm: VPDPBUSDS, CPU Feature: AVX512EVEX
 func (x Uint32x16) MaskedSaturatedUnsignedSignedQuadDotProdAccumulate(y Uint8x64, z Int8x64, u Mask32x16) Uint32x16
 
-/* MaskedSqrt */
+/* MaskedShiftAllLeft */
 
-// Sqrt computes the square root of each element.
+// ShiftAllLeft shifts each element to the left by the specified number of bits. Emptied lower bits are zeroed.
 //
-// Asm: VSQRTPS, CPU Feature: AVX512EVEX
-func (x Float32x4) MaskedSqrt(y Mask32x4) Float32x4
+// Asm: VPSLLQ, CPU Feature: AVX512EVEX
+func (x Int64x2) MaskedShiftAllLeft(y uint64, z Mask64x2) Int64x2
 
-// Sqrt computes the square root of each element.
+// ShiftAllLeft shifts each element to the left by the specified number of bits. Emptied lower bits are zeroed.
 //
-// Asm: VSQRTPS, CPU Feature: AVX512EVEX
-func (x Float32x8) MaskedSqrt(y Mask32x8) Float32x8
+// Asm: VPSLLQ, CPU Feature: AVX512EVEX
+func (x Int64x4) MaskedShiftAllLeft(y uint64, z Mask64x4) Int64x4
 
-// Sqrt computes the square root of each element.
+// ShiftAllLeft shifts each element to the left by the specified number of bits. Emptied lower bits are zeroed.
 //
-// Asm: VSQRTPS, CPU Feature: AVX512EVEX
-func (x Float32x16) MaskedSqrt(y Mask32x16) Float32x16
+// Asm: VPSLLQ, CPU Feature: AVX512EVEX
+func (x Int64x8) MaskedShiftAllLeft(y uint64, z Mask64x8) Int64x8
 
-// Sqrt computes the square root of each element.
+// ShiftAllLeft shifts each element to the left by the specified number of bits. Emptied lower bits are zeroed.
 //
-// Asm: VSQRTPD, CPU Feature: AVX512EVEX
-func (x Float64x2) MaskedSqrt(y Mask64x2) Float64x2
+// Asm: VPSLLQ, CPU Feature: AVX512EVEX
+func (x Uint64x2) MaskedShiftAllLeft(y uint64, z Mask64x2) Uint64x2
 
-// Sqrt computes the square root of each element.
+// ShiftAllLeft shifts each element to the left by the specified number of bits. Emptied lower bits are zeroed.
 //
-// Asm: VSQRTPD, CPU Feature: AVX512EVEX
-func (x Float64x4) MaskedSqrt(y Mask64x4) Float64x4
+// Asm: VPSLLQ, CPU Feature: AVX512EVEX
+func (x Uint64x4) MaskedShiftAllLeft(y uint64, z Mask64x4) Uint64x4
 
-// Sqrt computes the square root of each element.
+// ShiftAllLeft shifts each element to the left by the specified number of bits. Emptied lower bits are zeroed.
 //
-// Asm: VSQRTPD, CPU Feature: AVX512EVEX
-func (x Float64x8) MaskedSqrt(y Mask64x8) Float64x8
+// Asm: VPSLLQ, CPU Feature: AVX512EVEX
+func (x Uint64x8) MaskedShiftAllLeft(y uint64, z Mask64x8) Uint64x8
 
-/* MaskedSub */
+/* MaskedShiftAllLeftAndFillUpperFrom */
 
-// Sub subtracts corresponding elements of two vectors.
+// ShiftAllLeftAndFillUpperFrom shifts each element of x to the left by the number of bits specified by the
+// immediate(only the lower 5 bits are used), and then copies the upper bits of y to the emptied lower bits of the shifted x.
 //
-// Asm: VSUBPS, CPU Feature: AVX512EVEX
-func (x Float32x4) MaskedSub(y Float32x4, z Mask32x4) Float32x4
+// Asm: VPSHLDW, CPU Feature: AVX512EVEX
+func (x Int16x8) MaskedShiftAllLeftAndFillUpperFrom(imm uint8, y Int16x8, z Mask16x8) Int16x8
 
-// Sub subtracts corresponding elements of two vectors.
+// ShiftAllLeftAndFillUpperFrom shifts each element of x to the left by the number of bits specified by the
+// immediate(only the lower 5 bits are used), and then copies the upper bits of y to the emptied lower bits of the shifted x.
 //
-// Asm: VSUBPS, CPU Feature: AVX512EVEX
-func (x Float32x8) MaskedSub(y Float32x8, z Mask32x8) Float32x8
+// Asm: VPSHLDW, CPU Feature: AVX512EVEX
+func (x Int16x16) MaskedShiftAllLeftAndFillUpperFrom(imm uint8, y Int16x16, z Mask16x16) Int16x16
 
-// Sub subtracts corresponding elements of two vectors.
+// ShiftAllLeftAndFillUpperFrom shifts each element of x to the left by the number of bits specified by the
+// immediate(only the lower 5 bits are used), and then copies the upper bits of y to the emptied lower bits of the shifted x.
 //
-// Asm: VSUBPS, CPU Feature: AVX512EVEX
-func (x Float32x16) MaskedSub(y Float32x16, z Mask32x16) Float32x16
+// Asm: VPSHLDW, CPU Feature: AVX512EVEX
+func (x Int16x32) MaskedShiftAllLeftAndFillUpperFrom(imm uint8, y Int16x32, z Mask16x32) Int16x32
 
-// Sub subtracts corresponding elements of two vectors.
+// ShiftAllLeftAndFillUpperFrom shifts each element of x to the left by the number of bits specified by the
+// immediate(only the lower 5 bits are used), and then copies the upper bits of y to the emptied lower bits of the shifted x.
 //
-// Asm: VSUBPD, CPU Feature: AVX512EVEX
-func (x Float64x2) MaskedSub(y Float64x2, z Mask64x2) Float64x2
+// Asm: VPSHLDD, CPU Feature: AVX512EVEX
+func (x Int32x4) MaskedShiftAllLeftAndFillUpperFrom(imm uint8, y Int32x4, z Mask32x4) Int32x4
 
-// Sub subtracts corresponding elements of two vectors.
+// ShiftAllLeftAndFillUpperFrom shifts each element of x to the left by the number of bits specified by the
+// immediate(only the lower 5 bits are used), and then copies the upper bits of y to the emptied lower bits of the shifted x.
 //
-// Asm: VSUBPD, CPU Feature: AVX512EVEX
-func (x Float64x4) MaskedSub(y Float64x4, z Mask64x4) Float64x4
+// Asm: VPSHLDD, CPU Feature: AVX512EVEX
+func (x Int32x8) MaskedShiftAllLeftAndFillUpperFrom(imm uint8, y Int32x8, z Mask32x8) Int32x8
 
-// Sub subtracts corresponding elements of two vectors.
+// ShiftAllLeftAndFillUpperFrom shifts each element of x to the left by the number of bits specified by the
+// immediate(only the lower 5 bits are used), and then copies the upper bits of y to the emptied lower bits of the shifted x.
 //
-// Asm: VSUBPD, CPU Feature: AVX512EVEX
-func (x Float64x8) MaskedSub(y Float64x8, z Mask64x8) Float64x8
+// Asm: VPSHLDD, CPU Feature: AVX512EVEX
+func (x Int32x16) MaskedShiftAllLeftAndFillUpperFrom(imm uint8, y Int32x16, z Mask32x16) Int32x16
 
-// Sub subtracts corresponding elements of two vectors.
+// ShiftAllLeftAndFillUpperFrom shifts each element of x to the left by the number of bits specified by the
+// immediate(only the lower 5 bits are used), and then copies the upper bits of y to the emptied lower bits of the shifted x.
 //
-// Asm: VPSUBB, CPU Feature: AVX512EVEX
-func (x Int8x16) MaskedSub(y Int8x16, z Mask8x16) Int8x16
+// Asm: VPSHLDQ, CPU Feature: AVX512EVEX
+func (x Int64x2) MaskedShiftAllLeftAndFillUpperFrom(imm uint8, y Int64x2, z Mask64x2) Int64x2
 
-// Sub subtracts corresponding elements of two vectors.
+// ShiftAllLeftAndFillUpperFrom shifts each element of x to the left by the number of bits specified by the
+// immediate(only the lower 5 bits are used), and then copies the upper bits of y to the emptied lower bits of the shifted x.
 //
-// Asm: VPSUBB, CPU Feature: AVX512EVEX
-func (x Int8x32) MaskedSub(y Int8x32, z Mask8x32) Int8x32
+// Asm: VPSHLDQ, CPU Feature: AVX512EVEX
+func (x Int64x4) MaskedShiftAllLeftAndFillUpperFrom(imm uint8, y Int64x4, z Mask64x4) Int64x4
 
-// Sub subtracts corresponding elements of two vectors.
+// ShiftAllLeftAndFillUpperFrom shifts each element of x to the left by the number of bits specified by the
+// immediate(only the lower 5 bits are used), and then copies the upper bits of y to the emptied lower bits of the shifted x.
 //
-// Asm: VPSUBB, CPU Feature: AVX512EVEX
-func (x Int8x64) MaskedSub(y Int8x64, z Mask8x64) Int8x64
+// Asm: VPSHLDQ, CPU Feature: AVX512EVEX
+func (x Int64x8) MaskedShiftAllLeftAndFillUpperFrom(imm uint8, y Int64x8, z Mask64x8) Int64x8
 
-// Sub subtracts corresponding elements of two vectors.
+// ShiftAllLeftAndFillUpperFrom shifts each element of x to the left by the number of bits specified by the
+// immediate(only the lower 5 bits are used), and then copies the upper bits of y to the emptied lower bits of the shifted x.
 //
-// Asm: VPSUBW, CPU Feature: AVX512EVEX
-func (x Int16x8) MaskedSub(y Int16x8, z Mask16x8) Int16x8
+// Asm: VPSHLDW, CPU Feature: AVX512EVEX
+func (x Uint16x8) MaskedShiftAllLeftAndFillUpperFrom(imm uint8, y Uint16x8, z Mask16x8) Uint16x8
 
-// Sub subtracts corresponding elements of two vectors.
+// ShiftAllLeftAndFillUpperFrom shifts each element of x to the left by the number of bits specified by the
+// immediate(only the lower 5 bits are used), and then copies the upper bits of y to the emptied lower bits of the shifted x.
 //
-// Asm: VPSUBW, CPU Feature: AVX512EVEX
-func (x Int16x16) MaskedSub(y Int16x16, z Mask16x16) Int16x16
+// Asm: VPSHLDW, CPU Feature: AVX512EVEX
+func (x Uint16x16) MaskedShiftAllLeftAndFillUpperFrom(imm uint8, y Uint16x16, z Mask16x16) Uint16x16
 
-// Sub subtracts corresponding elements of two vectors.
+// ShiftAllLeftAndFillUpperFrom shifts each element of x to the left by the number of bits specified by the
+// immediate(only the lower 5 bits are used), and then copies the upper bits of y to the emptied lower bits of the shifted x.
 //
-// Asm: VPSUBW, CPU Feature: AVX512EVEX
-func (x Int16x32) MaskedSub(y Int16x32, z Mask16x32) Int16x32
+// Asm: VPSHLDW, CPU Feature: AVX512EVEX
+func (x Uint16x32) MaskedShiftAllLeftAndFillUpperFrom(imm uint8, y Uint16x32, z Mask16x32) Uint16x32
 
-// Sub subtracts corresponding elements of two vectors.
+// ShiftAllLeftAndFillUpperFrom shifts each element of x to the left by the number of bits specified by the
+// immediate(only the lower 5 bits are used), and then copies the upper bits of y to the emptied lower bits of the shifted x.
 //
-// Asm: VPSUBD, CPU Feature: AVX512EVEX
-func (x Int32x4) MaskedSub(y Int32x4, z Mask32x4) Int32x4
+// Asm: VPSHLDD, CPU Feature: AVX512EVEX
+func (x Uint32x4) MaskedShiftAllLeftAndFillUpperFrom(imm uint8, y Uint32x4, z Mask32x4) Uint32x4
 
-// Sub subtracts corresponding elements of two vectors.
+// ShiftAllLeftAndFillUpperFrom shifts each element of x to the left by the number of bits specified by the
+// immediate(only the lower 5 bits are used), and then copies the upper bits of y to the emptied lower bits of the shifted x.
 //
-// Asm: VPSUBD, CPU Feature: AVX512EVEX
-func (x Int32x8) MaskedSub(y Int32x8, z Mask32x8) Int32x8
+// Asm: VPSHLDD, CPU Feature: AVX512EVEX
+func (x Uint32x8) MaskedShiftAllLeftAndFillUpperFrom(imm uint8, y Uint32x8, z Mask32x8) Uint32x8
 
-// Sub subtracts corresponding elements of two vectors.
+// ShiftAllLeftAndFillUpperFrom shifts each element of x to the left by the number of bits specified by the
+// immediate(only the lower 5 bits are used), and then copies the upper bits of y to the emptied lower bits of the shifted x.
 //
-// Asm: VPSUBD, CPU Feature: AVX512EVEX
-func (x Int32x16) MaskedSub(y Int32x16, z Mask32x16) Int32x16
+// Asm: VPSHLDD, CPU Feature: AVX512EVEX
+func (x Uint32x16) MaskedShiftAllLeftAndFillUpperFrom(imm uint8, y Uint32x16, z Mask32x16) Uint32x16
 
-// Sub subtracts corresponding elements of two vectors.
+// ShiftAllLeftAndFillUpperFrom shifts each element of x to the left by the number of bits specified by the
+// immediate(only the lower 5 bits are used), and then copies the upper bits of y to the emptied lower bits of the shifted x.
 //
-// Asm: VPSUBQ, CPU Feature: AVX512EVEX
-func (x Int64x2) MaskedSub(y Int64x2, z Mask64x2) Int64x2
+// Asm: VPSHLDQ, CPU Feature: AVX512EVEX
+func (x Uint64x2) MaskedShiftAllLeftAndFillUpperFrom(imm uint8, y Uint64x2, z Mask64x2) Uint64x2
 
-// Sub subtracts corresponding elements of two vectors.
+// ShiftAllLeftAndFillUpperFrom shifts each element of x to the left by the number of bits specified by the
+// immediate(only the lower 5 bits are used), and then copies the upper bits of y to the emptied lower bits of the shifted x.
 //
-// Asm: VPSUBQ, CPU Feature: AVX512EVEX
-func (x Int64x4) MaskedSub(y Int64x4, z Mask64x4) Int64x4
+// Asm: VPSHLDQ, CPU Feature: AVX512EVEX
+func (x Uint64x4) MaskedShiftAllLeftAndFillUpperFrom(imm uint8, y Uint64x4, z Mask64x4) Uint64x4
 
-// Sub subtracts corresponding elements of two vectors.
+// ShiftAllLeftAndFillUpperFrom shifts each element of x to the left by the number of bits specified by the
+// immediate(only the lower 5 bits are used), and then copies the upper bits of y to the emptied lower bits of the shifted x.
 //
-// Asm: VPSUBQ, CPU Feature: AVX512EVEX
-func (x Int64x8) MaskedSub(y Int64x8, z Mask64x8) Int64x8
+// Asm: VPSHLDQ, CPU Feature: AVX512EVEX
+func (x Uint64x8) MaskedShiftAllLeftAndFillUpperFrom(imm uint8, y Uint64x8, z Mask64x8) Uint64x8
 
-// Sub subtracts corresponding elements of two vectors.
+/* MaskedShiftAllRight */
+
+// ShiftAllRight shifts each element to the right by the specified number of bits. Emptied upper bits are zeroed.
 //
-// Asm: VPSUBB, CPU Feature: AVX512EVEX
-func (x Uint8x16) MaskedSub(y Uint8x16, z Mask8x16) Uint8x16
+// Asm: VPSRLQ, CPU Feature: AVX512EVEX
+func (x Int64x2) MaskedShiftAllRight(y uint64, z Mask64x2) Int64x2
 
-// Sub subtracts corresponding elements of two vectors.
+// ShiftAllRight shifts each element to the right by the specified number of bits. Emptied upper bits are zeroed.
 //
-// Asm: VPSUBB, CPU Feature: AVX512EVEX
-func (x Uint8x32) MaskedSub(y Uint8x32, z Mask8x32) Uint8x32
+// Asm: VPSRLQ, CPU Feature: AVX512EVEX
+func (x Int64x4) MaskedShiftAllRight(y uint64, z Mask64x4) Int64x4
 
-// Sub subtracts corresponding elements of two vectors.
+// ShiftAllRight shifts each element to the right by the specified number of bits. Emptied upper bits are zeroed.
 //
-// Asm: VPSUBB, CPU Feature: AVX512EVEX
-func (x Uint8x64) MaskedSub(y Uint8x64, z Mask8x64) Uint8x64
+// Asm: VPSRLQ, CPU Feature: AVX512EVEX
+func (x Int64x8) MaskedShiftAllRight(y uint64, z Mask64x8) Int64x8
 
-// Sub subtracts corresponding elements of two vectors.
+// ShiftAllRight shifts each element to the right by the specified number of bits. Emptied upper bits are zeroed.
 //
-// Asm: VPSUBW, CPU Feature: AVX512EVEX
-func (x Uint16x8) MaskedSub(y Uint16x8, z Mask16x8) Uint16x8
+// Asm: VPSRLQ, CPU Feature: AVX512EVEX
+func (x Uint64x2) MaskedShiftAllRight(y uint64, z Mask64x2) Uint64x2
 
-// Sub subtracts corresponding elements of two vectors.
+// ShiftAllRight shifts each element to the right by the specified number of bits. Emptied upper bits are zeroed.
 //
-// Asm: VPSUBW, CPU Feature: AVX512EVEX
-func (x Uint16x16) MaskedSub(y Uint16x16, z Mask16x16) Uint16x16
+// Asm: VPSRLQ, CPU Feature: AVX512EVEX
+func (x Uint64x4) MaskedShiftAllRight(y uint64, z Mask64x4) Uint64x4
 
-// Sub subtracts corresponding elements of two vectors.
+// ShiftAllRight shifts each element to the right by the specified number of bits. Emptied upper bits are zeroed.
 //
-// Asm: VPSUBW, CPU Feature: AVX512EVEX
-func (x Uint16x32) MaskedSub(y Uint16x32, z Mask16x32) Uint16x32
+// Asm: VPSRLQ, CPU Feature: AVX512EVEX
+func (x Uint64x8) MaskedShiftAllRight(y uint64, z Mask64x8) Uint64x8
 
-// Sub subtracts corresponding elements of two vectors.
+/* MaskedShiftAllRightAndFillUpperFrom */
+
+// ShiftAllRightAndFillUpperFrom shifts each element of x to the right by the number of bits specified by the
+// immediate(only the lower 5 bits are used), and then copies the lower bits of y to the emptied upper bits of the shifted x.
 //
-// Asm: VPSUBD, CPU Feature: AVX512EVEX
-func (x Uint32x4) MaskedSub(y Uint32x4, z Mask32x4) Uint32x4
+// Asm: VPSHRDW, CPU Feature: AVX512EVEX
+func (x Int16x8) MaskedShiftAllRightAndFillUpperFrom(imm uint8, y Int16x8, z Mask16x8) Int16x8
 
-// Sub subtracts corresponding elements of two vectors.
+// ShiftAllRightAndFillUpperFrom shifts each element of x to the right by the number of bits specified by the
+// immediate(only the lower 5 bits are used), and then copies the lower bits of y to the emptied upper bits of the shifted x.
 //
-// Asm: VPSUBD, CPU Feature: AVX512EVEX
-func (x Uint32x8) MaskedSub(y Uint32x8, z Mask32x8) Uint32x8
+// Asm: VPSHRDW, CPU Feature: AVX512EVEX
+func (x Int16x16) MaskedShiftAllRightAndFillUpperFrom(imm uint8, y Int16x16, z Mask16x16) Int16x16
 
-// Sub subtracts corresponding elements of two vectors.
+// ShiftAllRightAndFillUpperFrom shifts each element of x to the right by the number of bits specified by the
+// immediate(only the lower 5 bits are used), and then copies the lower bits of y to the emptied upper bits of the shifted x.
 //
-// Asm: VPSUBD, CPU Feature: AVX512EVEX
-func (x Uint32x16) MaskedSub(y Uint32x16, z Mask32x16) Uint32x16
+// Asm: VPSHRDW, CPU Feature: AVX512EVEX
+func (x Int16x32) MaskedShiftAllRightAndFillUpperFrom(imm uint8, y Int16x32, z Mask16x32) Int16x32
 
-// Sub subtracts corresponding elements of two vectors.
+// ShiftAllRightAndFillUpperFrom shifts each element of x to the right by the number of bits specified by the
+// immediate(only the lower 5 bits are used), and then copies the lower bits of y to the emptied upper bits of the shifted x.
 //
-// Asm: VPSUBQ, CPU Feature: AVX512EVEX
-func (x Uint64x2) MaskedSub(y Uint64x2, z Mask64x2) Uint64x2
+// Asm: VPSHRDD, CPU Feature: AVX512EVEX
+func (x Int32x4) MaskedShiftAllRightAndFillUpperFrom(imm uint8, y Int32x4, z Mask32x4) Int32x4
 
-// Sub subtracts corresponding elements of two vectors.
+// ShiftAllRightAndFillUpperFrom shifts each element of x to the right by the number of bits specified by the
+// immediate(only the lower 5 bits are used), and then copies the lower bits of y to the emptied upper bits of the shifted x.
 //
-// Asm: VPSUBQ, CPU Feature: AVX512EVEX
-func (x Uint64x4) MaskedSub(y Uint64x4, z Mask64x4) Uint64x4
+// Asm: VPSHRDD, CPU Feature: AVX512EVEX
+func (x Int32x8) MaskedShiftAllRightAndFillUpperFrom(imm uint8, y Int32x8, z Mask32x8) Int32x8
 
-// Sub subtracts corresponding elements of two vectors.
+// ShiftAllRightAndFillUpperFrom shifts each element of x to the right by the number of bits specified by the
+// immediate(only the lower 5 bits are used), and then copies the lower bits of y to the emptied upper bits of the shifted x.
 //
-// Asm: VPSUBQ, CPU Feature: AVX512EVEX
-func (x Uint64x8) MaskedSub(y Uint64x8, z Mask64x8) Uint64x8
+// Asm: VPSHRDD, CPU Feature: AVX512EVEX
+func (x Int32x16) MaskedShiftAllRightAndFillUpperFrom(imm uint8, y Int32x16, z Mask32x16) Int32x16
 
-/* MaskedTruncSuppressExceptionWithPrecision */
+// ShiftAllRightAndFillUpperFrom shifts each element of x to the right by the number of bits specified by the
+// immediate(only the lower 5 bits are used), and then copies the lower bits of y to the emptied upper bits of the shifted x.
+//
+// Asm: VPSHRDQ, CPU Feature: AVX512EVEX
+func (x Int64x2) MaskedShiftAllRightAndFillUpperFrom(imm uint8, y Int64x2, z Mask64x2) Int64x2
 
-// TruncSuppressExceptionWithPrecision truncates elements with specified precision, suppressing exceptions.
-// Const Immediate = 11.
+// ShiftAllRightAndFillUpperFrom shifts each element of x to the right by the number of bits specified by the
+// immediate(only the lower 5 bits are used), and then copies the lower bits of y to the emptied upper bits of the shifted x.
 //
-// Asm: VRNDSCALEPS, CPU Feature: AVX512EVEX
-func (x Float32x4) MaskedTruncSuppressExceptionWithPrecision(imm uint8, y Mask32x4) Float32x4
+// Asm: VPSHRDQ, CPU Feature: AVX512EVEX
+func (x Int64x4) MaskedShiftAllRightAndFillUpperFrom(imm uint8, y Int64x4, z Mask64x4) Int64x4
 
-// TruncSuppressExceptionWithPrecision truncates elements with specified precision, suppressing exceptions.
-// Const Immediate = 11.
+// ShiftAllRightAndFillUpperFrom shifts each element of x to the right by the number of bits specified by the
+// immediate(only the lower 5 bits are used), and then copies the lower bits of y to the emptied upper bits of the shifted x.
 //
-// Asm: VRNDSCALEPS, CPU Feature: AVX512EVEX
-func (x Float32x8) MaskedTruncSuppressExceptionWithPrecision(imm uint8, y Mask32x8) Float32x8
+// Asm: VPSHRDQ, CPU Feature: AVX512EVEX
+func (x Int64x8) MaskedShiftAllRightAndFillUpperFrom(imm uint8, y Int64x8, z Mask64x8) Int64x8
 
-// TruncSuppressExceptionWithPrecision truncates elements with specified precision, suppressing exceptions.
-// Const Immediate = 11.
+// ShiftAllRightAndFillUpperFrom shifts each element of x to the right by the number of bits specified by the
+// immediate(only the lower 5 bits are used), and then copies the lower bits of y to the emptied upper bits of the shifted x.
 //
-// Asm: VRNDSCALEPS, CPU Feature: AVX512EVEX
-func (x Float32x16) MaskedTruncSuppressExceptionWithPrecision(imm uint8, y Mask32x16) Float32x16
+// Asm: VPSHRDW, CPU Feature: AVX512EVEX
+func (x Uint16x8) MaskedShiftAllRightAndFillUpperFrom(imm uint8, y Uint16x8, z Mask16x8) Uint16x8
 
-// TruncSuppressExceptionWithPrecision truncates elements with specified precision, suppressing exceptions.
-// Const Immediate = 11.
+// ShiftAllRightAndFillUpperFrom shifts each element of x to the right by the number of bits specified by the
+// immediate(only the lower 5 bits are used), and then copies the lower bits of y to the emptied upper bits of the shifted x.
 //
-// Asm: VRNDSCALEPD, CPU Feature: AVX512EVEX
-func (x Float64x2) MaskedTruncSuppressExceptionWithPrecision(imm uint8, y Mask64x2) Float64x2
+// Asm: VPSHRDW, CPU Feature: AVX512EVEX
+func (x Uint16x16) MaskedShiftAllRightAndFillUpperFrom(imm uint8, y Uint16x16, z Mask16x16) Uint16x16
 
-// TruncSuppressExceptionWithPrecision truncates elements with specified precision, suppressing exceptions.
-// Const Immediate = 11.
+// ShiftAllRightAndFillUpperFrom shifts each element of x to the right by the number of bits specified by the
+// immediate(only the lower 5 bits are used), and then copies the lower bits of y to the emptied upper bits of the shifted x.
 //
-// Asm: VRNDSCALEPD, CPU Feature: AVX512EVEX
-func (x Float64x4) MaskedTruncSuppressExceptionWithPrecision(imm uint8, y Mask64x4) Float64x4
+// Asm: VPSHRDW, CPU Feature: AVX512EVEX
+func (x Uint16x32) MaskedShiftAllRightAndFillUpperFrom(imm uint8, y Uint16x32, z Mask16x32) Uint16x32
 
-// TruncSuppressExceptionWithPrecision truncates elements with specified precision, suppressing exceptions.
-// Const Immediate = 11.
+// ShiftAllRightAndFillUpperFrom shifts each element of x to the right by the number of bits specified by the
+// immediate(only the lower 5 bits are used), and then copies the lower bits of y to the emptied upper bits of the shifted x.
 //
-// Asm: VRNDSCALEPD, CPU Feature: AVX512EVEX
-func (x Float64x8) MaskedTruncSuppressExceptionWithPrecision(imm uint8, y Mask64x8) Float64x8
+// Asm: VPSHRDD, CPU Feature: AVX512EVEX
+func (x Uint32x4) MaskedShiftAllRightAndFillUpperFrom(imm uint8, y Uint32x4, z Mask32x4) Uint32x4
 
-/* MaskedTruncWithPrecision */
+// ShiftAllRightAndFillUpperFrom shifts each element of x to the right by the number of bits specified by the
+// immediate(only the lower 5 bits are used), and then copies the lower bits of y to the emptied upper bits of the shifted x.
+//
+// Asm: VPSHRDD, CPU Feature: AVX512EVEX
+func (x Uint32x8) MaskedShiftAllRightAndFillUpperFrom(imm uint8, y Uint32x8, z Mask32x8) Uint32x8
 
-// TruncWithPrecision truncates elements with specified precision.
-// Const Immediate = 3.
+// ShiftAllRightAndFillUpperFrom shifts each element of x to the right by the number of bits specified by the
+// immediate(only the lower 5 bits are used), and then copies the lower bits of y to the emptied upper bits of the shifted x.
 //
-// Asm: VRNDSCALEPS, CPU Feature: AVX512EVEX
-func (x Float32x4) MaskedTruncWithPrecision(imm uint8, y Mask32x4) Float32x4
+// Asm: VPSHRDD, CPU Feature: AVX512EVEX
+func (x Uint32x16) MaskedShiftAllRightAndFillUpperFrom(imm uint8, y Uint32x16, z Mask32x16) Uint32x16
 
-// TruncWithPrecision truncates elements with specified precision.
-// Const Immediate = 3.
+// ShiftAllRightAndFillUpperFrom shifts each element of x to the right by the number of bits specified by the
+// immediate(only the lower 5 bits are used), and then copies the lower bits of y to the emptied upper bits of the shifted x.
 //
-// Asm: VRNDSCALEPS, CPU Feature: AVX512EVEX
-func (x Float32x8) MaskedTruncWithPrecision(imm uint8, y Mask32x8) Float32x8
+// Asm: VPSHRDQ, CPU Feature: AVX512EVEX
+func (x Uint64x2) MaskedShiftAllRightAndFillUpperFrom(imm uint8, y Uint64x2, z Mask64x2) Uint64x2
 
-// TruncWithPrecision truncates elements with specified precision.
-// Const Immediate = 3.
+// ShiftAllRightAndFillUpperFrom shifts each element of x to the right by the number of bits specified by the
+// immediate(only the lower 5 bits are used), and then copies the lower bits of y to the emptied upper bits of the shifted x.
 //
-// Asm: VRNDSCALEPS, CPU Feature: AVX512EVEX
-func (x Float32x16) MaskedTruncWithPrecision(imm uint8, y Mask32x16) Float32x16
+// Asm: VPSHRDQ, CPU Feature: AVX512EVEX
+func (x Uint64x4) MaskedShiftAllRightAndFillUpperFrom(imm uint8, y Uint64x4, z Mask64x4) Uint64x4
 
-// TruncWithPrecision truncates elements with specified precision.
-// Const Immediate = 3.
+// ShiftAllRightAndFillUpperFrom shifts each element of x to the right by the number of bits specified by the
+// immediate(only the lower 5 bits are used), and then copies the lower bits of y to the emptied upper bits of the shifted x.
 //
-// Asm: VRNDSCALEPD, CPU Feature: AVX512EVEX
-func (x Float64x2) MaskedTruncWithPrecision(imm uint8, y Mask64x2) Float64x2
+// Asm: VPSHRDQ, CPU Feature: AVX512EVEX
+func (x Uint64x8) MaskedShiftAllRightAndFillUpperFrom(imm uint8, y Uint64x8, z Mask64x8) Uint64x8
 
-// TruncWithPrecision truncates elements with specified precision.
-// Const Immediate = 3.
+/* MaskedShiftAllRightSignExtended */
+
+// ShiftAllRightSignExtended shifts each element to the right by the specified number of bits. Emptied upper bits are filled with the sign bit.
 //
-// Asm: VRNDSCALEPD, CPU Feature: AVX512EVEX
-func (x Float64x4) MaskedTruncWithPrecision(imm uint8, y Mask64x4) Float64x4
+// Asm: VPSRAQ, CPU Feature: AVX512EVEX
+func (x Int64x2) MaskedShiftAllRightSignExtended(y uint64, z Mask64x2) Int64x2
 
-// TruncWithPrecision truncates elements with specified precision.
-// Const Immediate = 3.
+// ShiftAllRightSignExtended shifts each element to the right by the specified number of bits. Emptied upper bits are filled with the sign bit.
 //
-// Asm: VRNDSCALEPD, CPU Feature: AVX512EVEX
-func (x Float64x8) MaskedTruncWithPrecision(imm uint8, y Mask64x8) Float64x8
+// Asm: VPSRAQ, CPU Feature: AVX512EVEX
+func (x Int64x4) MaskedShiftAllRightSignExtended(y uint64, z Mask64x4) Int64x4
 
-/* MaskedUnsignedSignedQuadDotProdAccumulate */
+// ShiftAllRightSignExtended shifts each element to the right by the specified number of bits. Emptied upper bits are filled with the sign bit.
+//
+// Asm: VPSRAQ, CPU Feature: AVX512EVEX
+func (x Int64x8) MaskedShiftAllRightSignExtended(y uint64, z Mask64x8) Int64x8
 
-// UnsignedSignedQuadDotProdAccumulate performs dot products on groups of 4 elements of y and z and accumulates the results to x.
+/* MaskedShiftLeft */
+
+// ShiftLeft shifts each element in x to the left by the number of bits specified in y's corresponding elements. Emptied lower bits are zeroed.
 //
-// Asm: VPDPBUSD, CPU Feature: AVX512EVEX
-func (x Int32x4) MaskedUnsignedSignedQuadDotProdAccumulate(y Uint8x16, z Int8x16, u Mask32x4) Int32x4
+// Asm: VPSLLVW, CPU Feature: AVX512EVEX
+func (x Int16x8) MaskedShiftLeft(y Int16x8, z Mask16x8) Int16x8
 
-// UnsignedSignedQuadDotProdAccumulate performs dot products on groups of 4 elements of y and z and accumulates the results to x.
+// ShiftLeft shifts each element in x to the left by the number of bits specified in y's corresponding elements. Emptied lower bits are zeroed.
 //
-// Asm: VPDPBUSD, CPU Feature: AVX512EVEX
-func (x Int32x8) MaskedUnsignedSignedQuadDotProdAccumulate(y Uint8x32, z Int8x32, u Mask32x8) Int32x8
+// Asm: VPSLLVW, CPU Feature: AVX512EVEX
+func (x Int16x16) MaskedShiftLeft(y Int16x16, z Mask16x16) Int16x16
 
-// UnsignedSignedQuadDotProdAccumulate performs dot products on groups of 4 elements of y and z and accumulates the results to x.
+// ShiftLeft shifts each element in x to the left by the number of bits specified in y's corresponding elements. Emptied lower bits are zeroed.
 //
-// Asm: VPDPBUSD, CPU Feature: AVX512EVEX
-func (x Int32x16) MaskedUnsignedSignedQuadDotProdAccumulate(y Uint8x64, z Int8x64, u Mask32x16) Int32x16
+// Asm: VPSLLVW, CPU Feature: AVX512EVEX
+func (x Int16x32) MaskedShiftLeft(y Int16x32, z Mask16x32) Int16x32
 
-// UnsignedSignedQuadDotProdAccumulate performs dot products on groups of 4 elements of y and z and accumulates the results to x.
+// ShiftLeft shifts each element in x to the left by the number of bits specified in y's corresponding elements. Emptied lower bits are zeroed.
 //
-// Asm: VPDPBUSD, CPU Feature: AVX512EVEX
-func (x Uint32x4) MaskedUnsignedSignedQuadDotProdAccumulate(y Uint8x16, z Int8x16, u Mask32x4) Uint32x4
+// Asm: VPSLLVD, CPU Feature: AVX512EVEX
+func (x Int32x4) MaskedShiftLeft(y Int32x4, z Mask32x4) Int32x4
 
-// UnsignedSignedQuadDotProdAccumulate performs dot products on groups of 4 elements of y and z and accumulates the results to x.
+// ShiftLeft shifts each element in x to the left by the number of bits specified in y's corresponding elements. Emptied lower bits are zeroed.
 //
-// Asm: VPDPBUSD, CPU Feature: AVX512EVEX
-func (x Uint32x8) MaskedUnsignedSignedQuadDotProdAccumulate(y Uint8x32, z Int8x32, u Mask32x8) Uint32x8
+// Asm: VPSLLVD, CPU Feature: AVX512EVEX
+func (x Int32x8) MaskedShiftLeft(y Int32x8, z Mask32x8) Int32x8
 
-// UnsignedSignedQuadDotProdAccumulate performs dot products on groups of 4 elements of y and z and accumulates the results to x.
+// ShiftLeft shifts each element in x to the left by the number of bits specified in y's corresponding elements. Emptied lower bits are zeroed.
 //
-// Asm: VPDPBUSD, CPU Feature: AVX512EVEX
-func (x Uint32x16) MaskedUnsignedSignedQuadDotProdAccumulate(y Uint8x64, z Int8x64, u Mask32x16) Uint32x16
+// Asm: VPSLLVD, CPU Feature: AVX512EVEX
+func (x Int32x16) MaskedShiftLeft(y Int32x16, z Mask32x16) Int32x16
 
-/* MaskedXor */
+// ShiftLeft shifts each element in x to the left by the number of bits specified in y's corresponding elements. Emptied lower bits are zeroed.
+//
+// Asm: VPSLLVQ, CPU Feature: AVX512EVEX
+func (x Int64x2) MaskedShiftLeft(y Int64x2, z Mask64x2) Int64x2
 
-// Xor performs a masked bitwise XOR operation between two vectors.
+// ShiftLeft shifts each element in x to the left by the number of bits specified in y's corresponding elements. Emptied lower bits are zeroed.
 //
-// Asm: VXORPS, CPU Feature: AVX512EVEX
-func (x Float32x4) MaskedXor(y Float32x4, z Mask32x4) Float32x4
+// Asm: VPSLLVQ, CPU Feature: AVX512EVEX
+func (x Int64x4) MaskedShiftLeft(y Int64x4, z Mask64x4) Int64x4
 
-// Xor performs a masked bitwise XOR operation between two vectors.
+// ShiftLeft shifts each element in x to the left by the number of bits specified in y's corresponding elements. Emptied lower bits are zeroed.
 //
-// Asm: VXORPS, CPU Feature: AVX512EVEX
-func (x Float32x8) MaskedXor(y Float32x8, z Mask32x8) Float32x8
+// Asm: VPSLLVQ, CPU Feature: AVX512EVEX
+func (x Int64x8) MaskedShiftLeft(y Int64x8, z Mask64x8) Int64x8
 
-// Xor performs a masked bitwise XOR operation between two vectors.
+// ShiftLeft shifts each element in x to the left by the number of bits specified in y's corresponding elements. Emptied lower bits are zeroed.
 //
-// Asm: VXORPS, CPU Feature: AVX512EVEX
-func (x Float32x16) MaskedXor(y Float32x16, z Mask32x16) Float32x16
+// Asm: VPSLLVW, CPU Feature: AVX512EVEX
+func (x Uint16x8) MaskedShiftLeft(y Uint16x8, z Mask16x8) Uint16x8
 
-// Xor performs a masked bitwise XOR operation between two vectors.
+// ShiftLeft shifts each element in x to the left by the number of bits specified in y's corresponding elements. Emptied lower bits are zeroed.
 //
-// Asm: VXORPD, CPU Feature: AVX512EVEX
-func (x Float64x2) MaskedXor(y Float64x2, z Mask64x2) Float64x2
+// Asm: VPSLLVW, CPU Feature: AVX512EVEX
+func (x Uint16x16) MaskedShiftLeft(y Uint16x16, z Mask16x16) Uint16x16
 
-// Xor performs a masked bitwise XOR operation between two vectors.
+// ShiftLeft shifts each element in x to the left by the number of bits specified in y's corresponding elements. Emptied lower bits are zeroed.
 //
-// Asm: VXORPD, CPU Feature: AVX512EVEX
-func (x Float64x4) MaskedXor(y Float64x4, z Mask64x4) Float64x4
+// Asm: VPSLLVW, CPU Feature: AVX512EVEX
+func (x Uint16x32) MaskedShiftLeft(y Uint16x32, z Mask16x32) Uint16x32
 
-// Xor performs a masked bitwise XOR operation between two vectors.
+// ShiftLeft shifts each element in x to the left by the number of bits specified in y's corresponding elements. Emptied lower bits are zeroed.
 //
-// Asm: VXORPD, CPU Feature: AVX512EVEX
-func (x Float64x8) MaskedXor(y Float64x8, z Mask64x8) Float64x8
+// Asm: VPSLLVD, CPU Feature: AVX512EVEX
+func (x Uint32x4) MaskedShiftLeft(y Uint32x4, z Mask32x4) Uint32x4
 
-// Xor performs a masked bitwise XOR operation between two vectors.
+// ShiftLeft shifts each element in x to the left by the number of bits specified in y's corresponding elements. Emptied lower bits are zeroed.
 //
-// Asm: VPXORD, CPU Feature: AVX512EVEX
-func (x Int32x4) MaskedXor(y Int32x4, z Mask32x4) Int32x4
+// Asm: VPSLLVD, CPU Feature: AVX512EVEX
+func (x Uint32x8) MaskedShiftLeft(y Uint32x8, z Mask32x8) Uint32x8
 
-// Xor performs a masked bitwise XOR operation between two vectors.
+// ShiftLeft shifts each element in x to the left by the number of bits specified in y's corresponding elements. Emptied lower bits are zeroed.
 //
-// Asm: VPXORD, CPU Feature: AVX512EVEX
-func (x Int32x8) MaskedXor(y Int32x8, z Mask32x8) Int32x8
+// Asm: VPSLLVD, CPU Feature: AVX512EVEX
+func (x Uint32x16) MaskedShiftLeft(y Uint32x16, z Mask32x16) Uint32x16
 
-// Xor performs a masked bitwise XOR operation between two vectors.
+// ShiftLeft shifts each element in x to the left by the number of bits specified in y's corresponding elements. Emptied lower bits are zeroed.
 //
-// Asm: VPXORD, CPU Feature: AVX512EVEX
-func (x Int32x16) MaskedXor(y Int32x16, z Mask32x16) Int32x16
+// Asm: VPSLLVQ, CPU Feature: AVX512EVEX
+func (x Uint64x2) MaskedShiftLeft(y Uint64x2, z Mask64x2) Uint64x2
 
-// Xor performs a masked bitwise XOR operation between two vectors.
+// ShiftLeft shifts each element in x to the left by the number of bits specified in y's corresponding elements. Emptied lower bits are zeroed.
 //
-// Asm: VPXORQ, CPU Feature: AVX512EVEX
-func (x Int64x2) MaskedXor(y Int64x2, z Mask64x2) Int64x2
+// Asm: VPSLLVQ, CPU Feature: AVX512EVEX
+func (x Uint64x4) MaskedShiftLeft(y Uint64x4, z Mask64x4) Uint64x4
 
-// Xor performs a masked bitwise XOR operation between two vectors.
+// ShiftLeft shifts each element in x to the left by the number of bits specified in y's corresponding elements. Emptied lower bits are zeroed.
 //
-// Asm: VPXORQ, CPU Feature: AVX512EVEX
-func (x Int64x4) MaskedXor(y Int64x4, z Mask64x4) Int64x4
+// Asm: VPSLLVQ, CPU Feature: AVX512EVEX
+func (x Uint64x8) MaskedShiftLeft(y Uint64x8, z Mask64x8) Uint64x8
 
-// Xor performs a masked bitwise XOR operation between two vectors.
+/* MaskedShiftLeftAndFillUpperFrom */
+
+// ShiftLeftAndFillUpperFrom shifts each element of x to the left by the number of bits specified by the
+// corresponding elements in y(only the lower 5 bits are used), and then copies the upper bits of z to the emptied lower bits of the shifted x.
 //
-// Asm: VPXORQ, CPU Feature: AVX512EVEX
-func (x Int64x8) MaskedXor(y Int64x8, z Mask64x8) Int64x8
+// Asm: VPSHLDVW, CPU Feature: AVX512EVEX
+func (x Int16x8) MaskedShiftLeftAndFillUpperFrom(y Int16x8, z Int16x8, u Mask16x8) Int16x8
 
-// Xor performs a masked bitwise XOR operation between two vectors.
+// ShiftLeftAndFillUpperFrom shifts each element of x to the left by the number of bits specified by the
+// corresponding elements in y(only the lower 5 bits are used), and then copies the upper bits of z to the emptied lower bits of the shifted x.
 //
-// Asm: VPXORD, CPU Feature: AVX512EVEX
-func (x Uint32x4) MaskedXor(y Uint32x4, z Mask32x4) Uint32x4
+// Asm: VPSHLDVW, CPU Feature: AVX512EVEX
+func (x Int16x16) MaskedShiftLeftAndFillUpperFrom(y Int16x16, z Int16x16, u Mask16x16) Int16x16
 
-// Xor performs a masked bitwise XOR operation between two vectors.
+// ShiftLeftAndFillUpperFrom shifts each element of x to the left by the number of bits specified by the
+// corresponding elements in y(only the lower 5 bits are used), and then copies the upper bits of z to the emptied lower bits of the shifted x.
 //
-// Asm: VPXORD, CPU Feature: AVX512EVEX
-func (x Uint32x8) MaskedXor(y Uint32x8, z Mask32x8) Uint32x8
+// Asm: VPSHLDVW, CPU Feature: AVX512EVEX
+func (x Int16x32) MaskedShiftLeftAndFillUpperFrom(y Int16x32, z Int16x32, u Mask16x32) Int16x32
 
-// Xor performs a masked bitwise XOR operation between two vectors.
+// ShiftLeftAndFillUpperFrom shifts each element of x to the left by the number of bits specified by the
+// corresponding elements in y(only the lower 5 bits are used), and then copies the upper bits of z to the emptied lower bits of the shifted x.
 //
-// Asm: VPXORD, CPU Feature: AVX512EVEX
-func (x Uint32x16) MaskedXor(y Uint32x16, z Mask32x16) Uint32x16
+// Asm: VPSHLDVD, CPU Feature: AVX512EVEX
+func (x Int32x4) MaskedShiftLeftAndFillUpperFrom(y Int32x4, z Int32x4, u Mask32x4) Int32x4
 
-// Xor performs a masked bitwise XOR operation between two vectors.
+// ShiftLeftAndFillUpperFrom shifts each element of x to the left by the number of bits specified by the
+// corresponding elements in y(only the lower 5 bits are used), and then copies the upper bits of z to the emptied lower bits of the shifted x.
 //
-// Asm: VPXORQ, CPU Feature: AVX512EVEX
-func (x Uint64x2) MaskedXor(y Uint64x2, z Mask64x2) Uint64x2
+// Asm: VPSHLDVD, CPU Feature: AVX512EVEX
+func (x Int32x8) MaskedShiftLeftAndFillUpperFrom(y Int32x8, z Int32x8, u Mask32x8) Int32x8
 
-// Xor performs a masked bitwise XOR operation between two vectors.
+// ShiftLeftAndFillUpperFrom shifts each element of x to the left by the number of bits specified by the
+// corresponding elements in y(only the lower 5 bits are used), and then copies the upper bits of z to the emptied lower bits of the shifted x.
 //
-// Asm: VPXORQ, CPU Feature: AVX512EVEX
-func (x Uint64x4) MaskedXor(y Uint64x4, z Mask64x4) Uint64x4
+// Asm: VPSHLDVD, CPU Feature: AVX512EVEX
+func (x Int32x16) MaskedShiftLeftAndFillUpperFrom(y Int32x16, z Int32x16, u Mask32x16) Int32x16
 
-// Xor performs a masked bitwise XOR operation between two vectors.
+// ShiftLeftAndFillUpperFrom shifts each element of x to the left by the number of bits specified by the
+// corresponding elements in y(only the lower 5 bits are used), and then copies the upper bits of z to the emptied lower bits of the shifted x.
 //
-// Asm: VPXORQ, CPU Feature: AVX512EVEX
-func (x Uint64x8) MaskedXor(y Uint64x8, z Mask64x8) Uint64x8
+// Asm: VPSHLDVQ, CPU Feature: AVX512EVEX
+func (x Int64x2) MaskedShiftLeftAndFillUpperFrom(y Int64x2, z Int64x2, u Mask64x2) Int64x2
 
-/* Max */
+// ShiftLeftAndFillUpperFrom shifts each element of x to the left by the number of bits specified by the
+// corresponding elements in y(only the lower 5 bits are used), and then copies the upper bits of z to the emptied lower bits of the shifted x.
+//
+// Asm: VPSHLDVQ, CPU Feature: AVX512EVEX
+func (x Int64x4) MaskedShiftLeftAndFillUpperFrom(y Int64x4, z Int64x4, u Mask64x4) Int64x4
 
-// Max computes the maximum of corresponding elements.
+// ShiftLeftAndFillUpperFrom shifts each element of x to the left by the number of bits specified by the
+// corresponding elements in y(only the lower 5 bits are used), and then copies the upper bits of z to the emptied lower bits of the shifted x.
 //
-// Asm: VMAXPS, CPU Feature: AVX
-func (x Float32x4) Max(y Float32x4) Float32x4
+// Asm: VPSHLDVQ, CPU Feature: AVX512EVEX
+func (x Int64x8) MaskedShiftLeftAndFillUpperFrom(y Int64x8, z Int64x8, u Mask64x8) Int64x8
 
-// Max computes the maximum of corresponding elements.
+// ShiftLeftAndFillUpperFrom shifts each element of x to the left by the number of bits specified by the
+// corresponding elements in y(only the lower 5 bits are used), and then copies the upper bits of z to the emptied lower bits of the shifted x.
 //
-// Asm: VMAXPS, CPU Feature: AVX
-func (x Float32x8) Max(y Float32x8) Float32x8
+// Asm: VPSHLDVW, CPU Feature: AVX512EVEX
+func (x Uint16x8) MaskedShiftLeftAndFillUpperFrom(y Uint16x8, z Uint16x8, u Mask16x8) Uint16x8
 
-// Max computes the maximum of corresponding elements.
+// ShiftLeftAndFillUpperFrom shifts each element of x to the left by the number of bits specified by the
+// corresponding elements in y(only the lower 5 bits are used), and then copies the upper bits of z to the emptied lower bits of the shifted x.
 //
-// Asm: VMAXPS, CPU Feature: AVX512EVEX
-func (x Float32x16) Max(y Float32x16) Float32x16
+// Asm: VPSHLDVW, CPU Feature: AVX512EVEX
+func (x Uint16x16) MaskedShiftLeftAndFillUpperFrom(y Uint16x16, z Uint16x16, u Mask16x16) Uint16x16
 
-// Max computes the maximum of corresponding elements.
+// ShiftLeftAndFillUpperFrom shifts each element of x to the left by the number of bits specified by the
+// corresponding elements in y(only the lower 5 bits are used), and then copies the upper bits of z to the emptied lower bits of the shifted x.
 //
-// Asm: VMAXPD, CPU Feature: AVX
-func (x Float64x2) Max(y Float64x2) Float64x2
+// Asm: VPSHLDVW, CPU Feature: AVX512EVEX
+func (x Uint16x32) MaskedShiftLeftAndFillUpperFrom(y Uint16x32, z Uint16x32, u Mask16x32) Uint16x32
 
-// Max computes the maximum of corresponding elements.
+// ShiftLeftAndFillUpperFrom shifts each element of x to the left by the number of bits specified by the
+// corresponding elements in y(only the lower 5 bits are used), and then copies the upper bits of z to the emptied lower bits of the shifted x.
 //
-// Asm: VMAXPD, CPU Feature: AVX
-func (x Float64x4) Max(y Float64x4) Float64x4
+// Asm: VPSHLDVD, CPU Feature: AVX512EVEX
+func (x Uint32x4) MaskedShiftLeftAndFillUpperFrom(y Uint32x4, z Uint32x4, u Mask32x4) Uint32x4
 
-// Max computes the maximum of corresponding elements.
+// ShiftLeftAndFillUpperFrom shifts each element of x to the left by the number of bits specified by the
+// corresponding elements in y(only the lower 5 bits are used), and then copies the upper bits of z to the emptied lower bits of the shifted x.
 //
-// Asm: VMAXPD, CPU Feature: AVX512EVEX
-func (x Float64x8) Max(y Float64x8) Float64x8
+// Asm: VPSHLDVD, CPU Feature: AVX512EVEX
+func (x Uint32x8) MaskedShiftLeftAndFillUpperFrom(y Uint32x8, z Uint32x8, u Mask32x8) Uint32x8
 
-// Max computes the maximum of corresponding elements.
+// ShiftLeftAndFillUpperFrom shifts each element of x to the left by the number of bits specified by the
+// corresponding elements in y(only the lower 5 bits are used), and then copies the upper bits of z to the emptied lower bits of the shifted x.
 //
-// Asm: VPMAXSB, CPU Feature: AVX
-func (x Int8x16) Max(y Int8x16) Int8x16
+// Asm: VPSHLDVD, CPU Feature: AVX512EVEX
+func (x Uint32x16) MaskedShiftLeftAndFillUpperFrom(y Uint32x16, z Uint32x16, u Mask32x16) Uint32x16
 
-// Max computes the maximum of corresponding elements.
+// ShiftLeftAndFillUpperFrom shifts each element of x to the left by the number of bits specified by the
+// corresponding elements in y(only the lower 5 bits are used), and then copies the upper bits of z to the emptied lower bits of the shifted x.
 //
-// Asm: VPMAXSB, CPU Feature: AVX2
-func (x Int8x32) Max(y Int8x32) Int8x32
+// Asm: VPSHLDVQ, CPU Feature: AVX512EVEX
+func (x Uint64x2) MaskedShiftLeftAndFillUpperFrom(y Uint64x2, z Uint64x2, u Mask64x2) Uint64x2
 
-// Max computes the maximum of corresponding elements.
+// ShiftLeftAndFillUpperFrom shifts each element of x to the left by the number of bits specified by the
+// corresponding elements in y(only the lower 5 bits are used), and then copies the upper bits of z to the emptied lower bits of the shifted x.
 //
-// Asm: VPMAXSB, CPU Feature: AVX512EVEX
-func (x Int8x64) Max(y Int8x64) Int8x64
+// Asm: VPSHLDVQ, CPU Feature: AVX512EVEX
+func (x Uint64x4) MaskedShiftLeftAndFillUpperFrom(y Uint64x4, z Uint64x4, u Mask64x4) Uint64x4
 
-// Max computes the maximum of corresponding elements.
+// ShiftLeftAndFillUpperFrom shifts each element of x to the left by the number of bits specified by the
+// corresponding elements in y(only the lower 5 bits are used), and then copies the upper bits of z to the emptied lower bits of the shifted x.
 //
-// Asm: VPMAXSW, CPU Feature: AVX
-func (x Int16x8) Max(y Int16x8) Int16x8
+// Asm: VPSHLDVQ, CPU Feature: AVX512EVEX
+func (x Uint64x8) MaskedShiftLeftAndFillUpperFrom(y Uint64x8, z Uint64x8, u Mask64x8) Uint64x8
 
-// Max computes the maximum of corresponding elements.
+/* MaskedShiftRight */
+
+// ShiftRight shifts each element in x to the right by the number of bits specified in y's corresponding elements. Emptied upper bits are zeroed.
 //
-// Asm: VPMAXSW, CPU Feature: AVX2
-func (x Int16x16) Max(y Int16x16) Int16x16
+// Asm: VPSRLVW, CPU Feature: AVX512EVEX
+func (x Int16x8) MaskedShiftRight(y Int16x8, z Mask16x8) Int16x8
 
-// Max computes the maximum of corresponding elements.
+// ShiftRight shifts each element in x to the right by the number of bits specified in y's corresponding elements. Emptied upper bits are zeroed.
 //
-// Asm: VPMAXSW, CPU Feature: AVX512EVEX
-func (x Int16x32) Max(y Int16x32) Int16x32
+// Asm: VPSRLVW, CPU Feature: AVX512EVEX
+func (x Int16x16) MaskedShiftRight(y Int16x16, z Mask16x16) Int16x16
 
-// Max computes the maximum of corresponding elements.
+// ShiftRight shifts each element in x to the right by the number of bits specified in y's corresponding elements. Emptied upper bits are zeroed.
 //
-// Asm: VPMAXSD, CPU Feature: AVX
-func (x Int32x4) Max(y Int32x4) Int32x4
+// Asm: VPSRLVW, CPU Feature: AVX512EVEX
+func (x Int16x32) MaskedShiftRight(y Int16x32, z Mask16x32) Int16x32
 
-// Max computes the maximum of corresponding elements.
+// ShiftRight shifts each element in x to the right by the number of bits specified in y's corresponding elements. Emptied upper bits are zeroed.
 //
-// Asm: VPMAXSD, CPU Feature: AVX2
-func (x Int32x8) Max(y Int32x8) Int32x8
+// Asm: VPSRLVD, CPU Feature: AVX512EVEX
+func (x Int32x4) MaskedShiftRight(y Int32x4, z Mask32x4) Int32x4
 
-// Max computes the maximum of corresponding elements.
+// ShiftRight shifts each element in x to the right by the number of bits specified in y's corresponding elements. Emptied upper bits are zeroed.
 //
-// Asm: VPMAXSD, CPU Feature: AVX512EVEX
-func (x Int32x16) Max(y Int32x16) Int32x16
+// Asm: VPSRLVD, CPU Feature: AVX512EVEX
+func (x Int32x8) MaskedShiftRight(y Int32x8, z Mask32x8) Int32x8
 
-// Max computes the maximum of corresponding elements.
+// ShiftRight shifts each element in x to the right by the number of bits specified in y's corresponding elements. Emptied upper bits are zeroed.
 //
-// Asm: VPMAXSQ, CPU Feature: AVX512EVEX
-func (x Int64x2) Max(y Int64x2) Int64x2
+// Asm: VPSRLVD, CPU Feature: AVX512EVEX
+func (x Int32x16) MaskedShiftRight(y Int32x16, z Mask32x16) Int32x16
 
-// Max computes the maximum of corresponding elements.
+// ShiftRight shifts each element in x to the right by the number of bits specified in y's corresponding elements. Emptied upper bits are zeroed.
 //
-// Asm: VPMAXSQ, CPU Feature: AVX512EVEX
-func (x Int64x4) Max(y Int64x4) Int64x4
+// Asm: VPSRLVQ, CPU Feature: AVX512EVEX
+func (x Int64x2) MaskedShiftRight(y Int64x2, z Mask64x2) Int64x2
 
-// Max computes the maximum of corresponding elements.
+// ShiftRight shifts each element in x to the right by the number of bits specified in y's corresponding elements. Emptied upper bits are zeroed.
 //
-// Asm: VPMAXSQ, CPU Feature: AVX512EVEX
-func (x Int64x8) Max(y Int64x8) Int64x8
+// Asm: VPSRLVQ, CPU Feature: AVX512EVEX
+func (x Int64x4) MaskedShiftRight(y Int64x4, z Mask64x4) Int64x4
 
-// Max computes the maximum of corresponding elements.
+// ShiftRight shifts each element in x to the right by the number of bits specified in y's corresponding elements. Emptied upper bits are zeroed.
 //
-// Asm: VPMAXUB, CPU Feature: AVX
-func (x Uint8x16) Max(y Uint8x16) Uint8x16
+// Asm: VPSRLVQ, CPU Feature: AVX512EVEX
+func (x Int64x8) MaskedShiftRight(y Int64x8, z Mask64x8) Int64x8
 
-// Max computes the maximum of corresponding elements.
+// ShiftRight shifts each element in x to the right by the number of bits specified in y's corresponding elements. Emptied upper bits are zeroed.
 //
-// Asm: VPMAXUB, CPU Feature: AVX2
-func (x Uint8x32) Max(y Uint8x32) Uint8x32
+// Asm: VPSRLVW, CPU Feature: AVX512EVEX
+func (x Uint16x8) MaskedShiftRight(y Uint16x8, z Mask16x8) Uint16x8
 
-// Max computes the maximum of corresponding elements.
+// ShiftRight shifts each element in x to the right by the number of bits specified in y's corresponding elements. Emptied upper bits are zeroed.
 //
-// Asm: VPMAXUB, CPU Feature: AVX512EVEX
-func (x Uint8x64) Max(y Uint8x64) Uint8x64
+// Asm: VPSRLVW, CPU Feature: AVX512EVEX
+func (x Uint16x16) MaskedShiftRight(y Uint16x16, z Mask16x16) Uint16x16
 
-// Max computes the maximum of corresponding elements.
+// ShiftRight shifts each element in x to the right by the number of bits specified in y's corresponding elements. Emptied upper bits are zeroed.
 //
-// Asm: VPMAXUW, CPU Feature: AVX
-func (x Uint16x8) Max(y Uint16x8) Uint16x8
+// Asm: VPSRLVW, CPU Feature: AVX512EVEX
+func (x Uint16x32) MaskedShiftRight(y Uint16x32, z Mask16x32) Uint16x32
 
-// Max computes the maximum of corresponding elements.
+// ShiftRight shifts each element in x to the right by the number of bits specified in y's corresponding elements. Emptied upper bits are zeroed.
 //
-// Asm: VPMAXUW, CPU Feature: AVX2
-func (x Uint16x16) Max(y Uint16x16) Uint16x16
+// Asm: VPSRLVD, CPU Feature: AVX512EVEX
+func (x Uint32x4) MaskedShiftRight(y Uint32x4, z Mask32x4) Uint32x4
 
-// Max computes the maximum of corresponding elements.
+// ShiftRight shifts each element in x to the right by the number of bits specified in y's corresponding elements. Emptied upper bits are zeroed.
 //
-// Asm: VPMAXUW, CPU Feature: AVX512EVEX
-func (x Uint16x32) Max(y Uint16x32) Uint16x32
+// Asm: VPSRLVD, CPU Feature: AVX512EVEX
+func (x Uint32x8) MaskedShiftRight(y Uint32x8, z Mask32x8) Uint32x8
 
-// Max computes the maximum of corresponding elements.
+// ShiftRight shifts each element in x to the right by the number of bits specified in y's corresponding elements. Emptied upper bits are zeroed.
 //
-// Asm: VPMAXUD, CPU Feature: AVX
-func (x Uint32x4) Max(y Uint32x4) Uint32x4
+// Asm: VPSRLVD, CPU Feature: AVX512EVEX
+func (x Uint32x16) MaskedShiftRight(y Uint32x16, z Mask32x16) Uint32x16
 
-// Max computes the maximum of corresponding elements.
+// ShiftRight shifts each element in x to the right by the number of bits specified in y's corresponding elements. Emptied upper bits are zeroed.
 //
-// Asm: VPMAXUD, CPU Feature: AVX2
-func (x Uint32x8) Max(y Uint32x8) Uint32x8
+// Asm: VPSRLVQ, CPU Feature: AVX512EVEX
+func (x Uint64x2) MaskedShiftRight(y Uint64x2, z Mask64x2) Uint64x2
 
-// Max computes the maximum of corresponding elements.
+// ShiftRight shifts each element in x to the right by the number of bits specified in y's corresponding elements. Emptied upper bits are zeroed.
 //
-// Asm: VPMAXUD, CPU Feature: AVX512EVEX
-func (x Uint32x16) Max(y Uint32x16) Uint32x16
+// Asm: VPSRLVQ, CPU Feature: AVX512EVEX
+func (x Uint64x4) MaskedShiftRight(y Uint64x4, z Mask64x4) Uint64x4
 
-// Max computes the maximum of corresponding elements.
+// ShiftRight shifts each element in x to the right by the number of bits specified in y's corresponding elements. Emptied upper bits are zeroed.
 //
-// Asm: VPMAXUQ, CPU Feature: AVX512EVEX
-func (x Uint64x2) Max(y Uint64x2) Uint64x2
+// Asm: VPSRLVQ, CPU Feature: AVX512EVEX
+func (x Uint64x8) MaskedShiftRight(y Uint64x8, z Mask64x8) Uint64x8
 
-// Max computes the maximum of corresponding elements.
+/* MaskedShiftRightAndFillUpperFrom */
+
+// ShiftRightAndFillUpperFrom shifts each element of x to the right by the number of bits specified by the
+// corresponding elements in y(only the lower 5 bits are used), and then copies the lower bits of z to the emptied upper bits of the shifted x.
 //
-// Asm: VPMAXUQ, CPU Feature: AVX512EVEX
-func (x Uint64x4) Max(y Uint64x4) Uint64x4
+// Asm: VPSHRDVW, CPU Feature: AVX512EVEX
+func (x Int16x8) MaskedShiftRightAndFillUpperFrom(y Int16x8, z Int16x8, u Mask16x8) Int16x8
 
-// Max computes the maximum of corresponding elements.
+// ShiftRightAndFillUpperFrom shifts each element of x to the right by the number of bits specified by the
+// corresponding elements in y(only the lower 5 bits are used), and then copies the lower bits of z to the emptied upper bits of the shifted x.
 //
-// Asm: VPMAXUQ, CPU Feature: AVX512EVEX
-func (x Uint64x8) Max(y Uint64x8) Uint64x8
+// Asm: VPSHRDVW, CPU Feature: AVX512EVEX
+func (x Int16x16) MaskedShiftRightAndFillUpperFrom(y Int16x16, z Int16x16, u Mask16x16) Int16x16
 
-/* Min */
+// ShiftRightAndFillUpperFrom shifts each element of x to the right by the number of bits specified by the
+// corresponding elements in y(only the lower 5 bits are used), and then copies the lower bits of z to the emptied upper bits of the shifted x.
+//
+// Asm: VPSHRDVW, CPU Feature: AVX512EVEX
+func (x Int16x32) MaskedShiftRightAndFillUpperFrom(y Int16x32, z Int16x32, u Mask16x32) Int16x32
 
-// Min computes the minimum of corresponding elements.
+// ShiftRightAndFillUpperFrom shifts each element of x to the right by the number of bits specified by the
+// corresponding elements in y(only the lower 5 bits are used), and then copies the lower bits of z to the emptied upper bits of the shifted x.
 //
-// Asm: VMINPS, CPU Feature: AVX
-func (x Float32x4) Min(y Float32x4) Float32x4
+// Asm: VPSHRDVD, CPU Feature: AVX512EVEX
+func (x Int32x4) MaskedShiftRightAndFillUpperFrom(y Int32x4, z Int32x4, u Mask32x4) Int32x4
 
-// Min computes the minimum of corresponding elements.
+// ShiftRightAndFillUpperFrom shifts each element of x to the right by the number of bits specified by the
+// corresponding elements in y(only the lower 5 bits are used), and then copies the lower bits of z to the emptied upper bits of the shifted x.
 //
-// Asm: VMINPS, CPU Feature: AVX
-func (x Float32x8) Min(y Float32x8) Float32x8
+// Asm: VPSHRDVD, CPU Feature: AVX512EVEX
+func (x Int32x8) MaskedShiftRightAndFillUpperFrom(y Int32x8, z Int32x8, u Mask32x8) Int32x8
 
-// Min computes the minimum of corresponding elements.
+// ShiftRightAndFillUpperFrom shifts each element of x to the right by the number of bits specified by the
+// corresponding elements in y(only the lower 5 bits are used), and then copies the lower bits of z to the emptied upper bits of the shifted x.
 //
-// Asm: VMINPS, CPU Feature: AVX512EVEX
-func (x Float32x16) Min(y Float32x16) Float32x16
+// Asm: VPSHRDVD, CPU Feature: AVX512EVEX
+func (x Int32x16) MaskedShiftRightAndFillUpperFrom(y Int32x16, z Int32x16, u Mask32x16) Int32x16
 
-// Min computes the minimum of corresponding elements.
+// ShiftRightAndFillUpperFrom shifts each element of x to the right by the number of bits specified by the
+// corresponding elements in y(only the lower 5 bits are used), and then copies the lower bits of z to the emptied upper bits of the shifted x.
 //
-// Asm: VMINPD, CPU Feature: AVX
-func (x Float64x2) Min(y Float64x2) Float64x2
+// Asm: VPSHRDVQ, CPU Feature: AVX512EVEX
+func (x Int64x2) MaskedShiftRightAndFillUpperFrom(y Int64x2, z Int64x2, u Mask64x2) Int64x2
 
-// Min computes the minimum of corresponding elements.
+// ShiftRightAndFillUpperFrom shifts each element of x to the right by the number of bits specified by the
+// corresponding elements in y(only the lower 5 bits are used), and then copies the lower bits of z to the emptied upper bits of the shifted x.
 //
-// Asm: VMINPD, CPU Feature: AVX
-func (x Float64x4) Min(y Float64x4) Float64x4
+// Asm: VPSHRDVQ, CPU Feature: AVX512EVEX
+func (x Int64x4) MaskedShiftRightAndFillUpperFrom(y Int64x4, z Int64x4, u Mask64x4) Int64x4
 
-// Min computes the minimum of corresponding elements.
+// ShiftRightAndFillUpperFrom shifts each element of x to the right by the number of bits specified by the
+// corresponding elements in y(only the lower 5 bits are used), and then copies the lower bits of z to the emptied upper bits of the shifted x.
 //
-// Asm: VMINPD, CPU Feature: AVX512EVEX
-func (x Float64x8) Min(y Float64x8) Float64x8
+// Asm: VPSHRDVQ, CPU Feature: AVX512EVEX
+func (x Int64x8) MaskedShiftRightAndFillUpperFrom(y Int64x8, z Int64x8, u Mask64x8) Int64x8
 
-// Min computes the minimum of corresponding elements.
+// ShiftRightAndFillUpperFrom shifts each element of x to the right by the number of bits specified by the
+// corresponding elements in y(only the lower 5 bits are used), and then copies the lower bits of z to the emptied upper bits of the shifted x.
 //
-// Asm: VPMINSB, CPU Feature: AVX
-func (x Int8x16) Min(y Int8x16) Int8x16
+// Asm: VPSHRDVW, CPU Feature: AVX512EVEX
+func (x Uint16x8) MaskedShiftRightAndFillUpperFrom(y Uint16x8, z Uint16x8, u Mask16x8) Uint16x8
 
-// Min computes the minimum of corresponding elements.
+// ShiftRightAndFillUpperFrom shifts each element of x to the right by the number of bits specified by the
+// corresponding elements in y(only the lower 5 bits are used), and then copies the lower bits of z to the emptied upper bits of the shifted x.
 //
-// Asm: VPMINSB, CPU Feature: AVX2
-func (x Int8x32) Min(y Int8x32) Int8x32
+// Asm: VPSHRDVW, CPU Feature: AVX512EVEX
+func (x Uint16x16) MaskedShiftRightAndFillUpperFrom(y Uint16x16, z Uint16x16, u Mask16x16) Uint16x16
 
-// Min computes the minimum of corresponding elements.
+// ShiftRightAndFillUpperFrom shifts each element of x to the right by the number of bits specified by the
+// corresponding elements in y(only the lower 5 bits are used), and then copies the lower bits of z to the emptied upper bits of the shifted x.
 //
-// Asm: VPMINSB, CPU Feature: AVX512EVEX
-func (x Int8x64) Min(y Int8x64) Int8x64
+// Asm: VPSHRDVW, CPU Feature: AVX512EVEX
+func (x Uint16x32) MaskedShiftRightAndFillUpperFrom(y Uint16x32, z Uint16x32, u Mask16x32) Uint16x32
 
-// Min computes the minimum of corresponding elements.
+// ShiftRightAndFillUpperFrom shifts each element of x to the right by the number of bits specified by the
+// corresponding elements in y(only the lower 5 bits are used), and then copies the lower bits of z to the emptied upper bits of the shifted x.
 //
-// Asm: VPMINSW, CPU Feature: AVX
-func (x Int16x8) Min(y Int16x8) Int16x8
+// Asm: VPSHRDVD, CPU Feature: AVX512EVEX
+func (x Uint32x4) MaskedShiftRightAndFillUpperFrom(y Uint32x4, z Uint32x4, u Mask32x4) Uint32x4
 
-// Min computes the minimum of corresponding elements.
+// ShiftRightAndFillUpperFrom shifts each element of x to the right by the number of bits specified by the
+// corresponding elements in y(only the lower 5 bits are used), and then copies the lower bits of z to the emptied upper bits of the shifted x.
 //
-// Asm: VPMINSW, CPU Feature: AVX2
-func (x Int16x16) Min(y Int16x16) Int16x16
+// Asm: VPSHRDVD, CPU Feature: AVX512EVEX
+func (x Uint32x8) MaskedShiftRightAndFillUpperFrom(y Uint32x8, z Uint32x8, u Mask32x8) Uint32x8
 
-// Min computes the minimum of corresponding elements.
+// ShiftRightAndFillUpperFrom shifts each element of x to the right by the number of bits specified by the
+// corresponding elements in y(only the lower 5 bits are used), and then copies the lower bits of z to the emptied upper bits of the shifted x.
 //
-// Asm: VPMINSW, CPU Feature: AVX512EVEX
-func (x Int16x32) Min(y Int16x32) Int16x32
+// Asm: VPSHRDVD, CPU Feature: AVX512EVEX
+func (x Uint32x16) MaskedShiftRightAndFillUpperFrom(y Uint32x16, z Uint32x16, u Mask32x16) Uint32x16
 
-// Min computes the minimum of corresponding elements.
+// ShiftRightAndFillUpperFrom shifts each element of x to the right by the number of bits specified by the
+// corresponding elements in y(only the lower 5 bits are used), and then copies the lower bits of z to the emptied upper bits of the shifted x.
 //
-// Asm: VPMINSD, CPU Feature: AVX
-func (x Int32x4) Min(y Int32x4) Int32x4
+// Asm: VPSHRDVQ, CPU Feature: AVX512EVEX
+func (x Uint64x2) MaskedShiftRightAndFillUpperFrom(y Uint64x2, z Uint64x2, u Mask64x2) Uint64x2
 
-// Min computes the minimum of corresponding elements.
+// ShiftRightAndFillUpperFrom shifts each element of x to the right by the number of bits specified by the
+// corresponding elements in y(only the lower 5 bits are used), and then copies the lower bits of z to the emptied upper bits of the shifted x.
 //
-// Asm: VPMINSD, CPU Feature: AVX2
-func (x Int32x8) Min(y Int32x8) Int32x8
+// Asm: VPSHRDVQ, CPU Feature: AVX512EVEX
+func (x Uint64x4) MaskedShiftRightAndFillUpperFrom(y Uint64x4, z Uint64x4, u Mask64x4) Uint64x4
 
-// Min computes the minimum of corresponding elements.
+// ShiftRightAndFillUpperFrom shifts each element of x to the right by the number of bits specified by the
+// corresponding elements in y(only the lower 5 bits are used), and then copies the lower bits of z to the emptied upper bits of the shifted x.
 //
-// Asm: VPMINSD, CPU Feature: AVX512EVEX
-func (x Int32x16) Min(y Int32x16) Int32x16
+// Asm: VPSHRDVQ, CPU Feature: AVX512EVEX
+func (x Uint64x8) MaskedShiftRightAndFillUpperFrom(y Uint64x8, z Uint64x8, u Mask64x8) Uint64x8
 
-// Min computes the minimum of corresponding elements.
+/* MaskedShiftRightSignExtended */
+
+// ShiftRightSignExtended shifts each element in x to the right by the number of bits specified in y's corresponding elements. Emptied upper bits are filled with the sign bit.
 //
-// Asm: VPMINSQ, CPU Feature: AVX512EVEX
-func (x Int64x2) Min(y Int64x2) Int64x2
+// Asm: VPSRAVW, CPU Feature: AVX512EVEX
+func (x Int16x8) MaskedShiftRightSignExtended(y Int16x8, z Mask16x8) Int16x8
 
-// Min computes the minimum of corresponding elements.
+// ShiftRightSignExtended shifts each element in x to the right by the number of bits specified in y's corresponding elements. Emptied upper bits are filled with the sign bit.
 //
-// Asm: VPMINSQ, CPU Feature: AVX512EVEX
-func (x Int64x4) Min(y Int64x4) Int64x4
+// Asm: VPSRAVW, CPU Feature: AVX512EVEX
+func (x Int16x16) MaskedShiftRightSignExtended(y Int16x16, z Mask16x16) Int16x16
 
-// Min computes the minimum of corresponding elements.
+// ShiftRightSignExtended shifts each element in x to the right by the number of bits specified in y's corresponding elements. Emptied upper bits are filled with the sign bit.
 //
-// Asm: VPMINSQ, CPU Feature: AVX512EVEX
-func (x Int64x8) Min(y Int64x8) Int64x8
+// Asm: VPSRAVW, CPU Feature: AVX512EVEX
+func (x Int16x32) MaskedShiftRightSignExtended(y Int16x32, z Mask16x32) Int16x32
 
-// Min computes the minimum of corresponding elements.
+// ShiftRightSignExtended shifts each element in x to the right by the number of bits specified in y's corresponding elements. Emptied upper bits are filled with the sign bit.
 //
-// Asm: VPMINUB, CPU Feature: AVX
-func (x Uint8x16) Min(y Uint8x16) Uint8x16
+// Asm: VPSRAVD, CPU Feature: AVX512EVEX
+func (x Int32x4) MaskedShiftRightSignExtended(y Int32x4, z Mask32x4) Int32x4
 
-// Min computes the minimum of corresponding elements.
+// ShiftRightSignExtended shifts each element in x to the right by the number of bits specified in y's corresponding elements. Emptied upper bits are filled with the sign bit.
 //
-// Asm: VPMINUB, CPU Feature: AVX2
-func (x Uint8x32) Min(y Uint8x32) Uint8x32
+// Asm: VPSRAVD, CPU Feature: AVX512EVEX
+func (x Int32x8) MaskedShiftRightSignExtended(y Int32x8, z Mask32x8) Int32x8
 
-// Min computes the minimum of corresponding elements.
+// ShiftRightSignExtended shifts each element in x to the right by the number of bits specified in y's corresponding elements. Emptied upper bits are filled with the sign bit.
 //
-// Asm: VPMINUB, CPU Feature: AVX512EVEX
-func (x Uint8x64) Min(y Uint8x64) Uint8x64
+// Asm: VPSRAVD, CPU Feature: AVX512EVEX
+func (x Int32x16) MaskedShiftRightSignExtended(y Int32x16, z Mask32x16) Int32x16
 
-// Min computes the minimum of corresponding elements.
+// ShiftRightSignExtended shifts each element in x to the right by the number of bits specified in y's corresponding elements. Emptied upper bits are filled with the sign bit.
 //
-// Asm: VPMINUW, CPU Feature: AVX
-func (x Uint16x8) Min(y Uint16x8) Uint16x8
+// Asm: VPSRAVQ, CPU Feature: AVX512EVEX
+func (x Int64x2) MaskedShiftRightSignExtended(y Int64x2, z Mask64x2) Int64x2
 
-// Min computes the minimum of corresponding elements.
+// ShiftRightSignExtended shifts each element in x to the right by the number of bits specified in y's corresponding elements. Emptied upper bits are filled with the sign bit.
 //
-// Asm: VPMINUW, CPU Feature: AVX2
-func (x Uint16x16) Min(y Uint16x16) Uint16x16
+// Asm: VPSRAVQ, CPU Feature: AVX512EVEX
+func (x Int64x4) MaskedShiftRightSignExtended(y Int64x4, z Mask64x4) Int64x4
 
-// Min computes the minimum of corresponding elements.
+// ShiftRightSignExtended shifts each element in x to the right by the number of bits specified in y's corresponding elements. Emptied upper bits are filled with the sign bit.
 //
-// Asm: VPMINUW, CPU Feature: AVX512EVEX
-func (x Uint16x32) Min(y Uint16x32) Uint16x32
+// Asm: VPSRAVQ, CPU Feature: AVX512EVEX
+func (x Int64x8) MaskedShiftRightSignExtended(y Int64x8, z Mask64x8) Int64x8
 
-// Min computes the minimum of corresponding elements.
+// ShiftRightSignExtended shifts each element in x to the right by the number of bits specified in y's corresponding elements. Emptied upper bits are filled with the sign bit.
 //
-// Asm: VPMINUD, CPU Feature: AVX
-func (x Uint32x4) Min(y Uint32x4) Uint32x4
+// Asm: VPSRAVW, CPU Feature: AVX512EVEX
+func (x Uint16x8) MaskedShiftRightSignExtended(y Uint16x8, z Mask16x8) Uint16x8
 
-// Min computes the minimum of corresponding elements.
+// ShiftRightSignExtended shifts each element in x to the right by the number of bits specified in y's corresponding elements. Emptied upper bits are filled with the sign bit.
 //
-// Asm: VPMINUD, CPU Feature: AVX2
-func (x Uint32x8) Min(y Uint32x8) Uint32x8
+// Asm: VPSRAVW, CPU Feature: AVX512EVEX
+func (x Uint16x16) MaskedShiftRightSignExtended(y Uint16x16, z Mask16x16) Uint16x16
 
-// Min computes the minimum of corresponding elements.
+// ShiftRightSignExtended shifts each element in x to the right by the number of bits specified in y's corresponding elements. Emptied upper bits are filled with the sign bit.
 //
-// Asm: VPMINUD, CPU Feature: AVX512EVEX
-func (x Uint32x16) Min(y Uint32x16) Uint32x16
+// Asm: VPSRAVW, CPU Feature: AVX512EVEX
+func (x Uint16x32) MaskedShiftRightSignExtended(y Uint16x32, z Mask16x32) Uint16x32
 
-// Min computes the minimum of corresponding elements.
+// ShiftRightSignExtended shifts each element in x to the right by the number of bits specified in y's corresponding elements. Emptied upper bits are filled with the sign bit.
 //
-// Asm: VPMINUQ, CPU Feature: AVX512EVEX
-func (x Uint64x2) Min(y Uint64x2) Uint64x2
+// Asm: VPSRAVD, CPU Feature: AVX512EVEX
+func (x Uint32x4) MaskedShiftRightSignExtended(y Uint32x4, z Mask32x4) Uint32x4
 
-// Min computes the minimum of corresponding elements.
+// ShiftRightSignExtended shifts each element in x to the right by the number of bits specified in y's corresponding elements. Emptied upper bits are filled with the sign bit.
 //
-// Asm: VPMINUQ, CPU Feature: AVX512EVEX
-func (x Uint64x4) Min(y Uint64x4) Uint64x4
+// Asm: VPSRAVD, CPU Feature: AVX512EVEX
+func (x Uint32x8) MaskedShiftRightSignExtended(y Uint32x8, z Mask32x8) Uint32x8
 
-// Min computes the minimum of corresponding elements.
+// ShiftRightSignExtended shifts each element in x to the right by the number of bits specified in y's corresponding elements. Emptied upper bits are filled with the sign bit.
 //
-// Asm: VPMINUQ, CPU Feature: AVX512EVEX
-func (x Uint64x8) Min(y Uint64x8) Uint64x8
-
-/* Mul */
+// Asm: VPSRAVD, CPU Feature: AVX512EVEX
+func (x Uint32x16) MaskedShiftRightSignExtended(y Uint32x16, z Mask32x16) Uint32x16
 
-// Mul multiplies corresponding elements of two vectors.
+// ShiftRightSignExtended shifts each element in x to the right by the number of bits specified in y's corresponding elements. Emptied upper bits are filled with the sign bit.
 //
-// Asm: VMULPS, CPU Feature: AVX
-func (x Float32x4) Mul(y Float32x4) Float32x4
+// Asm: VPSRAVQ, CPU Feature: AVX512EVEX
+func (x Uint64x2) MaskedShiftRightSignExtended(y Uint64x2, z Mask64x2) Uint64x2
 
-// Mul multiplies corresponding elements of two vectors.
+// ShiftRightSignExtended shifts each element in x to the right by the number of bits specified in y's corresponding elements. Emptied upper bits are filled with the sign bit.
 //
-// Asm: VMULPS, CPU Feature: AVX
-func (x Float32x8) Mul(y Float32x8) Float32x8
+// Asm: VPSRAVQ, CPU Feature: AVX512EVEX
+func (x Uint64x4) MaskedShiftRightSignExtended(y Uint64x4, z Mask64x4) Uint64x4
 
-// Mul multiplies corresponding elements of two vectors, masked.
+// ShiftRightSignExtended shifts each element in x to the right by the number of bits specified in y's corresponding elements. Emptied upper bits are filled with the sign bit.
 //
-// Asm: VMULPS, CPU Feature: AVX512EVEX
-func (x Float32x16) Mul(y Float32x16) Float32x16
+// Asm: VPSRAVQ, CPU Feature: AVX512EVEX
+func (x Uint64x8) MaskedShiftRightSignExtended(y Uint64x8, z Mask64x8) Uint64x8
 
-// Mul multiplies corresponding elements of two vectors.
-//
-// Asm: VMULPD, CPU Feature: AVX
-func (x Float64x2) Mul(y Float64x2) Float64x2
+/* MaskedSqrt */
 
-// Mul multiplies corresponding elements of two vectors.
+// Sqrt computes the square root of each element.
 //
-// Asm: VMULPD, CPU Feature: AVX
-func (x Float64x4) Mul(y Float64x4) Float64x4
+// Asm: VSQRTPS, CPU Feature: AVX512EVEX
+func (x Float32x4) MaskedSqrt(y Mask32x4) Float32x4
 
-// Mul multiplies corresponding elements of two vectors, masked.
+// Sqrt computes the square root of each element.
 //
-// Asm: VMULPD, CPU Feature: AVX512EVEX
-func (x Float64x8) Mul(y Float64x8) Float64x8
-
-/* MulByPowOf2 */
+// Asm: VSQRTPS, CPU Feature: AVX512EVEX
+func (x Float32x8) MaskedSqrt(y Mask32x8) Float32x8
 
-// MulByPowOf2 multiplies elements by a power of 2.
+// Sqrt computes the square root of each element.
 //
-// Asm: VSCALEFPS, CPU Feature: AVX512EVEX
-func (x Float32x4) MulByPowOf2(y Float32x4) Float32x4
+// Asm: VSQRTPS, CPU Feature: AVX512EVEX
+func (x Float32x16) MaskedSqrt(y Mask32x16) Float32x16
 
-// MulByPowOf2 multiplies elements by a power of 2.
+// Sqrt computes the square root of each element.
 //
-// Asm: VSCALEFPS, CPU Feature: AVX512EVEX
-func (x Float32x8) MulByPowOf2(y Float32x8) Float32x8
+// Asm: VSQRTPD, CPU Feature: AVX512EVEX
+func (x Float64x2) MaskedSqrt(y Mask64x2) Float64x2
 
-// MulByPowOf2 multiplies elements by a power of 2.
+// Sqrt computes the square root of each element.
 //
-// Asm: VSCALEFPS, CPU Feature: AVX512EVEX
-func (x Float32x16) MulByPowOf2(y Float32x16) Float32x16
+// Asm: VSQRTPD, CPU Feature: AVX512EVEX
+func (x Float64x4) MaskedSqrt(y Mask64x4) Float64x4
 
-// MulByPowOf2 multiplies elements by a power of 2.
+// Sqrt computes the square root of each element.
 //
-// Asm: VSCALEFPD, CPU Feature: AVX512EVEX
-func (x Float64x2) MulByPowOf2(y Float64x2) Float64x2
+// Asm: VSQRTPD, CPU Feature: AVX512EVEX
+func (x Float64x8) MaskedSqrt(y Mask64x8) Float64x8
 
-// MulByPowOf2 multiplies elements by a power of 2.
-//
-// Asm: VSCALEFPD, CPU Feature: AVX512EVEX
-func (x Float64x4) MulByPowOf2(y Float64x4) Float64x4
+/* MaskedSub */
 
-// MulByPowOf2 multiplies elements by a power of 2.
+// Sub subtracts corresponding elements of two vectors.
 //
-// Asm: VSCALEFPD, CPU Feature: AVX512EVEX
-func (x Float64x8) MulByPowOf2(y Float64x8) Float64x8
-
-/* MulEvenWiden */
+// Asm: VSUBPS, CPU Feature: AVX512EVEX
+func (x Float32x4) MaskedSub(y Float32x4, z Mask32x4) Float32x4
 
-// MulEvenWiden multiplies even-indexed elements, widening the result.
-// Result[i] = v1.Even[i] * v2.Even[i].
+// Sub subtracts corresponding elements of two vectors.
 //
-// Asm: VPMULDQ, CPU Feature: AVX
-func (x Int32x4) MulEvenWiden(y Int32x4) Int64x2
+// Asm: VSUBPS, CPU Feature: AVX512EVEX
+func (x Float32x8) MaskedSub(y Float32x8, z Mask32x8) Float32x8
 
-// MulEvenWiden multiplies even-indexed elements, widening the result.
-// Result[i] = v1.Even[i] * v2.Even[i].
+// Sub subtracts corresponding elements of two vectors.
 //
-// Asm: VPMULDQ, CPU Feature: AVX2
-func (x Int32x8) MulEvenWiden(y Int32x8) Int64x4
+// Asm: VSUBPS, CPU Feature: AVX512EVEX
+func (x Float32x16) MaskedSub(y Float32x16, z Mask32x16) Float32x16
 
-// MulEvenWiden multiplies even-indexed elements, widening the result, masked.
-// Result[i] = v1.Even[i] * v2.Even[i].
+// Sub subtracts corresponding elements of two vectors.
 //
-// Asm: VPMULDQ, CPU Feature: AVX512EVEX
-func (x Int64x2) MulEvenWiden(y Int64x2) Int64x2
+// Asm: VSUBPD, CPU Feature: AVX512EVEX
+func (x Float64x2) MaskedSub(y Float64x2, z Mask64x2) Float64x2
 
-// MulEvenWiden multiplies even-indexed elements, widening the result, masked.
-// Result[i] = v1.Even[i] * v2.Even[i].
+// Sub subtracts corresponding elements of two vectors.
 //
-// Asm: VPMULDQ, CPU Feature: AVX512EVEX
-func (x Int64x4) MulEvenWiden(y Int64x4) Int64x4
+// Asm: VSUBPD, CPU Feature: AVX512EVEX
+func (x Float64x4) MaskedSub(y Float64x4, z Mask64x4) Float64x4
 
-// MulEvenWiden multiplies even-indexed elements, widening the result, masked.
-// Result[i] = v1.Even[i] * v2.Even[i].
+// Sub subtracts corresponding elements of two vectors.
 //
-// Asm: VPMULDQ, CPU Feature: AVX512EVEX
-func (x Int64x8) MulEvenWiden(y Int64x8) Int64x8
+// Asm: VSUBPD, CPU Feature: AVX512EVEX
+func (x Float64x8) MaskedSub(y Float64x8, z Mask64x8) Float64x8
 
-// MulEvenWiden multiplies even-indexed elements, widening the result.
-// Result[i] = v1.Even[i] * v2.Even[i].
+// Sub subtracts corresponding elements of two vectors.
 //
-// Asm: VPMULUDQ, CPU Feature: AVX
-func (x Uint32x4) MulEvenWiden(y Uint32x4) Uint64x2
+// Asm: VPSUBB, CPU Feature: AVX512EVEX
+func (x Int8x16) MaskedSub(y Int8x16, z Mask8x16) Int8x16
 
-// MulEvenWiden multiplies even-indexed elements, widening the result.
-// Result[i] = v1.Even[i] * v2.Even[i].
+// Sub subtracts corresponding elements of two vectors.
 //
-// Asm: VPMULUDQ, CPU Feature: AVX2
-func (x Uint32x8) MulEvenWiden(y Uint32x8) Uint64x4
+// Asm: VPSUBB, CPU Feature: AVX512EVEX
+func (x Int8x32) MaskedSub(y Int8x32, z Mask8x32) Int8x32
 
-// MulEvenWiden multiplies even-indexed elements, widening the result, masked.
-// Result[i] = v1.Even[i] * v2.Even[i].
+// Sub subtracts corresponding elements of two vectors.
 //
-// Asm: VPMULUDQ, CPU Feature: AVX512EVEX
-func (x Uint64x2) MulEvenWiden(y Uint64x2) Uint64x2
+// Asm: VPSUBB, CPU Feature: AVX512EVEX
+func (x Int8x64) MaskedSub(y Int8x64, z Mask8x64) Int8x64
 
-// MulEvenWiden multiplies even-indexed elements, widening the result, masked.
-// Result[i] = v1.Even[i] * v2.Even[i].
+// Sub subtracts corresponding elements of two vectors.
 //
-// Asm: VPMULUDQ, CPU Feature: AVX512EVEX
-func (x Uint64x4) MulEvenWiden(y Uint64x4) Uint64x4
+// Asm: VPSUBW, CPU Feature: AVX512EVEX
+func (x Int16x8) MaskedSub(y Int16x8, z Mask16x8) Int16x8
 
-// MulEvenWiden multiplies even-indexed elements, widening the result, masked.
-// Result[i] = v1.Even[i] * v2.Even[i].
+// Sub subtracts corresponding elements of two vectors.
 //
-// Asm: VPMULUDQ, CPU Feature: AVX512EVEX
-func (x Uint64x8) MulEvenWiden(y Uint64x8) Uint64x8
+// Asm: VPSUBW, CPU Feature: AVX512EVEX
+func (x Int16x16) MaskedSub(y Int16x16, z Mask16x16) Int16x16
 
-/* MulHigh */
+// Sub subtracts corresponding elements of two vectors.
+//
+// Asm: VPSUBW, CPU Feature: AVX512EVEX
+func (x Int16x32) MaskedSub(y Int16x32, z Mask16x32) Int16x32
 
-// MulHigh multiplies elements and stores the high part of the result.
+// Sub subtracts corresponding elements of two vectors.
 //
-// Asm: VPMULHW, CPU Feature: AVX
-func (x Int16x8) MulHigh(y Int16x8) Int16x8
+// Asm: VPSUBD, CPU Feature: AVX512EVEX
+func (x Int32x4) MaskedSub(y Int32x4, z Mask32x4) Int32x4
 
-// MulHigh multiplies elements and stores the high part of the result.
+// Sub subtracts corresponding elements of two vectors.
 //
-// Asm: VPMULHW, CPU Feature: AVX2
-func (x Int16x16) MulHigh(y Int16x16) Int16x16
+// Asm: VPSUBD, CPU Feature: AVX512EVEX
+func (x Int32x8) MaskedSub(y Int32x8, z Mask32x8) Int32x8
 
-// MulHigh multiplies elements and stores the high part of the result, masked.
+// Sub subtracts corresponding elements of two vectors.
 //
-// Asm: VPMULHW, CPU Feature: AVX512EVEX
-func (x Int16x32) MulHigh(y Int16x32) Int16x32
+// Asm: VPSUBD, CPU Feature: AVX512EVEX
+func (x Int32x16) MaskedSub(y Int32x16, z Mask32x16) Int32x16
 
-// MulHigh multiplies elements and stores the high part of the result.
+// Sub subtracts corresponding elements of two vectors.
 //
-// Asm: VPMULHUW, CPU Feature: AVX
-func (x Uint16x8) MulHigh(y Uint16x8) Uint16x8
+// Asm: VPSUBQ, CPU Feature: AVX512EVEX
+func (x Int64x2) MaskedSub(y Int64x2, z Mask64x2) Int64x2
 
-// MulHigh multiplies elements and stores the high part of the result.
+// Sub subtracts corresponding elements of two vectors.
 //
-// Asm: VPMULHUW, CPU Feature: AVX2
-func (x Uint16x16) MulHigh(y Uint16x16) Uint16x16
+// Asm: VPSUBQ, CPU Feature: AVX512EVEX
+func (x Int64x4) MaskedSub(y Int64x4, z Mask64x4) Int64x4
 
-// MulHigh multiplies elements and stores the high part of the result, masked.
+// Sub subtracts corresponding elements of two vectors.
 //
-// Asm: VPMULHUW, CPU Feature: AVX512EVEX
-func (x Uint16x32) MulHigh(y Uint16x32) Uint16x32
+// Asm: VPSUBQ, CPU Feature: AVX512EVEX
+func (x Int64x8) MaskedSub(y Int64x8, z Mask64x8) Int64x8
 
-/* MulLow */
+// Sub subtracts corresponding elements of two vectors.
+//
+// Asm: VPSUBB, CPU Feature: AVX512EVEX
+func (x Uint8x16) MaskedSub(y Uint8x16, z Mask8x16) Uint8x16
 
-// MulLow multiplies elements and stores the low part of the result.
+// Sub subtracts corresponding elements of two vectors.
 //
-// Asm: VPMULLW, CPU Feature: AVX
-func (x Int16x8) MulLow(y Int16x8) Int16x8
+// Asm: VPSUBB, CPU Feature: AVX512EVEX
+func (x Uint8x32) MaskedSub(y Uint8x32, z Mask8x32) Uint8x32
 
-// MulLow multiplies elements and stores the low part of the result.
+// Sub subtracts corresponding elements of two vectors.
 //
-// Asm: VPMULLW, CPU Feature: AVX2
-func (x Int16x16) MulLow(y Int16x16) Int16x16
+// Asm: VPSUBB, CPU Feature: AVX512EVEX
+func (x Uint8x64) MaskedSub(y Uint8x64, z Mask8x64) Uint8x64
 
-// MulLow multiplies elements and stores the low part of the result, masked.
+// Sub subtracts corresponding elements of two vectors.
 //
-// Asm: VPMULLW, CPU Feature: AVX512EVEX
-func (x Int16x32) MulLow(y Int16x32) Int16x32
+// Asm: VPSUBW, CPU Feature: AVX512EVEX
+func (x Uint16x8) MaskedSub(y Uint16x8, z Mask16x8) Uint16x8
 
-// MulLow multiplies elements and stores the low part of the result.
+// Sub subtracts corresponding elements of two vectors.
 //
-// Asm: VPMULLD, CPU Feature: AVX
-func (x Int32x4) MulLow(y Int32x4) Int32x4
+// Asm: VPSUBW, CPU Feature: AVX512EVEX
+func (x Uint16x16) MaskedSub(y Uint16x16, z Mask16x16) Uint16x16
 
-// MulLow multiplies elements and stores the low part of the result.
+// Sub subtracts corresponding elements of two vectors.
 //
-// Asm: VPMULLD, CPU Feature: AVX2
-func (x Int32x8) MulLow(y Int32x8) Int32x8
+// Asm: VPSUBW, CPU Feature: AVX512EVEX
+func (x Uint16x32) MaskedSub(y Uint16x32, z Mask16x32) Uint16x32
 
-// MulLow multiplies elements and stores the low part of the result, masked.
+// Sub subtracts corresponding elements of two vectors.
 //
-// Asm: VPMULLD, CPU Feature: AVX512EVEX
-func (x Int32x16) MulLow(y Int32x16) Int32x16
+// Asm: VPSUBD, CPU Feature: AVX512EVEX
+func (x Uint32x4) MaskedSub(y Uint32x4, z Mask32x4) Uint32x4
 
-// MulLow multiplies elements and stores the low part of the result, masked.
+// Sub subtracts corresponding elements of two vectors.
 //
-// Asm: VPMULLQ, CPU Feature: AVX512EVEX
-func (x Int64x2) MulLow(y Int64x2) Int64x2
+// Asm: VPSUBD, CPU Feature: AVX512EVEX
+func (x Uint32x8) MaskedSub(y Uint32x8, z Mask32x8) Uint32x8
 
-// MulLow multiplies elements and stores the low part of the result, masked.
+// Sub subtracts corresponding elements of two vectors.
 //
-// Asm: VPMULLQ, CPU Feature: AVX512EVEX
-func (x Int64x4) MulLow(y Int64x4) Int64x4
+// Asm: VPSUBD, CPU Feature: AVX512EVEX
+func (x Uint32x16) MaskedSub(y Uint32x16, z Mask32x16) Uint32x16
 
-// MulLow multiplies elements and stores the low part of the result, masked.
+// Sub subtracts corresponding elements of two vectors.
 //
-// Asm: VPMULLQ, CPU Feature: AVX512EVEX
-func (x Int64x8) MulLow(y Int64x8) Int64x8
+// Asm: VPSUBQ, CPU Feature: AVX512EVEX
+func (x Uint64x2) MaskedSub(y Uint64x2, z Mask64x2) Uint64x2
 
-/* NotEqual */
+// Sub subtracts corresponding elements of two vectors.
+//
+// Asm: VPSUBQ, CPU Feature: AVX512EVEX
+func (x Uint64x4) MaskedSub(y Uint64x4, z Mask64x4) Uint64x4
+
+// Sub subtracts corresponding elements of two vectors.
+//
+// Asm: VPSUBQ, CPU Feature: AVX512EVEX
+func (x Uint64x8) MaskedSub(y Uint64x8, z Mask64x8) Uint64x8
+
+/* MaskedTruncSuppressExceptionWithPrecision */
+
+// TruncSuppressExceptionWithPrecision truncates elements with specified precision, suppressing exceptions.
+// Const Immediate = 11.
+//
+// Asm: VRNDSCALEPS, CPU Feature: AVX512EVEX
+func (x Float32x4) MaskedTruncSuppressExceptionWithPrecision(imm uint8, y Mask32x4) Float32x4
+
+// TruncSuppressExceptionWithPrecision truncates elements with specified precision, suppressing exceptions.
+// Const Immediate = 11.
+//
+// Asm: VRNDSCALEPS, CPU Feature: AVX512EVEX
+func (x Float32x8) MaskedTruncSuppressExceptionWithPrecision(imm uint8, y Mask32x8) Float32x8
+
+// TruncSuppressExceptionWithPrecision truncates elements with specified precision, suppressing exceptions.
+// Const Immediate = 11.
+//
+// Asm: VRNDSCALEPS, CPU Feature: AVX512EVEX
+func (x Float32x16) MaskedTruncSuppressExceptionWithPrecision(imm uint8, y Mask32x16) Float32x16
+
+// TruncSuppressExceptionWithPrecision truncates elements with specified precision, suppressing exceptions.
+// Const Immediate = 11.
+//
+// Asm: VRNDSCALEPD, CPU Feature: AVX512EVEX
+func (x Float64x2) MaskedTruncSuppressExceptionWithPrecision(imm uint8, y Mask64x2) Float64x2
+
+// TruncSuppressExceptionWithPrecision truncates elements with specified precision, suppressing exceptions.
+// Const Immediate = 11.
+//
+// Asm: VRNDSCALEPD, CPU Feature: AVX512EVEX
+func (x Float64x4) MaskedTruncSuppressExceptionWithPrecision(imm uint8, y Mask64x4) Float64x4
+
+// TruncSuppressExceptionWithPrecision truncates elements with specified precision, suppressing exceptions.
+// Const Immediate = 11.
+//
+// Asm: VRNDSCALEPD, CPU Feature: AVX512EVEX
+func (x Float64x8) MaskedTruncSuppressExceptionWithPrecision(imm uint8, y Mask64x8) Float64x8
+
+/* MaskedTruncWithPrecision */
+
+// TruncWithPrecision truncates elements with specified precision.
+// Const Immediate = 3.
+//
+// Asm: VRNDSCALEPS, CPU Feature: AVX512EVEX
+func (x Float32x4) MaskedTruncWithPrecision(imm uint8, y Mask32x4) Float32x4
+
+// TruncWithPrecision truncates elements with specified precision.
+// Const Immediate = 3.
+//
+// Asm: VRNDSCALEPS, CPU Feature: AVX512EVEX
+func (x Float32x8) MaskedTruncWithPrecision(imm uint8, y Mask32x8) Float32x8
+
+// TruncWithPrecision truncates elements with specified precision.
+// Const Immediate = 3.
+//
+// Asm: VRNDSCALEPS, CPU Feature: AVX512EVEX
+func (x Float32x16) MaskedTruncWithPrecision(imm uint8, y Mask32x16) Float32x16
+
+// TruncWithPrecision truncates elements with specified precision.
+// Const Immediate = 3.
+//
+// Asm: VRNDSCALEPD, CPU Feature: AVX512EVEX
+func (x Float64x2) MaskedTruncWithPrecision(imm uint8, y Mask64x2) Float64x2
+
+// TruncWithPrecision truncates elements with specified precision.
+// Const Immediate = 3.
+//
+// Asm: VRNDSCALEPD, CPU Feature: AVX512EVEX
+func (x Float64x4) MaskedTruncWithPrecision(imm uint8, y Mask64x4) Float64x4
+
+// TruncWithPrecision truncates elements with specified precision.
+// Const Immediate = 3.
+//
+// Asm: VRNDSCALEPD, CPU Feature: AVX512EVEX
+func (x Float64x8) MaskedTruncWithPrecision(imm uint8, y Mask64x8) Float64x8
+
+/* MaskedUnsignedSignedQuadDotProdAccumulate */
+
+// UnsignedSignedQuadDotProdAccumulate performs dot products on groups of 4 elements of y and z and accumulates the results to x.
+//
+// Asm: VPDPBUSD, CPU Feature: AVX512EVEX
+func (x Int32x4) MaskedUnsignedSignedQuadDotProdAccumulate(y Uint8x16, z Int8x16, u Mask32x4) Int32x4
+
+// UnsignedSignedQuadDotProdAccumulate performs dot products on groups of 4 elements of y and z and accumulates the results to x.
+//
+// Asm: VPDPBUSD, CPU Feature: AVX512EVEX
+func (x Int32x8) MaskedUnsignedSignedQuadDotProdAccumulate(y Uint8x32, z Int8x32, u Mask32x8) Int32x8
+
+// UnsignedSignedQuadDotProdAccumulate performs dot products on groups of 4 elements of y and z and accumulates the results to x.
+//
+// Asm: VPDPBUSD, CPU Feature: AVX512EVEX
+func (x Int32x16) MaskedUnsignedSignedQuadDotProdAccumulate(y Uint8x64, z Int8x64, u Mask32x16) Int32x16
+
+// UnsignedSignedQuadDotProdAccumulate performs dot products on groups of 4 elements of y and z and accumulates the results to x.
+//
+// Asm: VPDPBUSD, CPU Feature: AVX512EVEX
+func (x Uint32x4) MaskedUnsignedSignedQuadDotProdAccumulate(y Uint8x16, z Int8x16, u Mask32x4) Uint32x4
+
+// UnsignedSignedQuadDotProdAccumulate performs dot products on groups of 4 elements of y and z and accumulates the results to x.
+//
+// Asm: VPDPBUSD, CPU Feature: AVX512EVEX
+func (x Uint32x8) MaskedUnsignedSignedQuadDotProdAccumulate(y Uint8x32, z Int8x32, u Mask32x8) Uint32x8
+
+// UnsignedSignedQuadDotProdAccumulate performs dot products on groups of 4 elements of y and z and accumulates the results to x.
+//
+// Asm: VPDPBUSD, CPU Feature: AVX512EVEX
+func (x Uint32x16) MaskedUnsignedSignedQuadDotProdAccumulate(y Uint8x64, z Int8x64, u Mask32x16) Uint32x16
+
+/* MaskedXor */
+
+// Xor performs a masked bitwise XOR operation between two vectors.
+//
+// Asm: VXORPS, CPU Feature: AVX512EVEX
+func (x Float32x4) MaskedXor(y Float32x4, z Mask32x4) Float32x4
+
+// Xor performs a masked bitwise XOR operation between two vectors.
+//
+// Asm: VXORPS, CPU Feature: AVX512EVEX
+func (x Float32x8) MaskedXor(y Float32x8, z Mask32x8) Float32x8
+
+// Xor performs a masked bitwise XOR operation between two vectors.
+//
+// Asm: VXORPS, CPU Feature: AVX512EVEX
+func (x Float32x16) MaskedXor(y Float32x16, z Mask32x16) Float32x16
+
+// Xor performs a masked bitwise XOR operation between two vectors.
+//
+// Asm: VXORPD, CPU Feature: AVX512EVEX
+func (x Float64x2) MaskedXor(y Float64x2, z Mask64x2) Float64x2
+
+// Xor performs a masked bitwise XOR operation between two vectors.
+//
+// Asm: VXORPD, CPU Feature: AVX512EVEX
+func (x Float64x4) MaskedXor(y Float64x4, z Mask64x4) Float64x4
+
+// Xor performs a masked bitwise XOR operation between two vectors.
+//
+// Asm: VXORPD, CPU Feature: AVX512EVEX
+func (x Float64x8) MaskedXor(y Float64x8, z Mask64x8) Float64x8
+
+// Xor performs a masked bitwise XOR operation between two vectors.
+//
+// Asm: VPXORD, CPU Feature: AVX512EVEX
+func (x Int32x4) MaskedXor(y Int32x4, z Mask32x4) Int32x4
+
+// Xor performs a masked bitwise XOR operation between two vectors.
+//
+// Asm: VPXORD, CPU Feature: AVX512EVEX
+func (x Int32x8) MaskedXor(y Int32x8, z Mask32x8) Int32x8
+
+// Xor performs a masked bitwise XOR operation between two vectors.
+//
+// Asm: VPXORD, CPU Feature: AVX512EVEX
+func (x Int32x16) MaskedXor(y Int32x16, z Mask32x16) Int32x16
+
+// Xor performs a masked bitwise XOR operation between two vectors.
+//
+// Asm: VPXORQ, CPU Feature: AVX512EVEX
+func (x Int64x2) MaskedXor(y Int64x2, z Mask64x2) Int64x2
+
+// Xor performs a masked bitwise XOR operation between two vectors.
+//
+// Asm: VPXORQ, CPU Feature: AVX512EVEX
+func (x Int64x4) MaskedXor(y Int64x4, z Mask64x4) Int64x4
+
+// Xor performs a masked bitwise XOR operation between two vectors.
+//
+// Asm: VPXORQ, CPU Feature: AVX512EVEX
+func (x Int64x8) MaskedXor(y Int64x8, z Mask64x8) Int64x8
+
+// Xor performs a masked bitwise XOR operation between two vectors.
+//
+// Asm: VPXORD, CPU Feature: AVX512EVEX
+func (x Uint32x4) MaskedXor(y Uint32x4, z Mask32x4) Uint32x4
+
+// Xor performs a masked bitwise XOR operation between two vectors.
+//
+// Asm: VPXORD, CPU Feature: AVX512EVEX
+func (x Uint32x8) MaskedXor(y Uint32x8, z Mask32x8) Uint32x8
+
+// Xor performs a masked bitwise XOR operation between two vectors.
+//
+// Asm: VPXORD, CPU Feature: AVX512EVEX
+func (x Uint32x16) MaskedXor(y Uint32x16, z Mask32x16) Uint32x16
+
+// Xor performs a masked bitwise XOR operation between two vectors.
+//
+// Asm: VPXORQ, CPU Feature: AVX512EVEX
+func (x Uint64x2) MaskedXor(y Uint64x2, z Mask64x2) Uint64x2
+
+// Xor performs a masked bitwise XOR operation between two vectors.
+//
+// Asm: VPXORQ, CPU Feature: AVX512EVEX
+func (x Uint64x4) MaskedXor(y Uint64x4, z Mask64x4) Uint64x4
+
+// Xor performs a masked bitwise XOR operation between two vectors.
+//
+// Asm: VPXORQ, CPU Feature: AVX512EVEX
+func (x Uint64x8) MaskedXor(y Uint64x8, z Mask64x8) Uint64x8
+
+/* Max */
+
+// Max computes the maximum of corresponding elements.
+//
+// Asm: VMAXPS, CPU Feature: AVX
+func (x Float32x4) Max(y Float32x4) Float32x4
+
+// Max computes the maximum of corresponding elements.
+//
+// Asm: VMAXPS, CPU Feature: AVX
+func (x Float32x8) Max(y Float32x8) Float32x8
+
+// Max computes the maximum of corresponding elements.
+//
+// Asm: VMAXPS, CPU Feature: AVX512EVEX
+func (x Float32x16) Max(y Float32x16) Float32x16
+
+// Max computes the maximum of corresponding elements.
+//
+// Asm: VMAXPD, CPU Feature: AVX
+func (x Float64x2) Max(y Float64x2) Float64x2
+
+// Max computes the maximum of corresponding elements.
+//
+// Asm: VMAXPD, CPU Feature: AVX
+func (x Float64x4) Max(y Float64x4) Float64x4
+
+// Max computes the maximum of corresponding elements.
+//
+// Asm: VMAXPD, CPU Feature: AVX512EVEX
+func (x Float64x8) Max(y Float64x8) Float64x8
+
+// Max computes the maximum of corresponding elements.
+//
+// Asm: VPMAXSB, CPU Feature: AVX
+func (x Int8x16) Max(y Int8x16) Int8x16
+
+// Max computes the maximum of corresponding elements.
+//
+// Asm: VPMAXSB, CPU Feature: AVX2
+func (x Int8x32) Max(y Int8x32) Int8x32
+
+// Max computes the maximum of corresponding elements.
+//
+// Asm: VPMAXSB, CPU Feature: AVX512EVEX
+func (x Int8x64) Max(y Int8x64) Int8x64
+
+// Max computes the maximum of corresponding elements.
+//
+// Asm: VPMAXSW, CPU Feature: AVX
+func (x Int16x8) Max(y Int16x8) Int16x8
+
+// Max computes the maximum of corresponding elements.
+//
+// Asm: VPMAXSW, CPU Feature: AVX2
+func (x Int16x16) Max(y Int16x16) Int16x16
+
+// Max computes the maximum of corresponding elements.
+//
+// Asm: VPMAXSW, CPU Feature: AVX512EVEX
+func (x Int16x32) Max(y Int16x32) Int16x32
+
+// Max computes the maximum of corresponding elements.
+//
+// Asm: VPMAXSD, CPU Feature: AVX
+func (x Int32x4) Max(y Int32x4) Int32x4
+
+// Max computes the maximum of corresponding elements.
+//
+// Asm: VPMAXSD, CPU Feature: AVX2
+func (x Int32x8) Max(y Int32x8) Int32x8
+
+// Max computes the maximum of corresponding elements.
+//
+// Asm: VPMAXSD, CPU Feature: AVX512EVEX
+func (x Int32x16) Max(y Int32x16) Int32x16
+
+// Max computes the maximum of corresponding elements.
+//
+// Asm: VPMAXSQ, CPU Feature: AVX512EVEX
+func (x Int64x2) Max(y Int64x2) Int64x2
+
+// Max computes the maximum of corresponding elements.
+//
+// Asm: VPMAXSQ, CPU Feature: AVX512EVEX
+func (x Int64x4) Max(y Int64x4) Int64x4
+
+// Max computes the maximum of corresponding elements.
+//
+// Asm: VPMAXSQ, CPU Feature: AVX512EVEX
+func (x Int64x8) Max(y Int64x8) Int64x8
+
+// Max computes the maximum of corresponding elements.
+//
+// Asm: VPMAXUB, CPU Feature: AVX
+func (x Uint8x16) Max(y Uint8x16) Uint8x16
+
+// Max computes the maximum of corresponding elements.
+//
+// Asm: VPMAXUB, CPU Feature: AVX2
+func (x Uint8x32) Max(y Uint8x32) Uint8x32
+
+// Max computes the maximum of corresponding elements.
+//
+// Asm: VPMAXUB, CPU Feature: AVX512EVEX
+func (x Uint8x64) Max(y Uint8x64) Uint8x64
+
+// Max computes the maximum of corresponding elements.
+//
+// Asm: VPMAXUW, CPU Feature: AVX
+func (x Uint16x8) Max(y Uint16x8) Uint16x8
+
+// Max computes the maximum of corresponding elements.
+//
+// Asm: VPMAXUW, CPU Feature: AVX2
+func (x Uint16x16) Max(y Uint16x16) Uint16x16
+
+// Max computes the maximum of corresponding elements.
+//
+// Asm: VPMAXUW, CPU Feature: AVX512EVEX
+func (x Uint16x32) Max(y Uint16x32) Uint16x32
+
+// Max computes the maximum of corresponding elements.
+//
+// Asm: VPMAXUD, CPU Feature: AVX
+func (x Uint32x4) Max(y Uint32x4) Uint32x4
+
+// Max computes the maximum of corresponding elements.
+//
+// Asm: VPMAXUD, CPU Feature: AVX2
+func (x Uint32x8) Max(y Uint32x8) Uint32x8
+
+// Max computes the maximum of corresponding elements.
+//
+// Asm: VPMAXUD, CPU Feature: AVX512EVEX
+func (x Uint32x16) Max(y Uint32x16) Uint32x16
+
+// Max computes the maximum of corresponding elements.
+//
+// Asm: VPMAXUQ, CPU Feature: AVX512EVEX
+func (x Uint64x2) Max(y Uint64x2) Uint64x2
+
+// Max computes the maximum of corresponding elements.
+//
+// Asm: VPMAXUQ, CPU Feature: AVX512EVEX
+func (x Uint64x4) Max(y Uint64x4) Uint64x4
+
+// Max computes the maximum of corresponding elements.
+//
+// Asm: VPMAXUQ, CPU Feature: AVX512EVEX
+func (x Uint64x8) Max(y Uint64x8) Uint64x8
+
+/* Min */
+
+// Min computes the minimum of corresponding elements.
+//
+// Asm: VMINPS, CPU Feature: AVX
+func (x Float32x4) Min(y Float32x4) Float32x4
+
+// Min computes the minimum of corresponding elements.
+//
+// Asm: VMINPS, CPU Feature: AVX
+func (x Float32x8) Min(y Float32x8) Float32x8
+
+// Min computes the minimum of corresponding elements.
+//
+// Asm: VMINPS, CPU Feature: AVX512EVEX
+func (x Float32x16) Min(y Float32x16) Float32x16
+
+// Min computes the minimum of corresponding elements.
+//
+// Asm: VMINPD, CPU Feature: AVX
+func (x Float64x2) Min(y Float64x2) Float64x2
+
+// Min computes the minimum of corresponding elements.
+//
+// Asm: VMINPD, CPU Feature: AVX
+func (x Float64x4) Min(y Float64x4) Float64x4
+
+// Min computes the minimum of corresponding elements.
+//
+// Asm: VMINPD, CPU Feature: AVX512EVEX
+func (x Float64x8) Min(y Float64x8) Float64x8
+
+// Min computes the minimum of corresponding elements.
+//
+// Asm: VPMINSB, CPU Feature: AVX
+func (x Int8x16) Min(y Int8x16) Int8x16
+
+// Min computes the minimum of corresponding elements.
+//
+// Asm: VPMINSB, CPU Feature: AVX2
+func (x Int8x32) Min(y Int8x32) Int8x32
+
+// Min computes the minimum of corresponding elements.
+//
+// Asm: VPMINSB, CPU Feature: AVX512EVEX
+func (x Int8x64) Min(y Int8x64) Int8x64
+
+// Min computes the minimum of corresponding elements.
+//
+// Asm: VPMINSW, CPU Feature: AVX
+func (x Int16x8) Min(y Int16x8) Int16x8
+
+// Min computes the minimum of corresponding elements.
+//
+// Asm: VPMINSW, CPU Feature: AVX2
+func (x Int16x16) Min(y Int16x16) Int16x16
+
+// Min computes the minimum of corresponding elements.
+//
+// Asm: VPMINSW, CPU Feature: AVX512EVEX
+func (x Int16x32) Min(y Int16x32) Int16x32
+
+// Min computes the minimum of corresponding elements.
+//
+// Asm: VPMINSD, CPU Feature: AVX
+func (x Int32x4) Min(y Int32x4) Int32x4
+
+// Min computes the minimum of corresponding elements.
+//
+// Asm: VPMINSD, CPU Feature: AVX2
+func (x Int32x8) Min(y Int32x8) Int32x8
+
+// Min computes the minimum of corresponding elements.
+//
+// Asm: VPMINSD, CPU Feature: AVX512EVEX
+func (x Int32x16) Min(y Int32x16) Int32x16
+
+// Min computes the minimum of corresponding elements.
+//
+// Asm: VPMINSQ, CPU Feature: AVX512EVEX
+func (x Int64x2) Min(y Int64x2) Int64x2
+
+// Min computes the minimum of corresponding elements.
+//
+// Asm: VPMINSQ, CPU Feature: AVX512EVEX
+func (x Int64x4) Min(y Int64x4) Int64x4
+
+// Min computes the minimum of corresponding elements.
+//
+// Asm: VPMINSQ, CPU Feature: AVX512EVEX
+func (x Int64x8) Min(y Int64x8) Int64x8
+
+// Min computes the minimum of corresponding elements.
+//
+// Asm: VPMINUB, CPU Feature: AVX
+func (x Uint8x16) Min(y Uint8x16) Uint8x16
+
+// Min computes the minimum of corresponding elements.
+//
+// Asm: VPMINUB, CPU Feature: AVX2
+func (x Uint8x32) Min(y Uint8x32) Uint8x32
+
+// Min computes the minimum of corresponding elements.
+//
+// Asm: VPMINUB, CPU Feature: AVX512EVEX
+func (x Uint8x64) Min(y Uint8x64) Uint8x64
+
+// Min computes the minimum of corresponding elements.
+//
+// Asm: VPMINUW, CPU Feature: AVX
+func (x Uint16x8) Min(y Uint16x8) Uint16x8
+
+// Min computes the minimum of corresponding elements.
+//
+// Asm: VPMINUW, CPU Feature: AVX2
+func (x Uint16x16) Min(y Uint16x16) Uint16x16
+
+// Min computes the minimum of corresponding elements.
+//
+// Asm: VPMINUW, CPU Feature: AVX512EVEX
+func (x Uint16x32) Min(y Uint16x32) Uint16x32
+
+// Min computes the minimum of corresponding elements.
+//
+// Asm: VPMINUD, CPU Feature: AVX
+func (x Uint32x4) Min(y Uint32x4) Uint32x4
+
+// Min computes the minimum of corresponding elements.
+//
+// Asm: VPMINUD, CPU Feature: AVX2
+func (x Uint32x8) Min(y Uint32x8) Uint32x8
+
+// Min computes the minimum of corresponding elements.
+//
+// Asm: VPMINUD, CPU Feature: AVX512EVEX
+func (x Uint32x16) Min(y Uint32x16) Uint32x16
+
+// Min computes the minimum of corresponding elements.
+//
+// Asm: VPMINUQ, CPU Feature: AVX512EVEX
+func (x Uint64x2) Min(y Uint64x2) Uint64x2
+
+// Min computes the minimum of corresponding elements.
+//
+// Asm: VPMINUQ, CPU Feature: AVX512EVEX
+func (x Uint64x4) Min(y Uint64x4) Uint64x4
+
+// Min computes the minimum of corresponding elements.
+//
+// Asm: VPMINUQ, CPU Feature: AVX512EVEX
+func (x Uint64x8) Min(y Uint64x8) Uint64x8
+
+/* Mul */
+
+// Mul multiplies corresponding elements of two vectors.
+//
+// Asm: VMULPS, CPU Feature: AVX
+func (x Float32x4) Mul(y Float32x4) Float32x4
+
+// Mul multiplies corresponding elements of two vectors.
+//
+// Asm: VMULPS, CPU Feature: AVX
+func (x Float32x8) Mul(y Float32x8) Float32x8
+
+// Mul multiplies corresponding elements of two vectors, masked.
+//
+// Asm: VMULPS, CPU Feature: AVX512EVEX
+func (x Float32x16) Mul(y Float32x16) Float32x16
+
+// Mul multiplies corresponding elements of two vectors.
+//
+// Asm: VMULPD, CPU Feature: AVX
+func (x Float64x2) Mul(y Float64x2) Float64x2
+
+// Mul multiplies corresponding elements of two vectors.
+//
+// Asm: VMULPD, CPU Feature: AVX
+func (x Float64x4) Mul(y Float64x4) Float64x4
+
+// Mul multiplies corresponding elements of two vectors, masked.
+//
+// Asm: VMULPD, CPU Feature: AVX512EVEX
+func (x Float64x8) Mul(y Float64x8) Float64x8
+
+/* MulByPowOf2 */
+
+// MulByPowOf2 multiplies elements by a power of 2.
+//
+// Asm: VSCALEFPS, CPU Feature: AVX512EVEX
+func (x Float32x4) MulByPowOf2(y Float32x4) Float32x4
+
+// MulByPowOf2 multiplies elements by a power of 2.
+//
+// Asm: VSCALEFPS, CPU Feature: AVX512EVEX
+func (x Float32x8) MulByPowOf2(y Float32x8) Float32x8
+
+// MulByPowOf2 multiplies elements by a power of 2.
+//
+// Asm: VSCALEFPS, CPU Feature: AVX512EVEX
+func (x Float32x16) MulByPowOf2(y Float32x16) Float32x16
+
+// MulByPowOf2 multiplies elements by a power of 2.
+//
+// Asm: VSCALEFPD, CPU Feature: AVX512EVEX
+func (x Float64x2) MulByPowOf2(y Float64x2) Float64x2
+
+// MulByPowOf2 multiplies elements by a power of 2.
+//
+// Asm: VSCALEFPD, CPU Feature: AVX512EVEX
+func (x Float64x4) MulByPowOf2(y Float64x4) Float64x4
+
+// MulByPowOf2 multiplies elements by a power of 2.
+//
+// Asm: VSCALEFPD, CPU Feature: AVX512EVEX
+func (x Float64x8) MulByPowOf2(y Float64x8) Float64x8
+
+/* MulEvenWiden */
+
+// MulEvenWiden multiplies even-indexed elements, widening the result.
+// Result[i] = v1.Even[i] * v2.Even[i].
+//
+// Asm: VPMULDQ, CPU Feature: AVX
+func (x Int32x4) MulEvenWiden(y Int32x4) Int64x2
+
+// MulEvenWiden multiplies even-indexed elements, widening the result.
+// Result[i] = v1.Even[i] * v2.Even[i].
+//
+// Asm: VPMULDQ, CPU Feature: AVX2
+func (x Int32x8) MulEvenWiden(y Int32x8) Int64x4
+
+// MulEvenWiden multiplies even-indexed elements, widening the result, masked.
+// Result[i] = v1.Even[i] * v2.Even[i].
+//
+// Asm: VPMULDQ, CPU Feature: AVX512EVEX
+func (x Int64x2) MulEvenWiden(y Int64x2) Int64x2
+
+// MulEvenWiden multiplies even-indexed elements, widening the result, masked.
+// Result[i] = v1.Even[i] * v2.Even[i].
+//
+// Asm: VPMULDQ, CPU Feature: AVX512EVEX
+func (x Int64x4) MulEvenWiden(y Int64x4) Int64x4
+
+// MulEvenWiden multiplies even-indexed elements, widening the result, masked.
+// Result[i] = v1.Even[i] * v2.Even[i].
+//
+// Asm: VPMULDQ, CPU Feature: AVX512EVEX
+func (x Int64x8) MulEvenWiden(y Int64x8) Int64x8
+
+// MulEvenWiden multiplies even-indexed elements, widening the result.
+// Result[i] = v1.Even[i] * v2.Even[i].
+//
+// Asm: VPMULUDQ, CPU Feature: AVX
+func (x Uint32x4) MulEvenWiden(y Uint32x4) Uint64x2
+
+// MulEvenWiden multiplies even-indexed elements, widening the result.
+// Result[i] = v1.Even[i] * v2.Even[i].
+//
+// Asm: VPMULUDQ, CPU Feature: AVX2
+func (x Uint32x8) MulEvenWiden(y Uint32x8) Uint64x4
+
+// MulEvenWiden multiplies even-indexed elements, widening the result, masked.
+// Result[i] = v1.Even[i] * v2.Even[i].
+//
+// Asm: VPMULUDQ, CPU Feature: AVX512EVEX
+func (x Uint64x2) MulEvenWiden(y Uint64x2) Uint64x2
+
+// MulEvenWiden multiplies even-indexed elements, widening the result, masked.
+// Result[i] = v1.Even[i] * v2.Even[i].
+//
+// Asm: VPMULUDQ, CPU Feature: AVX512EVEX
+func (x Uint64x4) MulEvenWiden(y Uint64x4) Uint64x4
+
+// MulEvenWiden multiplies even-indexed elements, widening the result, masked.
+// Result[i] = v1.Even[i] * v2.Even[i].
+//
+// Asm: VPMULUDQ, CPU Feature: AVX512EVEX
+func (x Uint64x8) MulEvenWiden(y Uint64x8) Uint64x8
+
+/* MulHigh */
+
+// MulHigh multiplies elements and stores the high part of the result.
+//
+// Asm: VPMULHW, CPU Feature: AVX
+func (x Int16x8) MulHigh(y Int16x8) Int16x8
+
+// MulHigh multiplies elements and stores the high part of the result.
+//
+// Asm: VPMULHW, CPU Feature: AVX2
+func (x Int16x16) MulHigh(y Int16x16) Int16x16
+
+// MulHigh multiplies elements and stores the high part of the result, masked.
+//
+// Asm: VPMULHW, CPU Feature: AVX512EVEX
+func (x Int16x32) MulHigh(y Int16x32) Int16x32
+
+// MulHigh multiplies elements and stores the high part of the result.
+//
+// Asm: VPMULHUW, CPU Feature: AVX
+func (x Uint16x8) MulHigh(y Uint16x8) Uint16x8
+
+// MulHigh multiplies elements and stores the high part of the result.
+//
+// Asm: VPMULHUW, CPU Feature: AVX2
+func (x Uint16x16) MulHigh(y Uint16x16) Uint16x16
+
+// MulHigh multiplies elements and stores the high part of the result, masked.
+//
+// Asm: VPMULHUW, CPU Feature: AVX512EVEX
+func (x Uint16x32) MulHigh(y Uint16x32) Uint16x32
+
+/* MulLow */
+
+// MulLow multiplies elements and stores the low part of the result.
+//
+// Asm: VPMULLW, CPU Feature: AVX
+func (x Int16x8) MulLow(y Int16x8) Int16x8
+
+// MulLow multiplies elements and stores the low part of the result.
+//
+// Asm: VPMULLW, CPU Feature: AVX2
+func (x Int16x16) MulLow(y Int16x16) Int16x16
+
+// MulLow multiplies elements and stores the low part of the result, masked.
+//
+// Asm: VPMULLW, CPU Feature: AVX512EVEX
+func (x Int16x32) MulLow(y Int16x32) Int16x32
+
+// MulLow multiplies elements and stores the low part of the result.
+//
+// Asm: VPMULLD, CPU Feature: AVX
+func (x Int32x4) MulLow(y Int32x4) Int32x4
+
+// MulLow multiplies elements and stores the low part of the result.
+//
+// Asm: VPMULLD, CPU Feature: AVX2
+func (x Int32x8) MulLow(y Int32x8) Int32x8
+
+// MulLow multiplies elements and stores the low part of the result, masked.
+//
+// Asm: VPMULLD, CPU Feature: AVX512EVEX
+func (x Int32x16) MulLow(y Int32x16) Int32x16
+
+// MulLow multiplies elements and stores the low part of the result, masked.
+//
+// Asm: VPMULLQ, CPU Feature: AVX512EVEX
+func (x Int64x2) MulLow(y Int64x2) Int64x2
+
+// MulLow multiplies elements and stores the low part of the result, masked.
+//
+// Asm: VPMULLQ, CPU Feature: AVX512EVEX
+func (x Int64x4) MulLow(y Int64x4) Int64x4
+
+// MulLow multiplies elements and stores the low part of the result, masked.
+//
+// Asm: VPMULLQ, CPU Feature: AVX512EVEX
+func (x Int64x8) MulLow(y Int64x8) Int64x8
+
+/* NotEqual */
+
+// NotEqual compares for inequality.
+// Const Immediate = 4.
+//
+// Asm: VCMPPS, CPU Feature: AVX
+func (x Float32x4) NotEqual(y Float32x4) Mask32x4
+
+// NotEqual compares for inequality.
+// Const Immediate = 4.
+//
+// Asm: VCMPPS, CPU Feature: AVX
+func (x Float32x8) NotEqual(y Float32x8) Mask32x8
+
+// NotEqual compares for inequality.
+// Const Immediate = 4.
+//
+// Asm: VCMPPS, CPU Feature: AVX512EVEX
+func (x Float32x16) NotEqual(y Float32x16) Mask32x16
+
+// NotEqual compares for inequality.
+// Const Immediate = 4.
+//
+// Asm: VCMPPD, CPU Feature: AVX
+func (x Float64x2) NotEqual(y Float64x2) Mask64x2
+
+// NotEqual compares for inequality.
+// Const Immediate = 4.
+//
+// Asm: VCMPPD, CPU Feature: AVX
+func (x Float64x4) NotEqual(y Float64x4) Mask64x4
+
+// NotEqual compares for inequality.
+// Const Immediate = 4.
+//
+// Asm: VCMPPD, CPU Feature: AVX512EVEX
+func (x Float64x8) NotEqual(y Float64x8) Mask64x8
+
+// NotEqual compares for inequality.
+// Const Immediate = 4.
+//
+// Asm: VPCMPB, CPU Feature: AVX512EVEX
+func (x Int8x16) NotEqual(y Int8x16) Mask8x16
+
+// NotEqual compares for inequality.
+// Const Immediate = 4.
+//
+// Asm: VPCMPB, CPU Feature: AVX512EVEX
+func (x Int8x32) NotEqual(y Int8x32) Mask8x32
+
+// NotEqual compares for inequality.
+// Const Immediate = 4.
+//
+// Asm: VPCMPB, CPU Feature: AVX512EVEX
+func (x Int8x64) NotEqual(y Int8x64) Mask8x64
+
+// NotEqual compares for inequality.
+// Const Immediate = 4.
+//
+// Asm: VPCMPW, CPU Feature: AVX512EVEX
+func (x Int16x8) NotEqual(y Int16x8) Mask16x8
+
+// NotEqual compares for inequality.
+// Const Immediate = 4.
+//
+// Asm: VPCMPW, CPU Feature: AVX512EVEX
+func (x Int16x16) NotEqual(y Int16x16) Mask16x16
+
+// NotEqual compares for inequality.
+// Const Immediate = 4.
+//
+// Asm: VPCMPW, CPU Feature: AVX512EVEX
+func (x Int16x32) NotEqual(y Int16x32) Mask16x32
+
+// NotEqual compares for inequality.
+// Const Immediate = 4.
+//
+// Asm: VPCMPD, CPU Feature: AVX512EVEX
+func (x Int32x4) NotEqual(y Int32x4) Mask32x4
+
+// NotEqual compares for inequality.
+// Const Immediate = 4.
+//
+// Asm: VPCMPD, CPU Feature: AVX512EVEX
+func (x Int32x8) NotEqual(y Int32x8) Mask32x8
+
+// NotEqual compares for inequality.
+// Const Immediate = 4.
+//
+// Asm: VPCMPD, CPU Feature: AVX512EVEX
+func (x Int32x16) NotEqual(y Int32x16) Mask32x16
+
+// NotEqual compares for inequality.
+// Const Immediate = 4.
+//
+// Asm: VPCMPQ, CPU Feature: AVX512EVEX
+func (x Int64x2) NotEqual(y Int64x2) Mask64x2
+
+// NotEqual compares for inequality.
+// Const Immediate = 4.
+//
+// Asm: VPCMPQ, CPU Feature: AVX512EVEX
+func (x Int64x4) NotEqual(y Int64x4) Mask64x4
+
+// NotEqual compares for inequality.
+// Const Immediate = 4.
+//
+// Asm: VPCMPQ, CPU Feature: AVX512EVEX
+func (x Int64x8) NotEqual(y Int64x8) Mask64x8
+
+// NotEqual compares for inequality.
+// Const Immediate = 4.
+//
+// Asm: VPCMPUB, CPU Feature: AVX512EVEX
+func (x Uint8x16) NotEqual(y Uint8x16) Mask8x16
+
+// NotEqual compares for inequality.
+// Const Immediate = 4.
+//
+// Asm: VPCMPUB, CPU Feature: AVX512EVEX
+func (x Uint8x32) NotEqual(y Uint8x32) Mask8x32
+
+// NotEqual compares for inequality.
+// Const Immediate = 4.
+//
+// Asm: VPCMPUB, CPU Feature: AVX512EVEX
+func (x Uint8x64) NotEqual(y Uint8x64) Mask8x64
+
+// NotEqual compares for inequality.
+// Const Immediate = 4.
+//
+// Asm: VPCMPUW, CPU Feature: AVX512EVEX
+func (x Uint16x8) NotEqual(y Uint16x8) Mask16x8
+
+// NotEqual compares for inequality.
+// Const Immediate = 4.
+//
+// Asm: VPCMPUW, CPU Feature: AVX512EVEX
+func (x Uint16x16) NotEqual(y Uint16x16) Mask16x16
+
+// NotEqual compares for inequality.
+// Const Immediate = 4.
+//
+// Asm: VPCMPUW, CPU Feature: AVX512EVEX
+func (x Uint16x32) NotEqual(y Uint16x32) Mask16x32
+
+// NotEqual compares for inequality.
+// Const Immediate = 4.
+//
+// Asm: VPCMPUD, CPU Feature: AVX512EVEX
+func (x Uint32x4) NotEqual(y Uint32x4) Mask32x4
+
+// NotEqual compares for inequality.
+// Const Immediate = 4.
+//
+// Asm: VPCMPUD, CPU Feature: AVX512EVEX
+func (x Uint32x8) NotEqual(y Uint32x8) Mask32x8
+
+// NotEqual compares for inequality.
+// Const Immediate = 4.
+//
+// Asm: VPCMPUD, CPU Feature: AVX512EVEX
+func (x Uint32x16) NotEqual(y Uint32x16) Mask32x16
+
+// NotEqual compares for inequality.
+// Const Immediate = 4.
+//
+// Asm: VPCMPUQ, CPU Feature: AVX512EVEX
+func (x Uint64x2) NotEqual(y Uint64x2) Mask64x2
+
+// NotEqual compares for inequality.
+// Const Immediate = 4.
+//
+// Asm: VPCMPUQ, CPU Feature: AVX512EVEX
+func (x Uint64x4) NotEqual(y Uint64x4) Mask64x4
+
+// NotEqual compares for inequality.
+// Const Immediate = 4.
+//
+// Asm: VPCMPUQ, CPU Feature: AVX512EVEX
+func (x Uint64x8) NotEqual(y Uint64x8) Mask64x8
+
+/* Or */
+
+// Or performs a bitwise OR operation between two vectors.
+//
+// Asm: VORPS, CPU Feature: AVX
+func (x Float32x4) Or(y Float32x4) Float32x4
+
+// Or performs a bitwise OR operation between two vectors.
+//
+// Asm: VORPS, CPU Feature: AVX
+func (x Float32x8) Or(y Float32x8) Float32x8
+
+// Or performs a masked bitwise OR operation between two vectors.
+//
+// Asm: VORPS, CPU Feature: AVX512EVEX
+func (x Float32x16) Or(y Float32x16) Float32x16
+
+// Or performs a bitwise OR operation between two vectors.
+//
+// Asm: VORPD, CPU Feature: AVX
+func (x Float64x2) Or(y Float64x2) Float64x2
+
+// Or performs a bitwise OR operation between two vectors.
+//
+// Asm: VORPD, CPU Feature: AVX
+func (x Float64x4) Or(y Float64x4) Float64x4
+
+// Or performs a masked bitwise OR operation between two vectors.
+//
+// Asm: VORPD, CPU Feature: AVX512EVEX
+func (x Float64x8) Or(y Float64x8) Float64x8
+
+// Or performs a bitwise OR operation between two vectors.
+//
+// Asm: VPOR, CPU Feature: AVX
+func (x Int8x16) Or(y Int8x16) Int8x16
+
+// Or performs a bitwise OR operation between two vectors.
+//
+// Asm: VPOR, CPU Feature: AVX2
+func (x Int8x32) Or(y Int8x32) Int8x32
+
+// Or performs a bitwise OR operation between two vectors.
+//
+// Asm: VPOR, CPU Feature: AVX
+func (x Int16x8) Or(y Int16x8) Int16x8
+
+// Or performs a bitwise OR operation between two vectors.
+//
+// Asm: VPOR, CPU Feature: AVX2
+func (x Int16x16) Or(y Int16x16) Int16x16
+
+// Or performs a bitwise OR operation between two vectors.
+//
+// Asm: VPOR, CPU Feature: AVX
+func (x Int32x4) Or(y Int32x4) Int32x4
+
+// Or performs a bitwise OR operation between two vectors.
+//
+// Asm: VPOR, CPU Feature: AVX2
+func (x Int32x8) Or(y Int32x8) Int32x8
+
+// Or performs a masked bitwise OR operation between two vectors.
+//
+// Asm: VPORD, CPU Feature: AVX512EVEX
+func (x Int32x16) Or(y Int32x16) Int32x16
+
+// Or performs a bitwise OR operation between two vectors.
+//
+// Asm: VPOR, CPU Feature: AVX
+func (x Int64x2) Or(y Int64x2) Int64x2
+
+// Or performs a bitwise OR operation between two vectors.
+//
+// Asm: VPOR, CPU Feature: AVX2
+func (x Int64x4) Or(y Int64x4) Int64x4
+
+// Or performs a masked bitwise OR operation between two vectors.
+//
+// Asm: VPORQ, CPU Feature: AVX512EVEX
+func (x Int64x8) Or(y Int64x8) Int64x8
+
+// Or performs a bitwise OR operation between two vectors.
+//
+// Asm: VPOR, CPU Feature: AVX
+func (x Uint8x16) Or(y Uint8x16) Uint8x16
+
+// Or performs a bitwise OR operation between two vectors.
+//
+// Asm: VPOR, CPU Feature: AVX2
+func (x Uint8x32) Or(y Uint8x32) Uint8x32
+
+// Or performs a bitwise OR operation between two vectors.
+//
+// Asm: VPOR, CPU Feature: AVX
+func (x Uint16x8) Or(y Uint16x8) Uint16x8
+
+// Or performs a bitwise OR operation between two vectors.
+//
+// Asm: VPOR, CPU Feature: AVX2
+func (x Uint16x16) Or(y Uint16x16) Uint16x16
+
+// Or performs a bitwise OR operation between two vectors.
+//
+// Asm: VPOR, CPU Feature: AVX
+func (x Uint32x4) Or(y Uint32x4) Uint32x4
+
+// Or performs a bitwise OR operation between two vectors.
+//
+// Asm: VPOR, CPU Feature: AVX2
+func (x Uint32x8) Or(y Uint32x8) Uint32x8
+
+// Or performs a masked bitwise OR operation between two vectors.
+//
+// Asm: VPORD, CPU Feature: AVX512EVEX
+func (x Uint32x16) Or(y Uint32x16) Uint32x16
+
+// Or performs a bitwise OR operation between two vectors.
+//
+// Asm: VPOR, CPU Feature: AVX
+func (x Uint64x2) Or(y Uint64x2) Uint64x2
+
+// Or performs a bitwise OR operation between two vectors.
+//
+// Asm: VPOR, CPU Feature: AVX2
+func (x Uint64x4) Or(y Uint64x4) Uint64x4
+
+// Or performs a masked bitwise OR operation between two vectors.
+//
+// Asm: VPORQ, CPU Feature: AVX512EVEX
+func (x Uint64x8) Or(y Uint64x8) Uint64x8
+
+/* PairDotProd */
+
+// PairDotProd multiplies the elements and add the pairs together,
+// yielding a vector of half as many elements with twice the input element size.
+//
+// Asm: VPMADDWD, CPU Feature: AVX
+func (x Int16x8) PairDotProd(y Int16x8) Int32x4
+
+// PairDotProd multiplies the elements and add the pairs together,
+// yielding a vector of half as many elements with twice the input element size.
+//
+// Asm: VPMADDWD, CPU Feature: AVX2
+func (x Int16x16) PairDotProd(y Int16x16) Int32x8
+
+// PairDotProd multiplies the elements and add the pairs together,
+// yielding a vector of half as many elements with twice the input element size.
+//
+// Asm: VPMADDWD, CPU Feature: AVX512EVEX
+func (x Int16x32) PairDotProd(y Int16x32) Int32x16
+
+/* PairDotProdAccumulate */
+
+// PairDotProdAccumulate performs dot products on pairs of elements of y and z and accumulates the results to x.
+//
+// Asm: VPDPWSSD, CPU Feature: AVX_VNNI
+func (x Int32x4) PairDotProdAccumulate(y Int16x8, z Int16x8) Int32x4
+
+// PairDotProdAccumulate performs dot products on pairs of elements of y and z and accumulates the results to x.
+//
+// Asm: VPDPWSSD, CPU Feature: AVX_VNNI
+func (x Int32x8) PairDotProdAccumulate(y Int16x16, z Int16x16) Int32x8
+
+// PairDotProdAccumulate performs dot products on pairs of elements of y and z and accumulates the results to x.
+//
+// Asm: VPDPWSSD, CPU Feature: AVX512EVEX
+func (x Int32x16) PairDotProdAccumulate(y Int16x32, z Int16x32) Int32x16
+
+/* PairwiseAdd */
+
+// PairwiseAdd horizontally adds adjacent pairs of elements.
+// For x = [x0, x1, x2, x3, ...] and y = [y0, y1, y2, y3, ...], the result is [y0+y1, y2+y3, ..., x0+x1, x2+x3, ...].
+//
+// Asm: VHADDPS, CPU Feature: AVX
+func (x Float32x4) PairwiseAdd(y Float32x4) Float32x4
+
+// PairwiseAdd horizontally adds adjacent pairs of elements.
+// For x = [x0, x1, x2, x3, ...] and y = [y0, y1, y2, y3, ...], the result is [y0+y1, y2+y3, ..., x0+x1, x2+x3, ...].
+//
+// Asm: VHADDPS, CPU Feature: AVX
+func (x Float32x8) PairwiseAdd(y Float32x8) Float32x8
+
+// PairwiseAdd horizontally adds adjacent pairs of elements.
+// For x = [x0, x1, x2, x3, ...] and y = [y0, y1, y2, y3, ...], the result is [y0+y1, y2+y3, ..., x0+x1, x2+x3, ...].
+//
+// Asm: VHADDPD, CPU Feature: AVX
+func (x Float64x2) PairwiseAdd(y Float64x2) Float64x2
+
+// PairwiseAdd horizontally adds adjacent pairs of elements.
+// For x = [x0, x1, x2, x3, ...] and y = [y0, y1, y2, y3, ...], the result is [y0+y1, y2+y3, ..., x0+x1, x2+x3, ...].
+//
+// Asm: VHADDPD, CPU Feature: AVX
+func (x Float64x4) PairwiseAdd(y Float64x4) Float64x4
+
+// PairwiseAdd horizontally adds adjacent pairs of elements.
+// For x = [x0, x1, x2, x3, ...] and y = [y0, y1, y2, y3, ...], the result is [y0+y1, y2+y3, ..., x0+x1, x2+x3, ...].
+//
+// Asm: VPHADDW, CPU Feature: AVX
+func (x Int16x8) PairwiseAdd(y Int16x8) Int16x8
+
+// PairwiseAdd horizontally adds adjacent pairs of elements.
+// For x = [x0, x1, x2, x3, ...] and y = [y0, y1, y2, y3, ...], the result is [y0+y1, y2+y3, ..., x0+x1, x2+x3, ...].
+//
+// Asm: VPHADDW, CPU Feature: AVX2
+func (x Int16x16) PairwiseAdd(y Int16x16) Int16x16
+
+// PairwiseAdd horizontally adds adjacent pairs of elements.
+// For x = [x0, x1, x2, x3, ...] and y = [y0, y1, y2, y3, ...], the result is [y0+y1, y2+y3, ..., x0+x1, x2+x3, ...].
+//
+// Asm: VPHADDD, CPU Feature: AVX
+func (x Int32x4) PairwiseAdd(y Int32x4) Int32x4
+
+// PairwiseAdd horizontally adds adjacent pairs of elements.
+// For x = [x0, x1, x2, x3, ...] and y = [y0, y1, y2, y3, ...], the result is [y0+y1, y2+y3, ..., x0+x1, x2+x3, ...].
+//
+// Asm: VPHADDD, CPU Feature: AVX2
+func (x Int32x8) PairwiseAdd(y Int32x8) Int32x8
+
+// PairwiseAdd horizontally adds adjacent pairs of elements.
+// For x = [x0, x1, x2, x3, ...] and y = [y0, y1, y2, y3, ...], the result is [y0+y1, y2+y3, ..., x0+x1, x2+x3, ...].
+//
+// Asm: VPHADDW, CPU Feature: AVX
+func (x Uint16x8) PairwiseAdd(y Uint16x8) Uint16x8
+
+// PairwiseAdd horizontally adds adjacent pairs of elements.
+// For x = [x0, x1, x2, x3, ...] and y = [y0, y1, y2, y3, ...], the result is [y0+y1, y2+y3, ..., x0+x1, x2+x3, ...].
+//
+// Asm: VPHADDW, CPU Feature: AVX2
+func (x Uint16x16) PairwiseAdd(y Uint16x16) Uint16x16
+
+// PairwiseAdd horizontally adds adjacent pairs of elements.
+// For x = [x0, x1, x2, x3, ...] and y = [y0, y1, y2, y3, ...], the result is [y0+y1, y2+y3, ..., x0+x1, x2+x3, ...].
+//
+// Asm: VPHADDD, CPU Feature: AVX
+func (x Uint32x4) PairwiseAdd(y Uint32x4) Uint32x4
+
+// PairwiseAdd horizontally adds adjacent pairs of elements.
+// For x = [x0, x1, x2, x3, ...] and y = [y0, y1, y2, y3, ...], the result is [y0+y1, y2+y3, ..., x0+x1, x2+x3, ...].
+//
+// Asm: VPHADDD, CPU Feature: AVX2
+func (x Uint32x8) PairwiseAdd(y Uint32x8) Uint32x8
+
+/* PairwiseSub */
+
+// PairwiseSub horizontally subtracts adjacent pairs of elements.
+// For x = [x0, x1, x2, x3, ...] and y = [y0, y1, y2, y3, ...], the result is [y0-y1, y2-y3, ..., x0-x1, x2-x3, ...].
+//
+// Asm: VHSUBPS, CPU Feature: AVX
+func (x Float32x4) PairwiseSub(y Float32x4) Float32x4
+
+// PairwiseSub horizontally subtracts adjacent pairs of elements.
+// For x = [x0, x1, x2, x3, ...] and y = [y0, y1, y2, y3, ...], the result is [y0-y1, y2-y3, ..., x0-x1, x2-x3, ...].
+//
+// Asm: VHSUBPS, CPU Feature: AVX
+func (x Float32x8) PairwiseSub(y Float32x8) Float32x8
+
+// PairwiseSub horizontally subtracts adjacent pairs of elements.
+// For x = [x0, x1, x2, x3, ...] and y = [y0, y1, y2, y3, ...], the result is [y0-y1, y2-y3, ..., x0-x1, x2-x3, ...].
+//
+// Asm: VHSUBPD, CPU Feature: AVX
+func (x Float64x2) PairwiseSub(y Float64x2) Float64x2
+
+// PairwiseSub horizontally subtracts adjacent pairs of elements.
+// For x = [x0, x1, x2, x3, ...] and y = [y0, y1, y2, y3, ...], the result is [y0-y1, y2-y3, ..., x0-x1, x2-x3, ...].
+//
+// Asm: VHSUBPD, CPU Feature: AVX
+func (x Float64x4) PairwiseSub(y Float64x4) Float64x4
+
+// PairwiseSub horizontally subtracts adjacent pairs of elements.
+// For x = [x0, x1, x2, x3, ...] and y = [y0, y1, y2, y3, ...], the result is [y0-y1, y2-y3, ..., x0-x1, x2-x3, ...].
+//
+// Asm: VPHSUBW, CPU Feature: AVX
+func (x Int16x8) PairwiseSub(y Int16x8) Int16x8
+
+// PairwiseSub horizontally subtracts adjacent pairs of elements.
+// For x = [x0, x1, x2, x3, ...] and y = [y0, y1, y2, y3, ...], the result is [y0-y1, y2-y3, ..., x0-x1, x2-x3, ...].
+//
+// Asm: VPHSUBW, CPU Feature: AVX2
+func (x Int16x16) PairwiseSub(y Int16x16) Int16x16
+
+// PairwiseSub horizontally subtracts adjacent pairs of elements.
+// For x = [x0, x1, x2, x3, ...] and y = [y0, y1, y2, y3, ...], the result is [y0-y1, y2-y3, ..., x0-x1, x2-x3, ...].
+//
+// Asm: VPHSUBD, CPU Feature: AVX
+func (x Int32x4) PairwiseSub(y Int32x4) Int32x4
+
+// PairwiseSub horizontally subtracts adjacent pairs of elements.
+// For x = [x0, x1, x2, x3, ...] and y = [y0, y1, y2, y3, ...], the result is [y0-y1, y2-y3, ..., x0-x1, x2-x3, ...].
+//
+// Asm: VPHSUBD, CPU Feature: AVX2
+func (x Int32x8) PairwiseSub(y Int32x8) Int32x8
+
+// PairwiseSub horizontally subtracts adjacent pairs of elements.
+// For x = [x0, x1, x2, x3, ...] and y = [y0, y1, y2, y3, ...], the result is [y0-y1, y2-y3, ..., x0-x1, x2-x3, ...].
+//
+// Asm: VPHSUBW, CPU Feature: AVX
+func (x Uint16x8) PairwiseSub(y Uint16x8) Uint16x8
+
+// PairwiseSub horizontally subtracts adjacent pairs of elements.
+// For x = [x0, x1, x2, x3, ...] and y = [y0, y1, y2, y3, ...], the result is [y0-y1, y2-y3, ..., x0-x1, x2-x3, ...].
+//
+// Asm: VPHSUBW, CPU Feature: AVX2
+func (x Uint16x16) PairwiseSub(y Uint16x16) Uint16x16
+
+// PairwiseSub horizontally subtracts adjacent pairs of elements.
+// For x = [x0, x1, x2, x3, ...] and y = [y0, y1, y2, y3, ...], the result is [y0-y1, y2-y3, ..., x0-x1, x2-x3, ...].
+//
+// Asm: VPHSUBD, CPU Feature: AVX
+func (x Uint32x4) PairwiseSub(y Uint32x4) Uint32x4
+
+// PairwiseSub horizontally subtracts adjacent pairs of elements.
+// For x = [x0, x1, x2, x3, ...] and y = [y0, y1, y2, y3, ...], the result is [y0-y1, y2-y3, ..., x0-x1, x2-x3, ...].
+//
+// Asm: VPHSUBD, CPU Feature: AVX2
+func (x Uint32x8) PairwiseSub(y Uint32x8) Uint32x8
+
+/* PopCount */
+
+// PopCount counts the number of set bits in each element.
+//
+// Asm: VPOPCNTB, CPU Feature: AVX512EVEX
+func (x Int8x16) PopCount() Int8x16
+
+// PopCount counts the number of set bits in each element.
+//
+// Asm: VPOPCNTB, CPU Feature: AVX512EVEX
+func (x Int8x32) PopCount() Int8x32
+
+// PopCount counts the number of set bits in each element.
+//
+// Asm: VPOPCNTB, CPU Feature: AVX512EVEX
+func (x Int8x64) PopCount() Int8x64
+
+// PopCount counts the number of set bits in each element.
+//
+// Asm: VPOPCNTW, CPU Feature: AVX512EVEX
+func (x Int16x8) PopCount() Int16x8
+
+// PopCount counts the number of set bits in each element.
+//
+// Asm: VPOPCNTW, CPU Feature: AVX512EVEX
+func (x Int16x16) PopCount() Int16x16
+
+// PopCount counts the number of set bits in each element.
+//
+// Asm: VPOPCNTW, CPU Feature: AVX512EVEX
+func (x Int16x32) PopCount() Int16x32
+
+// PopCount counts the number of set bits in each element.
+//
+// Asm: VPOPCNTD, CPU Feature: AVX512EVEX
+func (x Int32x4) PopCount() Int32x4
+
+// PopCount counts the number of set bits in each element.
+//
+// Asm: VPOPCNTD, CPU Feature: AVX512EVEX
+func (x Int32x8) PopCount() Int32x8
+
+// PopCount counts the number of set bits in each element.
+//
+// Asm: VPOPCNTD, CPU Feature: AVX512EVEX
+func (x Int32x16) PopCount() Int32x16
+
+// PopCount counts the number of set bits in each element.
+//
+// Asm: VPOPCNTQ, CPU Feature: AVX512EVEX
+func (x Int64x2) PopCount() Int64x2
+
+// PopCount counts the number of set bits in each element.
+//
+// Asm: VPOPCNTQ, CPU Feature: AVX512EVEX
+func (x Int64x4) PopCount() Int64x4
+
+// PopCount counts the number of set bits in each element.
+//
+// Asm: VPOPCNTQ, CPU Feature: AVX512EVEX
+func (x Int64x8) PopCount() Int64x8
+
+// PopCount counts the number of set bits in each element.
+//
+// Asm: VPOPCNTB, CPU Feature: AVX512EVEX
+func (x Uint8x16) PopCount() Uint8x16
+
+// PopCount counts the number of set bits in each element.
+//
+// Asm: VPOPCNTB, CPU Feature: AVX512EVEX
+func (x Uint8x32) PopCount() Uint8x32
+
+// PopCount counts the number of set bits in each element.
+//
+// Asm: VPOPCNTB, CPU Feature: AVX512EVEX
+func (x Uint8x64) PopCount() Uint8x64
+
+// PopCount counts the number of set bits in each element.
+//
+// Asm: VPOPCNTW, CPU Feature: AVX512EVEX
+func (x Uint16x8) PopCount() Uint16x8
+
+// PopCount counts the number of set bits in each element.
+//
+// Asm: VPOPCNTW, CPU Feature: AVX512EVEX
+func (x Uint16x16) PopCount() Uint16x16
+
+// PopCount counts the number of set bits in each element.
+//
+// Asm: VPOPCNTW, CPU Feature: AVX512EVEX
+func (x Uint16x32) PopCount() Uint16x32
+
+// PopCount counts the number of set bits in each element.
+//
+// Asm: VPOPCNTD, CPU Feature: AVX512EVEX
+func (x Uint32x4) PopCount() Uint32x4
+
+// PopCount counts the number of set bits in each element.
+//
+// Asm: VPOPCNTD, CPU Feature: AVX512EVEX
+func (x Uint32x8) PopCount() Uint32x8
+
+// PopCount counts the number of set bits in each element.
+//
+// Asm: VPOPCNTD, CPU Feature: AVX512EVEX
+func (x Uint32x16) PopCount() Uint32x16
+
+// PopCount counts the number of set bits in each element.
+//
+// Asm: VPOPCNTQ, CPU Feature: AVX512EVEX
+func (x Uint64x2) PopCount() Uint64x2
+
+// PopCount counts the number of set bits in each element.
+//
+// Asm: VPOPCNTQ, CPU Feature: AVX512EVEX
+func (x Uint64x4) PopCount() Uint64x4
+
+// PopCount counts the number of set bits in each element.
+//
+// Asm: VPOPCNTQ, CPU Feature: AVX512EVEX
+func (x Uint64x8) PopCount() Uint64x8
+
+/* RotateAllLeft */
+
+// RotateAllLeft rotates each element to the left by the number of bits specified by the immediate.
+//
+// Asm: VPROLD, CPU Feature: AVX512EVEX
+func (x Int32x4) RotateAllLeft(imm8 uint8) Int32x4
+
+// RotateAllLeft rotates each element to the left by the number of bits specified by the immediate.
+//
+// Asm: VPROLD, CPU Feature: AVX512EVEX
+func (x Int32x8) RotateAllLeft(imm8 uint8) Int32x8
+
+// RotateAllLeft rotates each element to the left by the number of bits specified by the immediate.
+//
+// Asm: VPROLD, CPU Feature: AVX512EVEX
+func (x Int32x16) RotateAllLeft(imm8 uint8) Int32x16
+
+// RotateAllLeft rotates each element to the left by the number of bits specified by the immediate.
+//
+// Asm: VPROLQ, CPU Feature: AVX512EVEX
+func (x Int64x2) RotateAllLeft(imm8 uint8) Int64x2
+
+// RotateAllLeft rotates each element to the left by the number of bits specified by the immediate.
+//
+// Asm: VPROLQ, CPU Feature: AVX512EVEX
+func (x Int64x4) RotateAllLeft(imm8 uint8) Int64x4
+
+// RotateAllLeft rotates each element to the left by the number of bits specified by the immediate.
+//
+// Asm: VPROLQ, CPU Feature: AVX512EVEX
+func (x Int64x8) RotateAllLeft(imm8 uint8) Int64x8
+
+// RotateAllLeft rotates each element to the left by the number of bits specified by the immediate.
+//
+// Asm: VPROLD, CPU Feature: AVX512EVEX
+func (x Uint32x4) RotateAllLeft(imm8 uint8) Uint32x4
+
+// RotateAllLeft rotates each element to the left by the number of bits specified by the immediate.
+//
+// Asm: VPROLD, CPU Feature: AVX512EVEX
+func (x Uint32x8) RotateAllLeft(imm8 uint8) Uint32x8
+
+// RotateAllLeft rotates each element to the left by the number of bits specified by the immediate.
+//
+// Asm: VPROLD, CPU Feature: AVX512EVEX
+func (x Uint32x16) RotateAllLeft(imm8 uint8) Uint32x16
+
+// RotateAllLeft rotates each element to the left by the number of bits specified by the immediate.
+//
+// Asm: VPROLQ, CPU Feature: AVX512EVEX
+func (x Uint64x2) RotateAllLeft(imm8 uint8) Uint64x2
+
+// RotateAllLeft rotates each element to the left by the number of bits specified by the immediate.
+//
+// Asm: VPROLQ, CPU Feature: AVX512EVEX
+func (x Uint64x4) RotateAllLeft(imm8 uint8) Uint64x4
+
+// RotateAllLeft rotates each element to the left by the number of bits specified by the immediate.
+//
+// Asm: VPROLQ, CPU Feature: AVX512EVEX
+func (x Uint64x8) RotateAllLeft(imm8 uint8) Uint64x8
+
+/* RotateAllRight */
+
+// RotateAllRight rotates each element to the right by the number of bits specified by the immediate.
+//
+// Asm: VPRORD, CPU Feature: AVX512EVEX
+func (x Int32x4) RotateAllRight(imm8 uint8) Int32x4
+
+// RotateAllRight rotates each element to the right by the number of bits specified by the immediate.
+//
+// Asm: VPRORD, CPU Feature: AVX512EVEX
+func (x Int32x8) RotateAllRight(imm8 uint8) Int32x8
+
+// RotateAllRight rotates each element to the right by the number of bits specified by the immediate.
+//
+// Asm: VPRORD, CPU Feature: AVX512EVEX
+func (x Int32x16) RotateAllRight(imm8 uint8) Int32x16
+
+// RotateAllRight rotates each element to the right by the number of bits specified by the immediate.
+//
+// Asm: VPRORQ, CPU Feature: AVX512EVEX
+func (x Int64x2) RotateAllRight(imm8 uint8) Int64x2
+
+// RotateAllRight rotates each element to the right by the number of bits specified by the immediate.
+//
+// Asm: VPRORQ, CPU Feature: AVX512EVEX
+func (x Int64x4) RotateAllRight(imm8 uint8) Int64x4
+
+// RotateAllRight rotates each element to the right by the number of bits specified by the immediate.
+//
+// Asm: VPRORQ, CPU Feature: AVX512EVEX
+func (x Int64x8) RotateAllRight(imm8 uint8) Int64x8
+
+// RotateAllRight rotates each element to the right by the number of bits specified by the immediate.
+//
+// Asm: VPRORD, CPU Feature: AVX512EVEX
+func (x Uint32x4) RotateAllRight(imm8 uint8) Uint32x4
+
+// RotateAllRight rotates each element to the right by the number of bits specified by the immediate.
+//
+// Asm: VPRORD, CPU Feature: AVX512EVEX
+func (x Uint32x8) RotateAllRight(imm8 uint8) Uint32x8
+
+// RotateAllRight rotates each element to the right by the number of bits specified by the immediate.
+//
+// Asm: VPRORD, CPU Feature: AVX512EVEX
+func (x Uint32x16) RotateAllRight(imm8 uint8) Uint32x16
+
+// RotateAllRight rotates each element to the right by the number of bits specified by the immediate.
+//
+// Asm: VPRORQ, CPU Feature: AVX512EVEX
+func (x Uint64x2) RotateAllRight(imm8 uint8) Uint64x2
+
+// RotateAllRight rotates each element to the right by the number of bits specified by the immediate.
+//
+// Asm: VPRORQ, CPU Feature: AVX512EVEX
+func (x Uint64x4) RotateAllRight(imm8 uint8) Uint64x4
+
+// RotateAllRight rotates each element to the right by the number of bits specified by the immediate.
+//
+// Asm: VPRORQ, CPU Feature: AVX512EVEX
+func (x Uint64x8) RotateAllRight(imm8 uint8) Uint64x8
+
+/* RotateLeft */
+
+// RotateLeft rotates each element in x to the left by the number of bits specified by y's corresponding elements.
+//
+// Asm: VPROLVD, CPU Feature: AVX512EVEX
+func (x Int32x4) RotateLeft(y Int32x4) Int32x4
+
+// RotateLeft rotates each element in x to the left by the number of bits specified by y's corresponding elements.
+//
+// Asm: VPROLVD, CPU Feature: AVX512EVEX
+func (x Int32x8) RotateLeft(y Int32x8) Int32x8
+
+// RotateLeft rotates each element in x to the left by the number of bits specified by y's corresponding elements.
+//
+// Asm: VPROLVD, CPU Feature: AVX512EVEX
+func (x Int32x16) RotateLeft(y Int32x16) Int32x16
+
+// RotateLeft rotates each element in x to the left by the number of bits specified by y's corresponding elements.
+//
+// Asm: VPROLVQ, CPU Feature: AVX512EVEX
+func (x Int64x2) RotateLeft(y Int64x2) Int64x2
+
+// RotateLeft rotates each element in x to the left by the number of bits specified by y's corresponding elements.
+//
+// Asm: VPROLVQ, CPU Feature: AVX512EVEX
+func (x Int64x4) RotateLeft(y Int64x4) Int64x4
+
+// RotateLeft rotates each element in x to the left by the number of bits specified by y's corresponding elements.
+//
+// Asm: VPROLVQ, CPU Feature: AVX512EVEX
+func (x Int64x8) RotateLeft(y Int64x8) Int64x8
+
+// RotateLeft rotates each element in x to the left by the number of bits specified by y's corresponding elements.
+//
+// Asm: VPROLVD, CPU Feature: AVX512EVEX
+func (x Uint32x4) RotateLeft(y Uint32x4) Uint32x4
+
+// RotateLeft rotates each element in x to the left by the number of bits specified by y's corresponding elements.
+//
+// Asm: VPROLVD, CPU Feature: AVX512EVEX
+func (x Uint32x8) RotateLeft(y Uint32x8) Uint32x8
+
+// RotateLeft rotates each element in x to the left by the number of bits specified by y's corresponding elements.
+//
+// Asm: VPROLVD, CPU Feature: AVX512EVEX
+func (x Uint32x16) RotateLeft(y Uint32x16) Uint32x16
+
+// RotateLeft rotates each element in x to the left by the number of bits specified by y's corresponding elements.
+//
+// Asm: VPROLVQ, CPU Feature: AVX512EVEX
+func (x Uint64x2) RotateLeft(y Uint64x2) Uint64x2
+
+// RotateLeft rotates each element in x to the left by the number of bits specified by y's corresponding elements.
+//
+// Asm: VPROLVQ, CPU Feature: AVX512EVEX
+func (x Uint64x4) RotateLeft(y Uint64x4) Uint64x4
+
+// RotateLeft rotates each element in x to the left by the number of bits specified by y's corresponding elements.
+//
+// Asm: VPROLVQ, CPU Feature: AVX512EVEX
+func (x Uint64x8) RotateLeft(y Uint64x8) Uint64x8
+
+/* RotateRight */
+
+// RotateRight rotates each element in x to the right by the number of bits specified by y's corresponding elements.
+//
+// Asm: VPRORVD, CPU Feature: AVX512EVEX
+func (x Int32x4) RotateRight(y Int32x4) Int32x4
+
+// RotateRight rotates each element in x to the right by the number of bits specified by y's corresponding elements.
+//
+// Asm: VPRORVD, CPU Feature: AVX512EVEX
+func (x Int32x8) RotateRight(y Int32x8) Int32x8
+
+// RotateRight rotates each element in x to the right by the number of bits specified by y's corresponding elements.
+//
+// Asm: VPRORVD, CPU Feature: AVX512EVEX
+func (x Int32x16) RotateRight(y Int32x16) Int32x16
+
+// RotateRight rotates each element in x to the right by the number of bits specified by y's corresponding elements.
+//
+// Asm: VPRORVQ, CPU Feature: AVX512EVEX
+func (x Int64x2) RotateRight(y Int64x2) Int64x2
+
+// RotateRight rotates each element in x to the right by the number of bits specified by y's corresponding elements.
+//
+// Asm: VPRORVQ, CPU Feature: AVX512EVEX
+func (x Int64x4) RotateRight(y Int64x4) Int64x4
+
+// RotateRight rotates each element in x to the right by the number of bits specified by y's corresponding elements.
+//
+// Asm: VPRORVQ, CPU Feature: AVX512EVEX
+func (x Int64x8) RotateRight(y Int64x8) Int64x8
+
+// RotateRight rotates each element in x to the right by the number of bits specified by y's corresponding elements.
+//
+// Asm: VPRORVD, CPU Feature: AVX512EVEX
+func (x Uint32x4) RotateRight(y Uint32x4) Uint32x4
+
+// RotateRight rotates each element in x to the right by the number of bits specified by y's corresponding elements.
+//
+// Asm: VPRORVD, CPU Feature: AVX512EVEX
+func (x Uint32x8) RotateRight(y Uint32x8) Uint32x8
+
+// RotateRight rotates each element in x to the right by the number of bits specified by y's corresponding elements.
+//
+// Asm: VPRORVD, CPU Feature: AVX512EVEX
+func (x Uint32x16) RotateRight(y Uint32x16) Uint32x16
+
+// RotateRight rotates each element in x to the right by the number of bits specified by y's corresponding elements.
+//
+// Asm: VPRORVQ, CPU Feature: AVX512EVEX
+func (x Uint64x2) RotateRight(y Uint64x2) Uint64x2
+
+// RotateRight rotates each element in x to the right by the number of bits specified by y's corresponding elements.
+//
+// Asm: VPRORVQ, CPU Feature: AVX512EVEX
+func (x Uint64x4) RotateRight(y Uint64x4) Uint64x4
+
+// RotateRight rotates each element in x to the right by the number of bits specified by y's corresponding elements.
+//
+// Asm: VPRORVQ, CPU Feature: AVX512EVEX
+func (x Uint64x8) RotateRight(y Uint64x8) Uint64x8
+
+/* Round */
+
+// Round rounds elements to the nearest integer.
+// Const Immediate = 0.
+//
+// Asm: VROUNDPS, CPU Feature: AVX
+func (x Float32x4) Round() Float32x4
+
+// Round rounds elements to the nearest integer.
+// Const Immediate = 0.
+//
+// Asm: VROUNDPS, CPU Feature: AVX
+func (x Float32x8) Round() Float32x8
+
+// Round rounds elements to the nearest integer.
+// Const Immediate = 0.
+//
+// Asm: VROUNDPD, CPU Feature: AVX
+func (x Float64x2) Round() Float64x2
+
+// Round rounds elements to the nearest integer.
+// Const Immediate = 0.
+//
+// Asm: VROUNDPD, CPU Feature: AVX
+func (x Float64x4) Round() Float64x4
+
+/* RoundSuppressExceptionWithPrecision */
+
+// RoundSuppressExceptionWithPrecision rounds elements with specified precision, suppressing exceptions.
+// Const Immediate = 8.
+//
+// Asm: VRNDSCALEPS, CPU Feature: AVX512EVEX
+func (x Float32x4) RoundSuppressExceptionWithPrecision(imm8 uint8) Float32x4
+
+// RoundSuppressExceptionWithPrecision rounds elements with specified precision, suppressing exceptions.
+// Const Immediate = 8.
+//
+// Asm: VRNDSCALEPS, CPU Feature: AVX512EVEX
+func (x Float32x8) RoundSuppressExceptionWithPrecision(imm8 uint8) Float32x8
+
+// RoundSuppressExceptionWithPrecision rounds elements with specified precision, suppressing exceptions.
+// Const Immediate = 8.
+//
+// Asm: VRNDSCALEPS, CPU Feature: AVX512EVEX
+func (x Float32x16) RoundSuppressExceptionWithPrecision(imm8 uint8) Float32x16
+
+// RoundSuppressExceptionWithPrecision rounds elements with specified precision, suppressing exceptions.
+// Const Immediate = 8.
+//
+// Asm: VRNDSCALEPD, CPU Feature: AVX512EVEX
+func (x Float64x2) RoundSuppressExceptionWithPrecision(imm8 uint8) Float64x2
+
+// RoundSuppressExceptionWithPrecision rounds elements with specified precision, suppressing exceptions.
+// Const Immediate = 8.
+//
+// Asm: VRNDSCALEPD, CPU Feature: AVX512EVEX
+func (x Float64x4) RoundSuppressExceptionWithPrecision(imm8 uint8) Float64x4
+
+// RoundSuppressExceptionWithPrecision rounds elements with specified precision, suppressing exceptions.
+// Const Immediate = 8.
+//
+// Asm: VRNDSCALEPD, CPU Feature: AVX512EVEX
+func (x Float64x8) RoundSuppressExceptionWithPrecision(imm8 uint8) Float64x8
+
+/* RoundWithPrecision */
+
+// RoundWithPrecision rounds elements with specified precision.
+// Const Immediate = 0.
+//
+// Asm: VRNDSCALEPS, CPU Feature: AVX512EVEX
+func (x Float32x4) RoundWithPrecision(imm8 uint8) Float32x4
+
+// RoundWithPrecision rounds elements with specified precision.
+// Const Immediate = 0.
+//
+// Asm: VRNDSCALEPS, CPU Feature: AVX512EVEX
+func (x Float32x8) RoundWithPrecision(imm8 uint8) Float32x8
+
+// RoundWithPrecision rounds elements with specified precision.
+// Const Immediate = 0.
+//
+// Asm: VRNDSCALEPS, CPU Feature: AVX512EVEX
+func (x Float32x16) RoundWithPrecision(imm8 uint8) Float32x16
+
+// RoundWithPrecision rounds elements with specified precision.
+// Const Immediate = 0.
+//
+// Asm: VRNDSCALEPD, CPU Feature: AVX512EVEX
+func (x Float64x2) RoundWithPrecision(imm8 uint8) Float64x2
+
+// RoundWithPrecision rounds elements with specified precision.
+// Const Immediate = 0.
+//
+// Asm: VRNDSCALEPD, CPU Feature: AVX512EVEX
+func (x Float64x4) RoundWithPrecision(imm8 uint8) Float64x4
+
+// RoundWithPrecision rounds elements with specified precision.
+// Const Immediate = 0.
+//
+// Asm: VRNDSCALEPD, CPU Feature: AVX512EVEX
+func (x Float64x8) RoundWithPrecision(imm8 uint8) Float64x8
+
+/* SaturatedAdd */
+
+// SaturatedAdd adds corresponding elements of two vectors with saturation.
+//
+// Asm: VPADDSB, CPU Feature: AVX
+func (x Int8x16) SaturatedAdd(y Int8x16) Int8x16
+
+// SaturatedAdd adds corresponding elements of two vectors with saturation.
+//
+// Asm: VPADDSB, CPU Feature: AVX2
+func (x Int8x32) SaturatedAdd(y Int8x32) Int8x32
+
+// SaturatedAdd adds corresponding elements of two vectors with saturation.
+//
+// Asm: VPADDSB, CPU Feature: AVX512EVEX
+func (x Int8x64) SaturatedAdd(y Int8x64) Int8x64
+
+// SaturatedAdd adds corresponding elements of two vectors with saturation.
+//
+// Asm: VPADDSW, CPU Feature: AVX
+func (x Int16x8) SaturatedAdd(y Int16x8) Int16x8
+
+// SaturatedAdd adds corresponding elements of two vectors with saturation.
+//
+// Asm: VPADDSW, CPU Feature: AVX2
+func (x Int16x16) SaturatedAdd(y Int16x16) Int16x16
+
+// SaturatedAdd adds corresponding elements of two vectors with saturation.
+//
+// Asm: VPADDSW, CPU Feature: AVX512EVEX
+func (x Int16x32) SaturatedAdd(y Int16x32) Int16x32
+
+// SaturatedAdd adds corresponding elements of two vectors with saturation.
+//
+// Asm: VPADDSB, CPU Feature: AVX
+func (x Uint8x16) SaturatedAdd(y Uint8x16) Uint8x16
+
+// SaturatedAdd adds corresponding elements of two vectors with saturation.
+//
+// Asm: VPADDSB, CPU Feature: AVX2
+func (x Uint8x32) SaturatedAdd(y Uint8x32) Uint8x32
+
+// SaturatedAdd adds corresponding elements of two vectors with saturation.
+//
+// Asm: VPADDSB, CPU Feature: AVX512EVEX
+func (x Uint8x64) SaturatedAdd(y Uint8x64) Uint8x64
+
+// SaturatedAdd adds corresponding elements of two vectors with saturation.
+//
+// Asm: VPADDSW, CPU Feature: AVX
+func (x Uint16x8) SaturatedAdd(y Uint16x8) Uint16x8
+
+// SaturatedAdd adds corresponding elements of two vectors with saturation.
+//
+// Asm: VPADDSW, CPU Feature: AVX2
+func (x Uint16x16) SaturatedAdd(y Uint16x16) Uint16x16
+
+// SaturatedAdd adds corresponding elements of two vectors with saturation.
+//
+// Asm: VPADDSW, CPU Feature: AVX512EVEX
+func (x Uint16x32) SaturatedAdd(y Uint16x32) Uint16x32
+
+/* SaturatedPairDotProdAccumulate */
+
+// SaturatedPairDotProdAccumulate performs dot products on pairs of elements of y and z and accumulates the results to x.
+//
+// Asm: VPDPWSSDS, CPU Feature: AVX_VNNI
+func (x Int32x4) SaturatedPairDotProdAccumulate(y Int16x8, z Int16x8) Int32x4
+
+// SaturatedPairDotProdAccumulate performs dot products on pairs of elements of y and z and accumulates the results to x.
+//
+// Asm: VPDPWSSDS, CPU Feature: AVX_VNNI
+func (x Int32x8) SaturatedPairDotProdAccumulate(y Int16x16, z Int16x16) Int32x8
+
+// SaturatedPairDotProdAccumulate performs dot products on pairs of elements of y and z and accumulates the results to x.
+//
+// Asm: VPDPWSSDS, CPU Feature: AVX512EVEX
+func (x Int32x16) SaturatedPairDotProdAccumulate(y Int16x32, z Int16x32) Int32x16
+
+/* SaturatedPairwiseAdd */
+
+// SaturatedPairwiseAdd horizontally adds adjacent pairs of elements with saturation.
+// For x = [x0, x1, x2, x3, ...] and y = [y0, y1, y2, y3, ...], the result is [y0+y1, y2+y3, ..., x0+x1, x2+x3, ...].
+//
+// Asm: VPHADDSW, CPU Feature: AVX
+func (x Int16x8) SaturatedPairwiseAdd(y Int16x8) Int16x8
 
-// NotEqual compares for inequality.
-// Const Immediate = 4.
+// SaturatedPairwiseAdd horizontally adds adjacent pairs of elements with saturation.
+// For x = [x0, x1, x2, x3, ...] and y = [y0, y1, y2, y3, ...], the result is [y0+y1, y2+y3, ..., x0+x1, x2+x3, ...].
 //
-// Asm: VCMPPS, CPU Feature: AVX
-func (x Float32x4) NotEqual(y Float32x4) Mask32x4
+// Asm: VPHADDSW, CPU Feature: AVX2
+func (x Int16x16) SaturatedPairwiseAdd(y Int16x16) Int16x16
 
-// NotEqual compares for inequality.
-// Const Immediate = 4.
+/* SaturatedPairwiseSub */
+
+// SaturatedPairwiseSub horizontally subtracts adjacent pairs of elements with saturation.
+// For x = [x0, x1, x2, x3, ...] and y = [y0, y1, y2, y3, ...], the result is [y0-y1, y2-y3, ..., x0-x1, x2-x3, ...].
 //
-// Asm: VCMPPS, CPU Feature: AVX
-func (x Float32x8) NotEqual(y Float32x8) Mask32x8
+// Asm: VPHSUBSW, CPU Feature: AVX
+func (x Int16x8) SaturatedPairwiseSub(y Int16x8) Int16x8
 
-// NotEqual compares for inequality.
-// Const Immediate = 4.
+// SaturatedPairwiseSub horizontally subtracts adjacent pairs of elements with saturation.
+// For x = [x0, x1, x2, x3, ...] and y = [y0, y1, y2, y3, ...], the result is [y0-y1, y2-y3, ..., x0-x1, x2-x3, ...].
 //
-// Asm: VCMPPS, CPU Feature: AVX512EVEX
-func (x Float32x16) NotEqual(y Float32x16) Mask32x16
+// Asm: VPHSUBSW, CPU Feature: AVX2
+func (x Int16x16) SaturatedPairwiseSub(y Int16x16) Int16x16
 
-// NotEqual compares for inequality.
-// Const Immediate = 4.
+/* SaturatedSub */
+
+// SaturatedSub subtracts corresponding elements of two vectors with saturation.
 //
-// Asm: VCMPPD, CPU Feature: AVX
-func (x Float64x2) NotEqual(y Float64x2) Mask64x2
+// Asm: VPSUBSB, CPU Feature: AVX
+func (x Int8x16) SaturatedSub(y Int8x16) Int8x16
 
-// NotEqual compares for inequality.
-// Const Immediate = 4.
+// SaturatedSub subtracts corresponding elements of two vectors with saturation.
 //
-// Asm: VCMPPD, CPU Feature: AVX
-func (x Float64x4) NotEqual(y Float64x4) Mask64x4
+// Asm: VPSUBSB, CPU Feature: AVX2
+func (x Int8x32) SaturatedSub(y Int8x32) Int8x32
 
-// NotEqual compares for inequality.
-// Const Immediate = 4.
+// SaturatedSub subtracts corresponding elements of two vectors with saturation.
 //
-// Asm: VCMPPD, CPU Feature: AVX512EVEX
-func (x Float64x8) NotEqual(y Float64x8) Mask64x8
+// Asm: VPSUBSB, CPU Feature: AVX512EVEX
+func (x Int8x64) SaturatedSub(y Int8x64) Int8x64
 
-// NotEqual compares for inequality.
-// Const Immediate = 4.
+// SaturatedSub subtracts corresponding elements of two vectors with saturation.
 //
-// Asm: VPCMPB, CPU Feature: AVX512EVEX
-func (x Int8x16) NotEqual(y Int8x16) Mask8x16
+// Asm: VPSUBSW, CPU Feature: AVX
+func (x Int16x8) SaturatedSub(y Int16x8) Int16x8
 
-// NotEqual compares for inequality.
-// Const Immediate = 4.
+// SaturatedSub subtracts corresponding elements of two vectors with saturation.
 //
-// Asm: VPCMPB, CPU Feature: AVX512EVEX
-func (x Int8x32) NotEqual(y Int8x32) Mask8x32
+// Asm: VPSUBSW, CPU Feature: AVX2
+func (x Int16x16) SaturatedSub(y Int16x16) Int16x16
 
-// NotEqual compares for inequality.
-// Const Immediate = 4.
+// SaturatedSub subtracts corresponding elements of two vectors with saturation.
 //
-// Asm: VPCMPB, CPU Feature: AVX512EVEX
-func (x Int8x64) NotEqual(y Int8x64) Mask8x64
+// Asm: VPSUBSW, CPU Feature: AVX512EVEX
+func (x Int16x32) SaturatedSub(y Int16x32) Int16x32
 
-// NotEqual compares for inequality.
-// Const Immediate = 4.
+// SaturatedSub subtracts corresponding elements of two vectors with saturation.
 //
-// Asm: VPCMPW, CPU Feature: AVX512EVEX
-func (x Int16x8) NotEqual(y Int16x8) Mask16x8
+// Asm: VPSUBSB, CPU Feature: AVX
+func (x Uint8x16) SaturatedSub(y Uint8x16) Uint8x16
 
-// NotEqual compares for inequality.
-// Const Immediate = 4.
+// SaturatedSub subtracts corresponding elements of two vectors with saturation.
 //
-// Asm: VPCMPW, CPU Feature: AVX512EVEX
-func (x Int16x16) NotEqual(y Int16x16) Mask16x16
+// Asm: VPSUBSB, CPU Feature: AVX2
+func (x Uint8x32) SaturatedSub(y Uint8x32) Uint8x32
 
-// NotEqual compares for inequality.
-// Const Immediate = 4.
+// SaturatedSub subtracts corresponding elements of two vectors with saturation.
 //
-// Asm: VPCMPW, CPU Feature: AVX512EVEX
-func (x Int16x32) NotEqual(y Int16x32) Mask16x32
+// Asm: VPSUBSB, CPU Feature: AVX512EVEX
+func (x Uint8x64) SaturatedSub(y Uint8x64) Uint8x64
 
-// NotEqual compares for inequality.
-// Const Immediate = 4.
+// SaturatedSub subtracts corresponding elements of two vectors with saturation.
 //
-// Asm: VPCMPD, CPU Feature: AVX512EVEX
-func (x Int32x4) NotEqual(y Int32x4) Mask32x4
+// Asm: VPSUBSW, CPU Feature: AVX
+func (x Uint16x8) SaturatedSub(y Uint16x8) Uint16x8
 
-// NotEqual compares for inequality.
-// Const Immediate = 4.
+// SaturatedSub subtracts corresponding elements of two vectors with saturation.
 //
-// Asm: VPCMPD, CPU Feature: AVX512EVEX
-func (x Int32x8) NotEqual(y Int32x8) Mask32x8
+// Asm: VPSUBSW, CPU Feature: AVX2
+func (x Uint16x16) SaturatedSub(y Uint16x16) Uint16x16
 
-// NotEqual compares for inequality.
-// Const Immediate = 4.
+// SaturatedSub subtracts corresponding elements of two vectors with saturation.
 //
-// Asm: VPCMPD, CPU Feature: AVX512EVEX
-func (x Int32x16) NotEqual(y Int32x16) Mask32x16
+// Asm: VPSUBSW, CPU Feature: AVX512EVEX
+func (x Uint16x32) SaturatedSub(y Uint16x32) Uint16x32
 
-// NotEqual compares for inequality.
-// Const Immediate = 4.
+/* SaturatedUnsignedSignedPairDotProd */
+
+// SaturatedPairDotProd multiplies the elements and add the pairs together with saturation,
+// yielding a vector of half as many elements with twice the input element size.
 //
-// Asm: VPCMPQ, CPU Feature: AVX512EVEX
-func (x Int64x2) NotEqual(y Int64x2) Mask64x2
+// Asm: VPMADDUBSW, CPU Feature: AVX
+func (x Uint8x16) SaturatedUnsignedSignedPairDotProd(y Int8x16) Int16x8
 
-// NotEqual compares for inequality.
-// Const Immediate = 4.
+// SaturatedPairDotProd multiplies the elements and add the pairs together with saturation,
+// yielding a vector of half as many elements with twice the input element size.
 //
-// Asm: VPCMPQ, CPU Feature: AVX512EVEX
-func (x Int64x4) NotEqual(y Int64x4) Mask64x4
+// Asm: VPMADDUBSW, CPU Feature: AVX2
+func (x Uint8x32) SaturatedUnsignedSignedPairDotProd(y Int8x32) Int16x16
 
-// NotEqual compares for inequality.
-// Const Immediate = 4.
+// SaturatedPairDotProd multiplies the elements and add the pairs together with saturation,
+// yielding a vector of half as many elements with twice the input element size.
 //
-// Asm: VPCMPQ, CPU Feature: AVX512EVEX
-func (x Int64x8) NotEqual(y Int64x8) Mask64x8
+// Asm: VPMADDUBSW, CPU Feature: AVX512EVEX
+func (x Uint8x64) SaturatedUnsignedSignedPairDotProd(y Int8x64) Int16x32
 
-// NotEqual compares for inequality.
-// Const Immediate = 4.
+/* SaturatedUnsignedSignedQuadDotProdAccumulate */
+
+// SaturatedUnsignedSignedQuadDotProdAccumulate multiplies performs dot products on groups of 4 elements of y and z and accumulates the results to x.
 //
-// Asm: VPCMPUB, CPU Feature: AVX512EVEX
-func (x Uint8x16) NotEqual(y Uint8x16) Mask8x16
+// Asm: VPDPBUSDS, CPU Feature: AVX_VNNI
+func (x Int32x4) SaturatedUnsignedSignedQuadDotProdAccumulate(y Uint8x16, z Int8x16) Int32x4
 
-// NotEqual compares for inequality.
-// Const Immediate = 4.
+// SaturatedUnsignedSignedQuadDotProdAccumulate multiplies performs dot products on groups of 4 elements of y and z and accumulates the results to x.
 //
-// Asm: VPCMPUB, CPU Feature: AVX512EVEX
-func (x Uint8x32) NotEqual(y Uint8x32) Mask8x32
+// Asm: VPDPBUSDS, CPU Feature: AVX_VNNI
+func (x Int32x8) SaturatedUnsignedSignedQuadDotProdAccumulate(y Uint8x32, z Int8x32) Int32x8
 
-// NotEqual compares for inequality.
-// Const Immediate = 4.
+// SaturatedUnsignedSignedQuadDotProdAccumulate multiplies performs dot products on groups of 4 elements of y and z and accumulates the results to x.
 //
-// Asm: VPCMPUB, CPU Feature: AVX512EVEX
-func (x Uint8x64) NotEqual(y Uint8x64) Mask8x64
+// Asm: VPDPBUSDS, CPU Feature: AVX512EVEX
+func (x Int32x16) SaturatedUnsignedSignedQuadDotProdAccumulate(y Uint8x64, z Int8x64) Int32x16
 
-// NotEqual compares for inequality.
-// Const Immediate = 4.
+// SaturatedUnsignedSignedQuadDotProdAccumulate multiplies performs dot products on groups of 4 elements of y and z and accumulates the results to x.
 //
-// Asm: VPCMPUW, CPU Feature: AVX512EVEX
-func (x Uint16x8) NotEqual(y Uint16x8) Mask16x8
+// Asm: VPDPBUSDS, CPU Feature: AVX_VNNI
+func (x Uint32x4) SaturatedUnsignedSignedQuadDotProdAccumulate(y Uint8x16, z Int8x16) Uint32x4
 
-// NotEqual compares for inequality.
-// Const Immediate = 4.
+// SaturatedUnsignedSignedQuadDotProdAccumulate multiplies performs dot products on groups of 4 elements of y and z and accumulates the results to x.
 //
-// Asm: VPCMPUW, CPU Feature: AVX512EVEX
-func (x Uint16x16) NotEqual(y Uint16x16) Mask16x16
+// Asm: VPDPBUSDS, CPU Feature: AVX_VNNI
+func (x Uint32x8) SaturatedUnsignedSignedQuadDotProdAccumulate(y Uint8x32, z Int8x32) Uint32x8
 
-// NotEqual compares for inequality.
-// Const Immediate = 4.
+// SaturatedUnsignedSignedQuadDotProdAccumulate multiplies performs dot products on groups of 4 elements of y and z and accumulates the results to x.
 //
-// Asm: VPCMPUW, CPU Feature: AVX512EVEX
-func (x Uint16x32) NotEqual(y Uint16x32) Mask16x32
+// Asm: VPDPBUSDS, CPU Feature: AVX512EVEX
+func (x Uint32x16) SaturatedUnsignedSignedQuadDotProdAccumulate(y Uint8x64, z Int8x64) Uint32x16
 
-// NotEqual compares for inequality.
-// Const Immediate = 4.
+/* SetElem */
+
+// SetElem sets a single constant-indexed element's value.
 //
-// Asm: VPCMPUD, CPU Feature: AVX512EVEX
-func (x Uint32x4) NotEqual(y Uint32x4) Mask32x4
+// Asm: VPINSRB, CPU Feature: AVX
+func (x Int8x16) SetElem(imm uint8, y int8) Int8x16
 
-// NotEqual compares for inequality.
-// Const Immediate = 4.
+// SetElem sets a single constant-indexed element's value.
 //
-// Asm: VPCMPUD, CPU Feature: AVX512EVEX
-func (x Uint32x8) NotEqual(y Uint32x8) Mask32x8
+// Asm: VPINSRW, CPU Feature: AVX
+func (x Int16x8) SetElem(imm uint8, y int16) Int16x8
 
-// NotEqual compares for inequality.
-// Const Immediate = 4.
+// SetElem sets a single constant-indexed element's value.
 //
-// Asm: VPCMPUD, CPU Feature: AVX512EVEX
-func (x Uint32x16) NotEqual(y Uint32x16) Mask32x16
+// Asm: VPINSRD, CPU Feature: AVX
+func (x Int32x4) SetElem(imm uint8, y int32) Int32x4
 
-// NotEqual compares for inequality.
-// Const Immediate = 4.
+// SetElem sets a single constant-indexed element's value.
 //
-// Asm: VPCMPUQ, CPU Feature: AVX512EVEX
-func (x Uint64x2) NotEqual(y Uint64x2) Mask64x2
+// Asm: VPINSRQ, CPU Feature: AVX
+func (x Int64x2) SetElem(imm uint8, y int64) Int64x2
 
-// NotEqual compares for inequality.
-// Const Immediate = 4.
+// SetElem sets a single constant-indexed element's value.
 //
-// Asm: VPCMPUQ, CPU Feature: AVX512EVEX
-func (x Uint64x4) NotEqual(y Uint64x4) Mask64x4
+// Asm: VPINSRB, CPU Feature: AVX
+func (x Uint8x16) SetElem(imm uint8, y uint8) Uint8x16
 
-// NotEqual compares for inequality.
-// Const Immediate = 4.
+// SetElem sets a single constant-indexed element's value.
 //
-// Asm: VPCMPUQ, CPU Feature: AVX512EVEX
-func (x Uint64x8) NotEqual(y Uint64x8) Mask64x8
+// Asm: VPINSRW, CPU Feature: AVX
+func (x Uint16x8) SetElem(imm uint8, y uint16) Uint16x8
 
-/* Or */
+// SetElem sets a single constant-indexed element's value.
+//
+// Asm: VPINSRD, CPU Feature: AVX
+func (x Uint32x4) SetElem(imm uint8, y uint32) Uint32x4
 
-// Or performs a bitwise OR operation between two vectors.
+// SetElem sets a single constant-indexed element's value.
 //
-// Asm: VORPS, CPU Feature: AVX
-func (x Float32x4) Or(y Float32x4) Float32x4
+// Asm: VPINSRQ, CPU Feature: AVX
+func (x Uint64x2) SetElem(imm uint8, y uint64) Uint64x2
 
-// Or performs a bitwise OR operation between two vectors.
+/* ShiftAllLeft */
+
+// ShiftAllLeft shifts each element to the left by the specified number of bits. Emptied lower bits are zeroed.
 //
-// Asm: VORPS, CPU Feature: AVX
-func (x Float32x8) Or(y Float32x8) Float32x8
+// Asm: VPSLLW, CPU Feature: AVX
+func (x Int16x8) ShiftAllLeft(y uint64) Int16x8
 
-// Or performs a masked bitwise OR operation between two vectors.
+// ShiftAllLeft shifts each element to the left by the specified number of bits. Emptied lower bits are zeroed.
+//
+// Asm: VPSLLW, CPU Feature: AVX2
+func (x Int16x16) ShiftAllLeft(y uint64) Int16x16
+
+// ShiftAllLeft shifts each element to the left by the specified number of bits. Emptied lower bits are zeroed.
+//
+// Asm: VPSLLD, CPU Feature: AVX
+func (x Int32x4) ShiftAllLeft(y uint64) Int32x4
+
+// ShiftAllLeft shifts each element to the left by the specified number of bits. Emptied lower bits are zeroed.
+//
+// Asm: VPSLLD, CPU Feature: AVX2
+func (x Int32x8) ShiftAllLeft(y uint64) Int32x8
+
+// ShiftAllLeft shifts each element to the left by the specified number of bits. Emptied lower bits are zeroed.
+//
+// Asm: VPSLLQ, CPU Feature: AVX
+func (x Int64x2) ShiftAllLeft(y uint64) Int64x2
+
+// ShiftAllLeft shifts each element to the left by the specified number of bits. Emptied lower bits are zeroed.
+//
+// Asm: VPSLLQ, CPU Feature: AVX2
+func (x Int64x4) ShiftAllLeft(y uint64) Int64x4
+
+// ShiftAllLeft shifts each element to the left by the specified number of bits. Emptied lower bits are zeroed.
 //
-// Asm: VORPS, CPU Feature: AVX512EVEX
-func (x Float32x16) Or(y Float32x16) Float32x16
+// Asm: VPSLLQ, CPU Feature: AVX512EVEX
+func (x Int64x8) ShiftAllLeft(y uint64) Int64x8
 
-// Or performs a bitwise OR operation between two vectors.
+// ShiftAllLeft shifts each element to the left by the specified number of bits. Emptied lower bits are zeroed.
 //
-// Asm: VORPD, CPU Feature: AVX
-func (x Float64x2) Or(y Float64x2) Float64x2
+// Asm: VPSLLW, CPU Feature: AVX
+func (x Uint16x8) ShiftAllLeft(y uint64) Uint16x8
 
-// Or performs a bitwise OR operation between two vectors.
+// ShiftAllLeft shifts each element to the left by the specified number of bits. Emptied lower bits are zeroed.
 //
-// Asm: VORPD, CPU Feature: AVX
-func (x Float64x4) Or(y Float64x4) Float64x4
+// Asm: VPSLLW, CPU Feature: AVX2
+func (x Uint16x16) ShiftAllLeft(y uint64) Uint16x16
 
-// Or performs a masked bitwise OR operation between two vectors.
+// ShiftAllLeft shifts each element to the left by the specified number of bits. Emptied lower bits are zeroed.
 //
-// Asm: VORPD, CPU Feature: AVX512EVEX
-func (x Float64x8) Or(y Float64x8) Float64x8
+// Asm: VPSLLD, CPU Feature: AVX
+func (x Uint32x4) ShiftAllLeft(y uint64) Uint32x4
 
-// Or performs a bitwise OR operation between two vectors.
+// ShiftAllLeft shifts each element to the left by the specified number of bits. Emptied lower bits are zeroed.
 //
-// Asm: VPOR, CPU Feature: AVX
-func (x Int8x16) Or(y Int8x16) Int8x16
+// Asm: VPSLLD, CPU Feature: AVX2
+func (x Uint32x8) ShiftAllLeft(y uint64) Uint32x8
 
-// Or performs a bitwise OR operation between two vectors.
+// ShiftAllLeft shifts each element to the left by the specified number of bits. Emptied lower bits are zeroed.
 //
-// Asm: VPOR, CPU Feature: AVX2
-func (x Int8x32) Or(y Int8x32) Int8x32
+// Asm: VPSLLQ, CPU Feature: AVX
+func (x Uint64x2) ShiftAllLeft(y uint64) Uint64x2
 
-// Or performs a bitwise OR operation between two vectors.
+// ShiftAllLeft shifts each element to the left by the specified number of bits. Emptied lower bits are zeroed.
 //
-// Asm: VPOR, CPU Feature: AVX
-func (x Int16x8) Or(y Int16x8) Int16x8
+// Asm: VPSLLQ, CPU Feature: AVX2
+func (x Uint64x4) ShiftAllLeft(y uint64) Uint64x4
 
-// Or performs a bitwise OR operation between two vectors.
+// ShiftAllLeft shifts each element to the left by the specified number of bits. Emptied lower bits are zeroed.
 //
-// Asm: VPOR, CPU Feature: AVX2
-func (x Int16x16) Or(y Int16x16) Int16x16
+// Asm: VPSLLQ, CPU Feature: AVX512EVEX
+func (x Uint64x8) ShiftAllLeft(y uint64) Uint64x8
 
-// Or performs a bitwise OR operation between two vectors.
+/* ShiftAllLeftAndFillUpperFrom */
+
+// ShiftAllLeftAndFillUpperFrom shifts each element of x to the left by the number of bits specified by the
+// immediate(only the lower 5 bits are used), and then copies the upper bits of y to the emptied lower bits of the shifted x.
 //
-// Asm: VPOR, CPU Feature: AVX
-func (x Int32x4) Or(y Int32x4) Int32x4
+// Asm: VPSHLDW, CPU Feature: AVX512EVEX
+func (x Int16x8) ShiftAllLeftAndFillUpperFrom(imm uint8, y Int16x8) Int16x8
 
-// Or performs a bitwise OR operation between two vectors.
+// ShiftAllLeftAndFillUpperFrom shifts each element of x to the left by the number of bits specified by the
+// immediate(only the lower 5 bits are used), and then copies the upper bits of y to the emptied lower bits of the shifted x.
 //
-// Asm: VPOR, CPU Feature: AVX2
-func (x Int32x8) Or(y Int32x8) Int32x8
+// Asm: VPSHLDW, CPU Feature: AVX512EVEX
+func (x Int16x16) ShiftAllLeftAndFillUpperFrom(imm uint8, y Int16x16) Int16x16
 
-// Or performs a masked bitwise OR operation between two vectors.
+// ShiftAllLeftAndFillUpperFrom shifts each element of x to the left by the number of bits specified by the
+// immediate(only the lower 5 bits are used), and then copies the upper bits of y to the emptied lower bits of the shifted x.
 //
-// Asm: VPORD, CPU Feature: AVX512EVEX
-func (x Int32x16) Or(y Int32x16) Int32x16
+// Asm: VPSHLDW, CPU Feature: AVX512EVEX
+func (x Int16x32) ShiftAllLeftAndFillUpperFrom(imm uint8, y Int16x32) Int16x32
 
-// Or performs a bitwise OR operation between two vectors.
+// ShiftAllLeftAndFillUpperFrom shifts each element of x to the left by the number of bits specified by the
+// immediate(only the lower 5 bits are used), and then copies the upper bits of y to the emptied lower bits of the shifted x.
 //
-// Asm: VPOR, CPU Feature: AVX
-func (x Int64x2) Or(y Int64x2) Int64x2
+// Asm: VPSHLDD, CPU Feature: AVX512EVEX
+func (x Int32x4) ShiftAllLeftAndFillUpperFrom(imm uint8, y Int32x4) Int32x4
 
-// Or performs a bitwise OR operation between two vectors.
+// ShiftAllLeftAndFillUpperFrom shifts each element of x to the left by the number of bits specified by the
+// immediate(only the lower 5 bits are used), and then copies the upper bits of y to the emptied lower bits of the shifted x.
 //
-// Asm: VPOR, CPU Feature: AVX2
-func (x Int64x4) Or(y Int64x4) Int64x4
+// Asm: VPSHLDD, CPU Feature: AVX512EVEX
+func (x Int32x8) ShiftAllLeftAndFillUpperFrom(imm uint8, y Int32x8) Int32x8
 
-// Or performs a masked bitwise OR operation between two vectors.
+// ShiftAllLeftAndFillUpperFrom shifts each element of x to the left by the number of bits specified by the
+// immediate(only the lower 5 bits are used), and then copies the upper bits of y to the emptied lower bits of the shifted x.
 //
-// Asm: VPORQ, CPU Feature: AVX512EVEX
-func (x Int64x8) Or(y Int64x8) Int64x8
+// Asm: VPSHLDD, CPU Feature: AVX512EVEX
+func (x Int32x16) ShiftAllLeftAndFillUpperFrom(imm uint8, y Int32x16) Int32x16
 
-// Or performs a bitwise OR operation between two vectors.
+// ShiftAllLeftAndFillUpperFrom shifts each element of x to the left by the number of bits specified by the
+// immediate(only the lower 5 bits are used), and then copies the upper bits of y to the emptied lower bits of the shifted x.
 //
-// Asm: VPOR, CPU Feature: AVX
-func (x Uint8x16) Or(y Uint8x16) Uint8x16
+// Asm: VPSHLDQ, CPU Feature: AVX512EVEX
+func (x Int64x2) ShiftAllLeftAndFillUpperFrom(imm uint8, y Int64x2) Int64x2
 
-// Or performs a bitwise OR operation between two vectors.
+// ShiftAllLeftAndFillUpperFrom shifts each element of x to the left by the number of bits specified by the
+// immediate(only the lower 5 bits are used), and then copies the upper bits of y to the emptied lower bits of the shifted x.
 //
-// Asm: VPOR, CPU Feature: AVX2
-func (x Uint8x32) Or(y Uint8x32) Uint8x32
+// Asm: VPSHLDQ, CPU Feature: AVX512EVEX
+func (x Int64x4) ShiftAllLeftAndFillUpperFrom(imm uint8, y Int64x4) Int64x4
 
-// Or performs a bitwise OR operation between two vectors.
+// ShiftAllLeftAndFillUpperFrom shifts each element of x to the left by the number of bits specified by the
+// immediate(only the lower 5 bits are used), and then copies the upper bits of y to the emptied lower bits of the shifted x.
 //
-// Asm: VPOR, CPU Feature: AVX
-func (x Uint16x8) Or(y Uint16x8) Uint16x8
+// Asm: VPSHLDQ, CPU Feature: AVX512EVEX
+func (x Int64x8) ShiftAllLeftAndFillUpperFrom(imm uint8, y Int64x8) Int64x8
 
-// Or performs a bitwise OR operation between two vectors.
+// ShiftAllLeftAndFillUpperFrom shifts each element of x to the left by the number of bits specified by the
+// immediate(only the lower 5 bits are used), and then copies the upper bits of y to the emptied lower bits of the shifted x.
 //
-// Asm: VPOR, CPU Feature: AVX2
-func (x Uint16x16) Or(y Uint16x16) Uint16x16
+// Asm: VPSHLDW, CPU Feature: AVX512EVEX
+func (x Uint16x8) ShiftAllLeftAndFillUpperFrom(imm uint8, y Uint16x8) Uint16x8
 
-// Or performs a bitwise OR operation between two vectors.
+// ShiftAllLeftAndFillUpperFrom shifts each element of x to the left by the number of bits specified by the
+// immediate(only the lower 5 bits are used), and then copies the upper bits of y to the emptied lower bits of the shifted x.
 //
-// Asm: VPOR, CPU Feature: AVX
-func (x Uint32x4) Or(y Uint32x4) Uint32x4
+// Asm: VPSHLDW, CPU Feature: AVX512EVEX
+func (x Uint16x16) ShiftAllLeftAndFillUpperFrom(imm uint8, y Uint16x16) Uint16x16
 
-// Or performs a bitwise OR operation between two vectors.
+// ShiftAllLeftAndFillUpperFrom shifts each element of x to the left by the number of bits specified by the
+// immediate(only the lower 5 bits are used), and then copies the upper bits of y to the emptied lower bits of the shifted x.
 //
-// Asm: VPOR, CPU Feature: AVX2
-func (x Uint32x8) Or(y Uint32x8) Uint32x8
+// Asm: VPSHLDW, CPU Feature: AVX512EVEX
+func (x Uint16x32) ShiftAllLeftAndFillUpperFrom(imm uint8, y Uint16x32) Uint16x32
 
-// Or performs a masked bitwise OR operation between two vectors.
+// ShiftAllLeftAndFillUpperFrom shifts each element of x to the left by the number of bits specified by the
+// immediate(only the lower 5 bits are used), and then copies the upper bits of y to the emptied lower bits of the shifted x.
 //
-// Asm: VPORD, CPU Feature: AVX512EVEX
-func (x Uint32x16) Or(y Uint32x16) Uint32x16
+// Asm: VPSHLDD, CPU Feature: AVX512EVEX
+func (x Uint32x4) ShiftAllLeftAndFillUpperFrom(imm uint8, y Uint32x4) Uint32x4
 
-// Or performs a bitwise OR operation between two vectors.
+// ShiftAllLeftAndFillUpperFrom shifts each element of x to the left by the number of bits specified by the
+// immediate(only the lower 5 bits are used), and then copies the upper bits of y to the emptied lower bits of the shifted x.
 //
-// Asm: VPOR, CPU Feature: AVX
-func (x Uint64x2) Or(y Uint64x2) Uint64x2
+// Asm: VPSHLDD, CPU Feature: AVX512EVEX
+func (x Uint32x8) ShiftAllLeftAndFillUpperFrom(imm uint8, y Uint32x8) Uint32x8
 
-// Or performs a bitwise OR operation between two vectors.
+// ShiftAllLeftAndFillUpperFrom shifts each element of x to the left by the number of bits specified by the
+// immediate(only the lower 5 bits are used), and then copies the upper bits of y to the emptied lower bits of the shifted x.
 //
-// Asm: VPOR, CPU Feature: AVX2
-func (x Uint64x4) Or(y Uint64x4) Uint64x4
+// Asm: VPSHLDD, CPU Feature: AVX512EVEX
+func (x Uint32x16) ShiftAllLeftAndFillUpperFrom(imm uint8, y Uint32x16) Uint32x16
 
-// Or performs a masked bitwise OR operation between two vectors.
+// ShiftAllLeftAndFillUpperFrom shifts each element of x to the left by the number of bits specified by the
+// immediate(only the lower 5 bits are used), and then copies the upper bits of y to the emptied lower bits of the shifted x.
 //
-// Asm: VPORQ, CPU Feature: AVX512EVEX
-func (x Uint64x8) Or(y Uint64x8) Uint64x8
+// Asm: VPSHLDQ, CPU Feature: AVX512EVEX
+func (x Uint64x2) ShiftAllLeftAndFillUpperFrom(imm uint8, y Uint64x2) Uint64x2
 
-/* PairDotProd */
+// ShiftAllLeftAndFillUpperFrom shifts each element of x to the left by the number of bits specified by the
+// immediate(only the lower 5 bits are used), and then copies the upper bits of y to the emptied lower bits of the shifted x.
+//
+// Asm: VPSHLDQ, CPU Feature: AVX512EVEX
+func (x Uint64x4) ShiftAllLeftAndFillUpperFrom(imm uint8, y Uint64x4) Uint64x4
 
-// PairDotProd multiplies the elements and add the pairs together,
-// yielding a vector of half as many elements with twice the input element size.
+// ShiftAllLeftAndFillUpperFrom shifts each element of x to the left by the number of bits specified by the
+// immediate(only the lower 5 bits are used), and then copies the upper bits of y to the emptied lower bits of the shifted x.
 //
-// Asm: VPMADDWD, CPU Feature: AVX
-func (x Int16x8) PairDotProd(y Int16x8) Int32x4
+// Asm: VPSHLDQ, CPU Feature: AVX512EVEX
+func (x Uint64x8) ShiftAllLeftAndFillUpperFrom(imm uint8, y Uint64x8) Uint64x8
 
-// PairDotProd multiplies the elements and add the pairs together,
-// yielding a vector of half as many elements with twice the input element size.
+/* ShiftAllRight */
+
+// ShiftAllRight shifts each element to the right by the specified number of bits. Emptied upper bits are zeroed.
 //
-// Asm: VPMADDWD, CPU Feature: AVX2
-func (x Int16x16) PairDotProd(y Int16x16) Int32x8
+// Asm: VPSRLW, CPU Feature: AVX
+func (x Int16x8) ShiftAllRight(y uint64) Int16x8
 
-// PairDotProd multiplies the elements and add the pairs together,
-// yielding a vector of half as many elements with twice the input element size.
+// ShiftAllRight shifts each element to the right by the specified number of bits. Emptied upper bits are zeroed.
 //
-// Asm: VPMADDWD, CPU Feature: AVX512EVEX
-func (x Int16x32) PairDotProd(y Int16x32) Int32x16
+// Asm: VPSRLW, CPU Feature: AVX2
+func (x Int16x16) ShiftAllRight(y uint64) Int16x16
 
-/* PairDotProdAccumulate */
+// ShiftAllRight shifts each element to the right by the specified number of bits. Emptied upper bits are zeroed.
+//
+// Asm: VPSRLD, CPU Feature: AVX
+func (x Int32x4) ShiftAllRight(y uint64) Int32x4
 
-// PairDotProdAccumulate performs dot products on pairs of elements of y and z and accumulates the results to x.
+// ShiftAllRight shifts each element to the right by the specified number of bits. Emptied upper bits are zeroed.
 //
-// Asm: VPDPWSSD, CPU Feature: AVX_VNNI
-func (x Int32x4) PairDotProdAccumulate(y Int16x8, z Int16x8) Int32x4
+// Asm: VPSRLD, CPU Feature: AVX2
+func (x Int32x8) ShiftAllRight(y uint64) Int32x8
 
-// PairDotProdAccumulate performs dot products on pairs of elements of y and z and accumulates the results to x.
+// ShiftAllRight shifts each element to the right by the specified number of bits. Emptied upper bits are zeroed.
 //
-// Asm: VPDPWSSD, CPU Feature: AVX_VNNI
-func (x Int32x8) PairDotProdAccumulate(y Int16x16, z Int16x16) Int32x8
+// Asm: VPSRLQ, CPU Feature: AVX
+func (x Int64x2) ShiftAllRight(y uint64) Int64x2
 
-// PairDotProdAccumulate performs dot products on pairs of elements of y and z and accumulates the results to x.
+// ShiftAllRight shifts each element to the right by the specified number of bits. Emptied upper bits are zeroed.
 //
-// Asm: VPDPWSSD, CPU Feature: AVX512EVEX
-func (x Int32x16) PairDotProdAccumulate(y Int16x32, z Int16x32) Int32x16
+// Asm: VPSRLQ, CPU Feature: AVX2
+func (x Int64x4) ShiftAllRight(y uint64) Int64x4
 
-/* PairwiseAdd */
+// ShiftAllRight shifts each element to the right by the specified number of bits. Emptied upper bits are zeroed.
+//
+// Asm: VPSRLQ, CPU Feature: AVX512EVEX
+func (x Int64x8) ShiftAllRight(y uint64) Int64x8
 
-// PairwiseAdd horizontally adds adjacent pairs of elements.
-// For x = [x0, x1, x2, x3, ...] and y = [y0, y1, y2, y3, ...], the result is [y0+y1, y2+y3, ..., x0+x1, x2+x3, ...].
+// ShiftAllRight shifts each element to the right by the specified number of bits. Emptied upper bits are zeroed.
 //
-// Asm: VHADDPS, CPU Feature: AVX
-func (x Float32x4) PairwiseAdd(y Float32x4) Float32x4
+// Asm: VPSRLW, CPU Feature: AVX
+func (x Uint16x8) ShiftAllRight(y uint64) Uint16x8
 
-// PairwiseAdd horizontally adds adjacent pairs of elements.
-// For x = [x0, x1, x2, x3, ...] and y = [y0, y1, y2, y3, ...], the result is [y0+y1, y2+y3, ..., x0+x1, x2+x3, ...].
+// ShiftAllRight shifts each element to the right by the specified number of bits. Emptied upper bits are zeroed.
 //
-// Asm: VHADDPS, CPU Feature: AVX
-func (x Float32x8) PairwiseAdd(y Float32x8) Float32x8
+// Asm: VPSRLW, CPU Feature: AVX2
+func (x Uint16x16) ShiftAllRight(y uint64) Uint16x16
 
-// PairwiseAdd horizontally adds adjacent pairs of elements.
-// For x = [x0, x1, x2, x3, ...] and y = [y0, y1, y2, y3, ...], the result is [y0+y1, y2+y3, ..., x0+x1, x2+x3, ...].
+// ShiftAllRight shifts each element to the right by the specified number of bits. Emptied upper bits are zeroed.
 //
-// Asm: VHADDPD, CPU Feature: AVX
-func (x Float64x2) PairwiseAdd(y Float64x2) Float64x2
+// Asm: VPSRLD, CPU Feature: AVX
+func (x Uint32x4) ShiftAllRight(y uint64) Uint32x4
 
-// PairwiseAdd horizontally adds adjacent pairs of elements.
-// For x = [x0, x1, x2, x3, ...] and y = [y0, y1, y2, y3, ...], the result is [y0+y1, y2+y3, ..., x0+x1, x2+x3, ...].
+// ShiftAllRight shifts each element to the right by the specified number of bits. Emptied upper bits are zeroed.
 //
-// Asm: VHADDPD, CPU Feature: AVX
-func (x Float64x4) PairwiseAdd(y Float64x4) Float64x4
+// Asm: VPSRLD, CPU Feature: AVX2
+func (x Uint32x8) ShiftAllRight(y uint64) Uint32x8
 
-// PairwiseAdd horizontally adds adjacent pairs of elements.
-// For x = [x0, x1, x2, x3, ...] and y = [y0, y1, y2, y3, ...], the result is [y0+y1, y2+y3, ..., x0+x1, x2+x3, ...].
+// ShiftAllRight shifts each element to the right by the specified number of bits. Emptied upper bits are zeroed.
 //
-// Asm: VPHADDW, CPU Feature: AVX
-func (x Int16x8) PairwiseAdd(y Int16x8) Int16x8
+// Asm: VPSRLQ, CPU Feature: AVX
+func (x Uint64x2) ShiftAllRight(y uint64) Uint64x2
 
-// PairwiseAdd horizontally adds adjacent pairs of elements.
-// For x = [x0, x1, x2, x3, ...] and y = [y0, y1, y2, y3, ...], the result is [y0+y1, y2+y3, ..., x0+x1, x2+x3, ...].
+// ShiftAllRight shifts each element to the right by the specified number of bits. Emptied upper bits are zeroed.
 //
-// Asm: VPHADDW, CPU Feature: AVX2
-func (x Int16x16) PairwiseAdd(y Int16x16) Int16x16
+// Asm: VPSRLQ, CPU Feature: AVX2
+func (x Uint64x4) ShiftAllRight(y uint64) Uint64x4
 
-// PairwiseAdd horizontally adds adjacent pairs of elements.
-// For x = [x0, x1, x2, x3, ...] and y = [y0, y1, y2, y3, ...], the result is [y0+y1, y2+y3, ..., x0+x1, x2+x3, ...].
+// ShiftAllRight shifts each element to the right by the specified number of bits. Emptied upper bits are zeroed.
 //
-// Asm: VPHADDD, CPU Feature: AVX
-func (x Int32x4) PairwiseAdd(y Int32x4) Int32x4
+// Asm: VPSRLQ, CPU Feature: AVX512EVEX
+func (x Uint64x8) ShiftAllRight(y uint64) Uint64x8
 
-// PairwiseAdd horizontally adds adjacent pairs of elements.
-// For x = [x0, x1, x2, x3, ...] and y = [y0, y1, y2, y3, ...], the result is [y0+y1, y2+y3, ..., x0+x1, x2+x3, ...].
+/* ShiftAllRightAndFillUpperFrom */
+
+// ShiftAllRightAndFillUpperFrom shifts each element of x to the right by the number of bits specified by the
+// immediate(only the lower 5 bits are used), and then copies the lower bits of y to the emptied upper bits of the shifted x.
 //
-// Asm: VPHADDD, CPU Feature: AVX2
-func (x Int32x8) PairwiseAdd(y Int32x8) Int32x8
+// Asm: VPSHRDW, CPU Feature: AVX512EVEX
+func (x Int16x8) ShiftAllRightAndFillUpperFrom(imm uint8, y Int16x8) Int16x8
 
-// PairwiseAdd horizontally adds adjacent pairs of elements.
-// For x = [x0, x1, x2, x3, ...] and y = [y0, y1, y2, y3, ...], the result is [y0+y1, y2+y3, ..., x0+x1, x2+x3, ...].
+// ShiftAllRightAndFillUpperFrom shifts each element of x to the right by the number of bits specified by the
+// immediate(only the lower 5 bits are used), and then copies the lower bits of y to the emptied upper bits of the shifted x.
 //
-// Asm: VPHADDW, CPU Feature: AVX
-func (x Uint16x8) PairwiseAdd(y Uint16x8) Uint16x8
+// Asm: VPSHRDW, CPU Feature: AVX512EVEX
+func (x Int16x16) ShiftAllRightAndFillUpperFrom(imm uint8, y Int16x16) Int16x16
 
-// PairwiseAdd horizontally adds adjacent pairs of elements.
-// For x = [x0, x1, x2, x3, ...] and y = [y0, y1, y2, y3, ...], the result is [y0+y1, y2+y3, ..., x0+x1, x2+x3, ...].
+// ShiftAllRightAndFillUpperFrom shifts each element of x to the right by the number of bits specified by the
+// immediate(only the lower 5 bits are used), and then copies the lower bits of y to the emptied upper bits of the shifted x.
 //
-// Asm: VPHADDW, CPU Feature: AVX2
-func (x Uint16x16) PairwiseAdd(y Uint16x16) Uint16x16
+// Asm: VPSHRDW, CPU Feature: AVX512EVEX
+func (x Int16x32) ShiftAllRightAndFillUpperFrom(imm uint8, y Int16x32) Int16x32
 
-// PairwiseAdd horizontally adds adjacent pairs of elements.
-// For x = [x0, x1, x2, x3, ...] and y = [y0, y1, y2, y3, ...], the result is [y0+y1, y2+y3, ..., x0+x1, x2+x3, ...].
+// ShiftAllRightAndFillUpperFrom shifts each element of x to the right by the number of bits specified by the
+// immediate(only the lower 5 bits are used), and then copies the lower bits of y to the emptied upper bits of the shifted x.
 //
-// Asm: VPHADDD, CPU Feature: AVX
-func (x Uint32x4) PairwiseAdd(y Uint32x4) Uint32x4
+// Asm: VPSHRDD, CPU Feature: AVX512EVEX
+func (x Int32x4) ShiftAllRightAndFillUpperFrom(imm uint8, y Int32x4) Int32x4
 
-// PairwiseAdd horizontally adds adjacent pairs of elements.
-// For x = [x0, x1, x2, x3, ...] and y = [y0, y1, y2, y3, ...], the result is [y0+y1, y2+y3, ..., x0+x1, x2+x3, ...].
+// ShiftAllRightAndFillUpperFrom shifts each element of x to the right by the number of bits specified by the
+// immediate(only the lower 5 bits are used), and then copies the lower bits of y to the emptied upper bits of the shifted x.
 //
-// Asm: VPHADDD, CPU Feature: AVX2
-func (x Uint32x8) PairwiseAdd(y Uint32x8) Uint32x8
+// Asm: VPSHRDD, CPU Feature: AVX512EVEX
+func (x Int32x8) ShiftAllRightAndFillUpperFrom(imm uint8, y Int32x8) Int32x8
 
-/* PairwiseSub */
+// ShiftAllRightAndFillUpperFrom shifts each element of x to the right by the number of bits specified by the
+// immediate(only the lower 5 bits are used), and then copies the lower bits of y to the emptied upper bits of the shifted x.
+//
+// Asm: VPSHRDD, CPU Feature: AVX512EVEX
+func (x Int32x16) ShiftAllRightAndFillUpperFrom(imm uint8, y Int32x16) Int32x16
 
-// PairwiseSub horizontally subtracts adjacent pairs of elements.
-// For x = [x0, x1, x2, x3, ...] and y = [y0, y1, y2, y3, ...], the result is [y0-y1, y2-y3, ..., x0-x1, x2-x3, ...].
+// ShiftAllRightAndFillUpperFrom shifts each element of x to the right by the number of bits specified by the
+// immediate(only the lower 5 bits are used), and then copies the lower bits of y to the emptied upper bits of the shifted x.
 //
-// Asm: VHSUBPS, CPU Feature: AVX
-func (x Float32x4) PairwiseSub(y Float32x4) Float32x4
+// Asm: VPSHRDQ, CPU Feature: AVX512EVEX
+func (x Int64x2) ShiftAllRightAndFillUpperFrom(imm uint8, y Int64x2) Int64x2
 
-// PairwiseSub horizontally subtracts adjacent pairs of elements.
-// For x = [x0, x1, x2, x3, ...] and y = [y0, y1, y2, y3, ...], the result is [y0-y1, y2-y3, ..., x0-x1, x2-x3, ...].
+// ShiftAllRightAndFillUpperFrom shifts each element of x to the right by the number of bits specified by the
+// immediate(only the lower 5 bits are used), and then copies the lower bits of y to the emptied upper bits of the shifted x.
 //
-// Asm: VHSUBPS, CPU Feature: AVX
-func (x Float32x8) PairwiseSub(y Float32x8) Float32x8
+// Asm: VPSHRDQ, CPU Feature: AVX512EVEX
+func (x Int64x4) ShiftAllRightAndFillUpperFrom(imm uint8, y Int64x4) Int64x4
 
-// PairwiseSub horizontally subtracts adjacent pairs of elements.
-// For x = [x0, x1, x2, x3, ...] and y = [y0, y1, y2, y3, ...], the result is [y0-y1, y2-y3, ..., x0-x1, x2-x3, ...].
+// ShiftAllRightAndFillUpperFrom shifts each element of x to the right by the number of bits specified by the
+// immediate(only the lower 5 bits are used), and then copies the lower bits of y to the emptied upper bits of the shifted x.
 //
-// Asm: VHSUBPD, CPU Feature: AVX
-func (x Float64x2) PairwiseSub(y Float64x2) Float64x2
+// Asm: VPSHRDQ, CPU Feature: AVX512EVEX
+func (x Int64x8) ShiftAllRightAndFillUpperFrom(imm uint8, y Int64x8) Int64x8
 
-// PairwiseSub horizontally subtracts adjacent pairs of elements.
-// For x = [x0, x1, x2, x3, ...] and y = [y0, y1, y2, y3, ...], the result is [y0-y1, y2-y3, ..., x0-x1, x2-x3, ...].
+// ShiftAllRightAndFillUpperFrom shifts each element of x to the right by the number of bits specified by the
+// immediate(only the lower 5 bits are used), and then copies the lower bits of y to the emptied upper bits of the shifted x.
 //
-// Asm: VHSUBPD, CPU Feature: AVX
-func (x Float64x4) PairwiseSub(y Float64x4) Float64x4
+// Asm: VPSHRDW, CPU Feature: AVX512EVEX
+func (x Uint16x8) ShiftAllRightAndFillUpperFrom(imm uint8, y Uint16x8) Uint16x8
 
-// PairwiseSub horizontally subtracts adjacent pairs of elements.
-// For x = [x0, x1, x2, x3, ...] and y = [y0, y1, y2, y3, ...], the result is [y0-y1, y2-y3, ..., x0-x1, x2-x3, ...].
+// ShiftAllRightAndFillUpperFrom shifts each element of x to the right by the number of bits specified by the
+// immediate(only the lower 5 bits are used), and then copies the lower bits of y to the emptied upper bits of the shifted x.
 //
-// Asm: VPHSUBW, CPU Feature: AVX
-func (x Int16x8) PairwiseSub(y Int16x8) Int16x8
+// Asm: VPSHRDW, CPU Feature: AVX512EVEX
+func (x Uint16x16) ShiftAllRightAndFillUpperFrom(imm uint8, y Uint16x16) Uint16x16
 
-// PairwiseSub horizontally subtracts adjacent pairs of elements.
-// For x = [x0, x1, x2, x3, ...] and y = [y0, y1, y2, y3, ...], the result is [y0-y1, y2-y3, ..., x0-x1, x2-x3, ...].
+// ShiftAllRightAndFillUpperFrom shifts each element of x to the right by the number of bits specified by the
+// immediate(only the lower 5 bits are used), and then copies the lower bits of y to the emptied upper bits of the shifted x.
 //
-// Asm: VPHSUBW, CPU Feature: AVX2
-func (x Int16x16) PairwiseSub(y Int16x16) Int16x16
+// Asm: VPSHRDW, CPU Feature: AVX512EVEX
+func (x Uint16x32) ShiftAllRightAndFillUpperFrom(imm uint8, y Uint16x32) Uint16x32
 
-// PairwiseSub horizontally subtracts adjacent pairs of elements.
-// For x = [x0, x1, x2, x3, ...] and y = [y0, y1, y2, y3, ...], the result is [y0-y1, y2-y3, ..., x0-x1, x2-x3, ...].
+// ShiftAllRightAndFillUpperFrom shifts each element of x to the right by the number of bits specified by the
+// immediate(only the lower 5 bits are used), and then copies the lower bits of y to the emptied upper bits of the shifted x.
 //
-// Asm: VPHSUBD, CPU Feature: AVX
-func (x Int32x4) PairwiseSub(y Int32x4) Int32x4
+// Asm: VPSHRDD, CPU Feature: AVX512EVEX
+func (x Uint32x4) ShiftAllRightAndFillUpperFrom(imm uint8, y Uint32x4) Uint32x4
 
-// PairwiseSub horizontally subtracts adjacent pairs of elements.
-// For x = [x0, x1, x2, x3, ...] and y = [y0, y1, y2, y3, ...], the result is [y0-y1, y2-y3, ..., x0-x1, x2-x3, ...].
+// ShiftAllRightAndFillUpperFrom shifts each element of x to the right by the number of bits specified by the
+// immediate(only the lower 5 bits are used), and then copies the lower bits of y to the emptied upper bits of the shifted x.
 //
-// Asm: VPHSUBD, CPU Feature: AVX2
-func (x Int32x8) PairwiseSub(y Int32x8) Int32x8
+// Asm: VPSHRDD, CPU Feature: AVX512EVEX
+func (x Uint32x8) ShiftAllRightAndFillUpperFrom(imm uint8, y Uint32x8) Uint32x8
 
-// PairwiseSub horizontally subtracts adjacent pairs of elements.
-// For x = [x0, x1, x2, x3, ...] and y = [y0, y1, y2, y3, ...], the result is [y0-y1, y2-y3, ..., x0-x1, x2-x3, ...].
+// ShiftAllRightAndFillUpperFrom shifts each element of x to the right by the number of bits specified by the
+// immediate(only the lower 5 bits are used), and then copies the lower bits of y to the emptied upper bits of the shifted x.
 //
-// Asm: VPHSUBW, CPU Feature: AVX
-func (x Uint16x8) PairwiseSub(y Uint16x8) Uint16x8
+// Asm: VPSHRDD, CPU Feature: AVX512EVEX
+func (x Uint32x16) ShiftAllRightAndFillUpperFrom(imm uint8, y Uint32x16) Uint32x16
 
-// PairwiseSub horizontally subtracts adjacent pairs of elements.
-// For x = [x0, x1, x2, x3, ...] and y = [y0, y1, y2, y3, ...], the result is [y0-y1, y2-y3, ..., x0-x1, x2-x3, ...].
+// ShiftAllRightAndFillUpperFrom shifts each element of x to the right by the number of bits specified by the
+// immediate(only the lower 5 bits are used), and then copies the lower bits of y to the emptied upper bits of the shifted x.
 //
-// Asm: VPHSUBW, CPU Feature: AVX2
-func (x Uint16x16) PairwiseSub(y Uint16x16) Uint16x16
+// Asm: VPSHRDQ, CPU Feature: AVX512EVEX
+func (x Uint64x2) ShiftAllRightAndFillUpperFrom(imm uint8, y Uint64x2) Uint64x2
 
-// PairwiseSub horizontally subtracts adjacent pairs of elements.
-// For x = [x0, x1, x2, x3, ...] and y = [y0, y1, y2, y3, ...], the result is [y0-y1, y2-y3, ..., x0-x1, x2-x3, ...].
+// ShiftAllRightAndFillUpperFrom shifts each element of x to the right by the number of bits specified by the
+// immediate(only the lower 5 bits are used), and then copies the lower bits of y to the emptied upper bits of the shifted x.
 //
-// Asm: VPHSUBD, CPU Feature: AVX
-func (x Uint32x4) PairwiseSub(y Uint32x4) Uint32x4
+// Asm: VPSHRDQ, CPU Feature: AVX512EVEX
+func (x Uint64x4) ShiftAllRightAndFillUpperFrom(imm uint8, y Uint64x4) Uint64x4
 
-// PairwiseSub horizontally subtracts adjacent pairs of elements.
-// For x = [x0, x1, x2, x3, ...] and y = [y0, y1, y2, y3, ...], the result is [y0-y1, y2-y3, ..., x0-x1, x2-x3, ...].
+// ShiftAllRightAndFillUpperFrom shifts each element of x to the right by the number of bits specified by the
+// immediate(only the lower 5 bits are used), and then copies the lower bits of y to the emptied upper bits of the shifted x.
 //
-// Asm: VPHSUBD, CPU Feature: AVX2
-func (x Uint32x8) PairwiseSub(y Uint32x8) Uint32x8
+// Asm: VPSHRDQ, CPU Feature: AVX512EVEX
+func (x Uint64x8) ShiftAllRightAndFillUpperFrom(imm uint8, y Uint64x8) Uint64x8
 
-/* PopCount */
+/* ShiftAllRightSignExtended */
 
-// PopCount counts the number of set bits in each element.
+// ShiftAllRightSignExtended shifts each element to the right by the specified number of bits. Emptied upper bits are filled with the sign bit.
 //
-// Asm: VPOPCNTB, CPU Feature: AVX512EVEX
-func (x Int8x16) PopCount() Int8x16
+// Asm: VPSRAW, CPU Feature: AVX
+func (x Int16x8) ShiftAllRightSignExtended(y uint64) Int16x8
 
-// PopCount counts the number of set bits in each element.
+// ShiftAllRightSignExtended shifts each element to the right by the specified number of bits. Emptied upper bits are filled with the sign bit.
 //
-// Asm: VPOPCNTB, CPU Feature: AVX512EVEX
-func (x Int8x32) PopCount() Int8x32
+// Asm: VPSRAW, CPU Feature: AVX2
+func (x Int16x16) ShiftAllRightSignExtended(y uint64) Int16x16
 
-// PopCount counts the number of set bits in each element.
+// ShiftAllRightSignExtended shifts each element to the right by the specified number of bits. Emptied upper bits are filled with the sign bit.
 //
-// Asm: VPOPCNTB, CPU Feature: AVX512EVEX
-func (x Int8x64) PopCount() Int8x64
+// Asm: VPSRAD, CPU Feature: AVX
+func (x Int32x4) ShiftAllRightSignExtended(y uint64) Int32x4
 
-// PopCount counts the number of set bits in each element.
+// ShiftAllRightSignExtended shifts each element to the right by the specified number of bits. Emptied upper bits are filled with the sign bit.
 //
-// Asm: VPOPCNTW, CPU Feature: AVX512EVEX
-func (x Int16x8) PopCount() Int16x8
+// Asm: VPSRAD, CPU Feature: AVX2
+func (x Int32x8) ShiftAllRightSignExtended(y uint64) Int32x8
 
-// PopCount counts the number of set bits in each element.
+// ShiftAllRightSignExtended shifts each element to the right by the specified number of bits. Emptied upper bits are filled with the sign bit.
 //
-// Asm: VPOPCNTW, CPU Feature: AVX512EVEX
-func (x Int16x16) PopCount() Int16x16
+// Asm: VPSRAQ, CPU Feature: AVX512EVEX
+func (x Int64x2) ShiftAllRightSignExtended(y uint64) Int64x2
 
-// PopCount counts the number of set bits in each element.
+// ShiftAllRightSignExtended shifts each element to the right by the specified number of bits. Emptied upper bits are filled with the sign bit.
 //
-// Asm: VPOPCNTW, CPU Feature: AVX512EVEX
-func (x Int16x32) PopCount() Int16x32
+// Asm: VPSRAQ, CPU Feature: AVX512EVEX
+func (x Int64x4) ShiftAllRightSignExtended(y uint64) Int64x4
 
-// PopCount counts the number of set bits in each element.
+// ShiftAllRightSignExtended shifts each element to the right by the specified number of bits. Emptied upper bits are filled with the sign bit.
 //
-// Asm: VPOPCNTD, CPU Feature: AVX512EVEX
-func (x Int32x4) PopCount() Int32x4
+// Asm: VPSRAQ, CPU Feature: AVX512EVEX
+func (x Int64x8) ShiftAllRightSignExtended(y uint64) Int64x8
 
-// PopCount counts the number of set bits in each element.
+/* ShiftLeft */
+
+// ShiftLeft shifts each element in x to the left by the number of bits specified in y's corresponding elements. Emptied lower bits are zeroed.
 //
-// Asm: VPOPCNTD, CPU Feature: AVX512EVEX
-func (x Int32x8) PopCount() Int32x8
+// Asm: VPSLLVW, CPU Feature: AVX512EVEX
+func (x Int16x8) ShiftLeft(y Int16x8) Int16x8
 
-// PopCount counts the number of set bits in each element.
+// ShiftLeft shifts each element in x to the left by the number of bits specified in y's corresponding elements. Emptied lower bits are zeroed.
 //
-// Asm: VPOPCNTD, CPU Feature: AVX512EVEX
-func (x Int32x16) PopCount() Int32x16
+// Asm: VPSLLVW, CPU Feature: AVX512EVEX
+func (x Int16x16) ShiftLeft(y Int16x16) Int16x16
 
-// PopCount counts the number of set bits in each element.
+// ShiftLeft shifts each element in x to the left by the number of bits specified in y's corresponding elements. Emptied lower bits are zeroed.
 //
-// Asm: VPOPCNTQ, CPU Feature: AVX512EVEX
-func (x Int64x2) PopCount() Int64x2
+// Asm: VPSLLVW, CPU Feature: AVX512EVEX
+func (x Int16x32) ShiftLeft(y Int16x32) Int16x32
 
-// PopCount counts the number of set bits in each element.
+// ShiftLeft shifts each element in x to the left by the number of bits specified in y's corresponding elements. Emptied lower bits are zeroed.
 //
-// Asm: VPOPCNTQ, CPU Feature: AVX512EVEX
-func (x Int64x4) PopCount() Int64x4
+// Asm: VPSLLVD, CPU Feature: AVX2
+func (x Int32x4) ShiftLeft(y Int32x4) Int32x4
 
-// PopCount counts the number of set bits in each element.
+// ShiftLeft shifts each element in x to the left by the number of bits specified in y's corresponding elements. Emptied lower bits are zeroed.
 //
-// Asm: VPOPCNTQ, CPU Feature: AVX512EVEX
-func (x Int64x8) PopCount() Int64x8
+// Asm: VPSLLVD, CPU Feature: AVX2
+func (x Int32x8) ShiftLeft(y Int32x8) Int32x8
 
-// PopCount counts the number of set bits in each element.
+// ShiftLeft shifts each element in x to the left by the number of bits specified in y's corresponding elements. Emptied lower bits are zeroed.
 //
-// Asm: VPOPCNTB, CPU Feature: AVX512EVEX
-func (x Uint8x16) PopCount() Uint8x16
+// Asm: VPSLLVD, CPU Feature: AVX512EVEX
+func (x Int32x16) ShiftLeft(y Int32x16) Int32x16
 
-// PopCount counts the number of set bits in each element.
+// ShiftLeft shifts each element in x to the left by the number of bits specified in y's corresponding elements. Emptied lower bits are zeroed.
 //
-// Asm: VPOPCNTB, CPU Feature: AVX512EVEX
-func (x Uint8x32) PopCount() Uint8x32
+// Asm: VPSLLVQ, CPU Feature: AVX2
+func (x Int64x2) ShiftLeft(y Int64x2) Int64x2
 
-// PopCount counts the number of set bits in each element.
+// ShiftLeft shifts each element in x to the left by the number of bits specified in y's corresponding elements. Emptied lower bits are zeroed.
 //
-// Asm: VPOPCNTB, CPU Feature: AVX512EVEX
-func (x Uint8x64) PopCount() Uint8x64
+// Asm: VPSLLVQ, CPU Feature: AVX2
+func (x Int64x4) ShiftLeft(y Int64x4) Int64x4
 
-// PopCount counts the number of set bits in each element.
+// ShiftLeft shifts each element in x to the left by the number of bits specified in y's corresponding elements. Emptied lower bits are zeroed.
 //
-// Asm: VPOPCNTW, CPU Feature: AVX512EVEX
-func (x Uint16x8) PopCount() Uint16x8
+// Asm: VPSLLVQ, CPU Feature: AVX512EVEX
+func (x Int64x8) ShiftLeft(y Int64x8) Int64x8
 
-// PopCount counts the number of set bits in each element.
+// ShiftLeft shifts each element in x to the left by the number of bits specified in y's corresponding elements. Emptied lower bits are zeroed.
 //
-// Asm: VPOPCNTW, CPU Feature: AVX512EVEX
-func (x Uint16x16) PopCount() Uint16x16
+// Asm: VPSLLVW, CPU Feature: AVX512EVEX
+func (x Uint16x8) ShiftLeft(y Uint16x8) Uint16x8
 
-// PopCount counts the number of set bits in each element.
+// ShiftLeft shifts each element in x to the left by the number of bits specified in y's corresponding elements. Emptied lower bits are zeroed.
 //
-// Asm: VPOPCNTW, CPU Feature: AVX512EVEX
-func (x Uint16x32) PopCount() Uint16x32
+// Asm: VPSLLVW, CPU Feature: AVX512EVEX
+func (x Uint16x16) ShiftLeft(y Uint16x16) Uint16x16
+
+// ShiftLeft shifts each element in x to the left by the number of bits specified in y's corresponding elements. Emptied lower bits are zeroed.
+//
+// Asm: VPSLLVW, CPU Feature: AVX512EVEX
+func (x Uint16x32) ShiftLeft(y Uint16x32) Uint16x32
 
-// PopCount counts the number of set bits in each element.
+// ShiftLeft shifts each element in x to the left by the number of bits specified in y's corresponding elements. Emptied lower bits are zeroed.
 //
-// Asm: VPOPCNTD, CPU Feature: AVX512EVEX
-func (x Uint32x4) PopCount() Uint32x4
+// Asm: VPSLLVD, CPU Feature: AVX2
+func (x Uint32x4) ShiftLeft(y Uint32x4) Uint32x4
 
-// PopCount counts the number of set bits in each element.
+// ShiftLeft shifts each element in x to the left by the number of bits specified in y's corresponding elements. Emptied lower bits are zeroed.
 //
-// Asm: VPOPCNTD, CPU Feature: AVX512EVEX
-func (x Uint32x8) PopCount() Uint32x8
+// Asm: VPSLLVD, CPU Feature: AVX2
+func (x Uint32x8) ShiftLeft(y Uint32x8) Uint32x8
 
-// PopCount counts the number of set bits in each element.
+// ShiftLeft shifts each element in x to the left by the number of bits specified in y's corresponding elements. Emptied lower bits are zeroed.
 //
-// Asm: VPOPCNTD, CPU Feature: AVX512EVEX
-func (x Uint32x16) PopCount() Uint32x16
+// Asm: VPSLLVD, CPU Feature: AVX512EVEX
+func (x Uint32x16) ShiftLeft(y Uint32x16) Uint32x16
 
-// PopCount counts the number of set bits in each element.
+// ShiftLeft shifts each element in x to the left by the number of bits specified in y's corresponding elements. Emptied lower bits are zeroed.
 //
-// Asm: VPOPCNTQ, CPU Feature: AVX512EVEX
-func (x Uint64x2) PopCount() Uint64x2
+// Asm: VPSLLVQ, CPU Feature: AVX2
+func (x Uint64x2) ShiftLeft(y Uint64x2) Uint64x2
 
-// PopCount counts the number of set bits in each element.
+// ShiftLeft shifts each element in x to the left by the number of bits specified in y's corresponding elements. Emptied lower bits are zeroed.
 //
-// Asm: VPOPCNTQ, CPU Feature: AVX512EVEX
-func (x Uint64x4) PopCount() Uint64x4
+// Asm: VPSLLVQ, CPU Feature: AVX2
+func (x Uint64x4) ShiftLeft(y Uint64x4) Uint64x4
 
-// PopCount counts the number of set bits in each element.
+// ShiftLeft shifts each element in x to the left by the number of bits specified in y's corresponding elements. Emptied lower bits are zeroed.
 //
-// Asm: VPOPCNTQ, CPU Feature: AVX512EVEX
-func (x Uint64x8) PopCount() Uint64x8
+// Asm: VPSLLVQ, CPU Feature: AVX512EVEX
+func (x Uint64x8) ShiftLeft(y Uint64x8) Uint64x8
 
-/* Round */
+/* ShiftLeftAndFillUpperFrom */
 
-// Round rounds elements to the nearest integer.
-// Const Immediate = 0.
+// ShiftLeftAndFillUpperFrom shifts each element of x to the left by the number of bits specified by the
+// corresponding elements in y(only the lower 5 bits are used), and then copies the upper bits of z to the emptied lower bits of the shifted x.
 //
-// Asm: VROUNDPS, CPU Feature: AVX
-func (x Float32x4) Round() Float32x4
+// Asm: VPSHLDVW, CPU Feature: AVX512EVEX
+func (x Int16x8) ShiftLeftAndFillUpperFrom(y Int16x8, z Int16x8) Int16x8
 
-// Round rounds elements to the nearest integer.
-// Const Immediate = 0.
+// ShiftLeftAndFillUpperFrom shifts each element of x to the left by the number of bits specified by the
+// corresponding elements in y(only the lower 5 bits are used), and then copies the upper bits of z to the emptied lower bits of the shifted x.
 //
-// Asm: VROUNDPS, CPU Feature: AVX
-func (x Float32x8) Round() Float32x8
+// Asm: VPSHLDVW, CPU Feature: AVX512EVEX
+func (x Int16x16) ShiftLeftAndFillUpperFrom(y Int16x16, z Int16x16) Int16x16
 
-// Round rounds elements to the nearest integer.
-// Const Immediate = 0.
+// ShiftLeftAndFillUpperFrom shifts each element of x to the left by the number of bits specified by the
+// corresponding elements in y(only the lower 5 bits are used), and then copies the upper bits of z to the emptied lower bits of the shifted x.
 //
-// Asm: VROUNDPD, CPU Feature: AVX
-func (x Float64x2) Round() Float64x2
+// Asm: VPSHLDVW, CPU Feature: AVX512EVEX
+func (x Int16x32) ShiftLeftAndFillUpperFrom(y Int16x32, z Int16x32) Int16x32
 
-// Round rounds elements to the nearest integer.
-// Const Immediate = 0.
+// ShiftLeftAndFillUpperFrom shifts each element of x to the left by the number of bits specified by the
+// corresponding elements in y(only the lower 5 bits are used), and then copies the upper bits of z to the emptied lower bits of the shifted x.
 //
-// Asm: VROUNDPD, CPU Feature: AVX
-func (x Float64x4) Round() Float64x4
+// Asm: VPSHLDVD, CPU Feature: AVX512EVEX
+func (x Int32x4) ShiftLeftAndFillUpperFrom(y Int32x4, z Int32x4) Int32x4
 
-/* RoundSuppressExceptionWithPrecision */
+// ShiftLeftAndFillUpperFrom shifts each element of x to the left by the number of bits specified by the
+// corresponding elements in y(only the lower 5 bits are used), and then copies the upper bits of z to the emptied lower bits of the shifted x.
+//
+// Asm: VPSHLDVD, CPU Feature: AVX512EVEX
+func (x Int32x8) ShiftLeftAndFillUpperFrom(y Int32x8, z Int32x8) Int32x8
 
-// RoundSuppressExceptionWithPrecision rounds elements with specified precision, suppressing exceptions.
-// Const Immediate = 8.
+// ShiftLeftAndFillUpperFrom shifts each element of x to the left by the number of bits specified by the
+// corresponding elements in y(only the lower 5 bits are used), and then copies the upper bits of z to the emptied lower bits of the shifted x.
 //
-// Asm: VRNDSCALEPS, CPU Feature: AVX512EVEX
-func (x Float32x4) RoundSuppressExceptionWithPrecision(imm8 uint8) Float32x4
+// Asm: VPSHLDVD, CPU Feature: AVX512EVEX
+func (x Int32x16) ShiftLeftAndFillUpperFrom(y Int32x16, z Int32x16) Int32x16
 
-// RoundSuppressExceptionWithPrecision rounds elements with specified precision, suppressing exceptions.
-// Const Immediate = 8.
+// ShiftLeftAndFillUpperFrom shifts each element of x to the left by the number of bits specified by the
+// corresponding elements in y(only the lower 5 bits are used), and then copies the upper bits of z to the emptied lower bits of the shifted x.
 //
-// Asm: VRNDSCALEPS, CPU Feature: AVX512EVEX
-func (x Float32x8) RoundSuppressExceptionWithPrecision(imm8 uint8) Float32x8
+// Asm: VPSHLDVQ, CPU Feature: AVX512EVEX
+func (x Int64x2) ShiftLeftAndFillUpperFrom(y Int64x2, z Int64x2) Int64x2
 
-// RoundSuppressExceptionWithPrecision rounds elements with specified precision, suppressing exceptions.
-// Const Immediate = 8.
+// ShiftLeftAndFillUpperFrom shifts each element of x to the left by the number of bits specified by the
+// corresponding elements in y(only the lower 5 bits are used), and then copies the upper bits of z to the emptied lower bits of the shifted x.
 //
-// Asm: VRNDSCALEPS, CPU Feature: AVX512EVEX
-func (x Float32x16) RoundSuppressExceptionWithPrecision(imm8 uint8) Float32x16
+// Asm: VPSHLDVQ, CPU Feature: AVX512EVEX
+func (x Int64x4) ShiftLeftAndFillUpperFrom(y Int64x4, z Int64x4) Int64x4
 
-// RoundSuppressExceptionWithPrecision rounds elements with specified precision, suppressing exceptions.
-// Const Immediate = 8.
+// ShiftLeftAndFillUpperFrom shifts each element of x to the left by the number of bits specified by the
+// corresponding elements in y(only the lower 5 bits are used), and then copies the upper bits of z to the emptied lower bits of the shifted x.
 //
-// Asm: VRNDSCALEPD, CPU Feature: AVX512EVEX
-func (x Float64x2) RoundSuppressExceptionWithPrecision(imm8 uint8) Float64x2
+// Asm: VPSHLDVQ, CPU Feature: AVX512EVEX
+func (x Int64x8) ShiftLeftAndFillUpperFrom(y Int64x8, z Int64x8) Int64x8
 
-// RoundSuppressExceptionWithPrecision rounds elements with specified precision, suppressing exceptions.
-// Const Immediate = 8.
+// ShiftLeftAndFillUpperFrom shifts each element of x to the left by the number of bits specified by the
+// corresponding elements in y(only the lower 5 bits are used), and then copies the upper bits of z to the emptied lower bits of the shifted x.
 //
-// Asm: VRNDSCALEPD, CPU Feature: AVX512EVEX
-func (x Float64x4) RoundSuppressExceptionWithPrecision(imm8 uint8) Float64x4
+// Asm: VPSHLDVW, CPU Feature: AVX512EVEX
+func (x Uint16x8) ShiftLeftAndFillUpperFrom(y Uint16x8, z Uint16x8) Uint16x8
 
-// RoundSuppressExceptionWithPrecision rounds elements with specified precision, suppressing exceptions.
-// Const Immediate = 8.
+// ShiftLeftAndFillUpperFrom shifts each element of x to the left by the number of bits specified by the
+// corresponding elements in y(only the lower 5 bits are used), and then copies the upper bits of z to the emptied lower bits of the shifted x.
 //
-// Asm: VRNDSCALEPD, CPU Feature: AVX512EVEX
-func (x Float64x8) RoundSuppressExceptionWithPrecision(imm8 uint8) Float64x8
+// Asm: VPSHLDVW, CPU Feature: AVX512EVEX
+func (x Uint16x16) ShiftLeftAndFillUpperFrom(y Uint16x16, z Uint16x16) Uint16x16
 
-/* RoundWithPrecision */
+// ShiftLeftAndFillUpperFrom shifts each element of x to the left by the number of bits specified by the
+// corresponding elements in y(only the lower 5 bits are used), and then copies the upper bits of z to the emptied lower bits of the shifted x.
+//
+// Asm: VPSHLDVW, CPU Feature: AVX512EVEX
+func (x Uint16x32) ShiftLeftAndFillUpperFrom(y Uint16x32, z Uint16x32) Uint16x32
 
-// RoundWithPrecision rounds elements with specified precision.
-// Const Immediate = 0.
+// ShiftLeftAndFillUpperFrom shifts each element of x to the left by the number of bits specified by the
+// corresponding elements in y(only the lower 5 bits are used), and then copies the upper bits of z to the emptied lower bits of the shifted x.
 //
-// Asm: VRNDSCALEPS, CPU Feature: AVX512EVEX
-func (x Float32x4) RoundWithPrecision(imm8 uint8) Float32x4
+// Asm: VPSHLDVD, CPU Feature: AVX512EVEX
+func (x Uint32x4) ShiftLeftAndFillUpperFrom(y Uint32x4, z Uint32x4) Uint32x4
 
-// RoundWithPrecision rounds elements with specified precision.
-// Const Immediate = 0.
+// ShiftLeftAndFillUpperFrom shifts each element of x to the left by the number of bits specified by the
+// corresponding elements in y(only the lower 5 bits are used), and then copies the upper bits of z to the emptied lower bits of the shifted x.
 //
-// Asm: VRNDSCALEPS, CPU Feature: AVX512EVEX
-func (x Float32x8) RoundWithPrecision(imm8 uint8) Float32x8
+// Asm: VPSHLDVD, CPU Feature: AVX512EVEX
+func (x Uint32x8) ShiftLeftAndFillUpperFrom(y Uint32x8, z Uint32x8) Uint32x8
 
-// RoundWithPrecision rounds elements with specified precision.
-// Const Immediate = 0.
+// ShiftLeftAndFillUpperFrom shifts each element of x to the left by the number of bits specified by the
+// corresponding elements in y(only the lower 5 bits are used), and then copies the upper bits of z to the emptied lower bits of the shifted x.
 //
-// Asm: VRNDSCALEPS, CPU Feature: AVX512EVEX
-func (x Float32x16) RoundWithPrecision(imm8 uint8) Float32x16
+// Asm: VPSHLDVD, CPU Feature: AVX512EVEX
+func (x Uint32x16) ShiftLeftAndFillUpperFrom(y Uint32x16, z Uint32x16) Uint32x16
 
-// RoundWithPrecision rounds elements with specified precision.
-// Const Immediate = 0.
+// ShiftLeftAndFillUpperFrom shifts each element of x to the left by the number of bits specified by the
+// corresponding elements in y(only the lower 5 bits are used), and then copies the upper bits of z to the emptied lower bits of the shifted x.
 //
-// Asm: VRNDSCALEPD, CPU Feature: AVX512EVEX
-func (x Float64x2) RoundWithPrecision(imm8 uint8) Float64x2
+// Asm: VPSHLDVQ, CPU Feature: AVX512EVEX
+func (x Uint64x2) ShiftLeftAndFillUpperFrom(y Uint64x2, z Uint64x2) Uint64x2
 
-// RoundWithPrecision rounds elements with specified precision.
-// Const Immediate = 0.
+// ShiftLeftAndFillUpperFrom shifts each element of x to the left by the number of bits specified by the
+// corresponding elements in y(only the lower 5 bits are used), and then copies the upper bits of z to the emptied lower bits of the shifted x.
 //
-// Asm: VRNDSCALEPD, CPU Feature: AVX512EVEX
-func (x Float64x4) RoundWithPrecision(imm8 uint8) Float64x4
+// Asm: VPSHLDVQ, CPU Feature: AVX512EVEX
+func (x Uint64x4) ShiftLeftAndFillUpperFrom(y Uint64x4, z Uint64x4) Uint64x4
 
-// RoundWithPrecision rounds elements with specified precision.
-// Const Immediate = 0.
+// ShiftLeftAndFillUpperFrom shifts each element of x to the left by the number of bits specified by the
+// corresponding elements in y(only the lower 5 bits are used), and then copies the upper bits of z to the emptied lower bits of the shifted x.
 //
-// Asm: VRNDSCALEPD, CPU Feature: AVX512EVEX
-func (x Float64x8) RoundWithPrecision(imm8 uint8) Float64x8
+// Asm: VPSHLDVQ, CPU Feature: AVX512EVEX
+func (x Uint64x8) ShiftLeftAndFillUpperFrom(y Uint64x8, z Uint64x8) Uint64x8
 
-/* SaturatedAdd */
+/* ShiftRight */
 
-// SaturatedAdd adds corresponding elements of two vectors with saturation.
+// ShiftRight shifts each element in x to the right by the number of bits specified in y's corresponding elements. Emptied upper bits are zeroed.
 //
-// Asm: VPADDSB, CPU Feature: AVX
-func (x Int8x16) SaturatedAdd(y Int8x16) Int8x16
+// Asm: VPSRLVW, CPU Feature: AVX512EVEX
+func (x Int16x8) ShiftRight(y Int16x8) Int16x8
 
-// SaturatedAdd adds corresponding elements of two vectors with saturation.
+// ShiftRight shifts each element in x to the right by the number of bits specified in y's corresponding elements. Emptied upper bits are zeroed.
 //
-// Asm: VPADDSB, CPU Feature: AVX2
-func (x Int8x32) SaturatedAdd(y Int8x32) Int8x32
+// Asm: VPSRLVW, CPU Feature: AVX512EVEX
+func (x Int16x16) ShiftRight(y Int16x16) Int16x16
 
-// SaturatedAdd adds corresponding elements of two vectors with saturation.
+// ShiftRight shifts each element in x to the right by the number of bits specified in y's corresponding elements. Emptied upper bits are zeroed.
 //
-// Asm: VPADDSB, CPU Feature: AVX512EVEX
-func (x Int8x64) SaturatedAdd(y Int8x64) Int8x64
+// Asm: VPSRLVW, CPU Feature: AVX512EVEX
+func (x Int16x32) ShiftRight(y Int16x32) Int16x32
 
-// SaturatedAdd adds corresponding elements of two vectors with saturation.
+// ShiftRight shifts each element in x to the right by the number of bits specified in y's corresponding elements. Emptied upper bits are zeroed.
 //
-// Asm: VPADDSW, CPU Feature: AVX
-func (x Int16x8) SaturatedAdd(y Int16x8) Int16x8
+// Asm: VPSRLVD, CPU Feature: AVX2
+func (x Int32x4) ShiftRight(y Int32x4) Int32x4
 
-// SaturatedAdd adds corresponding elements of two vectors with saturation.
+// ShiftRight shifts each element in x to the right by the number of bits specified in y's corresponding elements. Emptied upper bits are zeroed.
 //
-// Asm: VPADDSW, CPU Feature: AVX2
-func (x Int16x16) SaturatedAdd(y Int16x16) Int16x16
+// Asm: VPSRLVD, CPU Feature: AVX2
+func (x Int32x8) ShiftRight(y Int32x8) Int32x8
 
-// SaturatedAdd adds corresponding elements of two vectors with saturation.
+// ShiftRight shifts each element in x to the right by the number of bits specified in y's corresponding elements. Emptied upper bits are zeroed.
 //
-// Asm: VPADDSW, CPU Feature: AVX512EVEX
-func (x Int16x32) SaturatedAdd(y Int16x32) Int16x32
+// Asm: VPSRLVD, CPU Feature: AVX512EVEX
+func (x Int32x16) ShiftRight(y Int32x16) Int32x16
 
-// SaturatedAdd adds corresponding elements of two vectors with saturation.
+// ShiftRight shifts each element in x to the right by the number of bits specified in y's corresponding elements. Emptied upper bits are zeroed.
 //
-// Asm: VPADDSB, CPU Feature: AVX
-func (x Uint8x16) SaturatedAdd(y Uint8x16) Uint8x16
+// Asm: VPSRLVQ, CPU Feature: AVX2
+func (x Int64x2) ShiftRight(y Int64x2) Int64x2
 
-// SaturatedAdd adds corresponding elements of two vectors with saturation.
+// ShiftRight shifts each element in x to the right by the number of bits specified in y's corresponding elements. Emptied upper bits are zeroed.
 //
-// Asm: VPADDSB, CPU Feature: AVX2
-func (x Uint8x32) SaturatedAdd(y Uint8x32) Uint8x32
+// Asm: VPSRLVQ, CPU Feature: AVX2
+func (x Int64x4) ShiftRight(y Int64x4) Int64x4
 
-// SaturatedAdd adds corresponding elements of two vectors with saturation.
+// ShiftRight shifts each element in x to the right by the number of bits specified in y's corresponding elements. Emptied upper bits are zeroed.
 //
-// Asm: VPADDSB, CPU Feature: AVX512EVEX
-func (x Uint8x64) SaturatedAdd(y Uint8x64) Uint8x64
+// Asm: VPSRLVQ, CPU Feature: AVX512EVEX
+func (x Int64x8) ShiftRight(y Int64x8) Int64x8
 
-// SaturatedAdd adds corresponding elements of two vectors with saturation.
+// ShiftRight shifts each element in x to the right by the number of bits specified in y's corresponding elements. Emptied upper bits are zeroed.
 //
-// Asm: VPADDSW, CPU Feature: AVX
-func (x Uint16x8) SaturatedAdd(y Uint16x8) Uint16x8
+// Asm: VPSRLVW, CPU Feature: AVX512EVEX
+func (x Uint16x8) ShiftRight(y Uint16x8) Uint16x8
 
-// SaturatedAdd adds corresponding elements of two vectors with saturation.
+// ShiftRight shifts each element in x to the right by the number of bits specified in y's corresponding elements. Emptied upper bits are zeroed.
 //
-// Asm: VPADDSW, CPU Feature: AVX2
-func (x Uint16x16) SaturatedAdd(y Uint16x16) Uint16x16
+// Asm: VPSRLVW, CPU Feature: AVX512EVEX
+func (x Uint16x16) ShiftRight(y Uint16x16) Uint16x16
 
-// SaturatedAdd adds corresponding elements of two vectors with saturation.
+// ShiftRight shifts each element in x to the right by the number of bits specified in y's corresponding elements. Emptied upper bits are zeroed.
 //
-// Asm: VPADDSW, CPU Feature: AVX512EVEX
-func (x Uint16x32) SaturatedAdd(y Uint16x32) Uint16x32
-
-/* SaturatedPairDotProdAccumulate */
+// Asm: VPSRLVW, CPU Feature: AVX512EVEX
+func (x Uint16x32) ShiftRight(y Uint16x32) Uint16x32
 
-// SaturatedPairDotProdAccumulate performs dot products on pairs of elements of y and z and accumulates the results to x.
+// ShiftRight shifts each element in x to the right by the number of bits specified in y's corresponding elements. Emptied upper bits are zeroed.
 //
-// Asm: VPDPWSSDS, CPU Feature: AVX_VNNI
-func (x Int32x4) SaturatedPairDotProdAccumulate(y Int16x8, z Int16x8) Int32x4
+// Asm: VPSRLVD, CPU Feature: AVX2
+func (x Uint32x4) ShiftRight(y Uint32x4) Uint32x4
 
-// SaturatedPairDotProdAccumulate performs dot products on pairs of elements of y and z and accumulates the results to x.
+// ShiftRight shifts each element in x to the right by the number of bits specified in y's corresponding elements. Emptied upper bits are zeroed.
 //
-// Asm: VPDPWSSDS, CPU Feature: AVX_VNNI
-func (x Int32x8) SaturatedPairDotProdAccumulate(y Int16x16, z Int16x16) Int32x8
+// Asm: VPSRLVD, CPU Feature: AVX2
+func (x Uint32x8) ShiftRight(y Uint32x8) Uint32x8
 
-// SaturatedPairDotProdAccumulate performs dot products on pairs of elements of y and z and accumulates the results to x.
+// ShiftRight shifts each element in x to the right by the number of bits specified in y's corresponding elements. Emptied upper bits are zeroed.
 //
-// Asm: VPDPWSSDS, CPU Feature: AVX512EVEX
-func (x Int32x16) SaturatedPairDotProdAccumulate(y Int16x32, z Int16x32) Int32x16
+// Asm: VPSRLVD, CPU Feature: AVX512EVEX
+func (x Uint32x16) ShiftRight(y Uint32x16) Uint32x16
 
-/* SaturatedPairwiseAdd */
+// ShiftRight shifts each element in x to the right by the number of bits specified in y's corresponding elements. Emptied upper bits are zeroed.
+//
+// Asm: VPSRLVQ, CPU Feature: AVX2
+func (x Uint64x2) ShiftRight(y Uint64x2) Uint64x2
 
-// SaturatedPairwiseAdd horizontally adds adjacent pairs of elements with saturation.
-// For x = [x0, x1, x2, x3, ...] and y = [y0, y1, y2, y3, ...], the result is [y0+y1, y2+y3, ..., x0+x1, x2+x3, ...].
+// ShiftRight shifts each element in x to the right by the number of bits specified in y's corresponding elements. Emptied upper bits are zeroed.
 //
-// Asm: VPHADDSW, CPU Feature: AVX
-func (x Int16x8) SaturatedPairwiseAdd(y Int16x8) Int16x8
+// Asm: VPSRLVQ, CPU Feature: AVX2
+func (x Uint64x4) ShiftRight(y Uint64x4) Uint64x4
 
-// SaturatedPairwiseAdd horizontally adds adjacent pairs of elements with saturation.
-// For x = [x0, x1, x2, x3, ...] and y = [y0, y1, y2, y3, ...], the result is [y0+y1, y2+y3, ..., x0+x1, x2+x3, ...].
+// ShiftRight shifts each element in x to the right by the number of bits specified in y's corresponding elements. Emptied upper bits are zeroed.
 //
-// Asm: VPHADDSW, CPU Feature: AVX2
-func (x Int16x16) SaturatedPairwiseAdd(y Int16x16) Int16x16
+// Asm: VPSRLVQ, CPU Feature: AVX512EVEX
+func (x Uint64x8) ShiftRight(y Uint64x8) Uint64x8
 
-/* SaturatedPairwiseSub */
+/* ShiftRightAndFillUpperFrom */
 
-// SaturatedPairwiseSub horizontally subtracts adjacent pairs of elements with saturation.
-// For x = [x0, x1, x2, x3, ...] and y = [y0, y1, y2, y3, ...], the result is [y0-y1, y2-y3, ..., x0-x1, x2-x3, ...].
+// ShiftRightAndFillUpperFrom shifts each element of x to the right by the number of bits specified by the
+// corresponding elements in y(only the lower 5 bits are used), and then copies the lower bits of z to the emptied upper bits of the shifted x.
 //
-// Asm: VPHSUBSW, CPU Feature: AVX
-func (x Int16x8) SaturatedPairwiseSub(y Int16x8) Int16x8
+// Asm: VPSHRDVW, CPU Feature: AVX512EVEX
+func (x Int16x8) ShiftRightAndFillUpperFrom(y Int16x8, z Int16x8) Int16x8
 
-// SaturatedPairwiseSub horizontally subtracts adjacent pairs of elements with saturation.
-// For x = [x0, x1, x2, x3, ...] and y = [y0, y1, y2, y3, ...], the result is [y0-y1, y2-y3, ..., x0-x1, x2-x3, ...].
+// ShiftRightAndFillUpperFrom shifts each element of x to the right by the number of bits specified by the
+// corresponding elements in y(only the lower 5 bits are used), and then copies the lower bits of z to the emptied upper bits of the shifted x.
 //
-// Asm: VPHSUBSW, CPU Feature: AVX2
-func (x Int16x16) SaturatedPairwiseSub(y Int16x16) Int16x16
+// Asm: VPSHRDVW, CPU Feature: AVX512EVEX
+func (x Int16x16) ShiftRightAndFillUpperFrom(y Int16x16, z Int16x16) Int16x16
 
-/* SaturatedSub */
+// ShiftRightAndFillUpperFrom shifts each element of x to the right by the number of bits specified by the
+// corresponding elements in y(only the lower 5 bits are used), and then copies the lower bits of z to the emptied upper bits of the shifted x.
+//
+// Asm: VPSHRDVW, CPU Feature: AVX512EVEX
+func (x Int16x32) ShiftRightAndFillUpperFrom(y Int16x32, z Int16x32) Int16x32
 
-// SaturatedSub subtracts corresponding elements of two vectors with saturation.
+// ShiftRightAndFillUpperFrom shifts each element of x to the right by the number of bits specified by the
+// corresponding elements in y(only the lower 5 bits are used), and then copies the lower bits of z to the emptied upper bits of the shifted x.
 //
-// Asm: VPSUBSB, CPU Feature: AVX
-func (x Int8x16) SaturatedSub(y Int8x16) Int8x16
+// Asm: VPSHRDVD, CPU Feature: AVX512EVEX
+func (x Int32x4) ShiftRightAndFillUpperFrom(y Int32x4, z Int32x4) Int32x4
 
-// SaturatedSub subtracts corresponding elements of two vectors with saturation.
+// ShiftRightAndFillUpperFrom shifts each element of x to the right by the number of bits specified by the
+// corresponding elements in y(only the lower 5 bits are used), and then copies the lower bits of z to the emptied upper bits of the shifted x.
 //
-// Asm: VPSUBSB, CPU Feature: AVX2
-func (x Int8x32) SaturatedSub(y Int8x32) Int8x32
+// Asm: VPSHRDVD, CPU Feature: AVX512EVEX
+func (x Int32x8) ShiftRightAndFillUpperFrom(y Int32x8, z Int32x8) Int32x8
 
-// SaturatedSub subtracts corresponding elements of two vectors with saturation.
+// ShiftRightAndFillUpperFrom shifts each element of x to the right by the number of bits specified by the
+// corresponding elements in y(only the lower 5 bits are used), and then copies the lower bits of z to the emptied upper bits of the shifted x.
 //
-// Asm: VPSUBSB, CPU Feature: AVX512EVEX
-func (x Int8x64) SaturatedSub(y Int8x64) Int8x64
+// Asm: VPSHRDVD, CPU Feature: AVX512EVEX
+func (x Int32x16) ShiftRightAndFillUpperFrom(y Int32x16, z Int32x16) Int32x16
 
-// SaturatedSub subtracts corresponding elements of two vectors with saturation.
+// ShiftRightAndFillUpperFrom shifts each element of x to the right by the number of bits specified by the
+// corresponding elements in y(only the lower 5 bits are used), and then copies the lower bits of z to the emptied upper bits of the shifted x.
 //
-// Asm: VPSUBSW, CPU Feature: AVX
-func (x Int16x8) SaturatedSub(y Int16x8) Int16x8
+// Asm: VPSHRDVQ, CPU Feature: AVX512EVEX
+func (x Int64x2) ShiftRightAndFillUpperFrom(y Int64x2, z Int64x2) Int64x2
 
-// SaturatedSub subtracts corresponding elements of two vectors with saturation.
+// ShiftRightAndFillUpperFrom shifts each element of x to the right by the number of bits specified by the
+// corresponding elements in y(only the lower 5 bits are used), and then copies the lower bits of z to the emptied upper bits of the shifted x.
 //
-// Asm: VPSUBSW, CPU Feature: AVX2
-func (x Int16x16) SaturatedSub(y Int16x16) Int16x16
+// Asm: VPSHRDVQ, CPU Feature: AVX512EVEX
+func (x Int64x4) ShiftRightAndFillUpperFrom(y Int64x4, z Int64x4) Int64x4
 
-// SaturatedSub subtracts corresponding elements of two vectors with saturation.
+// ShiftRightAndFillUpperFrom shifts each element of x to the right by the number of bits specified by the
+// corresponding elements in y(only the lower 5 bits are used), and then copies the lower bits of z to the emptied upper bits of the shifted x.
 //
-// Asm: VPSUBSW, CPU Feature: AVX512EVEX
-func (x Int16x32) SaturatedSub(y Int16x32) Int16x32
+// Asm: VPSHRDVQ, CPU Feature: AVX512EVEX
+func (x Int64x8) ShiftRightAndFillUpperFrom(y Int64x8, z Int64x8) Int64x8
 
-// SaturatedSub subtracts corresponding elements of two vectors with saturation.
+// ShiftRightAndFillUpperFrom shifts each element of x to the right by the number of bits specified by the
+// corresponding elements in y(only the lower 5 bits are used), and then copies the lower bits of z to the emptied upper bits of the shifted x.
 //
-// Asm: VPSUBSB, CPU Feature: AVX
-func (x Uint8x16) SaturatedSub(y Uint8x16) Uint8x16
+// Asm: VPSHRDVW, CPU Feature: AVX512EVEX
+func (x Uint16x8) ShiftRightAndFillUpperFrom(y Uint16x8, z Uint16x8) Uint16x8
 
-// SaturatedSub subtracts corresponding elements of two vectors with saturation.
+// ShiftRightAndFillUpperFrom shifts each element of x to the right by the number of bits specified by the
+// corresponding elements in y(only the lower 5 bits are used), and then copies the lower bits of z to the emptied upper bits of the shifted x.
 //
-// Asm: VPSUBSB, CPU Feature: AVX2
-func (x Uint8x32) SaturatedSub(y Uint8x32) Uint8x32
+// Asm: VPSHRDVW, CPU Feature: AVX512EVEX
+func (x Uint16x16) ShiftRightAndFillUpperFrom(y Uint16x16, z Uint16x16) Uint16x16
 
-// SaturatedSub subtracts corresponding elements of two vectors with saturation.
+// ShiftRightAndFillUpperFrom shifts each element of x to the right by the number of bits specified by the
+// corresponding elements in y(only the lower 5 bits are used), and then copies the lower bits of z to the emptied upper bits of the shifted x.
 //
-// Asm: VPSUBSB, CPU Feature: AVX512EVEX
-func (x Uint8x64) SaturatedSub(y Uint8x64) Uint8x64
+// Asm: VPSHRDVW, CPU Feature: AVX512EVEX
+func (x Uint16x32) ShiftRightAndFillUpperFrom(y Uint16x32, z Uint16x32) Uint16x32
 
-// SaturatedSub subtracts corresponding elements of two vectors with saturation.
+// ShiftRightAndFillUpperFrom shifts each element of x to the right by the number of bits specified by the
+// corresponding elements in y(only the lower 5 bits are used), and then copies the lower bits of z to the emptied upper bits of the shifted x.
 //
-// Asm: VPSUBSW, CPU Feature: AVX
-func (x Uint16x8) SaturatedSub(y Uint16x8) Uint16x8
+// Asm: VPSHRDVD, CPU Feature: AVX512EVEX
+func (x Uint32x4) ShiftRightAndFillUpperFrom(y Uint32x4, z Uint32x4) Uint32x4
 
-// SaturatedSub subtracts corresponding elements of two vectors with saturation.
+// ShiftRightAndFillUpperFrom shifts each element of x to the right by the number of bits specified by the
+// corresponding elements in y(only the lower 5 bits are used), and then copies the lower bits of z to the emptied upper bits of the shifted x.
 //
-// Asm: VPSUBSW, CPU Feature: AVX2
-func (x Uint16x16) SaturatedSub(y Uint16x16) Uint16x16
+// Asm: VPSHRDVD, CPU Feature: AVX512EVEX
+func (x Uint32x8) ShiftRightAndFillUpperFrom(y Uint32x8, z Uint32x8) Uint32x8
 
-// SaturatedSub subtracts corresponding elements of two vectors with saturation.
+// ShiftRightAndFillUpperFrom shifts each element of x to the right by the number of bits specified by the
+// corresponding elements in y(only the lower 5 bits are used), and then copies the lower bits of z to the emptied upper bits of the shifted x.
 //
-// Asm: VPSUBSW, CPU Feature: AVX512EVEX
-func (x Uint16x32) SaturatedSub(y Uint16x32) Uint16x32
+// Asm: VPSHRDVD, CPU Feature: AVX512EVEX
+func (x Uint32x16) ShiftRightAndFillUpperFrom(y Uint32x16, z Uint32x16) Uint32x16
 
-/* SaturatedUnsignedSignedPairDotProd */
+// ShiftRightAndFillUpperFrom shifts each element of x to the right by the number of bits specified by the
+// corresponding elements in y(only the lower 5 bits are used), and then copies the lower bits of z to the emptied upper bits of the shifted x.
+//
+// Asm: VPSHRDVQ, CPU Feature: AVX512EVEX
+func (x Uint64x2) ShiftRightAndFillUpperFrom(y Uint64x2, z Uint64x2) Uint64x2
 
-// SaturatedPairDotProd multiplies the elements and add the pairs together with saturation,
-// yielding a vector of half as many elements with twice the input element size.
+// ShiftRightAndFillUpperFrom shifts each element of x to the right by the number of bits specified by the
+// corresponding elements in y(only the lower 5 bits are used), and then copies the lower bits of z to the emptied upper bits of the shifted x.
 //
-// Asm: VPMADDUBSW, CPU Feature: AVX
-func (x Uint8x16) SaturatedUnsignedSignedPairDotProd(y Int8x16) Int16x8
+// Asm: VPSHRDVQ, CPU Feature: AVX512EVEX
+func (x Uint64x4) ShiftRightAndFillUpperFrom(y Uint64x4, z Uint64x4) Uint64x4
 
-// SaturatedPairDotProd multiplies the elements and add the pairs together with saturation,
-// yielding a vector of half as many elements with twice the input element size.
+// ShiftRightAndFillUpperFrom shifts each element of x to the right by the number of bits specified by the
+// corresponding elements in y(only the lower 5 bits are used), and then copies the lower bits of z to the emptied upper bits of the shifted x.
 //
-// Asm: VPMADDUBSW, CPU Feature: AVX2
-func (x Uint8x32) SaturatedUnsignedSignedPairDotProd(y Int8x32) Int16x16
+// Asm: VPSHRDVQ, CPU Feature: AVX512EVEX
+func (x Uint64x8) ShiftRightAndFillUpperFrom(y Uint64x8, z Uint64x8) Uint64x8
 
-// SaturatedPairDotProd multiplies the elements and add the pairs together with saturation,
-// yielding a vector of half as many elements with twice the input element size.
+/* ShiftRightSignExtended */
+
+// ShiftRightSignExtended shifts each element in x to the right by the number of bits specified in y's corresponding elements. Emptied upper bits are filled with the sign bit.
 //
-// Asm: VPMADDUBSW, CPU Feature: AVX512EVEX
-func (x Uint8x64) SaturatedUnsignedSignedPairDotProd(y Int8x64) Int16x32
+// Asm: VPSRAVW, CPU Feature: AVX512EVEX
+func (x Int16x8) ShiftRightSignExtended(y Int16x8) Int16x8
 
-/* SaturatedUnsignedSignedQuadDotProdAccumulate */
+// ShiftRightSignExtended shifts each element in x to the right by the number of bits specified in y's corresponding elements. Emptied upper bits are filled with the sign bit.
+//
+// Asm: VPSRAVW, CPU Feature: AVX512EVEX
+func (x Int16x16) ShiftRightSignExtended(y Int16x16) Int16x16
 
-// SaturatedUnsignedSignedQuadDotProdAccumulate multiplies performs dot products on groups of 4 elements of y and z and accumulates the results to x.
+// ShiftRightSignExtended shifts each element in x to the right by the number of bits specified in y's corresponding elements. Emptied upper bits are filled with the sign bit.
 //
-// Asm: VPDPBUSDS, CPU Feature: AVX_VNNI
-func (x Int32x4) SaturatedUnsignedSignedQuadDotProdAccumulate(y Uint8x16, z Int8x16) Int32x4
+// Asm: VPSRAVW, CPU Feature: AVX512EVEX
+func (x Int16x32) ShiftRightSignExtended(y Int16x32) Int16x32
 
-// SaturatedUnsignedSignedQuadDotProdAccumulate multiplies performs dot products on groups of 4 elements of y and z and accumulates the results to x.
+// ShiftRightSignExtended shifts each element in x to the right by the number of bits specified in y's corresponding elements. Emptied upper bits are filled with the sign bit.
 //
-// Asm: VPDPBUSDS, CPU Feature: AVX_VNNI
-func (x Int32x8) SaturatedUnsignedSignedQuadDotProdAccumulate(y Uint8x32, z Int8x32) Int32x8
+// Asm: VPSRAVD, CPU Feature: AVX2
+func (x Int32x4) ShiftRightSignExtended(y Int32x4) Int32x4
 
-// SaturatedUnsignedSignedQuadDotProdAccumulate multiplies performs dot products on groups of 4 elements of y and z and accumulates the results to x.
+// ShiftRightSignExtended shifts each element in x to the right by the number of bits specified in y's corresponding elements. Emptied upper bits are filled with the sign bit.
 //
-// Asm: VPDPBUSDS, CPU Feature: AVX512EVEX
-func (x Int32x16) SaturatedUnsignedSignedQuadDotProdAccumulate(y Uint8x64, z Int8x64) Int32x16
+// Asm: VPSRAVD, CPU Feature: AVX2
+func (x Int32x8) ShiftRightSignExtended(y Int32x8) Int32x8
 
-// SaturatedUnsignedSignedQuadDotProdAccumulate multiplies performs dot products on groups of 4 elements of y and z and accumulates the results to x.
+// ShiftRightSignExtended shifts each element in x to the right by the number of bits specified in y's corresponding elements. Emptied upper bits are filled with the sign bit.
 //
-// Asm: VPDPBUSDS, CPU Feature: AVX_VNNI
-func (x Uint32x4) SaturatedUnsignedSignedQuadDotProdAccumulate(y Uint8x16, z Int8x16) Uint32x4
+// Asm: VPSRAVD, CPU Feature: AVX512EVEX
+func (x Int32x16) ShiftRightSignExtended(y Int32x16) Int32x16
 
-// SaturatedUnsignedSignedQuadDotProdAccumulate multiplies performs dot products on groups of 4 elements of y and z and accumulates the results to x.
+// ShiftRightSignExtended shifts each element in x to the right by the number of bits specified in y's corresponding elements. Emptied upper bits are filled with the sign bit.
 //
-// Asm: VPDPBUSDS, CPU Feature: AVX_VNNI
-func (x Uint32x8) SaturatedUnsignedSignedQuadDotProdAccumulate(y Uint8x32, z Int8x32) Uint32x8
+// Asm: VPSRAVQ, CPU Feature: AVX512EVEX
+func (x Int64x2) ShiftRightSignExtended(y Int64x2) Int64x2
 
-// SaturatedUnsignedSignedQuadDotProdAccumulate multiplies performs dot products on groups of 4 elements of y and z and accumulates the results to x.
+// ShiftRightSignExtended shifts each element in x to the right by the number of bits specified in y's corresponding elements. Emptied upper bits are filled with the sign bit.
 //
-// Asm: VPDPBUSDS, CPU Feature: AVX512EVEX
-func (x Uint32x16) SaturatedUnsignedSignedQuadDotProdAccumulate(y Uint8x64, z Int8x64) Uint32x16
+// Asm: VPSRAVQ, CPU Feature: AVX512EVEX
+func (x Int64x4) ShiftRightSignExtended(y Int64x4) Int64x4
 
-/* SetElem */
+// ShiftRightSignExtended shifts each element in x to the right by the number of bits specified in y's corresponding elements. Emptied upper bits are filled with the sign bit.
+//
+// Asm: VPSRAVQ, CPU Feature: AVX512EVEX
+func (x Int64x8) ShiftRightSignExtended(y Int64x8) Int64x8
 
-// SetElem sets a single constant-indexed element's value.
+// ShiftRightSignExtended shifts each element in x to the right by the number of bits specified in y's corresponding elements. Emptied upper bits are filled with the sign bit.
 //
-// Asm: VPINSRB, CPU Feature: AVX
-func (x Int8x16) SetElem(imm uint8, y int8) Int8x16
+// Asm: VPSRAVW, CPU Feature: AVX512EVEX
+func (x Uint16x8) ShiftRightSignExtended(y Uint16x8) Uint16x8
 
-// SetElem sets a single constant-indexed element's value.
+// ShiftRightSignExtended shifts each element in x to the right by the number of bits specified in y's corresponding elements. Emptied upper bits are filled with the sign bit.
 //
-// Asm: VPINSRW, CPU Feature: AVX
-func (x Int16x8) SetElem(imm uint8, y int16) Int16x8
+// Asm: VPSRAVW, CPU Feature: AVX512EVEX
+func (x Uint16x16) ShiftRightSignExtended(y Uint16x16) Uint16x16
 
-// SetElem sets a single constant-indexed element's value.
+// ShiftRightSignExtended shifts each element in x to the right by the number of bits specified in y's corresponding elements. Emptied upper bits are filled with the sign bit.
 //
-// Asm: VPINSRD, CPU Feature: AVX
-func (x Int32x4) SetElem(imm uint8, y int32) Int32x4
+// Asm: VPSRAVW, CPU Feature: AVX512EVEX
+func (x Uint16x32) ShiftRightSignExtended(y Uint16x32) Uint16x32
 
-// SetElem sets a single constant-indexed element's value.
+// ShiftRightSignExtended shifts each element in x to the right by the number of bits specified in y's corresponding elements. Emptied upper bits are filled with the sign bit.
 //
-// Asm: VPINSRQ, CPU Feature: AVX
-func (x Int64x2) SetElem(imm uint8, y int64) Int64x2
+// Asm: VPSRAVD, CPU Feature: AVX2
+func (x Uint32x4) ShiftRightSignExtended(y Uint32x4) Uint32x4
 
-// SetElem sets a single constant-indexed element's value.
+// ShiftRightSignExtended shifts each element in x to the right by the number of bits specified in y's corresponding elements. Emptied upper bits are filled with the sign bit.
 //
-// Asm: VPINSRB, CPU Feature: AVX
-func (x Uint8x16) SetElem(imm uint8, y uint8) Uint8x16
+// Asm: VPSRAVD, CPU Feature: AVX2
+func (x Uint32x8) ShiftRightSignExtended(y Uint32x8) Uint32x8
 
-// SetElem sets a single constant-indexed element's value.
+// ShiftRightSignExtended shifts each element in x to the right by the number of bits specified in y's corresponding elements. Emptied upper bits are filled with the sign bit.
 //
-// Asm: VPINSRW, CPU Feature: AVX
-func (x Uint16x8) SetElem(imm uint8, y uint16) Uint16x8
+// Asm: VPSRAVD, CPU Feature: AVX512EVEX
+func (x Uint32x16) ShiftRightSignExtended(y Uint32x16) Uint32x16
 
-// SetElem sets a single constant-indexed element's value.
+// ShiftRightSignExtended shifts each element in x to the right by the number of bits specified in y's corresponding elements. Emptied upper bits are filled with the sign bit.
 //
-// Asm: VPINSRD, CPU Feature: AVX
-func (x Uint32x4) SetElem(imm uint8, y uint32) Uint32x4
+// Asm: VPSRAVQ, CPU Feature: AVX512EVEX
+func (x Uint64x2) ShiftRightSignExtended(y Uint64x2) Uint64x2
 
-// SetElem sets a single constant-indexed element's value.
+// ShiftRightSignExtended shifts each element in x to the right by the number of bits specified in y's corresponding elements. Emptied upper bits are filled with the sign bit.
 //
-// Asm: VPINSRQ, CPU Feature: AVX
-func (x Uint64x2) SetElem(imm uint8, y uint64) Uint64x2
+// Asm: VPSRAVQ, CPU Feature: AVX512EVEX
+func (x Uint64x4) ShiftRightSignExtended(y Uint64x4) Uint64x4
+
+// ShiftRightSignExtended shifts each element in x to the right by the number of bits specified in y's corresponding elements. Emptied upper bits are filled with the sign bit.
+//
+// Asm: VPSRAVQ, CPU Feature: AVX512EVEX
+func (x Uint64x8) ShiftRightSignExtended(y Uint64x8) Uint64x8
 
 /* Sign */