func simdAMD64Ops(v11, v21, v2k, vkv, v2kv, v2kk, v31, v3kv, vgpv, vgp, vfpv, vfpkv, w11, w21, w2k, wkw, w2kw, w2kk, w31, w3kw, wgpw, wgp, wfpw, wfpkw regInfo) []opData {
return []opData{
- {name: "VADDPS512", argLength: 2, reg: w21, asm: "VADDPS", commutative: true, typ: "Vec512", resultInArg0: false},
- {name: "VADDPSMasked512", argLength: 3, reg: w2kw, asm: "VADDPS", commutative: true, typ: "Vec512", resultInArg0: false},
- {name: "VRCP14PS512", argLength: 1, reg: w11, asm: "VRCP14PS", commutative: false, typ: "Vec512", resultInArg0: false},
- {name: "VRCP14PSMasked512", argLength: 2, reg: wkw, asm: "VRCP14PS", commutative: false, typ: "Vec512", resultInArg0: false},
- {name: "VRSQRT14PS512", argLength: 1, reg: w11, asm: "VRSQRT14PS", commutative: false, typ: "Vec512", resultInArg0: false},
- {name: "VRSQRT14PSMasked512", argLength: 2, reg: wkw, asm: "VRSQRT14PS", commutative: false, typ: "Vec512", resultInArg0: false},
- {name: "VCOMPRESSPSMasked512", argLength: 2, reg: wkw, asm: "VCOMPRESSPS", commutative: false, typ: "Vec512", resultInArg0: false},
- {name: "VDIVPS512", argLength: 2, reg: w21, asm: "VDIVPS", commutative: false, typ: "Vec512", resultInArg0: false},
- {name: "VDIVPSMasked512", argLength: 3, reg: w2kw, asm: "VDIVPS", commutative: false, typ: "Vec512", resultInArg0: false},
- {name: "VFMADD213PS512", argLength: 3, reg: w31, asm: "VFMADD213PS", commutative: false, typ: "Vec512", resultInArg0: true},
- {name: "VFMADD213PSMasked512", argLength: 4, reg: w3kw, asm: "VFMADD213PS", commutative: false, typ: "Vec512", resultInArg0: true},
- {name: "VFMADDSUB213PS512", argLength: 3, reg: w31, asm: "VFMADDSUB213PS", commutative: false, typ: "Vec512", resultInArg0: true},
- {name: "VFMADDSUB213PSMasked512", argLength: 4, reg: w3kw, asm: "VFMADDSUB213PS", commutative: false, typ: "Vec512", resultInArg0: true},
- {name: "VFMSUBADD213PS512", argLength: 3, reg: w31, asm: "VFMSUBADD213PS", commutative: false, typ: "Vec512", resultInArg0: true},
- {name: "VFMSUBADD213PSMasked512", argLength: 4, reg: w3kw, asm: "VFMSUBADD213PS", commutative: false, typ: "Vec512", resultInArg0: true},
- {name: "VMAXPS512", argLength: 2, reg: w21, asm: "VMAXPS", commutative: true, typ: "Vec512", resultInArg0: false},
- {name: "VMAXPSMasked512", argLength: 3, reg: w2kw, asm: "VMAXPS", commutative: true, typ: "Vec512", resultInArg0: false},
- {name: "VMINPS512", argLength: 2, reg: w21, asm: "VMINPS", commutative: true, typ: "Vec512", resultInArg0: false},
- {name: "VMINPSMasked512", argLength: 3, reg: w2kw, asm: "VMINPS", commutative: true, typ: "Vec512", resultInArg0: false},
- {name: "VMULPS512", argLength: 2, reg: w21, asm: "VMULPS", commutative: true, typ: "Vec512", resultInArg0: false},
- {name: "VSCALEFPS512", argLength: 2, reg: w21, asm: "VSCALEFPS", commutative: false, typ: "Vec512", resultInArg0: false},
- {name: "VSCALEFPSMasked512", argLength: 3, reg: w2kw, asm: "VSCALEFPS", commutative: false, typ: "Vec512", resultInArg0: false},
- {name: "VMULPSMasked512", argLength: 3, reg: w2kw, asm: "VMULPS", commutative: true, typ: "Vec512", resultInArg0: false},
- {name: "VSQRTPS512", argLength: 1, reg: w11, asm: "VSQRTPS", commutative: false, typ: "Vec512", resultInArg0: false},
- {name: "VSQRTPSMasked512", argLength: 2, reg: wkw, asm: "VSQRTPS", commutative: false, typ: "Vec512", resultInArg0: false},
- {name: "VSUBPS512", argLength: 2, reg: w21, asm: "VSUBPS", commutative: false, typ: "Vec512", resultInArg0: false},
- {name: "VSUBPSMasked512", argLength: 3, reg: w2kw, asm: "VSUBPS", commutative: false, typ: "Vec512", resultInArg0: false},
+ {name: "VADDPD128", argLength: 2, reg: v21, asm: "VADDPD", commutative: true, typ: "Vec128", resultInArg0: false},
+ {name: "VADDPD256", argLength: 2, reg: v21, asm: "VADDPD", commutative: true, typ: "Vec256", resultInArg0: false},
+ {name: "VADDPD512", argLength: 2, reg: w21, asm: "VADDPD", commutative: true, typ: "Vec512", resultInArg0: false},
+ {name: "VADDPDMasked128", argLength: 3, reg: w2kw, asm: "VADDPD", commutative: true, typ: "Vec128", resultInArg0: false},
+ {name: "VADDPDMasked256", argLength: 3, reg: w2kw, asm: "VADDPD", commutative: true, typ: "Vec256", resultInArg0: false},
+ {name: "VADDPDMasked512", argLength: 3, reg: w2kw, asm: "VADDPD", commutative: true, typ: "Vec512", resultInArg0: false},
{name: "VADDPS128", argLength: 2, reg: v21, asm: "VADDPS", commutative: true, typ: "Vec128", resultInArg0: false},
- {name: "VADDPSMasked128", argLength: 3, reg: w2kw, asm: "VADDPS", commutative: true, typ: "Vec128", resultInArg0: false},
- {name: "VADDSUBPS128", argLength: 2, reg: v21, asm: "VADDSUBPS", commutative: false, typ: "Vec128", resultInArg0: false},
- {name: "VRCPPS128", argLength: 1, reg: v11, asm: "VRCPPS", commutative: false, typ: "Vec128", resultInArg0: false},
- {name: "VRCP14PSMasked128", argLength: 2, reg: wkw, asm: "VRCP14PS", commutative: false, typ: "Vec128", resultInArg0: false},
- {name: "VRSQRTPS128", argLength: 1, reg: v11, asm: "VRSQRTPS", commutative: false, typ: "Vec128", resultInArg0: false},
- {name: "VRSQRT14PSMasked128", argLength: 2, reg: wkw, asm: "VRSQRT14PS", commutative: false, typ: "Vec128", resultInArg0: false},
- {name: "VCOMPRESSPSMasked128", argLength: 2, reg: wkw, asm: "VCOMPRESSPS", commutative: false, typ: "Vec128", resultInArg0: false},
- {name: "VDIVPS128", argLength: 2, reg: v21, asm: "VDIVPS", commutative: false, typ: "Vec128", resultInArg0: false},
- {name: "VDIVPSMasked128", argLength: 3, reg: w2kw, asm: "VDIVPS", commutative: false, typ: "Vec128", resultInArg0: false},
- {name: "VFMADD213PS128", argLength: 3, reg: w31, asm: "VFMADD213PS", commutative: false, typ: "Vec128", resultInArg0: true},
- {name: "VFMADD213PSMasked128", argLength: 4, reg: w3kw, asm: "VFMADD213PS", commutative: false, typ: "Vec128", resultInArg0: true},
- {name: "VFMADDSUB213PS128", argLength: 3, reg: w31, asm: "VFMADDSUB213PS", commutative: false, typ: "Vec128", resultInArg0: true},
- {name: "VFMADDSUB213PSMasked128", argLength: 4, reg: w3kw, asm: "VFMADDSUB213PS", commutative: false, typ: "Vec128", resultInArg0: true},
- {name: "VFMSUBADD213PS128", argLength: 3, reg: w31, asm: "VFMSUBADD213PS", commutative: false, typ: "Vec128", resultInArg0: true},
- {name: "VFMSUBADD213PSMasked128", argLength: 4, reg: w3kw, asm: "VFMSUBADD213PS", commutative: false, typ: "Vec128", resultInArg0: true},
- {name: "VMAXPS128", argLength: 2, reg: v21, asm: "VMAXPS", commutative: true, typ: "Vec128", resultInArg0: false},
- {name: "VMAXPSMasked128", argLength: 3, reg: w2kw, asm: "VMAXPS", commutative: true, typ: "Vec128", resultInArg0: false},
- {name: "VMINPS128", argLength: 2, reg: v21, asm: "VMINPS", commutative: true, typ: "Vec128", resultInArg0: false},
- {name: "VMINPSMasked128", argLength: 3, reg: w2kw, asm: "VMINPS", commutative: true, typ: "Vec128", resultInArg0: false},
- {name: "VMULPS128", argLength: 2, reg: v21, asm: "VMULPS", commutative: true, typ: "Vec128", resultInArg0: false},
- {name: "VSCALEFPS128", argLength: 2, reg: w21, asm: "VSCALEFPS", commutative: false, typ: "Vec128", resultInArg0: false},
- {name: "VSCALEFPSMasked128", argLength: 3, reg: w2kw, asm: "VSCALEFPS", commutative: false, typ: "Vec128", resultInArg0: false},
- {name: "VMULPSMasked128", argLength: 3, reg: w2kw, asm: "VMULPS", commutative: true, typ: "Vec128", resultInArg0: false},
- {name: "VHADDPS128", argLength: 2, reg: v21, asm: "VHADDPS", commutative: false, typ: "Vec128", resultInArg0: false},
- {name: "VHSUBPS128", argLength: 2, reg: v21, asm: "VHSUBPS", commutative: false, typ: "Vec128", resultInArg0: false},
- {name: "VSQRTPS128", argLength: 1, reg: v11, asm: "VSQRTPS", commutative: false, typ: "Vec128", resultInArg0: false},
- {name: "VSQRTPSMasked128", argLength: 2, reg: wkw, asm: "VSQRTPS", commutative: false, typ: "Vec128", resultInArg0: false},
- {name: "VSUBPS128", argLength: 2, reg: v21, asm: "VSUBPS", commutative: false, typ: "Vec128", resultInArg0: false},
- {name: "VSUBPSMasked128", argLength: 3, reg: w2kw, asm: "VSUBPS", commutative: false, typ: "Vec128", resultInArg0: false},
{name: "VADDPS256", argLength: 2, reg: v21, asm: "VADDPS", commutative: true, typ: "Vec256", resultInArg0: false},
+ {name: "VADDPS512", argLength: 2, reg: w21, asm: "VADDPS", commutative: true, typ: "Vec512", resultInArg0: false},
+ {name: "VADDPSMasked128", argLength: 3, reg: w2kw, asm: "VADDPS", commutative: true, typ: "Vec128", resultInArg0: false},
{name: "VADDPSMasked256", argLength: 3, reg: w2kw, asm: "VADDPS", commutative: true, typ: "Vec256", resultInArg0: false},
+ {name: "VADDPSMasked512", argLength: 3, reg: w2kw, asm: "VADDPS", commutative: true, typ: "Vec512", resultInArg0: false},
+ {name: "VADDSUBPD128", argLength: 2, reg: v21, asm: "VADDSUBPD", commutative: false, typ: "Vec128", resultInArg0: false},
+ {name: "VADDSUBPD256", argLength: 2, reg: v21, asm: "VADDSUBPD", commutative: false, typ: "Vec256", resultInArg0: false},
+ {name: "VADDSUBPS128", argLength: 2, reg: v21, asm: "VADDSUBPS", commutative: false, typ: "Vec128", resultInArg0: false},
{name: "VADDSUBPS256", argLength: 2, reg: v21, asm: "VADDSUBPS", commutative: false, typ: "Vec256", resultInArg0: false},
- {name: "VRCPPS256", argLength: 1, reg: v11, asm: "VRCPPS", commutative: false, typ: "Vec256", resultInArg0: false},
- {name: "VRCP14PSMasked256", argLength: 2, reg: wkw, asm: "VRCP14PS", commutative: false, typ: "Vec256", resultInArg0: false},
- {name: "VRSQRTPS256", argLength: 1, reg: v11, asm: "VRSQRTPS", commutative: false, typ: "Vec256", resultInArg0: false},
- {name: "VRSQRT14PSMasked256", argLength: 2, reg: wkw, asm: "VRSQRT14PS", commutative: false, typ: "Vec256", resultInArg0: false},
+ {name: "VCOMPRESSPDMasked128", argLength: 2, reg: wkw, asm: "VCOMPRESSPD", commutative: false, typ: "Vec128", resultInArg0: false},
+ {name: "VCOMPRESSPDMasked256", argLength: 2, reg: wkw, asm: "VCOMPRESSPD", commutative: false, typ: "Vec256", resultInArg0: false},
+ {name: "VCOMPRESSPDMasked512", argLength: 2, reg: wkw, asm: "VCOMPRESSPD", commutative: false, typ: "Vec512", resultInArg0: false},
+ {name: "VCOMPRESSPSMasked128", argLength: 2, reg: wkw, asm: "VCOMPRESSPS", commutative: false, typ: "Vec128", resultInArg0: false},
{name: "VCOMPRESSPSMasked256", argLength: 2, reg: wkw, asm: "VCOMPRESSPS", commutative: false, typ: "Vec256", resultInArg0: false},
+ {name: "VCOMPRESSPSMasked512", argLength: 2, reg: wkw, asm: "VCOMPRESSPS", commutative: false, typ: "Vec512", resultInArg0: false},
+ {name: "VDIVPD128", argLength: 2, reg: v21, asm: "VDIVPD", commutative: false, typ: "Vec128", resultInArg0: false},
+ {name: "VDIVPD256", argLength: 2, reg: v21, asm: "VDIVPD", commutative: false, typ: "Vec256", resultInArg0: false},
+ {name: "VDIVPD512", argLength: 2, reg: w21, asm: "VDIVPD", commutative: false, typ: "Vec512", resultInArg0: false},
+ {name: "VDIVPDMasked128", argLength: 3, reg: w2kw, asm: "VDIVPD", commutative: false, typ: "Vec128", resultInArg0: false},
+ {name: "VDIVPDMasked256", argLength: 3, reg: w2kw, asm: "VDIVPD", commutative: false, typ: "Vec256", resultInArg0: false},
+ {name: "VDIVPDMasked512", argLength: 3, reg: w2kw, asm: "VDIVPD", commutative: false, typ: "Vec512", resultInArg0: false},
+ {name: "VDIVPS128", argLength: 2, reg: v21, asm: "VDIVPS", commutative: false, typ: "Vec128", resultInArg0: false},
{name: "VDIVPS256", argLength: 2, reg: v21, asm: "VDIVPS", commutative: false, typ: "Vec256", resultInArg0: false},
+ {name: "VDIVPS512", argLength: 2, reg: w21, asm: "VDIVPS", commutative: false, typ: "Vec512", resultInArg0: false},
+ {name: "VDIVPSMasked128", argLength: 3, reg: w2kw, asm: "VDIVPS", commutative: false, typ: "Vec128", resultInArg0: false},
{name: "VDIVPSMasked256", argLength: 3, reg: w2kw, asm: "VDIVPS", commutative: false, typ: "Vec256", resultInArg0: false},
+ {name: "VDIVPSMasked512", argLength: 3, reg: w2kw, asm: "VDIVPS", commutative: false, typ: "Vec512", resultInArg0: false},
+ {name: "VFMADD213PD128", argLength: 3, reg: w31, asm: "VFMADD213PD", commutative: false, typ: "Vec128", resultInArg0: true},
+ {name: "VFMADD213PD256", argLength: 3, reg: w31, asm: "VFMADD213PD", commutative: false, typ: "Vec256", resultInArg0: true},
+ {name: "VFMADD213PD512", argLength: 3, reg: w31, asm: "VFMADD213PD", commutative: false, typ: "Vec512", resultInArg0: true},
+ {name: "VFMADD213PDMasked128", argLength: 4, reg: w3kw, asm: "VFMADD213PD", commutative: false, typ: "Vec128", resultInArg0: true},
+ {name: "VFMADD213PDMasked256", argLength: 4, reg: w3kw, asm: "VFMADD213PD", commutative: false, typ: "Vec256", resultInArg0: true},
+ {name: "VFMADD213PDMasked512", argLength: 4, reg: w3kw, asm: "VFMADD213PD", commutative: false, typ: "Vec512", resultInArg0: true},
+ {name: "VFMADD213PS128", argLength: 3, reg: w31, asm: "VFMADD213PS", commutative: false, typ: "Vec128", resultInArg0: true},
{name: "VFMADD213PS256", argLength: 3, reg: w31, asm: "VFMADD213PS", commutative: false, typ: "Vec256", resultInArg0: true},
+ {name: "VFMADD213PS512", argLength: 3, reg: w31, asm: "VFMADD213PS", commutative: false, typ: "Vec512", resultInArg0: true},
+ {name: "VFMADD213PSMasked128", argLength: 4, reg: w3kw, asm: "VFMADD213PS", commutative: false, typ: "Vec128", resultInArg0: true},
{name: "VFMADD213PSMasked256", argLength: 4, reg: w3kw, asm: "VFMADD213PS", commutative: false, typ: "Vec256", resultInArg0: true},
+ {name: "VFMADD213PSMasked512", argLength: 4, reg: w3kw, asm: "VFMADD213PS", commutative: false, typ: "Vec512", resultInArg0: true},
+ {name: "VFMADDSUB213PD128", argLength: 3, reg: w31, asm: "VFMADDSUB213PD", commutative: false, typ: "Vec128", resultInArg0: true},
+ {name: "VFMADDSUB213PD256", argLength: 3, reg: w31, asm: "VFMADDSUB213PD", commutative: false, typ: "Vec256", resultInArg0: true},
+ {name: "VFMADDSUB213PD512", argLength: 3, reg: w31, asm: "VFMADDSUB213PD", commutative: false, typ: "Vec512", resultInArg0: true},
+ {name: "VFMADDSUB213PDMasked128", argLength: 4, reg: w3kw, asm: "VFMADDSUB213PD", commutative: false, typ: "Vec128", resultInArg0: true},
+ {name: "VFMADDSUB213PDMasked256", argLength: 4, reg: w3kw, asm: "VFMADDSUB213PD", commutative: false, typ: "Vec256", resultInArg0: true},
+ {name: "VFMADDSUB213PDMasked512", argLength: 4, reg: w3kw, asm: "VFMADDSUB213PD", commutative: false, typ: "Vec512", resultInArg0: true},
+ {name: "VFMADDSUB213PS128", argLength: 3, reg: w31, asm: "VFMADDSUB213PS", commutative: false, typ: "Vec128", resultInArg0: true},
{name: "VFMADDSUB213PS256", argLength: 3, reg: w31, asm: "VFMADDSUB213PS", commutative: false, typ: "Vec256", resultInArg0: true},
+ {name: "VFMADDSUB213PS512", argLength: 3, reg: w31, asm: "VFMADDSUB213PS", commutative: false, typ: "Vec512", resultInArg0: true},
+ {name: "VFMADDSUB213PSMasked128", argLength: 4, reg: w3kw, asm: "VFMADDSUB213PS", commutative: false, typ: "Vec128", resultInArg0: true},
{name: "VFMADDSUB213PSMasked256", argLength: 4, reg: w3kw, asm: "VFMADDSUB213PS", commutative: false, typ: "Vec256", resultInArg0: true},
+ {name: "VFMADDSUB213PSMasked512", argLength: 4, reg: w3kw, asm: "VFMADDSUB213PS", commutative: false, typ: "Vec512", resultInArg0: true},
+ {name: "VFMSUBADD213PD128", argLength: 3, reg: w31, asm: "VFMSUBADD213PD", commutative: false, typ: "Vec128", resultInArg0: true},
+ {name: "VFMSUBADD213PD256", argLength: 3, reg: w31, asm: "VFMSUBADD213PD", commutative: false, typ: "Vec256", resultInArg0: true},
+ {name: "VFMSUBADD213PD512", argLength: 3, reg: w31, asm: "VFMSUBADD213PD", commutative: false, typ: "Vec512", resultInArg0: true},
+ {name: "VFMSUBADD213PDMasked128", argLength: 4, reg: w3kw, asm: "VFMSUBADD213PD", commutative: false, typ: "Vec128", resultInArg0: true},
+ {name: "VFMSUBADD213PDMasked256", argLength: 4, reg: w3kw, asm: "VFMSUBADD213PD", commutative: false, typ: "Vec256", resultInArg0: true},
+ {name: "VFMSUBADD213PDMasked512", argLength: 4, reg: w3kw, asm: "VFMSUBADD213PD", commutative: false, typ: "Vec512", resultInArg0: true},
+ {name: "VFMSUBADD213PS128", argLength: 3, reg: w31, asm: "VFMSUBADD213PS", commutative: false, typ: "Vec128", resultInArg0: true},
{name: "VFMSUBADD213PS256", argLength: 3, reg: w31, asm: "VFMSUBADD213PS", commutative: false, typ: "Vec256", resultInArg0: true},
+ {name: "VFMSUBADD213PS512", argLength: 3, reg: w31, asm: "VFMSUBADD213PS", commutative: false, typ: "Vec512", resultInArg0: true},
+ {name: "VFMSUBADD213PSMasked128", argLength: 4, reg: w3kw, asm: "VFMSUBADD213PS", commutative: false, typ: "Vec128", resultInArg0: true},
{name: "VFMSUBADD213PSMasked256", argLength: 4, reg: w3kw, asm: "VFMSUBADD213PS", commutative: false, typ: "Vec256", resultInArg0: true},
- {name: "VMAXPS256", argLength: 2, reg: v21, asm: "VMAXPS", commutative: true, typ: "Vec256", resultInArg0: false},
- {name: "VMAXPSMasked256", argLength: 3, reg: w2kw, asm: "VMAXPS", commutative: true, typ: "Vec256", resultInArg0: false},
- {name: "VMINPS256", argLength: 2, reg: v21, asm: "VMINPS", commutative: true, typ: "Vec256", resultInArg0: false},
- {name: "VMINPSMasked256", argLength: 3, reg: w2kw, asm: "VMINPS", commutative: true, typ: "Vec256", resultInArg0: false},
- {name: "VMULPS256", argLength: 2, reg: v21, asm: "VMULPS", commutative: true, typ: "Vec256", resultInArg0: false},
- {name: "VSCALEFPS256", argLength: 2, reg: w21, asm: "VSCALEFPS", commutative: false, typ: "Vec256", resultInArg0: false},
- {name: "VSCALEFPSMasked256", argLength: 3, reg: w2kw, asm: "VSCALEFPS", commutative: false, typ: "Vec256", resultInArg0: false},
- {name: "VMULPSMasked256", argLength: 3, reg: w2kw, asm: "VMULPS", commutative: true, typ: "Vec256", resultInArg0: false},
+ {name: "VFMSUBADD213PSMasked512", argLength: 4, reg: w3kw, asm: "VFMSUBADD213PS", commutative: false, typ: "Vec512", resultInArg0: true},
+ {name: "VGF2P8MULB128", argLength: 2, reg: w21, asm: "VGF2P8MULB", commutative: false, typ: "Vec128", resultInArg0: false},
+ {name: "VGF2P8MULB256", argLength: 2, reg: w21, asm: "VGF2P8MULB", commutative: false, typ: "Vec256", resultInArg0: false},
+ {name: "VGF2P8MULB512", argLength: 2, reg: w21, asm: "VGF2P8MULB", commutative: false, typ: "Vec512", resultInArg0: false},
+ {name: "VGF2P8MULBMasked128", argLength: 3, reg: w2kw, asm: "VGF2P8MULB", commutative: false, typ: "Vec128", resultInArg0: false},
+ {name: "VGF2P8MULBMasked256", argLength: 3, reg: w2kw, asm: "VGF2P8MULB", commutative: false, typ: "Vec256", resultInArg0: false},
+ {name: "VGF2P8MULBMasked512", argLength: 3, reg: w2kw, asm: "VGF2P8MULB", commutative: false, typ: "Vec512", resultInArg0: false},
+ {name: "VHADDPD128", argLength: 2, reg: v21, asm: "VHADDPD", commutative: false, typ: "Vec128", resultInArg0: false},
+ {name: "VHADDPD256", argLength: 2, reg: v21, asm: "VHADDPD", commutative: false, typ: "Vec256", resultInArg0: false},
+ {name: "VHADDPS128", argLength: 2, reg: v21, asm: "VHADDPS", commutative: false, typ: "Vec128", resultInArg0: false},
{name: "VHADDPS256", argLength: 2, reg: v21, asm: "VHADDPS", commutative: false, typ: "Vec256", resultInArg0: false},
+ {name: "VHSUBPD128", argLength: 2, reg: v21, asm: "VHSUBPD", commutative: false, typ: "Vec128", resultInArg0: false},
+ {name: "VHSUBPD256", argLength: 2, reg: v21, asm: "VHSUBPD", commutative: false, typ: "Vec256", resultInArg0: false},
+ {name: "VHSUBPS128", argLength: 2, reg: v21, asm: "VHSUBPS", commutative: false, typ: "Vec128", resultInArg0: false},
{name: "VHSUBPS256", argLength: 2, reg: v21, asm: "VHSUBPS", commutative: false, typ: "Vec256", resultInArg0: false},
- {name: "VSQRTPS256", argLength: 1, reg: v11, asm: "VSQRTPS", commutative: false, typ: "Vec256", resultInArg0: false},
- {name: "VSQRTPSMasked256", argLength: 2, reg: wkw, asm: "VSQRTPS", commutative: false, typ: "Vec256", resultInArg0: false},
- {name: "VSUBPS256", argLength: 2, reg: v21, asm: "VSUBPS", commutative: false, typ: "Vec256", resultInArg0: false},
- {name: "VSUBPSMasked256", argLength: 3, reg: w2kw, asm: "VSUBPS", commutative: false, typ: "Vec256", resultInArg0: false},
- {name: "VADDPD128", argLength: 2, reg: v21, asm: "VADDPD", commutative: true, typ: "Vec128", resultInArg0: false},
- {name: "VADDPDMasked128", argLength: 3, reg: w2kw, asm: "VADDPD", commutative: true, typ: "Vec128", resultInArg0: false},
- {name: "VADDSUBPD128", argLength: 2, reg: v21, asm: "VADDSUBPD", commutative: false, typ: "Vec128", resultInArg0: false},
- {name: "VRCP14PD128", argLength: 1, reg: w11, asm: "VRCP14PD", commutative: false, typ: "Vec128", resultInArg0: false},
- {name: "VRCP14PDMasked128", argLength: 2, reg: wkw, asm: "VRCP14PD", commutative: false, typ: "Vec128", resultInArg0: false},
- {name: "VRSQRT14PD128", argLength: 1, reg: w11, asm: "VRSQRT14PD", commutative: false, typ: "Vec128", resultInArg0: false},
- {name: "VRSQRT14PDMasked128", argLength: 2, reg: wkw, asm: "VRSQRT14PD", commutative: false, typ: "Vec128", resultInArg0: false},
- {name: "VCOMPRESSPDMasked128", argLength: 2, reg: wkw, asm: "VCOMPRESSPD", commutative: false, typ: "Vec128", resultInArg0: false},
- {name: "VDIVPD128", argLength: 2, reg: v21, asm: "VDIVPD", commutative: false, typ: "Vec128", resultInArg0: false},
- {name: "VDIVPDMasked128", argLength: 3, reg: w2kw, asm: "VDIVPD", commutative: false, typ: "Vec128", resultInArg0: false},
- {name: "VFMADD213PD128", argLength: 3, reg: w31, asm: "VFMADD213PD", commutative: false, typ: "Vec128", resultInArg0: true},
- {name: "VFMADD213PDMasked128", argLength: 4, reg: w3kw, asm: "VFMADD213PD", commutative: false, typ: "Vec128", resultInArg0: true},
- {name: "VFMADDSUB213PD128", argLength: 3, reg: w31, asm: "VFMADDSUB213PD", commutative: false, typ: "Vec128", resultInArg0: true},
- {name: "VFMADDSUB213PDMasked128", argLength: 4, reg: w3kw, asm: "VFMADDSUB213PD", commutative: false, typ: "Vec128", resultInArg0: true},
- {name: "VFMSUBADD213PD128", argLength: 3, reg: w31, asm: "VFMSUBADD213PD", commutative: false, typ: "Vec128", resultInArg0: true},
- {name: "VFMSUBADD213PDMasked128", argLength: 4, reg: w3kw, asm: "VFMSUBADD213PD", commutative: false, typ: "Vec128", resultInArg0: true},
{name: "VMAXPD128", argLength: 2, reg: v21, asm: "VMAXPD", commutative: true, typ: "Vec128", resultInArg0: false},
- {name: "VMAXPDMasked128", argLength: 3, reg: w2kw, asm: "VMAXPD", commutative: true, typ: "Vec128", resultInArg0: false},
- {name: "VMINPD128", argLength: 2, reg: v21, asm: "VMINPD", commutative: true, typ: "Vec128", resultInArg0: false},
- {name: "VMINPDMasked128", argLength: 3, reg: w2kw, asm: "VMINPD", commutative: true, typ: "Vec128", resultInArg0: false},
- {name: "VMULPD128", argLength: 2, reg: v21, asm: "VMULPD", commutative: true, typ: "Vec128", resultInArg0: false},
- {name: "VSCALEFPD128", argLength: 2, reg: w21, asm: "VSCALEFPD", commutative: false, typ: "Vec128", resultInArg0: false},
- {name: "VSCALEFPDMasked128", argLength: 3, reg: w2kw, asm: "VSCALEFPD", commutative: false, typ: "Vec128", resultInArg0: false},
- {name: "VMULPDMasked128", argLength: 3, reg: w2kw, asm: "VMULPD", commutative: true, typ: "Vec128", resultInArg0: false},
- {name: "VHADDPD128", argLength: 2, reg: v21, asm: "VHADDPD", commutative: false, typ: "Vec128", resultInArg0: false},
- {name: "VHSUBPD128", argLength: 2, reg: v21, asm: "VHSUBPD", commutative: false, typ: "Vec128", resultInArg0: false},
- {name: "VSQRTPD128", argLength: 1, reg: v11, asm: "VSQRTPD", commutative: false, typ: "Vec128", resultInArg0: false},
- {name: "VSQRTPDMasked128", argLength: 2, reg: wkw, asm: "VSQRTPD", commutative: false, typ: "Vec128", resultInArg0: false},
- {name: "VSUBPD128", argLength: 2, reg: v21, asm: "VSUBPD", commutative: false, typ: "Vec128", resultInArg0: false},
- {name: "VSUBPDMasked128", argLength: 3, reg: w2kw, asm: "VSUBPD", commutative: false, typ: "Vec128", resultInArg0: false},
- {name: "VADDPD256", argLength: 2, reg: v21, asm: "VADDPD", commutative: true, typ: "Vec256", resultInArg0: false},
- {name: "VADDPDMasked256", argLength: 3, reg: w2kw, asm: "VADDPD", commutative: true, typ: "Vec256", resultInArg0: false},
- {name: "VADDSUBPD256", argLength: 2, reg: v21, asm: "VADDSUBPD", commutative: false, typ: "Vec256", resultInArg0: false},
- {name: "VRCP14PD256", argLength: 1, reg: w11, asm: "VRCP14PD", commutative: false, typ: "Vec256", resultInArg0: false},
- {name: "VRCP14PDMasked256", argLength: 2, reg: wkw, asm: "VRCP14PD", commutative: false, typ: "Vec256", resultInArg0: false},
- {name: "VRSQRT14PD256", argLength: 1, reg: w11, asm: "VRSQRT14PD", commutative: false, typ: "Vec256", resultInArg0: false},
- {name: "VRSQRT14PDMasked256", argLength: 2, reg: wkw, asm: "VRSQRT14PD", commutative: false, typ: "Vec256", resultInArg0: false},
- {name: "VCOMPRESSPDMasked256", argLength: 2, reg: wkw, asm: "VCOMPRESSPD", commutative: false, typ: "Vec256", resultInArg0: false},
- {name: "VDIVPD256", argLength: 2, reg: v21, asm: "VDIVPD", commutative: false, typ: "Vec256", resultInArg0: false},
- {name: "VDIVPDMasked256", argLength: 3, reg: w2kw, asm: "VDIVPD", commutative: false, typ: "Vec256", resultInArg0: false},
- {name: "VFMADD213PD256", argLength: 3, reg: w31, asm: "VFMADD213PD", commutative: false, typ: "Vec256", resultInArg0: true},
- {name: "VFMADD213PDMasked256", argLength: 4, reg: w3kw, asm: "VFMADD213PD", commutative: false, typ: "Vec256", resultInArg0: true},
- {name: "VFMADDSUB213PD256", argLength: 3, reg: w31, asm: "VFMADDSUB213PD", commutative: false, typ: "Vec256", resultInArg0: true},
- {name: "VFMADDSUB213PDMasked256", argLength: 4, reg: w3kw, asm: "VFMADDSUB213PD", commutative: false, typ: "Vec256", resultInArg0: true},
- {name: "VFMSUBADD213PD256", argLength: 3, reg: w31, asm: "VFMSUBADD213PD", commutative: false, typ: "Vec256", resultInArg0: true},
- {name: "VFMSUBADD213PDMasked256", argLength: 4, reg: w3kw, asm: "VFMSUBADD213PD", commutative: false, typ: "Vec256", resultInArg0: true},
{name: "VMAXPD256", argLength: 2, reg: v21, asm: "VMAXPD", commutative: true, typ: "Vec256", resultInArg0: false},
- {name: "VMAXPDMasked256", argLength: 3, reg: w2kw, asm: "VMAXPD", commutative: true, typ: "Vec256", resultInArg0: false},
- {name: "VMINPD256", argLength: 2, reg: v21, asm: "VMINPD", commutative: true, typ: "Vec256", resultInArg0: false},
- {name: "VMINPDMasked256", argLength: 3, reg: w2kw, asm: "VMINPD", commutative: true, typ: "Vec256", resultInArg0: false},
- {name: "VMULPD256", argLength: 2, reg: v21, asm: "VMULPD", commutative: true, typ: "Vec256", resultInArg0: false},
- {name: "VSCALEFPD256", argLength: 2, reg: w21, asm: "VSCALEFPD", commutative: false, typ: "Vec256", resultInArg0: false},
- {name: "VSCALEFPDMasked256", argLength: 3, reg: w2kw, asm: "VSCALEFPD", commutative: false, typ: "Vec256", resultInArg0: false},
- {name: "VMULPDMasked256", argLength: 3, reg: w2kw, asm: "VMULPD", commutative: true, typ: "Vec256", resultInArg0: false},
- {name: "VHADDPD256", argLength: 2, reg: v21, asm: "VHADDPD", commutative: false, typ: "Vec256", resultInArg0: false},
- {name: "VHSUBPD256", argLength: 2, reg: v21, asm: "VHSUBPD", commutative: false, typ: "Vec256", resultInArg0: false},
- {name: "VSQRTPD256", argLength: 1, reg: v11, asm: "VSQRTPD", commutative: false, typ: "Vec256", resultInArg0: false},
- {name: "VSQRTPDMasked256", argLength: 2, reg: wkw, asm: "VSQRTPD", commutative: false, typ: "Vec256", resultInArg0: false},
- {name: "VSUBPD256", argLength: 2, reg: v21, asm: "VSUBPD", commutative: false, typ: "Vec256", resultInArg0: false},
- {name: "VSUBPDMasked256", argLength: 3, reg: w2kw, asm: "VSUBPD", commutative: false, typ: "Vec256", resultInArg0: false},
- {name: "VADDPD512", argLength: 2, reg: w21, asm: "VADDPD", commutative: true, typ: "Vec512", resultInArg0: false},
- {name: "VADDPDMasked512", argLength: 3, reg: w2kw, asm: "VADDPD", commutative: true, typ: "Vec512", resultInArg0: false},
- {name: "VRCP14PD512", argLength: 1, reg: w11, asm: "VRCP14PD", commutative: false, typ: "Vec512", resultInArg0: false},
- {name: "VRCP14PDMasked512", argLength: 2, reg: wkw, asm: "VRCP14PD", commutative: false, typ: "Vec512", resultInArg0: false},
- {name: "VRSQRT14PD512", argLength: 1, reg: w11, asm: "VRSQRT14PD", commutative: false, typ: "Vec512", resultInArg0: false},
- {name: "VRSQRT14PDMasked512", argLength: 2, reg: wkw, asm: "VRSQRT14PD", commutative: false, typ: "Vec512", resultInArg0: false},
- {name: "VCOMPRESSPDMasked512", argLength: 2, reg: wkw, asm: "VCOMPRESSPD", commutative: false, typ: "Vec512", resultInArg0: false},
- {name: "VDIVPD512", argLength: 2, reg: w21, asm: "VDIVPD", commutative: false, typ: "Vec512", resultInArg0: false},
- {name: "VDIVPDMasked512", argLength: 3, reg: w2kw, asm: "VDIVPD", commutative: false, typ: "Vec512", resultInArg0: false},
- {name: "VFMADD213PD512", argLength: 3, reg: w31, asm: "VFMADD213PD", commutative: false, typ: "Vec512", resultInArg0: true},
- {name: "VFMADD213PDMasked512", argLength: 4, reg: w3kw, asm: "VFMADD213PD", commutative: false, typ: "Vec512", resultInArg0: true},
- {name: "VFMADDSUB213PD512", argLength: 3, reg: w31, asm: "VFMADDSUB213PD", commutative: false, typ: "Vec512", resultInArg0: true},
- {name: "VFMADDSUB213PDMasked512", argLength: 4, reg: w3kw, asm: "VFMADDSUB213PD", commutative: false, typ: "Vec512", resultInArg0: true},
- {name: "VFMSUBADD213PD512", argLength: 3, reg: w31, asm: "VFMSUBADD213PD", commutative: false, typ: "Vec512", resultInArg0: true},
- {name: "VFMSUBADD213PDMasked512", argLength: 4, reg: w3kw, asm: "VFMSUBADD213PD", commutative: false, typ: "Vec512", resultInArg0: true},
{name: "VMAXPD512", argLength: 2, reg: w21, asm: "VMAXPD", commutative: true, typ: "Vec512", resultInArg0: false},
+ {name: "VMAXPDMasked128", argLength: 3, reg: w2kw, asm: "VMAXPD", commutative: true, typ: "Vec128", resultInArg0: false},
+ {name: "VMAXPDMasked256", argLength: 3, reg: w2kw, asm: "VMAXPD", commutative: true, typ: "Vec256", resultInArg0: false},
{name: "VMAXPDMasked512", argLength: 3, reg: w2kw, asm: "VMAXPD", commutative: true, typ: "Vec512", resultInArg0: false},
+ {name: "VMAXPS128", argLength: 2, reg: v21, asm: "VMAXPS", commutative: true, typ: "Vec128", resultInArg0: false},
+ {name: "VMAXPS256", argLength: 2, reg: v21, asm: "VMAXPS", commutative: true, typ: "Vec256", resultInArg0: false},
+ {name: "VMAXPS512", argLength: 2, reg: w21, asm: "VMAXPS", commutative: true, typ: "Vec512", resultInArg0: false},
+ {name: "VMAXPSMasked128", argLength: 3, reg: w2kw, asm: "VMAXPS", commutative: true, typ: "Vec128", resultInArg0: false},
+ {name: "VMAXPSMasked256", argLength: 3, reg: w2kw, asm: "VMAXPS", commutative: true, typ: "Vec256", resultInArg0: false},
+ {name: "VMAXPSMasked512", argLength: 3, reg: w2kw, asm: "VMAXPS", commutative: true, typ: "Vec512", resultInArg0: false},
+ {name: "VMINPD128", argLength: 2, reg: v21, asm: "VMINPD", commutative: true, typ: "Vec128", resultInArg0: false},
+ {name: "VMINPD256", argLength: 2, reg: v21, asm: "VMINPD", commutative: true, typ: "Vec256", resultInArg0: false},
{name: "VMINPD512", argLength: 2, reg: w21, asm: "VMINPD", commutative: true, typ: "Vec512", resultInArg0: false},
+ {name: "VMINPDMasked128", argLength: 3, reg: w2kw, asm: "VMINPD", commutative: true, typ: "Vec128", resultInArg0: false},
+ {name: "VMINPDMasked256", argLength: 3, reg: w2kw, asm: "VMINPD", commutative: true, typ: "Vec256", resultInArg0: false},
{name: "VMINPDMasked512", argLength: 3, reg: w2kw, asm: "VMINPD", commutative: true, typ: "Vec512", resultInArg0: false},
+ {name: "VMINPS128", argLength: 2, reg: v21, asm: "VMINPS", commutative: true, typ: "Vec128", resultInArg0: false},
+ {name: "VMINPS256", argLength: 2, reg: v21, asm: "VMINPS", commutative: true, typ: "Vec256", resultInArg0: false},
+ {name: "VMINPS512", argLength: 2, reg: w21, asm: "VMINPS", commutative: true, typ: "Vec512", resultInArg0: false},
+ {name: "VMINPSMasked128", argLength: 3, reg: w2kw, asm: "VMINPS", commutative: true, typ: "Vec128", resultInArg0: false},
+ {name: "VMINPSMasked256", argLength: 3, reg: w2kw, asm: "VMINPS", commutative: true, typ: "Vec256", resultInArg0: false},
+ {name: "VMINPSMasked512", argLength: 3, reg: w2kw, asm: "VMINPS", commutative: true, typ: "Vec512", resultInArg0: false},
+ {name: "VMULPD128", argLength: 2, reg: v21, asm: "VMULPD", commutative: true, typ: "Vec128", resultInArg0: false},
+ {name: "VMULPD256", argLength: 2, reg: v21, asm: "VMULPD", commutative: true, typ: "Vec256", resultInArg0: false},
{name: "VMULPD512", argLength: 2, reg: w21, asm: "VMULPD", commutative: true, typ: "Vec512", resultInArg0: false},
- {name: "VSCALEFPD512", argLength: 2, reg: w21, asm: "VSCALEFPD", commutative: false, typ: "Vec512", resultInArg0: false},
- {name: "VSCALEFPDMasked512", argLength: 3, reg: w2kw, asm: "VSCALEFPD", commutative: false, typ: "Vec512", resultInArg0: false},
+ {name: "VMULPDMasked128", argLength: 3, reg: w2kw, asm: "VMULPD", commutative: true, typ: "Vec128", resultInArg0: false},
+ {name: "VMULPDMasked256", argLength: 3, reg: w2kw, asm: "VMULPD", commutative: true, typ: "Vec256", resultInArg0: false},
{name: "VMULPDMasked512", argLength: 3, reg: w2kw, asm: "VMULPD", commutative: true, typ: "Vec512", resultInArg0: false},
- {name: "VSQRTPD512", argLength: 1, reg: w11, asm: "VSQRTPD", commutative: false, typ: "Vec512", resultInArg0: false},
- {name: "VSQRTPDMasked512", argLength: 2, reg: wkw, asm: "VSQRTPD", commutative: false, typ: "Vec512", resultInArg0: false},
- {name: "VSUBPD512", argLength: 2, reg: w21, asm: "VSUBPD", commutative: false, typ: "Vec512", resultInArg0: false},
- {name: "VSUBPDMasked512", argLength: 3, reg: w2kw, asm: "VSUBPD", commutative: false, typ: "Vec512", resultInArg0: false},
- {name: "VPABSW256", argLength: 1, reg: v11, asm: "VPABSW", commutative: false, typ: "Vec256", resultInArg0: false},
- {name: "VPABSWMasked256", argLength: 2, reg: wkw, asm: "VPABSW", commutative: false, typ: "Vec256", resultInArg0: false},
- {name: "VPADDW256", argLength: 2, reg: v21, asm: "VPADDW", commutative: true, typ: "Vec256", resultInArg0: false},
- {name: "VPADDWMasked256", argLength: 3, reg: w2kw, asm: "VPADDW", commutative: true, typ: "Vec256", resultInArg0: false},
- {name: "VPCOMPRESSWMasked256", argLength: 2, reg: wkw, asm: "VPCOMPRESSW", commutative: false, typ: "Vec256", resultInArg0: false},
- {name: "VPCMPEQW256", argLength: 2, reg: v21, asm: "VPCMPEQW", commutative: true, typ: "Vec256", resultInArg0: false},
- {name: "VPCMPGTW256", argLength: 2, reg: v21, asm: "VPCMPGTW", commutative: false, typ: "Vec256", resultInArg0: false},
- {name: "VPMAXSW256", argLength: 2, reg: v21, asm: "VPMAXSW", commutative: true, typ: "Vec256", resultInArg0: false},
- {name: "VPMAXSWMasked256", argLength: 3, reg: w2kw, asm: "VPMAXSW", commutative: true, typ: "Vec256", resultInArg0: false},
- {name: "VPMINSW256", argLength: 2, reg: v21, asm: "VPMINSW", commutative: true, typ: "Vec256", resultInArg0: false},
- {name: "VPMINSWMasked256", argLength: 3, reg: w2kw, asm: "VPMINSW", commutative: true, typ: "Vec256", resultInArg0: false},
- {name: "VPMULHW256", argLength: 2, reg: v21, asm: "VPMULHW", commutative: true, typ: "Vec256", resultInArg0: false},
- {name: "VPMULHWMasked256", argLength: 3, reg: w2kw, asm: "VPMULHW", commutative: true, typ: "Vec256", resultInArg0: false},
- {name: "VPMULLW256", argLength: 2, reg: v21, asm: "VPMULLW", commutative: true, typ: "Vec256", resultInArg0: false},
- {name: "VPMULLWMasked256", argLength: 3, reg: w2kw, asm: "VPMULLW", commutative: true, typ: "Vec256", resultInArg0: false},
- {name: "VPMADDWD256", argLength: 2, reg: v21, asm: "VPMADDWD", commutative: false, typ: "Vec256", resultInArg0: false},
- {name: "VPMADDWDMasked256", argLength: 3, reg: w2kw, asm: "VPMADDWD", commutative: false, typ: "Vec256", resultInArg0: false},
- {name: "VPHADDW256", argLength: 2, reg: v21, asm: "VPHADDW", commutative: false, typ: "Vec256", resultInArg0: false},
- {name: "VPHSUBW256", argLength: 2, reg: v21, asm: "VPHSUBW", commutative: false, typ: "Vec256", resultInArg0: false},
- {name: "VPOPCNTW256", argLength: 1, reg: w11, asm: "VPOPCNTW", commutative: false, typ: "Vec256", resultInArg0: false},
- {name: "VPOPCNTWMasked256", argLength: 2, reg: wkw, asm: "VPOPCNTW", commutative: false, typ: "Vec256", resultInArg0: false},
- {name: "VPADDSW256", argLength: 2, reg: v21, asm: "VPADDSW", commutative: true, typ: "Vec256", resultInArg0: false},
- {name: "VPADDSWMasked256", argLength: 3, reg: w2kw, asm: "VPADDSW", commutative: true, typ: "Vec256", resultInArg0: false},
- {name: "VPHADDSW256", argLength: 2, reg: v21, asm: "VPHADDSW", commutative: false, typ: "Vec256", resultInArg0: false},
- {name: "VPHSUBSW256", argLength: 2, reg: v21, asm: "VPHSUBSW", commutative: false, typ: "Vec256", resultInArg0: false},
- {name: "VPSUBSW256", argLength: 2, reg: v21, asm: "VPSUBSW", commutative: false, typ: "Vec256", resultInArg0: false},
- {name: "VPSUBSWMasked256", argLength: 3, reg: w2kw, asm: "VPSUBSW", commutative: false, typ: "Vec256", resultInArg0: false},
- {name: "VPSLLW256", argLength: 2, reg: vfpv, asm: "VPSLLW", commutative: false, typ: "Vec256", resultInArg0: false},
- {name: "VPSLLWMasked256", argLength: 3, reg: wfpkw, asm: "VPSLLW", commutative: false, typ: "Vec256", resultInArg0: false},
- {name: "VPSRAW256", argLength: 2, reg: vfpv, asm: "VPSRAW", commutative: false, typ: "Vec256", resultInArg0: false},
- {name: "VPSRAWMasked256", argLength: 3, reg: wfpkw, asm: "VPSRAW", commutative: false, typ: "Vec256", resultInArg0: false},
- {name: "VPSLLVW256", argLength: 2, reg: w21, asm: "VPSLLVW", commutative: false, typ: "Vec256", resultInArg0: false},
- {name: "VPSHLDVW256", argLength: 3, reg: w31, asm: "VPSHLDVW", commutative: false, typ: "Vec256", resultInArg0: true},
- {name: "VPSHLDVWMasked256", argLength: 4, reg: w3kw, asm: "VPSHLDVW", commutative: false, typ: "Vec256", resultInArg0: true},
- {name: "VPSLLVWMasked256", argLength: 3, reg: w2kw, asm: "VPSLLVW", commutative: false, typ: "Vec256", resultInArg0: false},
- {name: "VPSRAVW256", argLength: 2, reg: w21, asm: "VPSRAVW", commutative: false, typ: "Vec256", resultInArg0: false},
- {name: "VPSHRDVW256", argLength: 3, reg: w31, asm: "VPSHRDVW", commutative: false, typ: "Vec256", resultInArg0: true},
- {name: "VPSHRDVWMasked256", argLength: 4, reg: w3kw, asm: "VPSHRDVW", commutative: false, typ: "Vec256", resultInArg0: true},
- {name: "VPSRAVWMasked256", argLength: 3, reg: w2kw, asm: "VPSRAVW", commutative: false, typ: "Vec256", resultInArg0: false},
- {name: "VPSIGNW256", argLength: 2, reg: v21, asm: "VPSIGNW", commutative: false, typ: "Vec256", resultInArg0: false},
- {name: "VPSUBW256", argLength: 2, reg: v21, asm: "VPSUBW", commutative: false, typ: "Vec256", resultInArg0: false},
- {name: "VPSUBWMasked256", argLength: 3, reg: w2kw, asm: "VPSUBW", commutative: false, typ: "Vec256", resultInArg0: false},
+ {name: "VMULPS128", argLength: 2, reg: v21, asm: "VMULPS", commutative: true, typ: "Vec128", resultInArg0: false},
+ {name: "VMULPS256", argLength: 2, reg: v21, asm: "VMULPS", commutative: true, typ: "Vec256", resultInArg0: false},
+ {name: "VMULPS512", argLength: 2, reg: w21, asm: "VMULPS", commutative: true, typ: "Vec512", resultInArg0: false},
+ {name: "VMULPSMasked128", argLength: 3, reg: w2kw, asm: "VMULPS", commutative: true, typ: "Vec128", resultInArg0: false},
+ {name: "VMULPSMasked256", argLength: 3, reg: w2kw, asm: "VMULPS", commutative: true, typ: "Vec256", resultInArg0: false},
+ {name: "VMULPSMasked512", argLength: 3, reg: w2kw, asm: "VMULPS", commutative: true, typ: "Vec512", resultInArg0: false},
+ {name: "VPABSB128", argLength: 1, reg: v11, asm: "VPABSB", commutative: false, typ: "Vec128", resultInArg0: false},
+ {name: "VPABSB256", argLength: 1, reg: v11, asm: "VPABSB", commutative: false, typ: "Vec256", resultInArg0: false},
+ {name: "VPABSB512", argLength: 1, reg: w11, asm: "VPABSB", commutative: false, typ: "Vec512", resultInArg0: false},
+ {name: "VPABSBMasked128", argLength: 2, reg: wkw, asm: "VPABSB", commutative: false, typ: "Vec128", resultInArg0: false},
+ {name: "VPABSBMasked256", argLength: 2, reg: wkw, asm: "VPABSB", commutative: false, typ: "Vec256", resultInArg0: false},
+ {name: "VPABSBMasked512", argLength: 2, reg: wkw, asm: "VPABSB", commutative: false, typ: "Vec512", resultInArg0: false},
+ {name: "VPABSD128", argLength: 1, reg: v11, asm: "VPABSD", commutative: false, typ: "Vec128", resultInArg0: false},
+ {name: "VPABSD256", argLength: 1, reg: v11, asm: "VPABSD", commutative: false, typ: "Vec256", resultInArg0: false},
+ {name: "VPABSD512", argLength: 1, reg: w11, asm: "VPABSD", commutative: false, typ: "Vec512", resultInArg0: false},
+ {name: "VPABSDMasked128", argLength: 2, reg: wkw, asm: "VPABSD", commutative: false, typ: "Vec128", resultInArg0: false},
+ {name: "VPABSDMasked256", argLength: 2, reg: wkw, asm: "VPABSD", commutative: false, typ: "Vec256", resultInArg0: false},
+ {name: "VPABSDMasked512", argLength: 2, reg: wkw, asm: "VPABSD", commutative: false, typ: "Vec512", resultInArg0: false},
+ {name: "VPABSQ128", argLength: 1, reg: w11, asm: "VPABSQ", commutative: false, typ: "Vec128", resultInArg0: false},
+ {name: "VPABSQ256", argLength: 1, reg: w11, asm: "VPABSQ", commutative: false, typ: "Vec256", resultInArg0: false},
+ {name: "VPABSQ512", argLength: 1, reg: w11, asm: "VPABSQ", commutative: false, typ: "Vec512", resultInArg0: false},
+ {name: "VPABSQMasked128", argLength: 2, reg: wkw, asm: "VPABSQ", commutative: false, typ: "Vec128", resultInArg0: false},
+ {name: "VPABSQMasked256", argLength: 2, reg: wkw, asm: "VPABSQ", commutative: false, typ: "Vec256", resultInArg0: false},
+ {name: "VPABSQMasked512", argLength: 2, reg: wkw, asm: "VPABSQ", commutative: false, typ: "Vec512", resultInArg0: false},
+ {name: "VPABSW128", argLength: 1, reg: v11, asm: "VPABSW", commutative: false, typ: "Vec128", resultInArg0: false},
+ {name: "VPABSW256", argLength: 1, reg: v11, asm: "VPABSW", commutative: false, typ: "Vec256", resultInArg0: false},
{name: "VPABSW512", argLength: 1, reg: w11, asm: "VPABSW", commutative: false, typ: "Vec512", resultInArg0: false},
+ {name: "VPABSWMasked128", argLength: 2, reg: wkw, asm: "VPABSW", commutative: false, typ: "Vec128", resultInArg0: false},
+ {name: "VPABSWMasked256", argLength: 2, reg: wkw, asm: "VPABSW", commutative: false, typ: "Vec256", resultInArg0: false},
{name: "VPABSWMasked512", argLength: 2, reg: wkw, asm: "VPABSW", commutative: false, typ: "Vec512", resultInArg0: false},
- {name: "VPADDW512", argLength: 2, reg: w21, asm: "VPADDW", commutative: true, typ: "Vec512", resultInArg0: false},
- {name: "VPADDWMasked512", argLength: 3, reg: w2kw, asm: "VPADDW", commutative: true, typ: "Vec512", resultInArg0: false},
- {name: "VPCOMPRESSWMasked512", argLength: 2, reg: wkw, asm: "VPCOMPRESSW", commutative: false, typ: "Vec512", resultInArg0: false},
- {name: "VPCMPEQW512", argLength: 2, reg: w2k, asm: "VPCMPEQW", commutative: true, typ: "Mask", resultInArg0: false},
- {name: "VPCMPGTW512", argLength: 2, reg: w2k, asm: "VPCMPGTW", commutative: false, typ: "Mask", resultInArg0: false},
- {name: "VPMAXSW512", argLength: 2, reg: w21, asm: "VPMAXSW", commutative: true, typ: "Vec512", resultInArg0: false},
- {name: "VPMAXSWMasked512", argLength: 3, reg: w2kw, asm: "VPMAXSW", commutative: true, typ: "Vec512", resultInArg0: false},
- {name: "VPMINSW512", argLength: 2, reg: w21, asm: "VPMINSW", commutative: true, typ: "Vec512", resultInArg0: false},
- {name: "VPMINSWMasked512", argLength: 3, reg: w2kw, asm: "VPMINSW", commutative: true, typ: "Vec512", resultInArg0: false},
- {name: "VPMULHW512", argLength: 2, reg: w21, asm: "VPMULHW", commutative: true, typ: "Vec512", resultInArg0: false},
- {name: "VPMULHWMasked512", argLength: 3, reg: w2kw, asm: "VPMULHW", commutative: true, typ: "Vec512", resultInArg0: false},
- {name: "VPMULLW512", argLength: 2, reg: w21, asm: "VPMULLW", commutative: true, typ: "Vec512", resultInArg0: false},
- {name: "VPMULLWMasked512", argLength: 3, reg: w2kw, asm: "VPMULLW", commutative: true, typ: "Vec512", resultInArg0: false},
- {name: "VPMADDWD512", argLength: 2, reg: w21, asm: "VPMADDWD", commutative: false, typ: "Vec512", resultInArg0: false},
- {name: "VPMADDWDMasked512", argLength: 3, reg: w2kw, asm: "VPMADDWD", commutative: false, typ: "Vec512", resultInArg0: false},
- {name: "VPOPCNTW512", argLength: 1, reg: w11, asm: "VPOPCNTW", commutative: false, typ: "Vec512", resultInArg0: false},
- {name: "VPOPCNTWMasked512", argLength: 2, reg: wkw, asm: "VPOPCNTW", commutative: false, typ: "Vec512", resultInArg0: false},
+ {name: "VPADDB128", argLength: 2, reg: v21, asm: "VPADDB", commutative: true, typ: "Vec128", resultInArg0: false},
+ {name: "VPADDB256", argLength: 2, reg: v21, asm: "VPADDB", commutative: true, typ: "Vec256", resultInArg0: false},
+ {name: "VPADDB512", argLength: 2, reg: w21, asm: "VPADDB", commutative: true, typ: "Vec512", resultInArg0: false},
+ {name: "VPADDBMasked128", argLength: 3, reg: w2kw, asm: "VPADDB", commutative: true, typ: "Vec128", resultInArg0: false},
+ {name: "VPADDBMasked256", argLength: 3, reg: w2kw, asm: "VPADDB", commutative: true, typ: "Vec256", resultInArg0: false},
+ {name: "VPADDBMasked512", argLength: 3, reg: w2kw, asm: "VPADDB", commutative: true, typ: "Vec512", resultInArg0: false},
+ {name: "VPADDD128", argLength: 2, reg: v21, asm: "VPADDD", commutative: true, typ: "Vec128", resultInArg0: false},
+ {name: "VPADDD256", argLength: 2, reg: v21, asm: "VPADDD", commutative: true, typ: "Vec256", resultInArg0: false},
+ {name: "VPADDD512", argLength: 2, reg: w21, asm: "VPADDD", commutative: true, typ: "Vec512", resultInArg0: false},
+ {name: "VPADDDMasked128", argLength: 3, reg: w2kw, asm: "VPADDD", commutative: true, typ: "Vec128", resultInArg0: false},
+ {name: "VPADDDMasked256", argLength: 3, reg: w2kw, asm: "VPADDD", commutative: true, typ: "Vec256", resultInArg0: false},
+ {name: "VPADDDMasked512", argLength: 3, reg: w2kw, asm: "VPADDD", commutative: true, typ: "Vec512", resultInArg0: false},
+ {name: "VPADDQ128", argLength: 2, reg: v21, asm: "VPADDQ", commutative: true, typ: "Vec128", resultInArg0: false},
+ {name: "VPADDQ256", argLength: 2, reg: v21, asm: "VPADDQ", commutative: true, typ: "Vec256", resultInArg0: false},
+ {name: "VPADDQ512", argLength: 2, reg: w21, asm: "VPADDQ", commutative: true, typ: "Vec512", resultInArg0: false},
+ {name: "VPADDQMasked128", argLength: 3, reg: w2kw, asm: "VPADDQ", commutative: true, typ: "Vec128", resultInArg0: false},
+ {name: "VPADDQMasked256", argLength: 3, reg: w2kw, asm: "VPADDQ", commutative: true, typ: "Vec256", resultInArg0: false},
+ {name: "VPADDQMasked512", argLength: 3, reg: w2kw, asm: "VPADDQ", commutative: true, typ: "Vec512", resultInArg0: false},
+ {name: "VPADDSB128", argLength: 2, reg: v21, asm: "VPADDSB", commutative: true, typ: "Vec128", resultInArg0: false},
+ {name: "VPADDSB256", argLength: 2, reg: v21, asm: "VPADDSB", commutative: true, typ: "Vec256", resultInArg0: false},
+ {name: "VPADDSB512", argLength: 2, reg: w21, asm: "VPADDSB", commutative: true, typ: "Vec512", resultInArg0: false},
+ {name: "VPADDSBMasked128", argLength: 3, reg: w2kw, asm: "VPADDSB", commutative: true, typ: "Vec128", resultInArg0: false},
+ {name: "VPADDSBMasked256", argLength: 3, reg: w2kw, asm: "VPADDSB", commutative: true, typ: "Vec256", resultInArg0: false},
+ {name: "VPADDSBMasked512", argLength: 3, reg: w2kw, asm: "VPADDSB", commutative: true, typ: "Vec512", resultInArg0: false},
+ {name: "VPADDSW128", argLength: 2, reg: v21, asm: "VPADDSW", commutative: true, typ: "Vec128", resultInArg0: false},
+ {name: "VPADDSW256", argLength: 2, reg: v21, asm: "VPADDSW", commutative: true, typ: "Vec256", resultInArg0: false},
{name: "VPADDSW512", argLength: 2, reg: w21, asm: "VPADDSW", commutative: true, typ: "Vec512", resultInArg0: false},
+ {name: "VPADDSWMasked128", argLength: 3, reg: w2kw, asm: "VPADDSW", commutative: true, typ: "Vec128", resultInArg0: false},
+ {name: "VPADDSWMasked256", argLength: 3, reg: w2kw, asm: "VPADDSW", commutative: true, typ: "Vec256", resultInArg0: false},
{name: "VPADDSWMasked512", argLength: 3, reg: w2kw, asm: "VPADDSW", commutative: true, typ: "Vec512", resultInArg0: false},
- {name: "VPSUBSW512", argLength: 2, reg: w21, asm: "VPSUBSW", commutative: false, typ: "Vec512", resultInArg0: false},
- {name: "VPSUBSWMasked512", argLength: 3, reg: w2kw, asm: "VPSUBSW", commutative: false, typ: "Vec512", resultInArg0: false},
- {name: "VPSLLW512", argLength: 2, reg: wfpw, asm: "VPSLLW", commutative: false, typ: "Vec512", resultInArg0: false},
- {name: "VPSLLWMasked512", argLength: 3, reg: wfpkw, asm: "VPSLLW", commutative: false, typ: "Vec512", resultInArg0: false},
- {name: "VPSRAW512", argLength: 2, reg: wfpw, asm: "VPSRAW", commutative: false, typ: "Vec512", resultInArg0: false},
- {name: "VPSRAWMasked512", argLength: 3, reg: wfpkw, asm: "VPSRAW", commutative: false, typ: "Vec512", resultInArg0: false},
- {name: "VPSLLVW512", argLength: 2, reg: w21, asm: "VPSLLVW", commutative: false, typ: "Vec512", resultInArg0: false},
- {name: "VPSHLDVW512", argLength: 3, reg: w31, asm: "VPSHLDVW", commutative: false, typ: "Vec512", resultInArg0: true},
- {name: "VPSHLDVWMasked512", argLength: 4, reg: w3kw, asm: "VPSHLDVW", commutative: false, typ: "Vec512", resultInArg0: true},
- {name: "VPSLLVWMasked512", argLength: 3, reg: w2kw, asm: "VPSLLVW", commutative: false, typ: "Vec512", resultInArg0: false},
- {name: "VPSRAVW512", argLength: 2, reg: w21, asm: "VPSRAVW", commutative: false, typ: "Vec512", resultInArg0: false},
- {name: "VPSHRDVW512", argLength: 3, reg: w31, asm: "VPSHRDVW", commutative: false, typ: "Vec512", resultInArg0: true},
- {name: "VPSHRDVWMasked512", argLength: 4, reg: w3kw, asm: "VPSHRDVW", commutative: false, typ: "Vec512", resultInArg0: true},
- {name: "VPSRAVWMasked512", argLength: 3, reg: w2kw, asm: "VPSRAVW", commutative: false, typ: "Vec512", resultInArg0: false},
- {name: "VPSUBW512", argLength: 2, reg: w21, asm: "VPSUBW", commutative: false, typ: "Vec512", resultInArg0: false},
- {name: "VPSUBWMasked512", argLength: 3, reg: w2kw, asm: "VPSUBW", commutative: false, typ: "Vec512", resultInArg0: false},
- {name: "VPABSW128", argLength: 1, reg: v11, asm: "VPABSW", commutative: false, typ: "Vec128", resultInArg0: false},
- {name: "VPABSWMasked128", argLength: 2, reg: wkw, asm: "VPABSW", commutative: false, typ: "Vec128", resultInArg0: false},
{name: "VPADDW128", argLength: 2, reg: v21, asm: "VPADDW", commutative: true, typ: "Vec128", resultInArg0: false},
+ {name: "VPADDW256", argLength: 2, reg: v21, asm: "VPADDW", commutative: true, typ: "Vec256", resultInArg0: false},
+ {name: "VPADDW512", argLength: 2, reg: w21, asm: "VPADDW", commutative: true, typ: "Vec512", resultInArg0: false},
{name: "VPADDWMasked128", argLength: 3, reg: w2kw, asm: "VPADDW", commutative: true, typ: "Vec128", resultInArg0: false},
- {name: "VPCOMPRESSWMasked128", argLength: 2, reg: wkw, asm: "VPCOMPRESSW", commutative: false, typ: "Vec128", resultInArg0: false},
- {name: "VPCMPEQW128", argLength: 2, reg: v21, asm: "VPCMPEQW", commutative: true, typ: "Vec128", resultInArg0: false},
- {name: "VPCMPGTW128", argLength: 2, reg: v21, asm: "VPCMPGTW", commutative: false, typ: "Vec128", resultInArg0: false},
- {name: "VPMAXSW128", argLength: 2, reg: v21, asm: "VPMAXSW", commutative: true, typ: "Vec128", resultInArg0: false},
- {name: "VPMAXSWMasked128", argLength: 3, reg: w2kw, asm: "VPMAXSW", commutative: true, typ: "Vec128", resultInArg0: false},
- {name: "VPMINSW128", argLength: 2, reg: v21, asm: "VPMINSW", commutative: true, typ: "Vec128", resultInArg0: false},
- {name: "VPMINSWMasked128", argLength: 3, reg: w2kw, asm: "VPMINSW", commutative: true, typ: "Vec128", resultInArg0: false},
- {name: "VPMULHW128", argLength: 2, reg: v21, asm: "VPMULHW", commutative: true, typ: "Vec128", resultInArg0: false},
- {name: "VPMULHWMasked128", argLength: 3, reg: w2kw, asm: "VPMULHW", commutative: true, typ: "Vec128", resultInArg0: false},
- {name: "VPMULLW128", argLength: 2, reg: v21, asm: "VPMULLW", commutative: true, typ: "Vec128", resultInArg0: false},
- {name: "VPMULLWMasked128", argLength: 3, reg: w2kw, asm: "VPMULLW", commutative: true, typ: "Vec128", resultInArg0: false},
- {name: "VPMADDWD128", argLength: 2, reg: v21, asm: "VPMADDWD", commutative: false, typ: "Vec128", resultInArg0: false},
- {name: "VPMADDWDMasked128", argLength: 3, reg: w2kw, asm: "VPMADDWD", commutative: false, typ: "Vec128", resultInArg0: false},
- {name: "VPHADDW128", argLength: 2, reg: v21, asm: "VPHADDW", commutative: false, typ: "Vec128", resultInArg0: false},
- {name: "VPHSUBW128", argLength: 2, reg: v21, asm: "VPHSUBW", commutative: false, typ: "Vec128", resultInArg0: false},
- {name: "VPOPCNTW128", argLength: 1, reg: w11, asm: "VPOPCNTW", commutative: false, typ: "Vec128", resultInArg0: false},
- {name: "VPOPCNTWMasked128", argLength: 2, reg: wkw, asm: "VPOPCNTW", commutative: false, typ: "Vec128", resultInArg0: false},
- {name: "VPADDSW128", argLength: 2, reg: v21, asm: "VPADDSW", commutative: true, typ: "Vec128", resultInArg0: false},
- {name: "VPADDSWMasked128", argLength: 3, reg: w2kw, asm: "VPADDSW", commutative: true, typ: "Vec128", resultInArg0: false},
- {name: "VPHADDSW128", argLength: 2, reg: v21, asm: "VPHADDSW", commutative: false, typ: "Vec128", resultInArg0: false},
- {name: "VPHSUBSW128", argLength: 2, reg: v21, asm: "VPHSUBSW", commutative: false, typ: "Vec128", resultInArg0: false},
- {name: "VPSUBSW128", argLength: 2, reg: v21, asm: "VPSUBSW", commutative: false, typ: "Vec128", resultInArg0: false},
- {name: "VPSUBSWMasked128", argLength: 3, reg: w2kw, asm: "VPSUBSW", commutative: false, typ: "Vec128", resultInArg0: false},
- {name: "VPSLLW128", argLength: 2, reg: vfpv, asm: "VPSLLW", commutative: false, typ: "Vec128", resultInArg0: false},
- {name: "VPSLLWMasked128", argLength: 3, reg: wfpkw, asm: "VPSLLW", commutative: false, typ: "Vec128", resultInArg0: false},
- {name: "VPSRAW128", argLength: 2, reg: vfpv, asm: "VPSRAW", commutative: false, typ: "Vec128", resultInArg0: false},
- {name: "VPSRAWMasked128", argLength: 3, reg: wfpkw, asm: "VPSRAW", commutative: false, typ: "Vec128", resultInArg0: false},
- {name: "VPSLLVW128", argLength: 2, reg: w21, asm: "VPSLLVW", commutative: false, typ: "Vec128", resultInArg0: false},
- {name: "VPSHLDVW128", argLength: 3, reg: w31, asm: "VPSHLDVW", commutative: false, typ: "Vec128", resultInArg0: true},
- {name: "VPSHLDVWMasked128", argLength: 4, reg: w3kw, asm: "VPSHLDVW", commutative: false, typ: "Vec128", resultInArg0: true},
- {name: "VPSLLVWMasked128", argLength: 3, reg: w2kw, asm: "VPSLLVW", commutative: false, typ: "Vec128", resultInArg0: false},
- {name: "VPSRAVW128", argLength: 2, reg: w21, asm: "VPSRAVW", commutative: false, typ: "Vec128", resultInArg0: false},
- {name: "VPSHRDVW128", argLength: 3, reg: w31, asm: "VPSHRDVW", commutative: false, typ: "Vec128", resultInArg0: true},
- {name: "VPSHRDVWMasked128", argLength: 4, reg: w3kw, asm: "VPSHRDVW", commutative: false, typ: "Vec128", resultInArg0: true},
- {name: "VPSRAVWMasked128", argLength: 3, reg: w2kw, asm: "VPSRAVW", commutative: false, typ: "Vec128", resultInArg0: false},
- {name: "VPSIGNW128", argLength: 2, reg: v21, asm: "VPSIGNW", commutative: false, typ: "Vec128", resultInArg0: false},
- {name: "VPSUBW128", argLength: 2, reg: v21, asm: "VPSUBW", commutative: false, typ: "Vec128", resultInArg0: false},
- {name: "VPSUBWMasked128", argLength: 3, reg: w2kw, asm: "VPSUBW", commutative: false, typ: "Vec128", resultInArg0: false},
- {name: "VPABSD512", argLength: 1, reg: w11, asm: "VPABSD", commutative: false, typ: "Vec512", resultInArg0: false},
- {name: "VPABSDMasked512", argLength: 2, reg: wkw, asm: "VPABSD", commutative: false, typ: "Vec512", resultInArg0: false},
- {name: "VPADDD512", argLength: 2, reg: w21, asm: "VPADDD", commutative: true, typ: "Vec512", resultInArg0: false},
- {name: "VPADDDMasked512", argLength: 3, reg: w2kw, asm: "VPADDD", commutative: true, typ: "Vec512", resultInArg0: false},
+ {name: "VPADDWMasked256", argLength: 3, reg: w2kw, asm: "VPADDW", commutative: true, typ: "Vec256", resultInArg0: false},
+ {name: "VPADDWMasked512", argLength: 3, reg: w2kw, asm: "VPADDW", commutative: true, typ: "Vec512", resultInArg0: false},
+ {name: "VPAND128", argLength: 2, reg: v21, asm: "VPAND", commutative: true, typ: "Vec128", resultInArg0: false},
+ {name: "VPAND256", argLength: 2, reg: v21, asm: "VPAND", commutative: true, typ: "Vec256", resultInArg0: false},
{name: "VPANDD512", argLength: 2, reg: w21, asm: "VPANDD", commutative: true, typ: "Vec512", resultInArg0: false},
+ {name: "VPANDDMasked128", argLength: 3, reg: w2kw, asm: "VPANDD", commutative: true, typ: "Vec128", resultInArg0: false},
+ {name: "VPANDDMasked256", argLength: 3, reg: w2kw, asm: "VPANDD", commutative: true, typ: "Vec256", resultInArg0: false},
{name: "VPANDDMasked512", argLength: 3, reg: w2kw, asm: "VPANDD", commutative: true, typ: "Vec512", resultInArg0: false},
+ {name: "VPANDN128", argLength: 2, reg: v21, asm: "VPANDN", commutative: false, typ: "Vec128", resultInArg0: false},
+ {name: "VPANDN256", argLength: 2, reg: v21, asm: "VPANDN", commutative: false, typ: "Vec256", resultInArg0: false},
{name: "VPANDND512", argLength: 2, reg: w21, asm: "VPANDND", commutative: false, typ: "Vec512", resultInArg0: false},
+ {name: "VPANDNDMasked128", argLength: 3, reg: w2kw, asm: "VPANDND", commutative: false, typ: "Vec128", resultInArg0: false},
+ {name: "VPANDNDMasked256", argLength: 3, reg: w2kw, asm: "VPANDND", commutative: false, typ: "Vec256", resultInArg0: false},
{name: "VPANDNDMasked512", argLength: 3, reg: w2kw, asm: "VPANDND", commutative: false, typ: "Vec512", resultInArg0: false},
- {name: "VPCOMPRESSDMasked512", argLength: 2, reg: wkw, asm: "VPCOMPRESSD", commutative: false, typ: "Vec512", resultInArg0: false},
+ {name: "VPANDNQ512", argLength: 2, reg: w21, asm: "VPANDNQ", commutative: false, typ: "Vec512", resultInArg0: false},
+ {name: "VPANDNQMasked128", argLength: 3, reg: w2kw, asm: "VPANDNQ", commutative: false, typ: "Vec128", resultInArg0: false},
+ {name: "VPANDNQMasked256", argLength: 3, reg: w2kw, asm: "VPANDNQ", commutative: false, typ: "Vec256", resultInArg0: false},
+ {name: "VPANDNQMasked512", argLength: 3, reg: w2kw, asm: "VPANDNQ", commutative: false, typ: "Vec512", resultInArg0: false},
+ {name: "VPANDQ512", argLength: 2, reg: w21, asm: "VPANDQ", commutative: true, typ: "Vec512", resultInArg0: false},
+ {name: "VPANDQMasked128", argLength: 3, reg: w2kw, asm: "VPANDQ", commutative: true, typ: "Vec128", resultInArg0: false},
+ {name: "VPANDQMasked256", argLength: 3, reg: w2kw, asm: "VPANDQ", commutative: true, typ: "Vec256", resultInArg0: false},
+ {name: "VPANDQMasked512", argLength: 3, reg: w2kw, asm: "VPANDQ", commutative: true, typ: "Vec512", resultInArg0: false},
+ {name: "VPAVGB128", argLength: 2, reg: v21, asm: "VPAVGB", commutative: true, typ: "Vec128", resultInArg0: false},
+ {name: "VPAVGB256", argLength: 2, reg: v21, asm: "VPAVGB", commutative: true, typ: "Vec256", resultInArg0: false},
+ {name: "VPAVGB512", argLength: 2, reg: w21, asm: "VPAVGB", commutative: true, typ: "Vec512", resultInArg0: false},
+ {name: "VPAVGBMasked128", argLength: 3, reg: w2kw, asm: "VPAVGB", commutative: true, typ: "Vec128", resultInArg0: false},
+ {name: "VPAVGBMasked256", argLength: 3, reg: w2kw, asm: "VPAVGB", commutative: true, typ: "Vec256", resultInArg0: false},
+ {name: "VPAVGBMasked512", argLength: 3, reg: w2kw, asm: "VPAVGB", commutative: true, typ: "Vec512", resultInArg0: false},
+ {name: "VPAVGW128", argLength: 2, reg: v21, asm: "VPAVGW", commutative: true, typ: "Vec128", resultInArg0: false},
+ {name: "VPAVGW256", argLength: 2, reg: v21, asm: "VPAVGW", commutative: true, typ: "Vec256", resultInArg0: false},
+ {name: "VPAVGW512", argLength: 2, reg: w21, asm: "VPAVGW", commutative: true, typ: "Vec512", resultInArg0: false},
+ {name: "VPAVGWMasked128", argLength: 3, reg: w2kw, asm: "VPAVGW", commutative: true, typ: "Vec128", resultInArg0: false},
+ {name: "VPAVGWMasked256", argLength: 3, reg: w2kw, asm: "VPAVGW", commutative: true, typ: "Vec256", resultInArg0: false},
+ {name: "VPAVGWMasked512", argLength: 3, reg: w2kw, asm: "VPAVGW", commutative: true, typ: "Vec512", resultInArg0: false},
+ {name: "VPCMPEQB128", argLength: 2, reg: v21, asm: "VPCMPEQB", commutative: true, typ: "Vec128", resultInArg0: false},
+ {name: "VPCMPEQB256", argLength: 2, reg: v21, asm: "VPCMPEQB", commutative: true, typ: "Vec256", resultInArg0: false},
+ {name: "VPCMPEQB512", argLength: 2, reg: w2k, asm: "VPCMPEQB", commutative: true, typ: "Mask", resultInArg0: false},
+ {name: "VPCMPEQD128", argLength: 2, reg: v21, asm: "VPCMPEQD", commutative: true, typ: "Vec128", resultInArg0: false},
+ {name: "VPCMPEQD256", argLength: 2, reg: v21, asm: "VPCMPEQD", commutative: true, typ: "Vec256", resultInArg0: false},
{name: "VPCMPEQD512", argLength: 2, reg: w2k, asm: "VPCMPEQD", commutative: true, typ: "Mask", resultInArg0: false},
+ {name: "VPCMPEQQ128", argLength: 2, reg: v21, asm: "VPCMPEQQ", commutative: true, typ: "Vec128", resultInArg0: false},
+ {name: "VPCMPEQQ256", argLength: 2, reg: v21, asm: "VPCMPEQQ", commutative: true, typ: "Vec256", resultInArg0: false},
+ {name: "VPCMPEQQ512", argLength: 2, reg: w2k, asm: "VPCMPEQQ", commutative: true, typ: "Mask", resultInArg0: false},
+ {name: "VPCMPEQW128", argLength: 2, reg: v21, asm: "VPCMPEQW", commutative: true, typ: "Vec128", resultInArg0: false},
+ {name: "VPCMPEQW256", argLength: 2, reg: v21, asm: "VPCMPEQW", commutative: true, typ: "Vec256", resultInArg0: false},
+ {name: "VPCMPEQW512", argLength: 2, reg: w2k, asm: "VPCMPEQW", commutative: true, typ: "Mask", resultInArg0: false},
+ {name: "VPCMPGTB128", argLength: 2, reg: v21, asm: "VPCMPGTB", commutative: false, typ: "Vec128", resultInArg0: false},
+ {name: "VPCMPGTB256", argLength: 2, reg: v21, asm: "VPCMPGTB", commutative: false, typ: "Vec256", resultInArg0: false},
+ {name: "VPCMPGTB512", argLength: 2, reg: w2k, asm: "VPCMPGTB", commutative: false, typ: "Mask", resultInArg0: false},
+ {name: "VPCMPGTD128", argLength: 2, reg: v21, asm: "VPCMPGTD", commutative: false, typ: "Vec128", resultInArg0: false},
+ {name: "VPCMPGTD256", argLength: 2, reg: v21, asm: "VPCMPGTD", commutative: false, typ: "Vec256", resultInArg0: false},
{name: "VPCMPGTD512", argLength: 2, reg: w2k, asm: "VPCMPGTD", commutative: false, typ: "Mask", resultInArg0: false},
- {name: "VPMAXSD512", argLength: 2, reg: w21, asm: "VPMAXSD", commutative: true, typ: "Vec512", resultInArg0: false},
- {name: "VPMAXSDMasked512", argLength: 3, reg: w2kw, asm: "VPMAXSD", commutative: true, typ: "Vec512", resultInArg0: false},
- {name: "VPMINSD512", argLength: 2, reg: w21, asm: "VPMINSD", commutative: true, typ: "Vec512", resultInArg0: false},
- {name: "VPMINSDMasked512", argLength: 3, reg: w2kw, asm: "VPMINSD", commutative: true, typ: "Vec512", resultInArg0: false},
- {name: "VPMULLD512", argLength: 2, reg: w21, asm: "VPMULLD", commutative: true, typ: "Vec512", resultInArg0: false},
- {name: "VPMULLDMasked512", argLength: 3, reg: w2kw, asm: "VPMULLD", commutative: true, typ: "Vec512", resultInArg0: false},
- {name: "VPORD512", argLength: 2, reg: w21, asm: "VPORD", commutative: true, typ: "Vec512", resultInArg0: false},
- {name: "VPORDMasked512", argLength: 3, reg: w2kw, asm: "VPORD", commutative: true, typ: "Vec512", resultInArg0: false},
- {name: "VPDPWSSD512", argLength: 3, reg: w31, asm: "VPDPWSSD", commutative: false, typ: "Vec512", resultInArg0: true},
- {name: "VPDPWSSDMasked512", argLength: 4, reg: w3kw, asm: "VPDPWSSD", commutative: false, typ: "Vec512", resultInArg0: true},
- {name: "VPOPCNTD512", argLength: 1, reg: w11, asm: "VPOPCNTD", commutative: false, typ: "Vec512", resultInArg0: false},
- {name: "VPOPCNTDMasked512", argLength: 2, reg: wkw, asm: "VPOPCNTD", commutative: false, typ: "Vec512", resultInArg0: false},
- {name: "VPROLVD512", argLength: 2, reg: w21, asm: "VPROLVD", commutative: false, typ: "Vec512", resultInArg0: false},
- {name: "VPROLVDMasked512", argLength: 3, reg: w2kw, asm: "VPROLVD", commutative: false, typ: "Vec512", resultInArg0: false},
- {name: "VPRORVD512", argLength: 2, reg: w21, asm: "VPRORVD", commutative: false, typ: "Vec512", resultInArg0: false},
- {name: "VPRORVDMasked512", argLength: 3, reg: w2kw, asm: "VPRORVD", commutative: false, typ: "Vec512", resultInArg0: false},
- {name: "VPDPWSSDS512", argLength: 3, reg: w31, asm: "VPDPWSSDS", commutative: false, typ: "Vec512", resultInArg0: true},
- {name: "VPDPWSSDSMasked512", argLength: 4, reg: w3kw, asm: "VPDPWSSDS", commutative: false, typ: "Vec512", resultInArg0: true},
+ {name: "VPCMPGTQ128", argLength: 2, reg: v21, asm: "VPCMPGTQ", commutative: false, typ: "Vec128", resultInArg0: false},
+ {name: "VPCMPGTQ256", argLength: 2, reg: v21, asm: "VPCMPGTQ", commutative: false, typ: "Vec256", resultInArg0: false},
+ {name: "VPCMPGTQ512", argLength: 2, reg: w2k, asm: "VPCMPGTQ", commutative: false, typ: "Mask", resultInArg0: false},
+ {name: "VPCMPGTW128", argLength: 2, reg: v21, asm: "VPCMPGTW", commutative: false, typ: "Vec128", resultInArg0: false},
+ {name: "VPCMPGTW256", argLength: 2, reg: v21, asm: "VPCMPGTW", commutative: false, typ: "Vec256", resultInArg0: false},
+ {name: "VPCMPGTW512", argLength: 2, reg: w2k, asm: "VPCMPGTW", commutative: false, typ: "Mask", resultInArg0: false},
+ {name: "VPCOMPRESSBMasked128", argLength: 2, reg: wkw, asm: "VPCOMPRESSB", commutative: false, typ: "Vec128", resultInArg0: false},
+ {name: "VPCOMPRESSBMasked256", argLength: 2, reg: wkw, asm: "VPCOMPRESSB", commutative: false, typ: "Vec256", resultInArg0: false},
+ {name: "VPCOMPRESSBMasked512", argLength: 2, reg: wkw, asm: "VPCOMPRESSB", commutative: false, typ: "Vec512", resultInArg0: false},
+ {name: "VPCOMPRESSDMasked128", argLength: 2, reg: wkw, asm: "VPCOMPRESSD", commutative: false, typ: "Vec128", resultInArg0: false},
+ {name: "VPCOMPRESSDMasked256", argLength: 2, reg: wkw, asm: "VPCOMPRESSD", commutative: false, typ: "Vec256", resultInArg0: false},
+ {name: "VPCOMPRESSDMasked512", argLength: 2, reg: wkw, asm: "VPCOMPRESSD", commutative: false, typ: "Vec512", resultInArg0: false},
+ {name: "VPCOMPRESSQMasked128", argLength: 2, reg: wkw, asm: "VPCOMPRESSQ", commutative: false, typ: "Vec128", resultInArg0: false},
+ {name: "VPCOMPRESSQMasked256", argLength: 2, reg: wkw, asm: "VPCOMPRESSQ", commutative: false, typ: "Vec256", resultInArg0: false},
+ {name: "VPCOMPRESSQMasked512", argLength: 2, reg: wkw, asm: "VPCOMPRESSQ", commutative: false, typ: "Vec512", resultInArg0: false},
+ {name: "VPCOMPRESSWMasked128", argLength: 2, reg: wkw, asm: "VPCOMPRESSW", commutative: false, typ: "Vec128", resultInArg0: false},
+ {name: "VPCOMPRESSWMasked256", argLength: 2, reg: wkw, asm: "VPCOMPRESSW", commutative: false, typ: "Vec256", resultInArg0: false},
+ {name: "VPCOMPRESSWMasked512", argLength: 2, reg: wkw, asm: "VPCOMPRESSW", commutative: false, typ: "Vec512", resultInArg0: false},
+ {name: "VPDPBUSD128", argLength: 3, reg: v31, asm: "VPDPBUSD", commutative: false, typ: "Vec128", resultInArg0: true},
+ {name: "VPDPBUSD256", argLength: 3, reg: v31, asm: "VPDPBUSD", commutative: false, typ: "Vec256", resultInArg0: true},
+ {name: "VPDPBUSD512", argLength: 3, reg: w31, asm: "VPDPBUSD", commutative: false, typ: "Vec512", resultInArg0: true},
+ {name: "VPDPBUSDMasked128", argLength: 4, reg: w3kw, asm: "VPDPBUSD", commutative: false, typ: "Vec128", resultInArg0: true},
+ {name: "VPDPBUSDMasked256", argLength: 4, reg: w3kw, asm: "VPDPBUSD", commutative: false, typ: "Vec256", resultInArg0: true},
+ {name: "VPDPBUSDMasked512", argLength: 4, reg: w3kw, asm: "VPDPBUSD", commutative: false, typ: "Vec512", resultInArg0: true},
+ {name: "VPDPBUSDS128", argLength: 3, reg: v31, asm: "VPDPBUSDS", commutative: false, typ: "Vec128", resultInArg0: true},
+ {name: "VPDPBUSDS256", argLength: 3, reg: v31, asm: "VPDPBUSDS", commutative: false, typ: "Vec256", resultInArg0: true},
{name: "VPDPBUSDS512", argLength: 3, reg: w31, asm: "VPDPBUSDS", commutative: false, typ: "Vec512", resultInArg0: true},
+ {name: "VPDPBUSDSMasked128", argLength: 4, reg: w3kw, asm: "VPDPBUSDS", commutative: false, typ: "Vec128", resultInArg0: true},
+ {name: "VPDPBUSDSMasked256", argLength: 4, reg: w3kw, asm: "VPDPBUSDS", commutative: false, typ: "Vec256", resultInArg0: true},
{name: "VPDPBUSDSMasked512", argLength: 4, reg: w3kw, asm: "VPDPBUSDS", commutative: false, typ: "Vec512", resultInArg0: true},
- {name: "VPSLLD512", argLength: 2, reg: wfpw, asm: "VPSLLD", commutative: false, typ: "Vec512", resultInArg0: false},
- {name: "VPSLLDMasked512", argLength: 3, reg: wfpkw, asm: "VPSLLD", commutative: false, typ: "Vec512", resultInArg0: false},
- {name: "VPSRAD512", argLength: 2, reg: wfpw, asm: "VPSRAD", commutative: false, typ: "Vec512", resultInArg0: false},
- {name: "VPSRADMasked512", argLength: 3, reg: wfpkw, asm: "VPSRAD", commutative: false, typ: "Vec512", resultInArg0: false},
- {name: "VPSLLVD512", argLength: 2, reg: w21, asm: "VPSLLVD", commutative: false, typ: "Vec512", resultInArg0: false},
- {name: "VPSHLDVD512", argLength: 3, reg: w31, asm: "VPSHLDVD", commutative: false, typ: "Vec512", resultInArg0: true},
- {name: "VPSHLDVDMasked512", argLength: 4, reg: w3kw, asm: "VPSHLDVD", commutative: false, typ: "Vec512", resultInArg0: true},
- {name: "VPSLLVDMasked512", argLength: 3, reg: w2kw, asm: "VPSLLVD", commutative: false, typ: "Vec512", resultInArg0: false},
- {name: "VPSRAVD512", argLength: 2, reg: w21, asm: "VPSRAVD", commutative: false, typ: "Vec512", resultInArg0: false},
- {name: "VPSHRDVD512", argLength: 3, reg: w31, asm: "VPSHRDVD", commutative: false, typ: "Vec512", resultInArg0: true},
- {name: "VPSHRDVDMasked512", argLength: 4, reg: w3kw, asm: "VPSHRDVD", commutative: false, typ: "Vec512", resultInArg0: true},
- {name: "VPSRAVDMasked512", argLength: 3, reg: w2kw, asm: "VPSRAVD", commutative: false, typ: "Vec512", resultInArg0: false},
- {name: "VPSUBD512", argLength: 2, reg: w21, asm: "VPSUBD", commutative: false, typ: "Vec512", resultInArg0: false},
- {name: "VPSUBDMasked512", argLength: 3, reg: w2kw, asm: "VPSUBD", commutative: false, typ: "Vec512", resultInArg0: false},
- {name: "VPDPBUSD512", argLength: 3, reg: w31, asm: "VPDPBUSD", commutative: false, typ: "Vec512", resultInArg0: true},
- {name: "VPDPBUSDMasked512", argLength: 4, reg: w3kw, asm: "VPDPBUSD", commutative: false, typ: "Vec512", resultInArg0: true},
- {name: "VPXORD512", argLength: 2, reg: w21, asm: "VPXORD", commutative: true, typ: "Vec512", resultInArg0: false},
- {name: "VPXORDMasked512", argLength: 3, reg: w2kw, asm: "VPXORD", commutative: true, typ: "Vec512", resultInArg0: false},
- {name: "VPABSD128", argLength: 1, reg: v11, asm: "VPABSD", commutative: false, typ: "Vec128", resultInArg0: false},
- {name: "VPABSDMasked128", argLength: 2, reg: wkw, asm: "VPABSD", commutative: false, typ: "Vec128", resultInArg0: false},
- {name: "VPADDD128", argLength: 2, reg: v21, asm: "VPADDD", commutative: true, typ: "Vec128", resultInArg0: false},
- {name: "VPADDDMasked128", argLength: 3, reg: w2kw, asm: "VPADDD", commutative: true, typ: "Vec128", resultInArg0: false},
- {name: "VPANDDMasked128", argLength: 3, reg: w2kw, asm: "VPANDD", commutative: true, typ: "Vec128", resultInArg0: false},
- {name: "VPANDNDMasked128", argLength: 3, reg: w2kw, asm: "VPANDND", commutative: false, typ: "Vec128", resultInArg0: false},
- {name: "VPCOMPRESSDMasked128", argLength: 2, reg: wkw, asm: "VPCOMPRESSD", commutative: false, typ: "Vec128", resultInArg0: false},
- {name: "VPCMPEQD128", argLength: 2, reg: v21, asm: "VPCMPEQD", commutative: true, typ: "Vec128", resultInArg0: false},
- {name: "VPCMPGTD128", argLength: 2, reg: v21, asm: "VPCMPGTD", commutative: false, typ: "Vec128", resultInArg0: false},
- {name: "VPMAXSD128", argLength: 2, reg: v21, asm: "VPMAXSD", commutative: true, typ: "Vec128", resultInArg0: false},
- {name: "VPMAXSDMasked128", argLength: 3, reg: w2kw, asm: "VPMAXSD", commutative: true, typ: "Vec128", resultInArg0: false},
- {name: "VPMINSD128", argLength: 2, reg: v21, asm: "VPMINSD", commutative: true, typ: "Vec128", resultInArg0: false},
- {name: "VPMINSDMasked128", argLength: 3, reg: w2kw, asm: "VPMINSD", commutative: true, typ: "Vec128", resultInArg0: false},
- {name: "VPMULDQ128", argLength: 2, reg: v21, asm: "VPMULDQ", commutative: true, typ: "Vec128", resultInArg0: false},
- {name: "VPMULLD128", argLength: 2, reg: v21, asm: "VPMULLD", commutative: true, typ: "Vec128", resultInArg0: false},
- {name: "VPMULLDMasked128", argLength: 3, reg: w2kw, asm: "VPMULLD", commutative: true, typ: "Vec128", resultInArg0: false},
- {name: "VPORDMasked128", argLength: 3, reg: w2kw, asm: "VPORD", commutative: true, typ: "Vec128", resultInArg0: false},
{name: "VPDPWSSD128", argLength: 3, reg: v31, asm: "VPDPWSSD", commutative: false, typ: "Vec128", resultInArg0: true},
+ {name: "VPDPWSSD256", argLength: 3, reg: v31, asm: "VPDPWSSD", commutative: false, typ: "Vec256", resultInArg0: true},
+ {name: "VPDPWSSD512", argLength: 3, reg: w31, asm: "VPDPWSSD", commutative: false, typ: "Vec512", resultInArg0: true},
{name: "VPDPWSSDMasked128", argLength: 4, reg: w3kw, asm: "VPDPWSSD", commutative: false, typ: "Vec128", resultInArg0: true},
- {name: "VPHADDD128", argLength: 2, reg: v21, asm: "VPHADDD", commutative: false, typ: "Vec128", resultInArg0: false},
- {name: "VPHSUBD128", argLength: 2, reg: v21, asm: "VPHSUBD", commutative: false, typ: "Vec128", resultInArg0: false},
- {name: "VPOPCNTD128", argLength: 1, reg: w11, asm: "VPOPCNTD", commutative: false, typ: "Vec128", resultInArg0: false},
- {name: "VPOPCNTDMasked128", argLength: 2, reg: wkw, asm: "VPOPCNTD", commutative: false, typ: "Vec128", resultInArg0: false},
- {name: "VPROLVD128", argLength: 2, reg: w21, asm: "VPROLVD", commutative: false, typ: "Vec128", resultInArg0: false},
- {name: "VPROLVDMasked128", argLength: 3, reg: w2kw, asm: "VPROLVD", commutative: false, typ: "Vec128", resultInArg0: false},
- {name: "VPRORVD128", argLength: 2, reg: w21, asm: "VPRORVD", commutative: false, typ: "Vec128", resultInArg0: false},
- {name: "VPRORVDMasked128", argLength: 3, reg: w2kw, asm: "VPRORVD", commutative: false, typ: "Vec128", resultInArg0: false},
+ {name: "VPDPWSSDMasked256", argLength: 4, reg: w3kw, asm: "VPDPWSSD", commutative: false, typ: "Vec256", resultInArg0: true},
+ {name: "VPDPWSSDMasked512", argLength: 4, reg: w3kw, asm: "VPDPWSSD", commutative: false, typ: "Vec512", resultInArg0: true},
{name: "VPDPWSSDS128", argLength: 3, reg: v31, asm: "VPDPWSSDS", commutative: false, typ: "Vec128", resultInArg0: true},
+ {name: "VPDPWSSDS256", argLength: 3, reg: v31, asm: "VPDPWSSDS", commutative: false, typ: "Vec256", resultInArg0: true},
+ {name: "VPDPWSSDS512", argLength: 3, reg: w31, asm: "VPDPWSSDS", commutative: false, typ: "Vec512", resultInArg0: true},
{name: "VPDPWSSDSMasked128", argLength: 4, reg: w3kw, asm: "VPDPWSSDS", commutative: false, typ: "Vec128", resultInArg0: true},
- {name: "VPDPBUSDS128", argLength: 3, reg: v31, asm: "VPDPBUSDS", commutative: false, typ: "Vec128", resultInArg0: true},
- {name: "VPDPBUSDSMasked128", argLength: 4, reg: w3kw, asm: "VPDPBUSDS", commutative: false, typ: "Vec128", resultInArg0: true},
- {name: "VPSLLD128", argLength: 2, reg: vfpv, asm: "VPSLLD", commutative: false, typ: "Vec128", resultInArg0: false},
- {name: "VPSLLDMasked128", argLength: 3, reg: wfpkw, asm: "VPSLLD", commutative: false, typ: "Vec128", resultInArg0: false},
- {name: "VPSRAD128", argLength: 2, reg: vfpv, asm: "VPSRAD", commutative: false, typ: "Vec128", resultInArg0: false},
- {name: "VPSRADMasked128", argLength: 3, reg: wfpkw, asm: "VPSRAD", commutative: false, typ: "Vec128", resultInArg0: false},
- {name: "VPSLLVD128", argLength: 2, reg: v21, asm: "VPSLLVD", commutative: false, typ: "Vec128", resultInArg0: false},
- {name: "VPSHLDVD128", argLength: 3, reg: w31, asm: "VPSHLDVD", commutative: false, typ: "Vec128", resultInArg0: true},
- {name: "VPSHLDVDMasked128", argLength: 4, reg: w3kw, asm: "VPSHLDVD", commutative: false, typ: "Vec128", resultInArg0: true},
- {name: "VPSLLVDMasked128", argLength: 3, reg: w2kw, asm: "VPSLLVD", commutative: false, typ: "Vec128", resultInArg0: false},
- {name: "VPSRAVD128", argLength: 2, reg: v21, asm: "VPSRAVD", commutative: false, typ: "Vec128", resultInArg0: false},
- {name: "VPSHRDVD128", argLength: 3, reg: w31, asm: "VPSHRDVD", commutative: false, typ: "Vec128", resultInArg0: true},
- {name: "VPSHRDVDMasked128", argLength: 4, reg: w3kw, asm: "VPSHRDVD", commutative: false, typ: "Vec128", resultInArg0: true},
- {name: "VPSRAVDMasked128", argLength: 3, reg: w2kw, asm: "VPSRAVD", commutative: false, typ: "Vec128", resultInArg0: false},
- {name: "VPSIGND128", argLength: 2, reg: v21, asm: "VPSIGND", commutative: false, typ: "Vec128", resultInArg0: false},
- {name: "VPSUBD128", argLength: 2, reg: v21, asm: "VPSUBD", commutative: false, typ: "Vec128", resultInArg0: false},
- {name: "VPSUBDMasked128", argLength: 3, reg: w2kw, asm: "VPSUBD", commutative: false, typ: "Vec128", resultInArg0: false},
- {name: "VPDPBUSD128", argLength: 3, reg: v31, asm: "VPDPBUSD", commutative: false, typ: "Vec128", resultInArg0: true},
- {name: "VPDPBUSDMasked128", argLength: 4, reg: w3kw, asm: "VPDPBUSD", commutative: false, typ: "Vec128", resultInArg0: true},
- {name: "VPXORDMasked128", argLength: 3, reg: w2kw, asm: "VPXORD", commutative: true, typ: "Vec128", resultInArg0: false},
- {name: "VPABSD256", argLength: 1, reg: v11, asm: "VPABSD", commutative: false, typ: "Vec256", resultInArg0: false},
- {name: "VPABSDMasked256", argLength: 2, reg: wkw, asm: "VPABSD", commutative: false, typ: "Vec256", resultInArg0: false},
- {name: "VPADDD256", argLength: 2, reg: v21, asm: "VPADDD", commutative: true, typ: "Vec256", resultInArg0: false},
- {name: "VPADDDMasked256", argLength: 3, reg: w2kw, asm: "VPADDD", commutative: true, typ: "Vec256", resultInArg0: false},
- {name: "VPANDDMasked256", argLength: 3, reg: w2kw, asm: "VPANDD", commutative: true, typ: "Vec256", resultInArg0: false},
- {name: "VPANDNDMasked256", argLength: 3, reg: w2kw, asm: "VPANDND", commutative: false, typ: "Vec256", resultInArg0: false},
- {name: "VPCOMPRESSDMasked256", argLength: 2, reg: wkw, asm: "VPCOMPRESSD", commutative: false, typ: "Vec256", resultInArg0: false},
- {name: "VPCMPEQD256", argLength: 2, reg: v21, asm: "VPCMPEQD", commutative: true, typ: "Vec256", resultInArg0: false},
- {name: "VPCMPGTD256", argLength: 2, reg: v21, asm: "VPCMPGTD", commutative: false, typ: "Vec256", resultInArg0: false},
- {name: "VPMAXSD256", argLength: 2, reg: v21, asm: "VPMAXSD", commutative: true, typ: "Vec256", resultInArg0: false},
- {name: "VPMAXSDMasked256", argLength: 3, reg: w2kw, asm: "VPMAXSD", commutative: true, typ: "Vec256", resultInArg0: false},
- {name: "VPMINSD256", argLength: 2, reg: v21, asm: "VPMINSD", commutative: true, typ: "Vec256", resultInArg0: false},
- {name: "VPMINSDMasked256", argLength: 3, reg: w2kw, asm: "VPMINSD", commutative: true, typ: "Vec256", resultInArg0: false},
- {name: "VPMULDQ256", argLength: 2, reg: v21, asm: "VPMULDQ", commutative: true, typ: "Vec256", resultInArg0: false},
- {name: "VPMULLD256", argLength: 2, reg: v21, asm: "VPMULLD", commutative: true, typ: "Vec256", resultInArg0: false},
- {name: "VPMULLDMasked256", argLength: 3, reg: w2kw, asm: "VPMULLD", commutative: true, typ: "Vec256", resultInArg0: false},
- {name: "VPORDMasked256", argLength: 3, reg: w2kw, asm: "VPORD", commutative: true, typ: "Vec256", resultInArg0: false},
- {name: "VPDPWSSD256", argLength: 3, reg: v31, asm: "VPDPWSSD", commutative: false, typ: "Vec256", resultInArg0: true},
- {name: "VPDPWSSDMasked256", argLength: 4, reg: w3kw, asm: "VPDPWSSD", commutative: false, typ: "Vec256", resultInArg0: true},
+ {name: "VPDPWSSDSMasked256", argLength: 4, reg: w3kw, asm: "VPDPWSSDS", commutative: false, typ: "Vec256", resultInArg0: true},
+ {name: "VPDPWSSDSMasked512", argLength: 4, reg: w3kw, asm: "VPDPWSSDS", commutative: false, typ: "Vec512", resultInArg0: true},
+ {name: "VPERMB128", argLength: 2, reg: w21, asm: "VPERMB", commutative: false, typ: "Vec128", resultInArg0: false},
+ {name: "VPERMB256", argLength: 2, reg: w21, asm: "VPERMB", commutative: false, typ: "Vec256", resultInArg0: false},
+ {name: "VPERMB512", argLength: 2, reg: w21, asm: "VPERMB", commutative: false, typ: "Vec512", resultInArg0: false},
+ {name: "VPERMBMasked128", argLength: 3, reg: w2kw, asm: "VPERMB", commutative: false, typ: "Vec128", resultInArg0: false},
+ {name: "VPERMBMasked256", argLength: 3, reg: w2kw, asm: "VPERMB", commutative: false, typ: "Vec256", resultInArg0: false},
+ {name: "VPERMBMasked512", argLength: 3, reg: w2kw, asm: "VPERMB", commutative: false, typ: "Vec512", resultInArg0: false},
+ {name: "VPERMD256", argLength: 2, reg: v21, asm: "VPERMD", commutative: false, typ: "Vec256", resultInArg0: false},
+ {name: "VPERMD512", argLength: 2, reg: w21, asm: "VPERMD", commutative: false, typ: "Vec512", resultInArg0: false},
+ {name: "VPERMDMasked256", argLength: 3, reg: w2kw, asm: "VPERMD", commutative: false, typ: "Vec256", resultInArg0: false},
+ {name: "VPERMDMasked512", argLength: 3, reg: w2kw, asm: "VPERMD", commutative: false, typ: "Vec512", resultInArg0: false},
+ {name: "VPERMI2B128", argLength: 3, reg: w31, asm: "VPERMI2B", commutative: false, typ: "Vec128", resultInArg0: true},
+ {name: "VPERMI2B256", argLength: 3, reg: w31, asm: "VPERMI2B", commutative: false, typ: "Vec256", resultInArg0: true},
+ {name: "VPERMI2B512", argLength: 3, reg: w31, asm: "VPERMI2B", commutative: false, typ: "Vec512", resultInArg0: true},
+ {name: "VPERMI2BMasked128", argLength: 4, reg: w3kw, asm: "VPERMI2B", commutative: false, typ: "Vec128", resultInArg0: true},
+ {name: "VPERMI2BMasked256", argLength: 4, reg: w3kw, asm: "VPERMI2B", commutative: false, typ: "Vec256", resultInArg0: true},
+ {name: "VPERMI2BMasked512", argLength: 4, reg: w3kw, asm: "VPERMI2B", commutative: false, typ: "Vec512", resultInArg0: true},
+ {name: "VPERMI2D128", argLength: 3, reg: w31, asm: "VPERMI2D", commutative: false, typ: "Vec128", resultInArg0: true},
+ {name: "VPERMI2D256", argLength: 3, reg: w31, asm: "VPERMI2D", commutative: false, typ: "Vec256", resultInArg0: true},
+ {name: "VPERMI2D512", argLength: 3, reg: w31, asm: "VPERMI2D", commutative: false, typ: "Vec512", resultInArg0: true},
+ {name: "VPERMI2DMasked128", argLength: 4, reg: w3kw, asm: "VPERMI2D", commutative: false, typ: "Vec128", resultInArg0: true},
+ {name: "VPERMI2DMasked256", argLength: 4, reg: w3kw, asm: "VPERMI2D", commutative: false, typ: "Vec256", resultInArg0: true},
+ {name: "VPERMI2DMasked512", argLength: 4, reg: w3kw, asm: "VPERMI2D", commutative: false, typ: "Vec512", resultInArg0: true},
+ {name: "VPERMI2PD128", argLength: 3, reg: w31, asm: "VPERMI2PD", commutative: false, typ: "Vec128", resultInArg0: true},
+ {name: "VPERMI2PD256", argLength: 3, reg: w31, asm: "VPERMI2PD", commutative: false, typ: "Vec256", resultInArg0: true},
+ {name: "VPERMI2PD512", argLength: 3, reg: w31, asm: "VPERMI2PD", commutative: false, typ: "Vec512", resultInArg0: true},
+ {name: "VPERMI2PDMasked128", argLength: 4, reg: w3kw, asm: "VPERMI2PD", commutative: false, typ: "Vec128", resultInArg0: true},
+ {name: "VPERMI2PDMasked256", argLength: 4, reg: w3kw, asm: "VPERMI2PD", commutative: false, typ: "Vec256", resultInArg0: true},
+ {name: "VPERMI2PDMasked512", argLength: 4, reg: w3kw, asm: "VPERMI2PD", commutative: false, typ: "Vec512", resultInArg0: true},
+ {name: "VPERMI2PS128", argLength: 3, reg: w31, asm: "VPERMI2PS", commutative: false, typ: "Vec128", resultInArg0: true},
+ {name: "VPERMI2PS256", argLength: 3, reg: w31, asm: "VPERMI2PS", commutative: false, typ: "Vec256", resultInArg0: true},
+ {name: "VPERMI2PS512", argLength: 3, reg: w31, asm: "VPERMI2PS", commutative: false, typ: "Vec512", resultInArg0: true},
+ {name: "VPERMI2PSMasked128", argLength: 4, reg: w3kw, asm: "VPERMI2PS", commutative: false, typ: "Vec128", resultInArg0: true},
+ {name: "VPERMI2PSMasked256", argLength: 4, reg: w3kw, asm: "VPERMI2PS", commutative: false, typ: "Vec256", resultInArg0: true},
+ {name: "VPERMI2PSMasked512", argLength: 4, reg: w3kw, asm: "VPERMI2PS", commutative: false, typ: "Vec512", resultInArg0: true},
+ {name: "VPERMI2Q128", argLength: 3, reg: w31, asm: "VPERMI2Q", commutative: false, typ: "Vec128", resultInArg0: true},
+ {name: "VPERMI2Q256", argLength: 3, reg: w31, asm: "VPERMI2Q", commutative: false, typ: "Vec256", resultInArg0: true},
+ {name: "VPERMI2Q512", argLength: 3, reg: w31, asm: "VPERMI2Q", commutative: false, typ: "Vec512", resultInArg0: true},
+ {name: "VPERMI2QMasked128", argLength: 4, reg: w3kw, asm: "VPERMI2Q", commutative: false, typ: "Vec128", resultInArg0: true},
+ {name: "VPERMI2QMasked256", argLength: 4, reg: w3kw, asm: "VPERMI2Q", commutative: false, typ: "Vec256", resultInArg0: true},
+ {name: "VPERMI2QMasked512", argLength: 4, reg: w3kw, asm: "VPERMI2Q", commutative: false, typ: "Vec512", resultInArg0: true},
+ {name: "VPERMI2W128", argLength: 3, reg: w31, asm: "VPERMI2W", commutative: false, typ: "Vec128", resultInArg0: true},
+ {name: "VPERMI2W256", argLength: 3, reg: w31, asm: "VPERMI2W", commutative: false, typ: "Vec256", resultInArg0: true},
+ {name: "VPERMI2W512", argLength: 3, reg: w31, asm: "VPERMI2W", commutative: false, typ: "Vec512", resultInArg0: true},
+ {name: "VPERMI2WMasked128", argLength: 4, reg: w3kw, asm: "VPERMI2W", commutative: false, typ: "Vec128", resultInArg0: true},
+ {name: "VPERMI2WMasked256", argLength: 4, reg: w3kw, asm: "VPERMI2W", commutative: false, typ: "Vec256", resultInArg0: true},
+ {name: "VPERMI2WMasked512", argLength: 4, reg: w3kw, asm: "VPERMI2W", commutative: false, typ: "Vec512", resultInArg0: true},
+ {name: "VPERMPD256", argLength: 2, reg: w21, asm: "VPERMPD", commutative: false, typ: "Vec256", resultInArg0: false},
+ {name: "VPERMPD512", argLength: 2, reg: w21, asm: "VPERMPD", commutative: false, typ: "Vec512", resultInArg0: false},
+ {name: "VPERMPDMasked256", argLength: 3, reg: w2kw, asm: "VPERMPD", commutative: false, typ: "Vec256", resultInArg0: false},
+ {name: "VPERMPDMasked512", argLength: 3, reg: w2kw, asm: "VPERMPD", commutative: false, typ: "Vec512", resultInArg0: false},
+ {name: "VPERMPS256", argLength: 2, reg: v21, asm: "VPERMPS", commutative: false, typ: "Vec256", resultInArg0: false},
+ {name: "VPERMPS512", argLength: 2, reg: w21, asm: "VPERMPS", commutative: false, typ: "Vec512", resultInArg0: false},
+ {name: "VPERMPSMasked256", argLength: 3, reg: w2kw, asm: "VPERMPS", commutative: false, typ: "Vec256", resultInArg0: false},
+ {name: "VPERMPSMasked512", argLength: 3, reg: w2kw, asm: "VPERMPS", commutative: false, typ: "Vec512", resultInArg0: false},
+ {name: "VPERMQ256", argLength: 2, reg: w21, asm: "VPERMQ", commutative: false, typ: "Vec256", resultInArg0: false},
+ {name: "VPERMQ512", argLength: 2, reg: w21, asm: "VPERMQ", commutative: false, typ: "Vec512", resultInArg0: false},
+ {name: "VPERMQMasked256", argLength: 3, reg: w2kw, asm: "VPERMQ", commutative: false, typ: "Vec256", resultInArg0: false},
+ {name: "VPERMQMasked512", argLength: 3, reg: w2kw, asm: "VPERMQ", commutative: false, typ: "Vec512", resultInArg0: false},
+ {name: "VPERMW128", argLength: 2, reg: w21, asm: "VPERMW", commutative: false, typ: "Vec128", resultInArg0: false},
+ {name: "VPERMW256", argLength: 2, reg: w21, asm: "VPERMW", commutative: false, typ: "Vec256", resultInArg0: false},
+ {name: "VPERMW512", argLength: 2, reg: w21, asm: "VPERMW", commutative: false, typ: "Vec512", resultInArg0: false},
+ {name: "VPERMWMasked128", argLength: 3, reg: w2kw, asm: "VPERMW", commutative: false, typ: "Vec128", resultInArg0: false},
+ {name: "VPERMWMasked256", argLength: 3, reg: w2kw, asm: "VPERMW", commutative: false, typ: "Vec256", resultInArg0: false},
+ {name: "VPERMWMasked512", argLength: 3, reg: w2kw, asm: "VPERMW", commutative: false, typ: "Vec512", resultInArg0: false},
+ {name: "VPHADDD128", argLength: 2, reg: v21, asm: "VPHADDD", commutative: false, typ: "Vec128", resultInArg0: false},
{name: "VPHADDD256", argLength: 2, reg: v21, asm: "VPHADDD", commutative: false, typ: "Vec256", resultInArg0: false},
+ {name: "VPHADDSW128", argLength: 2, reg: v21, asm: "VPHADDSW", commutative: false, typ: "Vec128", resultInArg0: false},
+ {name: "VPHADDSW256", argLength: 2, reg: v21, asm: "VPHADDSW", commutative: false, typ: "Vec256", resultInArg0: false},
+ {name: "VPHADDW128", argLength: 2, reg: v21, asm: "VPHADDW", commutative: false, typ: "Vec128", resultInArg0: false},
+ {name: "VPHADDW256", argLength: 2, reg: v21, asm: "VPHADDW", commutative: false, typ: "Vec256", resultInArg0: false},
+ {name: "VPHSUBD128", argLength: 2, reg: v21, asm: "VPHSUBD", commutative: false, typ: "Vec128", resultInArg0: false},
{name: "VPHSUBD256", argLength: 2, reg: v21, asm: "VPHSUBD", commutative: false, typ: "Vec256", resultInArg0: false},
- {name: "VPOPCNTD256", argLength: 1, reg: w11, asm: "VPOPCNTD", commutative: false, typ: "Vec256", resultInArg0: false},
- {name: "VPOPCNTDMasked256", argLength: 2, reg: wkw, asm: "VPOPCNTD", commutative: false, typ: "Vec256", resultInArg0: false},
- {name: "VPROLVD256", argLength: 2, reg: w21, asm: "VPROLVD", commutative: false, typ: "Vec256", resultInArg0: false},
- {name: "VPROLVDMasked256", argLength: 3, reg: w2kw, asm: "VPROLVD", commutative: false, typ: "Vec256", resultInArg0: false},
- {name: "VPRORVD256", argLength: 2, reg: w21, asm: "VPRORVD", commutative: false, typ: "Vec256", resultInArg0: false},
- {name: "VPRORVDMasked256", argLength: 3, reg: w2kw, asm: "VPRORVD", commutative: false, typ: "Vec256", resultInArg0: false},
- {name: "VPDPWSSDS256", argLength: 3, reg: v31, asm: "VPDPWSSDS", commutative: false, typ: "Vec256", resultInArg0: true},
- {name: "VPDPWSSDSMasked256", argLength: 4, reg: w3kw, asm: "VPDPWSSDS", commutative: false, typ: "Vec256", resultInArg0: true},
- {name: "VPDPBUSDS256", argLength: 3, reg: v31, asm: "VPDPBUSDS", commutative: false, typ: "Vec256", resultInArg0: true},
- {name: "VPDPBUSDSMasked256", argLength: 4, reg: w3kw, asm: "VPDPBUSDS", commutative: false, typ: "Vec256", resultInArg0: true},
- {name: "VPSLLD256", argLength: 2, reg: vfpv, asm: "VPSLLD", commutative: false, typ: "Vec256", resultInArg0: false},
- {name: "VPSLLDMasked256", argLength: 3, reg: wfpkw, asm: "VPSLLD", commutative: false, typ: "Vec256", resultInArg0: false},
- {name: "VPSRAD256", argLength: 2, reg: vfpv, asm: "VPSRAD", commutative: false, typ: "Vec256", resultInArg0: false},
- {name: "VPSRADMasked256", argLength: 3, reg: wfpkw, asm: "VPSRAD", commutative: false, typ: "Vec256", resultInArg0: false},
- {name: "VPSLLVD256", argLength: 2, reg: v21, asm: "VPSLLVD", commutative: false, typ: "Vec256", resultInArg0: false},
- {name: "VPSHLDVD256", argLength: 3, reg: w31, asm: "VPSHLDVD", commutative: false, typ: "Vec256", resultInArg0: true},
- {name: "VPSHLDVDMasked256", argLength: 4, reg: w3kw, asm: "VPSHLDVD", commutative: false, typ: "Vec256", resultInArg0: true},
- {name: "VPSLLVDMasked256", argLength: 3, reg: w2kw, asm: "VPSLLVD", commutative: false, typ: "Vec256", resultInArg0: false},
- {name: "VPSRAVD256", argLength: 2, reg: v21, asm: "VPSRAVD", commutative: false, typ: "Vec256", resultInArg0: false},
- {name: "VPSHRDVD256", argLength: 3, reg: w31, asm: "VPSHRDVD", commutative: false, typ: "Vec256", resultInArg0: true},
- {name: "VPSHRDVDMasked256", argLength: 4, reg: w3kw, asm: "VPSHRDVD", commutative: false, typ: "Vec256", resultInArg0: true},
- {name: "VPSRAVDMasked256", argLength: 3, reg: w2kw, asm: "VPSRAVD", commutative: false, typ: "Vec256", resultInArg0: false},
- {name: "VPSIGND256", argLength: 2, reg: v21, asm: "VPSIGND", commutative: false, typ: "Vec256", resultInArg0: false},
- {name: "VPSUBD256", argLength: 2, reg: v21, asm: "VPSUBD", commutative: false, typ: "Vec256", resultInArg0: false},
- {name: "VPSUBDMasked256", argLength: 3, reg: w2kw, asm: "VPSUBD", commutative: false, typ: "Vec256", resultInArg0: false},
- {name: "VPDPBUSD256", argLength: 3, reg: v31, asm: "VPDPBUSD", commutative: false, typ: "Vec256", resultInArg0: true},
- {name: "VPDPBUSDMasked256", argLength: 4, reg: w3kw, asm: "VPDPBUSD", commutative: false, typ: "Vec256", resultInArg0: true},
- {name: "VPXORDMasked256", argLength: 3, reg: w2kw, asm: "VPXORD", commutative: true, typ: "Vec256", resultInArg0: false},
- {name: "VPABSQ128", argLength: 1, reg: w11, asm: "VPABSQ", commutative: false, typ: "Vec128", resultInArg0: false},
- {name: "VPABSQMasked128", argLength: 2, reg: wkw, asm: "VPABSQ", commutative: false, typ: "Vec128", resultInArg0: false},
- {name: "VPADDQ128", argLength: 2, reg: v21, asm: "VPADDQ", commutative: true, typ: "Vec128", resultInArg0: false},
- {name: "VPADDQMasked128", argLength: 3, reg: w2kw, asm: "VPADDQ", commutative: true, typ: "Vec128", resultInArg0: false},
- {name: "VPANDQMasked128", argLength: 3, reg: w2kw, asm: "VPANDQ", commutative: true, typ: "Vec128", resultInArg0: false},
- {name: "VPANDNQMasked128", argLength: 3, reg: w2kw, asm: "VPANDNQ", commutative: false, typ: "Vec128", resultInArg0: false},
- {name: "VPCOMPRESSQMasked128", argLength: 2, reg: wkw, asm: "VPCOMPRESSQ", commutative: false, typ: "Vec128", resultInArg0: false},
- {name: "VPCMPEQQ128", argLength: 2, reg: v21, asm: "VPCMPEQQ", commutative: true, typ: "Vec128", resultInArg0: false},
- {name: "VPCMPGTQ128", argLength: 2, reg: v21, asm: "VPCMPGTQ", commutative: false, typ: "Vec128", resultInArg0: false},
+ {name: "VPHSUBSW128", argLength: 2, reg: v21, asm: "VPHSUBSW", commutative: false, typ: "Vec128", resultInArg0: false},
+ {name: "VPHSUBSW256", argLength: 2, reg: v21, asm: "VPHSUBSW", commutative: false, typ: "Vec256", resultInArg0: false},
+ {name: "VPHSUBW128", argLength: 2, reg: v21, asm: "VPHSUBW", commutative: false, typ: "Vec128", resultInArg0: false},
+ {name: "VPHSUBW256", argLength: 2, reg: v21, asm: "VPHSUBW", commutative: false, typ: "Vec256", resultInArg0: false},
+ {name: "VPMADDUBSW128", argLength: 2, reg: v21, asm: "VPMADDUBSW", commutative: false, typ: "Vec128", resultInArg0: false},
+ {name: "VPMADDUBSW256", argLength: 2, reg: v21, asm: "VPMADDUBSW", commutative: false, typ: "Vec256", resultInArg0: false},
+ {name: "VPMADDUBSW512", argLength: 2, reg: w21, asm: "VPMADDUBSW", commutative: false, typ: "Vec512", resultInArg0: false},
+ {name: "VPMADDUBSWMasked128", argLength: 3, reg: w2kw, asm: "VPMADDUBSW", commutative: false, typ: "Vec128", resultInArg0: false},
+ {name: "VPMADDUBSWMasked256", argLength: 3, reg: w2kw, asm: "VPMADDUBSW", commutative: false, typ: "Vec256", resultInArg0: false},
+ {name: "VPMADDUBSWMasked512", argLength: 3, reg: w2kw, asm: "VPMADDUBSW", commutative: false, typ: "Vec512", resultInArg0: false},
+ {name: "VPMADDWD128", argLength: 2, reg: v21, asm: "VPMADDWD", commutative: false, typ: "Vec128", resultInArg0: false},
+ {name: "VPMADDWD256", argLength: 2, reg: v21, asm: "VPMADDWD", commutative: false, typ: "Vec256", resultInArg0: false},
+ {name: "VPMADDWD512", argLength: 2, reg: w21, asm: "VPMADDWD", commutative: false, typ: "Vec512", resultInArg0: false},
+ {name: "VPMADDWDMasked128", argLength: 3, reg: w2kw, asm: "VPMADDWD", commutative: false, typ: "Vec128", resultInArg0: false},
+ {name: "VPMADDWDMasked256", argLength: 3, reg: w2kw, asm: "VPMADDWD", commutative: false, typ: "Vec256", resultInArg0: false},
+ {name: "VPMADDWDMasked512", argLength: 3, reg: w2kw, asm: "VPMADDWD", commutative: false, typ: "Vec512", resultInArg0: false},
+ {name: "VPMAXSB128", argLength: 2, reg: v21, asm: "VPMAXSB", commutative: true, typ: "Vec128", resultInArg0: false},
+ {name: "VPMAXSB256", argLength: 2, reg: v21, asm: "VPMAXSB", commutative: true, typ: "Vec256", resultInArg0: false},
+ {name: "VPMAXSB512", argLength: 2, reg: w21, asm: "VPMAXSB", commutative: true, typ: "Vec512", resultInArg0: false},
+ {name: "VPMAXSBMasked128", argLength: 3, reg: w2kw, asm: "VPMAXSB", commutative: true, typ: "Vec128", resultInArg0: false},
+ {name: "VPMAXSBMasked256", argLength: 3, reg: w2kw, asm: "VPMAXSB", commutative: true, typ: "Vec256", resultInArg0: false},
+ {name: "VPMAXSBMasked512", argLength: 3, reg: w2kw, asm: "VPMAXSB", commutative: true, typ: "Vec512", resultInArg0: false},
+ {name: "VPMAXSD128", argLength: 2, reg: v21, asm: "VPMAXSD", commutative: true, typ: "Vec128", resultInArg0: false},
+ {name: "VPMAXSD256", argLength: 2, reg: v21, asm: "VPMAXSD", commutative: true, typ: "Vec256", resultInArg0: false},
+ {name: "VPMAXSD512", argLength: 2, reg: w21, asm: "VPMAXSD", commutative: true, typ: "Vec512", resultInArg0: false},
+ {name: "VPMAXSDMasked128", argLength: 3, reg: w2kw, asm: "VPMAXSD", commutative: true, typ: "Vec128", resultInArg0: false},
+ {name: "VPMAXSDMasked256", argLength: 3, reg: w2kw, asm: "VPMAXSD", commutative: true, typ: "Vec256", resultInArg0: false},
+ {name: "VPMAXSDMasked512", argLength: 3, reg: w2kw, asm: "VPMAXSD", commutative: true, typ: "Vec512", resultInArg0: false},
{name: "VPMAXSQ128", argLength: 2, reg: w21, asm: "VPMAXSQ", commutative: true, typ: "Vec128", resultInArg0: false},
+ {name: "VPMAXSQ256", argLength: 2, reg: w21, asm: "VPMAXSQ", commutative: true, typ: "Vec256", resultInArg0: false},
+ {name: "VPMAXSQ512", argLength: 2, reg: w21, asm: "VPMAXSQ", commutative: true, typ: "Vec512", resultInArg0: false},
{name: "VPMAXSQMasked128", argLength: 3, reg: w2kw, asm: "VPMAXSQ", commutative: true, typ: "Vec128", resultInArg0: false},
+ {name: "VPMAXSQMasked256", argLength: 3, reg: w2kw, asm: "VPMAXSQ", commutative: true, typ: "Vec256", resultInArg0: false},
+ {name: "VPMAXSQMasked512", argLength: 3, reg: w2kw, asm: "VPMAXSQ", commutative: true, typ: "Vec512", resultInArg0: false},
+ {name: "VPMAXSW128", argLength: 2, reg: v21, asm: "VPMAXSW", commutative: true, typ: "Vec128", resultInArg0: false},
+ {name: "VPMAXSW256", argLength: 2, reg: v21, asm: "VPMAXSW", commutative: true, typ: "Vec256", resultInArg0: false},
+ {name: "VPMAXSW512", argLength: 2, reg: w21, asm: "VPMAXSW", commutative: true, typ: "Vec512", resultInArg0: false},
+ {name: "VPMAXSWMasked128", argLength: 3, reg: w2kw, asm: "VPMAXSW", commutative: true, typ: "Vec128", resultInArg0: false},
+ {name: "VPMAXSWMasked256", argLength: 3, reg: w2kw, asm: "VPMAXSW", commutative: true, typ: "Vec256", resultInArg0: false},
+ {name: "VPMAXSWMasked512", argLength: 3, reg: w2kw, asm: "VPMAXSW", commutative: true, typ: "Vec512", resultInArg0: false},
+ {name: "VPMAXUB128", argLength: 2, reg: v21, asm: "VPMAXUB", commutative: true, typ: "Vec128", resultInArg0: false},
+ {name: "VPMAXUB256", argLength: 2, reg: v21, asm: "VPMAXUB", commutative: true, typ: "Vec256", resultInArg0: false},
+ {name: "VPMAXUB512", argLength: 2, reg: w21, asm: "VPMAXUB", commutative: true, typ: "Vec512", resultInArg0: false},
+ {name: "VPMAXUBMasked128", argLength: 3, reg: w2kw, asm: "VPMAXUB", commutative: true, typ: "Vec128", resultInArg0: false},
+ {name: "VPMAXUBMasked256", argLength: 3, reg: w2kw, asm: "VPMAXUB", commutative: true, typ: "Vec256", resultInArg0: false},
+ {name: "VPMAXUBMasked512", argLength: 3, reg: w2kw, asm: "VPMAXUB", commutative: true, typ: "Vec512", resultInArg0: false},
+ {name: "VPMAXUD128", argLength: 2, reg: v21, asm: "VPMAXUD", commutative: true, typ: "Vec128", resultInArg0: false},
+ {name: "VPMAXUD256", argLength: 2, reg: v21, asm: "VPMAXUD", commutative: true, typ: "Vec256", resultInArg0: false},
+ {name: "VPMAXUD512", argLength: 2, reg: w21, asm: "VPMAXUD", commutative: true, typ: "Vec512", resultInArg0: false},
+ {name: "VPMAXUDMasked128", argLength: 3, reg: w2kw, asm: "VPMAXUD", commutative: true, typ: "Vec128", resultInArg0: false},
+ {name: "VPMAXUDMasked256", argLength: 3, reg: w2kw, asm: "VPMAXUD", commutative: true, typ: "Vec256", resultInArg0: false},
+ {name: "VPMAXUDMasked512", argLength: 3, reg: w2kw, asm: "VPMAXUD", commutative: true, typ: "Vec512", resultInArg0: false},
+ {name: "VPMAXUQ128", argLength: 2, reg: w21, asm: "VPMAXUQ", commutative: true, typ: "Vec128", resultInArg0: false},
+ {name: "VPMAXUQ256", argLength: 2, reg: w21, asm: "VPMAXUQ", commutative: true, typ: "Vec256", resultInArg0: false},
+ {name: "VPMAXUQ512", argLength: 2, reg: w21, asm: "VPMAXUQ", commutative: true, typ: "Vec512", resultInArg0: false},
+ {name: "VPMAXUQMasked128", argLength: 3, reg: w2kw, asm: "VPMAXUQ", commutative: true, typ: "Vec128", resultInArg0: false},
+ {name: "VPMAXUQMasked256", argLength: 3, reg: w2kw, asm: "VPMAXUQ", commutative: true, typ: "Vec256", resultInArg0: false},
+ {name: "VPMAXUQMasked512", argLength: 3, reg: w2kw, asm: "VPMAXUQ", commutative: true, typ: "Vec512", resultInArg0: false},
+ {name: "VPMAXUW128", argLength: 2, reg: v21, asm: "VPMAXUW", commutative: true, typ: "Vec128", resultInArg0: false},
+ {name: "VPMAXUW256", argLength: 2, reg: v21, asm: "VPMAXUW", commutative: true, typ: "Vec256", resultInArg0: false},
+ {name: "VPMAXUW512", argLength: 2, reg: w21, asm: "VPMAXUW", commutative: true, typ: "Vec512", resultInArg0: false},
+ {name: "VPMAXUWMasked128", argLength: 3, reg: w2kw, asm: "VPMAXUW", commutative: true, typ: "Vec128", resultInArg0: false},
+ {name: "VPMAXUWMasked256", argLength: 3, reg: w2kw, asm: "VPMAXUW", commutative: true, typ: "Vec256", resultInArg0: false},
+ {name: "VPMAXUWMasked512", argLength: 3, reg: w2kw, asm: "VPMAXUW", commutative: true, typ: "Vec512", resultInArg0: false},
+ {name: "VPMINSB128", argLength: 2, reg: v21, asm: "VPMINSB", commutative: true, typ: "Vec128", resultInArg0: false},
+ {name: "VPMINSB256", argLength: 2, reg: v21, asm: "VPMINSB", commutative: true, typ: "Vec256", resultInArg0: false},
+ {name: "VPMINSB512", argLength: 2, reg: w21, asm: "VPMINSB", commutative: true, typ: "Vec512", resultInArg0: false},
+ {name: "VPMINSBMasked128", argLength: 3, reg: w2kw, asm: "VPMINSB", commutative: true, typ: "Vec128", resultInArg0: false},
+ {name: "VPMINSBMasked256", argLength: 3, reg: w2kw, asm: "VPMINSB", commutative: true, typ: "Vec256", resultInArg0: false},
+ {name: "VPMINSBMasked512", argLength: 3, reg: w2kw, asm: "VPMINSB", commutative: true, typ: "Vec512", resultInArg0: false},
+ {name: "VPMINSD128", argLength: 2, reg: v21, asm: "VPMINSD", commutative: true, typ: "Vec128", resultInArg0: false},
+ {name: "VPMINSD256", argLength: 2, reg: v21, asm: "VPMINSD", commutative: true, typ: "Vec256", resultInArg0: false},
+ {name: "VPMINSD512", argLength: 2, reg: w21, asm: "VPMINSD", commutative: true, typ: "Vec512", resultInArg0: false},
+ {name: "VPMINSDMasked128", argLength: 3, reg: w2kw, asm: "VPMINSD", commutative: true, typ: "Vec128", resultInArg0: false},
+ {name: "VPMINSDMasked256", argLength: 3, reg: w2kw, asm: "VPMINSD", commutative: true, typ: "Vec256", resultInArg0: false},
+ {name: "VPMINSDMasked512", argLength: 3, reg: w2kw, asm: "VPMINSD", commutative: true, typ: "Vec512", resultInArg0: false},
{name: "VPMINSQ128", argLength: 2, reg: w21, asm: "VPMINSQ", commutative: true, typ: "Vec128", resultInArg0: false},
+ {name: "VPMINSQ256", argLength: 2, reg: w21, asm: "VPMINSQ", commutative: true, typ: "Vec256", resultInArg0: false},
+ {name: "VPMINSQ512", argLength: 2, reg: w21, asm: "VPMINSQ", commutative: true, typ: "Vec512", resultInArg0: false},
{name: "VPMINSQMasked128", argLength: 3, reg: w2kw, asm: "VPMINSQ", commutative: true, typ: "Vec128", resultInArg0: false},
+ {name: "VPMINSQMasked256", argLength: 3, reg: w2kw, asm: "VPMINSQ", commutative: true, typ: "Vec256", resultInArg0: false},
+ {name: "VPMINSQMasked512", argLength: 3, reg: w2kw, asm: "VPMINSQ", commutative: true, typ: "Vec512", resultInArg0: false},
+ {name: "VPMINSW128", argLength: 2, reg: v21, asm: "VPMINSW", commutative: true, typ: "Vec128", resultInArg0: false},
+ {name: "VPMINSW256", argLength: 2, reg: v21, asm: "VPMINSW", commutative: true, typ: "Vec256", resultInArg0: false},
+ {name: "VPMINSW512", argLength: 2, reg: w21, asm: "VPMINSW", commutative: true, typ: "Vec512", resultInArg0: false},
+ {name: "VPMINSWMasked128", argLength: 3, reg: w2kw, asm: "VPMINSW", commutative: true, typ: "Vec128", resultInArg0: false},
+ {name: "VPMINSWMasked256", argLength: 3, reg: w2kw, asm: "VPMINSW", commutative: true, typ: "Vec256", resultInArg0: false},
+ {name: "VPMINSWMasked512", argLength: 3, reg: w2kw, asm: "VPMINSW", commutative: true, typ: "Vec512", resultInArg0: false},
+ {name: "VPMINUB128", argLength: 2, reg: v21, asm: "VPMINUB", commutative: true, typ: "Vec128", resultInArg0: false},
+ {name: "VPMINUB256", argLength: 2, reg: v21, asm: "VPMINUB", commutative: true, typ: "Vec256", resultInArg0: false},
+ {name: "VPMINUB512", argLength: 2, reg: w21, asm: "VPMINUB", commutative: true, typ: "Vec512", resultInArg0: false},
+ {name: "VPMINUBMasked128", argLength: 3, reg: w2kw, asm: "VPMINUB", commutative: true, typ: "Vec128", resultInArg0: false},
+ {name: "VPMINUBMasked256", argLength: 3, reg: w2kw, asm: "VPMINUB", commutative: true, typ: "Vec256", resultInArg0: false},
+ {name: "VPMINUBMasked512", argLength: 3, reg: w2kw, asm: "VPMINUB", commutative: true, typ: "Vec512", resultInArg0: false},
+ {name: "VPMINUD128", argLength: 2, reg: v21, asm: "VPMINUD", commutative: true, typ: "Vec128", resultInArg0: false},
+ {name: "VPMINUD256", argLength: 2, reg: v21, asm: "VPMINUD", commutative: true, typ: "Vec256", resultInArg0: false},
+ {name: "VPMINUD512", argLength: 2, reg: w21, asm: "VPMINUD", commutative: true, typ: "Vec512", resultInArg0: false},
+ {name: "VPMINUDMasked128", argLength: 3, reg: w2kw, asm: "VPMINUD", commutative: true, typ: "Vec128", resultInArg0: false},
+ {name: "VPMINUDMasked256", argLength: 3, reg: w2kw, asm: "VPMINUD", commutative: true, typ: "Vec256", resultInArg0: false},
+ {name: "VPMINUDMasked512", argLength: 3, reg: w2kw, asm: "VPMINUD", commutative: true, typ: "Vec512", resultInArg0: false},
+ {name: "VPMINUQ128", argLength: 2, reg: w21, asm: "VPMINUQ", commutative: true, typ: "Vec128", resultInArg0: false},
+ {name: "VPMINUQ256", argLength: 2, reg: w21, asm: "VPMINUQ", commutative: true, typ: "Vec256", resultInArg0: false},
+ {name: "VPMINUQ512", argLength: 2, reg: w21, asm: "VPMINUQ", commutative: true, typ: "Vec512", resultInArg0: false},
+ {name: "VPMINUQMasked128", argLength: 3, reg: w2kw, asm: "VPMINUQ", commutative: true, typ: "Vec128", resultInArg0: false},
+ {name: "VPMINUQMasked256", argLength: 3, reg: w2kw, asm: "VPMINUQ", commutative: true, typ: "Vec256", resultInArg0: false},
+ {name: "VPMINUQMasked512", argLength: 3, reg: w2kw, asm: "VPMINUQ", commutative: true, typ: "Vec512", resultInArg0: false},
+ {name: "VPMINUW128", argLength: 2, reg: v21, asm: "VPMINUW", commutative: true, typ: "Vec128", resultInArg0: false},
+ {name: "VPMINUW256", argLength: 2, reg: v21, asm: "VPMINUW", commutative: true, typ: "Vec256", resultInArg0: false},
+ {name: "VPMINUW512", argLength: 2, reg: w21, asm: "VPMINUW", commutative: true, typ: "Vec512", resultInArg0: false},
+ {name: "VPMINUWMasked128", argLength: 3, reg: w2kw, asm: "VPMINUW", commutative: true, typ: "Vec128", resultInArg0: false},
+ {name: "VPMINUWMasked256", argLength: 3, reg: w2kw, asm: "VPMINUW", commutative: true, typ: "Vec256", resultInArg0: false},
+ {name: "VPMINUWMasked512", argLength: 3, reg: w2kw, asm: "VPMINUW", commutative: true, typ: "Vec512", resultInArg0: false},
+ {name: "VPMULDQ128", argLength: 2, reg: v21, asm: "VPMULDQ", commutative: true, typ: "Vec128", resultInArg0: false},
+ {name: "VPMULDQ256", argLength: 2, reg: v21, asm: "VPMULDQ", commutative: true, typ: "Vec256", resultInArg0: false},
+ {name: "VPMULDQ512", argLength: 2, reg: w21, asm: "VPMULDQ", commutative: true, typ: "Vec512", resultInArg0: false},
{name: "VPMULDQMasked128", argLength: 3, reg: w2kw, asm: "VPMULDQ", commutative: true, typ: "Vec128", resultInArg0: false},
+ {name: "VPMULDQMasked256", argLength: 3, reg: w2kw, asm: "VPMULDQ", commutative: true, typ: "Vec256", resultInArg0: false},
+ {name: "VPMULDQMasked512", argLength: 3, reg: w2kw, asm: "VPMULDQ", commutative: true, typ: "Vec512", resultInArg0: false},
+ {name: "VPMULHUW128", argLength: 2, reg: v21, asm: "VPMULHUW", commutative: true, typ: "Vec128", resultInArg0: false},
+ {name: "VPMULHUW256", argLength: 2, reg: v21, asm: "VPMULHUW", commutative: true, typ: "Vec256", resultInArg0: false},
+ {name: "VPMULHUW512", argLength: 2, reg: w21, asm: "VPMULHUW", commutative: true, typ: "Vec512", resultInArg0: false},
+ {name: "VPMULHUWMasked128", argLength: 3, reg: w2kw, asm: "VPMULHUW", commutative: true, typ: "Vec128", resultInArg0: false},
+ {name: "VPMULHUWMasked256", argLength: 3, reg: w2kw, asm: "VPMULHUW", commutative: true, typ: "Vec256", resultInArg0: false},
+ {name: "VPMULHUWMasked512", argLength: 3, reg: w2kw, asm: "VPMULHUW", commutative: true, typ: "Vec512", resultInArg0: false},
+ {name: "VPMULHW128", argLength: 2, reg: v21, asm: "VPMULHW", commutative: true, typ: "Vec128", resultInArg0: false},
+ {name: "VPMULHW256", argLength: 2, reg: v21, asm: "VPMULHW", commutative: true, typ: "Vec256", resultInArg0: false},
+ {name: "VPMULHW512", argLength: 2, reg: w21, asm: "VPMULHW", commutative: true, typ: "Vec512", resultInArg0: false},
+ {name: "VPMULHWMasked128", argLength: 3, reg: w2kw, asm: "VPMULHW", commutative: true, typ: "Vec128", resultInArg0: false},
+ {name: "VPMULHWMasked256", argLength: 3, reg: w2kw, asm: "VPMULHW", commutative: true, typ: "Vec256", resultInArg0: false},
+ {name: "VPMULHWMasked512", argLength: 3, reg: w2kw, asm: "VPMULHW", commutative: true, typ: "Vec512", resultInArg0: false},
+ {name: "VPMULLD128", argLength: 2, reg: v21, asm: "VPMULLD", commutative: true, typ: "Vec128", resultInArg0: false},
+ {name: "VPMULLD256", argLength: 2, reg: v21, asm: "VPMULLD", commutative: true, typ: "Vec256", resultInArg0: false},
+ {name: "VPMULLD512", argLength: 2, reg: w21, asm: "VPMULLD", commutative: true, typ: "Vec512", resultInArg0: false},
+ {name: "VPMULLDMasked128", argLength: 3, reg: w2kw, asm: "VPMULLD", commutative: true, typ: "Vec128", resultInArg0: false},
+ {name: "VPMULLDMasked256", argLength: 3, reg: w2kw, asm: "VPMULLD", commutative: true, typ: "Vec256", resultInArg0: false},
+ {name: "VPMULLDMasked512", argLength: 3, reg: w2kw, asm: "VPMULLD", commutative: true, typ: "Vec512", resultInArg0: false},
{name: "VPMULLQ128", argLength: 2, reg: w21, asm: "VPMULLQ", commutative: true, typ: "Vec128", resultInArg0: false},
+ {name: "VPMULLQ256", argLength: 2, reg: w21, asm: "VPMULLQ", commutative: true, typ: "Vec256", resultInArg0: false},
+ {name: "VPMULLQ512", argLength: 2, reg: w21, asm: "VPMULLQ", commutative: true, typ: "Vec512", resultInArg0: false},
{name: "VPMULLQMasked128", argLength: 3, reg: w2kw, asm: "VPMULLQ", commutative: true, typ: "Vec128", resultInArg0: false},
- {name: "VPORQMasked128", argLength: 3, reg: w2kw, asm: "VPORQ", commutative: true, typ: "Vec128", resultInArg0: false},
+ {name: "VPMULLQMasked256", argLength: 3, reg: w2kw, asm: "VPMULLQ", commutative: true, typ: "Vec256", resultInArg0: false},
+ {name: "VPMULLQMasked512", argLength: 3, reg: w2kw, asm: "VPMULLQ", commutative: true, typ: "Vec512", resultInArg0: false},
+ {name: "VPMULLW128", argLength: 2, reg: v21, asm: "VPMULLW", commutative: true, typ: "Vec128", resultInArg0: false},
+ {name: "VPMULLW256", argLength: 2, reg: v21, asm: "VPMULLW", commutative: true, typ: "Vec256", resultInArg0: false},
+ {name: "VPMULLW512", argLength: 2, reg: w21, asm: "VPMULLW", commutative: true, typ: "Vec512", resultInArg0: false},
+ {name: "VPMULLWMasked128", argLength: 3, reg: w2kw, asm: "VPMULLW", commutative: true, typ: "Vec128", resultInArg0: false},
+ {name: "VPMULLWMasked256", argLength: 3, reg: w2kw, asm: "VPMULLW", commutative: true, typ: "Vec256", resultInArg0: false},
+ {name: "VPMULLWMasked512", argLength: 3, reg: w2kw, asm: "VPMULLW", commutative: true, typ: "Vec512", resultInArg0: false},
+ {name: "VPMULUDQ128", argLength: 2, reg: v21, asm: "VPMULUDQ", commutative: true, typ: "Vec128", resultInArg0: false},
+ {name: "VPMULUDQ256", argLength: 2, reg: v21, asm: "VPMULUDQ", commutative: true, typ: "Vec256", resultInArg0: false},
+ {name: "VPMULUDQ512", argLength: 2, reg: w21, asm: "VPMULUDQ", commutative: true, typ: "Vec512", resultInArg0: false},
+ {name: "VPMULUDQMasked128", argLength: 3, reg: w2kw, asm: "VPMULUDQ", commutative: true, typ: "Vec128", resultInArg0: false},
+ {name: "VPMULUDQMasked256", argLength: 3, reg: w2kw, asm: "VPMULUDQ", commutative: true, typ: "Vec256", resultInArg0: false},
+ {name: "VPMULUDQMasked512", argLength: 3, reg: w2kw, asm: "VPMULUDQ", commutative: true, typ: "Vec512", resultInArg0: false},
+ {name: "VPOPCNTB128", argLength: 1, reg: w11, asm: "VPOPCNTB", commutative: false, typ: "Vec128", resultInArg0: false},
+ {name: "VPOPCNTB256", argLength: 1, reg: w11, asm: "VPOPCNTB", commutative: false, typ: "Vec256", resultInArg0: false},
+ {name: "VPOPCNTB512", argLength: 1, reg: w11, asm: "VPOPCNTB", commutative: false, typ: "Vec512", resultInArg0: false},
+ {name: "VPOPCNTBMasked128", argLength: 2, reg: wkw, asm: "VPOPCNTB", commutative: false, typ: "Vec128", resultInArg0: false},
+ {name: "VPOPCNTBMasked256", argLength: 2, reg: wkw, asm: "VPOPCNTB", commutative: false, typ: "Vec256", resultInArg0: false},
+ {name: "VPOPCNTBMasked512", argLength: 2, reg: wkw, asm: "VPOPCNTB", commutative: false, typ: "Vec512", resultInArg0: false},
+ {name: "VPOPCNTD128", argLength: 1, reg: w11, asm: "VPOPCNTD", commutative: false, typ: "Vec128", resultInArg0: false},
+ {name: "VPOPCNTD256", argLength: 1, reg: w11, asm: "VPOPCNTD", commutative: false, typ: "Vec256", resultInArg0: false},
+ {name: "VPOPCNTD512", argLength: 1, reg: w11, asm: "VPOPCNTD", commutative: false, typ: "Vec512", resultInArg0: false},
+ {name: "VPOPCNTDMasked128", argLength: 2, reg: wkw, asm: "VPOPCNTD", commutative: false, typ: "Vec128", resultInArg0: false},
+ {name: "VPOPCNTDMasked256", argLength: 2, reg: wkw, asm: "VPOPCNTD", commutative: false, typ: "Vec256", resultInArg0: false},
+ {name: "VPOPCNTDMasked512", argLength: 2, reg: wkw, asm: "VPOPCNTD", commutative: false, typ: "Vec512", resultInArg0: false},
{name: "VPOPCNTQ128", argLength: 1, reg: w11, asm: "VPOPCNTQ", commutative: false, typ: "Vec128", resultInArg0: false},
+ {name: "VPOPCNTQ256", argLength: 1, reg: w11, asm: "VPOPCNTQ", commutative: false, typ: "Vec256", resultInArg0: false},
+ {name: "VPOPCNTQ512", argLength: 1, reg: w11, asm: "VPOPCNTQ", commutative: false, typ: "Vec512", resultInArg0: false},
{name: "VPOPCNTQMasked128", argLength: 2, reg: wkw, asm: "VPOPCNTQ", commutative: false, typ: "Vec128", resultInArg0: false},
+ {name: "VPOPCNTQMasked256", argLength: 2, reg: wkw, asm: "VPOPCNTQ", commutative: false, typ: "Vec256", resultInArg0: false},
+ {name: "VPOPCNTQMasked512", argLength: 2, reg: wkw, asm: "VPOPCNTQ", commutative: false, typ: "Vec512", resultInArg0: false},
+ {name: "VPOPCNTW128", argLength: 1, reg: w11, asm: "VPOPCNTW", commutative: false, typ: "Vec128", resultInArg0: false},
+ {name: "VPOPCNTW256", argLength: 1, reg: w11, asm: "VPOPCNTW", commutative: false, typ: "Vec256", resultInArg0: false},
+ {name: "VPOPCNTW512", argLength: 1, reg: w11, asm: "VPOPCNTW", commutative: false, typ: "Vec512", resultInArg0: false},
+ {name: "VPOPCNTWMasked128", argLength: 2, reg: wkw, asm: "VPOPCNTW", commutative: false, typ: "Vec128", resultInArg0: false},
+ {name: "VPOPCNTWMasked256", argLength: 2, reg: wkw, asm: "VPOPCNTW", commutative: false, typ: "Vec256", resultInArg0: false},
+ {name: "VPOPCNTWMasked512", argLength: 2, reg: wkw, asm: "VPOPCNTW", commutative: false, typ: "Vec512", resultInArg0: false},
+ {name: "VPOR128", argLength: 2, reg: v21, asm: "VPOR", commutative: true, typ: "Vec128", resultInArg0: false},
+ {name: "VPOR256", argLength: 2, reg: v21, asm: "VPOR", commutative: true, typ: "Vec256", resultInArg0: false},
+ {name: "VPORD512", argLength: 2, reg: w21, asm: "VPORD", commutative: true, typ: "Vec512", resultInArg0: false},
+ {name: "VPORDMasked128", argLength: 3, reg: w2kw, asm: "VPORD", commutative: true, typ: "Vec128", resultInArg0: false},
+ {name: "VPORDMasked256", argLength: 3, reg: w2kw, asm: "VPORD", commutative: true, typ: "Vec256", resultInArg0: false},
+ {name: "VPORDMasked512", argLength: 3, reg: w2kw, asm: "VPORD", commutative: true, typ: "Vec512", resultInArg0: false},
+ {name: "VPORQ512", argLength: 2, reg: w21, asm: "VPORQ", commutative: true, typ: "Vec512", resultInArg0: false},
+ {name: "VPORQMasked128", argLength: 3, reg: w2kw, asm: "VPORQ", commutative: true, typ: "Vec128", resultInArg0: false},
+ {name: "VPORQMasked256", argLength: 3, reg: w2kw, asm: "VPORQ", commutative: true, typ: "Vec256", resultInArg0: false},
+ {name: "VPORQMasked512", argLength: 3, reg: w2kw, asm: "VPORQ", commutative: true, typ: "Vec512", resultInArg0: false},
+ {name: "VPROLVD128", argLength: 2, reg: w21, asm: "VPROLVD", commutative: false, typ: "Vec128", resultInArg0: false},
+ {name: "VPROLVD256", argLength: 2, reg: w21, asm: "VPROLVD", commutative: false, typ: "Vec256", resultInArg0: false},
+ {name: "VPROLVD512", argLength: 2, reg: w21, asm: "VPROLVD", commutative: false, typ: "Vec512", resultInArg0: false},
+ {name: "VPROLVDMasked128", argLength: 3, reg: w2kw, asm: "VPROLVD", commutative: false, typ: "Vec128", resultInArg0: false},
+ {name: "VPROLVDMasked256", argLength: 3, reg: w2kw, asm: "VPROLVD", commutative: false, typ: "Vec256", resultInArg0: false},
+ {name: "VPROLVDMasked512", argLength: 3, reg: w2kw, asm: "VPROLVD", commutative: false, typ: "Vec512", resultInArg0: false},
{name: "VPROLVQ128", argLength: 2, reg: w21, asm: "VPROLVQ", commutative: false, typ: "Vec128", resultInArg0: false},
+ {name: "VPROLVQ256", argLength: 2, reg: w21, asm: "VPROLVQ", commutative: false, typ: "Vec256", resultInArg0: false},
+ {name: "VPROLVQ512", argLength: 2, reg: w21, asm: "VPROLVQ", commutative: false, typ: "Vec512", resultInArg0: false},
{name: "VPROLVQMasked128", argLength: 3, reg: w2kw, asm: "VPROLVQ", commutative: false, typ: "Vec128", resultInArg0: false},
+ {name: "VPROLVQMasked256", argLength: 3, reg: w2kw, asm: "VPROLVQ", commutative: false, typ: "Vec256", resultInArg0: false},
+ {name: "VPROLVQMasked512", argLength: 3, reg: w2kw, asm: "VPROLVQ", commutative: false, typ: "Vec512", resultInArg0: false},
+ {name: "VPRORVD128", argLength: 2, reg: w21, asm: "VPRORVD", commutative: false, typ: "Vec128", resultInArg0: false},
+ {name: "VPRORVD256", argLength: 2, reg: w21, asm: "VPRORVD", commutative: false, typ: "Vec256", resultInArg0: false},
+ {name: "VPRORVD512", argLength: 2, reg: w21, asm: "VPRORVD", commutative: false, typ: "Vec512", resultInArg0: false},
+ {name: "VPRORVDMasked128", argLength: 3, reg: w2kw, asm: "VPRORVD", commutative: false, typ: "Vec128", resultInArg0: false},
+ {name: "VPRORVDMasked256", argLength: 3, reg: w2kw, asm: "VPRORVD", commutative: false, typ: "Vec256", resultInArg0: false},
+ {name: "VPRORVDMasked512", argLength: 3, reg: w2kw, asm: "VPRORVD", commutative: false, typ: "Vec512", resultInArg0: false},
{name: "VPRORVQ128", argLength: 2, reg: w21, asm: "VPRORVQ", commutative: false, typ: "Vec128", resultInArg0: false},
+ {name: "VPRORVQ256", argLength: 2, reg: w21, asm: "VPRORVQ", commutative: false, typ: "Vec256", resultInArg0: false},
+ {name: "VPRORVQ512", argLength: 2, reg: w21, asm: "VPRORVQ", commutative: false, typ: "Vec512", resultInArg0: false},
{name: "VPRORVQMasked128", argLength: 3, reg: w2kw, asm: "VPRORVQ", commutative: false, typ: "Vec128", resultInArg0: false},
- {name: "VPSLLQ128", argLength: 2, reg: vfpv, asm: "VPSLLQ", commutative: false, typ: "Vec128", resultInArg0: false},
- {name: "VPSLLQMasked128", argLength: 3, reg: wfpkw, asm: "VPSLLQ", commutative: false, typ: "Vec128", resultInArg0: false},
- {name: "VPSRAQ128", argLength: 2, reg: wfpw, asm: "VPSRAQ", commutative: false, typ: "Vec128", resultInArg0: false},
- {name: "VPSRAQMasked128", argLength: 3, reg: wfpkw, asm: "VPSRAQ", commutative: false, typ: "Vec128", resultInArg0: false},
- {name: "VPSLLVQ128", argLength: 2, reg: v21, asm: "VPSLLVQ", commutative: false, typ: "Vec128", resultInArg0: false},
+ {name: "VPRORVQMasked256", argLength: 3, reg: w2kw, asm: "VPRORVQ", commutative: false, typ: "Vec256", resultInArg0: false},
+ {name: "VPRORVQMasked512", argLength: 3, reg: w2kw, asm: "VPRORVQ", commutative: false, typ: "Vec512", resultInArg0: false},
+ {name: "VPSHLDVD128", argLength: 3, reg: w31, asm: "VPSHLDVD", commutative: false, typ: "Vec128", resultInArg0: true},
+ {name: "VPSHLDVD256", argLength: 3, reg: w31, asm: "VPSHLDVD", commutative: false, typ: "Vec256", resultInArg0: true},
+ {name: "VPSHLDVD512", argLength: 3, reg: w31, asm: "VPSHLDVD", commutative: false, typ: "Vec512", resultInArg0: true},
+ {name: "VPSHLDVDMasked128", argLength: 4, reg: w3kw, asm: "VPSHLDVD", commutative: false, typ: "Vec128", resultInArg0: true},
+ {name: "VPSHLDVDMasked256", argLength: 4, reg: w3kw, asm: "VPSHLDVD", commutative: false, typ: "Vec256", resultInArg0: true},
+ {name: "VPSHLDVDMasked512", argLength: 4, reg: w3kw, asm: "VPSHLDVD", commutative: false, typ: "Vec512", resultInArg0: true},
{name: "VPSHLDVQ128", argLength: 3, reg: w31, asm: "VPSHLDVQ", commutative: false, typ: "Vec128", resultInArg0: true},
+ {name: "VPSHLDVQ256", argLength: 3, reg: w31, asm: "VPSHLDVQ", commutative: false, typ: "Vec256", resultInArg0: true},
+ {name: "VPSHLDVQ512", argLength: 3, reg: w31, asm: "VPSHLDVQ", commutative: false, typ: "Vec512", resultInArg0: true},
{name: "VPSHLDVQMasked128", argLength: 4, reg: w3kw, asm: "VPSHLDVQ", commutative: false, typ: "Vec128", resultInArg0: true},
- {name: "VPSLLVQMasked128", argLength: 3, reg: w2kw, asm: "VPSLLVQ", commutative: false, typ: "Vec128", resultInArg0: false},
- {name: "VPSRAVQ128", argLength: 2, reg: w21, asm: "VPSRAVQ", commutative: false, typ: "Vec128", resultInArg0: false},
+ {name: "VPSHLDVQMasked256", argLength: 4, reg: w3kw, asm: "VPSHLDVQ", commutative: false, typ: "Vec256", resultInArg0: true},
+ {name: "VPSHLDVQMasked512", argLength: 4, reg: w3kw, asm: "VPSHLDVQ", commutative: false, typ: "Vec512", resultInArg0: true},
+ {name: "VPSHLDVW128", argLength: 3, reg: w31, asm: "VPSHLDVW", commutative: false, typ: "Vec128", resultInArg0: true},
+ {name: "VPSHLDVW256", argLength: 3, reg: w31, asm: "VPSHLDVW", commutative: false, typ: "Vec256", resultInArg0: true},
+ {name: "VPSHLDVW512", argLength: 3, reg: w31, asm: "VPSHLDVW", commutative: false, typ: "Vec512", resultInArg0: true},
+ {name: "VPSHLDVWMasked128", argLength: 4, reg: w3kw, asm: "VPSHLDVW", commutative: false, typ: "Vec128", resultInArg0: true},
+ {name: "VPSHLDVWMasked256", argLength: 4, reg: w3kw, asm: "VPSHLDVW", commutative: false, typ: "Vec256", resultInArg0: true},
+ {name: "VPSHLDVWMasked512", argLength: 4, reg: w3kw, asm: "VPSHLDVW", commutative: false, typ: "Vec512", resultInArg0: true},
+ {name: "VPSHRDVD128", argLength: 3, reg: w31, asm: "VPSHRDVD", commutative: false, typ: "Vec128", resultInArg0: true},
+ {name: "VPSHRDVD256", argLength: 3, reg: w31, asm: "VPSHRDVD", commutative: false, typ: "Vec256", resultInArg0: true},
+ {name: "VPSHRDVD512", argLength: 3, reg: w31, asm: "VPSHRDVD", commutative: false, typ: "Vec512", resultInArg0: true},
+ {name: "VPSHRDVDMasked128", argLength: 4, reg: w3kw, asm: "VPSHRDVD", commutative: false, typ: "Vec128", resultInArg0: true},
+ {name: "VPSHRDVDMasked256", argLength: 4, reg: w3kw, asm: "VPSHRDVD", commutative: false, typ: "Vec256", resultInArg0: true},
+ {name: "VPSHRDVDMasked512", argLength: 4, reg: w3kw, asm: "VPSHRDVD", commutative: false, typ: "Vec512", resultInArg0: true},
{name: "VPSHRDVQ128", argLength: 3, reg: w31, asm: "VPSHRDVQ", commutative: false, typ: "Vec128", resultInArg0: true},
+ {name: "VPSHRDVQ256", argLength: 3, reg: w31, asm: "VPSHRDVQ", commutative: false, typ: "Vec256", resultInArg0: true},
+ {name: "VPSHRDVQ512", argLength: 3, reg: w31, asm: "VPSHRDVQ", commutative: false, typ: "Vec512", resultInArg0: true},
{name: "VPSHRDVQMasked128", argLength: 4, reg: w3kw, asm: "VPSHRDVQ", commutative: false, typ: "Vec128", resultInArg0: true},
- {name: "VPSRAVQMasked128", argLength: 3, reg: w2kw, asm: "VPSRAVQ", commutative: false, typ: "Vec128", resultInArg0: false},
- {name: "VPSUBQ128", argLength: 2, reg: v21, asm: "VPSUBQ", commutative: false, typ: "Vec128", resultInArg0: false},
- {name: "VPSUBQMasked128", argLength: 3, reg: w2kw, asm: "VPSUBQ", commutative: false, typ: "Vec128", resultInArg0: false},
- {name: "VPXORQMasked128", argLength: 3, reg: w2kw, asm: "VPXORQ", commutative: true, typ: "Vec128", resultInArg0: false},
- {name: "VPABSQ256", argLength: 1, reg: w11, asm: "VPABSQ", commutative: false, typ: "Vec256", resultInArg0: false},
- {name: "VPABSQMasked256", argLength: 2, reg: wkw, asm: "VPABSQ", commutative: false, typ: "Vec256", resultInArg0: false},
- {name: "VPADDQ256", argLength: 2, reg: v21, asm: "VPADDQ", commutative: true, typ: "Vec256", resultInArg0: false},
- {name: "VPADDQMasked256", argLength: 3, reg: w2kw, asm: "VPADDQ", commutative: true, typ: "Vec256", resultInArg0: false},
- {name: "VPANDQMasked256", argLength: 3, reg: w2kw, asm: "VPANDQ", commutative: true, typ: "Vec256", resultInArg0: false},
- {name: "VPANDNQMasked256", argLength: 3, reg: w2kw, asm: "VPANDNQ", commutative: false, typ: "Vec256", resultInArg0: false},
- {name: "VPCOMPRESSQMasked256", argLength: 2, reg: wkw, asm: "VPCOMPRESSQ", commutative: false, typ: "Vec256", resultInArg0: false},
- {name: "VPCMPEQQ256", argLength: 2, reg: v21, asm: "VPCMPEQQ", commutative: true, typ: "Vec256", resultInArg0: false},
- {name: "VPCMPGTQ256", argLength: 2, reg: v21, asm: "VPCMPGTQ", commutative: false, typ: "Vec256", resultInArg0: false},
- {name: "VPMAXSQ256", argLength: 2, reg: w21, asm: "VPMAXSQ", commutative: true, typ: "Vec256", resultInArg0: false},
- {name: "VPMAXSQMasked256", argLength: 3, reg: w2kw, asm: "VPMAXSQ", commutative: true, typ: "Vec256", resultInArg0: false},
- {name: "VPMINSQ256", argLength: 2, reg: w21, asm: "VPMINSQ", commutative: true, typ: "Vec256", resultInArg0: false},
- {name: "VPMINSQMasked256", argLength: 3, reg: w2kw, asm: "VPMINSQ", commutative: true, typ: "Vec256", resultInArg0: false},
- {name: "VPMULDQMasked256", argLength: 3, reg: w2kw, asm: "VPMULDQ", commutative: true, typ: "Vec256", resultInArg0: false},
- {name: "VPMULLQ256", argLength: 2, reg: w21, asm: "VPMULLQ", commutative: true, typ: "Vec256", resultInArg0: false},
- {name: "VPMULLQMasked256", argLength: 3, reg: w2kw, asm: "VPMULLQ", commutative: true, typ: "Vec256", resultInArg0: false},
- {name: "VPORQMasked256", argLength: 3, reg: w2kw, asm: "VPORQ", commutative: true, typ: "Vec256", resultInArg0: false},
- {name: "VPOPCNTQ256", argLength: 1, reg: w11, asm: "VPOPCNTQ", commutative: false, typ: "Vec256", resultInArg0: false},
- {name: "VPOPCNTQMasked256", argLength: 2, reg: wkw, asm: "VPOPCNTQ", commutative: false, typ: "Vec256", resultInArg0: false},
- {name: "VPROLVQ256", argLength: 2, reg: w21, asm: "VPROLVQ", commutative: false, typ: "Vec256", resultInArg0: false},
- {name: "VPROLVQMasked256", argLength: 3, reg: w2kw, asm: "VPROLVQ", commutative: false, typ: "Vec256", resultInArg0: false},
- {name: "VPRORVQ256", argLength: 2, reg: w21, asm: "VPRORVQ", commutative: false, typ: "Vec256", resultInArg0: false},
- {name: "VPRORVQMasked256", argLength: 3, reg: w2kw, asm: "VPRORVQ", commutative: false, typ: "Vec256", resultInArg0: false},
+ {name: "VPSHRDVQMasked256", argLength: 4, reg: w3kw, asm: "VPSHRDVQ", commutative: false, typ: "Vec256", resultInArg0: true},
+ {name: "VPSHRDVQMasked512", argLength: 4, reg: w3kw, asm: "VPSHRDVQ", commutative: false, typ: "Vec512", resultInArg0: true},
+ {name: "VPSHRDVW128", argLength: 3, reg: w31, asm: "VPSHRDVW", commutative: false, typ: "Vec128", resultInArg0: true},
+ {name: "VPSHRDVW256", argLength: 3, reg: w31, asm: "VPSHRDVW", commutative: false, typ: "Vec256", resultInArg0: true},
+ {name: "VPSHRDVW512", argLength: 3, reg: w31, asm: "VPSHRDVW", commutative: false, typ: "Vec512", resultInArg0: true},
+ {name: "VPSHRDVWMasked128", argLength: 4, reg: w3kw, asm: "VPSHRDVW", commutative: false, typ: "Vec128", resultInArg0: true},
+ {name: "VPSHRDVWMasked256", argLength: 4, reg: w3kw, asm: "VPSHRDVW", commutative: false, typ: "Vec256", resultInArg0: true},
+ {name: "VPSHRDVWMasked512", argLength: 4, reg: w3kw, asm: "VPSHRDVW", commutative: false, typ: "Vec512", resultInArg0: true},
+ {name: "VPSIGNB128", argLength: 2, reg: v21, asm: "VPSIGNB", commutative: false, typ: "Vec128", resultInArg0: false},
+ {name: "VPSIGNB256", argLength: 2, reg: v21, asm: "VPSIGNB", commutative: false, typ: "Vec256", resultInArg0: false},
+ {name: "VPSIGND128", argLength: 2, reg: v21, asm: "VPSIGND", commutative: false, typ: "Vec128", resultInArg0: false},
+ {name: "VPSIGND256", argLength: 2, reg: v21, asm: "VPSIGND", commutative: false, typ: "Vec256", resultInArg0: false},
+ {name: "VPSIGNW128", argLength: 2, reg: v21, asm: "VPSIGNW", commutative: false, typ: "Vec128", resultInArg0: false},
+ {name: "VPSIGNW256", argLength: 2, reg: v21, asm: "VPSIGNW", commutative: false, typ: "Vec256", resultInArg0: false},
+ {name: "VPSLLD128", argLength: 2, reg: vfpv, asm: "VPSLLD", commutative: false, typ: "Vec128", resultInArg0: false},
+ {name: "VPSLLD256", argLength: 2, reg: vfpv, asm: "VPSLLD", commutative: false, typ: "Vec256", resultInArg0: false},
+ {name: "VPSLLD512", argLength: 2, reg: wfpw, asm: "VPSLLD", commutative: false, typ: "Vec512", resultInArg0: false},
+ {name: "VPSLLDMasked128", argLength: 3, reg: wfpkw, asm: "VPSLLD", commutative: false, typ: "Vec128", resultInArg0: false},
+ {name: "VPSLLDMasked256", argLength: 3, reg: wfpkw, asm: "VPSLLD", commutative: false, typ: "Vec256", resultInArg0: false},
+ {name: "VPSLLDMasked512", argLength: 3, reg: wfpkw, asm: "VPSLLD", commutative: false, typ: "Vec512", resultInArg0: false},
+ {name: "VPSLLQ128", argLength: 2, reg: vfpv, asm: "VPSLLQ", commutative: false, typ: "Vec128", resultInArg0: false},
{name: "VPSLLQ256", argLength: 2, reg: vfpv, asm: "VPSLLQ", commutative: false, typ: "Vec256", resultInArg0: false},
+ {name: "VPSLLQ512", argLength: 2, reg: wfpw, asm: "VPSLLQ", commutative: false, typ: "Vec512", resultInArg0: false},
+ {name: "VPSLLQMasked128", argLength: 3, reg: wfpkw, asm: "VPSLLQ", commutative: false, typ: "Vec128", resultInArg0: false},
{name: "VPSLLQMasked256", argLength: 3, reg: wfpkw, asm: "VPSLLQ", commutative: false, typ: "Vec256", resultInArg0: false},
- {name: "VPSRAQ256", argLength: 2, reg: wfpw, asm: "VPSRAQ", commutative: false, typ: "Vec256", resultInArg0: false},
- {name: "VPSRAQMasked256", argLength: 3, reg: wfpkw, asm: "VPSRAQ", commutative: false, typ: "Vec256", resultInArg0: false},
+ {name: "VPSLLQMasked512", argLength: 3, reg: wfpkw, asm: "VPSLLQ", commutative: false, typ: "Vec512", resultInArg0: false},
+ {name: "VPSLLVD128", argLength: 2, reg: v21, asm: "VPSLLVD", commutative: false, typ: "Vec128", resultInArg0: false},
+ {name: "VPSLLVD256", argLength: 2, reg: v21, asm: "VPSLLVD", commutative: false, typ: "Vec256", resultInArg0: false},
+ {name: "VPSLLVD512", argLength: 2, reg: w21, asm: "VPSLLVD", commutative: false, typ: "Vec512", resultInArg0: false},
+ {name: "VPSLLVDMasked128", argLength: 3, reg: w2kw, asm: "VPSLLVD", commutative: false, typ: "Vec128", resultInArg0: false},
+ {name: "VPSLLVDMasked256", argLength: 3, reg: w2kw, asm: "VPSLLVD", commutative: false, typ: "Vec256", resultInArg0: false},
+ {name: "VPSLLVDMasked512", argLength: 3, reg: w2kw, asm: "VPSLLVD", commutative: false, typ: "Vec512", resultInArg0: false},
+ {name: "VPSLLVQ128", argLength: 2, reg: v21, asm: "VPSLLVQ", commutative: false, typ: "Vec128", resultInArg0: false},
{name: "VPSLLVQ256", argLength: 2, reg: v21, asm: "VPSLLVQ", commutative: false, typ: "Vec256", resultInArg0: false},
- {name: "VPSHLDVQ256", argLength: 3, reg: w31, asm: "VPSHLDVQ", commutative: false, typ: "Vec256", resultInArg0: true},
- {name: "VPSHLDVQMasked256", argLength: 4, reg: w3kw, asm: "VPSHLDVQ", commutative: false, typ: "Vec256", resultInArg0: true},
+ {name: "VPSLLVQ512", argLength: 2, reg: w21, asm: "VPSLLVQ", commutative: false, typ: "Vec512", resultInArg0: false},
+ {name: "VPSLLVQMasked128", argLength: 3, reg: w2kw, asm: "VPSLLVQ", commutative: false, typ: "Vec128", resultInArg0: false},
{name: "VPSLLVQMasked256", argLength: 3, reg: w2kw, asm: "VPSLLVQ", commutative: false, typ: "Vec256", resultInArg0: false},
- {name: "VPSRAVQ256", argLength: 2, reg: w21, asm: "VPSRAVQ", commutative: false, typ: "Vec256", resultInArg0: false},
- {name: "VPSHRDVQ256", argLength: 3, reg: w31, asm: "VPSHRDVQ", commutative: false, typ: "Vec256", resultInArg0: true},
- {name: "VPSHRDVQMasked256", argLength: 4, reg: w3kw, asm: "VPSHRDVQ", commutative: false, typ: "Vec256", resultInArg0: true},
- {name: "VPSRAVQMasked256", argLength: 3, reg: w2kw, asm: "VPSRAVQ", commutative: false, typ: "Vec256", resultInArg0: false},
- {name: "VPSUBQ256", argLength: 2, reg: v21, asm: "VPSUBQ", commutative: false, typ: "Vec256", resultInArg0: false},
- {name: "VPSUBQMasked256", argLength: 3, reg: w2kw, asm: "VPSUBQ", commutative: false, typ: "Vec256", resultInArg0: false},
- {name: "VPXORQMasked256", argLength: 3, reg: w2kw, asm: "VPXORQ", commutative: true, typ: "Vec256", resultInArg0: false},
- {name: "VPABSQ512", argLength: 1, reg: w11, asm: "VPABSQ", commutative: false, typ: "Vec512", resultInArg0: false},
- {name: "VPABSQMasked512", argLength: 2, reg: wkw, asm: "VPABSQ", commutative: false, typ: "Vec512", resultInArg0: false},
- {name: "VPADDQ512", argLength: 2, reg: w21, asm: "VPADDQ", commutative: true, typ: "Vec512", resultInArg0: false},
- {name: "VPADDQMasked512", argLength: 3, reg: w2kw, asm: "VPADDQ", commutative: true, typ: "Vec512", resultInArg0: false},
- {name: "VPANDQ512", argLength: 2, reg: w21, asm: "VPANDQ", commutative: true, typ: "Vec512", resultInArg0: false},
- {name: "VPANDQMasked512", argLength: 3, reg: w2kw, asm: "VPANDQ", commutative: true, typ: "Vec512", resultInArg0: false},
- {name: "VPANDNQ512", argLength: 2, reg: w21, asm: "VPANDNQ", commutative: false, typ: "Vec512", resultInArg0: false},
- {name: "VPANDNQMasked512", argLength: 3, reg: w2kw, asm: "VPANDNQ", commutative: false, typ: "Vec512", resultInArg0: false},
- {name: "VPCOMPRESSQMasked512", argLength: 2, reg: wkw, asm: "VPCOMPRESSQ", commutative: false, typ: "Vec512", resultInArg0: false},
- {name: "VPCMPEQQ512", argLength: 2, reg: w2k, asm: "VPCMPEQQ", commutative: true, typ: "Mask", resultInArg0: false},
- {name: "VPCMPGTQ512", argLength: 2, reg: w2k, asm: "VPCMPGTQ", commutative: false, typ: "Mask", resultInArg0: false},
- {name: "VPMAXSQ512", argLength: 2, reg: w21, asm: "VPMAXSQ", commutative: true, typ: "Vec512", resultInArg0: false},
- {name: "VPMAXSQMasked512", argLength: 3, reg: w2kw, asm: "VPMAXSQ", commutative: true, typ: "Vec512", resultInArg0: false},
- {name: "VPMINSQ512", argLength: 2, reg: w21, asm: "VPMINSQ", commutative: true, typ: "Vec512", resultInArg0: false},
- {name: "VPMINSQMasked512", argLength: 3, reg: w2kw, asm: "VPMINSQ", commutative: true, typ: "Vec512", resultInArg0: false},
- {name: "VPMULDQ512", argLength: 2, reg: w21, asm: "VPMULDQ", commutative: true, typ: "Vec512", resultInArg0: false},
- {name: "VPMULDQMasked512", argLength: 3, reg: w2kw, asm: "VPMULDQ", commutative: true, typ: "Vec512", resultInArg0: false},
- {name: "VPMULLQ512", argLength: 2, reg: w21, asm: "VPMULLQ", commutative: true, typ: "Vec512", resultInArg0: false},
- {name: "VPMULLQMasked512", argLength: 3, reg: w2kw, asm: "VPMULLQ", commutative: true, typ: "Vec512", resultInArg0: false},
- {name: "VPORQ512", argLength: 2, reg: w21, asm: "VPORQ", commutative: true, typ: "Vec512", resultInArg0: false},
- {name: "VPORQMasked512", argLength: 3, reg: w2kw, asm: "VPORQ", commutative: true, typ: "Vec512", resultInArg0: false},
- {name: "VPOPCNTQ512", argLength: 1, reg: w11, asm: "VPOPCNTQ", commutative: false, typ: "Vec512", resultInArg0: false},
- {name: "VPOPCNTQMasked512", argLength: 2, reg: wkw, asm: "VPOPCNTQ", commutative: false, typ: "Vec512", resultInArg0: false},
- {name: "VPROLVQ512", argLength: 2, reg: w21, asm: "VPROLVQ", commutative: false, typ: "Vec512", resultInArg0: false},
- {name: "VPROLVQMasked512", argLength: 3, reg: w2kw, asm: "VPROLVQ", commutative: false, typ: "Vec512", resultInArg0: false},
- {name: "VPRORVQ512", argLength: 2, reg: w21, asm: "VPRORVQ", commutative: false, typ: "Vec512", resultInArg0: false},
- {name: "VPRORVQMasked512", argLength: 3, reg: w2kw, asm: "VPRORVQ", commutative: false, typ: "Vec512", resultInArg0: false},
- {name: "VPSLLQ512", argLength: 2, reg: wfpw, asm: "VPSLLQ", commutative: false, typ: "Vec512", resultInArg0: false},
- {name: "VPSLLQMasked512", argLength: 3, reg: wfpkw, asm: "VPSLLQ", commutative: false, typ: "Vec512", resultInArg0: false},
+ {name: "VPSLLVQMasked512", argLength: 3, reg: w2kw, asm: "VPSLLVQ", commutative: false, typ: "Vec512", resultInArg0: false},
+ {name: "VPSLLVW128", argLength: 2, reg: w21, asm: "VPSLLVW", commutative: false, typ: "Vec128", resultInArg0: false},
+ {name: "VPSLLVW256", argLength: 2, reg: w21, asm: "VPSLLVW", commutative: false, typ: "Vec256", resultInArg0: false},
+ {name: "VPSLLVW512", argLength: 2, reg: w21, asm: "VPSLLVW", commutative: false, typ: "Vec512", resultInArg0: false},
+ {name: "VPSLLVWMasked128", argLength: 3, reg: w2kw, asm: "VPSLLVW", commutative: false, typ: "Vec128", resultInArg0: false},
+ {name: "VPSLLVWMasked256", argLength: 3, reg: w2kw, asm: "VPSLLVW", commutative: false, typ: "Vec256", resultInArg0: false},
+ {name: "VPSLLVWMasked512", argLength: 3, reg: w2kw, asm: "VPSLLVW", commutative: false, typ: "Vec512", resultInArg0: false},
+ {name: "VPSLLW128", argLength: 2, reg: vfpv, asm: "VPSLLW", commutative: false, typ: "Vec128", resultInArg0: false},
+ {name: "VPSLLW256", argLength: 2, reg: vfpv, asm: "VPSLLW", commutative: false, typ: "Vec256", resultInArg0: false},
+ {name: "VPSLLW512", argLength: 2, reg: wfpw, asm: "VPSLLW", commutative: false, typ: "Vec512", resultInArg0: false},
+ {name: "VPSLLWMasked128", argLength: 3, reg: wfpkw, asm: "VPSLLW", commutative: false, typ: "Vec128", resultInArg0: false},
+ {name: "VPSLLWMasked256", argLength: 3, reg: wfpkw, asm: "VPSLLW", commutative: false, typ: "Vec256", resultInArg0: false},
+ {name: "VPSLLWMasked512", argLength: 3, reg: wfpkw, asm: "VPSLLW", commutative: false, typ: "Vec512", resultInArg0: false},
+ {name: "VPSRAD128", argLength: 2, reg: vfpv, asm: "VPSRAD", commutative: false, typ: "Vec128", resultInArg0: false},
+ {name: "VPSRAD256", argLength: 2, reg: vfpv, asm: "VPSRAD", commutative: false, typ: "Vec256", resultInArg0: false},
+ {name: "VPSRAD512", argLength: 2, reg: wfpw, asm: "VPSRAD", commutative: false, typ: "Vec512", resultInArg0: false},
+ {name: "VPSRADMasked128", argLength: 3, reg: wfpkw, asm: "VPSRAD", commutative: false, typ: "Vec128", resultInArg0: false},
+ {name: "VPSRADMasked256", argLength: 3, reg: wfpkw, asm: "VPSRAD", commutative: false, typ: "Vec256", resultInArg0: false},
+ {name: "VPSRADMasked512", argLength: 3, reg: wfpkw, asm: "VPSRAD", commutative: false, typ: "Vec512", resultInArg0: false},
+ {name: "VPSRAQ128", argLength: 2, reg: wfpw, asm: "VPSRAQ", commutative: false, typ: "Vec128", resultInArg0: false},
+ {name: "VPSRAQ256", argLength: 2, reg: wfpw, asm: "VPSRAQ", commutative: false, typ: "Vec256", resultInArg0: false},
{name: "VPSRAQ512", argLength: 2, reg: wfpw, asm: "VPSRAQ", commutative: false, typ: "Vec512", resultInArg0: false},
+ {name: "VPSRAQMasked128", argLength: 3, reg: wfpkw, asm: "VPSRAQ", commutative: false, typ: "Vec128", resultInArg0: false},
+ {name: "VPSRAQMasked256", argLength: 3, reg: wfpkw, asm: "VPSRAQ", commutative: false, typ: "Vec256", resultInArg0: false},
{name: "VPSRAQMasked512", argLength: 3, reg: wfpkw, asm: "VPSRAQ", commutative: false, typ: "Vec512", resultInArg0: false},
- {name: "VPSLLVQ512", argLength: 2, reg: w21, asm: "VPSLLVQ", commutative: false, typ: "Vec512", resultInArg0: false},
- {name: "VPSHLDVQ512", argLength: 3, reg: w31, asm: "VPSHLDVQ", commutative: false, typ: "Vec512", resultInArg0: true},
- {name: "VPSHLDVQMasked512", argLength: 4, reg: w3kw, asm: "VPSHLDVQ", commutative: false, typ: "Vec512", resultInArg0: true},
- {name: "VPSLLVQMasked512", argLength: 3, reg: w2kw, asm: "VPSLLVQ", commutative: false, typ: "Vec512", resultInArg0: false},
+ {name: "VPSRAVD128", argLength: 2, reg: v21, asm: "VPSRAVD", commutative: false, typ: "Vec128", resultInArg0: false},
+ {name: "VPSRAVD256", argLength: 2, reg: v21, asm: "VPSRAVD", commutative: false, typ: "Vec256", resultInArg0: false},
+ {name: "VPSRAVD512", argLength: 2, reg: w21, asm: "VPSRAVD", commutative: false, typ: "Vec512", resultInArg0: false},
+ {name: "VPSRAVDMasked128", argLength: 3, reg: w2kw, asm: "VPSRAVD", commutative: false, typ: "Vec128", resultInArg0: false},
+ {name: "VPSRAVDMasked256", argLength: 3, reg: w2kw, asm: "VPSRAVD", commutative: false, typ: "Vec256", resultInArg0: false},
+ {name: "VPSRAVDMasked512", argLength: 3, reg: w2kw, asm: "VPSRAVD", commutative: false, typ: "Vec512", resultInArg0: false},
+ {name: "VPSRAVQ128", argLength: 2, reg: w21, asm: "VPSRAVQ", commutative: false, typ: "Vec128", resultInArg0: false},
+ {name: "VPSRAVQ256", argLength: 2, reg: w21, asm: "VPSRAVQ", commutative: false, typ: "Vec256", resultInArg0: false},
{name: "VPSRAVQ512", argLength: 2, reg: w21, asm: "VPSRAVQ", commutative: false, typ: "Vec512", resultInArg0: false},
- {name: "VPSHRDVQ512", argLength: 3, reg: w31, asm: "VPSHRDVQ", commutative: false, typ: "Vec512", resultInArg0: true},
- {name: "VPSHRDVQMasked512", argLength: 4, reg: w3kw, asm: "VPSHRDVQ", commutative: false, typ: "Vec512", resultInArg0: true},
+ {name: "VPSRAVQMasked128", argLength: 3, reg: w2kw, asm: "VPSRAVQ", commutative: false, typ: "Vec128", resultInArg0: false},
+ {name: "VPSRAVQMasked256", argLength: 3, reg: w2kw, asm: "VPSRAVQ", commutative: false, typ: "Vec256", resultInArg0: false},
{name: "VPSRAVQMasked512", argLength: 3, reg: w2kw, asm: "VPSRAVQ", commutative: false, typ: "Vec512", resultInArg0: false},
- {name: "VPSUBQ512", argLength: 2, reg: w21, asm: "VPSUBQ", commutative: false, typ: "Vec512", resultInArg0: false},
- {name: "VPSUBQMasked512", argLength: 3, reg: w2kw, asm: "VPSUBQ", commutative: false, typ: "Vec512", resultInArg0: false},
- {name: "VPXORQ512", argLength: 2, reg: w21, asm: "VPXORQ", commutative: true, typ: "Vec512", resultInArg0: false},
- {name: "VPXORQMasked512", argLength: 3, reg: w2kw, asm: "VPXORQ", commutative: true, typ: "Vec512", resultInArg0: false},
- {name: "VPABSB128", argLength: 1, reg: v11, asm: "VPABSB", commutative: false, typ: "Vec128", resultInArg0: false},
- {name: "VPABSBMasked128", argLength: 2, reg: wkw, asm: "VPABSB", commutative: false, typ: "Vec128", resultInArg0: false},
- {name: "VPADDB128", argLength: 2, reg: v21, asm: "VPADDB", commutative: true, typ: "Vec128", resultInArg0: false},
- {name: "VPADDBMasked128", argLength: 3, reg: w2kw, asm: "VPADDB", commutative: true, typ: "Vec128", resultInArg0: false},
- {name: "VPAND128", argLength: 2, reg: v21, asm: "VPAND", commutative: true, typ: "Vec128", resultInArg0: false},
- {name: "VPANDN128", argLength: 2, reg: v21, asm: "VPANDN", commutative: false, typ: "Vec128", resultInArg0: false},
- {name: "VPCOMPRESSBMasked128", argLength: 2, reg: wkw, asm: "VPCOMPRESSB", commutative: false, typ: "Vec128", resultInArg0: false},
- {name: "VPCMPEQB128", argLength: 2, reg: v21, asm: "VPCMPEQB", commutative: true, typ: "Vec128", resultInArg0: false},
- {name: "VPCMPGTB128", argLength: 2, reg: v21, asm: "VPCMPGTB", commutative: false, typ: "Vec128", resultInArg0: false},
- {name: "VPMAXSB128", argLength: 2, reg: v21, asm: "VPMAXSB", commutative: true, typ: "Vec128", resultInArg0: false},
- {name: "VPMAXSBMasked128", argLength: 3, reg: w2kw, asm: "VPMAXSB", commutative: true, typ: "Vec128", resultInArg0: false},
- {name: "VPMINSB128", argLength: 2, reg: v21, asm: "VPMINSB", commutative: true, typ: "Vec128", resultInArg0: false},
- {name: "VPMINSBMasked128", argLength: 3, reg: w2kw, asm: "VPMINSB", commutative: true, typ: "Vec128", resultInArg0: false},
- {name: "VPOR128", argLength: 2, reg: v21, asm: "VPOR", commutative: true, typ: "Vec128", resultInArg0: false},
- {name: "VPOPCNTB128", argLength: 1, reg: w11, asm: "VPOPCNTB", commutative: false, typ: "Vec128", resultInArg0: false},
- {name: "VPOPCNTBMasked128", argLength: 2, reg: wkw, asm: "VPOPCNTB", commutative: false, typ: "Vec128", resultInArg0: false},
- {name: "VPADDSB128", argLength: 2, reg: v21, asm: "VPADDSB", commutative: true, typ: "Vec128", resultInArg0: false},
- {name: "VPADDSBMasked128", argLength: 3, reg: w2kw, asm: "VPADDSB", commutative: true, typ: "Vec128", resultInArg0: false},
- {name: "VPSUBSB128", argLength: 2, reg: v21, asm: "VPSUBSB", commutative: false, typ: "Vec128", resultInArg0: false},
- {name: "VPSUBSBMasked128", argLength: 3, reg: w2kw, asm: "VPSUBSB", commutative: false, typ: "Vec128", resultInArg0: false},
- {name: "VPSIGNB128", argLength: 2, reg: v21, asm: "VPSIGNB", commutative: false, typ: "Vec128", resultInArg0: false},
- {name: "VPSUBB128", argLength: 2, reg: v21, asm: "VPSUBB", commutative: false, typ: "Vec128", resultInArg0: false},
- {name: "VPSUBBMasked128", argLength: 3, reg: w2kw, asm: "VPSUBB", commutative: false, typ: "Vec128", resultInArg0: false},
- {name: "VPXOR128", argLength: 2, reg: v21, asm: "VPXOR", commutative: true, typ: "Vec128", resultInArg0: false},
- {name: "VPABSB256", argLength: 1, reg: v11, asm: "VPABSB", commutative: false, typ: "Vec256", resultInArg0: false},
- {name: "VPABSBMasked256", argLength: 2, reg: wkw, asm: "VPABSB", commutative: false, typ: "Vec256", resultInArg0: false},
- {name: "VPADDB256", argLength: 2, reg: v21, asm: "VPADDB", commutative: true, typ: "Vec256", resultInArg0: false},
- {name: "VPADDBMasked256", argLength: 3, reg: w2kw, asm: "VPADDB", commutative: true, typ: "Vec256", resultInArg0: false},
- {name: "VPAND256", argLength: 2, reg: v21, asm: "VPAND", commutative: true, typ: "Vec256", resultInArg0: false},
- {name: "VPANDN256", argLength: 2, reg: v21, asm: "VPANDN", commutative: false, typ: "Vec256", resultInArg0: false},
- {name: "VPCOMPRESSBMasked256", argLength: 2, reg: wkw, asm: "VPCOMPRESSB", commutative: false, typ: "Vec256", resultInArg0: false},
- {name: "VPCMPEQB256", argLength: 2, reg: v21, asm: "VPCMPEQB", commutative: true, typ: "Vec256", resultInArg0: false},
- {name: "VPCMPGTB256", argLength: 2, reg: v21, asm: "VPCMPGTB", commutative: false, typ: "Vec256", resultInArg0: false},
- {name: "VPMAXSB256", argLength: 2, reg: v21, asm: "VPMAXSB", commutative: true, typ: "Vec256", resultInArg0: false},
- {name: "VPMAXSBMasked256", argLength: 3, reg: w2kw, asm: "VPMAXSB", commutative: true, typ: "Vec256", resultInArg0: false},
- {name: "VPMINSB256", argLength: 2, reg: v21, asm: "VPMINSB", commutative: true, typ: "Vec256", resultInArg0: false},
- {name: "VPMINSBMasked256", argLength: 3, reg: w2kw, asm: "VPMINSB", commutative: true, typ: "Vec256", resultInArg0: false},
- {name: "VPOR256", argLength: 2, reg: v21, asm: "VPOR", commutative: true, typ: "Vec256", resultInArg0: false},
- {name: "VPOPCNTB256", argLength: 1, reg: w11, asm: "VPOPCNTB", commutative: false, typ: "Vec256", resultInArg0: false},
- {name: "VPOPCNTBMasked256", argLength: 2, reg: wkw, asm: "VPOPCNTB", commutative: false, typ: "Vec256", resultInArg0: false},
- {name: "VPADDSB256", argLength: 2, reg: v21, asm: "VPADDSB", commutative: true, typ: "Vec256", resultInArg0: false},
- {name: "VPADDSBMasked256", argLength: 3, reg: w2kw, asm: "VPADDSB", commutative: true, typ: "Vec256", resultInArg0: false},
- {name: "VPSUBSB256", argLength: 2, reg: v21, asm: "VPSUBSB", commutative: false, typ: "Vec256", resultInArg0: false},
- {name: "VPSUBSBMasked256", argLength: 3, reg: w2kw, asm: "VPSUBSB", commutative: false, typ: "Vec256", resultInArg0: false},
- {name: "VPSIGNB256", argLength: 2, reg: v21, asm: "VPSIGNB", commutative: false, typ: "Vec256", resultInArg0: false},
- {name: "VPSUBB256", argLength: 2, reg: v21, asm: "VPSUBB", commutative: false, typ: "Vec256", resultInArg0: false},
- {name: "VPSUBBMasked256", argLength: 3, reg: w2kw, asm: "VPSUBB", commutative: false, typ: "Vec256", resultInArg0: false},
- {name: "VPXOR256", argLength: 2, reg: v21, asm: "VPXOR", commutative: true, typ: "Vec256", resultInArg0: false},
- {name: "VPABSB512", argLength: 1, reg: w11, asm: "VPABSB", commutative: false, typ: "Vec512", resultInArg0: false},
- {name: "VPABSBMasked512", argLength: 2, reg: wkw, asm: "VPABSB", commutative: false, typ: "Vec512", resultInArg0: false},
- {name: "VPADDB512", argLength: 2, reg: w21, asm: "VPADDB", commutative: true, typ: "Vec512", resultInArg0: false},
- {name: "VPADDBMasked512", argLength: 3, reg: w2kw, asm: "VPADDB", commutative: true, typ: "Vec512", resultInArg0: false},
- {name: "VPCOMPRESSBMasked512", argLength: 2, reg: wkw, asm: "VPCOMPRESSB", commutative: false, typ: "Vec512", resultInArg0: false},
- {name: "VPCMPEQB512", argLength: 2, reg: w2k, asm: "VPCMPEQB", commutative: true, typ: "Mask", resultInArg0: false},
- {name: "VPCMPGTB512", argLength: 2, reg: w2k, asm: "VPCMPGTB", commutative: false, typ: "Mask", resultInArg0: false},
- {name: "VPMAXSB512", argLength: 2, reg: w21, asm: "VPMAXSB", commutative: true, typ: "Vec512", resultInArg0: false},
- {name: "VPMAXSBMasked512", argLength: 3, reg: w2kw, asm: "VPMAXSB", commutative: true, typ: "Vec512", resultInArg0: false},
- {name: "VPMINSB512", argLength: 2, reg: w21, asm: "VPMINSB", commutative: true, typ: "Vec512", resultInArg0: false},
- {name: "VPMINSBMasked512", argLength: 3, reg: w2kw, asm: "VPMINSB", commutative: true, typ: "Vec512", resultInArg0: false},
- {name: "VPOPCNTB512", argLength: 1, reg: w11, asm: "VPOPCNTB", commutative: false, typ: "Vec512", resultInArg0: false},
- {name: "VPOPCNTBMasked512", argLength: 2, reg: wkw, asm: "VPOPCNTB", commutative: false, typ: "Vec512", resultInArg0: false},
- {name: "VPADDSB512", argLength: 2, reg: w21, asm: "VPADDSB", commutative: true, typ: "Vec512", resultInArg0: false},
- {name: "VPADDSBMasked512", argLength: 3, reg: w2kw, asm: "VPADDSB", commutative: true, typ: "Vec512", resultInArg0: false},
- {name: "VPSUBSB512", argLength: 2, reg: w21, asm: "VPSUBSB", commutative: false, typ: "Vec512", resultInArg0: false},
- {name: "VPSUBSBMasked512", argLength: 3, reg: w2kw, asm: "VPSUBSB", commutative: false, typ: "Vec512", resultInArg0: false},
- {name: "VPSUBB512", argLength: 2, reg: w21, asm: "VPSUBB", commutative: false, typ: "Vec512", resultInArg0: false},
- {name: "VPSUBBMasked512", argLength: 3, reg: w2kw, asm: "VPSUBB", commutative: false, typ: "Vec512", resultInArg0: false},
- {name: "VPAVGW256", argLength: 2, reg: v21, asm: "VPAVGW", commutative: true, typ: "Vec256", resultInArg0: false},
- {name: "VPAVGWMasked256", argLength: 3, reg: w2kw, asm: "VPAVGW", commutative: true, typ: "Vec256", resultInArg0: false},
- {name: "VPMAXUW256", argLength: 2, reg: v21, asm: "VPMAXUW", commutative: true, typ: "Vec256", resultInArg0: false},
- {name: "VPMAXUWMasked256", argLength: 3, reg: w2kw, asm: "VPMAXUW", commutative: true, typ: "Vec256", resultInArg0: false},
- {name: "VPMINUW256", argLength: 2, reg: v21, asm: "VPMINUW", commutative: true, typ: "Vec256", resultInArg0: false},
- {name: "VPMINUWMasked256", argLength: 3, reg: w2kw, asm: "VPMINUW", commutative: true, typ: "Vec256", resultInArg0: false},
- {name: "VPMULHUW256", argLength: 2, reg: v21, asm: "VPMULHUW", commutative: true, typ: "Vec256", resultInArg0: false},
- {name: "VPMULHUWMasked256", argLength: 3, reg: w2kw, asm: "VPMULHUW", commutative: true, typ: "Vec256", resultInArg0: false},
- {name: "VPERMW256", argLength: 2, reg: w21, asm: "VPERMW", commutative: false, typ: "Vec256", resultInArg0: false},
- {name: "VPERMI2W256", argLength: 3, reg: w31, asm: "VPERMI2W", commutative: false, typ: "Vec256", resultInArg0: true},
- {name: "VPERMI2WMasked256", argLength: 4, reg: w3kw, asm: "VPERMI2W", commutative: false, typ: "Vec256", resultInArg0: true},
- {name: "VPERMWMasked256", argLength: 3, reg: w2kw, asm: "VPERMW", commutative: false, typ: "Vec256", resultInArg0: false},
- {name: "VPSRLW256", argLength: 2, reg: vfpv, asm: "VPSRLW", commutative: false, typ: "Vec256", resultInArg0: false},
- {name: "VPSRLWMasked256", argLength: 3, reg: wfpkw, asm: "VPSRLW", commutative: false, typ: "Vec256", resultInArg0: false},
- {name: "VPSRLVW256", argLength: 2, reg: w21, asm: "VPSRLVW", commutative: false, typ: "Vec256", resultInArg0: false},
- {name: "VPSRLVWMasked256", argLength: 3, reg: w2kw, asm: "VPSRLVW", commutative: false, typ: "Vec256", resultInArg0: false},
- {name: "VPAVGW512", argLength: 2, reg: w21, asm: "VPAVGW", commutative: true, typ: "Vec512", resultInArg0: false},
- {name: "VPAVGWMasked512", argLength: 3, reg: w2kw, asm: "VPAVGW", commutative: true, typ: "Vec512", resultInArg0: false},
- {name: "VPMAXUW512", argLength: 2, reg: w21, asm: "VPMAXUW", commutative: true, typ: "Vec512", resultInArg0: false},
- {name: "VPMAXUWMasked512", argLength: 3, reg: w2kw, asm: "VPMAXUW", commutative: true, typ: "Vec512", resultInArg0: false},
- {name: "VPMINUW512", argLength: 2, reg: w21, asm: "VPMINUW", commutative: true, typ: "Vec512", resultInArg0: false},
- {name: "VPMINUWMasked512", argLength: 3, reg: w2kw, asm: "VPMINUW", commutative: true, typ: "Vec512", resultInArg0: false},
- {name: "VPMULHUW512", argLength: 2, reg: w21, asm: "VPMULHUW", commutative: true, typ: "Vec512", resultInArg0: false},
- {name: "VPMULHUWMasked512", argLength: 3, reg: w2kw, asm: "VPMULHUW", commutative: true, typ: "Vec512", resultInArg0: false},
- {name: "VPERMW512", argLength: 2, reg: w21, asm: "VPERMW", commutative: false, typ: "Vec512", resultInArg0: false},
- {name: "VPERMI2W512", argLength: 3, reg: w31, asm: "VPERMI2W", commutative: false, typ: "Vec512", resultInArg0: true},
- {name: "VPERMI2WMasked512", argLength: 4, reg: w3kw, asm: "VPERMI2W", commutative: false, typ: "Vec512", resultInArg0: true},
- {name: "VPERMWMasked512", argLength: 3, reg: w2kw, asm: "VPERMW", commutative: false, typ: "Vec512", resultInArg0: false},
- {name: "VPSRLW512", argLength: 2, reg: wfpw, asm: "VPSRLW", commutative: false, typ: "Vec512", resultInArg0: false},
- {name: "VPSRLWMasked512", argLength: 3, reg: wfpkw, asm: "VPSRLW", commutative: false, typ: "Vec512", resultInArg0: false},
- {name: "VPSRLVW512", argLength: 2, reg: w21, asm: "VPSRLVW", commutative: false, typ: "Vec512", resultInArg0: false},
- {name: "VPSRLVWMasked512", argLength: 3, reg: w2kw, asm: "VPSRLVW", commutative: false, typ: "Vec512", resultInArg0: false},
- {name: "VPAVGW128", argLength: 2, reg: v21, asm: "VPAVGW", commutative: true, typ: "Vec128", resultInArg0: false},
- {name: "VPAVGWMasked128", argLength: 3, reg: w2kw, asm: "VPAVGW", commutative: true, typ: "Vec128", resultInArg0: false},
- {name: "VPMAXUW128", argLength: 2, reg: v21, asm: "VPMAXUW", commutative: true, typ: "Vec128", resultInArg0: false},
- {name: "VPMAXUWMasked128", argLength: 3, reg: w2kw, asm: "VPMAXUW", commutative: true, typ: "Vec128", resultInArg0: false},
- {name: "VPMINUW128", argLength: 2, reg: v21, asm: "VPMINUW", commutative: true, typ: "Vec128", resultInArg0: false},
- {name: "VPMINUWMasked128", argLength: 3, reg: w2kw, asm: "VPMINUW", commutative: true, typ: "Vec128", resultInArg0: false},
- {name: "VPMULHUW128", argLength: 2, reg: v21, asm: "VPMULHUW", commutative: true, typ: "Vec128", resultInArg0: false},
- {name: "VPMULHUWMasked128", argLength: 3, reg: w2kw, asm: "VPMULHUW", commutative: true, typ: "Vec128", resultInArg0: false},
- {name: "VPERMW128", argLength: 2, reg: w21, asm: "VPERMW", commutative: false, typ: "Vec128", resultInArg0: false},
- {name: "VPERMI2W128", argLength: 3, reg: w31, asm: "VPERMI2W", commutative: false, typ: "Vec128", resultInArg0: true},
- {name: "VPERMI2WMasked128", argLength: 4, reg: w3kw, asm: "VPERMI2W", commutative: false, typ: "Vec128", resultInArg0: true},
- {name: "VPERMWMasked128", argLength: 3, reg: w2kw, asm: "VPERMW", commutative: false, typ: "Vec128", resultInArg0: false},
- {name: "VPSRLW128", argLength: 2, reg: vfpv, asm: "VPSRLW", commutative: false, typ: "Vec128", resultInArg0: false},
- {name: "VPSRLWMasked128", argLength: 3, reg: wfpkw, asm: "VPSRLW", commutative: false, typ: "Vec128", resultInArg0: false},
- {name: "VPSRLVW128", argLength: 2, reg: w21, asm: "VPSRLVW", commutative: false, typ: "Vec128", resultInArg0: false},
- {name: "VPSRLVWMasked128", argLength: 3, reg: w2kw, asm: "VPSRLVW", commutative: false, typ: "Vec128", resultInArg0: false},
- {name: "VPMAXUD512", argLength: 2, reg: w21, asm: "VPMAXUD", commutative: true, typ: "Vec512", resultInArg0: false},
- {name: "VPMAXUDMasked512", argLength: 3, reg: w2kw, asm: "VPMAXUD", commutative: true, typ: "Vec512", resultInArg0: false},
- {name: "VPMINUD512", argLength: 2, reg: w21, asm: "VPMINUD", commutative: true, typ: "Vec512", resultInArg0: false},
- {name: "VPMINUDMasked512", argLength: 3, reg: w2kw, asm: "VPMINUD", commutative: true, typ: "Vec512", resultInArg0: false},
- {name: "VPERMD512", argLength: 2, reg: w21, asm: "VPERMD", commutative: false, typ: "Vec512", resultInArg0: false},
- {name: "VPERMPS512", argLength: 2, reg: w21, asm: "VPERMPS", commutative: false, typ: "Vec512", resultInArg0: false},
- {name: "VPERMI2PS512", argLength: 3, reg: w31, asm: "VPERMI2PS", commutative: false, typ: "Vec512", resultInArg0: true},
- {name: "VPERMI2D512", argLength: 3, reg: w31, asm: "VPERMI2D", commutative: false, typ: "Vec512", resultInArg0: true},
- {name: "VPERMI2PSMasked512", argLength: 4, reg: w3kw, asm: "VPERMI2PS", commutative: false, typ: "Vec512", resultInArg0: true},
- {name: "VPERMI2DMasked512", argLength: 4, reg: w3kw, asm: "VPERMI2D", commutative: false, typ: "Vec512", resultInArg0: true},
- {name: "VPERMPSMasked512", argLength: 3, reg: w2kw, asm: "VPERMPS", commutative: false, typ: "Vec512", resultInArg0: false},
- {name: "VPERMDMasked512", argLength: 3, reg: w2kw, asm: "VPERMD", commutative: false, typ: "Vec512", resultInArg0: false},
- {name: "VPSRLD512", argLength: 2, reg: wfpw, asm: "VPSRLD", commutative: false, typ: "Vec512", resultInArg0: false},
- {name: "VPSRLDMasked512", argLength: 3, reg: wfpkw, asm: "VPSRLD", commutative: false, typ: "Vec512", resultInArg0: false},
- {name: "VPSRLVD512", argLength: 2, reg: w21, asm: "VPSRLVD", commutative: false, typ: "Vec512", resultInArg0: false},
- {name: "VPSRLVDMasked512", argLength: 3, reg: w2kw, asm: "VPSRLVD", commutative: false, typ: "Vec512", resultInArg0: false},
- {name: "VPMAXUD128", argLength: 2, reg: v21, asm: "VPMAXUD", commutative: true, typ: "Vec128", resultInArg0: false},
- {name: "VPMAXUDMasked128", argLength: 3, reg: w2kw, asm: "VPMAXUD", commutative: true, typ: "Vec128", resultInArg0: false},
- {name: "VPMINUD128", argLength: 2, reg: v21, asm: "VPMINUD", commutative: true, typ: "Vec128", resultInArg0: false},
- {name: "VPMINUDMasked128", argLength: 3, reg: w2kw, asm: "VPMINUD", commutative: true, typ: "Vec128", resultInArg0: false},
- {name: "VPMULUDQ128", argLength: 2, reg: v21, asm: "VPMULUDQ", commutative: true, typ: "Vec128", resultInArg0: false},
- {name: "VPERMI2PS128", argLength: 3, reg: w31, asm: "VPERMI2PS", commutative: false, typ: "Vec128", resultInArg0: true},
- {name: "VPERMI2D128", argLength: 3, reg: w31, asm: "VPERMI2D", commutative: false, typ: "Vec128", resultInArg0: true},
- {name: "VPERMI2DMasked128", argLength: 4, reg: w3kw, asm: "VPERMI2D", commutative: false, typ: "Vec128", resultInArg0: true},
- {name: "VPERMI2PSMasked128", argLength: 4, reg: w3kw, asm: "VPERMI2PS", commutative: false, typ: "Vec128", resultInArg0: true},
- {name: "VPSRLD128", argLength: 2, reg: vfpv, asm: "VPSRLD", commutative: false, typ: "Vec128", resultInArg0: false},
- {name: "VPSRLDMasked128", argLength: 3, reg: wfpkw, asm: "VPSRLD", commutative: false, typ: "Vec128", resultInArg0: false},
- {name: "VPSRLVD128", argLength: 2, reg: v21, asm: "VPSRLVD", commutative: false, typ: "Vec128", resultInArg0: false},
- {name: "VPSRLVDMasked128", argLength: 3, reg: w2kw, asm: "VPSRLVD", commutative: false, typ: "Vec128", resultInArg0: false},
- {name: "VPMAXUD256", argLength: 2, reg: v21, asm: "VPMAXUD", commutative: true, typ: "Vec256", resultInArg0: false},
- {name: "VPMAXUDMasked256", argLength: 3, reg: w2kw, asm: "VPMAXUD", commutative: true, typ: "Vec256", resultInArg0: false},
- {name: "VPMINUD256", argLength: 2, reg: v21, asm: "VPMINUD", commutative: true, typ: "Vec256", resultInArg0: false},
- {name: "VPMINUDMasked256", argLength: 3, reg: w2kw, asm: "VPMINUD", commutative: true, typ: "Vec256", resultInArg0: false},
- {name: "VPMULUDQ256", argLength: 2, reg: v21, asm: "VPMULUDQ", commutative: true, typ: "Vec256", resultInArg0: false},
- {name: "VPERMD256", argLength: 2, reg: v21, asm: "VPERMD", commutative: false, typ: "Vec256", resultInArg0: false},
- {name: "VPERMPS256", argLength: 2, reg: v21, asm: "VPERMPS", commutative: false, typ: "Vec256", resultInArg0: false},
- {name: "VPERMI2PS256", argLength: 3, reg: w31, asm: "VPERMI2PS", commutative: false, typ: "Vec256", resultInArg0: true},
- {name: "VPERMI2D256", argLength: 3, reg: w31, asm: "VPERMI2D", commutative: false, typ: "Vec256", resultInArg0: true},
- {name: "VPERMI2PSMasked256", argLength: 4, reg: w3kw, asm: "VPERMI2PS", commutative: false, typ: "Vec256", resultInArg0: true},
- {name: "VPERMI2DMasked256", argLength: 4, reg: w3kw, asm: "VPERMI2D", commutative: false, typ: "Vec256", resultInArg0: true},
- {name: "VPERMPSMasked256", argLength: 3, reg: w2kw, asm: "VPERMPS", commutative: false, typ: "Vec256", resultInArg0: false},
- {name: "VPERMDMasked256", argLength: 3, reg: w2kw, asm: "VPERMD", commutative: false, typ: "Vec256", resultInArg0: false},
+ {name: "VPSRAVW128", argLength: 2, reg: w21, asm: "VPSRAVW", commutative: false, typ: "Vec128", resultInArg0: false},
+ {name: "VPSRAVW256", argLength: 2, reg: w21, asm: "VPSRAVW", commutative: false, typ: "Vec256", resultInArg0: false},
+ {name: "VPSRAVW512", argLength: 2, reg: w21, asm: "VPSRAVW", commutative: false, typ: "Vec512", resultInArg0: false},
+ {name: "VPSRAVWMasked128", argLength: 3, reg: w2kw, asm: "VPSRAVW", commutative: false, typ: "Vec128", resultInArg0: false},
+ {name: "VPSRAVWMasked256", argLength: 3, reg: w2kw, asm: "VPSRAVW", commutative: false, typ: "Vec256", resultInArg0: false},
+ {name: "VPSRAVWMasked512", argLength: 3, reg: w2kw, asm: "VPSRAVW", commutative: false, typ: "Vec512", resultInArg0: false},
+ {name: "VPSRAW128", argLength: 2, reg: vfpv, asm: "VPSRAW", commutative: false, typ: "Vec128", resultInArg0: false},
+ {name: "VPSRAW256", argLength: 2, reg: vfpv, asm: "VPSRAW", commutative: false, typ: "Vec256", resultInArg0: false},
+ {name: "VPSRAW512", argLength: 2, reg: wfpw, asm: "VPSRAW", commutative: false, typ: "Vec512", resultInArg0: false},
+ {name: "VPSRAWMasked128", argLength: 3, reg: wfpkw, asm: "VPSRAW", commutative: false, typ: "Vec128", resultInArg0: false},
+ {name: "VPSRAWMasked256", argLength: 3, reg: wfpkw, asm: "VPSRAW", commutative: false, typ: "Vec256", resultInArg0: false},
+ {name: "VPSRAWMasked512", argLength: 3, reg: wfpkw, asm: "VPSRAW", commutative: false, typ: "Vec512", resultInArg0: false},
+ {name: "VPSRLD128", argLength: 2, reg: vfpv, asm: "VPSRLD", commutative: false, typ: "Vec128", resultInArg0: false},
{name: "VPSRLD256", argLength: 2, reg: vfpv, asm: "VPSRLD", commutative: false, typ: "Vec256", resultInArg0: false},
+ {name: "VPSRLD512", argLength: 2, reg: wfpw, asm: "VPSRLD", commutative: false, typ: "Vec512", resultInArg0: false},
+ {name: "VPSRLDMasked128", argLength: 3, reg: wfpkw, asm: "VPSRLD", commutative: false, typ: "Vec128", resultInArg0: false},
{name: "VPSRLDMasked256", argLength: 3, reg: wfpkw, asm: "VPSRLD", commutative: false, typ: "Vec256", resultInArg0: false},
- {name: "VPSRLVD256", argLength: 2, reg: v21, asm: "VPSRLVD", commutative: false, typ: "Vec256", resultInArg0: false},
- {name: "VPSRLVDMasked256", argLength: 3, reg: w2kw, asm: "VPSRLVD", commutative: false, typ: "Vec256", resultInArg0: false},
- {name: "VPMAXUQ128", argLength: 2, reg: w21, asm: "VPMAXUQ", commutative: true, typ: "Vec128", resultInArg0: false},
- {name: "VPMAXUQMasked128", argLength: 3, reg: w2kw, asm: "VPMAXUQ", commutative: true, typ: "Vec128", resultInArg0: false},
- {name: "VPMINUQ128", argLength: 2, reg: w21, asm: "VPMINUQ", commutative: true, typ: "Vec128", resultInArg0: false},
- {name: "VPMINUQMasked128", argLength: 3, reg: w2kw, asm: "VPMINUQ", commutative: true, typ: "Vec128", resultInArg0: false},
- {name: "VPMULUDQMasked128", argLength: 3, reg: w2kw, asm: "VPMULUDQ", commutative: true, typ: "Vec128", resultInArg0: false},
- {name: "VPERMI2PD128", argLength: 3, reg: w31, asm: "VPERMI2PD", commutative: false, typ: "Vec128", resultInArg0: true},
- {name: "VPERMI2Q128", argLength: 3, reg: w31, asm: "VPERMI2Q", commutative: false, typ: "Vec128", resultInArg0: true},
- {name: "VPERMI2PDMasked128", argLength: 4, reg: w3kw, asm: "VPERMI2PD", commutative: false, typ: "Vec128", resultInArg0: true},
- {name: "VPERMI2QMasked128", argLength: 4, reg: w3kw, asm: "VPERMI2Q", commutative: false, typ: "Vec128", resultInArg0: true},
+ {name: "VPSRLDMasked512", argLength: 3, reg: wfpkw, asm: "VPSRLD", commutative: false, typ: "Vec512", resultInArg0: false},
{name: "VPSRLQ128", argLength: 2, reg: vfpv, asm: "VPSRLQ", commutative: false, typ: "Vec128", resultInArg0: false},
- {name: "VPSRLQMasked128", argLength: 3, reg: wfpkw, asm: "VPSRLQ", commutative: false, typ: "Vec128", resultInArg0: false},
- {name: "VPSRLVQ128", argLength: 2, reg: v21, asm: "VPSRLVQ", commutative: false, typ: "Vec128", resultInArg0: false},
- {name: "VPSRLVQMasked128", argLength: 3, reg: w2kw, asm: "VPSRLVQ", commutative: false, typ: "Vec128", resultInArg0: false},
- {name: "VPMAXUQ256", argLength: 2, reg: w21, asm: "VPMAXUQ", commutative: true, typ: "Vec256", resultInArg0: false},
- {name: "VPMAXUQMasked256", argLength: 3, reg: w2kw, asm: "VPMAXUQ", commutative: true, typ: "Vec256", resultInArg0: false},
- {name: "VPMINUQ256", argLength: 2, reg: w21, asm: "VPMINUQ", commutative: true, typ: "Vec256", resultInArg0: false},
- {name: "VPMINUQMasked256", argLength: 3, reg: w2kw, asm: "VPMINUQ", commutative: true, typ: "Vec256", resultInArg0: false},
- {name: "VPMULUDQMasked256", argLength: 3, reg: w2kw, asm: "VPMULUDQ", commutative: true, typ: "Vec256", resultInArg0: false},
- {name: "VPERMPD256", argLength: 2, reg: w21, asm: "VPERMPD", commutative: false, typ: "Vec256", resultInArg0: false},
- {name: "VPERMQ256", argLength: 2, reg: w21, asm: "VPERMQ", commutative: false, typ: "Vec256", resultInArg0: false},
- {name: "VPERMI2PD256", argLength: 3, reg: w31, asm: "VPERMI2PD", commutative: false, typ: "Vec256", resultInArg0: true},
- {name: "VPERMI2Q256", argLength: 3, reg: w31, asm: "VPERMI2Q", commutative: false, typ: "Vec256", resultInArg0: true},
- {name: "VPERMI2PDMasked256", argLength: 4, reg: w3kw, asm: "VPERMI2PD", commutative: false, typ: "Vec256", resultInArg0: true},
- {name: "VPERMI2QMasked256", argLength: 4, reg: w3kw, asm: "VPERMI2Q", commutative: false, typ: "Vec256", resultInArg0: true},
- {name: "VPERMQMasked256", argLength: 3, reg: w2kw, asm: "VPERMQ", commutative: false, typ: "Vec256", resultInArg0: false},
- {name: "VPERMPDMasked256", argLength: 3, reg: w2kw, asm: "VPERMPD", commutative: false, typ: "Vec256", resultInArg0: false},
{name: "VPSRLQ256", argLength: 2, reg: vfpv, asm: "VPSRLQ", commutative: false, typ: "Vec256", resultInArg0: false},
- {name: "VPSRLQMasked256", argLength: 3, reg: wfpkw, asm: "VPSRLQ", commutative: false, typ: "Vec256", resultInArg0: false},
- {name: "VPSRLVQ256", argLength: 2, reg: v21, asm: "VPSRLVQ", commutative: false, typ: "Vec256", resultInArg0: false},
- {name: "VPSRLVQMasked256", argLength: 3, reg: w2kw, asm: "VPSRLVQ", commutative: false, typ: "Vec256", resultInArg0: false},
- {name: "VPMAXUQ512", argLength: 2, reg: w21, asm: "VPMAXUQ", commutative: true, typ: "Vec512", resultInArg0: false},
- {name: "VPMAXUQMasked512", argLength: 3, reg: w2kw, asm: "VPMAXUQ", commutative: true, typ: "Vec512", resultInArg0: false},
- {name: "VPMINUQ512", argLength: 2, reg: w21, asm: "VPMINUQ", commutative: true, typ: "Vec512", resultInArg0: false},
- {name: "VPMINUQMasked512", argLength: 3, reg: w2kw, asm: "VPMINUQ", commutative: true, typ: "Vec512", resultInArg0: false},
- {name: "VPMULUDQ512", argLength: 2, reg: w21, asm: "VPMULUDQ", commutative: true, typ: "Vec512", resultInArg0: false},
- {name: "VPMULUDQMasked512", argLength: 3, reg: w2kw, asm: "VPMULUDQ", commutative: true, typ: "Vec512", resultInArg0: false},
- {name: "VPERMPD512", argLength: 2, reg: w21, asm: "VPERMPD", commutative: false, typ: "Vec512", resultInArg0: false},
- {name: "VPERMQ512", argLength: 2, reg: w21, asm: "VPERMQ", commutative: false, typ: "Vec512", resultInArg0: false},
- {name: "VPERMI2Q512", argLength: 3, reg: w31, asm: "VPERMI2Q", commutative: false, typ: "Vec512", resultInArg0: true},
- {name: "VPERMI2PD512", argLength: 3, reg: w31, asm: "VPERMI2PD", commutative: false, typ: "Vec512", resultInArg0: true},
- {name: "VPERMI2QMasked512", argLength: 4, reg: w3kw, asm: "VPERMI2Q", commutative: false, typ: "Vec512", resultInArg0: true},
- {name: "VPERMI2PDMasked512", argLength: 4, reg: w3kw, asm: "VPERMI2PD", commutative: false, typ: "Vec512", resultInArg0: true},
- {name: "VPERMPDMasked512", argLength: 3, reg: w2kw, asm: "VPERMPD", commutative: false, typ: "Vec512", resultInArg0: false},
- {name: "VPERMQMasked512", argLength: 3, reg: w2kw, asm: "VPERMQ", commutative: false, typ: "Vec512", resultInArg0: false},
{name: "VPSRLQ512", argLength: 2, reg: wfpw, asm: "VPSRLQ", commutative: false, typ: "Vec512", resultInArg0: false},
+ {name: "VPSRLQMasked128", argLength: 3, reg: wfpkw, asm: "VPSRLQ", commutative: false, typ: "Vec128", resultInArg0: false},
+ {name: "VPSRLQMasked256", argLength: 3, reg: wfpkw, asm: "VPSRLQ", commutative: false, typ: "Vec256", resultInArg0: false},
{name: "VPSRLQMasked512", argLength: 3, reg: wfpkw, asm: "VPSRLQ", commutative: false, typ: "Vec512", resultInArg0: false},
+ {name: "VPSRLVD128", argLength: 2, reg: v21, asm: "VPSRLVD", commutative: false, typ: "Vec128", resultInArg0: false},
+ {name: "VPSRLVD256", argLength: 2, reg: v21, asm: "VPSRLVD", commutative: false, typ: "Vec256", resultInArg0: false},
+ {name: "VPSRLVD512", argLength: 2, reg: w21, asm: "VPSRLVD", commutative: false, typ: "Vec512", resultInArg0: false},
+ {name: "VPSRLVDMasked128", argLength: 3, reg: w2kw, asm: "VPSRLVD", commutative: false, typ: "Vec128", resultInArg0: false},
+ {name: "VPSRLVDMasked256", argLength: 3, reg: w2kw, asm: "VPSRLVD", commutative: false, typ: "Vec256", resultInArg0: false},
+ {name: "VPSRLVDMasked512", argLength: 3, reg: w2kw, asm: "VPSRLVD", commutative: false, typ: "Vec512", resultInArg0: false},
+ {name: "VPSRLVQ128", argLength: 2, reg: v21, asm: "VPSRLVQ", commutative: false, typ: "Vec128", resultInArg0: false},
+ {name: "VPSRLVQ256", argLength: 2, reg: v21, asm: "VPSRLVQ", commutative: false, typ: "Vec256", resultInArg0: false},
{name: "VPSRLVQ512", argLength: 2, reg: w21, asm: "VPSRLVQ", commutative: false, typ: "Vec512", resultInArg0: false},
+ {name: "VPSRLVQMasked128", argLength: 3, reg: w2kw, asm: "VPSRLVQ", commutative: false, typ: "Vec128", resultInArg0: false},
+ {name: "VPSRLVQMasked256", argLength: 3, reg: w2kw, asm: "VPSRLVQ", commutative: false, typ: "Vec256", resultInArg0: false},
{name: "VPSRLVQMasked512", argLength: 3, reg: w2kw, asm: "VPSRLVQ", commutative: false, typ: "Vec512", resultInArg0: false},
- {name: "VPAVGB128", argLength: 2, reg: v21, asm: "VPAVGB", commutative: true, typ: "Vec128", resultInArg0: false},
- {name: "VPAVGBMasked128", argLength: 3, reg: w2kw, asm: "VPAVGB", commutative: true, typ: "Vec128", resultInArg0: false},
- {name: "VGF2P8MULB128", argLength: 2, reg: w21, asm: "VGF2P8MULB", commutative: false, typ: "Vec128", resultInArg0: false},
- {name: "VGF2P8MULBMasked128", argLength: 3, reg: w2kw, asm: "VGF2P8MULB", commutative: false, typ: "Vec128", resultInArg0: false},
- {name: "VPMAXUB128", argLength: 2, reg: v21, asm: "VPMAXUB", commutative: true, typ: "Vec128", resultInArg0: false},
- {name: "VPMAXUBMasked128", argLength: 3, reg: w2kw, asm: "VPMAXUB", commutative: true, typ: "Vec128", resultInArg0: false},
- {name: "VPMINUB128", argLength: 2, reg: v21, asm: "VPMINUB", commutative: true, typ: "Vec128", resultInArg0: false},
- {name: "VPMINUBMasked128", argLength: 3, reg: w2kw, asm: "VPMINUB", commutative: true, typ: "Vec128", resultInArg0: false},
- {name: "VPERMB128", argLength: 2, reg: w21, asm: "VPERMB", commutative: false, typ: "Vec128", resultInArg0: false},
- {name: "VPERMI2B128", argLength: 3, reg: w31, asm: "VPERMI2B", commutative: false, typ: "Vec128", resultInArg0: true},
- {name: "VPERMI2BMasked128", argLength: 4, reg: w3kw, asm: "VPERMI2B", commutative: false, typ: "Vec128", resultInArg0: true},
- {name: "VPERMBMasked128", argLength: 3, reg: w2kw, asm: "VPERMB", commutative: false, typ: "Vec128", resultInArg0: false},
- {name: "VPMADDUBSW128", argLength: 2, reg: v21, asm: "VPMADDUBSW", commutative: false, typ: "Vec128", resultInArg0: false},
- {name: "VPMADDUBSWMasked128", argLength: 3, reg: w2kw, asm: "VPMADDUBSW", commutative: false, typ: "Vec128", resultInArg0: false},
- {name: "VPAVGB256", argLength: 2, reg: v21, asm: "VPAVGB", commutative: true, typ: "Vec256", resultInArg0: false},
- {name: "VPAVGBMasked256", argLength: 3, reg: w2kw, asm: "VPAVGB", commutative: true, typ: "Vec256", resultInArg0: false},
- {name: "VGF2P8MULB256", argLength: 2, reg: w21, asm: "VGF2P8MULB", commutative: false, typ: "Vec256", resultInArg0: false},
- {name: "VGF2P8MULBMasked256", argLength: 3, reg: w2kw, asm: "VGF2P8MULB", commutative: false, typ: "Vec256", resultInArg0: false},
- {name: "VPMAXUB256", argLength: 2, reg: v21, asm: "VPMAXUB", commutative: true, typ: "Vec256", resultInArg0: false},
- {name: "VPMAXUBMasked256", argLength: 3, reg: w2kw, asm: "VPMAXUB", commutative: true, typ: "Vec256", resultInArg0: false},
- {name: "VPMINUB256", argLength: 2, reg: v21, asm: "VPMINUB", commutative: true, typ: "Vec256", resultInArg0: false},
- {name: "VPMINUBMasked256", argLength: 3, reg: w2kw, asm: "VPMINUB", commutative: true, typ: "Vec256", resultInArg0: false},
- {name: "VPERMB256", argLength: 2, reg: w21, asm: "VPERMB", commutative: false, typ: "Vec256", resultInArg0: false},
- {name: "VPERMI2B256", argLength: 3, reg: w31, asm: "VPERMI2B", commutative: false, typ: "Vec256", resultInArg0: true},
- {name: "VPERMI2BMasked256", argLength: 4, reg: w3kw, asm: "VPERMI2B", commutative: false, typ: "Vec256", resultInArg0: true},
- {name: "VPERMBMasked256", argLength: 3, reg: w2kw, asm: "VPERMB", commutative: false, typ: "Vec256", resultInArg0: false},
- {name: "VPMADDUBSW256", argLength: 2, reg: v21, asm: "VPMADDUBSW", commutative: false, typ: "Vec256", resultInArg0: false},
- {name: "VPMADDUBSWMasked256", argLength: 3, reg: w2kw, asm: "VPMADDUBSW", commutative: false, typ: "Vec256", resultInArg0: false},
- {name: "VPAVGB512", argLength: 2, reg: w21, asm: "VPAVGB", commutative: true, typ: "Vec512", resultInArg0: false},
- {name: "VPAVGBMasked512", argLength: 3, reg: w2kw, asm: "VPAVGB", commutative: true, typ: "Vec512", resultInArg0: false},
- {name: "VGF2P8MULB512", argLength: 2, reg: w21, asm: "VGF2P8MULB", commutative: false, typ: "Vec512", resultInArg0: false},
- {name: "VGF2P8MULBMasked512", argLength: 3, reg: w2kw, asm: "VGF2P8MULB", commutative: false, typ: "Vec512", resultInArg0: false},
- {name: "VPMAXUB512", argLength: 2, reg: w21, asm: "VPMAXUB", commutative: true, typ: "Vec512", resultInArg0: false},
- {name: "VPMAXUBMasked512", argLength: 3, reg: w2kw, asm: "VPMAXUB", commutative: true, typ: "Vec512", resultInArg0: false},
- {name: "VPMINUB512", argLength: 2, reg: w21, asm: "VPMINUB", commutative: true, typ: "Vec512", resultInArg0: false},
- {name: "VPMINUBMasked512", argLength: 3, reg: w2kw, asm: "VPMINUB", commutative: true, typ: "Vec512", resultInArg0: false},
- {name: "VPERMB512", argLength: 2, reg: w21, asm: "VPERMB", commutative: false, typ: "Vec512", resultInArg0: false},
- {name: "VPERMI2B512", argLength: 3, reg: w31, asm: "VPERMI2B", commutative: false, typ: "Vec512", resultInArg0: true},
- {name: "VPERMI2BMasked512", argLength: 4, reg: w3kw, asm: "VPERMI2B", commutative: false, typ: "Vec512", resultInArg0: true},
- {name: "VPERMBMasked512", argLength: 3, reg: w2kw, asm: "VPERMB", commutative: false, typ: "Vec512", resultInArg0: false},
- {name: "VPMADDUBSW512", argLength: 2, reg: w21, asm: "VPMADDUBSW", commutative: false, typ: "Vec512", resultInArg0: false},
- {name: "VPMADDUBSWMasked512", argLength: 3, reg: w2kw, asm: "VPMADDUBSW", commutative: false, typ: "Vec512", resultInArg0: false},
- {name: "VRNDSCALEPS512", argLength: 1, reg: w11, asm: "VRNDSCALEPS", aux: "Int8", commutative: false, typ: "Vec512", resultInArg0: false},
- {name: "VRNDSCALEPSMasked512", argLength: 2, reg: wkw, asm: "VRNDSCALEPS", aux: "Int8", commutative: false, typ: "Vec512", resultInArg0: false},
- {name: "VREDUCEPS512", argLength: 1, reg: w11, asm: "VREDUCEPS", aux: "Int8", commutative: false, typ: "Vec512", resultInArg0: false},
- {name: "VREDUCEPSMasked512", argLength: 2, reg: wkw, asm: "VREDUCEPS", aux: "Int8", commutative: false, typ: "Vec512", resultInArg0: false},
- {name: "VCMPPS512", argLength: 2, reg: w2k, asm: "VCMPPS", aux: "Int8", commutative: true, typ: "Mask", resultInArg0: false},
- {name: "VCMPPSMasked512", argLength: 3, reg: w2kk, asm: "VCMPPS", aux: "Int8", commutative: true, typ: "Mask", resultInArg0: false},
+ {name: "VPSRLVW128", argLength: 2, reg: w21, asm: "VPSRLVW", commutative: false, typ: "Vec128", resultInArg0: false},
+ {name: "VPSRLVW256", argLength: 2, reg: w21, asm: "VPSRLVW", commutative: false, typ: "Vec256", resultInArg0: false},
+ {name: "VPSRLVW512", argLength: 2, reg: w21, asm: "VPSRLVW", commutative: false, typ: "Vec512", resultInArg0: false},
+ {name: "VPSRLVWMasked128", argLength: 3, reg: w2kw, asm: "VPSRLVW", commutative: false, typ: "Vec128", resultInArg0: false},
+ {name: "VPSRLVWMasked256", argLength: 3, reg: w2kw, asm: "VPSRLVW", commutative: false, typ: "Vec256", resultInArg0: false},
+ {name: "VPSRLVWMasked512", argLength: 3, reg: w2kw, asm: "VPSRLVW", commutative: false, typ: "Vec512", resultInArg0: false},
+ {name: "VPSRLW128", argLength: 2, reg: vfpv, asm: "VPSRLW", commutative: false, typ: "Vec128", resultInArg0: false},
+ {name: "VPSRLW256", argLength: 2, reg: vfpv, asm: "VPSRLW", commutative: false, typ: "Vec256", resultInArg0: false},
+ {name: "VPSRLW512", argLength: 2, reg: wfpw, asm: "VPSRLW", commutative: false, typ: "Vec512", resultInArg0: false},
+ {name: "VPSRLWMasked128", argLength: 3, reg: wfpkw, asm: "VPSRLW", commutative: false, typ: "Vec128", resultInArg0: false},
+ {name: "VPSRLWMasked256", argLength: 3, reg: wfpkw, asm: "VPSRLW", commutative: false, typ: "Vec256", resultInArg0: false},
+ {name: "VPSRLWMasked512", argLength: 3, reg: wfpkw, asm: "VPSRLW", commutative: false, typ: "Vec512", resultInArg0: false},
+ {name: "VPSUBB128", argLength: 2, reg: v21, asm: "VPSUBB", commutative: false, typ: "Vec128", resultInArg0: false},
+ {name: "VPSUBB256", argLength: 2, reg: v21, asm: "VPSUBB", commutative: false, typ: "Vec256", resultInArg0: false},
+ {name: "VPSUBB512", argLength: 2, reg: w21, asm: "VPSUBB", commutative: false, typ: "Vec512", resultInArg0: false},
+ {name: "VPSUBBMasked128", argLength: 3, reg: w2kw, asm: "VPSUBB", commutative: false, typ: "Vec128", resultInArg0: false},
+ {name: "VPSUBBMasked256", argLength: 3, reg: w2kw, asm: "VPSUBB", commutative: false, typ: "Vec256", resultInArg0: false},
+ {name: "VPSUBBMasked512", argLength: 3, reg: w2kw, asm: "VPSUBB", commutative: false, typ: "Vec512", resultInArg0: false},
+ {name: "VPSUBD128", argLength: 2, reg: v21, asm: "VPSUBD", commutative: false, typ: "Vec128", resultInArg0: false},
+ {name: "VPSUBD256", argLength: 2, reg: v21, asm: "VPSUBD", commutative: false, typ: "Vec256", resultInArg0: false},
+ {name: "VPSUBD512", argLength: 2, reg: w21, asm: "VPSUBD", commutative: false, typ: "Vec512", resultInArg0: false},
+ {name: "VPSUBDMasked128", argLength: 3, reg: w2kw, asm: "VPSUBD", commutative: false, typ: "Vec128", resultInArg0: false},
+ {name: "VPSUBDMasked256", argLength: 3, reg: w2kw, asm: "VPSUBD", commutative: false, typ: "Vec256", resultInArg0: false},
+ {name: "VPSUBDMasked512", argLength: 3, reg: w2kw, asm: "VPSUBD", commutative: false, typ: "Vec512", resultInArg0: false},
+ {name: "VPSUBQ128", argLength: 2, reg: v21, asm: "VPSUBQ", commutative: false, typ: "Vec128", resultInArg0: false},
+ {name: "VPSUBQ256", argLength: 2, reg: v21, asm: "VPSUBQ", commutative: false, typ: "Vec256", resultInArg0: false},
+ {name: "VPSUBQ512", argLength: 2, reg: w21, asm: "VPSUBQ", commutative: false, typ: "Vec512", resultInArg0: false},
+ {name: "VPSUBQMasked128", argLength: 3, reg: w2kw, asm: "VPSUBQ", commutative: false, typ: "Vec128", resultInArg0: false},
+ {name: "VPSUBQMasked256", argLength: 3, reg: w2kw, asm: "VPSUBQ", commutative: false, typ: "Vec256", resultInArg0: false},
+ {name: "VPSUBQMasked512", argLength: 3, reg: w2kw, asm: "VPSUBQ", commutative: false, typ: "Vec512", resultInArg0: false},
+ {name: "VPSUBSB128", argLength: 2, reg: v21, asm: "VPSUBSB", commutative: false, typ: "Vec128", resultInArg0: false},
+ {name: "VPSUBSB256", argLength: 2, reg: v21, asm: "VPSUBSB", commutative: false, typ: "Vec256", resultInArg0: false},
+ {name: "VPSUBSB512", argLength: 2, reg: w21, asm: "VPSUBSB", commutative: false, typ: "Vec512", resultInArg0: false},
+ {name: "VPSUBSBMasked128", argLength: 3, reg: w2kw, asm: "VPSUBSB", commutative: false, typ: "Vec128", resultInArg0: false},
+ {name: "VPSUBSBMasked256", argLength: 3, reg: w2kw, asm: "VPSUBSB", commutative: false, typ: "Vec256", resultInArg0: false},
+ {name: "VPSUBSBMasked512", argLength: 3, reg: w2kw, asm: "VPSUBSB", commutative: false, typ: "Vec512", resultInArg0: false},
+ {name: "VPSUBSW128", argLength: 2, reg: v21, asm: "VPSUBSW", commutative: false, typ: "Vec128", resultInArg0: false},
+ {name: "VPSUBSW256", argLength: 2, reg: v21, asm: "VPSUBSW", commutative: false, typ: "Vec256", resultInArg0: false},
+ {name: "VPSUBSW512", argLength: 2, reg: w21, asm: "VPSUBSW", commutative: false, typ: "Vec512", resultInArg0: false},
+ {name: "VPSUBSWMasked128", argLength: 3, reg: w2kw, asm: "VPSUBSW", commutative: false, typ: "Vec128", resultInArg0: false},
+ {name: "VPSUBSWMasked256", argLength: 3, reg: w2kw, asm: "VPSUBSW", commutative: false, typ: "Vec256", resultInArg0: false},
+ {name: "VPSUBSWMasked512", argLength: 3, reg: w2kw, asm: "VPSUBSW", commutative: false, typ: "Vec512", resultInArg0: false},
+ {name: "VPSUBW128", argLength: 2, reg: v21, asm: "VPSUBW", commutative: false, typ: "Vec128", resultInArg0: false},
+ {name: "VPSUBW256", argLength: 2, reg: v21, asm: "VPSUBW", commutative: false, typ: "Vec256", resultInArg0: false},
+ {name: "VPSUBW512", argLength: 2, reg: w21, asm: "VPSUBW", commutative: false, typ: "Vec512", resultInArg0: false},
+ {name: "VPSUBWMasked128", argLength: 3, reg: w2kw, asm: "VPSUBW", commutative: false, typ: "Vec128", resultInArg0: false},
+ {name: "VPSUBWMasked256", argLength: 3, reg: w2kw, asm: "VPSUBW", commutative: false, typ: "Vec256", resultInArg0: false},
+ {name: "VPSUBWMasked512", argLength: 3, reg: w2kw, asm: "VPSUBW", commutative: false, typ: "Vec512", resultInArg0: false},
+ {name: "VPXOR128", argLength: 2, reg: v21, asm: "VPXOR", commutative: true, typ: "Vec128", resultInArg0: false},
+ {name: "VPXOR256", argLength: 2, reg: v21, asm: "VPXOR", commutative: true, typ: "Vec256", resultInArg0: false},
+ {name: "VPXORD512", argLength: 2, reg: w21, asm: "VPXORD", commutative: true, typ: "Vec512", resultInArg0: false},
+ {name: "VPXORDMasked128", argLength: 3, reg: w2kw, asm: "VPXORD", commutative: true, typ: "Vec128", resultInArg0: false},
+ {name: "VPXORDMasked256", argLength: 3, reg: w2kw, asm: "VPXORD", commutative: true, typ: "Vec256", resultInArg0: false},
+ {name: "VPXORDMasked512", argLength: 3, reg: w2kw, asm: "VPXORD", commutative: true, typ: "Vec512", resultInArg0: false},
+ {name: "VPXORQ512", argLength: 2, reg: w21, asm: "VPXORQ", commutative: true, typ: "Vec512", resultInArg0: false},
+ {name: "VPXORQMasked128", argLength: 3, reg: w2kw, asm: "VPXORQ", commutative: true, typ: "Vec128", resultInArg0: false},
+ {name: "VPXORQMasked256", argLength: 3, reg: w2kw, asm: "VPXORQ", commutative: true, typ: "Vec256", resultInArg0: false},
+ {name: "VPXORQMasked512", argLength: 3, reg: w2kw, asm: "VPXORQ", commutative: true, typ: "Vec512", resultInArg0: false},
+ {name: "VRCP14PD128", argLength: 1, reg: w11, asm: "VRCP14PD", commutative: false, typ: "Vec128", resultInArg0: false},
+ {name: "VRCP14PD256", argLength: 1, reg: w11, asm: "VRCP14PD", commutative: false, typ: "Vec256", resultInArg0: false},
+ {name: "VRCP14PD512", argLength: 1, reg: w11, asm: "VRCP14PD", commutative: false, typ: "Vec512", resultInArg0: false},
+ {name: "VRCP14PDMasked128", argLength: 2, reg: wkw, asm: "VRCP14PD", commutative: false, typ: "Vec128", resultInArg0: false},
+ {name: "VRCP14PDMasked256", argLength: 2, reg: wkw, asm: "VRCP14PD", commutative: false, typ: "Vec256", resultInArg0: false},
+ {name: "VRCP14PDMasked512", argLength: 2, reg: wkw, asm: "VRCP14PD", commutative: false, typ: "Vec512", resultInArg0: false},
+ {name: "VRCP14PS512", argLength: 1, reg: w11, asm: "VRCP14PS", commutative: false, typ: "Vec512", resultInArg0: false},
+ {name: "VRCP14PSMasked128", argLength: 2, reg: wkw, asm: "VRCP14PS", commutative: false, typ: "Vec128", resultInArg0: false},
+ {name: "VRCP14PSMasked256", argLength: 2, reg: wkw, asm: "VRCP14PS", commutative: false, typ: "Vec256", resultInArg0: false},
+ {name: "VRCP14PSMasked512", argLength: 2, reg: wkw, asm: "VRCP14PS", commutative: false, typ: "Vec512", resultInArg0: false},
+ {name: "VRCPPS128", argLength: 1, reg: v11, asm: "VRCPPS", commutative: false, typ: "Vec128", resultInArg0: false},
+ {name: "VRCPPS256", argLength: 1, reg: v11, asm: "VRCPPS", commutative: false, typ: "Vec256", resultInArg0: false},
+ {name: "VRSQRT14PD128", argLength: 1, reg: w11, asm: "VRSQRT14PD", commutative: false, typ: "Vec128", resultInArg0: false},
+ {name: "VRSQRT14PD256", argLength: 1, reg: w11, asm: "VRSQRT14PD", commutative: false, typ: "Vec256", resultInArg0: false},
+ {name: "VRSQRT14PD512", argLength: 1, reg: w11, asm: "VRSQRT14PD", commutative: false, typ: "Vec512", resultInArg0: false},
+ {name: "VRSQRT14PDMasked128", argLength: 2, reg: wkw, asm: "VRSQRT14PD", commutative: false, typ: "Vec128", resultInArg0: false},
+ {name: "VRSQRT14PDMasked256", argLength: 2, reg: wkw, asm: "VRSQRT14PD", commutative: false, typ: "Vec256", resultInArg0: false},
+ {name: "VRSQRT14PDMasked512", argLength: 2, reg: wkw, asm: "VRSQRT14PD", commutative: false, typ: "Vec512", resultInArg0: false},
+ {name: "VRSQRT14PS512", argLength: 1, reg: w11, asm: "VRSQRT14PS", commutative: false, typ: "Vec512", resultInArg0: false},
+ {name: "VRSQRT14PSMasked128", argLength: 2, reg: wkw, asm: "VRSQRT14PS", commutative: false, typ: "Vec128", resultInArg0: false},
+ {name: "VRSQRT14PSMasked256", argLength: 2, reg: wkw, asm: "VRSQRT14PS", commutative: false, typ: "Vec256", resultInArg0: false},
+ {name: "VRSQRT14PSMasked512", argLength: 2, reg: wkw, asm: "VRSQRT14PS", commutative: false, typ: "Vec512", resultInArg0: false},
+ {name: "VRSQRTPS128", argLength: 1, reg: v11, asm: "VRSQRTPS", commutative: false, typ: "Vec128", resultInArg0: false},
+ {name: "VRSQRTPS256", argLength: 1, reg: v11, asm: "VRSQRTPS", commutative: false, typ: "Vec256", resultInArg0: false},
+ {name: "VSCALEFPD128", argLength: 2, reg: w21, asm: "VSCALEFPD", commutative: false, typ: "Vec128", resultInArg0: false},
+ {name: "VSCALEFPD256", argLength: 2, reg: w21, asm: "VSCALEFPD", commutative: false, typ: "Vec256", resultInArg0: false},
+ {name: "VSCALEFPD512", argLength: 2, reg: w21, asm: "VSCALEFPD", commutative: false, typ: "Vec512", resultInArg0: false},
+ {name: "VSCALEFPDMasked128", argLength: 3, reg: w2kw, asm: "VSCALEFPD", commutative: false, typ: "Vec128", resultInArg0: false},
+ {name: "VSCALEFPDMasked256", argLength: 3, reg: w2kw, asm: "VSCALEFPD", commutative: false, typ: "Vec256", resultInArg0: false},
+ {name: "VSCALEFPDMasked512", argLength: 3, reg: w2kw, asm: "VSCALEFPD", commutative: false, typ: "Vec512", resultInArg0: false},
+ {name: "VSCALEFPS128", argLength: 2, reg: w21, asm: "VSCALEFPS", commutative: false, typ: "Vec128", resultInArg0: false},
+ {name: "VSCALEFPS256", argLength: 2, reg: w21, asm: "VSCALEFPS", commutative: false, typ: "Vec256", resultInArg0: false},
+ {name: "VSCALEFPS512", argLength: 2, reg: w21, asm: "VSCALEFPS", commutative: false, typ: "Vec512", resultInArg0: false},
+ {name: "VSCALEFPSMasked128", argLength: 3, reg: w2kw, asm: "VSCALEFPS", commutative: false, typ: "Vec128", resultInArg0: false},
+ {name: "VSCALEFPSMasked256", argLength: 3, reg: w2kw, asm: "VSCALEFPS", commutative: false, typ: "Vec256", resultInArg0: false},
+ {name: "VSCALEFPSMasked512", argLength: 3, reg: w2kw, asm: "VSCALEFPS", commutative: false, typ: "Vec512", resultInArg0: false},
+ {name: "VSQRTPD128", argLength: 1, reg: v11, asm: "VSQRTPD", commutative: false, typ: "Vec128", resultInArg0: false},
+ {name: "VSQRTPD256", argLength: 1, reg: v11, asm: "VSQRTPD", commutative: false, typ: "Vec256", resultInArg0: false},
+ {name: "VSQRTPD512", argLength: 1, reg: w11, asm: "VSQRTPD", commutative: false, typ: "Vec512", resultInArg0: false},
+ {name: "VSQRTPDMasked128", argLength: 2, reg: wkw, asm: "VSQRTPD", commutative: false, typ: "Vec128", resultInArg0: false},
+ {name: "VSQRTPDMasked256", argLength: 2, reg: wkw, asm: "VSQRTPD", commutative: false, typ: "Vec256", resultInArg0: false},
+ {name: "VSQRTPDMasked512", argLength: 2, reg: wkw, asm: "VSQRTPD", commutative: false, typ: "Vec512", resultInArg0: false},
+ {name: "VSQRTPS128", argLength: 1, reg: v11, asm: "VSQRTPS", commutative: false, typ: "Vec128", resultInArg0: false},
+ {name: "VSQRTPS256", argLength: 1, reg: v11, asm: "VSQRTPS", commutative: false, typ: "Vec256", resultInArg0: false},
+ {name: "VSQRTPS512", argLength: 1, reg: w11, asm: "VSQRTPS", commutative: false, typ: "Vec512", resultInArg0: false},
+ {name: "VSQRTPSMasked128", argLength: 2, reg: wkw, asm: "VSQRTPS", commutative: false, typ: "Vec128", resultInArg0: false},
+ {name: "VSQRTPSMasked256", argLength: 2, reg: wkw, asm: "VSQRTPS", commutative: false, typ: "Vec256", resultInArg0: false},
+ {name: "VSQRTPSMasked512", argLength: 2, reg: wkw, asm: "VSQRTPS", commutative: false, typ: "Vec512", resultInArg0: false},
+ {name: "VSUBPD128", argLength: 2, reg: v21, asm: "VSUBPD", commutative: false, typ: "Vec128", resultInArg0: false},
+ {name: "VSUBPD256", argLength: 2, reg: v21, asm: "VSUBPD", commutative: false, typ: "Vec256", resultInArg0: false},
+ {name: "VSUBPD512", argLength: 2, reg: w21, asm: "VSUBPD", commutative: false, typ: "Vec512", resultInArg0: false},
+ {name: "VSUBPDMasked128", argLength: 3, reg: w2kw, asm: "VSUBPD", commutative: false, typ: "Vec128", resultInArg0: false},
+ {name: "VSUBPDMasked256", argLength: 3, reg: w2kw, asm: "VSUBPD", commutative: false, typ: "Vec256", resultInArg0: false},
+ {name: "VSUBPDMasked512", argLength: 3, reg: w2kw, asm: "VSUBPD", commutative: false, typ: "Vec512", resultInArg0: false},
+ {name: "VSUBPS128", argLength: 2, reg: v21, asm: "VSUBPS", commutative: false, typ: "Vec128", resultInArg0: false},
+ {name: "VSUBPS256", argLength: 2, reg: v21, asm: "VSUBPS", commutative: false, typ: "Vec256", resultInArg0: false},
+ {name: "VSUBPS512", argLength: 2, reg: w21, asm: "VSUBPS", commutative: false, typ: "Vec512", resultInArg0: false},
+ {name: "VSUBPSMasked128", argLength: 3, reg: w2kw, asm: "VSUBPS", commutative: false, typ: "Vec128", resultInArg0: false},
+ {name: "VSUBPSMasked256", argLength: 3, reg: w2kw, asm: "VSUBPS", commutative: false, typ: "Vec256", resultInArg0: false},
+ {name: "VSUBPSMasked512", argLength: 3, reg: w2kw, asm: "VSUBPS", commutative: false, typ: "Vec512", resultInArg0: false},
{name: "VROUNDPS128", argLength: 1, reg: v11, asm: "VROUNDPS", aux: "Int8", commutative: false, typ: "Vec128", resultInArg0: false},
- {name: "VRNDSCALEPS128", argLength: 1, reg: w11, asm: "VRNDSCALEPS", aux: "Int8", commutative: false, typ: "Vec128", resultInArg0: false},
- {name: "VRNDSCALEPSMasked128", argLength: 2, reg: wkw, asm: "VRNDSCALEPS", aux: "Int8", commutative: false, typ: "Vec128", resultInArg0: false},
- {name: "VREDUCEPS128", argLength: 1, reg: w11, asm: "VREDUCEPS", aux: "Int8", commutative: false, typ: "Vec128", resultInArg0: false},
- {name: "VREDUCEPSMasked128", argLength: 2, reg: wkw, asm: "VREDUCEPS", aux: "Int8", commutative: false, typ: "Vec128", resultInArg0: false},
- {name: "VDPPS128", argLength: 2, reg: v21, asm: "VDPPS", aux: "Int8", commutative: true, typ: "Vec128", resultInArg0: false},
- {name: "VCMPPS128", argLength: 2, reg: v21, asm: "VCMPPS", aux: "Int8", commutative: true, typ: "Vec128", resultInArg0: false},
- {name: "VCMPPSMasked128", argLength: 3, reg: w2kk, asm: "VCMPPS", aux: "Int8", commutative: true, typ: "Mask", resultInArg0: false},
{name: "VROUNDPS256", argLength: 1, reg: v11, asm: "VROUNDPS", aux: "Int8", commutative: false, typ: "Vec256", resultInArg0: false},
- {name: "VRNDSCALEPS256", argLength: 1, reg: w11, asm: "VRNDSCALEPS", aux: "Int8", commutative: false, typ: "Vec256", resultInArg0: false},
- {name: "VRNDSCALEPSMasked256", argLength: 2, reg: wkw, asm: "VRNDSCALEPS", aux: "Int8", commutative: false, typ: "Vec256", resultInArg0: false},
- {name: "VREDUCEPS256", argLength: 1, reg: w11, asm: "VREDUCEPS", aux: "Int8", commutative: false, typ: "Vec256", resultInArg0: false},
- {name: "VREDUCEPSMasked256", argLength: 2, reg: wkw, asm: "VREDUCEPS", aux: "Int8", commutative: false, typ: "Vec256", resultInArg0: false},
- {name: "VDPPS256", argLength: 2, reg: v21, asm: "VDPPS", aux: "Int8", commutative: true, typ: "Vec256", resultInArg0: false},
- {name: "VCMPPS256", argLength: 2, reg: v21, asm: "VCMPPS", aux: "Int8", commutative: true, typ: "Vec256", resultInArg0: false},
- {name: "VCMPPSMasked256", argLength: 3, reg: w2kk, asm: "VCMPPS", aux: "Int8", commutative: true, typ: "Mask", resultInArg0: false},
- {name: "VEXTRACTF128128", argLength: 1, reg: v11, asm: "VEXTRACTF128", aux: "Int8", commutative: false, typ: "Vec128", resultInArg0: false},
- {name: "VINSERTF128256", argLength: 2, reg: v21, asm: "VINSERTF128", aux: "Int8", commutative: false, typ: "Vec256", resultInArg0: false},
{name: "VROUNDPD128", argLength: 1, reg: v11, asm: "VROUNDPD", aux: "Int8", commutative: false, typ: "Vec128", resultInArg0: false},
+ {name: "VROUNDPD256", argLength: 1, reg: v11, asm: "VROUNDPD", aux: "Int8", commutative: false, typ: "Vec256", resultInArg0: false},
+ {name: "VRNDSCALEPS128", argLength: 1, reg: w11, asm: "VRNDSCALEPS", aux: "Int8", commutative: false, typ: "Vec128", resultInArg0: false},
+ {name: "VRNDSCALEPS256", argLength: 1, reg: w11, asm: "VRNDSCALEPS", aux: "Int8", commutative: false, typ: "Vec256", resultInArg0: false},
+ {name: "VRNDSCALEPS512", argLength: 1, reg: w11, asm: "VRNDSCALEPS", aux: "Int8", commutative: false, typ: "Vec512", resultInArg0: false},
{name: "VRNDSCALEPD128", argLength: 1, reg: w11, asm: "VRNDSCALEPD", aux: "Int8", commutative: false, typ: "Vec128", resultInArg0: false},
+ {name: "VRNDSCALEPD256", argLength: 1, reg: w11, asm: "VRNDSCALEPD", aux: "Int8", commutative: false, typ: "Vec256", resultInArg0: false},
+ {name: "VRNDSCALEPD512", argLength: 1, reg: w11, asm: "VRNDSCALEPD", aux: "Int8", commutative: false, typ: "Vec512", resultInArg0: false},
+ {name: "VRNDSCALEPSMasked128", argLength: 2, reg: wkw, asm: "VRNDSCALEPS", aux: "Int8", commutative: false, typ: "Vec128", resultInArg0: false},
+ {name: "VRNDSCALEPSMasked256", argLength: 2, reg: wkw, asm: "VRNDSCALEPS", aux: "Int8", commutative: false, typ: "Vec256", resultInArg0: false},
+ {name: "VRNDSCALEPSMasked512", argLength: 2, reg: wkw, asm: "VRNDSCALEPS", aux: "Int8", commutative: false, typ: "Vec512", resultInArg0: false},
{name: "VRNDSCALEPDMasked128", argLength: 2, reg: wkw, asm: "VRNDSCALEPD", aux: "Int8", commutative: false, typ: "Vec128", resultInArg0: false},
+ {name: "VRNDSCALEPDMasked256", argLength: 2, reg: wkw, asm: "VRNDSCALEPD", aux: "Int8", commutative: false, typ: "Vec256", resultInArg0: false},
+ {name: "VRNDSCALEPDMasked512", argLength: 2, reg: wkw, asm: "VRNDSCALEPD", aux: "Int8", commutative: false, typ: "Vec512", resultInArg0: false},
+ {name: "VREDUCEPS128", argLength: 1, reg: w11, asm: "VREDUCEPS", aux: "Int8", commutative: false, typ: "Vec128", resultInArg0: false},
+ {name: "VREDUCEPS256", argLength: 1, reg: w11, asm: "VREDUCEPS", aux: "Int8", commutative: false, typ: "Vec256", resultInArg0: false},
+ {name: "VREDUCEPS512", argLength: 1, reg: w11, asm: "VREDUCEPS", aux: "Int8", commutative: false, typ: "Vec512", resultInArg0: false},
{name: "VREDUCEPD128", argLength: 1, reg: w11, asm: "VREDUCEPD", aux: "Int8", commutative: false, typ: "Vec128", resultInArg0: false},
+ {name: "VREDUCEPD256", argLength: 1, reg: w11, asm: "VREDUCEPD", aux: "Int8", commutative: false, typ: "Vec256", resultInArg0: false},
+ {name: "VREDUCEPD512", argLength: 1, reg: w11, asm: "VREDUCEPD", aux: "Int8", commutative: false, typ: "Vec512", resultInArg0: false},
+ {name: "VREDUCEPSMasked128", argLength: 2, reg: wkw, asm: "VREDUCEPS", aux: "Int8", commutative: false, typ: "Vec128", resultInArg0: false},
+ {name: "VREDUCEPSMasked256", argLength: 2, reg: wkw, asm: "VREDUCEPS", aux: "Int8", commutative: false, typ: "Vec256", resultInArg0: false},
+ {name: "VREDUCEPSMasked512", argLength: 2, reg: wkw, asm: "VREDUCEPS", aux: "Int8", commutative: false, typ: "Vec512", resultInArg0: false},
{name: "VREDUCEPDMasked128", argLength: 2, reg: wkw, asm: "VREDUCEPD", aux: "Int8", commutative: false, typ: "Vec128", resultInArg0: false},
+ {name: "VREDUCEPDMasked256", argLength: 2, reg: wkw, asm: "VREDUCEPD", aux: "Int8", commutative: false, typ: "Vec256", resultInArg0: false},
+ {name: "VREDUCEPDMasked512", argLength: 2, reg: wkw, asm: "VREDUCEPD", aux: "Int8", commutative: false, typ: "Vec512", resultInArg0: false},
+ {name: "VDPPS128", argLength: 2, reg: v21, asm: "VDPPS", aux: "Int8", commutative: true, typ: "Vec128", resultInArg0: false},
+ {name: "VDPPS256", argLength: 2, reg: v21, asm: "VDPPS", aux: "Int8", commutative: true, typ: "Vec256", resultInArg0: false},
{name: "VDPPD128", argLength: 2, reg: v21, asm: "VDPPD", aux: "Int8", commutative: true, typ: "Vec128", resultInArg0: false},
+ {name: "VCMPPS128", argLength: 2, reg: v21, asm: "VCMPPS", aux: "Int8", commutative: true, typ: "Vec128", resultInArg0: false},
+ {name: "VCMPPS256", argLength: 2, reg: v21, asm: "VCMPPS", aux: "Int8", commutative: true, typ: "Vec256", resultInArg0: false},
+ {name: "VCMPPS512", argLength: 2, reg: w2k, asm: "VCMPPS", aux: "Int8", commutative: true, typ: "Mask", resultInArg0: false},
{name: "VCMPPD128", argLength: 2, reg: v21, asm: "VCMPPD", aux: "Int8", commutative: true, typ: "Vec128", resultInArg0: false},
- {name: "VCMPPDMasked128", argLength: 3, reg: w2kk, asm: "VCMPPD", aux: "Int8", commutative: true, typ: "Mask", resultInArg0: false},
- {name: "VROUNDPD256", argLength: 1, reg: v11, asm: "VROUNDPD", aux: "Int8", commutative: false, typ: "Vec256", resultInArg0: false},
- {name: "VRNDSCALEPD256", argLength: 1, reg: w11, asm: "VRNDSCALEPD", aux: "Int8", commutative: false, typ: "Vec256", resultInArg0: false},
- {name: "VRNDSCALEPDMasked256", argLength: 2, reg: wkw, asm: "VRNDSCALEPD", aux: "Int8", commutative: false, typ: "Vec256", resultInArg0: false},
- {name: "VREDUCEPD256", argLength: 1, reg: w11, asm: "VREDUCEPD", aux: "Int8", commutative: false, typ: "Vec256", resultInArg0: false},
- {name: "VREDUCEPDMasked256", argLength: 2, reg: wkw, asm: "VREDUCEPD", aux: "Int8", commutative: false, typ: "Vec256", resultInArg0: false},
{name: "VCMPPD256", argLength: 2, reg: v21, asm: "VCMPPD", aux: "Int8", commutative: true, typ: "Vec256", resultInArg0: false},
- {name: "VCMPPDMasked256", argLength: 3, reg: w2kk, asm: "VCMPPD", aux: "Int8", commutative: true, typ: "Mask", resultInArg0: false},
- {name: "VRNDSCALEPD512", argLength: 1, reg: w11, asm: "VRNDSCALEPD", aux: "Int8", commutative: false, typ: "Vec512", resultInArg0: false},
- {name: "VRNDSCALEPDMasked512", argLength: 2, reg: wkw, asm: "VRNDSCALEPD", aux: "Int8", commutative: false, typ: "Vec512", resultInArg0: false},
- {name: "VREDUCEPD512", argLength: 1, reg: w11, asm: "VREDUCEPD", aux: "Int8", commutative: false, typ: "Vec512", resultInArg0: false},
- {name: "VREDUCEPDMasked512", argLength: 2, reg: wkw, asm: "VREDUCEPD", aux: "Int8", commutative: false, typ: "Vec512", resultInArg0: false},
{name: "VCMPPD512", argLength: 2, reg: w2k, asm: "VCMPPD", aux: "Int8", commutative: true, typ: "Mask", resultInArg0: false},
+ {name: "VCMPPSMasked128", argLength: 3, reg: w2kk, asm: "VCMPPS", aux: "Int8", commutative: true, typ: "Mask", resultInArg0: false},
+ {name: "VCMPPSMasked256", argLength: 3, reg: w2kk, asm: "VCMPPS", aux: "Int8", commutative: true, typ: "Mask", resultInArg0: false},
+ {name: "VCMPPSMasked512", argLength: 3, reg: w2kk, asm: "VCMPPS", aux: "Int8", commutative: true, typ: "Mask", resultInArg0: false},
+ {name: "VCMPPDMasked128", argLength: 3, reg: w2kk, asm: "VCMPPD", aux: "Int8", commutative: true, typ: "Mask", resultInArg0: false},
+ {name: "VCMPPDMasked256", argLength: 3, reg: w2kk, asm: "VCMPPD", aux: "Int8", commutative: true, typ: "Mask", resultInArg0: false},
{name: "VCMPPDMasked512", argLength: 3, reg: w2kk, asm: "VCMPPD", aux: "Int8", commutative: true, typ: "Mask", resultInArg0: false},
+ {name: "VPCMPBMasked128", argLength: 3, reg: w2kk, asm: "VPCMPB", aux: "Int8", commutative: true, typ: "Mask", resultInArg0: false},
+ {name: "VPCMPBMasked256", argLength: 3, reg: w2kk, asm: "VPCMPB", aux: "Int8", commutative: true, typ: "Mask", resultInArg0: false},
+ {name: "VPCMPBMasked512", argLength: 3, reg: w2kk, asm: "VPCMPB", aux: "Int8", commutative: true, typ: "Mask", resultInArg0: false},
+ {name: "VPCMPWMasked128", argLength: 3, reg: w2kk, asm: "VPCMPW", aux: "Int8", commutative: true, typ: "Mask", resultInArg0: false},
{name: "VPCMPWMasked256", argLength: 3, reg: w2kk, asm: "VPCMPW", aux: "Int8", commutative: true, typ: "Mask", resultInArg0: false},
- {name: "VPCMPW256", argLength: 2, reg: w2k, asm: "VPCMPW", aux: "Int8", commutative: false, typ: "Mask", resultInArg0: false},
- {name: "VPSHLDW256", argLength: 2, reg: w21, asm: "VPSHLDW", aux: "Int8", commutative: false, typ: "Vec256", resultInArg0: false},
- {name: "VPSHLDWMasked256", argLength: 3, reg: w2kw, asm: "VPSHLDW", aux: "Int8", commutative: false, typ: "Vec256", resultInArg0: false},
- {name: "VPSHRDW256", argLength: 2, reg: w21, asm: "VPSHRDW", aux: "Int8", commutative: false, typ: "Vec256", resultInArg0: false},
- {name: "VPSHRDWMasked256", argLength: 3, reg: w2kw, asm: "VPSHRDW", aux: "Int8", commutative: false, typ: "Vec256", resultInArg0: false},
{name: "VPCMPWMasked512", argLength: 3, reg: w2kk, asm: "VPCMPW", aux: "Int8", commutative: true, typ: "Mask", resultInArg0: false},
- {name: "VPCMPW512", argLength: 2, reg: w2k, asm: "VPCMPW", aux: "Int8", commutative: false, typ: "Mask", resultInArg0: false},
- {name: "VPSHLDW512", argLength: 2, reg: w21, asm: "VPSHLDW", aux: "Int8", commutative: false, typ: "Vec512", resultInArg0: false},
- {name: "VPSHLDWMasked512", argLength: 3, reg: w2kw, asm: "VPSHLDW", aux: "Int8", commutative: false, typ: "Vec512", resultInArg0: false},
- {name: "VPSHRDW512", argLength: 2, reg: w21, asm: "VPSHRDW", aux: "Int8", commutative: false, typ: "Vec512", resultInArg0: false},
- {name: "VPSHRDWMasked512", argLength: 3, reg: w2kw, asm: "VPSHRDW", aux: "Int8", commutative: false, typ: "Vec512", resultInArg0: false},
- {name: "VPCMPWMasked128", argLength: 3, reg: w2kk, asm: "VPCMPW", aux: "Int8", commutative: true, typ: "Mask", resultInArg0: false},
- {name: "VPEXTRW128", argLength: 1, reg: wgp, asm: "VPEXTRW", aux: "Int8", commutative: false, typ: "int16", resultInArg0: false},
- {name: "VPCMPW128", argLength: 2, reg: w2k, asm: "VPCMPW", aux: "Int8", commutative: false, typ: "Mask", resultInArg0: false},
- {name: "VPINSRW128", argLength: 2, reg: vgpv, asm: "VPINSRW", aux: "Int8", commutative: false, typ: "Vec128", resultInArg0: false},
- {name: "VPSHLDW128", argLength: 2, reg: w21, asm: "VPSHLDW", aux: "Int8", commutative: false, typ: "Vec128", resultInArg0: false},
- {name: "VPSHLDWMasked128", argLength: 3, reg: w2kw, asm: "VPSHLDW", aux: "Int8", commutative: false, typ: "Vec128", resultInArg0: false},
- {name: "VPSHRDW128", argLength: 2, reg: w21, asm: "VPSHRDW", aux: "Int8", commutative: false, typ: "Vec128", resultInArg0: false},
- {name: "VPSHRDWMasked128", argLength: 3, reg: w2kw, asm: "VPSHRDW", aux: "Int8", commutative: false, typ: "Vec128", resultInArg0: false},
- {name: "VPCMPDMasked512", argLength: 3, reg: w2kk, asm: "VPCMPD", aux: "Int8", commutative: true, typ: "Mask", resultInArg0: false},
- {name: "VPCMPD512", argLength: 2, reg: w2k, asm: "VPCMPD", aux: "Int8", commutative: false, typ: "Mask", resultInArg0: false},
- {name: "VPROLD512", argLength: 1, reg: w11, asm: "VPROLD", aux: "Int8", commutative: false, typ: "Vec512", resultInArg0: false},
- {name: "VPROLDMasked512", argLength: 2, reg: wkw, asm: "VPROLD", aux: "Int8", commutative: false, typ: "Vec512", resultInArg0: false},
- {name: "VPRORD512", argLength: 1, reg: w11, asm: "VPRORD", aux: "Int8", commutative: false, typ: "Vec512", resultInArg0: false},
- {name: "VPRORDMasked512", argLength: 2, reg: wkw, asm: "VPRORD", aux: "Int8", commutative: false, typ: "Vec512", resultInArg0: false},
- {name: "VPSHLDD512", argLength: 2, reg: w21, asm: "VPSHLDD", aux: "Int8", commutative: false, typ: "Vec512", resultInArg0: false},
- {name: "VPSHLDDMasked512", argLength: 3, reg: w2kw, asm: "VPSHLDD", aux: "Int8", commutative: false, typ: "Vec512", resultInArg0: false},
- {name: "VPSHRDD512", argLength: 2, reg: w21, asm: "VPSHRDD", aux: "Int8", commutative: false, typ: "Vec512", resultInArg0: false},
- {name: "VPSHRDDMasked512", argLength: 3, reg: w2kw, asm: "VPSHRDD", aux: "Int8", commutative: false, typ: "Vec512", resultInArg0: false},
{name: "VPCMPDMasked128", argLength: 3, reg: w2kk, asm: "VPCMPD", aux: "Int8", commutative: true, typ: "Mask", resultInArg0: false},
- {name: "VPEXTRD128", argLength: 1, reg: vgp, asm: "VPEXTRD", aux: "Int8", commutative: false, typ: "int32", resultInArg0: false},
- {name: "VPCMPD128", argLength: 2, reg: w2k, asm: "VPCMPD", aux: "Int8", commutative: false, typ: "Mask", resultInArg0: false},
- {name: "VPROLD128", argLength: 1, reg: w11, asm: "VPROLD", aux: "Int8", commutative: false, typ: "Vec128", resultInArg0: false},
- {name: "VPROLDMasked128", argLength: 2, reg: wkw, asm: "VPROLD", aux: "Int8", commutative: false, typ: "Vec128", resultInArg0: false},
- {name: "VPRORD128", argLength: 1, reg: w11, asm: "VPRORD", aux: "Int8", commutative: false, typ: "Vec128", resultInArg0: false},
- {name: "VPRORDMasked128", argLength: 2, reg: wkw, asm: "VPRORD", aux: "Int8", commutative: false, typ: "Vec128", resultInArg0: false},
- {name: "VPINSRD128", argLength: 2, reg: vgpv, asm: "VPINSRD", aux: "Int8", commutative: false, typ: "Vec128", resultInArg0: false},
- {name: "VPSHLDD128", argLength: 2, reg: w21, asm: "VPSHLDD", aux: "Int8", commutative: false, typ: "Vec128", resultInArg0: false},
- {name: "VPSHLDDMasked128", argLength: 3, reg: w2kw, asm: "VPSHLDD", aux: "Int8", commutative: false, typ: "Vec128", resultInArg0: false},
- {name: "VPSHRDD128", argLength: 2, reg: w21, asm: "VPSHRDD", aux: "Int8", commutative: false, typ: "Vec128", resultInArg0: false},
- {name: "VPSHRDDMasked128", argLength: 3, reg: w2kw, asm: "VPSHRDD", aux: "Int8", commutative: false, typ: "Vec128", resultInArg0: false},
{name: "VPCMPDMasked256", argLength: 3, reg: w2kk, asm: "VPCMPD", aux: "Int8", commutative: true, typ: "Mask", resultInArg0: false},
- {name: "VPCMPD256", argLength: 2, reg: w2k, asm: "VPCMPD", aux: "Int8", commutative: false, typ: "Mask", resultInArg0: false},
- {name: "VPROLD256", argLength: 1, reg: w11, asm: "VPROLD", aux: "Int8", commutative: false, typ: "Vec256", resultInArg0: false},
- {name: "VPROLDMasked256", argLength: 2, reg: wkw, asm: "VPROLD", aux: "Int8", commutative: false, typ: "Vec256", resultInArg0: false},
- {name: "VPRORD256", argLength: 1, reg: w11, asm: "VPRORD", aux: "Int8", commutative: false, typ: "Vec256", resultInArg0: false},
- {name: "VPRORDMasked256", argLength: 2, reg: wkw, asm: "VPRORD", aux: "Int8", commutative: false, typ: "Vec256", resultInArg0: false},
- {name: "VPSHLDD256", argLength: 2, reg: w21, asm: "VPSHLDD", aux: "Int8", commutative: false, typ: "Vec256", resultInArg0: false},
- {name: "VPSHLDDMasked256", argLength: 3, reg: w2kw, asm: "VPSHLDD", aux: "Int8", commutative: false, typ: "Vec256", resultInArg0: false},
- {name: "VPSHRDD256", argLength: 2, reg: w21, asm: "VPSHRDD", aux: "Int8", commutative: false, typ: "Vec256", resultInArg0: false},
- {name: "VPSHRDDMasked256", argLength: 3, reg: w2kw, asm: "VPSHRDD", aux: "Int8", commutative: false, typ: "Vec256", resultInArg0: false},
+ {name: "VPCMPDMasked512", argLength: 3, reg: w2kk, asm: "VPCMPD", aux: "Int8", commutative: true, typ: "Mask", resultInArg0: false},
{name: "VPCMPQMasked128", argLength: 3, reg: w2kk, asm: "VPCMPQ", aux: "Int8", commutative: true, typ: "Mask", resultInArg0: false},
- {name: "VPEXTRQ128", argLength: 1, reg: vgp, asm: "VPEXTRQ", aux: "Int8", commutative: false, typ: "int64", resultInArg0: false},
- {name: "VPCMPQ128", argLength: 2, reg: w2k, asm: "VPCMPQ", aux: "Int8", commutative: false, typ: "Mask", resultInArg0: false},
- {name: "VPROLQ128", argLength: 1, reg: w11, asm: "VPROLQ", aux: "Int8", commutative: false, typ: "Vec128", resultInArg0: false},
- {name: "VPROLQMasked128", argLength: 2, reg: wkw, asm: "VPROLQ", aux: "Int8", commutative: false, typ: "Vec128", resultInArg0: false},
- {name: "VPRORQ128", argLength: 1, reg: w11, asm: "VPRORQ", aux: "Int8", commutative: false, typ: "Vec128", resultInArg0: false},
- {name: "VPRORQMasked128", argLength: 2, reg: wkw, asm: "VPRORQ", aux: "Int8", commutative: false, typ: "Vec128", resultInArg0: false},
- {name: "VPINSRQ128", argLength: 2, reg: vgpv, asm: "VPINSRQ", aux: "Int8", commutative: false, typ: "Vec128", resultInArg0: false},
- {name: "VPSHLDQ128", argLength: 2, reg: w21, asm: "VPSHLDQ", aux: "Int8", commutative: false, typ: "Vec128", resultInArg0: false},
- {name: "VPSHLDQMasked128", argLength: 3, reg: w2kw, asm: "VPSHLDQ", aux: "Int8", commutative: false, typ: "Vec128", resultInArg0: false},
- {name: "VPSHRDQ128", argLength: 2, reg: w21, asm: "VPSHRDQ", aux: "Int8", commutative: false, typ: "Vec128", resultInArg0: false},
- {name: "VPSHRDQMasked128", argLength: 3, reg: w2kw, asm: "VPSHRDQ", aux: "Int8", commutative: false, typ: "Vec128", resultInArg0: false},
{name: "VPCMPQMasked256", argLength: 3, reg: w2kk, asm: "VPCMPQ", aux: "Int8", commutative: true, typ: "Mask", resultInArg0: false},
- {name: "VPCMPQ256", argLength: 2, reg: w2k, asm: "VPCMPQ", aux: "Int8", commutative: false, typ: "Mask", resultInArg0: false},
- {name: "VPROLQ256", argLength: 1, reg: w11, asm: "VPROLQ", aux: "Int8", commutative: false, typ: "Vec256", resultInArg0: false},
- {name: "VPROLQMasked256", argLength: 2, reg: wkw, asm: "VPROLQ", aux: "Int8", commutative: false, typ: "Vec256", resultInArg0: false},
- {name: "VPRORQ256", argLength: 1, reg: w11, asm: "VPRORQ", aux: "Int8", commutative: false, typ: "Vec256", resultInArg0: false},
- {name: "VPRORQMasked256", argLength: 2, reg: wkw, asm: "VPRORQ", aux: "Int8", commutative: false, typ: "Vec256", resultInArg0: false},
- {name: "VPSHLDQ256", argLength: 2, reg: w21, asm: "VPSHLDQ", aux: "Int8", commutative: false, typ: "Vec256", resultInArg0: false},
- {name: "VPSHLDQMasked256", argLength: 3, reg: w2kw, asm: "VPSHLDQ", aux: "Int8", commutative: false, typ: "Vec256", resultInArg0: false},
- {name: "VPSHRDQ256", argLength: 2, reg: w21, asm: "VPSHRDQ", aux: "Int8", commutative: false, typ: "Vec256", resultInArg0: false},
- {name: "VPSHRDQMasked256", argLength: 3, reg: w2kw, asm: "VPSHRDQ", aux: "Int8", commutative: false, typ: "Vec256", resultInArg0: false},
{name: "VPCMPQMasked512", argLength: 3, reg: w2kk, asm: "VPCMPQ", aux: "Int8", commutative: true, typ: "Mask", resultInArg0: false},
- {name: "VPCMPQ512", argLength: 2, reg: w2k, asm: "VPCMPQ", aux: "Int8", commutative: false, typ: "Mask", resultInArg0: false},
- {name: "VPROLQ512", argLength: 1, reg: w11, asm: "VPROLQ", aux: "Int8", commutative: false, typ: "Vec512", resultInArg0: false},
- {name: "VPROLQMasked512", argLength: 2, reg: wkw, asm: "VPROLQ", aux: "Int8", commutative: false, typ: "Vec512", resultInArg0: false},
- {name: "VPRORQ512", argLength: 1, reg: w11, asm: "VPRORQ", aux: "Int8", commutative: false, typ: "Vec512", resultInArg0: false},
- {name: "VPRORQMasked512", argLength: 2, reg: wkw, asm: "VPRORQ", aux: "Int8", commutative: false, typ: "Vec512", resultInArg0: false},
- {name: "VPSHLDQ512", argLength: 2, reg: w21, asm: "VPSHLDQ", aux: "Int8", commutative: false, typ: "Vec512", resultInArg0: false},
- {name: "VPSHLDQMasked512", argLength: 3, reg: w2kw, asm: "VPSHLDQ", aux: "Int8", commutative: false, typ: "Vec512", resultInArg0: false},
- {name: "VPSHRDQ512", argLength: 2, reg: w21, asm: "VPSHRDQ", aux: "Int8", commutative: false, typ: "Vec512", resultInArg0: false},
- {name: "VPSHRDQMasked512", argLength: 3, reg: w2kw, asm: "VPSHRDQ", aux: "Int8", commutative: false, typ: "Vec512", resultInArg0: false},
- {name: "VPCMPBMasked128", argLength: 3, reg: w2kk, asm: "VPCMPB", aux: "Int8", commutative: true, typ: "Mask", resultInArg0: false},
- {name: "VPEXTRB128", argLength: 1, reg: wgp, asm: "VPEXTRB", aux: "Int8", commutative: false, typ: "int8", resultInArg0: false},
- {name: "VPCMPB128", argLength: 2, reg: w2k, asm: "VPCMPB", aux: "Int8", commutative: false, typ: "Mask", resultInArg0: false},
- {name: "VPINSRB128", argLength: 2, reg: vgpv, asm: "VPINSRB", aux: "Int8", commutative: false, typ: "Vec128", resultInArg0: false},
- {name: "VPCMPBMasked256", argLength: 3, reg: w2kk, asm: "VPCMPB", aux: "Int8", commutative: true, typ: "Mask", resultInArg0: false},
- {name: "VEXTRACTI128128", argLength: 1, reg: v11, asm: "VEXTRACTI128", aux: "Int8", commutative: false, typ: "Vec128", resultInArg0: false},
- {name: "VPCMPB256", argLength: 2, reg: w2k, asm: "VPCMPB", aux: "Int8", commutative: false, typ: "Mask", resultInArg0: false},
- {name: "VINSERTI128256", argLength: 2, reg: v21, asm: "VINSERTI128", aux: "Int8", commutative: false, typ: "Vec256", resultInArg0: false},
- {name: "VPCMPBMasked512", argLength: 3, reg: w2kk, asm: "VPCMPB", aux: "Int8", commutative: true, typ: "Mask", resultInArg0: false},
- {name: "VPCMPB512", argLength: 2, reg: w2k, asm: "VPCMPB", aux: "Int8", commutative: false, typ: "Mask", resultInArg0: false},
+ {name: "VPCMPUBMasked128", argLength: 3, reg: w2kk, asm: "VPCMPUB", aux: "Int8", commutative: true, typ: "Mask", resultInArg0: false},
+ {name: "VPCMPUBMasked256", argLength: 3, reg: w2kk, asm: "VPCMPUB", aux: "Int8", commutative: true, typ: "Mask", resultInArg0: false},
+ {name: "VPCMPUBMasked512", argLength: 3, reg: w2kk, asm: "VPCMPUB", aux: "Int8", commutative: true, typ: "Mask", resultInArg0: false},
+ {name: "VPCMPUWMasked128", argLength: 3, reg: w2kk, asm: "VPCMPUW", aux: "Int8", commutative: true, typ: "Mask", resultInArg0: false},
{name: "VPCMPUWMasked256", argLength: 3, reg: w2kk, asm: "VPCMPUW", aux: "Int8", commutative: true, typ: "Mask", resultInArg0: false},
- {name: "VPCMPUW256", argLength: 2, reg: w2k, asm: "VPCMPUW", aux: "Int8", commutative: false, typ: "Mask", resultInArg0: false},
{name: "VPCMPUWMasked512", argLength: 3, reg: w2kk, asm: "VPCMPUW", aux: "Int8", commutative: true, typ: "Mask", resultInArg0: false},
- {name: "VPCMPUW512", argLength: 2, reg: w2k, asm: "VPCMPUW", aux: "Int8", commutative: false, typ: "Mask", resultInArg0: false},
- {name: "VPCMPUWMasked128", argLength: 3, reg: w2kk, asm: "VPCMPUW", aux: "Int8", commutative: true, typ: "Mask", resultInArg0: false},
- {name: "VPCMPUW128", argLength: 2, reg: w2k, asm: "VPCMPUW", aux: "Int8", commutative: false, typ: "Mask", resultInArg0: false},
- {name: "VPCMPUDMasked512", argLength: 3, reg: w2kk, asm: "VPCMPUD", aux: "Int8", commutative: true, typ: "Mask", resultInArg0: false},
- {name: "VPCMPUD512", argLength: 2, reg: w2k, asm: "VPCMPUD", aux: "Int8", commutative: false, typ: "Mask", resultInArg0: false},
{name: "VPCMPUDMasked128", argLength: 3, reg: w2kk, asm: "VPCMPUD", aux: "Int8", commutative: true, typ: "Mask", resultInArg0: false},
- {name: "VPCMPUD128", argLength: 2, reg: w2k, asm: "VPCMPUD", aux: "Int8", commutative: false, typ: "Mask", resultInArg0: false},
{name: "VPCMPUDMasked256", argLength: 3, reg: w2kk, asm: "VPCMPUD", aux: "Int8", commutative: true, typ: "Mask", resultInArg0: false},
- {name: "VPCMPUD256", argLength: 2, reg: w2k, asm: "VPCMPUD", aux: "Int8", commutative: false, typ: "Mask", resultInArg0: false},
+ {name: "VPCMPUDMasked512", argLength: 3, reg: w2kk, asm: "VPCMPUD", aux: "Int8", commutative: true, typ: "Mask", resultInArg0: false},
{name: "VPCMPUQMasked128", argLength: 3, reg: w2kk, asm: "VPCMPUQ", aux: "Int8", commutative: true, typ: "Mask", resultInArg0: false},
- {name: "VPCMPUQ128", argLength: 2, reg: w2k, asm: "VPCMPUQ", aux: "Int8", commutative: false, typ: "Mask", resultInArg0: false},
{name: "VPCMPUQMasked256", argLength: 3, reg: w2kk, asm: "VPCMPUQ", aux: "Int8", commutative: true, typ: "Mask", resultInArg0: false},
- {name: "VPCMPUQ256", argLength: 2, reg: w2k, asm: "VPCMPUQ", aux: "Int8", commutative: false, typ: "Mask", resultInArg0: false},
{name: "VPCMPUQMasked512", argLength: 3, reg: w2kk, asm: "VPCMPUQ", aux: "Int8", commutative: true, typ: "Mask", resultInArg0: false},
- {name: "VPCMPUQ512", argLength: 2, reg: w2k, asm: "VPCMPUQ", aux: "Int8", commutative: false, typ: "Mask", resultInArg0: false},
- {name: "VPCMPUBMasked128", argLength: 3, reg: w2kk, asm: "VPCMPUB", aux: "Int8", commutative: true, typ: "Mask", resultInArg0: false},
{name: "VGF2P8AFFINEQB128", argLength: 2, reg: w21, asm: "VGF2P8AFFINEQB", aux: "Int8", commutative: false, typ: "Vec128", resultInArg0: false},
- {name: "VGF2P8AFFINEINVQB128", argLength: 2, reg: w21, asm: "VGF2P8AFFINEINVQB", aux: "Int8", commutative: false, typ: "Vec128", resultInArg0: false},
- {name: "VGF2P8AFFINEINVQBMasked128", argLength: 3, reg: w2kw, asm: "VGF2P8AFFINEINVQB", aux: "Int8", commutative: false, typ: "Vec128", resultInArg0: false},
- {name: "VGF2P8AFFINEQBMasked128", argLength: 3, reg: w2kw, asm: "VGF2P8AFFINEQB", aux: "Int8", commutative: false, typ: "Vec128", resultInArg0: false},
- {name: "VPCMPUB128", argLength: 2, reg: w2k, asm: "VPCMPUB", aux: "Int8", commutative: false, typ: "Mask", resultInArg0: false},
- {name: "VPCMPUBMasked256", argLength: 3, reg: w2kk, asm: "VPCMPUB", aux: "Int8", commutative: true, typ: "Mask", resultInArg0: false},
{name: "VGF2P8AFFINEQB256", argLength: 2, reg: w21, asm: "VGF2P8AFFINEQB", aux: "Int8", commutative: false, typ: "Vec256", resultInArg0: false},
- {name: "VGF2P8AFFINEINVQB256", argLength: 2, reg: w21, asm: "VGF2P8AFFINEINVQB", aux: "Int8", commutative: false, typ: "Vec256", resultInArg0: false},
- {name: "VGF2P8AFFINEINVQBMasked256", argLength: 3, reg: w2kw, asm: "VGF2P8AFFINEINVQB", aux: "Int8", commutative: false, typ: "Vec256", resultInArg0: false},
- {name: "VGF2P8AFFINEQBMasked256", argLength: 3, reg: w2kw, asm: "VGF2P8AFFINEQB", aux: "Int8", commutative: false, typ: "Vec256", resultInArg0: false},
- {name: "VPCMPUB256", argLength: 2, reg: w2k, asm: "VPCMPUB", aux: "Int8", commutative: false, typ: "Mask", resultInArg0: false},
- {name: "VPCMPUBMasked512", argLength: 3, reg: w2kk, asm: "VPCMPUB", aux: "Int8", commutative: true, typ: "Mask", resultInArg0: false},
{name: "VGF2P8AFFINEQB512", argLength: 2, reg: w21, asm: "VGF2P8AFFINEQB", aux: "Int8", commutative: false, typ: "Vec512", resultInArg0: false},
+ {name: "VGF2P8AFFINEINVQB128", argLength: 2, reg: w21, asm: "VGF2P8AFFINEINVQB", aux: "Int8", commutative: false, typ: "Vec128", resultInArg0: false},
+ {name: "VGF2P8AFFINEINVQB256", argLength: 2, reg: w21, asm: "VGF2P8AFFINEINVQB", aux: "Int8", commutative: false, typ: "Vec256", resultInArg0: false},
{name: "VGF2P8AFFINEINVQB512", argLength: 2, reg: w21, asm: "VGF2P8AFFINEINVQB", aux: "Int8", commutative: false, typ: "Vec512", resultInArg0: false},
+ {name: "VGF2P8AFFINEINVQBMasked128", argLength: 3, reg: w2kw, asm: "VGF2P8AFFINEINVQB", aux: "Int8", commutative: false, typ: "Vec128", resultInArg0: false},
+ {name: "VGF2P8AFFINEINVQBMasked256", argLength: 3, reg: w2kw, asm: "VGF2P8AFFINEINVQB", aux: "Int8", commutative: false, typ: "Vec256", resultInArg0: false},
{name: "VGF2P8AFFINEINVQBMasked512", argLength: 3, reg: w2kw, asm: "VGF2P8AFFINEINVQB", aux: "Int8", commutative: false, typ: "Vec512", resultInArg0: false},
+ {name: "VGF2P8AFFINEQBMasked128", argLength: 3, reg: w2kw, asm: "VGF2P8AFFINEQB", aux: "Int8", commutative: false, typ: "Vec128", resultInArg0: false},
+ {name: "VGF2P8AFFINEQBMasked256", argLength: 3, reg: w2kw, asm: "VGF2P8AFFINEQB", aux: "Int8", commutative: false, typ: "Vec256", resultInArg0: false},
{name: "VGF2P8AFFINEQBMasked512", argLength: 3, reg: w2kw, asm: "VGF2P8AFFINEQB", aux: "Int8", commutative: false, typ: "Vec512", resultInArg0: false},
+ {name: "VEXTRACTF128128", argLength: 1, reg: v11, asm: "VEXTRACTF128", aux: "Int8", commutative: false, typ: "Vec128", resultInArg0: false},
+ {name: "VEXTRACTI128128", argLength: 1, reg: v11, asm: "VEXTRACTI128", aux: "Int8", commutative: false, typ: "Vec128", resultInArg0: false},
+ {name: "VPEXTRB128", argLength: 1, reg: wgp, asm: "VPEXTRB", aux: "Int8", commutative: false, typ: "int8", resultInArg0: false},
+ {name: "VPEXTRW128", argLength: 1, reg: wgp, asm: "VPEXTRW", aux: "Int8", commutative: false, typ: "int16", resultInArg0: false},
+ {name: "VPEXTRD128", argLength: 1, reg: vgp, asm: "VPEXTRD", aux: "Int8", commutative: false, typ: "int32", resultInArg0: false},
+ {name: "VPEXTRQ128", argLength: 1, reg: vgp, asm: "VPEXTRQ", aux: "Int8", commutative: false, typ: "int64", resultInArg0: false},
+ {name: "VPCMPUB128", argLength: 2, reg: w2k, asm: "VPCMPUB", aux: "Int8", commutative: false, typ: "Mask", resultInArg0: false},
+ {name: "VPCMPUB256", argLength: 2, reg: w2k, asm: "VPCMPUB", aux: "Int8", commutative: false, typ: "Mask", resultInArg0: false},
{name: "VPCMPUB512", argLength: 2, reg: w2k, asm: "VPCMPUB", aux: "Int8", commutative: false, typ: "Mask", resultInArg0: false},
+ {name: "VPCMPUW128", argLength: 2, reg: w2k, asm: "VPCMPUW", aux: "Int8", commutative: false, typ: "Mask", resultInArg0: false},
+ {name: "VPCMPUW256", argLength: 2, reg: w2k, asm: "VPCMPUW", aux: "Int8", commutative: false, typ: "Mask", resultInArg0: false},
+ {name: "VPCMPUW512", argLength: 2, reg: w2k, asm: "VPCMPUW", aux: "Int8", commutative: false, typ: "Mask", resultInArg0: false},
+ {name: "VPCMPUD128", argLength: 2, reg: w2k, asm: "VPCMPUD", aux: "Int8", commutative: false, typ: "Mask", resultInArg0: false},
+ {name: "VPCMPUD256", argLength: 2, reg: w2k, asm: "VPCMPUD", aux: "Int8", commutative: false, typ: "Mask", resultInArg0: false},
+ {name: "VPCMPUD512", argLength: 2, reg: w2k, asm: "VPCMPUD", aux: "Int8", commutative: false, typ: "Mask", resultInArg0: false},
+ {name: "VPCMPUQ128", argLength: 2, reg: w2k, asm: "VPCMPUQ", aux: "Int8", commutative: false, typ: "Mask", resultInArg0: false},
+ {name: "VPCMPUQ256", argLength: 2, reg: w2k, asm: "VPCMPUQ", aux: "Int8", commutative: false, typ: "Mask", resultInArg0: false},
+ {name: "VPCMPUQ512", argLength: 2, reg: w2k, asm: "VPCMPUQ", aux: "Int8", commutative: false, typ: "Mask", resultInArg0: false},
+ {name: "VPCMPB128", argLength: 2, reg: w2k, asm: "VPCMPB", aux: "Int8", commutative: false, typ: "Mask", resultInArg0: false},
+ {name: "VPCMPB256", argLength: 2, reg: w2k, asm: "VPCMPB", aux: "Int8", commutative: false, typ: "Mask", resultInArg0: false},
+ {name: "VPCMPB512", argLength: 2, reg: w2k, asm: "VPCMPB", aux: "Int8", commutative: false, typ: "Mask", resultInArg0: false},
+ {name: "VPCMPW128", argLength: 2, reg: w2k, asm: "VPCMPW", aux: "Int8", commutative: false, typ: "Mask", resultInArg0: false},
+ {name: "VPCMPW256", argLength: 2, reg: w2k, asm: "VPCMPW", aux: "Int8", commutative: false, typ: "Mask", resultInArg0: false},
+ {name: "VPCMPW512", argLength: 2, reg: w2k, asm: "VPCMPW", aux: "Int8", commutative: false, typ: "Mask", resultInArg0: false},
+ {name: "VPCMPD128", argLength: 2, reg: w2k, asm: "VPCMPD", aux: "Int8", commutative: false, typ: "Mask", resultInArg0: false},
+ {name: "VPCMPD256", argLength: 2, reg: w2k, asm: "VPCMPD", aux: "Int8", commutative: false, typ: "Mask", resultInArg0: false},
+ {name: "VPCMPD512", argLength: 2, reg: w2k, asm: "VPCMPD", aux: "Int8", commutative: false, typ: "Mask", resultInArg0: false},
+ {name: "VPCMPQ128", argLength: 2, reg: w2k, asm: "VPCMPQ", aux: "Int8", commutative: false, typ: "Mask", resultInArg0: false},
+ {name: "VPCMPQ256", argLength: 2, reg: w2k, asm: "VPCMPQ", aux: "Int8", commutative: false, typ: "Mask", resultInArg0: false},
+ {name: "VPCMPQ512", argLength: 2, reg: w2k, asm: "VPCMPQ", aux: "Int8", commutative: false, typ: "Mask", resultInArg0: false},
+ {name: "VPROLD128", argLength: 1, reg: w11, asm: "VPROLD", aux: "Int8", commutative: false, typ: "Vec128", resultInArg0: false},
+ {name: "VPROLD256", argLength: 1, reg: w11, asm: "VPROLD", aux: "Int8", commutative: false, typ: "Vec256", resultInArg0: false},
+ {name: "VPROLD512", argLength: 1, reg: w11, asm: "VPROLD", aux: "Int8", commutative: false, typ: "Vec512", resultInArg0: false},
+ {name: "VPROLQ128", argLength: 1, reg: w11, asm: "VPROLQ", aux: "Int8", commutative: false, typ: "Vec128", resultInArg0: false},
+ {name: "VPROLQ256", argLength: 1, reg: w11, asm: "VPROLQ", aux: "Int8", commutative: false, typ: "Vec256", resultInArg0: false},
+ {name: "VPROLQ512", argLength: 1, reg: w11, asm: "VPROLQ", aux: "Int8", commutative: false, typ: "Vec512", resultInArg0: false},
+ {name: "VPROLDMasked128", argLength: 2, reg: wkw, asm: "VPROLD", aux: "Int8", commutative: false, typ: "Vec128", resultInArg0: false},
+ {name: "VPROLDMasked256", argLength: 2, reg: wkw, asm: "VPROLD", aux: "Int8", commutative: false, typ: "Vec256", resultInArg0: false},
+ {name: "VPROLDMasked512", argLength: 2, reg: wkw, asm: "VPROLD", aux: "Int8", commutative: false, typ: "Vec512", resultInArg0: false},
+ {name: "VPROLQMasked128", argLength: 2, reg: wkw, asm: "VPROLQ", aux: "Int8", commutative: false, typ: "Vec128", resultInArg0: false},
+ {name: "VPROLQMasked256", argLength: 2, reg: wkw, asm: "VPROLQ", aux: "Int8", commutative: false, typ: "Vec256", resultInArg0: false},
+ {name: "VPROLQMasked512", argLength: 2, reg: wkw, asm: "VPROLQ", aux: "Int8", commutative: false, typ: "Vec512", resultInArg0: false},
+ {name: "VPRORD128", argLength: 1, reg: w11, asm: "VPRORD", aux: "Int8", commutative: false, typ: "Vec128", resultInArg0: false},
+ {name: "VPRORD256", argLength: 1, reg: w11, asm: "VPRORD", aux: "Int8", commutative: false, typ: "Vec256", resultInArg0: false},
+ {name: "VPRORD512", argLength: 1, reg: w11, asm: "VPRORD", aux: "Int8", commutative: false, typ: "Vec512", resultInArg0: false},
+ {name: "VPRORQ128", argLength: 1, reg: w11, asm: "VPRORQ", aux: "Int8", commutative: false, typ: "Vec128", resultInArg0: false},
+ {name: "VPRORQ256", argLength: 1, reg: w11, asm: "VPRORQ", aux: "Int8", commutative: false, typ: "Vec256", resultInArg0: false},
+ {name: "VPRORQ512", argLength: 1, reg: w11, asm: "VPRORQ", aux: "Int8", commutative: false, typ: "Vec512", resultInArg0: false},
+ {name: "VPRORDMasked128", argLength: 2, reg: wkw, asm: "VPRORD", aux: "Int8", commutative: false, typ: "Vec128", resultInArg0: false},
+ {name: "VPRORDMasked256", argLength: 2, reg: wkw, asm: "VPRORD", aux: "Int8", commutative: false, typ: "Vec256", resultInArg0: false},
+ {name: "VPRORDMasked512", argLength: 2, reg: wkw, asm: "VPRORD", aux: "Int8", commutative: false, typ: "Vec512", resultInArg0: false},
+ {name: "VPRORQMasked128", argLength: 2, reg: wkw, asm: "VPRORQ", aux: "Int8", commutative: false, typ: "Vec128", resultInArg0: false},
+ {name: "VPRORQMasked256", argLength: 2, reg: wkw, asm: "VPRORQ", aux: "Int8", commutative: false, typ: "Vec256", resultInArg0: false},
+ {name: "VPRORQMasked512", argLength: 2, reg: wkw, asm: "VPRORQ", aux: "Int8", commutative: false, typ: "Vec512", resultInArg0: false},
+ {name: "VINSERTF128256", argLength: 2, reg: v21, asm: "VINSERTF128", aux: "Int8", commutative: false, typ: "Vec256", resultInArg0: false},
+ {name: "VINSERTI128256", argLength: 2, reg: v21, asm: "VINSERTI128", aux: "Int8", commutative: false, typ: "Vec256", resultInArg0: false},
+ {name: "VPINSRB128", argLength: 2, reg: vgpv, asm: "VPINSRB", aux: "Int8", commutative: false, typ: "Vec128", resultInArg0: false},
+ {name: "VPINSRW128", argLength: 2, reg: vgpv, asm: "VPINSRW", aux: "Int8", commutative: false, typ: "Vec128", resultInArg0: false},
+ {name: "VPINSRD128", argLength: 2, reg: vgpv, asm: "VPINSRD", aux: "Int8", commutative: false, typ: "Vec128", resultInArg0: false},
+ {name: "VPINSRQ128", argLength: 2, reg: vgpv, asm: "VPINSRQ", aux: "Int8", commutative: false, typ: "Vec128", resultInArg0: false},
+ {name: "VPSHLDW128", argLength: 2, reg: w21, asm: "VPSHLDW", aux: "Int8", commutative: false, typ: "Vec128", resultInArg0: false},
+ {name: "VPSHLDW256", argLength: 2, reg: w21, asm: "VPSHLDW", aux: "Int8", commutative: false, typ: "Vec256", resultInArg0: false},
+ {name: "VPSHLDW512", argLength: 2, reg: w21, asm: "VPSHLDW", aux: "Int8", commutative: false, typ: "Vec512", resultInArg0: false},
+ {name: "VPSHLDD128", argLength: 2, reg: w21, asm: "VPSHLDD", aux: "Int8", commutative: false, typ: "Vec128", resultInArg0: false},
+ {name: "VPSHLDD256", argLength: 2, reg: w21, asm: "VPSHLDD", aux: "Int8", commutative: false, typ: "Vec256", resultInArg0: false},
+ {name: "VPSHLDD512", argLength: 2, reg: w21, asm: "VPSHLDD", aux: "Int8", commutative: false, typ: "Vec512", resultInArg0: false},
+ {name: "VPSHLDQ128", argLength: 2, reg: w21, asm: "VPSHLDQ", aux: "Int8", commutative: false, typ: "Vec128", resultInArg0: false},
+ {name: "VPSHLDQ256", argLength: 2, reg: w21, asm: "VPSHLDQ", aux: "Int8", commutative: false, typ: "Vec256", resultInArg0: false},
+ {name: "VPSHLDQ512", argLength: 2, reg: w21, asm: "VPSHLDQ", aux: "Int8", commutative: false, typ: "Vec512", resultInArg0: false},
+ {name: "VPSHLDWMasked128", argLength: 3, reg: w2kw, asm: "VPSHLDW", aux: "Int8", commutative: false, typ: "Vec128", resultInArg0: false},
+ {name: "VPSHLDWMasked256", argLength: 3, reg: w2kw, asm: "VPSHLDW", aux: "Int8", commutative: false, typ: "Vec256", resultInArg0: false},
+ {name: "VPSHLDWMasked512", argLength: 3, reg: w2kw, asm: "VPSHLDW", aux: "Int8", commutative: false, typ: "Vec512", resultInArg0: false},
+ {name: "VPSHLDDMasked128", argLength: 3, reg: w2kw, asm: "VPSHLDD", aux: "Int8", commutative: false, typ: "Vec128", resultInArg0: false},
+ {name: "VPSHLDDMasked256", argLength: 3, reg: w2kw, asm: "VPSHLDD", aux: "Int8", commutative: false, typ: "Vec256", resultInArg0: false},
+ {name: "VPSHLDDMasked512", argLength: 3, reg: w2kw, asm: "VPSHLDD", aux: "Int8", commutative: false, typ: "Vec512", resultInArg0: false},
+ {name: "VPSHLDQMasked128", argLength: 3, reg: w2kw, asm: "VPSHLDQ", aux: "Int8", commutative: false, typ: "Vec128", resultInArg0: false},
+ {name: "VPSHLDQMasked256", argLength: 3, reg: w2kw, asm: "VPSHLDQ", aux: "Int8", commutative: false, typ: "Vec256", resultInArg0: false},
+ {name: "VPSHLDQMasked512", argLength: 3, reg: w2kw, asm: "VPSHLDQ", aux: "Int8", commutative: false, typ: "Vec512", resultInArg0: false},
+ {name: "VPSHRDW128", argLength: 2, reg: w21, asm: "VPSHRDW", aux: "Int8", commutative: false, typ: "Vec128", resultInArg0: false},
+ {name: "VPSHRDW256", argLength: 2, reg: w21, asm: "VPSHRDW", aux: "Int8", commutative: false, typ: "Vec256", resultInArg0: false},
+ {name: "VPSHRDW512", argLength: 2, reg: w21, asm: "VPSHRDW", aux: "Int8", commutative: false, typ: "Vec512", resultInArg0: false},
+ {name: "VPSHRDD128", argLength: 2, reg: w21, asm: "VPSHRDD", aux: "Int8", commutative: false, typ: "Vec128", resultInArg0: false},
+ {name: "VPSHRDD256", argLength: 2, reg: w21, asm: "VPSHRDD", aux: "Int8", commutative: false, typ: "Vec256", resultInArg0: false},
+ {name: "VPSHRDD512", argLength: 2, reg: w21, asm: "VPSHRDD", aux: "Int8", commutative: false, typ: "Vec512", resultInArg0: false},
+ {name: "VPSHRDQ128", argLength: 2, reg: w21, asm: "VPSHRDQ", aux: "Int8", commutative: false, typ: "Vec128", resultInArg0: false},
+ {name: "VPSHRDQ256", argLength: 2, reg: w21, asm: "VPSHRDQ", aux: "Int8", commutative: false, typ: "Vec256", resultInArg0: false},
+ {name: "VPSHRDQ512", argLength: 2, reg: w21, asm: "VPSHRDQ", aux: "Int8", commutative: false, typ: "Vec512", resultInArg0: false},
+ {name: "VPSHRDWMasked128", argLength: 3, reg: w2kw, asm: "VPSHRDW", aux: "Int8", commutative: false, typ: "Vec128", resultInArg0: false},
+ {name: "VPSHRDWMasked256", argLength: 3, reg: w2kw, asm: "VPSHRDW", aux: "Int8", commutative: false, typ: "Vec256", resultInArg0: false},
+ {name: "VPSHRDWMasked512", argLength: 3, reg: w2kw, asm: "VPSHRDW", aux: "Int8", commutative: false, typ: "Vec512", resultInArg0: false},
+ {name: "VPSHRDDMasked128", argLength: 3, reg: w2kw, asm: "VPSHRDD", aux: "Int8", commutative: false, typ: "Vec128", resultInArg0: false},
+ {name: "VPSHRDDMasked256", argLength: 3, reg: w2kw, asm: "VPSHRDD", aux: "Int8", commutative: false, typ: "Vec256", resultInArg0: false},
+ {name: "VPSHRDDMasked512", argLength: 3, reg: w2kw, asm: "VPSHRDD", aux: "Int8", commutative: false, typ: "Vec512", resultInArg0: false},
+ {name: "VPSHRDQMasked128", argLength: 3, reg: w2kw, asm: "VPSHRDQ", aux: "Int8", commutative: false, typ: "Vec128", resultInArg0: false},
+ {name: "VPSHRDQMasked256", argLength: 3, reg: w2kw, asm: "VPSHRDQ", aux: "Int8", commutative: false, typ: "Vec256", resultInArg0: false},
+ {name: "VPSHRDQMasked512", argLength: 3, reg: w2kw, asm: "VPSHRDQ", aux: "Int8", commutative: false, typ: "Vec512", resultInArg0: false},
}
}
func simdGenericOps() []opData {
return []opData{
+ {name: "AbsoluteInt8x16", argLength: 1, commutative: false},
+ {name: "AbsoluteInt8x32", argLength: 1, commutative: false},
+ {name: "AbsoluteInt8x64", argLength: 1, commutative: false},
+ {name: "AbsoluteInt16x8", argLength: 1, commutative: false},
+ {name: "AbsoluteInt16x16", argLength: 1, commutative: false},
+ {name: "AbsoluteInt16x32", argLength: 1, commutative: false},
+ {name: "AbsoluteInt32x4", argLength: 1, commutative: false},
+ {name: "AbsoluteInt32x8", argLength: 1, commutative: false},
+ {name: "AbsoluteInt32x16", argLength: 1, commutative: false},
+ {name: "AbsoluteInt64x2", argLength: 1, commutative: false},
+ {name: "AbsoluteInt64x4", argLength: 1, commutative: false},
+ {name: "AbsoluteInt64x8", argLength: 1, commutative: false},
+ {name: "AbsoluteMaskedInt8x16", argLength: 2, commutative: false},
+ {name: "AbsoluteMaskedInt8x32", argLength: 2, commutative: false},
+ {name: "AbsoluteMaskedInt8x64", argLength: 2, commutative: false},
+ {name: "AbsoluteMaskedInt16x8", argLength: 2, commutative: false},
+ {name: "AbsoluteMaskedInt16x16", argLength: 2, commutative: false},
+ {name: "AbsoluteMaskedInt16x32", argLength: 2, commutative: false},
+ {name: "AbsoluteMaskedInt32x4", argLength: 2, commutative: false},
+ {name: "AbsoluteMaskedInt32x8", argLength: 2, commutative: false},
+ {name: "AbsoluteMaskedInt32x16", argLength: 2, commutative: false},
+ {name: "AbsoluteMaskedInt64x2", argLength: 2, commutative: false},
+ {name: "AbsoluteMaskedInt64x4", argLength: 2, commutative: false},
+ {name: "AbsoluteMaskedInt64x8", argLength: 2, commutative: false},
+ {name: "AddFloat32x4", argLength: 2, commutative: true},
+ {name: "AddFloat32x8", argLength: 2, commutative: true},
{name: "AddFloat32x16", argLength: 2, commutative: true},
+ {name: "AddFloat64x2", argLength: 2, commutative: true},
+ {name: "AddFloat64x4", argLength: 2, commutative: true},
+ {name: "AddFloat64x8", argLength: 2, commutative: true},
+ {name: "AddInt8x16", argLength: 2, commutative: true},
+ {name: "AddInt8x32", argLength: 2, commutative: true},
+ {name: "AddInt8x64", argLength: 2, commutative: true},
+ {name: "AddInt16x8", argLength: 2, commutative: true},
+ {name: "AddInt16x16", argLength: 2, commutative: true},
+ {name: "AddInt16x32", argLength: 2, commutative: true},
+ {name: "AddInt32x4", argLength: 2, commutative: true},
+ {name: "AddInt32x8", argLength: 2, commutative: true},
+ {name: "AddInt32x16", argLength: 2, commutative: true},
+ {name: "AddInt64x2", argLength: 2, commutative: true},
+ {name: "AddInt64x4", argLength: 2, commutative: true},
+ {name: "AddInt64x8", argLength: 2, commutative: true},
+ {name: "AddMaskedFloat32x4", argLength: 3, commutative: true},
+ {name: "AddMaskedFloat32x8", argLength: 3, commutative: true},
{name: "AddMaskedFloat32x16", argLength: 3, commutative: true},
+ {name: "AddMaskedFloat64x2", argLength: 3, commutative: true},
+ {name: "AddMaskedFloat64x4", argLength: 3, commutative: true},
+ {name: "AddMaskedFloat64x8", argLength: 3, commutative: true},
+ {name: "AddMaskedInt8x16", argLength: 3, commutative: true},
+ {name: "AddMaskedInt8x32", argLength: 3, commutative: true},
+ {name: "AddMaskedInt8x64", argLength: 3, commutative: true},
+ {name: "AddMaskedInt16x8", argLength: 3, commutative: true},
+ {name: "AddMaskedInt16x16", argLength: 3, commutative: true},
+ {name: "AddMaskedInt16x32", argLength: 3, commutative: true},
+ {name: "AddMaskedInt32x4", argLength: 3, commutative: true},
+ {name: "AddMaskedInt32x8", argLength: 3, commutative: true},
+ {name: "AddMaskedInt32x16", argLength: 3, commutative: true},
+ {name: "AddMaskedInt64x2", argLength: 3, commutative: true},
+ {name: "AddMaskedInt64x4", argLength: 3, commutative: true},
+ {name: "AddMaskedInt64x8", argLength: 3, commutative: true},
+ {name: "AddMaskedUint8x16", argLength: 3, commutative: true},
+ {name: "AddMaskedUint8x32", argLength: 3, commutative: true},
+ {name: "AddMaskedUint8x64", argLength: 3, commutative: true},
+ {name: "AddMaskedUint16x8", argLength: 3, commutative: true},
+ {name: "AddMaskedUint16x16", argLength: 3, commutative: true},
+ {name: "AddMaskedUint16x32", argLength: 3, commutative: true},
+ {name: "AddMaskedUint32x4", argLength: 3, commutative: true},
+ {name: "AddMaskedUint32x8", argLength: 3, commutative: true},
+ {name: "AddMaskedUint32x16", argLength: 3, commutative: true},
+ {name: "AddMaskedUint64x2", argLength: 3, commutative: true},
+ {name: "AddMaskedUint64x4", argLength: 3, commutative: true},
+ {name: "AddMaskedUint64x8", argLength: 3, commutative: true},
+ {name: "AddSubFloat32x4", argLength: 2, commutative: false},
+ {name: "AddSubFloat32x8", argLength: 2, commutative: false},
+ {name: "AddSubFloat64x2", argLength: 2, commutative: false},
+ {name: "AddSubFloat64x4", argLength: 2, commutative: false},
+ {name: "AddUint8x16", argLength: 2, commutative: true},
+ {name: "AddUint8x32", argLength: 2, commutative: true},
+ {name: "AddUint8x64", argLength: 2, commutative: true},
+ {name: "AddUint16x8", argLength: 2, commutative: true},
+ {name: "AddUint16x16", argLength: 2, commutative: true},
+ {name: "AddUint16x32", argLength: 2, commutative: true},
+ {name: "AddUint32x4", argLength: 2, commutative: true},
+ {name: "AddUint32x8", argLength: 2, commutative: true},
+ {name: "AddUint32x16", argLength: 2, commutative: true},
+ {name: "AddUint64x2", argLength: 2, commutative: true},
+ {name: "AddUint64x4", argLength: 2, commutative: true},
+ {name: "AddUint64x8", argLength: 2, commutative: true},
+ {name: "AndInt8x16", argLength: 2, commutative: true},
+ {name: "AndInt8x32", argLength: 2, commutative: true},
+ {name: "AndInt16x8", argLength: 2, commutative: true},
+ {name: "AndInt16x16", argLength: 2, commutative: true},
+ {name: "AndInt32x4", argLength: 2, commutative: true},
+ {name: "AndInt32x8", argLength: 2, commutative: true},
+ {name: "AndInt32x16", argLength: 2, commutative: true},
+ {name: "AndInt64x2", argLength: 2, commutative: true},
+ {name: "AndInt64x4", argLength: 2, commutative: true},
+ {name: "AndInt64x8", argLength: 2, commutative: true},
+ {name: "AndMaskedInt32x4", argLength: 3, commutative: true},
+ {name: "AndMaskedInt32x8", argLength: 3, commutative: true},
+ {name: "AndMaskedInt32x16", argLength: 3, commutative: true},
+ {name: "AndMaskedInt64x2", argLength: 3, commutative: true},
+ {name: "AndMaskedInt64x4", argLength: 3, commutative: true},
+ {name: "AndMaskedInt64x8", argLength: 3, commutative: true},
+ {name: "AndMaskedUint32x4", argLength: 3, commutative: true},
+ {name: "AndMaskedUint32x8", argLength: 3, commutative: true},
+ {name: "AndMaskedUint32x16", argLength: 3, commutative: true},
+ {name: "AndMaskedUint64x2", argLength: 3, commutative: true},
+ {name: "AndMaskedUint64x4", argLength: 3, commutative: true},
+ {name: "AndMaskedUint64x8", argLength: 3, commutative: true},
+ {name: "AndNotInt8x16", argLength: 2, commutative: false},
+ {name: "AndNotInt8x32", argLength: 2, commutative: false},
+ {name: "AndNotInt16x8", argLength: 2, commutative: false},
+ {name: "AndNotInt16x16", argLength: 2, commutative: false},
+ {name: "AndNotInt32x4", argLength: 2, commutative: false},
+ {name: "AndNotInt32x8", argLength: 2, commutative: false},
+ {name: "AndNotInt32x16", argLength: 2, commutative: false},
+ {name: "AndNotInt64x2", argLength: 2, commutative: false},
+ {name: "AndNotInt64x4", argLength: 2, commutative: false},
+ {name: "AndNotInt64x8", argLength: 2, commutative: false},
+ {name: "AndNotMaskedInt32x4", argLength: 3, commutative: false},
+ {name: "AndNotMaskedInt32x8", argLength: 3, commutative: false},
+ {name: "AndNotMaskedInt32x16", argLength: 3, commutative: false},
+ {name: "AndNotMaskedInt64x2", argLength: 3, commutative: false},
+ {name: "AndNotMaskedInt64x4", argLength: 3, commutative: false},
+ {name: "AndNotMaskedInt64x8", argLength: 3, commutative: false},
+ {name: "AndNotMaskedUint32x4", argLength: 3, commutative: false},
+ {name: "AndNotMaskedUint32x8", argLength: 3, commutative: false},
+ {name: "AndNotMaskedUint32x16", argLength: 3, commutative: false},
+ {name: "AndNotMaskedUint64x2", argLength: 3, commutative: false},
+ {name: "AndNotMaskedUint64x4", argLength: 3, commutative: false},
+ {name: "AndNotMaskedUint64x8", argLength: 3, commutative: false},
+ {name: "AndNotUint8x16", argLength: 2, commutative: false},
+ {name: "AndNotUint8x32", argLength: 2, commutative: false},
+ {name: "AndNotUint16x8", argLength: 2, commutative: false},
+ {name: "AndNotUint16x16", argLength: 2, commutative: false},
+ {name: "AndNotUint32x4", argLength: 2, commutative: false},
+ {name: "AndNotUint32x8", argLength: 2, commutative: false},
+ {name: "AndNotUint32x16", argLength: 2, commutative: false},
+ {name: "AndNotUint64x2", argLength: 2, commutative: false},
+ {name: "AndNotUint64x4", argLength: 2, commutative: false},
+ {name: "AndNotUint64x8", argLength: 2, commutative: false},
+ {name: "AndUint8x16", argLength: 2, commutative: true},
+ {name: "AndUint8x32", argLength: 2, commutative: true},
+ {name: "AndUint16x8", argLength: 2, commutative: true},
+ {name: "AndUint16x16", argLength: 2, commutative: true},
+ {name: "AndUint32x4", argLength: 2, commutative: true},
+ {name: "AndUint32x8", argLength: 2, commutative: true},
+ {name: "AndUint32x16", argLength: 2, commutative: true},
+ {name: "AndUint64x2", argLength: 2, commutative: true},
+ {name: "AndUint64x4", argLength: 2, commutative: true},
+ {name: "AndUint64x8", argLength: 2, commutative: true},
+ {name: "ApproximateReciprocalFloat32x4", argLength: 1, commutative: false},
+ {name: "ApproximateReciprocalFloat32x8", argLength: 1, commutative: false},
{name: "ApproximateReciprocalFloat32x16", argLength: 1, commutative: false},
+ {name: "ApproximateReciprocalFloat64x2", argLength: 1, commutative: false},
+ {name: "ApproximateReciprocalFloat64x4", argLength: 1, commutative: false},
+ {name: "ApproximateReciprocalFloat64x8", argLength: 1, commutative: false},
+ {name: "ApproximateReciprocalMaskedFloat32x4", argLength: 2, commutative: false},
+ {name: "ApproximateReciprocalMaskedFloat32x8", argLength: 2, commutative: false},
{name: "ApproximateReciprocalMaskedFloat32x16", argLength: 2, commutative: false},
+ {name: "ApproximateReciprocalMaskedFloat64x2", argLength: 2, commutative: false},
+ {name: "ApproximateReciprocalMaskedFloat64x4", argLength: 2, commutative: false},
+ {name: "ApproximateReciprocalMaskedFloat64x8", argLength: 2, commutative: false},
+ {name: "ApproximateReciprocalOfSqrtFloat32x4", argLength: 1, commutative: false},
+ {name: "ApproximateReciprocalOfSqrtFloat32x8", argLength: 1, commutative: false},
{name: "ApproximateReciprocalOfSqrtFloat32x16", argLength: 1, commutative: false},
+ {name: "ApproximateReciprocalOfSqrtFloat64x2", argLength: 1, commutative: false},
+ {name: "ApproximateReciprocalOfSqrtFloat64x4", argLength: 1, commutative: false},
+ {name: "ApproximateReciprocalOfSqrtFloat64x8", argLength: 1, commutative: false},
+ {name: "ApproximateReciprocalOfSqrtMaskedFloat32x4", argLength: 2, commutative: false},
+ {name: "ApproximateReciprocalOfSqrtMaskedFloat32x8", argLength: 2, commutative: false},
{name: "ApproximateReciprocalOfSqrtMaskedFloat32x16", argLength: 2, commutative: false},
+ {name: "ApproximateReciprocalOfSqrtMaskedFloat64x2", argLength: 2, commutative: false},
+ {name: "ApproximateReciprocalOfSqrtMaskedFloat64x4", argLength: 2, commutative: false},
+ {name: "ApproximateReciprocalOfSqrtMaskedFloat64x8", argLength: 2, commutative: false},
+ {name: "AverageMaskedUint8x16", argLength: 3, commutative: true},
+ {name: "AverageMaskedUint8x32", argLength: 3, commutative: true},
+ {name: "AverageMaskedUint8x64", argLength: 3, commutative: true},
+ {name: "AverageMaskedUint16x8", argLength: 3, commutative: true},
+ {name: "AverageMaskedUint16x16", argLength: 3, commutative: true},
+ {name: "AverageMaskedUint16x32", argLength: 3, commutative: true},
+ {name: "AverageUint8x16", argLength: 2, commutative: true},
+ {name: "AverageUint8x32", argLength: 2, commutative: true},
+ {name: "AverageUint8x64", argLength: 2, commutative: true},
+ {name: "AverageUint16x8", argLength: 2, commutative: true},
+ {name: "AverageUint16x16", argLength: 2, commutative: true},
+ {name: "AverageUint16x32", argLength: 2, commutative: true},
+ {name: "CeilFloat32x4", argLength: 1, commutative: false},
+ {name: "CeilFloat32x8", argLength: 1, commutative: false},
+ {name: "CeilFloat64x2", argLength: 1, commutative: false},
+ {name: "CeilFloat64x4", argLength: 1, commutative: false},
+ {name: "CompressFloat32x4", argLength: 2, commutative: false},
+ {name: "CompressFloat32x8", argLength: 2, commutative: false},
{name: "CompressFloat32x16", argLength: 2, commutative: false},
+ {name: "CompressFloat64x2", argLength: 2, commutative: false},
+ {name: "CompressFloat64x4", argLength: 2, commutative: false},
+ {name: "CompressFloat64x8", argLength: 2, commutative: false},
+ {name: "CompressInt8x16", argLength: 2, commutative: false},
+ {name: "CompressInt8x32", argLength: 2, commutative: false},
+ {name: "CompressInt8x64", argLength: 2, commutative: false},
+ {name: "CompressInt16x8", argLength: 2, commutative: false},
+ {name: "CompressInt16x16", argLength: 2, commutative: false},
+ {name: "CompressInt16x32", argLength: 2, commutative: false},
+ {name: "CompressInt32x4", argLength: 2, commutative: false},
+ {name: "CompressInt32x8", argLength: 2, commutative: false},
+ {name: "CompressInt32x16", argLength: 2, commutative: false},
+ {name: "CompressInt64x2", argLength: 2, commutative: false},
+ {name: "CompressInt64x4", argLength: 2, commutative: false},
+ {name: "CompressInt64x8", argLength: 2, commutative: false},
+ {name: "CompressUint8x16", argLength: 2, commutative: false},
+ {name: "CompressUint8x32", argLength: 2, commutative: false},
+ {name: "CompressUint8x64", argLength: 2, commutative: false},
+ {name: "CompressUint16x8", argLength: 2, commutative: false},
+ {name: "CompressUint16x16", argLength: 2, commutative: false},
+ {name: "CompressUint16x32", argLength: 2, commutative: false},
+ {name: "CompressUint32x4", argLength: 2, commutative: false},
+ {name: "CompressUint32x8", argLength: 2, commutative: false},
+ {name: "CompressUint32x16", argLength: 2, commutative: false},
+ {name: "CompressUint64x2", argLength: 2, commutative: false},
+ {name: "CompressUint64x4", argLength: 2, commutative: false},
+ {name: "CompressUint64x8", argLength: 2, commutative: false},
+ {name: "DivFloat32x4", argLength: 2, commutative: false},
+ {name: "DivFloat32x8", argLength: 2, commutative: false},
{name: "DivFloat32x16", argLength: 2, commutative: false},
+ {name: "DivFloat64x2", argLength: 2, commutative: false},
+ {name: "DivFloat64x4", argLength: 2, commutative: false},
+ {name: "DivFloat64x8", argLength: 2, commutative: false},
+ {name: "DivMaskedFloat32x4", argLength: 3, commutative: false},
+ {name: "DivMaskedFloat32x8", argLength: 3, commutative: false},
{name: "DivMaskedFloat32x16", argLength: 3, commutative: false},
+ {name: "DivMaskedFloat64x2", argLength: 3, commutative: false},
+ {name: "DivMaskedFloat64x4", argLength: 3, commutative: false},
+ {name: "DivMaskedFloat64x8", argLength: 3, commutative: false},
+ {name: "DotProdBroadcastFloat32x4", argLength: 2, commutative: true},
+ {name: "DotProdBroadcastFloat32x8", argLength: 2, commutative: true},
+ {name: "DotProdBroadcastFloat64x2", argLength: 2, commutative: true},
+ {name: "EqualFloat32x4", argLength: 2, commutative: true},
+ {name: "EqualFloat32x8", argLength: 2, commutative: true},
{name: "EqualFloat32x16", argLength: 2, commutative: true},
+ {name: "EqualFloat64x2", argLength: 2, commutative: true},
+ {name: "EqualFloat64x4", argLength: 2, commutative: true},
+ {name: "EqualFloat64x8", argLength: 2, commutative: true},
+ {name: "EqualInt8x16", argLength: 2, commutative: true},
+ {name: "EqualInt8x32", argLength: 2, commutative: true},
+ {name: "EqualInt8x64", argLength: 2, commutative: true},
+ {name: "EqualInt16x8", argLength: 2, commutative: true},
+ {name: "EqualInt16x16", argLength: 2, commutative: true},
+ {name: "EqualInt16x32", argLength: 2, commutative: true},
+ {name: "EqualInt32x4", argLength: 2, commutative: true},
+ {name: "EqualInt32x8", argLength: 2, commutative: true},
+ {name: "EqualInt32x16", argLength: 2, commutative: true},
+ {name: "EqualInt64x2", argLength: 2, commutative: true},
+ {name: "EqualInt64x4", argLength: 2, commutative: true},
+ {name: "EqualInt64x8", argLength: 2, commutative: true},
+ {name: "EqualMaskedFloat32x4", argLength: 3, commutative: true},
+ {name: "EqualMaskedFloat32x8", argLength: 3, commutative: true},
{name: "EqualMaskedFloat32x16", argLength: 3, commutative: true},
- {name: "FusedMultiplyAddFloat32x16", argLength: 3, commutative: false},
- {name: "FusedMultiplyAddMaskedFloat32x16", argLength: 4, commutative: false},
- {name: "FusedMultiplyAddSubFloat32x16", argLength: 3, commutative: false},
- {name: "FusedMultiplyAddSubMaskedFloat32x16", argLength: 4, commutative: false},
- {name: "FusedMultiplySubAddFloat32x16", argLength: 3, commutative: false},
- {name: "FusedMultiplySubAddMaskedFloat32x16", argLength: 4, commutative: false},
- {name: "GreaterFloat32x16", argLength: 2, commutative: false},
- {name: "GreaterEqualFloat32x16", argLength: 2, commutative: false},
- {name: "GreaterEqualMaskedFloat32x16", argLength: 3, commutative: false},
- {name: "GreaterMaskedFloat32x16", argLength: 3, commutative: false},
- {name: "IsNanFloat32x16", argLength: 2, commutative: true},
- {name: "IsNanMaskedFloat32x16", argLength: 3, commutative: true},
- {name: "LessFloat32x16", argLength: 2, commutative: false},
- {name: "LessEqualFloat32x16", argLength: 2, commutative: false},
- {name: "LessEqualMaskedFloat32x16", argLength: 3, commutative: false},
- {name: "LessMaskedFloat32x16", argLength: 3, commutative: false},
- {name: "MaxFloat32x16", argLength: 2, commutative: true},
- {name: "MaxMaskedFloat32x16", argLength: 3, commutative: true},
- {name: "MinFloat32x16", argLength: 2, commutative: true},
- {name: "MinMaskedFloat32x16", argLength: 3, commutative: true},
- {name: "MulFloat32x16", argLength: 2, commutative: true},
- {name: "MulByPowOf2Float32x16", argLength: 2, commutative: false},
- {name: "MulByPowOf2MaskedFloat32x16", argLength: 3, commutative: false},
- {name: "MulMaskedFloat32x16", argLength: 3, commutative: true},
- {name: "NotEqualFloat32x16", argLength: 2, commutative: true},
- {name: "NotEqualMaskedFloat32x16", argLength: 3, commutative: true},
- {name: "SqrtFloat32x16", argLength: 1, commutative: false},
- {name: "SqrtMaskedFloat32x16", argLength: 2, commutative: false},
- {name: "SubFloat32x16", argLength: 2, commutative: false},
- {name: "SubMaskedFloat32x16", argLength: 3, commutative: false},
- {name: "AddFloat32x4", argLength: 2, commutative: true},
- {name: "AddMaskedFloat32x4", argLength: 3, commutative: true},
- {name: "AddSubFloat32x4", argLength: 2, commutative: false},
- {name: "ApproximateReciprocalFloat32x4", argLength: 1, commutative: false},
- {name: "ApproximateReciprocalMaskedFloat32x4", argLength: 2, commutative: false},
- {name: "ApproximateReciprocalOfSqrtFloat32x4", argLength: 1, commutative: false},
- {name: "ApproximateReciprocalOfSqrtMaskedFloat32x4", argLength: 2, commutative: false},
- {name: "CeilFloat32x4", argLength: 1, commutative: false},
- {name: "CompressFloat32x4", argLength: 2, commutative: false},
- {name: "DivFloat32x4", argLength: 2, commutative: false},
- {name: "DivMaskedFloat32x4", argLength: 3, commutative: false},
- {name: "DotProdBroadcastFloat32x4", argLength: 2, commutative: true},
- {name: "EqualFloat32x4", argLength: 2, commutative: true},
- {name: "EqualMaskedFloat32x4", argLength: 3, commutative: true},
+ {name: "EqualMaskedFloat64x2", argLength: 3, commutative: true},
+ {name: "EqualMaskedFloat64x4", argLength: 3, commutative: true},
+ {name: "EqualMaskedFloat64x8", argLength: 3, commutative: true},
+ {name: "EqualMaskedInt8x16", argLength: 3, commutative: true},
+ {name: "EqualMaskedInt8x32", argLength: 3, commutative: true},
+ {name: "EqualMaskedInt8x64", argLength: 3, commutative: true},
+ {name: "EqualMaskedInt16x8", argLength: 3, commutative: true},
+ {name: "EqualMaskedInt16x16", argLength: 3, commutative: true},
+ {name: "EqualMaskedInt16x32", argLength: 3, commutative: true},
+ {name: "EqualMaskedInt32x4", argLength: 3, commutative: true},
+ {name: "EqualMaskedInt32x8", argLength: 3, commutative: true},
+ {name: "EqualMaskedInt32x16", argLength: 3, commutative: true},
+ {name: "EqualMaskedInt64x2", argLength: 3, commutative: true},
+ {name: "EqualMaskedInt64x4", argLength: 3, commutative: true},
+ {name: "EqualMaskedInt64x8", argLength: 3, commutative: true},
+ {name: "EqualMaskedUint8x16", argLength: 3, commutative: true},
+ {name: "EqualMaskedUint8x32", argLength: 3, commutative: true},
+ {name: "EqualMaskedUint8x64", argLength: 3, commutative: true},
+ {name: "EqualMaskedUint16x8", argLength: 3, commutative: true},
+ {name: "EqualMaskedUint16x16", argLength: 3, commutative: true},
+ {name: "EqualMaskedUint16x32", argLength: 3, commutative: true},
+ {name: "EqualMaskedUint32x4", argLength: 3, commutative: true},
+ {name: "EqualMaskedUint32x8", argLength: 3, commutative: true},
+ {name: "EqualMaskedUint32x16", argLength: 3, commutative: true},
+ {name: "EqualMaskedUint64x2", argLength: 3, commutative: true},
+ {name: "EqualMaskedUint64x4", argLength: 3, commutative: true},
+ {name: "EqualMaskedUint64x8", argLength: 3, commutative: true},
+ {name: "EqualUint8x16", argLength: 2, commutative: true},
+ {name: "EqualUint8x32", argLength: 2, commutative: true},
+ {name: "EqualUint8x64", argLength: 2, commutative: true},
+ {name: "EqualUint16x8", argLength: 2, commutative: true},
+ {name: "EqualUint16x16", argLength: 2, commutative: true},
+ {name: "EqualUint16x32", argLength: 2, commutative: true},
+ {name: "EqualUint32x4", argLength: 2, commutative: true},
+ {name: "EqualUint32x8", argLength: 2, commutative: true},
+ {name: "EqualUint32x16", argLength: 2, commutative: true},
+ {name: "EqualUint64x2", argLength: 2, commutative: true},
+ {name: "EqualUint64x4", argLength: 2, commutative: true},
+ {name: "EqualUint64x8", argLength: 2, commutative: true},
{name: "FloorFloat32x4", argLength: 1, commutative: false},
+ {name: "FloorFloat32x8", argLength: 1, commutative: false},
+ {name: "FloorFloat64x2", argLength: 1, commutative: false},
+ {name: "FloorFloat64x4", argLength: 1, commutative: false},
{name: "FusedMultiplyAddFloat32x4", argLength: 3, commutative: false},
+ {name: "FusedMultiplyAddFloat32x8", argLength: 3, commutative: false},
+ {name: "FusedMultiplyAddFloat32x16", argLength: 3, commutative: false},
+ {name: "FusedMultiplyAddFloat64x2", argLength: 3, commutative: false},
+ {name: "FusedMultiplyAddFloat64x4", argLength: 3, commutative: false},
+ {name: "FusedMultiplyAddFloat64x8", argLength: 3, commutative: false},
{name: "FusedMultiplyAddMaskedFloat32x4", argLength: 4, commutative: false},
+ {name: "FusedMultiplyAddMaskedFloat32x8", argLength: 4, commutative: false},
+ {name: "FusedMultiplyAddMaskedFloat32x16", argLength: 4, commutative: false},
+ {name: "FusedMultiplyAddMaskedFloat64x2", argLength: 4, commutative: false},
+ {name: "FusedMultiplyAddMaskedFloat64x4", argLength: 4, commutative: false},
+ {name: "FusedMultiplyAddMaskedFloat64x8", argLength: 4, commutative: false},
{name: "FusedMultiplyAddSubFloat32x4", argLength: 3, commutative: false},
+ {name: "FusedMultiplyAddSubFloat32x8", argLength: 3, commutative: false},
+ {name: "FusedMultiplyAddSubFloat32x16", argLength: 3, commutative: false},
+ {name: "FusedMultiplyAddSubFloat64x2", argLength: 3, commutative: false},
+ {name: "FusedMultiplyAddSubFloat64x4", argLength: 3, commutative: false},
+ {name: "FusedMultiplyAddSubFloat64x8", argLength: 3, commutative: false},
{name: "FusedMultiplyAddSubMaskedFloat32x4", argLength: 4, commutative: false},
+ {name: "FusedMultiplyAddSubMaskedFloat32x8", argLength: 4, commutative: false},
+ {name: "FusedMultiplyAddSubMaskedFloat32x16", argLength: 4, commutative: false},
+ {name: "FusedMultiplyAddSubMaskedFloat64x2", argLength: 4, commutative: false},
+ {name: "FusedMultiplyAddSubMaskedFloat64x4", argLength: 4, commutative: false},
+ {name: "FusedMultiplyAddSubMaskedFloat64x8", argLength: 4, commutative: false},
{name: "FusedMultiplySubAddFloat32x4", argLength: 3, commutative: false},
+ {name: "FusedMultiplySubAddFloat32x8", argLength: 3, commutative: false},
+ {name: "FusedMultiplySubAddFloat32x16", argLength: 3, commutative: false},
+ {name: "FusedMultiplySubAddFloat64x2", argLength: 3, commutative: false},
+ {name: "FusedMultiplySubAddFloat64x4", argLength: 3, commutative: false},
+ {name: "FusedMultiplySubAddFloat64x8", argLength: 3, commutative: false},
{name: "FusedMultiplySubAddMaskedFloat32x4", argLength: 4, commutative: false},
- {name: "GreaterFloat32x4", argLength: 2, commutative: false},
+ {name: "FusedMultiplySubAddMaskedFloat32x8", argLength: 4, commutative: false},
+ {name: "FusedMultiplySubAddMaskedFloat32x16", argLength: 4, commutative: false},
+ {name: "FusedMultiplySubAddMaskedFloat64x2", argLength: 4, commutative: false},
+ {name: "FusedMultiplySubAddMaskedFloat64x4", argLength: 4, commutative: false},
+ {name: "FusedMultiplySubAddMaskedFloat64x8", argLength: 4, commutative: false},
+ {name: "GaloisFieldMulMaskedUint8x16", argLength: 3, commutative: false},
+ {name: "GaloisFieldMulMaskedUint8x32", argLength: 3, commutative: false},
+ {name: "GaloisFieldMulMaskedUint8x64", argLength: 3, commutative: false},
+ {name: "GaloisFieldMulUint8x16", argLength: 2, commutative: false},
+ {name: "GaloisFieldMulUint8x32", argLength: 2, commutative: false},
+ {name: "GaloisFieldMulUint8x64", argLength: 2, commutative: false},
{name: "GreaterEqualFloat32x4", argLength: 2, commutative: false},
+ {name: "GreaterEqualFloat32x8", argLength: 2, commutative: false},
+ {name: "GreaterEqualFloat32x16", argLength: 2, commutative: false},
+ {name: "GreaterEqualFloat64x2", argLength: 2, commutative: false},
+ {name: "GreaterEqualFloat64x4", argLength: 2, commutative: false},
+ {name: "GreaterEqualFloat64x8", argLength: 2, commutative: false},
+ {name: "GreaterEqualInt8x16", argLength: 2, commutative: false},
+ {name: "GreaterEqualInt8x32", argLength: 2, commutative: false},
+ {name: "GreaterEqualInt8x64", argLength: 2, commutative: false},
+ {name: "GreaterEqualInt16x8", argLength: 2, commutative: false},
+ {name: "GreaterEqualInt16x16", argLength: 2, commutative: false},
+ {name: "GreaterEqualInt16x32", argLength: 2, commutative: false},
+ {name: "GreaterEqualInt32x4", argLength: 2, commutative: false},
+ {name: "GreaterEqualInt32x8", argLength: 2, commutative: false},
+ {name: "GreaterEqualInt32x16", argLength: 2, commutative: false},
+ {name: "GreaterEqualInt64x2", argLength: 2, commutative: false},
+ {name: "GreaterEqualInt64x4", argLength: 2, commutative: false},
+ {name: "GreaterEqualInt64x8", argLength: 2, commutative: false},
{name: "GreaterEqualMaskedFloat32x4", argLength: 3, commutative: false},
+ {name: "GreaterEqualMaskedFloat32x8", argLength: 3, commutative: false},
+ {name: "GreaterEqualMaskedFloat32x16", argLength: 3, commutative: false},
+ {name: "GreaterEqualMaskedFloat64x2", argLength: 3, commutative: false},
+ {name: "GreaterEqualMaskedFloat64x4", argLength: 3, commutative: false},
+ {name: "GreaterEqualMaskedFloat64x8", argLength: 3, commutative: false},
+ {name: "GreaterEqualMaskedInt8x16", argLength: 3, commutative: false},
+ {name: "GreaterEqualMaskedInt8x32", argLength: 3, commutative: false},
+ {name: "GreaterEqualMaskedInt8x64", argLength: 3, commutative: false},
+ {name: "GreaterEqualMaskedInt16x8", argLength: 3, commutative: false},
+ {name: "GreaterEqualMaskedInt16x16", argLength: 3, commutative: false},
+ {name: "GreaterEqualMaskedInt16x32", argLength: 3, commutative: false},
+ {name: "GreaterEqualMaskedInt32x4", argLength: 3, commutative: false},
+ {name: "GreaterEqualMaskedInt32x8", argLength: 3, commutative: false},
+ {name: "GreaterEqualMaskedInt32x16", argLength: 3, commutative: false},
+ {name: "GreaterEqualMaskedInt64x2", argLength: 3, commutative: false},
+ {name: "GreaterEqualMaskedInt64x4", argLength: 3, commutative: false},
+ {name: "GreaterEqualMaskedInt64x8", argLength: 3, commutative: false},
+ {name: "GreaterEqualMaskedUint8x16", argLength: 3, commutative: false},
+ {name: "GreaterEqualMaskedUint8x32", argLength: 3, commutative: false},
+ {name: "GreaterEqualMaskedUint8x64", argLength: 3, commutative: false},
+ {name: "GreaterEqualMaskedUint16x8", argLength: 3, commutative: false},
+ {name: "GreaterEqualMaskedUint16x16", argLength: 3, commutative: false},
+ {name: "GreaterEqualMaskedUint16x32", argLength: 3, commutative: false},
+ {name: "GreaterEqualMaskedUint32x4", argLength: 3, commutative: false},
+ {name: "GreaterEqualMaskedUint32x8", argLength: 3, commutative: false},
+ {name: "GreaterEqualMaskedUint32x16", argLength: 3, commutative: false},
+ {name: "GreaterEqualMaskedUint64x2", argLength: 3, commutative: false},
+ {name: "GreaterEqualMaskedUint64x4", argLength: 3, commutative: false},
+ {name: "GreaterEqualMaskedUint64x8", argLength: 3, commutative: false},
+ {name: "GreaterEqualUint8x16", argLength: 2, commutative: false},
+ {name: "GreaterEqualUint8x32", argLength: 2, commutative: false},
+ {name: "GreaterEqualUint8x64", argLength: 2, commutative: false},
+ {name: "GreaterEqualUint16x8", argLength: 2, commutative: false},
+ {name: "GreaterEqualUint16x16", argLength: 2, commutative: false},
+ {name: "GreaterEqualUint16x32", argLength: 2, commutative: false},
+ {name: "GreaterEqualUint32x4", argLength: 2, commutative: false},
+ {name: "GreaterEqualUint32x8", argLength: 2, commutative: false},
+ {name: "GreaterEqualUint32x16", argLength: 2, commutative: false},
+ {name: "GreaterEqualUint64x2", argLength: 2, commutative: false},
+ {name: "GreaterEqualUint64x4", argLength: 2, commutative: false},
+ {name: "GreaterEqualUint64x8", argLength: 2, commutative: false},
+ {name: "GreaterFloat32x4", argLength: 2, commutative: false},
+ {name: "GreaterFloat32x8", argLength: 2, commutative: false},
+ {name: "GreaterFloat32x16", argLength: 2, commutative: false},
+ {name: "GreaterFloat64x2", argLength: 2, commutative: false},
+ {name: "GreaterFloat64x4", argLength: 2, commutative: false},
+ {name: "GreaterFloat64x8", argLength: 2, commutative: false},
+ {name: "GreaterInt8x16", argLength: 2, commutative: false},
+ {name: "GreaterInt8x32", argLength: 2, commutative: false},
+ {name: "GreaterInt8x64", argLength: 2, commutative: false},
+ {name: "GreaterInt16x8", argLength: 2, commutative: false},
+ {name: "GreaterInt16x16", argLength: 2, commutative: false},
+ {name: "GreaterInt16x32", argLength: 2, commutative: false},
+ {name: "GreaterInt32x4", argLength: 2, commutative: false},
+ {name: "GreaterInt32x8", argLength: 2, commutative: false},
+ {name: "GreaterInt32x16", argLength: 2, commutative: false},
+ {name: "GreaterInt64x2", argLength: 2, commutative: false},
+ {name: "GreaterInt64x4", argLength: 2, commutative: false},
+ {name: "GreaterInt64x8", argLength: 2, commutative: false},
{name: "GreaterMaskedFloat32x4", argLength: 3, commutative: false},
+ {name: "GreaterMaskedFloat32x8", argLength: 3, commutative: false},
+ {name: "GreaterMaskedFloat32x16", argLength: 3, commutative: false},
+ {name: "GreaterMaskedFloat64x2", argLength: 3, commutative: false},
+ {name: "GreaterMaskedFloat64x4", argLength: 3, commutative: false},
+ {name: "GreaterMaskedFloat64x8", argLength: 3, commutative: false},
+ {name: "GreaterMaskedInt8x16", argLength: 3, commutative: false},
+ {name: "GreaterMaskedInt8x32", argLength: 3, commutative: false},
+ {name: "GreaterMaskedInt8x64", argLength: 3, commutative: false},
+ {name: "GreaterMaskedInt16x8", argLength: 3, commutative: false},
+ {name: "GreaterMaskedInt16x16", argLength: 3, commutative: false},
+ {name: "GreaterMaskedInt16x32", argLength: 3, commutative: false},
+ {name: "GreaterMaskedInt32x4", argLength: 3, commutative: false},
+ {name: "GreaterMaskedInt32x8", argLength: 3, commutative: false},
+ {name: "GreaterMaskedInt32x16", argLength: 3, commutative: false},
+ {name: "GreaterMaskedInt64x2", argLength: 3, commutative: false},
+ {name: "GreaterMaskedInt64x4", argLength: 3, commutative: false},
+ {name: "GreaterMaskedInt64x8", argLength: 3, commutative: false},
+ {name: "GreaterMaskedUint8x16", argLength: 3, commutative: false},
+ {name: "GreaterMaskedUint8x32", argLength: 3, commutative: false},
+ {name: "GreaterMaskedUint8x64", argLength: 3, commutative: false},
+ {name: "GreaterMaskedUint16x8", argLength: 3, commutative: false},
+ {name: "GreaterMaskedUint16x16", argLength: 3, commutative: false},
+ {name: "GreaterMaskedUint16x32", argLength: 3, commutative: false},
+ {name: "GreaterMaskedUint32x4", argLength: 3, commutative: false},
+ {name: "GreaterMaskedUint32x8", argLength: 3, commutative: false},
+ {name: "GreaterMaskedUint32x16", argLength: 3, commutative: false},
+ {name: "GreaterMaskedUint64x2", argLength: 3, commutative: false},
+ {name: "GreaterMaskedUint64x4", argLength: 3, commutative: false},
+ {name: "GreaterMaskedUint64x8", argLength: 3, commutative: false},
+ {name: "GreaterUint8x16", argLength: 2, commutative: false},
+ {name: "GreaterUint8x32", argLength: 2, commutative: false},
+ {name: "GreaterUint8x64", argLength: 2, commutative: false},
+ {name: "GreaterUint16x8", argLength: 2, commutative: false},
+ {name: "GreaterUint16x16", argLength: 2, commutative: false},
+ {name: "GreaterUint16x32", argLength: 2, commutative: false},
+ {name: "GreaterUint32x4", argLength: 2, commutative: false},
+ {name: "GreaterUint32x8", argLength: 2, commutative: false},
+ {name: "GreaterUint32x16", argLength: 2, commutative: false},
+ {name: "GreaterUint64x2", argLength: 2, commutative: false},
+ {name: "GreaterUint64x4", argLength: 2, commutative: false},
+ {name: "GreaterUint64x8", argLength: 2, commutative: false},
{name: "IsNanFloat32x4", argLength: 2, commutative: true},
+ {name: "IsNanFloat32x8", argLength: 2, commutative: true},
+ {name: "IsNanFloat32x16", argLength: 2, commutative: true},
+ {name: "IsNanFloat64x2", argLength: 2, commutative: true},
+ {name: "IsNanFloat64x4", argLength: 2, commutative: true},
+ {name: "IsNanFloat64x8", argLength: 2, commutative: true},
{name: "IsNanMaskedFloat32x4", argLength: 3, commutative: true},
- {name: "LessFloat32x4", argLength: 2, commutative: false},
+ {name: "IsNanMaskedFloat32x8", argLength: 3, commutative: true},
+ {name: "IsNanMaskedFloat32x16", argLength: 3, commutative: true},
+ {name: "IsNanMaskedFloat64x2", argLength: 3, commutative: true},
+ {name: "IsNanMaskedFloat64x4", argLength: 3, commutative: true},
+ {name: "IsNanMaskedFloat64x8", argLength: 3, commutative: true},
{name: "LessEqualFloat32x4", argLength: 2, commutative: false},
- {name: "LessEqualMaskedFloat32x4", argLength: 3, commutative: false},
- {name: "LessMaskedFloat32x4", argLength: 3, commutative: false},
- {name: "MaxFloat32x4", argLength: 2, commutative: true},
- {name: "MaxMaskedFloat32x4", argLength: 3, commutative: true},
- {name: "MinFloat32x4", argLength: 2, commutative: true},
- {name: "MinMaskedFloat32x4", argLength: 3, commutative: true},
- {name: "MulFloat32x4", argLength: 2, commutative: true},
- {name: "MulByPowOf2Float32x4", argLength: 2, commutative: false},
- {name: "MulByPowOf2MaskedFloat32x4", argLength: 3, commutative: false},
- {name: "MulMaskedFloat32x4", argLength: 3, commutative: true},
- {name: "NotEqualFloat32x4", argLength: 2, commutative: true},
- {name: "NotEqualMaskedFloat32x4", argLength: 3, commutative: true},
- {name: "PairwiseAddFloat32x4", argLength: 2, commutative: false},
- {name: "PairwiseSubFloat32x4", argLength: 2, commutative: false},
- {name: "RoundFloat32x4", argLength: 1, commutative: false},
- {name: "SqrtFloat32x4", argLength: 1, commutative: false},
- {name: "SqrtMaskedFloat32x4", argLength: 2, commutative: false},
- {name: "SubFloat32x4", argLength: 2, commutative: false},
- {name: "SubMaskedFloat32x4", argLength: 3, commutative: false},
- {name: "TruncFloat32x4", argLength: 1, commutative: false},
- {name: "AddFloat32x8", argLength: 2, commutative: true},
- {name: "AddMaskedFloat32x8", argLength: 3, commutative: true},
- {name: "AddSubFloat32x8", argLength: 2, commutative: false},
- {name: "ApproximateReciprocalFloat32x8", argLength: 1, commutative: false},
- {name: "ApproximateReciprocalMaskedFloat32x8", argLength: 2, commutative: false},
- {name: "ApproximateReciprocalOfSqrtFloat32x8", argLength: 1, commutative: false},
- {name: "ApproximateReciprocalOfSqrtMaskedFloat32x8", argLength: 2, commutative: false},
- {name: "CeilFloat32x8", argLength: 1, commutative: false},
- {name: "CompressFloat32x8", argLength: 2, commutative: false},
- {name: "DivFloat32x8", argLength: 2, commutative: false},
- {name: "DivMaskedFloat32x8", argLength: 3, commutative: false},
- {name: "DotProdBroadcastFloat32x8", argLength: 2, commutative: true},
- {name: "EqualFloat32x8", argLength: 2, commutative: true},
- {name: "EqualMaskedFloat32x8", argLength: 3, commutative: true},
- {name: "FloorFloat32x8", argLength: 1, commutative: false},
- {name: "FusedMultiplyAddFloat32x8", argLength: 3, commutative: false},
- {name: "FusedMultiplyAddMaskedFloat32x8", argLength: 4, commutative: false},
- {name: "FusedMultiplyAddSubFloat32x8", argLength: 3, commutative: false},
- {name: "FusedMultiplyAddSubMaskedFloat32x8", argLength: 4, commutative: false},
- {name: "FusedMultiplySubAddFloat32x8", argLength: 3, commutative: false},
- {name: "FusedMultiplySubAddMaskedFloat32x8", argLength: 4, commutative: false},
- {name: "GreaterFloat32x8", argLength: 2, commutative: false},
- {name: "GreaterEqualFloat32x8", argLength: 2, commutative: false},
- {name: "GreaterEqualMaskedFloat32x8", argLength: 3, commutative: false},
- {name: "GreaterMaskedFloat32x8", argLength: 3, commutative: false},
- {name: "IsNanFloat32x8", argLength: 2, commutative: true},
- {name: "IsNanMaskedFloat32x8", argLength: 3, commutative: true},
- {name: "LessFloat32x8", argLength: 2, commutative: false},
{name: "LessEqualFloat32x8", argLength: 2, commutative: false},
+ {name: "LessEqualFloat32x16", argLength: 2, commutative: false},
+ {name: "LessEqualFloat64x2", argLength: 2, commutative: false},
+ {name: "LessEqualFloat64x4", argLength: 2, commutative: false},
+ {name: "LessEqualFloat64x8", argLength: 2, commutative: false},
+ {name: "LessEqualInt8x16", argLength: 2, commutative: false},
+ {name: "LessEqualInt8x32", argLength: 2, commutative: false},
+ {name: "LessEqualInt8x64", argLength: 2, commutative: false},
+ {name: "LessEqualInt16x8", argLength: 2, commutative: false},
+ {name: "LessEqualInt16x16", argLength: 2, commutative: false},
+ {name: "LessEqualInt16x32", argLength: 2, commutative: false},
+ {name: "LessEqualInt32x4", argLength: 2, commutative: false},
+ {name: "LessEqualInt32x8", argLength: 2, commutative: false},
+ {name: "LessEqualInt32x16", argLength: 2, commutative: false},
+ {name: "LessEqualInt64x2", argLength: 2, commutative: false},
+ {name: "LessEqualInt64x4", argLength: 2, commutative: false},
+ {name: "LessEqualInt64x8", argLength: 2, commutative: false},
+ {name: "LessEqualMaskedFloat32x4", argLength: 3, commutative: false},
{name: "LessEqualMaskedFloat32x8", argLength: 3, commutative: false},
+ {name: "LessEqualMaskedFloat32x16", argLength: 3, commutative: false},
+ {name: "LessEqualMaskedFloat64x2", argLength: 3, commutative: false},
+ {name: "LessEqualMaskedFloat64x4", argLength: 3, commutative: false},
+ {name: "LessEqualMaskedFloat64x8", argLength: 3, commutative: false},
+ {name: "LessEqualMaskedInt8x16", argLength: 3, commutative: false},
+ {name: "LessEqualMaskedInt8x32", argLength: 3, commutative: false},
+ {name: "LessEqualMaskedInt8x64", argLength: 3, commutative: false},
+ {name: "LessEqualMaskedInt16x8", argLength: 3, commutative: false},
+ {name: "LessEqualMaskedInt16x16", argLength: 3, commutative: false},
+ {name: "LessEqualMaskedInt16x32", argLength: 3, commutative: false},
+ {name: "LessEqualMaskedInt32x4", argLength: 3, commutative: false},
+ {name: "LessEqualMaskedInt32x8", argLength: 3, commutative: false},
+ {name: "LessEqualMaskedInt32x16", argLength: 3, commutative: false},
+ {name: "LessEqualMaskedInt64x2", argLength: 3, commutative: false},
+ {name: "LessEqualMaskedInt64x4", argLength: 3, commutative: false},
+ {name: "LessEqualMaskedInt64x8", argLength: 3, commutative: false},
+ {name: "LessEqualMaskedUint8x16", argLength: 3, commutative: false},
+ {name: "LessEqualMaskedUint8x32", argLength: 3, commutative: false},
+ {name: "LessEqualMaskedUint8x64", argLength: 3, commutative: false},
+ {name: "LessEqualMaskedUint16x8", argLength: 3, commutative: false},
+ {name: "LessEqualMaskedUint16x16", argLength: 3, commutative: false},
+ {name: "LessEqualMaskedUint16x32", argLength: 3, commutative: false},
+ {name: "LessEqualMaskedUint32x4", argLength: 3, commutative: false},
+ {name: "LessEqualMaskedUint32x8", argLength: 3, commutative: false},
+ {name: "LessEqualMaskedUint32x16", argLength: 3, commutative: false},
+ {name: "LessEqualMaskedUint64x2", argLength: 3, commutative: false},
+ {name: "LessEqualMaskedUint64x4", argLength: 3, commutative: false},
+ {name: "LessEqualMaskedUint64x8", argLength: 3, commutative: false},
+ {name: "LessEqualUint8x16", argLength: 2, commutative: false},
+ {name: "LessEqualUint8x32", argLength: 2, commutative: false},
+ {name: "LessEqualUint8x64", argLength: 2, commutative: false},
+ {name: "LessEqualUint16x8", argLength: 2, commutative: false},
+ {name: "LessEqualUint16x16", argLength: 2, commutative: false},
+ {name: "LessEqualUint16x32", argLength: 2, commutative: false},
+ {name: "LessEqualUint32x4", argLength: 2, commutative: false},
+ {name: "LessEqualUint32x8", argLength: 2, commutative: false},
+ {name: "LessEqualUint32x16", argLength: 2, commutative: false},
+ {name: "LessEqualUint64x2", argLength: 2, commutative: false},
+ {name: "LessEqualUint64x4", argLength: 2, commutative: false},
+ {name: "LessEqualUint64x8", argLength: 2, commutative: false},
+ {name: "LessFloat32x4", argLength: 2, commutative: false},
+ {name: "LessFloat32x8", argLength: 2, commutative: false},
+ {name: "LessFloat32x16", argLength: 2, commutative: false},
+ {name: "LessFloat64x2", argLength: 2, commutative: false},
+ {name: "LessFloat64x4", argLength: 2, commutative: false},
+ {name: "LessFloat64x8", argLength: 2, commutative: false},
+ {name: "LessInt8x16", argLength: 2, commutative: false},
+ {name: "LessInt8x32", argLength: 2, commutative: false},
+ {name: "LessInt8x64", argLength: 2, commutative: false},
+ {name: "LessInt16x8", argLength: 2, commutative: false},
+ {name: "LessInt16x16", argLength: 2, commutative: false},
+ {name: "LessInt16x32", argLength: 2, commutative: false},
+ {name: "LessInt32x4", argLength: 2, commutative: false},
+ {name: "LessInt32x8", argLength: 2, commutative: false},
+ {name: "LessInt32x16", argLength: 2, commutative: false},
+ {name: "LessInt64x2", argLength: 2, commutative: false},
+ {name: "LessInt64x4", argLength: 2, commutative: false},
+ {name: "LessInt64x8", argLength: 2, commutative: false},
+ {name: "LessMaskedFloat32x4", argLength: 3, commutative: false},
{name: "LessMaskedFloat32x8", argLength: 3, commutative: false},
+ {name: "LessMaskedFloat32x16", argLength: 3, commutative: false},
+ {name: "LessMaskedFloat64x2", argLength: 3, commutative: false},
+ {name: "LessMaskedFloat64x4", argLength: 3, commutative: false},
+ {name: "LessMaskedFloat64x8", argLength: 3, commutative: false},
+ {name: "LessMaskedInt8x16", argLength: 3, commutative: false},
+ {name: "LessMaskedInt8x32", argLength: 3, commutative: false},
+ {name: "LessMaskedInt8x64", argLength: 3, commutative: false},
+ {name: "LessMaskedInt16x8", argLength: 3, commutative: false},
+ {name: "LessMaskedInt16x16", argLength: 3, commutative: false},
+ {name: "LessMaskedInt16x32", argLength: 3, commutative: false},
+ {name: "LessMaskedInt32x4", argLength: 3, commutative: false},
+ {name: "LessMaskedInt32x8", argLength: 3, commutative: false},
+ {name: "LessMaskedInt32x16", argLength: 3, commutative: false},
+ {name: "LessMaskedInt64x2", argLength: 3, commutative: false},
+ {name: "LessMaskedInt64x4", argLength: 3, commutative: false},
+ {name: "LessMaskedInt64x8", argLength: 3, commutative: false},
+ {name: "LessMaskedUint8x16", argLength: 3, commutative: false},
+ {name: "LessMaskedUint8x32", argLength: 3, commutative: false},
+ {name: "LessMaskedUint8x64", argLength: 3, commutative: false},
+ {name: "LessMaskedUint16x8", argLength: 3, commutative: false},
+ {name: "LessMaskedUint16x16", argLength: 3, commutative: false},
+ {name: "LessMaskedUint16x32", argLength: 3, commutative: false},
+ {name: "LessMaskedUint32x4", argLength: 3, commutative: false},
+ {name: "LessMaskedUint32x8", argLength: 3, commutative: false},
+ {name: "LessMaskedUint32x16", argLength: 3, commutative: false},
+ {name: "LessMaskedUint64x2", argLength: 3, commutative: false},
+ {name: "LessMaskedUint64x4", argLength: 3, commutative: false},
+ {name: "LessMaskedUint64x8", argLength: 3, commutative: false},
+ {name: "LessUint8x16", argLength: 2, commutative: false},
+ {name: "LessUint8x32", argLength: 2, commutative: false},
+ {name: "LessUint8x64", argLength: 2, commutative: false},
+ {name: "LessUint16x8", argLength: 2, commutative: false},
+ {name: "LessUint16x16", argLength: 2, commutative: false},
+ {name: "LessUint16x32", argLength: 2, commutative: false},
+ {name: "LessUint32x4", argLength: 2, commutative: false},
+ {name: "LessUint32x8", argLength: 2, commutative: false},
+ {name: "LessUint32x16", argLength: 2, commutative: false},
+ {name: "LessUint64x2", argLength: 2, commutative: false},
+ {name: "LessUint64x4", argLength: 2, commutative: false},
+ {name: "LessUint64x8", argLength: 2, commutative: false},
+ {name: "MaxFloat32x4", argLength: 2, commutative: true},
{name: "MaxFloat32x8", argLength: 2, commutative: true},
+ {name: "MaxFloat32x16", argLength: 2, commutative: true},
+ {name: "MaxFloat64x2", argLength: 2, commutative: true},
+ {name: "MaxFloat64x4", argLength: 2, commutative: true},
+ {name: "MaxFloat64x8", argLength: 2, commutative: true},
+ {name: "MaxInt8x16", argLength: 2, commutative: true},
+ {name: "MaxInt8x32", argLength: 2, commutative: true},
+ {name: "MaxInt8x64", argLength: 2, commutative: true},
+ {name: "MaxInt16x8", argLength: 2, commutative: true},
+ {name: "MaxInt16x16", argLength: 2, commutative: true},
+ {name: "MaxInt16x32", argLength: 2, commutative: true},
+ {name: "MaxInt32x4", argLength: 2, commutative: true},
+ {name: "MaxInt32x8", argLength: 2, commutative: true},
+ {name: "MaxInt32x16", argLength: 2, commutative: true},
+ {name: "MaxInt64x2", argLength: 2, commutative: true},
+ {name: "MaxInt64x4", argLength: 2, commutative: true},
+ {name: "MaxInt64x8", argLength: 2, commutative: true},
+ {name: "MaxMaskedFloat32x4", argLength: 3, commutative: true},
{name: "MaxMaskedFloat32x8", argLength: 3, commutative: true},
+ {name: "MaxMaskedFloat32x16", argLength: 3, commutative: true},
+ {name: "MaxMaskedFloat64x2", argLength: 3, commutative: true},
+ {name: "MaxMaskedFloat64x4", argLength: 3, commutative: true},
+ {name: "MaxMaskedFloat64x8", argLength: 3, commutative: true},
+ {name: "MaxMaskedInt8x16", argLength: 3, commutative: true},
+ {name: "MaxMaskedInt8x32", argLength: 3, commutative: true},
+ {name: "MaxMaskedInt8x64", argLength: 3, commutative: true},
+ {name: "MaxMaskedInt16x8", argLength: 3, commutative: true},
+ {name: "MaxMaskedInt16x16", argLength: 3, commutative: true},
+ {name: "MaxMaskedInt16x32", argLength: 3, commutative: true},
+ {name: "MaxMaskedInt32x4", argLength: 3, commutative: true},
+ {name: "MaxMaskedInt32x8", argLength: 3, commutative: true},
+ {name: "MaxMaskedInt32x16", argLength: 3, commutative: true},
+ {name: "MaxMaskedInt64x2", argLength: 3, commutative: true},
+ {name: "MaxMaskedInt64x4", argLength: 3, commutative: true},
+ {name: "MaxMaskedInt64x8", argLength: 3, commutative: true},
+ {name: "MaxMaskedUint8x16", argLength: 3, commutative: true},
+ {name: "MaxMaskedUint8x32", argLength: 3, commutative: true},
+ {name: "MaxMaskedUint8x64", argLength: 3, commutative: true},
+ {name: "MaxMaskedUint16x8", argLength: 3, commutative: true},
+ {name: "MaxMaskedUint16x16", argLength: 3, commutative: true},
+ {name: "MaxMaskedUint16x32", argLength: 3, commutative: true},
+ {name: "MaxMaskedUint32x4", argLength: 3, commutative: true},
+ {name: "MaxMaskedUint32x8", argLength: 3, commutative: true},
+ {name: "MaxMaskedUint32x16", argLength: 3, commutative: true},
+ {name: "MaxMaskedUint64x2", argLength: 3, commutative: true},
+ {name: "MaxMaskedUint64x4", argLength: 3, commutative: true},
+ {name: "MaxMaskedUint64x8", argLength: 3, commutative: true},
+ {name: "MaxUint8x16", argLength: 2, commutative: true},
+ {name: "MaxUint8x32", argLength: 2, commutative: true},
+ {name: "MaxUint8x64", argLength: 2, commutative: true},
+ {name: "MaxUint16x8", argLength: 2, commutative: true},
+ {name: "MaxUint16x16", argLength: 2, commutative: true},
+ {name: "MaxUint16x32", argLength: 2, commutative: true},
+ {name: "MaxUint32x4", argLength: 2, commutative: true},
+ {name: "MaxUint32x8", argLength: 2, commutative: true},
+ {name: "MaxUint32x16", argLength: 2, commutative: true},
+ {name: "MaxUint64x2", argLength: 2, commutative: true},
+ {name: "MaxUint64x4", argLength: 2, commutative: true},
+ {name: "MaxUint64x8", argLength: 2, commutative: true},
+ {name: "MinFloat32x4", argLength: 2, commutative: true},
{name: "MinFloat32x8", argLength: 2, commutative: true},
+ {name: "MinFloat32x16", argLength: 2, commutative: true},
+ {name: "MinFloat64x2", argLength: 2, commutative: true},
+ {name: "MinFloat64x4", argLength: 2, commutative: true},
+ {name: "MinFloat64x8", argLength: 2, commutative: true},
+ {name: "MinInt8x16", argLength: 2, commutative: true},
+ {name: "MinInt8x32", argLength: 2, commutative: true},
+ {name: "MinInt8x64", argLength: 2, commutative: true},
+ {name: "MinInt16x8", argLength: 2, commutative: true},
+ {name: "MinInt16x16", argLength: 2, commutative: true},
+ {name: "MinInt16x32", argLength: 2, commutative: true},
+ {name: "MinInt32x4", argLength: 2, commutative: true},
+ {name: "MinInt32x8", argLength: 2, commutative: true},
+ {name: "MinInt32x16", argLength: 2, commutative: true},
+ {name: "MinInt64x2", argLength: 2, commutative: true},
+ {name: "MinInt64x4", argLength: 2, commutative: true},
+ {name: "MinInt64x8", argLength: 2, commutative: true},
+ {name: "MinMaskedFloat32x4", argLength: 3, commutative: true},
{name: "MinMaskedFloat32x8", argLength: 3, commutative: true},
- {name: "MulFloat32x8", argLength: 2, commutative: true},
- {name: "MulByPowOf2Float32x8", argLength: 2, commutative: false},
- {name: "MulByPowOf2MaskedFloat32x8", argLength: 3, commutative: false},
- {name: "MulMaskedFloat32x8", argLength: 3, commutative: true},
- {name: "NotEqualFloat32x8", argLength: 2, commutative: true},
- {name: "NotEqualMaskedFloat32x8", argLength: 3, commutative: true},
- {name: "PairwiseAddFloat32x8", argLength: 2, commutative: false},
- {name: "PairwiseSubFloat32x8", argLength: 2, commutative: false},
- {name: "RoundFloat32x8", argLength: 1, commutative: false},
- {name: "SqrtFloat32x8", argLength: 1, commutative: false},
- {name: "SqrtMaskedFloat32x8", argLength: 2, commutative: false},
- {name: "SubFloat32x8", argLength: 2, commutative: false},
- {name: "SubMaskedFloat32x8", argLength: 3, commutative: false},
- {name: "TruncFloat32x8", argLength: 1, commutative: false},
- {name: "AddFloat64x2", argLength: 2, commutative: true},
- {name: "AddMaskedFloat64x2", argLength: 3, commutative: true},
- {name: "AddSubFloat64x2", argLength: 2, commutative: false},
- {name: "ApproximateReciprocalFloat64x2", argLength: 1, commutative: false},
- {name: "ApproximateReciprocalMaskedFloat64x2", argLength: 2, commutative: false},
- {name: "ApproximateReciprocalOfSqrtFloat64x2", argLength: 1, commutative: false},
- {name: "ApproximateReciprocalOfSqrtMaskedFloat64x2", argLength: 2, commutative: false},
- {name: "CeilFloat64x2", argLength: 1, commutative: false},
- {name: "CompressFloat64x2", argLength: 2, commutative: false},
- {name: "DivFloat64x2", argLength: 2, commutative: false},
- {name: "DivMaskedFloat64x2", argLength: 3, commutative: false},
- {name: "DotProdBroadcastFloat64x2", argLength: 2, commutative: true},
- {name: "EqualFloat64x2", argLength: 2, commutative: true},
- {name: "EqualMaskedFloat64x2", argLength: 3, commutative: true},
- {name: "FloorFloat64x2", argLength: 1, commutative: false},
- {name: "FusedMultiplyAddFloat64x2", argLength: 3, commutative: false},
- {name: "FusedMultiplyAddMaskedFloat64x2", argLength: 4, commutative: false},
- {name: "FusedMultiplyAddSubFloat64x2", argLength: 3, commutative: false},
- {name: "FusedMultiplyAddSubMaskedFloat64x2", argLength: 4, commutative: false},
- {name: "FusedMultiplySubAddFloat64x2", argLength: 3, commutative: false},
- {name: "FusedMultiplySubAddMaskedFloat64x2", argLength: 4, commutative: false},
- {name: "GreaterFloat64x2", argLength: 2, commutative: false},
- {name: "GreaterEqualFloat64x2", argLength: 2, commutative: false},
- {name: "GreaterEqualMaskedFloat64x2", argLength: 3, commutative: false},
- {name: "GreaterMaskedFloat64x2", argLength: 3, commutative: false},
- {name: "IsNanFloat64x2", argLength: 2, commutative: true},
- {name: "IsNanMaskedFloat64x2", argLength: 3, commutative: true},
- {name: "LessFloat64x2", argLength: 2, commutative: false},
- {name: "LessEqualFloat64x2", argLength: 2, commutative: false},
- {name: "LessEqualMaskedFloat64x2", argLength: 3, commutative: false},
- {name: "LessMaskedFloat64x2", argLength: 3, commutative: false},
- {name: "MaxFloat64x2", argLength: 2, commutative: true},
- {name: "MaxMaskedFloat64x2", argLength: 3, commutative: true},
- {name: "MinFloat64x2", argLength: 2, commutative: true},
+ {name: "MinMaskedFloat32x16", argLength: 3, commutative: true},
{name: "MinMaskedFloat64x2", argLength: 3, commutative: true},
- {name: "MulFloat64x2", argLength: 2, commutative: true},
- {name: "MulByPowOf2Float64x2", argLength: 2, commutative: false},
- {name: "MulByPowOf2MaskedFloat64x2", argLength: 3, commutative: false},
- {name: "MulMaskedFloat64x2", argLength: 3, commutative: true},
- {name: "NotEqualFloat64x2", argLength: 2, commutative: true},
- {name: "NotEqualMaskedFloat64x2", argLength: 3, commutative: true},
- {name: "PairwiseAddFloat64x2", argLength: 2, commutative: false},
- {name: "PairwiseSubFloat64x2", argLength: 2, commutative: false},
- {name: "RoundFloat64x2", argLength: 1, commutative: false},
- {name: "SqrtFloat64x2", argLength: 1, commutative: false},
- {name: "SqrtMaskedFloat64x2", argLength: 2, commutative: false},
- {name: "SubFloat64x2", argLength: 2, commutative: false},
- {name: "SubMaskedFloat64x2", argLength: 3, commutative: false},
- {name: "TruncFloat64x2", argLength: 1, commutative: false},
- {name: "AddFloat64x4", argLength: 2, commutative: true},
- {name: "AddMaskedFloat64x4", argLength: 3, commutative: true},
- {name: "AddSubFloat64x4", argLength: 2, commutative: false},
- {name: "ApproximateReciprocalFloat64x4", argLength: 1, commutative: false},
- {name: "ApproximateReciprocalMaskedFloat64x4", argLength: 2, commutative: false},
- {name: "ApproximateReciprocalOfSqrtFloat64x4", argLength: 1, commutative: false},
- {name: "ApproximateReciprocalOfSqrtMaskedFloat64x4", argLength: 2, commutative: false},
- {name: "CeilFloat64x4", argLength: 1, commutative: false},
- {name: "CompressFloat64x4", argLength: 2, commutative: false},
- {name: "DivFloat64x4", argLength: 2, commutative: false},
- {name: "DivMaskedFloat64x4", argLength: 3, commutative: false},
- {name: "EqualFloat64x4", argLength: 2, commutative: true},
- {name: "EqualMaskedFloat64x4", argLength: 3, commutative: true},
- {name: "FloorFloat64x4", argLength: 1, commutative: false},
- {name: "FusedMultiplyAddFloat64x4", argLength: 3, commutative: false},
- {name: "FusedMultiplyAddMaskedFloat64x4", argLength: 4, commutative: false},
- {name: "FusedMultiplyAddSubFloat64x4", argLength: 3, commutative: false},
- {name: "FusedMultiplyAddSubMaskedFloat64x4", argLength: 4, commutative: false},
- {name: "FusedMultiplySubAddFloat64x4", argLength: 3, commutative: false},
- {name: "FusedMultiplySubAddMaskedFloat64x4", argLength: 4, commutative: false},
- {name: "GreaterFloat64x4", argLength: 2, commutative: false},
- {name: "GreaterEqualFloat64x4", argLength: 2, commutative: false},
- {name: "GreaterEqualMaskedFloat64x4", argLength: 3, commutative: false},
- {name: "GreaterMaskedFloat64x4", argLength: 3, commutative: false},
- {name: "IsNanFloat64x4", argLength: 2, commutative: true},
- {name: "IsNanMaskedFloat64x4", argLength: 3, commutative: true},
- {name: "LessFloat64x4", argLength: 2, commutative: false},
- {name: "LessEqualFloat64x4", argLength: 2, commutative: false},
- {name: "LessEqualMaskedFloat64x4", argLength: 3, commutative: false},
- {name: "LessMaskedFloat64x4", argLength: 3, commutative: false},
- {name: "MaxFloat64x4", argLength: 2, commutative: true},
- {name: "MaxMaskedFloat64x4", argLength: 3, commutative: true},
- {name: "MinFloat64x4", argLength: 2, commutative: true},
{name: "MinMaskedFloat64x4", argLength: 3, commutative: true},
- {name: "MulFloat64x4", argLength: 2, commutative: true},
- {name: "MulByPowOf2Float64x4", argLength: 2, commutative: false},
- {name: "MulByPowOf2MaskedFloat64x4", argLength: 3, commutative: false},
- {name: "MulMaskedFloat64x4", argLength: 3, commutative: true},
- {name: "NotEqualFloat64x4", argLength: 2, commutative: true},
- {name: "NotEqualMaskedFloat64x4", argLength: 3, commutative: true},
- {name: "PairwiseAddFloat64x4", argLength: 2, commutative: false},
- {name: "PairwiseSubFloat64x4", argLength: 2, commutative: false},
- {name: "RoundFloat64x4", argLength: 1, commutative: false},
- {name: "SqrtFloat64x4", argLength: 1, commutative: false},
- {name: "SqrtMaskedFloat64x4", argLength: 2, commutative: false},
- {name: "SubFloat64x4", argLength: 2, commutative: false},
- {name: "SubMaskedFloat64x4", argLength: 3, commutative: false},
- {name: "TruncFloat64x4", argLength: 1, commutative: false},
- {name: "AddFloat64x8", argLength: 2, commutative: true},
- {name: "AddMaskedFloat64x8", argLength: 3, commutative: true},
- {name: "ApproximateReciprocalFloat64x8", argLength: 1, commutative: false},
- {name: "ApproximateReciprocalMaskedFloat64x8", argLength: 2, commutative: false},
- {name: "ApproximateReciprocalOfSqrtFloat64x8", argLength: 1, commutative: false},
- {name: "ApproximateReciprocalOfSqrtMaskedFloat64x8", argLength: 2, commutative: false},
- {name: "CompressFloat64x8", argLength: 2, commutative: false},
- {name: "DivFloat64x8", argLength: 2, commutative: false},
- {name: "DivMaskedFloat64x8", argLength: 3, commutative: false},
- {name: "EqualFloat64x8", argLength: 2, commutative: true},
- {name: "EqualMaskedFloat64x8", argLength: 3, commutative: true},
- {name: "FusedMultiplyAddFloat64x8", argLength: 3, commutative: false},
- {name: "FusedMultiplyAddMaskedFloat64x8", argLength: 4, commutative: false},
- {name: "FusedMultiplyAddSubFloat64x8", argLength: 3, commutative: false},
- {name: "FusedMultiplyAddSubMaskedFloat64x8", argLength: 4, commutative: false},
- {name: "FusedMultiplySubAddFloat64x8", argLength: 3, commutative: false},
- {name: "FusedMultiplySubAddMaskedFloat64x8", argLength: 4, commutative: false},
- {name: "GreaterFloat64x8", argLength: 2, commutative: false},
- {name: "GreaterEqualFloat64x8", argLength: 2, commutative: false},
- {name: "GreaterEqualMaskedFloat64x8", argLength: 3, commutative: false},
- {name: "GreaterMaskedFloat64x8", argLength: 3, commutative: false},
- {name: "IsNanFloat64x8", argLength: 2, commutative: true},
- {name: "IsNanMaskedFloat64x8", argLength: 3, commutative: true},
- {name: "LessFloat64x8", argLength: 2, commutative: false},
- {name: "LessEqualFloat64x8", argLength: 2, commutative: false},
- {name: "LessEqualMaskedFloat64x8", argLength: 3, commutative: false},
- {name: "LessMaskedFloat64x8", argLength: 3, commutative: false},
- {name: "MaxFloat64x8", argLength: 2, commutative: true},
- {name: "MaxMaskedFloat64x8", argLength: 3, commutative: true},
- {name: "MinFloat64x8", argLength: 2, commutative: true},
{name: "MinMaskedFloat64x8", argLength: 3, commutative: true},
- {name: "MulFloat64x8", argLength: 2, commutative: true},
+ {name: "MinMaskedInt8x16", argLength: 3, commutative: true},
+ {name: "MinMaskedInt8x32", argLength: 3, commutative: true},
+ {name: "MinMaskedInt8x64", argLength: 3, commutative: true},
+ {name: "MinMaskedInt16x8", argLength: 3, commutative: true},
+ {name: "MinMaskedInt16x16", argLength: 3, commutative: true},
+ {name: "MinMaskedInt16x32", argLength: 3, commutative: true},
+ {name: "MinMaskedInt32x4", argLength: 3, commutative: true},
+ {name: "MinMaskedInt32x8", argLength: 3, commutative: true},
+ {name: "MinMaskedInt32x16", argLength: 3, commutative: true},
+ {name: "MinMaskedInt64x2", argLength: 3, commutative: true},
+ {name: "MinMaskedInt64x4", argLength: 3, commutative: true},
+ {name: "MinMaskedInt64x8", argLength: 3, commutative: true},
+ {name: "MinMaskedUint8x16", argLength: 3, commutative: true},
+ {name: "MinMaskedUint8x32", argLength: 3, commutative: true},
+ {name: "MinMaskedUint8x64", argLength: 3, commutative: true},
+ {name: "MinMaskedUint16x8", argLength: 3, commutative: true},
+ {name: "MinMaskedUint16x16", argLength: 3, commutative: true},
+ {name: "MinMaskedUint16x32", argLength: 3, commutative: true},
+ {name: "MinMaskedUint32x4", argLength: 3, commutative: true},
+ {name: "MinMaskedUint32x8", argLength: 3, commutative: true},
+ {name: "MinMaskedUint32x16", argLength: 3, commutative: true},
+ {name: "MinMaskedUint64x2", argLength: 3, commutative: true},
+ {name: "MinMaskedUint64x4", argLength: 3, commutative: true},
+ {name: "MinMaskedUint64x8", argLength: 3, commutative: true},
+ {name: "MinUint8x16", argLength: 2, commutative: true},
+ {name: "MinUint8x32", argLength: 2, commutative: true},
+ {name: "MinUint8x64", argLength: 2, commutative: true},
+ {name: "MinUint16x8", argLength: 2, commutative: true},
+ {name: "MinUint16x16", argLength: 2, commutative: true},
+ {name: "MinUint16x32", argLength: 2, commutative: true},
+ {name: "MinUint32x4", argLength: 2, commutative: true},
+ {name: "MinUint32x8", argLength: 2, commutative: true},
+ {name: "MinUint32x16", argLength: 2, commutative: true},
+ {name: "MinUint64x2", argLength: 2, commutative: true},
+ {name: "MinUint64x4", argLength: 2, commutative: true},
+ {name: "MinUint64x8", argLength: 2, commutative: true},
+ {name: "MulByPowOf2Float32x4", argLength: 2, commutative: false},
+ {name: "MulByPowOf2Float32x8", argLength: 2, commutative: false},
+ {name: "MulByPowOf2Float32x16", argLength: 2, commutative: false},
+ {name: "MulByPowOf2Float64x2", argLength: 2, commutative: false},
+ {name: "MulByPowOf2Float64x4", argLength: 2, commutative: false},
{name: "MulByPowOf2Float64x8", argLength: 2, commutative: false},
+ {name: "MulByPowOf2MaskedFloat32x4", argLength: 3, commutative: false},
+ {name: "MulByPowOf2MaskedFloat32x8", argLength: 3, commutative: false},
+ {name: "MulByPowOf2MaskedFloat32x16", argLength: 3, commutative: false},
+ {name: "MulByPowOf2MaskedFloat64x2", argLength: 3, commutative: false},
+ {name: "MulByPowOf2MaskedFloat64x4", argLength: 3, commutative: false},
{name: "MulByPowOf2MaskedFloat64x8", argLength: 3, commutative: false},
- {name: "MulMaskedFloat64x8", argLength: 3, commutative: true},
- {name: "NotEqualFloat64x8", argLength: 2, commutative: true},
- {name: "NotEqualMaskedFloat64x8", argLength: 3, commutative: true},
- {name: "SqrtFloat64x8", argLength: 1, commutative: false},
- {name: "SqrtMaskedFloat64x8", argLength: 2, commutative: false},
- {name: "SubFloat64x8", argLength: 2, commutative: false},
- {name: "SubMaskedFloat64x8", argLength: 3, commutative: false},
- {name: "AbsoluteInt16x16", argLength: 1, commutative: false},
- {name: "AbsoluteMaskedInt16x16", argLength: 2, commutative: false},
- {name: "AddInt16x16", argLength: 2, commutative: true},
- {name: "AddMaskedInt16x16", argLength: 3, commutative: true},
- {name: "AndInt16x16", argLength: 2, commutative: true},
- {name: "AndNotInt16x16", argLength: 2, commutative: false},
- {name: "CompressInt16x16", argLength: 2, commutative: false},
- {name: "EqualInt16x16", argLength: 2, commutative: true},
- {name: "EqualMaskedInt16x16", argLength: 3, commutative: true},
- {name: "GreaterInt16x16", argLength: 2, commutative: false},
- {name: "GreaterEqualInt16x16", argLength: 2, commutative: false},
- {name: "GreaterEqualMaskedInt16x16", argLength: 3, commutative: false},
- {name: "GreaterMaskedInt16x16", argLength: 3, commutative: false},
- {name: "LessInt16x16", argLength: 2, commutative: false},
- {name: "LessEqualInt16x16", argLength: 2, commutative: false},
- {name: "LessEqualMaskedInt16x16", argLength: 3, commutative: false},
- {name: "LessMaskedInt16x16", argLength: 3, commutative: false},
- {name: "MaxInt16x16", argLength: 2, commutative: true},
- {name: "MaxMaskedInt16x16", argLength: 3, commutative: true},
- {name: "MinInt16x16", argLength: 2, commutative: true},
- {name: "MinMaskedInt16x16", argLength: 3, commutative: true},
+ {name: "MulEvenWidenInt32x4", argLength: 2, commutative: true},
+ {name: "MulEvenWidenInt32x8", argLength: 2, commutative: true},
+ {name: "MulEvenWidenInt64x2", argLength: 2, commutative: true},
+ {name: "MulEvenWidenInt64x4", argLength: 2, commutative: true},
+ {name: "MulEvenWidenInt64x8", argLength: 2, commutative: true},
+ {name: "MulEvenWidenMaskedInt64x2", argLength: 3, commutative: true},
+ {name: "MulEvenWidenMaskedInt64x4", argLength: 3, commutative: true},
+ {name: "MulEvenWidenMaskedInt64x8", argLength: 3, commutative: true},
+ {name: "MulEvenWidenMaskedUint64x2", argLength: 3, commutative: true},
+ {name: "MulEvenWidenMaskedUint64x4", argLength: 3, commutative: true},
+ {name: "MulEvenWidenMaskedUint64x8", argLength: 3, commutative: true},
+ {name: "MulEvenWidenUint32x4", argLength: 2, commutative: true},
+ {name: "MulEvenWidenUint32x8", argLength: 2, commutative: true},
+ {name: "MulEvenWidenUint64x2", argLength: 2, commutative: true},
+ {name: "MulEvenWidenUint64x4", argLength: 2, commutative: true},
+ {name: "MulEvenWidenUint64x8", argLength: 2, commutative: true},
+ {name: "MulFloat32x4", argLength: 2, commutative: true},
+ {name: "MulFloat32x8", argLength: 2, commutative: true},
+ {name: "MulFloat32x16", argLength: 2, commutative: true},
+ {name: "MulFloat64x2", argLength: 2, commutative: true},
+ {name: "MulFloat64x4", argLength: 2, commutative: true},
+ {name: "MulFloat64x8", argLength: 2, commutative: true},
+ {name: "MulHighInt16x8", argLength: 2, commutative: true},
{name: "MulHighInt16x16", argLength: 2, commutative: true},
+ {name: "MulHighInt16x32", argLength: 2, commutative: true},
+ {name: "MulHighMaskedInt16x8", argLength: 3, commutative: true},
{name: "MulHighMaskedInt16x16", argLength: 3, commutative: true},
+ {name: "MulHighMaskedInt16x32", argLength: 3, commutative: true},
+ {name: "MulHighMaskedUint16x8", argLength: 3, commutative: true},
+ {name: "MulHighMaskedUint16x16", argLength: 3, commutative: true},
+ {name: "MulHighMaskedUint16x32", argLength: 3, commutative: true},
+ {name: "MulHighUint16x8", argLength: 2, commutative: true},
+ {name: "MulHighUint16x16", argLength: 2, commutative: true},
+ {name: "MulHighUint16x32", argLength: 2, commutative: true},
+ {name: "MulLowInt16x8", argLength: 2, commutative: true},
{name: "MulLowInt16x16", argLength: 2, commutative: true},
+ {name: "MulLowInt16x32", argLength: 2, commutative: true},
+ {name: "MulLowInt32x4", argLength: 2, commutative: true},
+ {name: "MulLowInt32x8", argLength: 2, commutative: true},
+ {name: "MulLowInt32x16", argLength: 2, commutative: true},
+ {name: "MulLowInt64x2", argLength: 2, commutative: true},
+ {name: "MulLowInt64x4", argLength: 2, commutative: true},
+ {name: "MulLowInt64x8", argLength: 2, commutative: true},
+ {name: "MulLowMaskedInt16x8", argLength: 3, commutative: true},
{name: "MulLowMaskedInt16x16", argLength: 3, commutative: true},
+ {name: "MulLowMaskedInt16x32", argLength: 3, commutative: true},
+ {name: "MulLowMaskedInt32x4", argLength: 3, commutative: true},
+ {name: "MulLowMaskedInt32x8", argLength: 3, commutative: true},
+ {name: "MulLowMaskedInt32x16", argLength: 3, commutative: true},
+ {name: "MulLowMaskedInt64x2", argLength: 3, commutative: true},
+ {name: "MulLowMaskedInt64x4", argLength: 3, commutative: true},
+ {name: "MulLowMaskedInt64x8", argLength: 3, commutative: true},
+ {name: "MulMaskedFloat32x4", argLength: 3, commutative: true},
+ {name: "MulMaskedFloat32x8", argLength: 3, commutative: true},
+ {name: "MulMaskedFloat32x16", argLength: 3, commutative: true},
+ {name: "MulMaskedFloat64x2", argLength: 3, commutative: true},
+ {name: "MulMaskedFloat64x4", argLength: 3, commutative: true},
+ {name: "MulMaskedFloat64x8", argLength: 3, commutative: true},
+ {name: "NotEqualFloat32x4", argLength: 2, commutative: true},
+ {name: "NotEqualFloat32x8", argLength: 2, commutative: true},
+ {name: "NotEqualFloat32x16", argLength: 2, commutative: true},
+ {name: "NotEqualFloat64x2", argLength: 2, commutative: true},
+ {name: "NotEqualFloat64x4", argLength: 2, commutative: true},
+ {name: "NotEqualFloat64x8", argLength: 2, commutative: true},
+ {name: "NotEqualInt8x16", argLength: 2, commutative: true},
+ {name: "NotEqualInt8x32", argLength: 2, commutative: true},
+ {name: "NotEqualInt8x64", argLength: 2, commutative: true},
+ {name: "NotEqualInt16x8", argLength: 2, commutative: true},
{name: "NotEqualInt16x16", argLength: 2, commutative: true},
- {name: "NotEqualMaskedInt16x16", argLength: 3, commutative: true},
- {name: "OrInt16x16", argLength: 2, commutative: true},
- {name: "PairDotProdInt16x16", argLength: 2, commutative: false},
- {name: "PairDotProdMaskedInt16x16", argLength: 3, commutative: false},
- {name: "PairwiseAddInt16x16", argLength: 2, commutative: false},
- {name: "PairwiseSubInt16x16", argLength: 2, commutative: false},
- {name: "PopCountInt16x16", argLength: 1, commutative: false},
- {name: "PopCountMaskedInt16x16", argLength: 2, commutative: false},
- {name: "SaturatedAddInt16x16", argLength: 2, commutative: true},
- {name: "SaturatedAddMaskedInt16x16", argLength: 3, commutative: true},
- {name: "SaturatedPairwiseAddInt16x16", argLength: 2, commutative: false},
- {name: "SaturatedPairwiseSubInt16x16", argLength: 2, commutative: false},
- {name: "SaturatedSubInt16x16", argLength: 2, commutative: false},
- {name: "SaturatedSubMaskedInt16x16", argLength: 3, commutative: false},
- {name: "ShiftAllLeftInt16x16", argLength: 2, commutative: false},
- {name: "ShiftAllLeftMaskedInt16x16", argLength: 3, commutative: false},
- {name: "ShiftAllRightInt16x16", argLength: 2, commutative: false},
- {name: "ShiftAllRightMaskedInt16x16", argLength: 3, commutative: false},
- {name: "ShiftLeftInt16x16", argLength: 2, commutative: false},
- {name: "ShiftLeftAndFillUpperFromInt16x16", argLength: 3, commutative: false},
- {name: "ShiftLeftAndFillUpperFromMaskedInt16x16", argLength: 4, commutative: false},
- {name: "ShiftLeftMaskedInt16x16", argLength: 3, commutative: false},
- {name: "ShiftRightInt16x16", argLength: 2, commutative: false},
- {name: "ShiftRightAndFillUpperFromInt16x16", argLength: 3, commutative: false},
- {name: "ShiftRightAndFillUpperFromMaskedInt16x16", argLength: 4, commutative: false},
- {name: "ShiftRightMaskedInt16x16", argLength: 3, commutative: false},
- {name: "SignInt16x16", argLength: 2, commutative: false},
- {name: "SubInt16x16", argLength: 2, commutative: false},
- {name: "SubMaskedInt16x16", argLength: 3, commutative: false},
- {name: "XorInt16x16", argLength: 2, commutative: true},
- {name: "AbsoluteInt16x32", argLength: 1, commutative: false},
- {name: "AbsoluteMaskedInt16x32", argLength: 2, commutative: false},
- {name: "AddInt16x32", argLength: 2, commutative: true},
- {name: "AddMaskedInt16x32", argLength: 3, commutative: true},
- {name: "CompressInt16x32", argLength: 2, commutative: false},
- {name: "EqualInt16x32", argLength: 2, commutative: true},
- {name: "EqualMaskedInt16x32", argLength: 3, commutative: true},
- {name: "GreaterInt16x32", argLength: 2, commutative: false},
- {name: "GreaterEqualInt16x32", argLength: 2, commutative: false},
- {name: "GreaterEqualMaskedInt16x32", argLength: 3, commutative: false},
- {name: "GreaterMaskedInt16x32", argLength: 3, commutative: false},
- {name: "LessInt16x32", argLength: 2, commutative: false},
- {name: "LessEqualInt16x32", argLength: 2, commutative: false},
- {name: "LessEqualMaskedInt16x32", argLength: 3, commutative: false},
- {name: "LessMaskedInt16x32", argLength: 3, commutative: false},
- {name: "MaxInt16x32", argLength: 2, commutative: true},
- {name: "MaxMaskedInt16x32", argLength: 3, commutative: true},
- {name: "MinInt16x32", argLength: 2, commutative: true},
- {name: "MinMaskedInt16x32", argLength: 3, commutative: true},
- {name: "MulHighInt16x32", argLength: 2, commutative: true},
- {name: "MulHighMaskedInt16x32", argLength: 3, commutative: true},
- {name: "MulLowInt16x32", argLength: 2, commutative: true},
- {name: "MulLowMaskedInt16x32", argLength: 3, commutative: true},
{name: "NotEqualInt16x32", argLength: 2, commutative: true},
- {name: "NotEqualMaskedInt16x32", argLength: 3, commutative: true},
- {name: "PairDotProdInt16x32", argLength: 2, commutative: false},
- {name: "PairDotProdMaskedInt16x32", argLength: 3, commutative: false},
- {name: "PopCountInt16x32", argLength: 1, commutative: false},
- {name: "PopCountMaskedInt16x32", argLength: 2, commutative: false},
- {name: "SaturatedAddInt16x32", argLength: 2, commutative: true},
- {name: "SaturatedAddMaskedInt16x32", argLength: 3, commutative: true},
- {name: "SaturatedSubInt16x32", argLength: 2, commutative: false},
- {name: "SaturatedSubMaskedInt16x32", argLength: 3, commutative: false},
- {name: "ShiftAllLeftInt16x32", argLength: 2, commutative: false},
- {name: "ShiftAllLeftMaskedInt16x32", argLength: 3, commutative: false},
- {name: "ShiftAllRightInt16x32", argLength: 2, commutative: false},
- {name: "ShiftAllRightMaskedInt16x32", argLength: 3, commutative: false},
- {name: "ShiftLeftInt16x32", argLength: 2, commutative: false},
- {name: "ShiftLeftAndFillUpperFromInt16x32", argLength: 3, commutative: false},
- {name: "ShiftLeftAndFillUpperFromMaskedInt16x32", argLength: 4, commutative: false},
- {name: "ShiftLeftMaskedInt16x32", argLength: 3, commutative: false},
- {name: "ShiftRightInt16x32", argLength: 2, commutative: false},
- {name: "ShiftRightAndFillUpperFromInt16x32", argLength: 3, commutative: false},
- {name: "ShiftRightAndFillUpperFromMaskedInt16x32", argLength: 4, commutative: false},
- {name: "ShiftRightMaskedInt16x32", argLength: 3, commutative: false},
- {name: "SubInt16x32", argLength: 2, commutative: false},
- {name: "SubMaskedInt16x32", argLength: 3, commutative: false},
- {name: "AbsoluteInt16x8", argLength: 1, commutative: false},
- {name: "AbsoluteMaskedInt16x8", argLength: 2, commutative: false},
- {name: "AddInt16x8", argLength: 2, commutative: true},
- {name: "AddMaskedInt16x8", argLength: 3, commutative: true},
- {name: "AndInt16x8", argLength: 2, commutative: true},
- {name: "AndNotInt16x8", argLength: 2, commutative: false},
- {name: "CompressInt16x8", argLength: 2, commutative: false},
- {name: "EqualInt16x8", argLength: 2, commutative: true},
- {name: "EqualMaskedInt16x8", argLength: 3, commutative: true},
- {name: "GreaterInt16x8", argLength: 2, commutative: false},
- {name: "GreaterEqualInt16x8", argLength: 2, commutative: false},
- {name: "GreaterEqualMaskedInt16x8", argLength: 3, commutative: false},
- {name: "GreaterMaskedInt16x8", argLength: 3, commutative: false},
- {name: "LessInt16x8", argLength: 2, commutative: false},
- {name: "LessEqualInt16x8", argLength: 2, commutative: false},
- {name: "LessEqualMaskedInt16x8", argLength: 3, commutative: false},
- {name: "LessMaskedInt16x8", argLength: 3, commutative: false},
- {name: "MaxInt16x8", argLength: 2, commutative: true},
- {name: "MaxMaskedInt16x8", argLength: 3, commutative: true},
- {name: "MinInt16x8", argLength: 2, commutative: true},
- {name: "MinMaskedInt16x8", argLength: 3, commutative: true},
- {name: "MulHighInt16x8", argLength: 2, commutative: true},
- {name: "MulHighMaskedInt16x8", argLength: 3, commutative: true},
- {name: "MulLowInt16x8", argLength: 2, commutative: true},
- {name: "MulLowMaskedInt16x8", argLength: 3, commutative: true},
- {name: "NotEqualInt16x8", argLength: 2, commutative: true},
- {name: "NotEqualMaskedInt16x8", argLength: 3, commutative: true},
- {name: "OrInt16x8", argLength: 2, commutative: true},
- {name: "PairDotProdInt16x8", argLength: 2, commutative: false},
- {name: "PairDotProdMaskedInt16x8", argLength: 3, commutative: false},
- {name: "PairwiseAddInt16x8", argLength: 2, commutative: false},
- {name: "PairwiseSubInt16x8", argLength: 2, commutative: false},
- {name: "PopCountInt16x8", argLength: 1, commutative: false},
- {name: "PopCountMaskedInt16x8", argLength: 2, commutative: false},
- {name: "SaturatedAddInt16x8", argLength: 2, commutative: true},
- {name: "SaturatedAddMaskedInt16x8", argLength: 3, commutative: true},
- {name: "SaturatedPairwiseAddInt16x8", argLength: 2, commutative: false},
- {name: "SaturatedPairwiseSubInt16x8", argLength: 2, commutative: false},
- {name: "SaturatedSubInt16x8", argLength: 2, commutative: false},
- {name: "SaturatedSubMaskedInt16x8", argLength: 3, commutative: false},
- {name: "ShiftAllLeftInt16x8", argLength: 2, commutative: false},
- {name: "ShiftAllLeftMaskedInt16x8", argLength: 3, commutative: false},
- {name: "ShiftAllRightInt16x8", argLength: 2, commutative: false},
- {name: "ShiftAllRightMaskedInt16x8", argLength: 3, commutative: false},
- {name: "ShiftLeftInt16x8", argLength: 2, commutative: false},
- {name: "ShiftLeftAndFillUpperFromInt16x8", argLength: 3, commutative: false},
- {name: "ShiftLeftAndFillUpperFromMaskedInt16x8", argLength: 4, commutative: false},
- {name: "ShiftLeftMaskedInt16x8", argLength: 3, commutative: false},
- {name: "ShiftRightInt16x8", argLength: 2, commutative: false},
- {name: "ShiftRightAndFillUpperFromInt16x8", argLength: 3, commutative: false},
- {name: "ShiftRightAndFillUpperFromMaskedInt16x8", argLength: 4, commutative: false},
- {name: "ShiftRightMaskedInt16x8", argLength: 3, commutative: false},
- {name: "SignInt16x8", argLength: 2, commutative: false},
- {name: "SubInt16x8", argLength: 2, commutative: false},
- {name: "SubMaskedInt16x8", argLength: 3, commutative: false},
- {name: "XorInt16x8", argLength: 2, commutative: true},
- {name: "AbsoluteInt32x16", argLength: 1, commutative: false},
- {name: "AbsoluteMaskedInt32x16", argLength: 2, commutative: false},
- {name: "AddInt32x16", argLength: 2, commutative: true},
- {name: "AddMaskedInt32x16", argLength: 3, commutative: true},
- {name: "AndInt32x16", argLength: 2, commutative: true},
- {name: "AndMaskedInt32x16", argLength: 3, commutative: true},
- {name: "AndNotInt32x16", argLength: 2, commutative: false},
- {name: "AndNotMaskedInt32x16", argLength: 3, commutative: false},
- {name: "CompressInt32x16", argLength: 2, commutative: false},
- {name: "EqualInt32x16", argLength: 2, commutative: true},
- {name: "EqualMaskedInt32x16", argLength: 3, commutative: true},
- {name: "GreaterInt32x16", argLength: 2, commutative: false},
- {name: "GreaterEqualInt32x16", argLength: 2, commutative: false},
- {name: "GreaterEqualMaskedInt32x16", argLength: 3, commutative: false},
- {name: "GreaterMaskedInt32x16", argLength: 3, commutative: false},
- {name: "LessInt32x16", argLength: 2, commutative: false},
- {name: "LessEqualInt32x16", argLength: 2, commutative: false},
- {name: "LessEqualMaskedInt32x16", argLength: 3, commutative: false},
- {name: "LessMaskedInt32x16", argLength: 3, commutative: false},
- {name: "MaxInt32x16", argLength: 2, commutative: true},
- {name: "MaxMaskedInt32x16", argLength: 3, commutative: true},
- {name: "MinInt32x16", argLength: 2, commutative: true},
- {name: "MinMaskedInt32x16", argLength: 3, commutative: true},
- {name: "MulLowInt32x16", argLength: 2, commutative: true},
- {name: "MulLowMaskedInt32x16", argLength: 3, commutative: true},
+ {name: "NotEqualInt32x4", argLength: 2, commutative: true},
+ {name: "NotEqualInt32x8", argLength: 2, commutative: true},
{name: "NotEqualInt32x16", argLength: 2, commutative: true},
+ {name: "NotEqualInt64x2", argLength: 2, commutative: true},
+ {name: "NotEqualInt64x4", argLength: 2, commutative: true},
+ {name: "NotEqualInt64x8", argLength: 2, commutative: true},
+ {name: "NotEqualMaskedFloat32x4", argLength: 3, commutative: true},
+ {name: "NotEqualMaskedFloat32x8", argLength: 3, commutative: true},
+ {name: "NotEqualMaskedFloat32x16", argLength: 3, commutative: true},
+ {name: "NotEqualMaskedFloat64x2", argLength: 3, commutative: true},
+ {name: "NotEqualMaskedFloat64x4", argLength: 3, commutative: true},
+ {name: "NotEqualMaskedFloat64x8", argLength: 3, commutative: true},
+ {name: "NotEqualMaskedInt8x16", argLength: 3, commutative: true},
+ {name: "NotEqualMaskedInt8x32", argLength: 3, commutative: true},
+ {name: "NotEqualMaskedInt8x64", argLength: 3, commutative: true},
+ {name: "NotEqualMaskedInt16x8", argLength: 3, commutative: true},
+ {name: "NotEqualMaskedInt16x16", argLength: 3, commutative: true},
+ {name: "NotEqualMaskedInt16x32", argLength: 3, commutative: true},
+ {name: "NotEqualMaskedInt32x4", argLength: 3, commutative: true},
+ {name: "NotEqualMaskedInt32x8", argLength: 3, commutative: true},
{name: "NotEqualMaskedInt32x16", argLength: 3, commutative: true},
+ {name: "NotEqualMaskedInt64x2", argLength: 3, commutative: true},
+ {name: "NotEqualMaskedInt64x4", argLength: 3, commutative: true},
+ {name: "NotEqualMaskedInt64x8", argLength: 3, commutative: true},
+ {name: "NotEqualMaskedUint8x16", argLength: 3, commutative: true},
+ {name: "NotEqualMaskedUint8x32", argLength: 3, commutative: true},
+ {name: "NotEqualMaskedUint8x64", argLength: 3, commutative: true},
+ {name: "NotEqualMaskedUint16x8", argLength: 3, commutative: true},
+ {name: "NotEqualMaskedUint16x16", argLength: 3, commutative: true},
+ {name: "NotEqualMaskedUint16x32", argLength: 3, commutative: true},
+ {name: "NotEqualMaskedUint32x4", argLength: 3, commutative: true},
+ {name: "NotEqualMaskedUint32x8", argLength: 3, commutative: true},
+ {name: "NotEqualMaskedUint32x16", argLength: 3, commutative: true},
+ {name: "NotEqualMaskedUint64x2", argLength: 3, commutative: true},
+ {name: "NotEqualMaskedUint64x4", argLength: 3, commutative: true},
+ {name: "NotEqualMaskedUint64x8", argLength: 3, commutative: true},
+ {name: "NotEqualUint8x16", argLength: 2, commutative: true},
+ {name: "NotEqualUint8x32", argLength: 2, commutative: true},
+ {name: "NotEqualUint8x64", argLength: 2, commutative: true},
+ {name: "NotEqualUint16x8", argLength: 2, commutative: true},
+ {name: "NotEqualUint16x16", argLength: 2, commutative: true},
+ {name: "NotEqualUint16x32", argLength: 2, commutative: true},
+ {name: "NotEqualUint32x4", argLength: 2, commutative: true},
+ {name: "NotEqualUint32x8", argLength: 2, commutative: true},
+ {name: "NotEqualUint32x16", argLength: 2, commutative: true},
+ {name: "NotEqualUint64x2", argLength: 2, commutative: true},
+ {name: "NotEqualUint64x4", argLength: 2, commutative: true},
+ {name: "NotEqualUint64x8", argLength: 2, commutative: true},
+ {name: "OrInt8x16", argLength: 2, commutative: true},
+ {name: "OrInt8x32", argLength: 2, commutative: true},
+ {name: "OrInt16x8", argLength: 2, commutative: true},
+ {name: "OrInt16x16", argLength: 2, commutative: true},
+ {name: "OrInt32x4", argLength: 2, commutative: true},
+ {name: "OrInt32x8", argLength: 2, commutative: true},
{name: "OrInt32x16", argLength: 2, commutative: true},
+ {name: "OrInt64x2", argLength: 2, commutative: true},
+ {name: "OrInt64x4", argLength: 2, commutative: true},
+ {name: "OrInt64x8", argLength: 2, commutative: true},
+ {name: "OrMaskedInt32x4", argLength: 3, commutative: true},
+ {name: "OrMaskedInt32x8", argLength: 3, commutative: true},
{name: "OrMaskedInt32x16", argLength: 3, commutative: true},
+ {name: "OrMaskedInt64x2", argLength: 3, commutative: true},
+ {name: "OrMaskedInt64x4", argLength: 3, commutative: true},
+ {name: "OrMaskedInt64x8", argLength: 3, commutative: true},
+ {name: "OrMaskedUint32x4", argLength: 3, commutative: true},
+ {name: "OrMaskedUint32x8", argLength: 3, commutative: true},
+ {name: "OrMaskedUint32x16", argLength: 3, commutative: true},
+ {name: "OrMaskedUint64x2", argLength: 3, commutative: true},
+ {name: "OrMaskedUint64x4", argLength: 3, commutative: true},
+ {name: "OrMaskedUint64x8", argLength: 3, commutative: true},
+ {name: "OrUint8x16", argLength: 2, commutative: true},
+ {name: "OrUint8x32", argLength: 2, commutative: true},
+ {name: "OrUint16x8", argLength: 2, commutative: true},
+ {name: "OrUint16x16", argLength: 2, commutative: true},
+ {name: "OrUint32x4", argLength: 2, commutative: true},
+ {name: "OrUint32x8", argLength: 2, commutative: true},
+ {name: "OrUint32x16", argLength: 2, commutative: true},
+ {name: "OrUint64x2", argLength: 2, commutative: true},
+ {name: "OrUint64x4", argLength: 2, commutative: true},
+ {name: "OrUint64x8", argLength: 2, commutative: true},
+ {name: "PairDotProdAccumulateInt32x4", argLength: 3, commutative: false},
+ {name: "PairDotProdAccumulateInt32x8", argLength: 3, commutative: false},
{name: "PairDotProdAccumulateInt32x16", argLength: 3, commutative: false},
+ {name: "PairDotProdAccumulateMaskedInt32x4", argLength: 4, commutative: false},
+ {name: "PairDotProdAccumulateMaskedInt32x8", argLength: 4, commutative: false},
{name: "PairDotProdAccumulateMaskedInt32x16", argLength: 4, commutative: false},
- {name: "PopCountInt32x16", argLength: 1, commutative: false},
- {name: "PopCountMaskedInt32x16", argLength: 2, commutative: false},
- {name: "RotateLeftInt32x16", argLength: 2, commutative: false},
- {name: "RotateLeftMaskedInt32x16", argLength: 3, commutative: false},
- {name: "RotateRightInt32x16", argLength: 2, commutative: false},
- {name: "RotateRightMaskedInt32x16", argLength: 3, commutative: false},
- {name: "SaturatedPairDotProdAccumulateInt32x16", argLength: 3, commutative: false},
- {name: "SaturatedPairDotProdAccumulateMaskedInt32x16", argLength: 4, commutative: false},
- {name: "SaturatedUnsignedSignedQuadDotProdAccumulateInt32x16", argLength: 3, commutative: false},
- {name: "SaturatedUnsignedSignedQuadDotProdAccumulateMaskedInt32x16", argLength: 4, commutative: false},
- {name: "ShiftAllLeftInt32x16", argLength: 2, commutative: false},
- {name: "ShiftAllLeftMaskedInt32x16", argLength: 3, commutative: false},
- {name: "ShiftAllRightInt32x16", argLength: 2, commutative: false},
- {name: "ShiftAllRightMaskedInt32x16", argLength: 3, commutative: false},
- {name: "ShiftLeftInt32x16", argLength: 2, commutative: false},
- {name: "ShiftLeftAndFillUpperFromInt32x16", argLength: 3, commutative: false},
- {name: "ShiftLeftAndFillUpperFromMaskedInt32x16", argLength: 4, commutative: false},
- {name: "ShiftLeftMaskedInt32x16", argLength: 3, commutative: false},
- {name: "ShiftRightInt32x16", argLength: 2, commutative: false},
- {name: "ShiftRightAndFillUpperFromInt32x16", argLength: 3, commutative: false},
- {name: "ShiftRightAndFillUpperFromMaskedInt32x16", argLength: 4, commutative: false},
- {name: "ShiftRightMaskedInt32x16", argLength: 3, commutative: false},
- {name: "SubInt32x16", argLength: 2, commutative: false},
- {name: "SubMaskedInt32x16", argLength: 3, commutative: false},
- {name: "UnsignedSignedQuadDotProdAccumulateInt32x16", argLength: 3, commutative: false},
- {name: "UnsignedSignedQuadDotProdAccumulateMaskedInt32x16", argLength: 4, commutative: false},
- {name: "XorInt32x16", argLength: 2, commutative: true},
- {name: "XorMaskedInt32x16", argLength: 3, commutative: true},
- {name: "AbsoluteInt32x4", argLength: 1, commutative: false},
- {name: "AbsoluteMaskedInt32x4", argLength: 2, commutative: false},
- {name: "AddInt32x4", argLength: 2, commutative: true},
- {name: "AddMaskedInt32x4", argLength: 3, commutative: true},
- {name: "AndInt32x4", argLength: 2, commutative: true},
- {name: "AndMaskedInt32x4", argLength: 3, commutative: true},
- {name: "AndNotInt32x4", argLength: 2, commutative: false},
- {name: "AndNotMaskedInt32x4", argLength: 3, commutative: false},
- {name: "CompressInt32x4", argLength: 2, commutative: false},
- {name: "EqualInt32x4", argLength: 2, commutative: true},
- {name: "EqualMaskedInt32x4", argLength: 3, commutative: true},
- {name: "GreaterInt32x4", argLength: 2, commutative: false},
- {name: "GreaterEqualInt32x4", argLength: 2, commutative: false},
- {name: "GreaterEqualMaskedInt32x4", argLength: 3, commutative: false},
- {name: "GreaterMaskedInt32x4", argLength: 3, commutative: false},
- {name: "LessInt32x4", argLength: 2, commutative: false},
- {name: "LessEqualInt32x4", argLength: 2, commutative: false},
- {name: "LessEqualMaskedInt32x4", argLength: 3, commutative: false},
- {name: "LessMaskedInt32x4", argLength: 3, commutative: false},
- {name: "MaxInt32x4", argLength: 2, commutative: true},
- {name: "MaxMaskedInt32x4", argLength: 3, commutative: true},
- {name: "MinInt32x4", argLength: 2, commutative: true},
- {name: "MinMaskedInt32x4", argLength: 3, commutative: true},
- {name: "MulEvenWidenInt32x4", argLength: 2, commutative: true},
- {name: "MulLowInt32x4", argLength: 2, commutative: true},
- {name: "MulLowMaskedInt32x4", argLength: 3, commutative: true},
- {name: "NotEqualInt32x4", argLength: 2, commutative: true},
- {name: "NotEqualMaskedInt32x4", argLength: 3, commutative: true},
- {name: "OrInt32x4", argLength: 2, commutative: true},
- {name: "OrMaskedInt32x4", argLength: 3, commutative: true},
- {name: "PairDotProdAccumulateInt32x4", argLength: 3, commutative: false},
- {name: "PairDotProdAccumulateMaskedInt32x4", argLength: 4, commutative: false},
+ {name: "PairDotProdInt16x8", argLength: 2, commutative: false},
+ {name: "PairDotProdInt16x16", argLength: 2, commutative: false},
+ {name: "PairDotProdInt16x32", argLength: 2, commutative: false},
+ {name: "PairDotProdMaskedInt16x8", argLength: 3, commutative: false},
+ {name: "PairDotProdMaskedInt16x16", argLength: 3, commutative: false},
+ {name: "PairDotProdMaskedInt16x32", argLength: 3, commutative: false},
+ {name: "PairwiseAddFloat32x4", argLength: 2, commutative: false},
+ {name: "PairwiseAddFloat32x8", argLength: 2, commutative: false},
+ {name: "PairwiseAddFloat64x2", argLength: 2, commutative: false},
+ {name: "PairwiseAddFloat64x4", argLength: 2, commutative: false},
+ {name: "PairwiseAddInt16x8", argLength: 2, commutative: false},
+ {name: "PairwiseAddInt16x16", argLength: 2, commutative: false},
{name: "PairwiseAddInt32x4", argLength: 2, commutative: false},
+ {name: "PairwiseAddInt32x8", argLength: 2, commutative: false},
+ {name: "PairwiseAddUint16x8", argLength: 2, commutative: false},
+ {name: "PairwiseAddUint16x16", argLength: 2, commutative: false},
+ {name: "PairwiseAddUint32x4", argLength: 2, commutative: false},
+ {name: "PairwiseAddUint32x8", argLength: 2, commutative: false},
+ {name: "PairwiseSubFloat32x4", argLength: 2, commutative: false},
+ {name: "PairwiseSubFloat32x8", argLength: 2, commutative: false},
+ {name: "PairwiseSubFloat64x2", argLength: 2, commutative: false},
+ {name: "PairwiseSubFloat64x4", argLength: 2, commutative: false},
+ {name: "PairwiseSubInt16x8", argLength: 2, commutative: false},
+ {name: "PairwiseSubInt16x16", argLength: 2, commutative: false},
{name: "PairwiseSubInt32x4", argLength: 2, commutative: false},
+ {name: "PairwiseSubInt32x8", argLength: 2, commutative: false},
+ {name: "PairwiseSubUint16x8", argLength: 2, commutative: false},
+ {name: "PairwiseSubUint16x16", argLength: 2, commutative: false},
+ {name: "PairwiseSubUint32x4", argLength: 2, commutative: false},
+ {name: "PairwiseSubUint32x8", argLength: 2, commutative: false},
+ {name: "Permute2Float32x4", argLength: 3, commutative: false},
+ {name: "Permute2Float32x8", argLength: 3, commutative: false},
+ {name: "Permute2Float32x16", argLength: 3, commutative: false},
+ {name: "Permute2Float64x2", argLength: 3, commutative: false},
+ {name: "Permute2Float64x4", argLength: 3, commutative: false},
+ {name: "Permute2Float64x8", argLength: 3, commutative: false},
+ {name: "Permute2Int8x16", argLength: 3, commutative: false},
+ {name: "Permute2Int8x32", argLength: 3, commutative: false},
+ {name: "Permute2Int8x64", argLength: 3, commutative: false},
+ {name: "Permute2Int16x8", argLength: 3, commutative: false},
+ {name: "Permute2Int16x16", argLength: 3, commutative: false},
+ {name: "Permute2Int16x32", argLength: 3, commutative: false},
+ {name: "Permute2Int32x4", argLength: 3, commutative: false},
+ {name: "Permute2Int32x8", argLength: 3, commutative: false},
+ {name: "Permute2Int32x16", argLength: 3, commutative: false},
+ {name: "Permute2Int64x2", argLength: 3, commutative: false},
+ {name: "Permute2Int64x4", argLength: 3, commutative: false},
+ {name: "Permute2Int64x8", argLength: 3, commutative: false},
+ {name: "Permute2MaskedFloat32x4", argLength: 4, commutative: false},
+ {name: "Permute2MaskedFloat32x8", argLength: 4, commutative: false},
+ {name: "Permute2MaskedFloat32x16", argLength: 4, commutative: false},
+ {name: "Permute2MaskedFloat64x2", argLength: 4, commutative: false},
+ {name: "Permute2MaskedFloat64x4", argLength: 4, commutative: false},
+ {name: "Permute2MaskedFloat64x8", argLength: 4, commutative: false},
+ {name: "Permute2MaskedInt8x16", argLength: 4, commutative: false},
+ {name: "Permute2MaskedInt8x32", argLength: 4, commutative: false},
+ {name: "Permute2MaskedInt8x64", argLength: 4, commutative: false},
+ {name: "Permute2MaskedInt16x8", argLength: 4, commutative: false},
+ {name: "Permute2MaskedInt16x16", argLength: 4, commutative: false},
+ {name: "Permute2MaskedInt16x32", argLength: 4, commutative: false},
+ {name: "Permute2MaskedInt32x4", argLength: 4, commutative: false},
+ {name: "Permute2MaskedInt32x8", argLength: 4, commutative: false},
+ {name: "Permute2MaskedInt32x16", argLength: 4, commutative: false},
+ {name: "Permute2MaskedInt64x2", argLength: 4, commutative: false},
+ {name: "Permute2MaskedInt64x4", argLength: 4, commutative: false},
+ {name: "Permute2MaskedInt64x8", argLength: 4, commutative: false},
+ {name: "Permute2MaskedUint8x16", argLength: 4, commutative: false},
+ {name: "Permute2MaskedUint8x32", argLength: 4, commutative: false},
+ {name: "Permute2MaskedUint8x64", argLength: 4, commutative: false},
+ {name: "Permute2MaskedUint16x8", argLength: 4, commutative: false},
+ {name: "Permute2MaskedUint16x16", argLength: 4, commutative: false},
+ {name: "Permute2MaskedUint16x32", argLength: 4, commutative: false},
+ {name: "Permute2MaskedUint32x4", argLength: 4, commutative: false},
+ {name: "Permute2MaskedUint32x8", argLength: 4, commutative: false},
+ {name: "Permute2MaskedUint32x16", argLength: 4, commutative: false},
+ {name: "Permute2MaskedUint64x2", argLength: 4, commutative: false},
+ {name: "Permute2MaskedUint64x4", argLength: 4, commutative: false},
+ {name: "Permute2MaskedUint64x8", argLength: 4, commutative: false},
+ {name: "Permute2Uint8x16", argLength: 3, commutative: false},
+ {name: "Permute2Uint8x32", argLength: 3, commutative: false},
+ {name: "Permute2Uint8x64", argLength: 3, commutative: false},
+ {name: "Permute2Uint16x8", argLength: 3, commutative: false},
+ {name: "Permute2Uint16x16", argLength: 3, commutative: false},
+ {name: "Permute2Uint16x32", argLength: 3, commutative: false},
+ {name: "Permute2Uint32x4", argLength: 3, commutative: false},
+ {name: "Permute2Uint32x8", argLength: 3, commutative: false},
+ {name: "Permute2Uint32x16", argLength: 3, commutative: false},
+ {name: "Permute2Uint64x2", argLength: 3, commutative: false},
+ {name: "Permute2Uint64x4", argLength: 3, commutative: false},
+ {name: "Permute2Uint64x8", argLength: 3, commutative: false},
+ {name: "PermuteFloat32x8", argLength: 2, commutative: false},
+ {name: "PermuteFloat32x16", argLength: 2, commutative: false},
+ {name: "PermuteFloat64x4", argLength: 2, commutative: false},
+ {name: "PermuteFloat64x8", argLength: 2, commutative: false},
+ {name: "PermuteInt8x16", argLength: 2, commutative: false},
+ {name: "PermuteInt8x32", argLength: 2, commutative: false},
+ {name: "PermuteInt8x64", argLength: 2, commutative: false},
+ {name: "PermuteInt16x8", argLength: 2, commutative: false},
+ {name: "PermuteInt16x16", argLength: 2, commutative: false},
+ {name: "PermuteInt16x32", argLength: 2, commutative: false},
+ {name: "PermuteInt32x8", argLength: 2, commutative: false},
+ {name: "PermuteInt32x16", argLength: 2, commutative: false},
+ {name: "PermuteInt64x4", argLength: 2, commutative: false},
+ {name: "PermuteInt64x8", argLength: 2, commutative: false},
+ {name: "PermuteMaskedFloat32x8", argLength: 3, commutative: false},
+ {name: "PermuteMaskedFloat32x16", argLength: 3, commutative: false},
+ {name: "PermuteMaskedFloat64x4", argLength: 3, commutative: false},
+ {name: "PermuteMaskedFloat64x8", argLength: 3, commutative: false},
+ {name: "PermuteMaskedInt8x16", argLength: 3, commutative: false},
+ {name: "PermuteMaskedInt8x32", argLength: 3, commutative: false},
+ {name: "PermuteMaskedInt8x64", argLength: 3, commutative: false},
+ {name: "PermuteMaskedInt16x8", argLength: 3, commutative: false},
+ {name: "PermuteMaskedInt16x16", argLength: 3, commutative: false},
+ {name: "PermuteMaskedInt16x32", argLength: 3, commutative: false},
+ {name: "PermuteMaskedInt32x8", argLength: 3, commutative: false},
+ {name: "PermuteMaskedInt32x16", argLength: 3, commutative: false},
+ {name: "PermuteMaskedInt64x4", argLength: 3, commutative: false},
+ {name: "PermuteMaskedInt64x8", argLength: 3, commutative: false},
+ {name: "PermuteMaskedUint8x16", argLength: 3, commutative: false},
+ {name: "PermuteMaskedUint8x32", argLength: 3, commutative: false},
+ {name: "PermuteMaskedUint8x64", argLength: 3, commutative: false},
+ {name: "PermuteMaskedUint16x8", argLength: 3, commutative: false},
+ {name: "PermuteMaskedUint16x16", argLength: 3, commutative: false},
+ {name: "PermuteMaskedUint16x32", argLength: 3, commutative: false},
+ {name: "PermuteMaskedUint32x8", argLength: 3, commutative: false},
+ {name: "PermuteMaskedUint32x16", argLength: 3, commutative: false},
+ {name: "PermuteMaskedUint64x4", argLength: 3, commutative: false},
+ {name: "PermuteMaskedUint64x8", argLength: 3, commutative: false},
+ {name: "PermuteUint8x16", argLength: 2, commutative: false},
+ {name: "PermuteUint8x32", argLength: 2, commutative: false},
+ {name: "PermuteUint8x64", argLength: 2, commutative: false},
+ {name: "PermuteUint16x8", argLength: 2, commutative: false},
+ {name: "PermuteUint16x16", argLength: 2, commutative: false},
+ {name: "PermuteUint16x32", argLength: 2, commutative: false},
+ {name: "PermuteUint32x8", argLength: 2, commutative: false},
+ {name: "PermuteUint32x16", argLength: 2, commutative: false},
+ {name: "PermuteUint64x4", argLength: 2, commutative: false},
+ {name: "PermuteUint64x8", argLength: 2, commutative: false},
+ {name: "PopCountInt8x16", argLength: 1, commutative: false},
+ {name: "PopCountInt8x32", argLength: 1, commutative: false},
+ {name: "PopCountInt8x64", argLength: 1, commutative: false},
+ {name: "PopCountInt16x8", argLength: 1, commutative: false},
+ {name: "PopCountInt16x16", argLength: 1, commutative: false},
+ {name: "PopCountInt16x32", argLength: 1, commutative: false},
{name: "PopCountInt32x4", argLength: 1, commutative: false},
+ {name: "PopCountInt32x8", argLength: 1, commutative: false},
+ {name: "PopCountInt32x16", argLength: 1, commutative: false},
+ {name: "PopCountInt64x2", argLength: 1, commutative: false},
+ {name: "PopCountInt64x4", argLength: 1, commutative: false},
+ {name: "PopCountInt64x8", argLength: 1, commutative: false},
+ {name: "PopCountMaskedInt8x16", argLength: 2, commutative: false},
+ {name: "PopCountMaskedInt8x32", argLength: 2, commutative: false},
+ {name: "PopCountMaskedInt8x64", argLength: 2, commutative: false},
+ {name: "PopCountMaskedInt16x8", argLength: 2, commutative: false},
+ {name: "PopCountMaskedInt16x16", argLength: 2, commutative: false},
+ {name: "PopCountMaskedInt16x32", argLength: 2, commutative: false},
{name: "PopCountMaskedInt32x4", argLength: 2, commutative: false},
+ {name: "PopCountMaskedInt32x8", argLength: 2, commutative: false},
+ {name: "PopCountMaskedInt32x16", argLength: 2, commutative: false},
+ {name: "PopCountMaskedInt64x2", argLength: 2, commutative: false},
+ {name: "PopCountMaskedInt64x4", argLength: 2, commutative: false},
+ {name: "PopCountMaskedInt64x8", argLength: 2, commutative: false},
+ {name: "PopCountMaskedUint8x16", argLength: 2, commutative: false},
+ {name: "PopCountMaskedUint8x32", argLength: 2, commutative: false},
+ {name: "PopCountMaskedUint8x64", argLength: 2, commutative: false},
+ {name: "PopCountMaskedUint16x8", argLength: 2, commutative: false},
+ {name: "PopCountMaskedUint16x16", argLength: 2, commutative: false},
+ {name: "PopCountMaskedUint16x32", argLength: 2, commutative: false},
+ {name: "PopCountMaskedUint32x4", argLength: 2, commutative: false},
+ {name: "PopCountMaskedUint32x8", argLength: 2, commutative: false},
+ {name: "PopCountMaskedUint32x16", argLength: 2, commutative: false},
+ {name: "PopCountMaskedUint64x2", argLength: 2, commutative: false},
+ {name: "PopCountMaskedUint64x4", argLength: 2, commutative: false},
+ {name: "PopCountMaskedUint64x8", argLength: 2, commutative: false},
+ {name: "PopCountUint8x16", argLength: 1, commutative: false},
+ {name: "PopCountUint8x32", argLength: 1, commutative: false},
+ {name: "PopCountUint8x64", argLength: 1, commutative: false},
+ {name: "PopCountUint16x8", argLength: 1, commutative: false},
+ {name: "PopCountUint16x16", argLength: 1, commutative: false},
+ {name: "PopCountUint16x32", argLength: 1, commutative: false},
+ {name: "PopCountUint32x4", argLength: 1, commutative: false},
+ {name: "PopCountUint32x8", argLength: 1, commutative: false},
+ {name: "PopCountUint32x16", argLength: 1, commutative: false},
+ {name: "PopCountUint64x2", argLength: 1, commutative: false},
+ {name: "PopCountUint64x4", argLength: 1, commutative: false},
+ {name: "PopCountUint64x8", argLength: 1, commutative: false},
{name: "RotateLeftInt32x4", argLength: 2, commutative: false},
+ {name: "RotateLeftInt32x8", argLength: 2, commutative: false},
+ {name: "RotateLeftInt32x16", argLength: 2, commutative: false},
+ {name: "RotateLeftInt64x2", argLength: 2, commutative: false},
+ {name: "RotateLeftInt64x4", argLength: 2, commutative: false},
+ {name: "RotateLeftInt64x8", argLength: 2, commutative: false},
{name: "RotateLeftMaskedInt32x4", argLength: 3, commutative: false},
+ {name: "RotateLeftMaskedInt32x8", argLength: 3, commutative: false},
+ {name: "RotateLeftMaskedInt32x16", argLength: 3, commutative: false},
+ {name: "RotateLeftMaskedInt64x2", argLength: 3, commutative: false},
+ {name: "RotateLeftMaskedInt64x4", argLength: 3, commutative: false},
+ {name: "RotateLeftMaskedInt64x8", argLength: 3, commutative: false},
+ {name: "RotateLeftMaskedUint32x4", argLength: 3, commutative: false},
+ {name: "RotateLeftMaskedUint32x8", argLength: 3, commutative: false},
+ {name: "RotateLeftMaskedUint32x16", argLength: 3, commutative: false},
+ {name: "RotateLeftMaskedUint64x2", argLength: 3, commutative: false},
+ {name: "RotateLeftMaskedUint64x4", argLength: 3, commutative: false},
+ {name: "RotateLeftMaskedUint64x8", argLength: 3, commutative: false},
+ {name: "RotateLeftUint32x4", argLength: 2, commutative: false},
+ {name: "RotateLeftUint32x8", argLength: 2, commutative: false},
+ {name: "RotateLeftUint32x16", argLength: 2, commutative: false},
+ {name: "RotateLeftUint64x2", argLength: 2, commutative: false},
+ {name: "RotateLeftUint64x4", argLength: 2, commutative: false},
+ {name: "RotateLeftUint64x8", argLength: 2, commutative: false},
{name: "RotateRightInt32x4", argLength: 2, commutative: false},
+ {name: "RotateRightInt32x8", argLength: 2, commutative: false},
+ {name: "RotateRightInt32x16", argLength: 2, commutative: false},
+ {name: "RotateRightInt64x2", argLength: 2, commutative: false},
+ {name: "RotateRightInt64x4", argLength: 2, commutative: false},
+ {name: "RotateRightInt64x8", argLength: 2, commutative: false},
{name: "RotateRightMaskedInt32x4", argLength: 3, commutative: false},
- {name: "SaturatedPairDotProdAccumulateInt32x4", argLength: 3, commutative: false},
- {name: "SaturatedPairDotProdAccumulateMaskedInt32x4", argLength: 4, commutative: false},
- {name: "SaturatedUnsignedSignedQuadDotProdAccumulateInt32x4", argLength: 3, commutative: false},
- {name: "SaturatedUnsignedSignedQuadDotProdAccumulateMaskedInt32x4", argLength: 4, commutative: false},
- {name: "ShiftAllLeftInt32x4", argLength: 2, commutative: false},
- {name: "ShiftAllLeftMaskedInt32x4", argLength: 3, commutative: false},
- {name: "ShiftAllRightInt32x4", argLength: 2, commutative: false},
- {name: "ShiftAllRightMaskedInt32x4", argLength: 3, commutative: false},
- {name: "ShiftLeftInt32x4", argLength: 2, commutative: false},
- {name: "ShiftLeftAndFillUpperFromInt32x4", argLength: 3, commutative: false},
- {name: "ShiftLeftAndFillUpperFromMaskedInt32x4", argLength: 4, commutative: false},
- {name: "ShiftLeftMaskedInt32x4", argLength: 3, commutative: false},
- {name: "ShiftRightInt32x4", argLength: 2, commutative: false},
- {name: "ShiftRightAndFillUpperFromInt32x4", argLength: 3, commutative: false},
- {name: "ShiftRightAndFillUpperFromMaskedInt32x4", argLength: 4, commutative: false},
- {name: "ShiftRightMaskedInt32x4", argLength: 3, commutative: false},
- {name: "SignInt32x4", argLength: 2, commutative: false},
- {name: "SubInt32x4", argLength: 2, commutative: false},
- {name: "SubMaskedInt32x4", argLength: 3, commutative: false},
- {name: "UnsignedSignedQuadDotProdAccumulateInt32x4", argLength: 3, commutative: false},
- {name: "UnsignedSignedQuadDotProdAccumulateMaskedInt32x4", argLength: 4, commutative: false},
- {name: "XorInt32x4", argLength: 2, commutative: true},
- {name: "XorMaskedInt32x4", argLength: 3, commutative: true},
- {name: "AbsoluteInt32x8", argLength: 1, commutative: false},
- {name: "AbsoluteMaskedInt32x8", argLength: 2, commutative: false},
- {name: "AddInt32x8", argLength: 2, commutative: true},
- {name: "AddMaskedInt32x8", argLength: 3, commutative: true},
- {name: "AndInt32x8", argLength: 2, commutative: true},
- {name: "AndMaskedInt32x8", argLength: 3, commutative: true},
- {name: "AndNotInt32x8", argLength: 2, commutative: false},
- {name: "AndNotMaskedInt32x8", argLength: 3, commutative: false},
- {name: "CompressInt32x8", argLength: 2, commutative: false},
- {name: "EqualInt32x8", argLength: 2, commutative: true},
- {name: "EqualMaskedInt32x8", argLength: 3, commutative: true},
- {name: "GreaterInt32x8", argLength: 2, commutative: false},
- {name: "GreaterEqualInt32x8", argLength: 2, commutative: false},
- {name: "GreaterEqualMaskedInt32x8", argLength: 3, commutative: false},
- {name: "GreaterMaskedInt32x8", argLength: 3, commutative: false},
- {name: "LessInt32x8", argLength: 2, commutative: false},
- {name: "LessEqualInt32x8", argLength: 2, commutative: false},
- {name: "LessEqualMaskedInt32x8", argLength: 3, commutative: false},
- {name: "LessMaskedInt32x8", argLength: 3, commutative: false},
- {name: "MaxInt32x8", argLength: 2, commutative: true},
- {name: "MaxMaskedInt32x8", argLength: 3, commutative: true},
- {name: "MinInt32x8", argLength: 2, commutative: true},
- {name: "MinMaskedInt32x8", argLength: 3, commutative: true},
- {name: "MulEvenWidenInt32x8", argLength: 2, commutative: true},
- {name: "MulLowInt32x8", argLength: 2, commutative: true},
- {name: "MulLowMaskedInt32x8", argLength: 3, commutative: true},
- {name: "NotEqualInt32x8", argLength: 2, commutative: true},
- {name: "NotEqualMaskedInt32x8", argLength: 3, commutative: true},
- {name: "OrInt32x8", argLength: 2, commutative: true},
- {name: "OrMaskedInt32x8", argLength: 3, commutative: true},
- {name: "PairDotProdAccumulateInt32x8", argLength: 3, commutative: false},
- {name: "PairDotProdAccumulateMaskedInt32x8", argLength: 4, commutative: false},
- {name: "PairwiseAddInt32x8", argLength: 2, commutative: false},
- {name: "PairwiseSubInt32x8", argLength: 2, commutative: false},
- {name: "PopCountInt32x8", argLength: 1, commutative: false},
- {name: "PopCountMaskedInt32x8", argLength: 2, commutative: false},
- {name: "RotateLeftInt32x8", argLength: 2, commutative: false},
- {name: "RotateLeftMaskedInt32x8", argLength: 3, commutative: false},
- {name: "RotateRightInt32x8", argLength: 2, commutative: false},
{name: "RotateRightMaskedInt32x8", argLength: 3, commutative: false},
+ {name: "RotateRightMaskedInt32x16", argLength: 3, commutative: false},
+ {name: "RotateRightMaskedInt64x2", argLength: 3, commutative: false},
+ {name: "RotateRightMaskedInt64x4", argLength: 3, commutative: false},
+ {name: "RotateRightMaskedInt64x8", argLength: 3, commutative: false},
+ {name: "RotateRightMaskedUint32x4", argLength: 3, commutative: false},
+ {name: "RotateRightMaskedUint32x8", argLength: 3, commutative: false},
+ {name: "RotateRightMaskedUint32x16", argLength: 3, commutative: false},
+ {name: "RotateRightMaskedUint64x2", argLength: 3, commutative: false},
+ {name: "RotateRightMaskedUint64x4", argLength: 3, commutative: false},
+ {name: "RotateRightMaskedUint64x8", argLength: 3, commutative: false},
+ {name: "RotateRightUint32x4", argLength: 2, commutative: false},
+ {name: "RotateRightUint32x8", argLength: 2, commutative: false},
+ {name: "RotateRightUint32x16", argLength: 2, commutative: false},
+ {name: "RotateRightUint64x2", argLength: 2, commutative: false},
+ {name: "RotateRightUint64x4", argLength: 2, commutative: false},
+ {name: "RotateRightUint64x8", argLength: 2, commutative: false},
+ {name: "RoundFloat32x4", argLength: 1, commutative: false},
+ {name: "RoundFloat32x8", argLength: 1, commutative: false},
+ {name: "RoundFloat64x2", argLength: 1, commutative: false},
+ {name: "RoundFloat64x4", argLength: 1, commutative: false},
+ {name: "SaturatedAddInt8x16", argLength: 2, commutative: true},
+ {name: "SaturatedAddInt8x32", argLength: 2, commutative: true},
+ {name: "SaturatedAddInt8x64", argLength: 2, commutative: true},
+ {name: "SaturatedAddInt16x8", argLength: 2, commutative: true},
+ {name: "SaturatedAddInt16x16", argLength: 2, commutative: true},
+ {name: "SaturatedAddInt16x32", argLength: 2, commutative: true},
+ {name: "SaturatedAddMaskedInt8x16", argLength: 3, commutative: true},
+ {name: "SaturatedAddMaskedInt8x32", argLength: 3, commutative: true},
+ {name: "SaturatedAddMaskedInt8x64", argLength: 3, commutative: true},
+ {name: "SaturatedAddMaskedInt16x8", argLength: 3, commutative: true},
+ {name: "SaturatedAddMaskedInt16x16", argLength: 3, commutative: true},
+ {name: "SaturatedAddMaskedInt16x32", argLength: 3, commutative: true},
+ {name: "SaturatedAddMaskedUint8x16", argLength: 3, commutative: true},
+ {name: "SaturatedAddMaskedUint8x32", argLength: 3, commutative: true},
+ {name: "SaturatedAddMaskedUint8x64", argLength: 3, commutative: true},
+ {name: "SaturatedAddMaskedUint16x8", argLength: 3, commutative: true},
+ {name: "SaturatedAddMaskedUint16x16", argLength: 3, commutative: true},
+ {name: "SaturatedAddMaskedUint16x32", argLength: 3, commutative: true},
+ {name: "SaturatedAddUint8x16", argLength: 2, commutative: true},
+ {name: "SaturatedAddUint8x32", argLength: 2, commutative: true},
+ {name: "SaturatedAddUint8x64", argLength: 2, commutative: true},
+ {name: "SaturatedAddUint16x8", argLength: 2, commutative: true},
+ {name: "SaturatedAddUint16x16", argLength: 2, commutative: true},
+ {name: "SaturatedAddUint16x32", argLength: 2, commutative: true},
+ {name: "SaturatedPairDotProdAccumulateInt32x4", argLength: 3, commutative: false},
{name: "SaturatedPairDotProdAccumulateInt32x8", argLength: 3, commutative: false},
+ {name: "SaturatedPairDotProdAccumulateInt32x16", argLength: 3, commutative: false},
+ {name: "SaturatedPairDotProdAccumulateMaskedInt32x4", argLength: 4, commutative: false},
{name: "SaturatedPairDotProdAccumulateMaskedInt32x8", argLength: 4, commutative: false},
+ {name: "SaturatedPairDotProdAccumulateMaskedInt32x16", argLength: 4, commutative: false},
+ {name: "SaturatedPairwiseAddInt16x8", argLength: 2, commutative: false},
+ {name: "SaturatedPairwiseAddInt16x16", argLength: 2, commutative: false},
+ {name: "SaturatedPairwiseSubInt16x8", argLength: 2, commutative: false},
+ {name: "SaturatedPairwiseSubInt16x16", argLength: 2, commutative: false},
+ {name: "SaturatedSubInt8x16", argLength: 2, commutative: false},
+ {name: "SaturatedSubInt8x32", argLength: 2, commutative: false},
+ {name: "SaturatedSubInt8x64", argLength: 2, commutative: false},
+ {name: "SaturatedSubInt16x8", argLength: 2, commutative: false},
+ {name: "SaturatedSubInt16x16", argLength: 2, commutative: false},
+ {name: "SaturatedSubInt16x32", argLength: 2, commutative: false},
+ {name: "SaturatedSubMaskedInt8x16", argLength: 3, commutative: false},
+ {name: "SaturatedSubMaskedInt8x32", argLength: 3, commutative: false},
+ {name: "SaturatedSubMaskedInt8x64", argLength: 3, commutative: false},
+ {name: "SaturatedSubMaskedInt16x8", argLength: 3, commutative: false},
+ {name: "SaturatedSubMaskedInt16x16", argLength: 3, commutative: false},
+ {name: "SaturatedSubMaskedInt16x32", argLength: 3, commutative: false},
+ {name: "SaturatedSubMaskedUint8x16", argLength: 3, commutative: false},
+ {name: "SaturatedSubMaskedUint8x32", argLength: 3, commutative: false},
+ {name: "SaturatedSubMaskedUint8x64", argLength: 3, commutative: false},
+ {name: "SaturatedSubMaskedUint16x8", argLength: 3, commutative: false},
+ {name: "SaturatedSubMaskedUint16x16", argLength: 3, commutative: false},
+ {name: "SaturatedSubMaskedUint16x32", argLength: 3, commutative: false},
+ {name: "SaturatedSubUint8x16", argLength: 2, commutative: false},
+ {name: "SaturatedSubUint8x32", argLength: 2, commutative: false},
+ {name: "SaturatedSubUint8x64", argLength: 2, commutative: false},
+ {name: "SaturatedSubUint16x8", argLength: 2, commutative: false},
+ {name: "SaturatedSubUint16x16", argLength: 2, commutative: false},
+ {name: "SaturatedSubUint16x32", argLength: 2, commutative: false},
+ {name: "SaturatedUnsignedSignedPairDotProdMaskedUint8x16", argLength: 3, commutative: false},
+ {name: "SaturatedUnsignedSignedPairDotProdMaskedUint8x32", argLength: 3, commutative: false},
+ {name: "SaturatedUnsignedSignedPairDotProdMaskedUint8x64", argLength: 3, commutative: false},
+ {name: "SaturatedUnsignedSignedPairDotProdUint8x16", argLength: 2, commutative: false},
+ {name: "SaturatedUnsignedSignedPairDotProdUint8x32", argLength: 2, commutative: false},
+ {name: "SaturatedUnsignedSignedPairDotProdUint8x64", argLength: 2, commutative: false},
+ {name: "SaturatedUnsignedSignedQuadDotProdAccumulateInt32x4", argLength: 3, commutative: false},
{name: "SaturatedUnsignedSignedQuadDotProdAccumulateInt32x8", argLength: 3, commutative: false},
+ {name: "SaturatedUnsignedSignedQuadDotProdAccumulateInt32x16", argLength: 3, commutative: false},
+ {name: "SaturatedUnsignedSignedQuadDotProdAccumulateMaskedInt32x4", argLength: 4, commutative: false},
{name: "SaturatedUnsignedSignedQuadDotProdAccumulateMaskedInt32x8", argLength: 4, commutative: false},
+ {name: "SaturatedUnsignedSignedQuadDotProdAccumulateMaskedInt32x16", argLength: 4, commutative: false},
+ {name: "ShiftAllLeftInt16x8", argLength: 2, commutative: false},
+ {name: "ShiftAllLeftInt16x16", argLength: 2, commutative: false},
+ {name: "ShiftAllLeftInt16x32", argLength: 2, commutative: false},
+ {name: "ShiftAllLeftInt32x4", argLength: 2, commutative: false},
{name: "ShiftAllLeftInt32x8", argLength: 2, commutative: false},
+ {name: "ShiftAllLeftInt32x16", argLength: 2, commutative: false},
+ {name: "ShiftAllLeftInt64x2", argLength: 2, commutative: false},
+ {name: "ShiftAllLeftInt64x4", argLength: 2, commutative: false},
+ {name: "ShiftAllLeftInt64x8", argLength: 2, commutative: false},
+ {name: "ShiftAllLeftMaskedInt16x8", argLength: 3, commutative: false},
+ {name: "ShiftAllLeftMaskedInt16x16", argLength: 3, commutative: false},
+ {name: "ShiftAllLeftMaskedInt16x32", argLength: 3, commutative: false},
+ {name: "ShiftAllLeftMaskedInt32x4", argLength: 3, commutative: false},
{name: "ShiftAllLeftMaskedInt32x8", argLength: 3, commutative: false},
+ {name: "ShiftAllLeftMaskedInt32x16", argLength: 3, commutative: false},
+ {name: "ShiftAllLeftMaskedInt64x2", argLength: 3, commutative: false},
+ {name: "ShiftAllLeftMaskedInt64x4", argLength: 3, commutative: false},
+ {name: "ShiftAllLeftMaskedInt64x8", argLength: 3, commutative: false},
+ {name: "ShiftAllLeftMaskedUint16x8", argLength: 3, commutative: false},
+ {name: "ShiftAllLeftMaskedUint16x16", argLength: 3, commutative: false},
+ {name: "ShiftAllLeftMaskedUint16x32", argLength: 3, commutative: false},
+ {name: "ShiftAllLeftMaskedUint32x4", argLength: 3, commutative: false},
+ {name: "ShiftAllLeftMaskedUint32x8", argLength: 3, commutative: false},
+ {name: "ShiftAllLeftMaskedUint32x16", argLength: 3, commutative: false},
+ {name: "ShiftAllLeftMaskedUint64x2", argLength: 3, commutative: false},
+ {name: "ShiftAllLeftMaskedUint64x4", argLength: 3, commutative: false},
+ {name: "ShiftAllLeftMaskedUint64x8", argLength: 3, commutative: false},
+ {name: "ShiftAllLeftUint16x8", argLength: 2, commutative: false},
+ {name: "ShiftAllLeftUint16x16", argLength: 2, commutative: false},
+ {name: "ShiftAllLeftUint16x32", argLength: 2, commutative: false},
+ {name: "ShiftAllLeftUint32x4", argLength: 2, commutative: false},
+ {name: "ShiftAllLeftUint32x8", argLength: 2, commutative: false},
+ {name: "ShiftAllLeftUint32x16", argLength: 2, commutative: false},
+ {name: "ShiftAllLeftUint64x2", argLength: 2, commutative: false},
+ {name: "ShiftAllLeftUint64x4", argLength: 2, commutative: false},
+ {name: "ShiftAllLeftUint64x8", argLength: 2, commutative: false},
+ {name: "ShiftAllRightInt16x8", argLength: 2, commutative: false},
+ {name: "ShiftAllRightInt16x16", argLength: 2, commutative: false},
+ {name: "ShiftAllRightInt16x32", argLength: 2, commutative: false},
+ {name: "ShiftAllRightInt32x4", argLength: 2, commutative: false},
{name: "ShiftAllRightInt32x8", argLength: 2, commutative: false},
+ {name: "ShiftAllRightInt32x16", argLength: 2, commutative: false},
+ {name: "ShiftAllRightInt64x2", argLength: 2, commutative: false},
+ {name: "ShiftAllRightInt64x4", argLength: 2, commutative: false},
+ {name: "ShiftAllRightInt64x8", argLength: 2, commutative: false},
+ {name: "ShiftAllRightMaskedInt16x8", argLength: 3, commutative: false},
+ {name: "ShiftAllRightMaskedInt16x16", argLength: 3, commutative: false},
+ {name: "ShiftAllRightMaskedInt16x32", argLength: 3, commutative: false},
+ {name: "ShiftAllRightMaskedInt32x4", argLength: 3, commutative: false},
{name: "ShiftAllRightMaskedInt32x8", argLength: 3, commutative: false},
- {name: "ShiftLeftInt32x8", argLength: 2, commutative: false},
+ {name: "ShiftAllRightMaskedInt32x16", argLength: 3, commutative: false},
+ {name: "ShiftAllRightMaskedInt64x2", argLength: 3, commutative: false},
+ {name: "ShiftAllRightMaskedInt64x4", argLength: 3, commutative: false},
+ {name: "ShiftAllRightMaskedInt64x8", argLength: 3, commutative: false},
+ {name: "ShiftAllRightMaskedUint16x8", argLength: 3, commutative: false},
+ {name: "ShiftAllRightMaskedUint16x16", argLength: 3, commutative: false},
+ {name: "ShiftAllRightMaskedUint16x32", argLength: 3, commutative: false},
+ {name: "ShiftAllRightMaskedUint32x4", argLength: 3, commutative: false},
+ {name: "ShiftAllRightMaskedUint32x8", argLength: 3, commutative: false},
+ {name: "ShiftAllRightMaskedUint32x16", argLength: 3, commutative: false},
+ {name: "ShiftAllRightMaskedUint64x2", argLength: 3, commutative: false},
+ {name: "ShiftAllRightMaskedUint64x4", argLength: 3, commutative: false},
+ {name: "ShiftAllRightMaskedUint64x8", argLength: 3, commutative: false},
+ {name: "ShiftAllRightUint16x8", argLength: 2, commutative: false},
+ {name: "ShiftAllRightUint16x16", argLength: 2, commutative: false},
+ {name: "ShiftAllRightUint16x32", argLength: 2, commutative: false},
+ {name: "ShiftAllRightUint32x4", argLength: 2, commutative: false},
+ {name: "ShiftAllRightUint32x8", argLength: 2, commutative: false},
+ {name: "ShiftAllRightUint32x16", argLength: 2, commutative: false},
+ {name: "ShiftAllRightUint64x2", argLength: 2, commutative: false},
+ {name: "ShiftAllRightUint64x4", argLength: 2, commutative: false},
+ {name: "ShiftAllRightUint64x8", argLength: 2, commutative: false},
+ {name: "ShiftLeftAndFillUpperFromInt16x8", argLength: 3, commutative: false},
+ {name: "ShiftLeftAndFillUpperFromInt16x16", argLength: 3, commutative: false},
+ {name: "ShiftLeftAndFillUpperFromInt16x32", argLength: 3, commutative: false},
+ {name: "ShiftLeftAndFillUpperFromInt32x4", argLength: 3, commutative: false},
{name: "ShiftLeftAndFillUpperFromInt32x8", argLength: 3, commutative: false},
+ {name: "ShiftLeftAndFillUpperFromInt32x16", argLength: 3, commutative: false},
+ {name: "ShiftLeftAndFillUpperFromInt64x2", argLength: 3, commutative: false},
+ {name: "ShiftLeftAndFillUpperFromInt64x4", argLength: 3, commutative: false},
+ {name: "ShiftLeftAndFillUpperFromInt64x8", argLength: 3, commutative: false},
+ {name: "ShiftLeftAndFillUpperFromMaskedInt16x8", argLength: 4, commutative: false},
+ {name: "ShiftLeftAndFillUpperFromMaskedInt16x16", argLength: 4, commutative: false},
+ {name: "ShiftLeftAndFillUpperFromMaskedInt16x32", argLength: 4, commutative: false},
+ {name: "ShiftLeftAndFillUpperFromMaskedInt32x4", argLength: 4, commutative: false},
{name: "ShiftLeftAndFillUpperFromMaskedInt32x8", argLength: 4, commutative: false},
+ {name: "ShiftLeftAndFillUpperFromMaskedInt32x16", argLength: 4, commutative: false},
+ {name: "ShiftLeftAndFillUpperFromMaskedInt64x2", argLength: 4, commutative: false},
+ {name: "ShiftLeftAndFillUpperFromMaskedInt64x4", argLength: 4, commutative: false},
+ {name: "ShiftLeftAndFillUpperFromMaskedInt64x8", argLength: 4, commutative: false},
+ {name: "ShiftLeftAndFillUpperFromMaskedUint16x8", argLength: 4, commutative: false},
+ {name: "ShiftLeftAndFillUpperFromMaskedUint16x16", argLength: 4, commutative: false},
+ {name: "ShiftLeftAndFillUpperFromMaskedUint16x32", argLength: 4, commutative: false},
+ {name: "ShiftLeftAndFillUpperFromMaskedUint32x4", argLength: 4, commutative: false},
+ {name: "ShiftLeftAndFillUpperFromMaskedUint32x8", argLength: 4, commutative: false},
+ {name: "ShiftLeftAndFillUpperFromMaskedUint32x16", argLength: 4, commutative: false},
+ {name: "ShiftLeftAndFillUpperFromMaskedUint64x2", argLength: 4, commutative: false},
+ {name: "ShiftLeftAndFillUpperFromMaskedUint64x4", argLength: 4, commutative: false},
+ {name: "ShiftLeftAndFillUpperFromMaskedUint64x8", argLength: 4, commutative: false},
+ {name: "ShiftLeftAndFillUpperFromUint16x8", argLength: 3, commutative: false},
+ {name: "ShiftLeftAndFillUpperFromUint16x16", argLength: 3, commutative: false},
+ {name: "ShiftLeftAndFillUpperFromUint16x32", argLength: 3, commutative: false},
+ {name: "ShiftLeftAndFillUpperFromUint32x4", argLength: 3, commutative: false},
+ {name: "ShiftLeftAndFillUpperFromUint32x8", argLength: 3, commutative: false},
+ {name: "ShiftLeftAndFillUpperFromUint32x16", argLength: 3, commutative: false},
+ {name: "ShiftLeftAndFillUpperFromUint64x2", argLength: 3, commutative: false},
+ {name: "ShiftLeftAndFillUpperFromUint64x4", argLength: 3, commutative: false},
+ {name: "ShiftLeftAndFillUpperFromUint64x8", argLength: 3, commutative: false},
+ {name: "ShiftLeftInt16x8", argLength: 2, commutative: false},
+ {name: "ShiftLeftInt16x16", argLength: 2, commutative: false},
+ {name: "ShiftLeftInt16x32", argLength: 2, commutative: false},
+ {name: "ShiftLeftInt32x4", argLength: 2, commutative: false},
+ {name: "ShiftLeftInt32x8", argLength: 2, commutative: false},
+ {name: "ShiftLeftInt32x16", argLength: 2, commutative: false},
+ {name: "ShiftLeftInt64x2", argLength: 2, commutative: false},
+ {name: "ShiftLeftInt64x4", argLength: 2, commutative: false},
+ {name: "ShiftLeftInt64x8", argLength: 2, commutative: false},
+ {name: "ShiftLeftMaskedInt16x8", argLength: 3, commutative: false},
+ {name: "ShiftLeftMaskedInt16x16", argLength: 3, commutative: false},
+ {name: "ShiftLeftMaskedInt16x32", argLength: 3, commutative: false},
+ {name: "ShiftLeftMaskedInt32x4", argLength: 3, commutative: false},
{name: "ShiftLeftMaskedInt32x8", argLength: 3, commutative: false},
- {name: "ShiftRightInt32x8", argLength: 2, commutative: false},
- {name: "ShiftRightAndFillUpperFromInt32x8", argLength: 3, commutative: false},
- {name: "ShiftRightAndFillUpperFromMaskedInt32x8", argLength: 4, commutative: false},
- {name: "ShiftRightMaskedInt32x8", argLength: 3, commutative: false},
- {name: "SignInt32x8", argLength: 2, commutative: false},
- {name: "SubInt32x8", argLength: 2, commutative: false},
- {name: "SubMaskedInt32x8", argLength: 3, commutative: false},
- {name: "UnsignedSignedQuadDotProdAccumulateInt32x8", argLength: 3, commutative: false},
- {name: "UnsignedSignedQuadDotProdAccumulateMaskedInt32x8", argLength: 4, commutative: false},
- {name: "XorInt32x8", argLength: 2, commutative: true},
- {name: "XorMaskedInt32x8", argLength: 3, commutative: true},
- {name: "AbsoluteInt64x2", argLength: 1, commutative: false},
- {name: "AbsoluteMaskedInt64x2", argLength: 2, commutative: false},
- {name: "AddInt64x2", argLength: 2, commutative: true},
- {name: "AddMaskedInt64x2", argLength: 3, commutative: true},
- {name: "AndInt64x2", argLength: 2, commutative: true},
- {name: "AndMaskedInt64x2", argLength: 3, commutative: true},
- {name: "AndNotInt64x2", argLength: 2, commutative: false},
- {name: "AndNotMaskedInt64x2", argLength: 3, commutative: false},
- {name: "CompressInt64x2", argLength: 2, commutative: false},
- {name: "EqualInt64x2", argLength: 2, commutative: true},
- {name: "EqualMaskedInt64x2", argLength: 3, commutative: true},
- {name: "GreaterInt64x2", argLength: 2, commutative: false},
- {name: "GreaterEqualInt64x2", argLength: 2, commutative: false},
- {name: "GreaterEqualMaskedInt64x2", argLength: 3, commutative: false},
- {name: "GreaterMaskedInt64x2", argLength: 3, commutative: false},
- {name: "LessInt64x2", argLength: 2, commutative: false},
- {name: "LessEqualInt64x2", argLength: 2, commutative: false},
- {name: "LessEqualMaskedInt64x2", argLength: 3, commutative: false},
- {name: "LessMaskedInt64x2", argLength: 3, commutative: false},
- {name: "MaxInt64x2", argLength: 2, commutative: true},
- {name: "MaxMaskedInt64x2", argLength: 3, commutative: true},
- {name: "MinInt64x2", argLength: 2, commutative: true},
- {name: "MinMaskedInt64x2", argLength: 3, commutative: true},
- {name: "MulEvenWidenInt64x2", argLength: 2, commutative: true},
- {name: "MulEvenWidenMaskedInt64x2", argLength: 3, commutative: true},
- {name: "MulLowInt64x2", argLength: 2, commutative: true},
- {name: "MulLowMaskedInt64x2", argLength: 3, commutative: true},
- {name: "NotEqualInt64x2", argLength: 2, commutative: true},
- {name: "NotEqualMaskedInt64x2", argLength: 3, commutative: true},
- {name: "OrInt64x2", argLength: 2, commutative: true},
- {name: "OrMaskedInt64x2", argLength: 3, commutative: true},
- {name: "PopCountInt64x2", argLength: 1, commutative: false},
- {name: "PopCountMaskedInt64x2", argLength: 2, commutative: false},
- {name: "RotateLeftInt64x2", argLength: 2, commutative: false},
- {name: "RotateLeftMaskedInt64x2", argLength: 3, commutative: false},
- {name: "RotateRightInt64x2", argLength: 2, commutative: false},
- {name: "RotateRightMaskedInt64x2", argLength: 3, commutative: false},
- {name: "ShiftAllLeftInt64x2", argLength: 2, commutative: false},
- {name: "ShiftAllLeftMaskedInt64x2", argLength: 3, commutative: false},
- {name: "ShiftAllRightInt64x2", argLength: 2, commutative: false},
- {name: "ShiftAllRightMaskedInt64x2", argLength: 3, commutative: false},
- {name: "ShiftLeftInt64x2", argLength: 2, commutative: false},
- {name: "ShiftLeftAndFillUpperFromInt64x2", argLength: 3, commutative: false},
- {name: "ShiftLeftAndFillUpperFromMaskedInt64x2", argLength: 4, commutative: false},
+ {name: "ShiftLeftMaskedInt32x16", argLength: 3, commutative: false},
{name: "ShiftLeftMaskedInt64x2", argLength: 3, commutative: false},
- {name: "ShiftRightInt64x2", argLength: 2, commutative: false},
- {name: "ShiftRightAndFillUpperFromInt64x2", argLength: 3, commutative: false},
- {name: "ShiftRightAndFillUpperFromMaskedInt64x2", argLength: 4, commutative: false},
- {name: "ShiftRightMaskedInt64x2", argLength: 3, commutative: false},
- {name: "SubInt64x2", argLength: 2, commutative: false},
- {name: "SubMaskedInt64x2", argLength: 3, commutative: false},
- {name: "XorInt64x2", argLength: 2, commutative: true},
- {name: "XorMaskedInt64x2", argLength: 3, commutative: true},
- {name: "AbsoluteInt64x4", argLength: 1, commutative: false},
- {name: "AbsoluteMaskedInt64x4", argLength: 2, commutative: false},
- {name: "AddInt64x4", argLength: 2, commutative: true},
- {name: "AddMaskedInt64x4", argLength: 3, commutative: true},
- {name: "AndInt64x4", argLength: 2, commutative: true},
- {name: "AndMaskedInt64x4", argLength: 3, commutative: true},
- {name: "AndNotInt64x4", argLength: 2, commutative: false},
- {name: "AndNotMaskedInt64x4", argLength: 3, commutative: false},
- {name: "CompressInt64x4", argLength: 2, commutative: false},
- {name: "EqualInt64x4", argLength: 2, commutative: true},
- {name: "EqualMaskedInt64x4", argLength: 3, commutative: true},
- {name: "GreaterInt64x4", argLength: 2, commutative: false},
- {name: "GreaterEqualInt64x4", argLength: 2, commutative: false},
- {name: "GreaterEqualMaskedInt64x4", argLength: 3, commutative: false},
- {name: "GreaterMaskedInt64x4", argLength: 3, commutative: false},
- {name: "LessInt64x4", argLength: 2, commutative: false},
- {name: "LessEqualInt64x4", argLength: 2, commutative: false},
- {name: "LessEqualMaskedInt64x4", argLength: 3, commutative: false},
- {name: "LessMaskedInt64x4", argLength: 3, commutative: false},
- {name: "MaxInt64x4", argLength: 2, commutative: true},
- {name: "MaxMaskedInt64x4", argLength: 3, commutative: true},
- {name: "MinInt64x4", argLength: 2, commutative: true},
- {name: "MinMaskedInt64x4", argLength: 3, commutative: true},
- {name: "MulEvenWidenInt64x4", argLength: 2, commutative: true},
- {name: "MulEvenWidenMaskedInt64x4", argLength: 3, commutative: true},
- {name: "MulLowInt64x4", argLength: 2, commutative: true},
- {name: "MulLowMaskedInt64x4", argLength: 3, commutative: true},
- {name: "NotEqualInt64x4", argLength: 2, commutative: true},
- {name: "NotEqualMaskedInt64x4", argLength: 3, commutative: true},
- {name: "OrInt64x4", argLength: 2, commutative: true},
- {name: "OrMaskedInt64x4", argLength: 3, commutative: true},
- {name: "PopCountInt64x4", argLength: 1, commutative: false},
- {name: "PopCountMaskedInt64x4", argLength: 2, commutative: false},
- {name: "RotateLeftInt64x4", argLength: 2, commutative: false},
- {name: "RotateLeftMaskedInt64x4", argLength: 3, commutative: false},
- {name: "RotateRightInt64x4", argLength: 2, commutative: false},
- {name: "RotateRightMaskedInt64x4", argLength: 3, commutative: false},
- {name: "ShiftAllLeftInt64x4", argLength: 2, commutative: false},
- {name: "ShiftAllLeftMaskedInt64x4", argLength: 3, commutative: false},
- {name: "ShiftAllRightInt64x4", argLength: 2, commutative: false},
- {name: "ShiftAllRightMaskedInt64x4", argLength: 3, commutative: false},
- {name: "ShiftLeftInt64x4", argLength: 2, commutative: false},
- {name: "ShiftLeftAndFillUpperFromInt64x4", argLength: 3, commutative: false},
- {name: "ShiftLeftAndFillUpperFromMaskedInt64x4", argLength: 4, commutative: false},
{name: "ShiftLeftMaskedInt64x4", argLength: 3, commutative: false},
- {name: "ShiftRightInt64x4", argLength: 2, commutative: false},
+ {name: "ShiftLeftMaskedInt64x8", argLength: 3, commutative: false},
+ {name: "ShiftLeftMaskedUint16x8", argLength: 3, commutative: false},
+ {name: "ShiftLeftMaskedUint16x16", argLength: 3, commutative: false},
+ {name: "ShiftLeftMaskedUint16x32", argLength: 3, commutative: false},
+ {name: "ShiftLeftMaskedUint32x4", argLength: 3, commutative: false},
+ {name: "ShiftLeftMaskedUint32x8", argLength: 3, commutative: false},
+ {name: "ShiftLeftMaskedUint32x16", argLength: 3, commutative: false},
+ {name: "ShiftLeftMaskedUint64x2", argLength: 3, commutative: false},
+ {name: "ShiftLeftMaskedUint64x4", argLength: 3, commutative: false},
+ {name: "ShiftLeftMaskedUint64x8", argLength: 3, commutative: false},
+ {name: "ShiftLeftUint16x8", argLength: 2, commutative: false},
+ {name: "ShiftLeftUint16x16", argLength: 2, commutative: false},
+ {name: "ShiftLeftUint16x32", argLength: 2, commutative: false},
+ {name: "ShiftLeftUint32x4", argLength: 2, commutative: false},
+ {name: "ShiftLeftUint32x8", argLength: 2, commutative: false},
+ {name: "ShiftLeftUint32x16", argLength: 2, commutative: false},
+ {name: "ShiftLeftUint64x2", argLength: 2, commutative: false},
+ {name: "ShiftLeftUint64x4", argLength: 2, commutative: false},
+ {name: "ShiftLeftUint64x8", argLength: 2, commutative: false},
+ {name: "ShiftRightAndFillUpperFromInt16x8", argLength: 3, commutative: false},
+ {name: "ShiftRightAndFillUpperFromInt16x16", argLength: 3, commutative: false},
+ {name: "ShiftRightAndFillUpperFromInt16x32", argLength: 3, commutative: false},
+ {name: "ShiftRightAndFillUpperFromInt32x4", argLength: 3, commutative: false},
+ {name: "ShiftRightAndFillUpperFromInt32x8", argLength: 3, commutative: false},
+ {name: "ShiftRightAndFillUpperFromInt32x16", argLength: 3, commutative: false},
+ {name: "ShiftRightAndFillUpperFromInt64x2", argLength: 3, commutative: false},
{name: "ShiftRightAndFillUpperFromInt64x4", argLength: 3, commutative: false},
+ {name: "ShiftRightAndFillUpperFromInt64x8", argLength: 3, commutative: false},
+ {name: "ShiftRightAndFillUpperFromMaskedInt16x8", argLength: 4, commutative: false},
+ {name: "ShiftRightAndFillUpperFromMaskedInt16x16", argLength: 4, commutative: false},
+ {name: "ShiftRightAndFillUpperFromMaskedInt16x32", argLength: 4, commutative: false},
+ {name: "ShiftRightAndFillUpperFromMaskedInt32x4", argLength: 4, commutative: false},
+ {name: "ShiftRightAndFillUpperFromMaskedInt32x8", argLength: 4, commutative: false},
+ {name: "ShiftRightAndFillUpperFromMaskedInt32x16", argLength: 4, commutative: false},
+ {name: "ShiftRightAndFillUpperFromMaskedInt64x2", argLength: 4, commutative: false},
{name: "ShiftRightAndFillUpperFromMaskedInt64x4", argLength: 4, commutative: false},
+ {name: "ShiftRightAndFillUpperFromMaskedInt64x8", argLength: 4, commutative: false},
+ {name: "ShiftRightAndFillUpperFromMaskedUint16x8", argLength: 4, commutative: false},
+ {name: "ShiftRightAndFillUpperFromMaskedUint16x16", argLength: 4, commutative: false},
+ {name: "ShiftRightAndFillUpperFromMaskedUint16x32", argLength: 4, commutative: false},
+ {name: "ShiftRightAndFillUpperFromMaskedUint32x4", argLength: 4, commutative: false},
+ {name: "ShiftRightAndFillUpperFromMaskedUint32x8", argLength: 4, commutative: false},
+ {name: "ShiftRightAndFillUpperFromMaskedUint32x16", argLength: 4, commutative: false},
+ {name: "ShiftRightAndFillUpperFromMaskedUint64x2", argLength: 4, commutative: false},
+ {name: "ShiftRightAndFillUpperFromMaskedUint64x4", argLength: 4, commutative: false},
+ {name: "ShiftRightAndFillUpperFromMaskedUint64x8", argLength: 4, commutative: false},
+ {name: "ShiftRightAndFillUpperFromUint16x8", argLength: 3, commutative: false},
+ {name: "ShiftRightAndFillUpperFromUint16x16", argLength: 3, commutative: false},
+ {name: "ShiftRightAndFillUpperFromUint16x32", argLength: 3, commutative: false},
+ {name: "ShiftRightAndFillUpperFromUint32x4", argLength: 3, commutative: false},
+ {name: "ShiftRightAndFillUpperFromUint32x8", argLength: 3, commutative: false},
+ {name: "ShiftRightAndFillUpperFromUint32x16", argLength: 3, commutative: false},
+ {name: "ShiftRightAndFillUpperFromUint64x2", argLength: 3, commutative: false},
+ {name: "ShiftRightAndFillUpperFromUint64x4", argLength: 3, commutative: false},
+ {name: "ShiftRightAndFillUpperFromUint64x8", argLength: 3, commutative: false},
+ {name: "ShiftRightInt16x8", argLength: 2, commutative: false},
+ {name: "ShiftRightInt16x16", argLength: 2, commutative: false},
+ {name: "ShiftRightInt16x32", argLength: 2, commutative: false},
+ {name: "ShiftRightInt32x4", argLength: 2, commutative: false},
+ {name: "ShiftRightInt32x8", argLength: 2, commutative: false},
+ {name: "ShiftRightInt32x16", argLength: 2, commutative: false},
+ {name: "ShiftRightInt64x2", argLength: 2, commutative: false},
+ {name: "ShiftRightInt64x4", argLength: 2, commutative: false},
+ {name: "ShiftRightInt64x8", argLength: 2, commutative: false},
+ {name: "ShiftRightMaskedInt16x8", argLength: 3, commutative: false},
+ {name: "ShiftRightMaskedInt16x16", argLength: 3, commutative: false},
+ {name: "ShiftRightMaskedInt16x32", argLength: 3, commutative: false},
+ {name: "ShiftRightMaskedInt32x4", argLength: 3, commutative: false},
+ {name: "ShiftRightMaskedInt32x8", argLength: 3, commutative: false},
+ {name: "ShiftRightMaskedInt32x16", argLength: 3, commutative: false},
+ {name: "ShiftRightMaskedInt64x2", argLength: 3, commutative: false},
{name: "ShiftRightMaskedInt64x4", argLength: 3, commutative: false},
+ {name: "ShiftRightMaskedInt64x8", argLength: 3, commutative: false},
+ {name: "ShiftRightMaskedUint16x8", argLength: 3, commutative: false},
+ {name: "ShiftRightMaskedUint16x16", argLength: 3, commutative: false},
+ {name: "ShiftRightMaskedUint16x32", argLength: 3, commutative: false},
+ {name: "ShiftRightMaskedUint32x4", argLength: 3, commutative: false},
+ {name: "ShiftRightMaskedUint32x8", argLength: 3, commutative: false},
+ {name: "ShiftRightMaskedUint32x16", argLength: 3, commutative: false},
+ {name: "ShiftRightMaskedUint64x2", argLength: 3, commutative: false},
+ {name: "ShiftRightMaskedUint64x4", argLength: 3, commutative: false},
+ {name: "ShiftRightMaskedUint64x8", argLength: 3, commutative: false},
+ {name: "ShiftRightUint16x8", argLength: 2, commutative: false},
+ {name: "ShiftRightUint16x16", argLength: 2, commutative: false},
+ {name: "ShiftRightUint16x32", argLength: 2, commutative: false},
+ {name: "ShiftRightUint32x4", argLength: 2, commutative: false},
+ {name: "ShiftRightUint32x8", argLength: 2, commutative: false},
+ {name: "ShiftRightUint32x16", argLength: 2, commutative: false},
+ {name: "ShiftRightUint64x2", argLength: 2, commutative: false},
+ {name: "ShiftRightUint64x4", argLength: 2, commutative: false},
+ {name: "ShiftRightUint64x8", argLength: 2, commutative: false},
+ {name: "SignInt8x16", argLength: 2, commutative: false},
+ {name: "SignInt8x32", argLength: 2, commutative: false},
+ {name: "SignInt16x8", argLength: 2, commutative: false},
+ {name: "SignInt16x16", argLength: 2, commutative: false},
+ {name: "SignInt32x4", argLength: 2, commutative: false},
+ {name: "SignInt32x8", argLength: 2, commutative: false},
+ {name: "SqrtFloat32x4", argLength: 1, commutative: false},
+ {name: "SqrtFloat32x8", argLength: 1, commutative: false},
+ {name: "SqrtFloat32x16", argLength: 1, commutative: false},
+ {name: "SqrtFloat64x2", argLength: 1, commutative: false},
+ {name: "SqrtFloat64x4", argLength: 1, commutative: false},
+ {name: "SqrtFloat64x8", argLength: 1, commutative: false},
+ {name: "SqrtMaskedFloat32x4", argLength: 2, commutative: false},
+ {name: "SqrtMaskedFloat32x8", argLength: 2, commutative: false},
+ {name: "SqrtMaskedFloat32x16", argLength: 2, commutative: false},
+ {name: "SqrtMaskedFloat64x2", argLength: 2, commutative: false},
+ {name: "SqrtMaskedFloat64x4", argLength: 2, commutative: false},
+ {name: "SqrtMaskedFloat64x8", argLength: 2, commutative: false},
+ {name: "SubFloat32x4", argLength: 2, commutative: false},
+ {name: "SubFloat32x8", argLength: 2, commutative: false},
+ {name: "SubFloat32x16", argLength: 2, commutative: false},
+ {name: "SubFloat64x2", argLength: 2, commutative: false},
+ {name: "SubFloat64x4", argLength: 2, commutative: false},
+ {name: "SubFloat64x8", argLength: 2, commutative: false},
+ {name: "SubInt8x16", argLength: 2, commutative: false},
+ {name: "SubInt8x32", argLength: 2, commutative: false},
+ {name: "SubInt8x64", argLength: 2, commutative: false},
+ {name: "SubInt16x8", argLength: 2, commutative: false},
+ {name: "SubInt16x16", argLength: 2, commutative: false},
+ {name: "SubInt16x32", argLength: 2, commutative: false},
+ {name: "SubInt32x4", argLength: 2, commutative: false},
+ {name: "SubInt32x8", argLength: 2, commutative: false},
+ {name: "SubInt32x16", argLength: 2, commutative: false},
+ {name: "SubInt64x2", argLength: 2, commutative: false},
{name: "SubInt64x4", argLength: 2, commutative: false},
+ {name: "SubInt64x8", argLength: 2, commutative: false},
+ {name: "SubMaskedFloat32x4", argLength: 3, commutative: false},
+ {name: "SubMaskedFloat32x8", argLength: 3, commutative: false},
+ {name: "SubMaskedFloat32x16", argLength: 3, commutative: false},
+ {name: "SubMaskedFloat64x2", argLength: 3, commutative: false},
+ {name: "SubMaskedFloat64x4", argLength: 3, commutative: false},
+ {name: "SubMaskedFloat64x8", argLength: 3, commutative: false},
+ {name: "SubMaskedInt8x16", argLength: 3, commutative: false},
+ {name: "SubMaskedInt8x32", argLength: 3, commutative: false},
+ {name: "SubMaskedInt8x64", argLength: 3, commutative: false},
+ {name: "SubMaskedInt16x8", argLength: 3, commutative: false},
+ {name: "SubMaskedInt16x16", argLength: 3, commutative: false},
+ {name: "SubMaskedInt16x32", argLength: 3, commutative: false},
+ {name: "SubMaskedInt32x4", argLength: 3, commutative: false},
+ {name: "SubMaskedInt32x8", argLength: 3, commutative: false},
+ {name: "SubMaskedInt32x16", argLength: 3, commutative: false},
+ {name: "SubMaskedInt64x2", argLength: 3, commutative: false},
{name: "SubMaskedInt64x4", argLength: 3, commutative: false},
- {name: "XorInt64x4", argLength: 2, commutative: true},
- {name: "XorMaskedInt64x4", argLength: 3, commutative: true},
- {name: "AbsoluteInt64x8", argLength: 1, commutative: false},
- {name: "AbsoluteMaskedInt64x8", argLength: 2, commutative: false},
- {name: "AddInt64x8", argLength: 2, commutative: true},
- {name: "AddMaskedInt64x8", argLength: 3, commutative: true},
- {name: "AndInt64x8", argLength: 2, commutative: true},
- {name: "AndMaskedInt64x8", argLength: 3, commutative: true},
- {name: "AndNotInt64x8", argLength: 2, commutative: false},
- {name: "AndNotMaskedInt64x8", argLength: 3, commutative: false},
- {name: "CompressInt64x8", argLength: 2, commutative: false},
- {name: "EqualInt64x8", argLength: 2, commutative: true},
- {name: "EqualMaskedInt64x8", argLength: 3, commutative: true},
- {name: "GreaterInt64x8", argLength: 2, commutative: false},
- {name: "GreaterEqualInt64x8", argLength: 2, commutative: false},
- {name: "GreaterEqualMaskedInt64x8", argLength: 3, commutative: false},
- {name: "GreaterMaskedInt64x8", argLength: 3, commutative: false},
- {name: "LessInt64x8", argLength: 2, commutative: false},
- {name: "LessEqualInt64x8", argLength: 2, commutative: false},
- {name: "LessEqualMaskedInt64x8", argLength: 3, commutative: false},
- {name: "LessMaskedInt64x8", argLength: 3, commutative: false},
- {name: "MaxInt64x8", argLength: 2, commutative: true},
- {name: "MaxMaskedInt64x8", argLength: 3, commutative: true},
- {name: "MinInt64x8", argLength: 2, commutative: true},
- {name: "MinMaskedInt64x8", argLength: 3, commutative: true},
- {name: "MulEvenWidenInt64x8", argLength: 2, commutative: true},
- {name: "MulEvenWidenMaskedInt64x8", argLength: 3, commutative: true},
- {name: "MulLowInt64x8", argLength: 2, commutative: true},
- {name: "MulLowMaskedInt64x8", argLength: 3, commutative: true},
- {name: "NotEqualInt64x8", argLength: 2, commutative: true},
- {name: "NotEqualMaskedInt64x8", argLength: 3, commutative: true},
- {name: "OrInt64x8", argLength: 2, commutative: true},
- {name: "OrMaskedInt64x8", argLength: 3, commutative: true},
- {name: "PopCountInt64x8", argLength: 1, commutative: false},
- {name: "PopCountMaskedInt64x8", argLength: 2, commutative: false},
- {name: "RotateLeftInt64x8", argLength: 2, commutative: false},
- {name: "RotateLeftMaskedInt64x8", argLength: 3, commutative: false},
- {name: "RotateRightInt64x8", argLength: 2, commutative: false},
- {name: "RotateRightMaskedInt64x8", argLength: 3, commutative: false},
- {name: "ShiftAllLeftInt64x8", argLength: 2, commutative: false},
- {name: "ShiftAllLeftMaskedInt64x8", argLength: 3, commutative: false},
- {name: "ShiftAllRightInt64x8", argLength: 2, commutative: false},
- {name: "ShiftAllRightMaskedInt64x8", argLength: 3, commutative: false},
- {name: "ShiftLeftInt64x8", argLength: 2, commutative: false},
- {name: "ShiftLeftAndFillUpperFromInt64x8", argLength: 3, commutative: false},
- {name: "ShiftLeftAndFillUpperFromMaskedInt64x8", argLength: 4, commutative: false},
- {name: "ShiftLeftMaskedInt64x8", argLength: 3, commutative: false},
- {name: "ShiftRightInt64x8", argLength: 2, commutative: false},
- {name: "ShiftRightAndFillUpperFromInt64x8", argLength: 3, commutative: false},
- {name: "ShiftRightAndFillUpperFromMaskedInt64x8", argLength: 4, commutative: false},
- {name: "ShiftRightMaskedInt64x8", argLength: 3, commutative: false},
- {name: "SubInt64x8", argLength: 2, commutative: false},
{name: "SubMaskedInt64x8", argLength: 3, commutative: false},
- {name: "XorInt64x8", argLength: 2, commutative: true},
- {name: "XorMaskedInt64x8", argLength: 3, commutative: true},
- {name: "AbsoluteInt8x16", argLength: 1, commutative: false},
- {name: "AbsoluteMaskedInt8x16", argLength: 2, commutative: false},
- {name: "AddInt8x16", argLength: 2, commutative: true},
- {name: "AddMaskedInt8x16", argLength: 3, commutative: true},
- {name: "AndInt8x16", argLength: 2, commutative: true},
- {name: "AndNotInt8x16", argLength: 2, commutative: false},
- {name: "CompressInt8x16", argLength: 2, commutative: false},
- {name: "EqualInt8x16", argLength: 2, commutative: true},
- {name: "EqualMaskedInt8x16", argLength: 3, commutative: true},
- {name: "GreaterInt8x16", argLength: 2, commutative: false},
- {name: "GreaterEqualInt8x16", argLength: 2, commutative: false},
- {name: "GreaterEqualMaskedInt8x16", argLength: 3, commutative: false},
- {name: "GreaterMaskedInt8x16", argLength: 3, commutative: false},
- {name: "LessInt8x16", argLength: 2, commutative: false},
- {name: "LessEqualInt8x16", argLength: 2, commutative: false},
- {name: "LessEqualMaskedInt8x16", argLength: 3, commutative: false},
- {name: "LessMaskedInt8x16", argLength: 3, commutative: false},
- {name: "MaxInt8x16", argLength: 2, commutative: true},
- {name: "MaxMaskedInt8x16", argLength: 3, commutative: true},
- {name: "MinInt8x16", argLength: 2, commutative: true},
- {name: "MinMaskedInt8x16", argLength: 3, commutative: true},
- {name: "NotEqualInt8x16", argLength: 2, commutative: true},
- {name: "NotEqualMaskedInt8x16", argLength: 3, commutative: true},
- {name: "OrInt8x16", argLength: 2, commutative: true},
- {name: "PopCountInt8x16", argLength: 1, commutative: false},
- {name: "PopCountMaskedInt8x16", argLength: 2, commutative: false},
- {name: "SaturatedAddInt8x16", argLength: 2, commutative: true},
- {name: "SaturatedAddMaskedInt8x16", argLength: 3, commutative: true},
- {name: "SaturatedSubInt8x16", argLength: 2, commutative: false},
- {name: "SaturatedSubMaskedInt8x16", argLength: 3, commutative: false},
- {name: "SignInt8x16", argLength: 2, commutative: false},
- {name: "SubInt8x16", argLength: 2, commutative: false},
- {name: "SubMaskedInt8x16", argLength: 3, commutative: false},
- {name: "XorInt8x16", argLength: 2, commutative: true},
- {name: "AbsoluteInt8x32", argLength: 1, commutative: false},
- {name: "AbsoluteMaskedInt8x32", argLength: 2, commutative: false},
- {name: "AddInt8x32", argLength: 2, commutative: true},
- {name: "AddMaskedInt8x32", argLength: 3, commutative: true},
- {name: "AndInt8x32", argLength: 2, commutative: true},
- {name: "AndNotInt8x32", argLength: 2, commutative: false},
- {name: "CompressInt8x32", argLength: 2, commutative: false},
- {name: "EqualInt8x32", argLength: 2, commutative: true},
- {name: "EqualMaskedInt8x32", argLength: 3, commutative: true},
- {name: "GreaterInt8x32", argLength: 2, commutative: false},
- {name: "GreaterEqualInt8x32", argLength: 2, commutative: false},
- {name: "GreaterEqualMaskedInt8x32", argLength: 3, commutative: false},
- {name: "GreaterMaskedInt8x32", argLength: 3, commutative: false},
- {name: "LessInt8x32", argLength: 2, commutative: false},
- {name: "LessEqualInt8x32", argLength: 2, commutative: false},
- {name: "LessEqualMaskedInt8x32", argLength: 3, commutative: false},
- {name: "LessMaskedInt8x32", argLength: 3, commutative: false},
- {name: "MaxInt8x32", argLength: 2, commutative: true},
- {name: "MaxMaskedInt8x32", argLength: 3, commutative: true},
- {name: "MinInt8x32", argLength: 2, commutative: true},
- {name: "MinMaskedInt8x32", argLength: 3, commutative: true},
- {name: "NotEqualInt8x32", argLength: 2, commutative: true},
- {name: "NotEqualMaskedInt8x32", argLength: 3, commutative: true},
- {name: "OrInt8x32", argLength: 2, commutative: true},
- {name: "PopCountInt8x32", argLength: 1, commutative: false},
- {name: "PopCountMaskedInt8x32", argLength: 2, commutative: false},
- {name: "SaturatedAddInt8x32", argLength: 2, commutative: true},
- {name: "SaturatedAddMaskedInt8x32", argLength: 3, commutative: true},
- {name: "SaturatedSubInt8x32", argLength: 2, commutative: false},
- {name: "SaturatedSubMaskedInt8x32", argLength: 3, commutative: false},
- {name: "SignInt8x32", argLength: 2, commutative: false},
- {name: "SubInt8x32", argLength: 2, commutative: false},
- {name: "SubMaskedInt8x32", argLength: 3, commutative: false},
- {name: "XorInt8x32", argLength: 2, commutative: true},
- {name: "AbsoluteInt8x64", argLength: 1, commutative: false},
- {name: "AbsoluteMaskedInt8x64", argLength: 2, commutative: false},
- {name: "AddInt8x64", argLength: 2, commutative: true},
- {name: "AddMaskedInt8x64", argLength: 3, commutative: true},
- {name: "CompressInt8x64", argLength: 2, commutative: false},
- {name: "EqualInt8x64", argLength: 2, commutative: true},
- {name: "EqualMaskedInt8x64", argLength: 3, commutative: true},
- {name: "GreaterInt8x64", argLength: 2, commutative: false},
- {name: "GreaterEqualInt8x64", argLength: 2, commutative: false},
- {name: "GreaterEqualMaskedInt8x64", argLength: 3, commutative: false},
- {name: "GreaterMaskedInt8x64", argLength: 3, commutative: false},
- {name: "LessInt8x64", argLength: 2, commutative: false},
- {name: "LessEqualInt8x64", argLength: 2, commutative: false},
- {name: "LessEqualMaskedInt8x64", argLength: 3, commutative: false},
- {name: "LessMaskedInt8x64", argLength: 3, commutative: false},
- {name: "MaxInt8x64", argLength: 2, commutative: true},
- {name: "MaxMaskedInt8x64", argLength: 3, commutative: true},
- {name: "MinInt8x64", argLength: 2, commutative: true},
- {name: "MinMaskedInt8x64", argLength: 3, commutative: true},
- {name: "NotEqualInt8x64", argLength: 2, commutative: true},
- {name: "NotEqualMaskedInt8x64", argLength: 3, commutative: true},
- {name: "PopCountInt8x64", argLength: 1, commutative: false},
- {name: "PopCountMaskedInt8x64", argLength: 2, commutative: false},
- {name: "SaturatedAddInt8x64", argLength: 2, commutative: true},
- {name: "SaturatedAddMaskedInt8x64", argLength: 3, commutative: true},
- {name: "SaturatedSubInt8x64", argLength: 2, commutative: false},
- {name: "SaturatedSubMaskedInt8x64", argLength: 3, commutative: false},
- {name: "SubInt8x64", argLength: 2, commutative: false},
- {name: "SubMaskedInt8x64", argLength: 3, commutative: false},
- {name: "AddUint16x16", argLength: 2, commutative: true},
- {name: "AddMaskedUint16x16", argLength: 3, commutative: true},
- {name: "AndUint16x16", argLength: 2, commutative: true},
- {name: "AndNotUint16x16", argLength: 2, commutative: false},
- {name: "AverageUint16x16", argLength: 2, commutative: true},
- {name: "AverageMaskedUint16x16", argLength: 3, commutative: true},
- {name: "CompressUint16x16", argLength: 2, commutative: false},
- {name: "EqualUint16x16", argLength: 2, commutative: true},
- {name: "EqualMaskedUint16x16", argLength: 3, commutative: true},
- {name: "GreaterUint16x16", argLength: 2, commutative: false},
- {name: "GreaterEqualUint16x16", argLength: 2, commutative: false},
- {name: "GreaterEqualMaskedUint16x16", argLength: 3, commutative: false},
- {name: "GreaterMaskedUint16x16", argLength: 3, commutative: false},
- {name: "LessUint16x16", argLength: 2, commutative: false},
- {name: "LessEqualUint16x16", argLength: 2, commutative: false},
- {name: "LessEqualMaskedUint16x16", argLength: 3, commutative: false},
- {name: "LessMaskedUint16x16", argLength: 3, commutative: false},
- {name: "MaxUint16x16", argLength: 2, commutative: true},
- {name: "MaxMaskedUint16x16", argLength: 3, commutative: true},
- {name: "MinUint16x16", argLength: 2, commutative: true},
- {name: "MinMaskedUint16x16", argLength: 3, commutative: true},
- {name: "MulHighUint16x16", argLength: 2, commutative: true},
- {name: "MulHighMaskedUint16x16", argLength: 3, commutative: true},
- {name: "NotEqualUint16x16", argLength: 2, commutative: true},
- {name: "NotEqualMaskedUint16x16", argLength: 3, commutative: true},
- {name: "OrUint16x16", argLength: 2, commutative: true},
- {name: "PairwiseAddUint16x16", argLength: 2, commutative: false},
- {name: "PairwiseSubUint16x16", argLength: 2, commutative: false},
- {name: "PermuteInt16x16", argLength: 2, commutative: false},
- {name: "PermuteUint16x16", argLength: 2, commutative: false},
- {name: "Permute2Uint16x16", argLength: 3, commutative: false},
- {name: "Permute2Int16x16", argLength: 3, commutative: false},
- {name: "Permute2MaskedUint16x16", argLength: 4, commutative: false},
- {name: "Permute2MaskedInt16x16", argLength: 4, commutative: false},
- {name: "PermuteMaskedInt16x16", argLength: 3, commutative: false},
- {name: "PermuteMaskedUint16x16", argLength: 3, commutative: false},
- {name: "PopCountUint16x16", argLength: 1, commutative: false},
- {name: "PopCountMaskedUint16x16", argLength: 2, commutative: false},
- {name: "SaturatedAddUint16x16", argLength: 2, commutative: true},
- {name: "SaturatedAddMaskedUint16x16", argLength: 3, commutative: true},
- {name: "SaturatedSubUint16x16", argLength: 2, commutative: false},
- {name: "SaturatedSubMaskedUint16x16", argLength: 3, commutative: false},
- {name: "ShiftAllLeftUint16x16", argLength: 2, commutative: false},
- {name: "ShiftAllLeftMaskedUint16x16", argLength: 3, commutative: false},
- {name: "ShiftAllRightUint16x16", argLength: 2, commutative: false},
- {name: "ShiftAllRightMaskedUint16x16", argLength: 3, commutative: false},
- {name: "ShiftLeftUint16x16", argLength: 2, commutative: false},
- {name: "ShiftLeftAndFillUpperFromUint16x16", argLength: 3, commutative: false},
- {name: "ShiftLeftAndFillUpperFromMaskedUint16x16", argLength: 4, commutative: false},
- {name: "ShiftLeftMaskedUint16x16", argLength: 3, commutative: false},
- {name: "ShiftRightUint16x16", argLength: 2, commutative: false},
- {name: "ShiftRightAndFillUpperFromUint16x16", argLength: 3, commutative: false},
- {name: "ShiftRightAndFillUpperFromMaskedUint16x16", argLength: 4, commutative: false},
- {name: "ShiftRightMaskedUint16x16", argLength: 3, commutative: false},
- {name: "SubUint16x16", argLength: 2, commutative: false},
+ {name: "SubMaskedUint8x16", argLength: 3, commutative: false},
+ {name: "SubMaskedUint8x32", argLength: 3, commutative: false},
+ {name: "SubMaskedUint8x64", argLength: 3, commutative: false},
+ {name: "SubMaskedUint16x8", argLength: 3, commutative: false},
{name: "SubMaskedUint16x16", argLength: 3, commutative: false},
- {name: "XorUint16x16", argLength: 2, commutative: true},
- {name: "AddUint16x32", argLength: 2, commutative: true},
- {name: "AddMaskedUint16x32", argLength: 3, commutative: true},
- {name: "AverageUint16x32", argLength: 2, commutative: true},
- {name: "AverageMaskedUint16x32", argLength: 3, commutative: true},
- {name: "CompressUint16x32", argLength: 2, commutative: false},
- {name: "EqualUint16x32", argLength: 2, commutative: true},
- {name: "EqualMaskedUint16x32", argLength: 3, commutative: true},
- {name: "GreaterUint16x32", argLength: 2, commutative: false},
- {name: "GreaterEqualUint16x32", argLength: 2, commutative: false},
- {name: "GreaterEqualMaskedUint16x32", argLength: 3, commutative: false},
- {name: "GreaterMaskedUint16x32", argLength: 3, commutative: false},
- {name: "LessUint16x32", argLength: 2, commutative: false},
- {name: "LessEqualUint16x32", argLength: 2, commutative: false},
- {name: "LessEqualMaskedUint16x32", argLength: 3, commutative: false},
- {name: "LessMaskedUint16x32", argLength: 3, commutative: false},
- {name: "MaxUint16x32", argLength: 2, commutative: true},
- {name: "MaxMaskedUint16x32", argLength: 3, commutative: true},
- {name: "MinUint16x32", argLength: 2, commutative: true},
- {name: "MinMaskedUint16x32", argLength: 3, commutative: true},
- {name: "MulHighUint16x32", argLength: 2, commutative: true},
- {name: "MulHighMaskedUint16x32", argLength: 3, commutative: true},
- {name: "NotEqualUint16x32", argLength: 2, commutative: true},
- {name: "NotEqualMaskedUint16x32", argLength: 3, commutative: true},
- {name: "PermuteUint16x32", argLength: 2, commutative: false},
- {name: "PermuteInt16x32", argLength: 2, commutative: false},
- {name: "Permute2Uint16x32", argLength: 3, commutative: false},
- {name: "Permute2Int16x32", argLength: 3, commutative: false},
- {name: "Permute2MaskedUint16x32", argLength: 4, commutative: false},
- {name: "Permute2MaskedInt16x32", argLength: 4, commutative: false},
- {name: "PermuteMaskedInt16x32", argLength: 3, commutative: false},
- {name: "PermuteMaskedUint16x32", argLength: 3, commutative: false},
- {name: "PopCountUint16x32", argLength: 1, commutative: false},
- {name: "PopCountMaskedUint16x32", argLength: 2, commutative: false},
- {name: "SaturatedAddUint16x32", argLength: 2, commutative: true},
- {name: "SaturatedAddMaskedUint16x32", argLength: 3, commutative: true},
- {name: "SaturatedSubUint16x32", argLength: 2, commutative: false},
- {name: "SaturatedSubMaskedUint16x32", argLength: 3, commutative: false},
- {name: "ShiftAllLeftUint16x32", argLength: 2, commutative: false},
- {name: "ShiftAllLeftMaskedUint16x32", argLength: 3, commutative: false},
- {name: "ShiftAllRightUint16x32", argLength: 2, commutative: false},
- {name: "ShiftAllRightMaskedUint16x32", argLength: 3, commutative: false},
- {name: "ShiftLeftUint16x32", argLength: 2, commutative: false},
- {name: "ShiftLeftAndFillUpperFromUint16x32", argLength: 3, commutative: false},
- {name: "ShiftLeftAndFillUpperFromMaskedUint16x32", argLength: 4, commutative: false},
- {name: "ShiftLeftMaskedUint16x32", argLength: 3, commutative: false},
- {name: "ShiftRightUint16x32", argLength: 2, commutative: false},
- {name: "ShiftRightAndFillUpperFromUint16x32", argLength: 3, commutative: false},
- {name: "ShiftRightAndFillUpperFromMaskedUint16x32", argLength: 4, commutative: false},
- {name: "ShiftRightMaskedUint16x32", argLength: 3, commutative: false},
- {name: "SubUint16x32", argLength: 2, commutative: false},
{name: "SubMaskedUint16x32", argLength: 3, commutative: false},
- {name: "AddUint16x8", argLength: 2, commutative: true},
- {name: "AddMaskedUint16x8", argLength: 3, commutative: true},
- {name: "AndUint16x8", argLength: 2, commutative: true},
- {name: "AndNotUint16x8", argLength: 2, commutative: false},
- {name: "AverageUint16x8", argLength: 2, commutative: true},
- {name: "AverageMaskedUint16x8", argLength: 3, commutative: true},
- {name: "CompressUint16x8", argLength: 2, commutative: false},
- {name: "EqualUint16x8", argLength: 2, commutative: true},
- {name: "EqualMaskedUint16x8", argLength: 3, commutative: true},
- {name: "GreaterUint16x8", argLength: 2, commutative: false},
- {name: "GreaterEqualUint16x8", argLength: 2, commutative: false},
- {name: "GreaterEqualMaskedUint16x8", argLength: 3, commutative: false},
- {name: "GreaterMaskedUint16x8", argLength: 3, commutative: false},
- {name: "LessUint16x8", argLength: 2, commutative: false},
- {name: "LessEqualUint16x8", argLength: 2, commutative: false},
- {name: "LessEqualMaskedUint16x8", argLength: 3, commutative: false},
- {name: "LessMaskedUint16x8", argLength: 3, commutative: false},
- {name: "MaxUint16x8", argLength: 2, commutative: true},
- {name: "MaxMaskedUint16x8", argLength: 3, commutative: true},
- {name: "MinUint16x8", argLength: 2, commutative: true},
- {name: "MinMaskedUint16x8", argLength: 3, commutative: true},
- {name: "MulHighUint16x8", argLength: 2, commutative: true},
- {name: "MulHighMaskedUint16x8", argLength: 3, commutative: true},
- {name: "NotEqualUint16x8", argLength: 2, commutative: true},
- {name: "NotEqualMaskedUint16x8", argLength: 3, commutative: true},
- {name: "OrUint16x8", argLength: 2, commutative: true},
- {name: "PairwiseAddUint16x8", argLength: 2, commutative: false},
- {name: "PairwiseSubUint16x8", argLength: 2, commutative: false},
- {name: "PermuteInt16x8", argLength: 2, commutative: false},
- {name: "PermuteUint16x8", argLength: 2, commutative: false},
- {name: "Permute2Uint16x8", argLength: 3, commutative: false},
- {name: "Permute2Int16x8", argLength: 3, commutative: false},
- {name: "Permute2MaskedInt16x8", argLength: 4, commutative: false},
- {name: "Permute2MaskedUint16x8", argLength: 4, commutative: false},
- {name: "PermuteMaskedInt16x8", argLength: 3, commutative: false},
- {name: "PermuteMaskedUint16x8", argLength: 3, commutative: false},
- {name: "PopCountUint16x8", argLength: 1, commutative: false},
- {name: "PopCountMaskedUint16x8", argLength: 2, commutative: false},
- {name: "SaturatedAddUint16x8", argLength: 2, commutative: true},
- {name: "SaturatedAddMaskedUint16x8", argLength: 3, commutative: true},
- {name: "SaturatedSubUint16x8", argLength: 2, commutative: false},
- {name: "SaturatedSubMaskedUint16x8", argLength: 3, commutative: false},
- {name: "ShiftAllLeftUint16x8", argLength: 2, commutative: false},
- {name: "ShiftAllLeftMaskedUint16x8", argLength: 3, commutative: false},
- {name: "ShiftAllRightUint16x8", argLength: 2, commutative: false},
- {name: "ShiftAllRightMaskedUint16x8", argLength: 3, commutative: false},
- {name: "ShiftLeftUint16x8", argLength: 2, commutative: false},
- {name: "ShiftLeftAndFillUpperFromUint16x8", argLength: 3, commutative: false},
- {name: "ShiftLeftAndFillUpperFromMaskedUint16x8", argLength: 4, commutative: false},
- {name: "ShiftLeftMaskedUint16x8", argLength: 3, commutative: false},
- {name: "ShiftRightUint16x8", argLength: 2, commutative: false},
- {name: "ShiftRightAndFillUpperFromUint16x8", argLength: 3, commutative: false},
- {name: "ShiftRightAndFillUpperFromMaskedUint16x8", argLength: 4, commutative: false},
- {name: "ShiftRightMaskedUint16x8", argLength: 3, commutative: false},
- {name: "SubUint16x8", argLength: 2, commutative: false},
- {name: "SubMaskedUint16x8", argLength: 3, commutative: false},
- {name: "XorUint16x8", argLength: 2, commutative: true},
- {name: "AddUint32x16", argLength: 2, commutative: true},
- {name: "AddMaskedUint32x16", argLength: 3, commutative: true},
- {name: "AndUint32x16", argLength: 2, commutative: true},
- {name: "AndMaskedUint32x16", argLength: 3, commutative: true},
- {name: "AndNotUint32x16", argLength: 2, commutative: false},
- {name: "AndNotMaskedUint32x16", argLength: 3, commutative: false},
- {name: "CompressUint32x16", argLength: 2, commutative: false},
- {name: "EqualUint32x16", argLength: 2, commutative: true},
- {name: "EqualMaskedUint32x16", argLength: 3, commutative: true},
- {name: "GreaterUint32x16", argLength: 2, commutative: false},
- {name: "GreaterEqualUint32x16", argLength: 2, commutative: false},
- {name: "GreaterEqualMaskedUint32x16", argLength: 3, commutative: false},
- {name: "GreaterMaskedUint32x16", argLength: 3, commutative: false},
- {name: "LessUint32x16", argLength: 2, commutative: false},
- {name: "LessEqualUint32x16", argLength: 2, commutative: false},
- {name: "LessEqualMaskedUint32x16", argLength: 3, commutative: false},
- {name: "LessMaskedUint32x16", argLength: 3, commutative: false},
- {name: "MaxUint32x16", argLength: 2, commutative: true},
- {name: "MaxMaskedUint32x16", argLength: 3, commutative: true},
- {name: "MinUint32x16", argLength: 2, commutative: true},
- {name: "MinMaskedUint32x16", argLength: 3, commutative: true},
- {name: "NotEqualUint32x16", argLength: 2, commutative: true},
- {name: "NotEqualMaskedUint32x16", argLength: 3, commutative: true},
- {name: "OrUint32x16", argLength: 2, commutative: true},
- {name: "OrMaskedUint32x16", argLength: 3, commutative: true},
- {name: "PermuteInt32x16", argLength: 2, commutative: false},
- {name: "PermuteFloat32x16", argLength: 2, commutative: false},
- {name: "PermuteUint32x16", argLength: 2, commutative: false},
- {name: "Permute2Uint32x16", argLength: 3, commutative: false},
- {name: "Permute2Float32x16", argLength: 3, commutative: false},
- {name: "Permute2Int32x16", argLength: 3, commutative: false},
- {name: "Permute2MaskedUint32x16", argLength: 4, commutative: false},
- {name: "Permute2MaskedInt32x16", argLength: 4, commutative: false},
- {name: "Permute2MaskedFloat32x16", argLength: 4, commutative: false},
- {name: "PermuteMaskedFloat32x16", argLength: 3, commutative: false},
- {name: "PermuteMaskedInt32x16", argLength: 3, commutative: false},
- {name: "PermuteMaskedUint32x16", argLength: 3, commutative: false},
- {name: "PopCountUint32x16", argLength: 1, commutative: false},
- {name: "PopCountMaskedUint32x16", argLength: 2, commutative: false},
- {name: "RotateLeftUint32x16", argLength: 2, commutative: false},
- {name: "RotateLeftMaskedUint32x16", argLength: 3, commutative: false},
- {name: "RotateRightUint32x16", argLength: 2, commutative: false},
- {name: "RotateRightMaskedUint32x16", argLength: 3, commutative: false},
- {name: "ShiftAllLeftUint32x16", argLength: 2, commutative: false},
- {name: "ShiftAllLeftMaskedUint32x16", argLength: 3, commutative: false},
- {name: "ShiftAllRightUint32x16", argLength: 2, commutative: false},
- {name: "ShiftAllRightMaskedUint32x16", argLength: 3, commutative: false},
- {name: "ShiftLeftUint32x16", argLength: 2, commutative: false},
- {name: "ShiftLeftAndFillUpperFromUint32x16", argLength: 3, commutative: false},
- {name: "ShiftLeftAndFillUpperFromMaskedUint32x16", argLength: 4, commutative: false},
- {name: "ShiftLeftMaskedUint32x16", argLength: 3, commutative: false},
- {name: "ShiftRightUint32x16", argLength: 2, commutative: false},
- {name: "ShiftRightAndFillUpperFromUint32x16", argLength: 3, commutative: false},
- {name: "ShiftRightAndFillUpperFromMaskedUint32x16", argLength: 4, commutative: false},
- {name: "ShiftRightMaskedUint32x16", argLength: 3, commutative: false},
- {name: "SubUint32x16", argLength: 2, commutative: false},
- {name: "SubMaskedUint32x16", argLength: 3, commutative: false},
- {name: "XorUint32x16", argLength: 2, commutative: true},
- {name: "XorMaskedUint32x16", argLength: 3, commutative: true},
- {name: "AddUint32x4", argLength: 2, commutative: true},
- {name: "AddMaskedUint32x4", argLength: 3, commutative: true},
- {name: "AndUint32x4", argLength: 2, commutative: true},
- {name: "AndMaskedUint32x4", argLength: 3, commutative: true},
- {name: "AndNotUint32x4", argLength: 2, commutative: false},
- {name: "AndNotMaskedUint32x4", argLength: 3, commutative: false},
- {name: "CompressUint32x4", argLength: 2, commutative: false},
- {name: "EqualUint32x4", argLength: 2, commutative: true},
- {name: "EqualMaskedUint32x4", argLength: 3, commutative: true},
- {name: "GreaterUint32x4", argLength: 2, commutative: false},
- {name: "GreaterEqualUint32x4", argLength: 2, commutative: false},
- {name: "GreaterEqualMaskedUint32x4", argLength: 3, commutative: false},
- {name: "GreaterMaskedUint32x4", argLength: 3, commutative: false},
- {name: "LessUint32x4", argLength: 2, commutative: false},
- {name: "LessEqualUint32x4", argLength: 2, commutative: false},
- {name: "LessEqualMaskedUint32x4", argLength: 3, commutative: false},
- {name: "LessMaskedUint32x4", argLength: 3, commutative: false},
- {name: "MaxUint32x4", argLength: 2, commutative: true},
- {name: "MaxMaskedUint32x4", argLength: 3, commutative: true},
- {name: "MinUint32x4", argLength: 2, commutative: true},
- {name: "MinMaskedUint32x4", argLength: 3, commutative: true},
- {name: "MulEvenWidenUint32x4", argLength: 2, commutative: true},
- {name: "NotEqualUint32x4", argLength: 2, commutative: true},
- {name: "NotEqualMaskedUint32x4", argLength: 3, commutative: true},
- {name: "OrUint32x4", argLength: 2, commutative: true},
- {name: "OrMaskedUint32x4", argLength: 3, commutative: true},
- {name: "PairwiseAddUint32x4", argLength: 2, commutative: false},
- {name: "PairwiseSubUint32x4", argLength: 2, commutative: false},
- {name: "Permute2Float32x4", argLength: 3, commutative: false},
- {name: "Permute2Uint32x4", argLength: 3, commutative: false},
- {name: "Permute2Int32x4", argLength: 3, commutative: false},
- {name: "Permute2MaskedInt32x4", argLength: 4, commutative: false},
- {name: "Permute2MaskedUint32x4", argLength: 4, commutative: false},
- {name: "Permute2MaskedFloat32x4", argLength: 4, commutative: false},
- {name: "PopCountUint32x4", argLength: 1, commutative: false},
- {name: "PopCountMaskedUint32x4", argLength: 2, commutative: false},
- {name: "RotateLeftUint32x4", argLength: 2, commutative: false},
- {name: "RotateLeftMaskedUint32x4", argLength: 3, commutative: false},
- {name: "RotateRightUint32x4", argLength: 2, commutative: false},
- {name: "RotateRightMaskedUint32x4", argLength: 3, commutative: false},
- {name: "ShiftAllLeftUint32x4", argLength: 2, commutative: false},
- {name: "ShiftAllLeftMaskedUint32x4", argLength: 3, commutative: false},
- {name: "ShiftAllRightUint32x4", argLength: 2, commutative: false},
- {name: "ShiftAllRightMaskedUint32x4", argLength: 3, commutative: false},
- {name: "ShiftLeftUint32x4", argLength: 2, commutative: false},
- {name: "ShiftLeftAndFillUpperFromUint32x4", argLength: 3, commutative: false},
- {name: "ShiftLeftAndFillUpperFromMaskedUint32x4", argLength: 4, commutative: false},
- {name: "ShiftLeftMaskedUint32x4", argLength: 3, commutative: false},
- {name: "ShiftRightUint32x4", argLength: 2, commutative: false},
- {name: "ShiftRightAndFillUpperFromUint32x4", argLength: 3, commutative: false},
- {name: "ShiftRightAndFillUpperFromMaskedUint32x4", argLength: 4, commutative: false},
- {name: "ShiftRightMaskedUint32x4", argLength: 3, commutative: false},
- {name: "SubUint32x4", argLength: 2, commutative: false},
- {name: "SubMaskedUint32x4", argLength: 3, commutative: false},
- {name: "XorUint32x4", argLength: 2, commutative: true},
- {name: "XorMaskedUint32x4", argLength: 3, commutative: true},
- {name: "AddUint32x8", argLength: 2, commutative: true},
- {name: "AddMaskedUint32x8", argLength: 3, commutative: true},
- {name: "AndUint32x8", argLength: 2, commutative: true},
- {name: "AndMaskedUint32x8", argLength: 3, commutative: true},
- {name: "AndNotUint32x8", argLength: 2, commutative: false},
- {name: "AndNotMaskedUint32x8", argLength: 3, commutative: false},
- {name: "CompressUint32x8", argLength: 2, commutative: false},
- {name: "EqualUint32x8", argLength: 2, commutative: true},
- {name: "EqualMaskedUint32x8", argLength: 3, commutative: true},
- {name: "GreaterUint32x8", argLength: 2, commutative: false},
- {name: "GreaterEqualUint32x8", argLength: 2, commutative: false},
- {name: "GreaterEqualMaskedUint32x8", argLength: 3, commutative: false},
- {name: "GreaterMaskedUint32x8", argLength: 3, commutative: false},
- {name: "LessUint32x8", argLength: 2, commutative: false},
- {name: "LessEqualUint32x8", argLength: 2, commutative: false},
- {name: "LessEqualMaskedUint32x8", argLength: 3, commutative: false},
- {name: "LessMaskedUint32x8", argLength: 3, commutative: false},
- {name: "MaxUint32x8", argLength: 2, commutative: true},
- {name: "MaxMaskedUint32x8", argLength: 3, commutative: true},
- {name: "MinUint32x8", argLength: 2, commutative: true},
- {name: "MinMaskedUint32x8", argLength: 3, commutative: true},
- {name: "MulEvenWidenUint32x8", argLength: 2, commutative: true},
- {name: "NotEqualUint32x8", argLength: 2, commutative: true},
- {name: "NotEqualMaskedUint32x8", argLength: 3, commutative: true},
- {name: "OrUint32x8", argLength: 2, commutative: true},
- {name: "OrMaskedUint32x8", argLength: 3, commutative: true},
- {name: "PairwiseAddUint32x8", argLength: 2, commutative: false},
- {name: "PairwiseSubUint32x8", argLength: 2, commutative: false},
- {name: "PermuteUint32x8", argLength: 2, commutative: false},
- {name: "PermuteFloat32x8", argLength: 2, commutative: false},
- {name: "PermuteInt32x8", argLength: 2, commutative: false},
- {name: "Permute2Int32x8", argLength: 3, commutative: false},
- {name: "Permute2Float32x8", argLength: 3, commutative: false},
- {name: "Permute2Uint32x8", argLength: 3, commutative: false},
- {name: "Permute2MaskedFloat32x8", argLength: 4, commutative: false},
- {name: "Permute2MaskedUint32x8", argLength: 4, commutative: false},
- {name: "Permute2MaskedInt32x8", argLength: 4, commutative: false},
- {name: "PermuteMaskedInt32x8", argLength: 3, commutative: false},
- {name: "PermuteMaskedUint32x8", argLength: 3, commutative: false},
- {name: "PermuteMaskedFloat32x8", argLength: 3, commutative: false},
- {name: "PopCountUint32x8", argLength: 1, commutative: false},
- {name: "PopCountMaskedUint32x8", argLength: 2, commutative: false},
- {name: "RotateLeftUint32x8", argLength: 2, commutative: false},
- {name: "RotateLeftMaskedUint32x8", argLength: 3, commutative: false},
- {name: "RotateRightUint32x8", argLength: 2, commutative: false},
- {name: "RotateRightMaskedUint32x8", argLength: 3, commutative: false},
- {name: "ShiftAllLeftUint32x8", argLength: 2, commutative: false},
- {name: "ShiftAllLeftMaskedUint32x8", argLength: 3, commutative: false},
- {name: "ShiftAllRightUint32x8", argLength: 2, commutative: false},
- {name: "ShiftAllRightMaskedUint32x8", argLength: 3, commutative: false},
- {name: "ShiftLeftUint32x8", argLength: 2, commutative: false},
- {name: "ShiftLeftAndFillUpperFromUint32x8", argLength: 3, commutative: false},
- {name: "ShiftLeftAndFillUpperFromMaskedUint32x8", argLength: 4, commutative: false},
- {name: "ShiftLeftMaskedUint32x8", argLength: 3, commutative: false},
- {name: "ShiftRightUint32x8", argLength: 2, commutative: false},
- {name: "ShiftRightAndFillUpperFromUint32x8", argLength: 3, commutative: false},
- {name: "ShiftRightAndFillUpperFromMaskedUint32x8", argLength: 4, commutative: false},
- {name: "ShiftRightMaskedUint32x8", argLength: 3, commutative: false},
- {name: "SubUint32x8", argLength: 2, commutative: false},
- {name: "SubMaskedUint32x8", argLength: 3, commutative: false},
- {name: "XorUint32x8", argLength: 2, commutative: true},
- {name: "XorMaskedUint32x8", argLength: 3, commutative: true},
- {name: "AddUint64x2", argLength: 2, commutative: true},
- {name: "AddMaskedUint64x2", argLength: 3, commutative: true},
- {name: "AndUint64x2", argLength: 2, commutative: true},
- {name: "AndMaskedUint64x2", argLength: 3, commutative: true},
- {name: "AndNotUint64x2", argLength: 2, commutative: false},
- {name: "AndNotMaskedUint64x2", argLength: 3, commutative: false},
- {name: "CompressUint64x2", argLength: 2, commutative: false},
- {name: "EqualUint64x2", argLength: 2, commutative: true},
- {name: "EqualMaskedUint64x2", argLength: 3, commutative: true},
- {name: "GreaterUint64x2", argLength: 2, commutative: false},
- {name: "GreaterEqualUint64x2", argLength: 2, commutative: false},
- {name: "GreaterEqualMaskedUint64x2", argLength: 3, commutative: false},
- {name: "GreaterMaskedUint64x2", argLength: 3, commutative: false},
- {name: "LessUint64x2", argLength: 2, commutative: false},
- {name: "LessEqualUint64x2", argLength: 2, commutative: false},
- {name: "LessEqualMaskedUint64x2", argLength: 3, commutative: false},
- {name: "LessMaskedUint64x2", argLength: 3, commutative: false},
- {name: "MaxUint64x2", argLength: 2, commutative: true},
- {name: "MaxMaskedUint64x2", argLength: 3, commutative: true},
- {name: "MinUint64x2", argLength: 2, commutative: true},
- {name: "MinMaskedUint64x2", argLength: 3, commutative: true},
- {name: "MulEvenWidenUint64x2", argLength: 2, commutative: true},
- {name: "MulEvenWidenMaskedUint64x2", argLength: 3, commutative: true},
- {name: "NotEqualUint64x2", argLength: 2, commutative: true},
- {name: "NotEqualMaskedUint64x2", argLength: 3, commutative: true},
- {name: "OrUint64x2", argLength: 2, commutative: true},
- {name: "OrMaskedUint64x2", argLength: 3, commutative: true},
- {name: "Permute2Float64x2", argLength: 3, commutative: false},
- {name: "Permute2Uint64x2", argLength: 3, commutative: false},
- {name: "Permute2Int64x2", argLength: 3, commutative: false},
- {name: "Permute2MaskedInt64x2", argLength: 4, commutative: false},
- {name: "Permute2MaskedFloat64x2", argLength: 4, commutative: false},
- {name: "Permute2MaskedUint64x2", argLength: 4, commutative: false},
- {name: "PopCountUint64x2", argLength: 1, commutative: false},
- {name: "PopCountMaskedUint64x2", argLength: 2, commutative: false},
- {name: "RotateLeftUint64x2", argLength: 2, commutative: false},
- {name: "RotateLeftMaskedUint64x2", argLength: 3, commutative: false},
- {name: "RotateRightUint64x2", argLength: 2, commutative: false},
- {name: "RotateRightMaskedUint64x2", argLength: 3, commutative: false},
- {name: "ShiftAllLeftUint64x2", argLength: 2, commutative: false},
- {name: "ShiftAllLeftMaskedUint64x2", argLength: 3, commutative: false},
- {name: "ShiftAllRightUint64x2", argLength: 2, commutative: false},
- {name: "ShiftAllRightMaskedUint64x2", argLength: 3, commutative: false},
- {name: "ShiftLeftUint64x2", argLength: 2, commutative: false},
- {name: "ShiftLeftAndFillUpperFromUint64x2", argLength: 3, commutative: false},
- {name: "ShiftLeftAndFillUpperFromMaskedUint64x2", argLength: 4, commutative: false},
- {name: "ShiftLeftMaskedUint64x2", argLength: 3, commutative: false},
- {name: "ShiftRightUint64x2", argLength: 2, commutative: false},
- {name: "ShiftRightAndFillUpperFromUint64x2", argLength: 3, commutative: false},
- {name: "ShiftRightAndFillUpperFromMaskedUint64x2", argLength: 4, commutative: false},
- {name: "ShiftRightMaskedUint64x2", argLength: 3, commutative: false},
- {name: "SubUint64x2", argLength: 2, commutative: false},
- {name: "SubMaskedUint64x2", argLength: 3, commutative: false},
- {name: "XorUint64x2", argLength: 2, commutative: true},
- {name: "XorMaskedUint64x2", argLength: 3, commutative: true},
- {name: "AddUint64x4", argLength: 2, commutative: true},
- {name: "AddMaskedUint64x4", argLength: 3, commutative: true},
- {name: "AndUint64x4", argLength: 2, commutative: true},
- {name: "AndMaskedUint64x4", argLength: 3, commutative: true},
- {name: "AndNotUint64x4", argLength: 2, commutative: false},
- {name: "AndNotMaskedUint64x4", argLength: 3, commutative: false},
- {name: "CompressUint64x4", argLength: 2, commutative: false},
- {name: "EqualUint64x4", argLength: 2, commutative: true},
- {name: "EqualMaskedUint64x4", argLength: 3, commutative: true},
- {name: "GreaterUint64x4", argLength: 2, commutative: false},
- {name: "GreaterEqualUint64x4", argLength: 2, commutative: false},
- {name: "GreaterEqualMaskedUint64x4", argLength: 3, commutative: false},
- {name: "GreaterMaskedUint64x4", argLength: 3, commutative: false},
- {name: "LessUint64x4", argLength: 2, commutative: false},
- {name: "LessEqualUint64x4", argLength: 2, commutative: false},
- {name: "LessEqualMaskedUint64x4", argLength: 3, commutative: false},
- {name: "LessMaskedUint64x4", argLength: 3, commutative: false},
- {name: "MaxUint64x4", argLength: 2, commutative: true},
- {name: "MaxMaskedUint64x4", argLength: 3, commutative: true},
- {name: "MinUint64x4", argLength: 2, commutative: true},
- {name: "MinMaskedUint64x4", argLength: 3, commutative: true},
- {name: "MulEvenWidenUint64x4", argLength: 2, commutative: true},
- {name: "MulEvenWidenMaskedUint64x4", argLength: 3, commutative: true},
- {name: "NotEqualUint64x4", argLength: 2, commutative: true},
- {name: "NotEqualMaskedUint64x4", argLength: 3, commutative: true},
- {name: "OrUint64x4", argLength: 2, commutative: true},
- {name: "OrMaskedUint64x4", argLength: 3, commutative: true},
- {name: "PermuteUint64x4", argLength: 2, commutative: false},
- {name: "PermuteInt64x4", argLength: 2, commutative: false},
- {name: "PermuteFloat64x4", argLength: 2, commutative: false},
- {name: "Permute2Uint64x4", argLength: 3, commutative: false},
- {name: "Permute2Int64x4", argLength: 3, commutative: false},
- {name: "Permute2Float64x4", argLength: 3, commutative: false},
- {name: "Permute2MaskedUint64x4", argLength: 4, commutative: false},
- {name: "Permute2MaskedFloat64x4", argLength: 4, commutative: false},
- {name: "Permute2MaskedInt64x4", argLength: 4, commutative: false},
- {name: "PermuteMaskedUint64x4", argLength: 3, commutative: false},
- {name: "PermuteMaskedFloat64x4", argLength: 3, commutative: false},
- {name: "PermuteMaskedInt64x4", argLength: 3, commutative: false},
- {name: "PopCountUint64x4", argLength: 1, commutative: false},
- {name: "PopCountMaskedUint64x4", argLength: 2, commutative: false},
- {name: "RotateLeftUint64x4", argLength: 2, commutative: false},
- {name: "RotateLeftMaskedUint64x4", argLength: 3, commutative: false},
- {name: "RotateRightUint64x4", argLength: 2, commutative: false},
- {name: "RotateRightMaskedUint64x4", argLength: 3, commutative: false},
- {name: "ShiftAllLeftUint64x4", argLength: 2, commutative: false},
- {name: "ShiftAllLeftMaskedUint64x4", argLength: 3, commutative: false},
- {name: "ShiftAllRightUint64x4", argLength: 2, commutative: false},
- {name: "ShiftAllRightMaskedUint64x4", argLength: 3, commutative: false},
- {name: "ShiftLeftUint64x4", argLength: 2, commutative: false},
- {name: "ShiftLeftAndFillUpperFromUint64x4", argLength: 3, commutative: false},
- {name: "ShiftLeftAndFillUpperFromMaskedUint64x4", argLength: 4, commutative: false},
- {name: "ShiftLeftMaskedUint64x4", argLength: 3, commutative: false},
- {name: "ShiftRightUint64x4", argLength: 2, commutative: false},
- {name: "ShiftRightAndFillUpperFromUint64x4", argLength: 3, commutative: false},
- {name: "ShiftRightAndFillUpperFromMaskedUint64x4", argLength: 4, commutative: false},
- {name: "ShiftRightMaskedUint64x4", argLength: 3, commutative: false},
- {name: "SubUint64x4", argLength: 2, commutative: false},
- {name: "SubMaskedUint64x4", argLength: 3, commutative: false},
- {name: "XorUint64x4", argLength: 2, commutative: true},
- {name: "XorMaskedUint64x4", argLength: 3, commutative: true},
- {name: "AddUint64x8", argLength: 2, commutative: true},
- {name: "AddMaskedUint64x8", argLength: 3, commutative: true},
- {name: "AndUint64x8", argLength: 2, commutative: true},
- {name: "AndMaskedUint64x8", argLength: 3, commutative: true},
- {name: "AndNotUint64x8", argLength: 2, commutative: false},
- {name: "AndNotMaskedUint64x8", argLength: 3, commutative: false},
- {name: "CompressUint64x8", argLength: 2, commutative: false},
- {name: "EqualUint64x8", argLength: 2, commutative: true},
- {name: "EqualMaskedUint64x8", argLength: 3, commutative: true},
- {name: "GreaterUint64x8", argLength: 2, commutative: false},
- {name: "GreaterEqualUint64x8", argLength: 2, commutative: false},
- {name: "GreaterEqualMaskedUint64x8", argLength: 3, commutative: false},
- {name: "GreaterMaskedUint64x8", argLength: 3, commutative: false},
- {name: "LessUint64x8", argLength: 2, commutative: false},
- {name: "LessEqualUint64x8", argLength: 2, commutative: false},
- {name: "LessEqualMaskedUint64x8", argLength: 3, commutative: false},
- {name: "LessMaskedUint64x8", argLength: 3, commutative: false},
- {name: "MaxUint64x8", argLength: 2, commutative: true},
- {name: "MaxMaskedUint64x8", argLength: 3, commutative: true},
- {name: "MinUint64x8", argLength: 2, commutative: true},
- {name: "MinMaskedUint64x8", argLength: 3, commutative: true},
- {name: "MulEvenWidenUint64x8", argLength: 2, commutative: true},
- {name: "MulEvenWidenMaskedUint64x8", argLength: 3, commutative: true},
- {name: "NotEqualUint64x8", argLength: 2, commutative: true},
- {name: "NotEqualMaskedUint64x8", argLength: 3, commutative: true},
- {name: "OrUint64x8", argLength: 2, commutative: true},
- {name: "OrMaskedUint64x8", argLength: 3, commutative: true},
- {name: "PermuteUint64x8", argLength: 2, commutative: false},
- {name: "PermuteFloat64x8", argLength: 2, commutative: false},
- {name: "PermuteInt64x8", argLength: 2, commutative: false},
- {name: "Permute2Float64x8", argLength: 3, commutative: false},
- {name: "Permute2Uint64x8", argLength: 3, commutative: false},
- {name: "Permute2Int64x8", argLength: 3, commutative: false},
- {name: "Permute2MaskedFloat64x8", argLength: 4, commutative: false},
- {name: "Permute2MaskedUint64x8", argLength: 4, commutative: false},
- {name: "Permute2MaskedInt64x8", argLength: 4, commutative: false},
- {name: "PermuteMaskedInt64x8", argLength: 3, commutative: false},
- {name: "PermuteMaskedFloat64x8", argLength: 3, commutative: false},
- {name: "PermuteMaskedUint64x8", argLength: 3, commutative: false},
- {name: "PopCountUint64x8", argLength: 1, commutative: false},
- {name: "PopCountMaskedUint64x8", argLength: 2, commutative: false},
- {name: "RotateLeftUint64x8", argLength: 2, commutative: false},
- {name: "RotateLeftMaskedUint64x8", argLength: 3, commutative: false},
- {name: "RotateRightUint64x8", argLength: 2, commutative: false},
- {name: "RotateRightMaskedUint64x8", argLength: 3, commutative: false},
- {name: "ShiftAllLeftUint64x8", argLength: 2, commutative: false},
- {name: "ShiftAllLeftMaskedUint64x8", argLength: 3, commutative: false},
- {name: "ShiftAllRightUint64x8", argLength: 2, commutative: false},
- {name: "ShiftAllRightMaskedUint64x8", argLength: 3, commutative: false},
- {name: "ShiftLeftUint64x8", argLength: 2, commutative: false},
- {name: "ShiftLeftAndFillUpperFromUint64x8", argLength: 3, commutative: false},
- {name: "ShiftLeftAndFillUpperFromMaskedUint64x8", argLength: 4, commutative: false},
- {name: "ShiftLeftMaskedUint64x8", argLength: 3, commutative: false},
- {name: "ShiftRightUint64x8", argLength: 2, commutative: false},
- {name: "ShiftRightAndFillUpperFromUint64x8", argLength: 3, commutative: false},
- {name: "ShiftRightAndFillUpperFromMaskedUint64x8", argLength: 4, commutative: false},
- {name: "ShiftRightMaskedUint64x8", argLength: 3, commutative: false},
- {name: "SubUint64x8", argLength: 2, commutative: false},
- {name: "SubMaskedUint64x8", argLength: 3, commutative: false},
- {name: "XorUint64x8", argLength: 2, commutative: true},
- {name: "XorMaskedUint64x8", argLength: 3, commutative: true},
- {name: "AddUint8x16", argLength: 2, commutative: true},
- {name: "AddMaskedUint8x16", argLength: 3, commutative: true},
- {name: "AndUint8x16", argLength: 2, commutative: true},
- {name: "AndNotUint8x16", argLength: 2, commutative: false},
- {name: "AverageUint8x16", argLength: 2, commutative: true},
- {name: "AverageMaskedUint8x16", argLength: 3, commutative: true},
- {name: "CompressUint8x16", argLength: 2, commutative: false},
- {name: "EqualUint8x16", argLength: 2, commutative: true},
- {name: "EqualMaskedUint8x16", argLength: 3, commutative: true},
- {name: "GaloisFieldMulUint8x16", argLength: 2, commutative: false},
- {name: "GaloisFieldMulMaskedUint8x16", argLength: 3, commutative: false},
- {name: "GreaterUint8x16", argLength: 2, commutative: false},
- {name: "GreaterEqualUint8x16", argLength: 2, commutative: false},
- {name: "GreaterEqualMaskedUint8x16", argLength: 3, commutative: false},
- {name: "GreaterMaskedUint8x16", argLength: 3, commutative: false},
- {name: "LessUint8x16", argLength: 2, commutative: false},
- {name: "LessEqualUint8x16", argLength: 2, commutative: false},
- {name: "LessEqualMaskedUint8x16", argLength: 3, commutative: false},
- {name: "LessMaskedUint8x16", argLength: 3, commutative: false},
- {name: "MaxUint8x16", argLength: 2, commutative: true},
- {name: "MaxMaskedUint8x16", argLength: 3, commutative: true},
- {name: "MinUint8x16", argLength: 2, commutative: true},
- {name: "MinMaskedUint8x16", argLength: 3, commutative: true},
- {name: "NotEqualUint8x16", argLength: 2, commutative: true},
- {name: "NotEqualMaskedUint8x16", argLength: 3, commutative: true},
- {name: "OrUint8x16", argLength: 2, commutative: true},
- {name: "PermuteUint8x16", argLength: 2, commutative: false},
- {name: "PermuteInt8x16", argLength: 2, commutative: false},
- {name: "Permute2Uint8x16", argLength: 3, commutative: false},
- {name: "Permute2Int8x16", argLength: 3, commutative: false},
- {name: "Permute2MaskedInt8x16", argLength: 4, commutative: false},
- {name: "Permute2MaskedUint8x16", argLength: 4, commutative: false},
- {name: "PermuteMaskedUint8x16", argLength: 3, commutative: false},
- {name: "PermuteMaskedInt8x16", argLength: 3, commutative: false},
- {name: "PopCountUint8x16", argLength: 1, commutative: false},
- {name: "PopCountMaskedUint8x16", argLength: 2, commutative: false},
- {name: "SaturatedAddUint8x16", argLength: 2, commutative: true},
- {name: "SaturatedAddMaskedUint8x16", argLength: 3, commutative: true},
- {name: "SaturatedSubUint8x16", argLength: 2, commutative: false},
- {name: "SaturatedSubMaskedUint8x16", argLength: 3, commutative: false},
- {name: "SaturatedUnsignedSignedPairDotProdUint8x16", argLength: 2, commutative: false},
- {name: "SaturatedUnsignedSignedPairDotProdMaskedUint8x16", argLength: 3, commutative: false},
- {name: "SubUint8x16", argLength: 2, commutative: false},
- {name: "SubMaskedUint8x16", argLength: 3, commutative: false},
- {name: "XorUint8x16", argLength: 2, commutative: true},
- {name: "AddUint8x32", argLength: 2, commutative: true},
- {name: "AddMaskedUint8x32", argLength: 3, commutative: true},
- {name: "AndUint8x32", argLength: 2, commutative: true},
- {name: "AndNotUint8x32", argLength: 2, commutative: false},
- {name: "AverageUint8x32", argLength: 2, commutative: true},
- {name: "AverageMaskedUint8x32", argLength: 3, commutative: true},
- {name: "CompressUint8x32", argLength: 2, commutative: false},
- {name: "EqualUint8x32", argLength: 2, commutative: true},
- {name: "EqualMaskedUint8x32", argLength: 3, commutative: true},
- {name: "GaloisFieldMulUint8x32", argLength: 2, commutative: false},
- {name: "GaloisFieldMulMaskedUint8x32", argLength: 3, commutative: false},
- {name: "GreaterUint8x32", argLength: 2, commutative: false},
- {name: "GreaterEqualUint8x32", argLength: 2, commutative: false},
- {name: "GreaterEqualMaskedUint8x32", argLength: 3, commutative: false},
- {name: "GreaterMaskedUint8x32", argLength: 3, commutative: false},
- {name: "LessUint8x32", argLength: 2, commutative: false},
- {name: "LessEqualUint8x32", argLength: 2, commutative: false},
- {name: "LessEqualMaskedUint8x32", argLength: 3, commutative: false},
- {name: "LessMaskedUint8x32", argLength: 3, commutative: false},
- {name: "MaxUint8x32", argLength: 2, commutative: true},
- {name: "MaxMaskedUint8x32", argLength: 3, commutative: true},
- {name: "MinUint8x32", argLength: 2, commutative: true},
- {name: "MinMaskedUint8x32", argLength: 3, commutative: true},
- {name: "NotEqualUint8x32", argLength: 2, commutative: true},
- {name: "NotEqualMaskedUint8x32", argLength: 3, commutative: true},
- {name: "OrUint8x32", argLength: 2, commutative: true},
- {name: "PermuteUint8x32", argLength: 2, commutative: false},
- {name: "PermuteInt8x32", argLength: 2, commutative: false},
- {name: "Permute2Int8x32", argLength: 3, commutative: false},
- {name: "Permute2Uint8x32", argLength: 3, commutative: false},
- {name: "Permute2MaskedUint8x32", argLength: 4, commutative: false},
- {name: "Permute2MaskedInt8x32", argLength: 4, commutative: false},
- {name: "PermuteMaskedUint8x32", argLength: 3, commutative: false},
- {name: "PermuteMaskedInt8x32", argLength: 3, commutative: false},
- {name: "PopCountUint8x32", argLength: 1, commutative: false},
- {name: "PopCountMaskedUint8x32", argLength: 2, commutative: false},
- {name: "SaturatedAddUint8x32", argLength: 2, commutative: true},
- {name: "SaturatedAddMaskedUint8x32", argLength: 3, commutative: true},
- {name: "SaturatedSubUint8x32", argLength: 2, commutative: false},
- {name: "SaturatedSubMaskedUint8x32", argLength: 3, commutative: false},
- {name: "SaturatedUnsignedSignedPairDotProdUint8x32", argLength: 2, commutative: false},
- {name: "SaturatedUnsignedSignedPairDotProdMaskedUint8x32", argLength: 3, commutative: false},
- {name: "SubUint8x32", argLength: 2, commutative: false},
- {name: "SubMaskedUint8x32", argLength: 3, commutative: false},
- {name: "XorUint8x32", argLength: 2, commutative: true},
- {name: "AddUint8x64", argLength: 2, commutative: true},
- {name: "AddMaskedUint8x64", argLength: 3, commutative: true},
- {name: "AverageUint8x64", argLength: 2, commutative: true},
- {name: "AverageMaskedUint8x64", argLength: 3, commutative: true},
- {name: "CompressUint8x64", argLength: 2, commutative: false},
- {name: "EqualUint8x64", argLength: 2, commutative: true},
- {name: "EqualMaskedUint8x64", argLength: 3, commutative: true},
- {name: "GaloisFieldMulUint8x64", argLength: 2, commutative: false},
- {name: "GaloisFieldMulMaskedUint8x64", argLength: 3, commutative: false},
- {name: "GreaterUint8x64", argLength: 2, commutative: false},
- {name: "GreaterEqualUint8x64", argLength: 2, commutative: false},
- {name: "GreaterEqualMaskedUint8x64", argLength: 3, commutative: false},
- {name: "GreaterMaskedUint8x64", argLength: 3, commutative: false},
- {name: "LessUint8x64", argLength: 2, commutative: false},
- {name: "LessEqualUint8x64", argLength: 2, commutative: false},
- {name: "LessEqualMaskedUint8x64", argLength: 3, commutative: false},
- {name: "LessMaskedUint8x64", argLength: 3, commutative: false},
- {name: "MaxUint8x64", argLength: 2, commutative: true},
- {name: "MaxMaskedUint8x64", argLength: 3, commutative: true},
- {name: "MinUint8x64", argLength: 2, commutative: true},
- {name: "MinMaskedUint8x64", argLength: 3, commutative: true},
- {name: "NotEqualUint8x64", argLength: 2, commutative: true},
- {name: "NotEqualMaskedUint8x64", argLength: 3, commutative: true},
- {name: "PermuteInt8x64", argLength: 2, commutative: false},
- {name: "PermuteUint8x64", argLength: 2, commutative: false},
- {name: "Permute2Uint8x64", argLength: 3, commutative: false},
- {name: "Permute2Int8x64", argLength: 3, commutative: false},
- {name: "Permute2MaskedUint8x64", argLength: 4, commutative: false},
- {name: "Permute2MaskedInt8x64", argLength: 4, commutative: false},
- {name: "PermuteMaskedUint8x64", argLength: 3, commutative: false},
- {name: "PermuteMaskedInt8x64", argLength: 3, commutative: false},
- {name: "PopCountUint8x64", argLength: 1, commutative: false},
- {name: "PopCountMaskedUint8x64", argLength: 2, commutative: false},
- {name: "SaturatedAddUint8x64", argLength: 2, commutative: true},
- {name: "SaturatedAddMaskedUint8x64", argLength: 3, commutative: true},
- {name: "SaturatedSubUint8x64", argLength: 2, commutative: false},
- {name: "SaturatedSubMaskedUint8x64", argLength: 3, commutative: false},
- {name: "SaturatedUnsignedSignedPairDotProdUint8x64", argLength: 2, commutative: false},
- {name: "SaturatedUnsignedSignedPairDotProdMaskedUint8x64", argLength: 3, commutative: false},
+ {name: "SubMaskedUint32x4", argLength: 3, commutative: false},
+ {name: "SubMaskedUint32x8", argLength: 3, commutative: false},
+ {name: "SubMaskedUint32x16", argLength: 3, commutative: false},
+ {name: "SubMaskedUint64x2", argLength: 3, commutative: false},
+ {name: "SubMaskedUint64x4", argLength: 3, commutative: false},
+ {name: "SubMaskedUint64x8", argLength: 3, commutative: false},
+ {name: "SubUint8x16", argLength: 2, commutative: false},
+ {name: "SubUint8x32", argLength: 2, commutative: false},
{name: "SubUint8x64", argLength: 2, commutative: false},
- {name: "SubMaskedUint8x64", argLength: 3, commutative: false},
- {name: "CeilWithPrecisionFloat32x16", argLength: 1, commutative: false, aux: "Int8"},
- {name: "CeilWithPrecisionMaskedFloat32x16", argLength: 2, commutative: false, aux: "Int8"},
- {name: "DiffWithCeilWithPrecisionFloat32x16", argLength: 1, commutative: false, aux: "Int8"},
- {name: "DiffWithCeilWithPrecisionMaskedFloat32x16", argLength: 2, commutative: false, aux: "Int8"},
- {name: "DiffWithFloorWithPrecisionFloat32x16", argLength: 1, commutative: false, aux: "Int8"},
- {name: "DiffWithFloorWithPrecisionMaskedFloat32x16", argLength: 2, commutative: false, aux: "Int8"},
- {name: "DiffWithRoundWithPrecisionFloat32x16", argLength: 1, commutative: false, aux: "Int8"},
- {name: "DiffWithRoundWithPrecisionMaskedFloat32x16", argLength: 2, commutative: false, aux: "Int8"},
- {name: "DiffWithTruncWithPrecisionFloat32x16", argLength: 1, commutative: false, aux: "Int8"},
- {name: "DiffWithTruncWithPrecisionMaskedFloat32x16", argLength: 2, commutative: false, aux: "Int8"},
- {name: "FloorWithPrecisionFloat32x16", argLength: 1, commutative: false, aux: "Int8"},
- {name: "FloorWithPrecisionMaskedFloat32x16", argLength: 2, commutative: false, aux: "Int8"},
- {name: "RoundWithPrecisionFloat32x16", argLength: 1, commutative: false, aux: "Int8"},
- {name: "RoundWithPrecisionMaskedFloat32x16", argLength: 2, commutative: false, aux: "Int8"},
- {name: "TruncWithPrecisionFloat32x16", argLength: 1, commutative: false, aux: "Int8"},
- {name: "TruncWithPrecisionMaskedFloat32x16", argLength: 2, commutative: false, aux: "Int8"},
+ {name: "SubUint16x8", argLength: 2, commutative: false},
+ {name: "SubUint16x16", argLength: 2, commutative: false},
+ {name: "SubUint16x32", argLength: 2, commutative: false},
+ {name: "SubUint32x4", argLength: 2, commutative: false},
+ {name: "SubUint32x8", argLength: 2, commutative: false},
+ {name: "SubUint32x16", argLength: 2, commutative: false},
+ {name: "SubUint64x2", argLength: 2, commutative: false},
+ {name: "SubUint64x4", argLength: 2, commutative: false},
+ {name: "SubUint64x8", argLength: 2, commutative: false},
+ {name: "TruncFloat32x4", argLength: 1, commutative: false},
+ {name: "TruncFloat32x8", argLength: 1, commutative: false},
+ {name: "TruncFloat64x2", argLength: 1, commutative: false},
+ {name: "TruncFloat64x4", argLength: 1, commutative: false},
+ {name: "UnsignedSignedQuadDotProdAccumulateInt32x4", argLength: 3, commutative: false},
+ {name: "UnsignedSignedQuadDotProdAccumulateInt32x8", argLength: 3, commutative: false},
+ {name: "UnsignedSignedQuadDotProdAccumulateInt32x16", argLength: 3, commutative: false},
+ {name: "UnsignedSignedQuadDotProdAccumulateMaskedInt32x4", argLength: 4, commutative: false},
+ {name: "UnsignedSignedQuadDotProdAccumulateMaskedInt32x8", argLength: 4, commutative: false},
+ {name: "UnsignedSignedQuadDotProdAccumulateMaskedInt32x16", argLength: 4, commutative: false},
+ {name: "XorInt8x16", argLength: 2, commutative: true},
+ {name: "XorInt8x32", argLength: 2, commutative: true},
+ {name: "XorInt16x8", argLength: 2, commutative: true},
+ {name: "XorInt16x16", argLength: 2, commutative: true},
+ {name: "XorInt32x4", argLength: 2, commutative: true},
+ {name: "XorInt32x8", argLength: 2, commutative: true},
+ {name: "XorInt32x16", argLength: 2, commutative: true},
+ {name: "XorInt64x2", argLength: 2, commutative: true},
+ {name: "XorInt64x4", argLength: 2, commutative: true},
+ {name: "XorInt64x8", argLength: 2, commutative: true},
+ {name: "XorMaskedInt32x4", argLength: 3, commutative: true},
+ {name: "XorMaskedInt32x8", argLength: 3, commutative: true},
+ {name: "XorMaskedInt32x16", argLength: 3, commutative: true},
+ {name: "XorMaskedInt64x2", argLength: 3, commutative: true},
+ {name: "XorMaskedInt64x4", argLength: 3, commutative: true},
+ {name: "XorMaskedInt64x8", argLength: 3, commutative: true},
+ {name: "XorMaskedUint32x4", argLength: 3, commutative: true},
+ {name: "XorMaskedUint32x8", argLength: 3, commutative: true},
+ {name: "XorMaskedUint32x16", argLength: 3, commutative: true},
+ {name: "XorMaskedUint64x2", argLength: 3, commutative: true},
+ {name: "XorMaskedUint64x4", argLength: 3, commutative: true},
+ {name: "XorMaskedUint64x8", argLength: 3, commutative: true},
+ {name: "XorUint8x16", argLength: 2, commutative: true},
+ {name: "XorUint8x32", argLength: 2, commutative: true},
+ {name: "XorUint16x8", argLength: 2, commutative: true},
+ {name: "XorUint16x16", argLength: 2, commutative: true},
+ {name: "XorUint32x4", argLength: 2, commutative: true},
+ {name: "XorUint32x8", argLength: 2, commutative: true},
+ {name: "XorUint32x16", argLength: 2, commutative: true},
+ {name: "XorUint64x2", argLength: 2, commutative: true},
+ {name: "XorUint64x4", argLength: 2, commutative: true},
+ {name: "XorUint64x8", argLength: 2, commutative: true},
{name: "CeilWithPrecisionFloat32x4", argLength: 1, commutative: false, aux: "Int8"},
- {name: "CeilWithPrecisionMaskedFloat32x4", argLength: 2, commutative: false, aux: "Int8"},
- {name: "DiffWithCeilWithPrecisionFloat32x4", argLength: 1, commutative: false, aux: "Int8"},
- {name: "DiffWithCeilWithPrecisionMaskedFloat32x4", argLength: 2, commutative: false, aux: "Int8"},
- {name: "DiffWithFloorWithPrecisionFloat32x4", argLength: 1, commutative: false, aux: "Int8"},
- {name: "DiffWithFloorWithPrecisionMaskedFloat32x4", argLength: 2, commutative: false, aux: "Int8"},
- {name: "DiffWithRoundWithPrecisionFloat32x4", argLength: 1, commutative: false, aux: "Int8"},
- {name: "DiffWithRoundWithPrecisionMaskedFloat32x4", argLength: 2, commutative: false, aux: "Int8"},
- {name: "DiffWithTruncWithPrecisionFloat32x4", argLength: 1, commutative: false, aux: "Int8"},
- {name: "DiffWithTruncWithPrecisionMaskedFloat32x4", argLength: 2, commutative: false, aux: "Int8"},
- {name: "FloorWithPrecisionFloat32x4", argLength: 1, commutative: false, aux: "Int8"},
- {name: "FloorWithPrecisionMaskedFloat32x4", argLength: 2, commutative: false, aux: "Int8"},
- {name: "RoundWithPrecisionFloat32x4", argLength: 1, commutative: false, aux: "Int8"},
- {name: "RoundWithPrecisionMaskedFloat32x4", argLength: 2, commutative: false, aux: "Int8"},
- {name: "TruncWithPrecisionFloat32x4", argLength: 1, commutative: false, aux: "Int8"},
- {name: "TruncWithPrecisionMaskedFloat32x4", argLength: 2, commutative: false, aux: "Int8"},
{name: "CeilWithPrecisionFloat32x8", argLength: 1, commutative: false, aux: "Int8"},
- {name: "CeilWithPrecisionMaskedFloat32x8", argLength: 2, commutative: false, aux: "Int8"},
- {name: "DiffWithCeilWithPrecisionFloat32x8", argLength: 1, commutative: false, aux: "Int8"},
- {name: "DiffWithCeilWithPrecisionMaskedFloat32x8", argLength: 2, commutative: false, aux: "Int8"},
- {name: "DiffWithFloorWithPrecisionFloat32x8", argLength: 1, commutative: false, aux: "Int8"},
- {name: "DiffWithFloorWithPrecisionMaskedFloat32x8", argLength: 2, commutative: false, aux: "Int8"},
- {name: "DiffWithRoundWithPrecisionFloat32x8", argLength: 1, commutative: false, aux: "Int8"},
- {name: "DiffWithRoundWithPrecisionMaskedFloat32x8", argLength: 2, commutative: false, aux: "Int8"},
- {name: "DiffWithTruncWithPrecisionFloat32x8", argLength: 1, commutative: false, aux: "Int8"},
- {name: "DiffWithTruncWithPrecisionMaskedFloat32x8", argLength: 2, commutative: false, aux: "Int8"},
- {name: "FloorWithPrecisionFloat32x8", argLength: 1, commutative: false, aux: "Int8"},
- {name: "FloorWithPrecisionMaskedFloat32x8", argLength: 2, commutative: false, aux: "Int8"},
- {name: "Get128Float32x8", argLength: 1, commutative: false, aux: "Int8"},
- {name: "RoundWithPrecisionFloat32x8", argLength: 1, commutative: false, aux: "Int8"},
- {name: "RoundWithPrecisionMaskedFloat32x8", argLength: 2, commutative: false, aux: "Int8"},
- {name: "Set128Float32x8", argLength: 2, commutative: false, aux: "Int8"},
- {name: "TruncWithPrecisionFloat32x8", argLength: 1, commutative: false, aux: "Int8"},
- {name: "TruncWithPrecisionMaskedFloat32x8", argLength: 2, commutative: false, aux: "Int8"},
+ {name: "CeilWithPrecisionFloat32x16", argLength: 1, commutative: false, aux: "Int8"},
{name: "CeilWithPrecisionFloat64x2", argLength: 1, commutative: false, aux: "Int8"},
- {name: "CeilWithPrecisionMaskedFloat64x2", argLength: 2, commutative: false, aux: "Int8"},
- {name: "DiffWithCeilWithPrecisionFloat64x2", argLength: 1, commutative: false, aux: "Int8"},
- {name: "DiffWithCeilWithPrecisionMaskedFloat64x2", argLength: 2, commutative: false, aux: "Int8"},
- {name: "DiffWithFloorWithPrecisionFloat64x2", argLength: 1, commutative: false, aux: "Int8"},
- {name: "DiffWithFloorWithPrecisionMaskedFloat64x2", argLength: 2, commutative: false, aux: "Int8"},
- {name: "DiffWithRoundWithPrecisionFloat64x2", argLength: 1, commutative: false, aux: "Int8"},
- {name: "DiffWithRoundWithPrecisionMaskedFloat64x2", argLength: 2, commutative: false, aux: "Int8"},
- {name: "DiffWithTruncWithPrecisionFloat64x2", argLength: 1, commutative: false, aux: "Int8"},
- {name: "DiffWithTruncWithPrecisionMaskedFloat64x2", argLength: 2, commutative: false, aux: "Int8"},
- {name: "FloorWithPrecisionFloat64x2", argLength: 1, commutative: false, aux: "Int8"},
- {name: "FloorWithPrecisionMaskedFloat64x2", argLength: 2, commutative: false, aux: "Int8"},
- {name: "RoundWithPrecisionFloat64x2", argLength: 1, commutative: false, aux: "Int8"},
- {name: "RoundWithPrecisionMaskedFloat64x2", argLength: 2, commutative: false, aux: "Int8"},
- {name: "TruncWithPrecisionFloat64x2", argLength: 1, commutative: false, aux: "Int8"},
- {name: "TruncWithPrecisionMaskedFloat64x2", argLength: 2, commutative: false, aux: "Int8"},
{name: "CeilWithPrecisionFloat64x4", argLength: 1, commutative: false, aux: "Int8"},
+ {name: "CeilWithPrecisionFloat64x8", argLength: 1, commutative: false, aux: "Int8"},
+ {name: "CeilWithPrecisionMaskedFloat32x4", argLength: 2, commutative: false, aux: "Int8"},
+ {name: "CeilWithPrecisionMaskedFloat32x8", argLength: 2, commutative: false, aux: "Int8"},
+ {name: "CeilWithPrecisionMaskedFloat32x16", argLength: 2, commutative: false, aux: "Int8"},
+ {name: "CeilWithPrecisionMaskedFloat64x2", argLength: 2, commutative: false, aux: "Int8"},
{name: "CeilWithPrecisionMaskedFloat64x4", argLength: 2, commutative: false, aux: "Int8"},
+ {name: "CeilWithPrecisionMaskedFloat64x8", argLength: 2, commutative: false, aux: "Int8"},
+ {name: "DiffWithCeilWithPrecisionFloat32x4", argLength: 1, commutative: false, aux: "Int8"},
+ {name: "DiffWithCeilWithPrecisionFloat32x8", argLength: 1, commutative: false, aux: "Int8"},
+ {name: "DiffWithCeilWithPrecisionFloat32x16", argLength: 1, commutative: false, aux: "Int8"},
+ {name: "DiffWithCeilWithPrecisionFloat64x2", argLength: 1, commutative: false, aux: "Int8"},
{name: "DiffWithCeilWithPrecisionFloat64x4", argLength: 1, commutative: false, aux: "Int8"},
+ {name: "DiffWithCeilWithPrecisionFloat64x8", argLength: 1, commutative: false, aux: "Int8"},
+ {name: "DiffWithCeilWithPrecisionMaskedFloat32x4", argLength: 2, commutative: false, aux: "Int8"},
+ {name: "DiffWithCeilWithPrecisionMaskedFloat32x8", argLength: 2, commutative: false, aux: "Int8"},
+ {name: "DiffWithCeilWithPrecisionMaskedFloat32x16", argLength: 2, commutative: false, aux: "Int8"},
+ {name: "DiffWithCeilWithPrecisionMaskedFloat64x2", argLength: 2, commutative: false, aux: "Int8"},
{name: "DiffWithCeilWithPrecisionMaskedFloat64x4", argLength: 2, commutative: false, aux: "Int8"},
+ {name: "DiffWithCeilWithPrecisionMaskedFloat64x8", argLength: 2, commutative: false, aux: "Int8"},
+ {name: "DiffWithFloorWithPrecisionFloat32x4", argLength: 1, commutative: false, aux: "Int8"},
+ {name: "DiffWithFloorWithPrecisionFloat32x8", argLength: 1, commutative: false, aux: "Int8"},
+ {name: "DiffWithFloorWithPrecisionFloat32x16", argLength: 1, commutative: false, aux: "Int8"},
+ {name: "DiffWithFloorWithPrecisionFloat64x2", argLength: 1, commutative: false, aux: "Int8"},
{name: "DiffWithFloorWithPrecisionFloat64x4", argLength: 1, commutative: false, aux: "Int8"},
+ {name: "DiffWithFloorWithPrecisionFloat64x8", argLength: 1, commutative: false, aux: "Int8"},
+ {name: "DiffWithFloorWithPrecisionMaskedFloat32x4", argLength: 2, commutative: false, aux: "Int8"},
+ {name: "DiffWithFloorWithPrecisionMaskedFloat32x8", argLength: 2, commutative: false, aux: "Int8"},
+ {name: "DiffWithFloorWithPrecisionMaskedFloat32x16", argLength: 2, commutative: false, aux: "Int8"},
+ {name: "DiffWithFloorWithPrecisionMaskedFloat64x2", argLength: 2, commutative: false, aux: "Int8"},
{name: "DiffWithFloorWithPrecisionMaskedFloat64x4", argLength: 2, commutative: false, aux: "Int8"},
+ {name: "DiffWithFloorWithPrecisionMaskedFloat64x8", argLength: 2, commutative: false, aux: "Int8"},
+ {name: "DiffWithRoundWithPrecisionFloat32x4", argLength: 1, commutative: false, aux: "Int8"},
+ {name: "DiffWithRoundWithPrecisionFloat32x8", argLength: 1, commutative: false, aux: "Int8"},
+ {name: "DiffWithRoundWithPrecisionFloat32x16", argLength: 1, commutative: false, aux: "Int8"},
+ {name: "DiffWithRoundWithPrecisionFloat64x2", argLength: 1, commutative: false, aux: "Int8"},
{name: "DiffWithRoundWithPrecisionFloat64x4", argLength: 1, commutative: false, aux: "Int8"},
+ {name: "DiffWithRoundWithPrecisionFloat64x8", argLength: 1, commutative: false, aux: "Int8"},
+ {name: "DiffWithRoundWithPrecisionMaskedFloat32x4", argLength: 2, commutative: false, aux: "Int8"},
+ {name: "DiffWithRoundWithPrecisionMaskedFloat32x8", argLength: 2, commutative: false, aux: "Int8"},
+ {name: "DiffWithRoundWithPrecisionMaskedFloat32x16", argLength: 2, commutative: false, aux: "Int8"},
+ {name: "DiffWithRoundWithPrecisionMaskedFloat64x2", argLength: 2, commutative: false, aux: "Int8"},
{name: "DiffWithRoundWithPrecisionMaskedFloat64x4", argLength: 2, commutative: false, aux: "Int8"},
+ {name: "DiffWithRoundWithPrecisionMaskedFloat64x8", argLength: 2, commutative: false, aux: "Int8"},
+ {name: "DiffWithTruncWithPrecisionFloat32x4", argLength: 1, commutative: false, aux: "Int8"},
+ {name: "DiffWithTruncWithPrecisionFloat32x8", argLength: 1, commutative: false, aux: "Int8"},
+ {name: "DiffWithTruncWithPrecisionFloat32x16", argLength: 1, commutative: false, aux: "Int8"},
+ {name: "DiffWithTruncWithPrecisionFloat64x2", argLength: 1, commutative: false, aux: "Int8"},
{name: "DiffWithTruncWithPrecisionFloat64x4", argLength: 1, commutative: false, aux: "Int8"},
+ {name: "DiffWithTruncWithPrecisionFloat64x8", argLength: 1, commutative: false, aux: "Int8"},
+ {name: "DiffWithTruncWithPrecisionMaskedFloat32x4", argLength: 2, commutative: false, aux: "Int8"},
+ {name: "DiffWithTruncWithPrecisionMaskedFloat32x8", argLength: 2, commutative: false, aux: "Int8"},
+ {name: "DiffWithTruncWithPrecisionMaskedFloat32x16", argLength: 2, commutative: false, aux: "Int8"},
+ {name: "DiffWithTruncWithPrecisionMaskedFloat64x2", argLength: 2, commutative: false, aux: "Int8"},
{name: "DiffWithTruncWithPrecisionMaskedFloat64x4", argLength: 2, commutative: false, aux: "Int8"},
+ {name: "DiffWithTruncWithPrecisionMaskedFloat64x8", argLength: 2, commutative: false, aux: "Int8"},
+ {name: "FloorWithPrecisionFloat32x4", argLength: 1, commutative: false, aux: "Int8"},
+ {name: "FloorWithPrecisionFloat32x8", argLength: 1, commutative: false, aux: "Int8"},
+ {name: "FloorWithPrecisionFloat32x16", argLength: 1, commutative: false, aux: "Int8"},
+ {name: "FloorWithPrecisionFloat64x2", argLength: 1, commutative: false, aux: "Int8"},
{name: "FloorWithPrecisionFloat64x4", argLength: 1, commutative: false, aux: "Int8"},
+ {name: "FloorWithPrecisionFloat64x8", argLength: 1, commutative: false, aux: "Int8"},
+ {name: "FloorWithPrecisionMaskedFloat32x4", argLength: 2, commutative: false, aux: "Int8"},
+ {name: "FloorWithPrecisionMaskedFloat32x8", argLength: 2, commutative: false, aux: "Int8"},
+ {name: "FloorWithPrecisionMaskedFloat32x16", argLength: 2, commutative: false, aux: "Int8"},
+ {name: "FloorWithPrecisionMaskedFloat64x2", argLength: 2, commutative: false, aux: "Int8"},
{name: "FloorWithPrecisionMaskedFloat64x4", argLength: 2, commutative: false, aux: "Int8"},
+ {name: "FloorWithPrecisionMaskedFloat64x8", argLength: 2, commutative: false, aux: "Int8"},
+ {name: "GaloisFieldAffineTransformInverseMaskedUint8x16", argLength: 3, commutative: false, aux: "Int8"},
+ {name: "GaloisFieldAffineTransformInverseMaskedUint8x32", argLength: 3, commutative: false, aux: "Int8"},
+ {name: "GaloisFieldAffineTransformInverseMaskedUint8x64", argLength: 3, commutative: false, aux: "Int8"},
+ {name: "GaloisFieldAffineTransformInverseUint8x16", argLength: 2, commutative: false, aux: "Int8"},
+ {name: "GaloisFieldAffineTransformInverseUint8x32", argLength: 2, commutative: false, aux: "Int8"},
+ {name: "GaloisFieldAffineTransformInverseUint8x64", argLength: 2, commutative: false, aux: "Int8"},
+ {name: "GaloisFieldAffineTransformMaskedUint8x16", argLength: 3, commutative: false, aux: "Int8"},
+ {name: "GaloisFieldAffineTransformMaskedUint8x32", argLength: 3, commutative: false, aux: "Int8"},
+ {name: "GaloisFieldAffineTransformMaskedUint8x64", argLength: 3, commutative: false, aux: "Int8"},
+ {name: "GaloisFieldAffineTransformUint8x16", argLength: 2, commutative: false, aux: "Int8"},
+ {name: "GaloisFieldAffineTransformUint8x32", argLength: 2, commutative: false, aux: "Int8"},
+ {name: "GaloisFieldAffineTransformUint8x64", argLength: 2, commutative: false, aux: "Int8"},
+ {name: "Get128Float32x8", argLength: 1, commutative: false, aux: "Int8"},
{name: "Get128Float64x4", argLength: 1, commutative: false, aux: "Int8"},
+ {name: "Get128Int8x32", argLength: 1, commutative: false, aux: "Int8"},
+ {name: "Get128Int16x16", argLength: 1, commutative: false, aux: "Int8"},
+ {name: "Get128Int32x8", argLength: 1, commutative: false, aux: "Int8"},
+ {name: "Get128Int64x4", argLength: 1, commutative: false, aux: "Int8"},
+ {name: "Get128Uint8x32", argLength: 1, commutative: false, aux: "Int8"},
+ {name: "Get128Uint16x16", argLength: 1, commutative: false, aux: "Int8"},
+ {name: "Get128Uint32x8", argLength: 1, commutative: false, aux: "Int8"},
+ {name: "Get128Uint64x4", argLength: 1, commutative: false, aux: "Int8"},
+ {name: "GetElemInt8x16", argLength: 1, commutative: false, aux: "Int8"},
+ {name: "GetElemInt16x8", argLength: 1, commutative: false, aux: "Int8"},
+ {name: "GetElemInt32x4", argLength: 1, commutative: false, aux: "Int8"},
+ {name: "GetElemInt64x2", argLength: 1, commutative: false, aux: "Int8"},
+ {name: "GetElemUint8x16", argLength: 1, commutative: false, aux: "Int8"},
+ {name: "GetElemUint16x8", argLength: 1, commutative: false, aux: "Int8"},
+ {name: "GetElemUint32x4", argLength: 1, commutative: false, aux: "Int8"},
+ {name: "GetElemUint64x2", argLength: 1, commutative: false, aux: "Int8"},
+ {name: "RotateAllLeftInt32x4", argLength: 1, commutative: false, aux: "Int8"},
+ {name: "RotateAllLeftInt32x8", argLength: 1, commutative: false, aux: "Int8"},
+ {name: "RotateAllLeftInt32x16", argLength: 1, commutative: false, aux: "Int8"},
+ {name: "RotateAllLeftInt64x2", argLength: 1, commutative: false, aux: "Int8"},
+ {name: "RotateAllLeftInt64x4", argLength: 1, commutative: false, aux: "Int8"},
+ {name: "RotateAllLeftInt64x8", argLength: 1, commutative: false, aux: "Int8"},
+ {name: "RotateAllLeftMaskedInt32x4", argLength: 2, commutative: false, aux: "Int8"},
+ {name: "RotateAllLeftMaskedInt32x8", argLength: 2, commutative: false, aux: "Int8"},
+ {name: "RotateAllLeftMaskedInt32x16", argLength: 2, commutative: false, aux: "Int8"},
+ {name: "RotateAllLeftMaskedInt64x2", argLength: 2, commutative: false, aux: "Int8"},
+ {name: "RotateAllLeftMaskedInt64x4", argLength: 2, commutative: false, aux: "Int8"},
+ {name: "RotateAllLeftMaskedInt64x8", argLength: 2, commutative: false, aux: "Int8"},
+ {name: "RotateAllLeftMaskedUint32x4", argLength: 2, commutative: false, aux: "Int8"},
+ {name: "RotateAllLeftMaskedUint32x8", argLength: 2, commutative: false, aux: "Int8"},
+ {name: "RotateAllLeftMaskedUint32x16", argLength: 2, commutative: false, aux: "Int8"},
+ {name: "RotateAllLeftMaskedUint64x2", argLength: 2, commutative: false, aux: "Int8"},
+ {name: "RotateAllLeftMaskedUint64x4", argLength: 2, commutative: false, aux: "Int8"},
+ {name: "RotateAllLeftMaskedUint64x8", argLength: 2, commutative: false, aux: "Int8"},
+ {name: "RotateAllLeftUint32x4", argLength: 1, commutative: false, aux: "Int8"},
+ {name: "RotateAllLeftUint32x8", argLength: 1, commutative: false, aux: "Int8"},
+ {name: "RotateAllLeftUint32x16", argLength: 1, commutative: false, aux: "Int8"},
+ {name: "RotateAllLeftUint64x2", argLength: 1, commutative: false, aux: "Int8"},
+ {name: "RotateAllLeftUint64x4", argLength: 1, commutative: false, aux: "Int8"},
+ {name: "RotateAllLeftUint64x8", argLength: 1, commutative: false, aux: "Int8"},
+ {name: "RotateAllRightInt32x4", argLength: 1, commutative: false, aux: "Int8"},
+ {name: "RotateAllRightInt32x8", argLength: 1, commutative: false, aux: "Int8"},
+ {name: "RotateAllRightInt32x16", argLength: 1, commutative: false, aux: "Int8"},
+ {name: "RotateAllRightInt64x2", argLength: 1, commutative: false, aux: "Int8"},
+ {name: "RotateAllRightInt64x4", argLength: 1, commutative: false, aux: "Int8"},
+ {name: "RotateAllRightInt64x8", argLength: 1, commutative: false, aux: "Int8"},
+ {name: "RotateAllRightMaskedInt32x4", argLength: 2, commutative: false, aux: "Int8"},
+ {name: "RotateAllRightMaskedInt32x8", argLength: 2, commutative: false, aux: "Int8"},
+ {name: "RotateAllRightMaskedInt32x16", argLength: 2, commutative: false, aux: "Int8"},
+ {name: "RotateAllRightMaskedInt64x2", argLength: 2, commutative: false, aux: "Int8"},
+ {name: "RotateAllRightMaskedInt64x4", argLength: 2, commutative: false, aux: "Int8"},
+ {name: "RotateAllRightMaskedInt64x8", argLength: 2, commutative: false, aux: "Int8"},
+ {name: "RotateAllRightMaskedUint32x4", argLength: 2, commutative: false, aux: "Int8"},
+ {name: "RotateAllRightMaskedUint32x8", argLength: 2, commutative: false, aux: "Int8"},
+ {name: "RotateAllRightMaskedUint32x16", argLength: 2, commutative: false, aux: "Int8"},
+ {name: "RotateAllRightMaskedUint64x2", argLength: 2, commutative: false, aux: "Int8"},
+ {name: "RotateAllRightMaskedUint64x4", argLength: 2, commutative: false, aux: "Int8"},
+ {name: "RotateAllRightMaskedUint64x8", argLength: 2, commutative: false, aux: "Int8"},
+ {name: "RotateAllRightUint32x4", argLength: 1, commutative: false, aux: "Int8"},
+ {name: "RotateAllRightUint32x8", argLength: 1, commutative: false, aux: "Int8"},
+ {name: "RotateAllRightUint32x16", argLength: 1, commutative: false, aux: "Int8"},
+ {name: "RotateAllRightUint64x2", argLength: 1, commutative: false, aux: "Int8"},
+ {name: "RotateAllRightUint64x4", argLength: 1, commutative: false, aux: "Int8"},
+ {name: "RotateAllRightUint64x8", argLength: 1, commutative: false, aux: "Int8"},
+ {name: "RoundWithPrecisionFloat32x4", argLength: 1, commutative: false, aux: "Int8"},
+ {name: "RoundWithPrecisionFloat32x8", argLength: 1, commutative: false, aux: "Int8"},
+ {name: "RoundWithPrecisionFloat32x16", argLength: 1, commutative: false, aux: "Int8"},
+ {name: "RoundWithPrecisionFloat64x2", argLength: 1, commutative: false, aux: "Int8"},
{name: "RoundWithPrecisionFloat64x4", argLength: 1, commutative: false, aux: "Int8"},
- {name: "RoundWithPrecisionMaskedFloat64x4", argLength: 2, commutative: false, aux: "Int8"},
- {name: "Set128Float64x4", argLength: 2, commutative: false, aux: "Int8"},
- {name: "TruncWithPrecisionFloat64x4", argLength: 1, commutative: false, aux: "Int8"},
- {name: "TruncWithPrecisionMaskedFloat64x4", argLength: 2, commutative: false, aux: "Int8"},
- {name: "CeilWithPrecisionFloat64x8", argLength: 1, commutative: false, aux: "Int8"},
- {name: "CeilWithPrecisionMaskedFloat64x8", argLength: 2, commutative: false, aux: "Int8"},
- {name: "DiffWithCeilWithPrecisionFloat64x8", argLength: 1, commutative: false, aux: "Int8"},
- {name: "DiffWithCeilWithPrecisionMaskedFloat64x8", argLength: 2, commutative: false, aux: "Int8"},
- {name: "DiffWithFloorWithPrecisionFloat64x8", argLength: 1, commutative: false, aux: "Int8"},
- {name: "DiffWithFloorWithPrecisionMaskedFloat64x8", argLength: 2, commutative: false, aux: "Int8"},
- {name: "DiffWithRoundWithPrecisionFloat64x8", argLength: 1, commutative: false, aux: "Int8"},
- {name: "DiffWithRoundWithPrecisionMaskedFloat64x8", argLength: 2, commutative: false, aux: "Int8"},
- {name: "DiffWithTruncWithPrecisionFloat64x8", argLength: 1, commutative: false, aux: "Int8"},
- {name: "DiffWithTruncWithPrecisionMaskedFloat64x8", argLength: 2, commutative: false, aux: "Int8"},
- {name: "FloorWithPrecisionFloat64x8", argLength: 1, commutative: false, aux: "Int8"},
- {name: "FloorWithPrecisionMaskedFloat64x8", argLength: 2, commutative: false, aux: "Int8"},
{name: "RoundWithPrecisionFloat64x8", argLength: 1, commutative: false, aux: "Int8"},
+ {name: "RoundWithPrecisionMaskedFloat32x4", argLength: 2, commutative: false, aux: "Int8"},
+ {name: "RoundWithPrecisionMaskedFloat32x8", argLength: 2, commutative: false, aux: "Int8"},
+ {name: "RoundWithPrecisionMaskedFloat32x16", argLength: 2, commutative: false, aux: "Int8"},
+ {name: "RoundWithPrecisionMaskedFloat64x2", argLength: 2, commutative: false, aux: "Int8"},
+ {name: "RoundWithPrecisionMaskedFloat64x4", argLength: 2, commutative: false, aux: "Int8"},
{name: "RoundWithPrecisionMaskedFloat64x8", argLength: 2, commutative: false, aux: "Int8"},
- {name: "TruncWithPrecisionFloat64x8", argLength: 1, commutative: false, aux: "Int8"},
- {name: "TruncWithPrecisionMaskedFloat64x8", argLength: 2, commutative: false, aux: "Int8"},
- {name: "Get128Int16x16", argLength: 1, commutative: false, aux: "Int8"},
+ {name: "Set128Float32x8", argLength: 2, commutative: false, aux: "Int8"},
+ {name: "Set128Float64x4", argLength: 2, commutative: false, aux: "Int8"},
+ {name: "Set128Int8x32", argLength: 2, commutative: false, aux: "Int8"},
{name: "Set128Int16x16", argLength: 2, commutative: false, aux: "Int8"},
- {name: "ShiftAllLeftAndFillUpperFromInt16x16", argLength: 2, commutative: false, aux: "Int8"},
- {name: "ShiftAllLeftAndFillUpperFromMaskedInt16x16", argLength: 3, commutative: false, aux: "Int8"},
- {name: "ShiftAllRightAndFillUpperFromInt16x16", argLength: 2, commutative: false, aux: "Int8"},
- {name: "ShiftAllRightAndFillUpperFromMaskedInt16x16", argLength: 3, commutative: false, aux: "Int8"},
- {name: "ShiftAllLeftAndFillUpperFromInt16x32", argLength: 2, commutative: false, aux: "Int8"},
- {name: "ShiftAllLeftAndFillUpperFromMaskedInt16x32", argLength: 3, commutative: false, aux: "Int8"},
- {name: "ShiftAllRightAndFillUpperFromInt16x32", argLength: 2, commutative: false, aux: "Int8"},
- {name: "ShiftAllRightAndFillUpperFromMaskedInt16x32", argLength: 3, commutative: false, aux: "Int8"},
- {name: "GetElemInt16x8", argLength: 1, commutative: false, aux: "Int8"},
+ {name: "Set128Int32x8", argLength: 2, commutative: false, aux: "Int8"},
+ {name: "Set128Int64x4", argLength: 2, commutative: false, aux: "Int8"},
+ {name: "Set128Uint8x32", argLength: 2, commutative: false, aux: "Int8"},
+ {name: "Set128Uint16x16", argLength: 2, commutative: false, aux: "Int8"},
+ {name: "Set128Uint32x8", argLength: 2, commutative: false, aux: "Int8"},
+ {name: "Set128Uint64x4", argLength: 2, commutative: false, aux: "Int8"},
+ {name: "SetElemInt8x16", argLength: 2, commutative: false, aux: "Int8"},
{name: "SetElemInt16x8", argLength: 2, commutative: false, aux: "Int8"},
- {name: "ShiftAllLeftAndFillUpperFromInt16x8", argLength: 2, commutative: false, aux: "Int8"},
- {name: "ShiftAllLeftAndFillUpperFromMaskedInt16x8", argLength: 3, commutative: false, aux: "Int8"},
- {name: "ShiftAllRightAndFillUpperFromInt16x8", argLength: 2, commutative: false, aux: "Int8"},
- {name: "ShiftAllRightAndFillUpperFromMaskedInt16x8", argLength: 3, commutative: false, aux: "Int8"},
- {name: "RotateAllLeftInt32x16", argLength: 1, commutative: false, aux: "Int8"},
- {name: "RotateAllLeftMaskedInt32x16", argLength: 2, commutative: false, aux: "Int8"},
- {name: "RotateAllRightInt32x16", argLength: 1, commutative: false, aux: "Int8"},
- {name: "RotateAllRightMaskedInt32x16", argLength: 2, commutative: false, aux: "Int8"},
- {name: "ShiftAllLeftAndFillUpperFromInt32x16", argLength: 2, commutative: false, aux: "Int8"},
- {name: "ShiftAllLeftAndFillUpperFromMaskedInt32x16", argLength: 3, commutative: false, aux: "Int8"},
- {name: "ShiftAllRightAndFillUpperFromInt32x16", argLength: 2, commutative: false, aux: "Int8"},
- {name: "ShiftAllRightAndFillUpperFromMaskedInt32x16", argLength: 3, commutative: false, aux: "Int8"},
- {name: "GetElemInt32x4", argLength: 1, commutative: false, aux: "Int8"},
- {name: "RotateAllLeftInt32x4", argLength: 1, commutative: false, aux: "Int8"},
- {name: "RotateAllLeftMaskedInt32x4", argLength: 2, commutative: false, aux: "Int8"},
- {name: "RotateAllRightInt32x4", argLength: 1, commutative: false, aux: "Int8"},
- {name: "RotateAllRightMaskedInt32x4", argLength: 2, commutative: false, aux: "Int8"},
{name: "SetElemInt32x4", argLength: 2, commutative: false, aux: "Int8"},
+ {name: "SetElemInt64x2", argLength: 2, commutative: false, aux: "Int8"},
+ {name: "SetElemUint8x16", argLength: 2, commutative: false, aux: "Int8"},
+ {name: "SetElemUint16x8", argLength: 2, commutative: false, aux: "Int8"},
+ {name: "SetElemUint32x4", argLength: 2, commutative: false, aux: "Int8"},
+ {name: "SetElemUint64x2", argLength: 2, commutative: false, aux: "Int8"},
+ {name: "ShiftAllLeftAndFillUpperFromInt16x8", argLength: 2, commutative: false, aux: "Int8"},
+ {name: "ShiftAllLeftAndFillUpperFromInt16x16", argLength: 2, commutative: false, aux: "Int8"},
+ {name: "ShiftAllLeftAndFillUpperFromInt16x32", argLength: 2, commutative: false, aux: "Int8"},
{name: "ShiftAllLeftAndFillUpperFromInt32x4", argLength: 2, commutative: false, aux: "Int8"},
- {name: "ShiftAllLeftAndFillUpperFromMaskedInt32x4", argLength: 3, commutative: false, aux: "Int8"},
- {name: "ShiftAllRightAndFillUpperFromInt32x4", argLength: 2, commutative: false, aux: "Int8"},
- {name: "ShiftAllRightAndFillUpperFromMaskedInt32x4", argLength: 3, commutative: false, aux: "Int8"},
- {name: "Get128Int32x8", argLength: 1, commutative: false, aux: "Int8"},
- {name: "RotateAllLeftInt32x8", argLength: 1, commutative: false, aux: "Int8"},
- {name: "RotateAllLeftMaskedInt32x8", argLength: 2, commutative: false, aux: "Int8"},
- {name: "RotateAllRightInt32x8", argLength: 1, commutative: false, aux: "Int8"},
- {name: "RotateAllRightMaskedInt32x8", argLength: 2, commutative: false, aux: "Int8"},
- {name: "Set128Int32x8", argLength: 2, commutative: false, aux: "Int8"},
{name: "ShiftAllLeftAndFillUpperFromInt32x8", argLength: 2, commutative: false, aux: "Int8"},
- {name: "ShiftAllLeftAndFillUpperFromMaskedInt32x8", argLength: 3, commutative: false, aux: "Int8"},
- {name: "ShiftAllRightAndFillUpperFromInt32x8", argLength: 2, commutative: false, aux: "Int8"},
- {name: "ShiftAllRightAndFillUpperFromMaskedInt32x8", argLength: 3, commutative: false, aux: "Int8"},
- {name: "GetElemInt64x2", argLength: 1, commutative: false, aux: "Int8"},
- {name: "RotateAllLeftInt64x2", argLength: 1, commutative: false, aux: "Int8"},
- {name: "RotateAllLeftMaskedInt64x2", argLength: 2, commutative: false, aux: "Int8"},
- {name: "RotateAllRightInt64x2", argLength: 1, commutative: false, aux: "Int8"},
- {name: "RotateAllRightMaskedInt64x2", argLength: 2, commutative: false, aux: "Int8"},
- {name: "SetElemInt64x2", argLength: 2, commutative: false, aux: "Int8"},
+ {name: "ShiftAllLeftAndFillUpperFromInt32x16", argLength: 2, commutative: false, aux: "Int8"},
{name: "ShiftAllLeftAndFillUpperFromInt64x2", argLength: 2, commutative: false, aux: "Int8"},
- {name: "ShiftAllLeftAndFillUpperFromMaskedInt64x2", argLength: 3, commutative: false, aux: "Int8"},
- {name: "ShiftAllRightAndFillUpperFromInt64x2", argLength: 2, commutative: false, aux: "Int8"},
- {name: "ShiftAllRightAndFillUpperFromMaskedInt64x2", argLength: 3, commutative: false, aux: "Int8"},
- {name: "Get128Int64x4", argLength: 1, commutative: false, aux: "Int8"},
- {name: "RotateAllLeftInt64x4", argLength: 1, commutative: false, aux: "Int8"},
- {name: "RotateAllLeftMaskedInt64x4", argLength: 2, commutative: false, aux: "Int8"},
- {name: "RotateAllRightInt64x4", argLength: 1, commutative: false, aux: "Int8"},
- {name: "RotateAllRightMaskedInt64x4", argLength: 2, commutative: false, aux: "Int8"},
- {name: "Set128Int64x4", argLength: 2, commutative: false, aux: "Int8"},
{name: "ShiftAllLeftAndFillUpperFromInt64x4", argLength: 2, commutative: false, aux: "Int8"},
- {name: "ShiftAllLeftAndFillUpperFromMaskedInt64x4", argLength: 3, commutative: false, aux: "Int8"},
- {name: "ShiftAllRightAndFillUpperFromInt64x4", argLength: 2, commutative: false, aux: "Int8"},
- {name: "ShiftAllRightAndFillUpperFromMaskedInt64x4", argLength: 3, commutative: false, aux: "Int8"},
- {name: "RotateAllLeftInt64x8", argLength: 1, commutative: false, aux: "Int8"},
- {name: "RotateAllLeftMaskedInt64x8", argLength: 2, commutative: false, aux: "Int8"},
- {name: "RotateAllRightInt64x8", argLength: 1, commutative: false, aux: "Int8"},
- {name: "RotateAllRightMaskedInt64x8", argLength: 2, commutative: false, aux: "Int8"},
{name: "ShiftAllLeftAndFillUpperFromInt64x8", argLength: 2, commutative: false, aux: "Int8"},
+ {name: "ShiftAllLeftAndFillUpperFromMaskedInt16x8", argLength: 3, commutative: false, aux: "Int8"},
+ {name: "ShiftAllLeftAndFillUpperFromMaskedInt16x16", argLength: 3, commutative: false, aux: "Int8"},
+ {name: "ShiftAllLeftAndFillUpperFromMaskedInt16x32", argLength: 3, commutative: false, aux: "Int8"},
+ {name: "ShiftAllLeftAndFillUpperFromMaskedInt32x4", argLength: 3, commutative: false, aux: "Int8"},
+ {name: "ShiftAllLeftAndFillUpperFromMaskedInt32x8", argLength: 3, commutative: false, aux: "Int8"},
+ {name: "ShiftAllLeftAndFillUpperFromMaskedInt32x16", argLength: 3, commutative: false, aux: "Int8"},
+ {name: "ShiftAllLeftAndFillUpperFromMaskedInt64x2", argLength: 3, commutative: false, aux: "Int8"},
+ {name: "ShiftAllLeftAndFillUpperFromMaskedInt64x4", argLength: 3, commutative: false, aux: "Int8"},
{name: "ShiftAllLeftAndFillUpperFromMaskedInt64x8", argLength: 3, commutative: false, aux: "Int8"},
- {name: "ShiftAllRightAndFillUpperFromInt64x8", argLength: 2, commutative: false, aux: "Int8"},
- {name: "ShiftAllRightAndFillUpperFromMaskedInt64x8", argLength: 3, commutative: false, aux: "Int8"},
- {name: "GetElemInt8x16", argLength: 1, commutative: false, aux: "Int8"},
- {name: "SetElemInt8x16", argLength: 2, commutative: false, aux: "Int8"},
- {name: "Get128Int8x32", argLength: 1, commutative: false, aux: "Int8"},
- {name: "Set128Int8x32", argLength: 2, commutative: false, aux: "Int8"},
- {name: "Get128Uint16x16", argLength: 1, commutative: false, aux: "Int8"},
- {name: "Set128Uint16x16", argLength: 2, commutative: false, aux: "Int8"},
- {name: "ShiftAllLeftAndFillUpperFromUint16x16", argLength: 2, commutative: false, aux: "Int8"},
+ {name: "ShiftAllLeftAndFillUpperFromMaskedUint16x8", argLength: 3, commutative: false, aux: "Int8"},
{name: "ShiftAllLeftAndFillUpperFromMaskedUint16x16", argLength: 3, commutative: false, aux: "Int8"},
- {name: "ShiftAllRightAndFillUpperFromUint16x16", argLength: 2, commutative: false, aux: "Int8"},
- {name: "ShiftAllRightAndFillUpperFromMaskedUint16x16", argLength: 3, commutative: false, aux: "Int8"},
- {name: "ShiftAllLeftAndFillUpperFromUint16x32", argLength: 2, commutative: false, aux: "Int8"},
{name: "ShiftAllLeftAndFillUpperFromMaskedUint16x32", argLength: 3, commutative: false, aux: "Int8"},
- {name: "ShiftAllRightAndFillUpperFromUint16x32", argLength: 2, commutative: false, aux: "Int8"},
- {name: "ShiftAllRightAndFillUpperFromMaskedUint16x32", argLength: 3, commutative: false, aux: "Int8"},
- {name: "GetElemUint16x8", argLength: 1, commutative: false, aux: "Int8"},
- {name: "SetElemUint16x8", argLength: 2, commutative: false, aux: "Int8"},
+ {name: "ShiftAllLeftAndFillUpperFromMaskedUint32x4", argLength: 3, commutative: false, aux: "Int8"},
+ {name: "ShiftAllLeftAndFillUpperFromMaskedUint32x8", argLength: 3, commutative: false, aux: "Int8"},
+ {name: "ShiftAllLeftAndFillUpperFromMaskedUint32x16", argLength: 3, commutative: false, aux: "Int8"},
+ {name: "ShiftAllLeftAndFillUpperFromMaskedUint64x2", argLength: 3, commutative: false, aux: "Int8"},
+ {name: "ShiftAllLeftAndFillUpperFromMaskedUint64x4", argLength: 3, commutative: false, aux: "Int8"},
+ {name: "ShiftAllLeftAndFillUpperFromMaskedUint64x8", argLength: 3, commutative: false, aux: "Int8"},
{name: "ShiftAllLeftAndFillUpperFromUint16x8", argLength: 2, commutative: false, aux: "Int8"},
- {name: "ShiftAllLeftAndFillUpperFromMaskedUint16x8", argLength: 3, commutative: false, aux: "Int8"},
- {name: "ShiftAllRightAndFillUpperFromUint16x8", argLength: 2, commutative: false, aux: "Int8"},
- {name: "ShiftAllRightAndFillUpperFromMaskedUint16x8", argLength: 3, commutative: false, aux: "Int8"},
- {name: "RotateAllLeftUint32x16", argLength: 1, commutative: false, aux: "Int8"},
- {name: "RotateAllLeftMaskedUint32x16", argLength: 2, commutative: false, aux: "Int8"},
- {name: "RotateAllRightUint32x16", argLength: 1, commutative: false, aux: "Int8"},
- {name: "RotateAllRightMaskedUint32x16", argLength: 2, commutative: false, aux: "Int8"},
+ {name: "ShiftAllLeftAndFillUpperFromUint16x16", argLength: 2, commutative: false, aux: "Int8"},
+ {name: "ShiftAllLeftAndFillUpperFromUint16x32", argLength: 2, commutative: false, aux: "Int8"},
+ {name: "ShiftAllLeftAndFillUpperFromUint32x4", argLength: 2, commutative: false, aux: "Int8"},
+ {name: "ShiftAllLeftAndFillUpperFromUint32x8", argLength: 2, commutative: false, aux: "Int8"},
{name: "ShiftAllLeftAndFillUpperFromUint32x16", argLength: 2, commutative: false, aux: "Int8"},
- {name: "ShiftAllLeftAndFillUpperFromMaskedUint32x16", argLength: 3, commutative: false, aux: "Int8"},
- {name: "ShiftAllRightAndFillUpperFromUint32x16", argLength: 2, commutative: false, aux: "Int8"},
+ {name: "ShiftAllLeftAndFillUpperFromUint64x2", argLength: 2, commutative: false, aux: "Int8"},
+ {name: "ShiftAllLeftAndFillUpperFromUint64x4", argLength: 2, commutative: false, aux: "Int8"},
+ {name: "ShiftAllLeftAndFillUpperFromUint64x8", argLength: 2, commutative: false, aux: "Int8"},
+ {name: "ShiftAllRightAndFillUpperFromInt16x8", argLength: 2, commutative: false, aux: "Int8"},
+ {name: "ShiftAllRightAndFillUpperFromInt16x16", argLength: 2, commutative: false, aux: "Int8"},
+ {name: "ShiftAllRightAndFillUpperFromInt16x32", argLength: 2, commutative: false, aux: "Int8"},
+ {name: "ShiftAllRightAndFillUpperFromInt32x4", argLength: 2, commutative: false, aux: "Int8"},
+ {name: "ShiftAllRightAndFillUpperFromInt32x8", argLength: 2, commutative: false, aux: "Int8"},
+ {name: "ShiftAllRightAndFillUpperFromInt32x16", argLength: 2, commutative: false, aux: "Int8"},
+ {name: "ShiftAllRightAndFillUpperFromInt64x2", argLength: 2, commutative: false, aux: "Int8"},
+ {name: "ShiftAllRightAndFillUpperFromInt64x4", argLength: 2, commutative: false, aux: "Int8"},
+ {name: "ShiftAllRightAndFillUpperFromInt64x8", argLength: 2, commutative: false, aux: "Int8"},
+ {name: "ShiftAllRightAndFillUpperFromMaskedInt16x8", argLength: 3, commutative: false, aux: "Int8"},
+ {name: "ShiftAllRightAndFillUpperFromMaskedInt16x16", argLength: 3, commutative: false, aux: "Int8"},
+ {name: "ShiftAllRightAndFillUpperFromMaskedInt16x32", argLength: 3, commutative: false, aux: "Int8"},
+ {name: "ShiftAllRightAndFillUpperFromMaskedInt32x4", argLength: 3, commutative: false, aux: "Int8"},
+ {name: "ShiftAllRightAndFillUpperFromMaskedInt32x8", argLength: 3, commutative: false, aux: "Int8"},
+ {name: "ShiftAllRightAndFillUpperFromMaskedInt32x16", argLength: 3, commutative: false, aux: "Int8"},
+ {name: "ShiftAllRightAndFillUpperFromMaskedInt64x2", argLength: 3, commutative: false, aux: "Int8"},
+ {name: "ShiftAllRightAndFillUpperFromMaskedInt64x4", argLength: 3, commutative: false, aux: "Int8"},
+ {name: "ShiftAllRightAndFillUpperFromMaskedInt64x8", argLength: 3, commutative: false, aux: "Int8"},
+ {name: "ShiftAllRightAndFillUpperFromMaskedUint16x8", argLength: 3, commutative: false, aux: "Int8"},
+ {name: "ShiftAllRightAndFillUpperFromMaskedUint16x16", argLength: 3, commutative: false, aux: "Int8"},
+ {name: "ShiftAllRightAndFillUpperFromMaskedUint16x32", argLength: 3, commutative: false, aux: "Int8"},
+ {name: "ShiftAllRightAndFillUpperFromMaskedUint32x4", argLength: 3, commutative: false, aux: "Int8"},
+ {name: "ShiftAllRightAndFillUpperFromMaskedUint32x8", argLength: 3, commutative: false, aux: "Int8"},
{name: "ShiftAllRightAndFillUpperFromMaskedUint32x16", argLength: 3, commutative: false, aux: "Int8"},
- {name: "GetElemUint32x4", argLength: 1, commutative: false, aux: "Int8"},
- {name: "RotateAllLeftUint32x4", argLength: 1, commutative: false, aux: "Int8"},
- {name: "RotateAllLeftMaskedUint32x4", argLength: 2, commutative: false, aux: "Int8"},
- {name: "RotateAllRightUint32x4", argLength: 1, commutative: false, aux: "Int8"},
- {name: "RotateAllRightMaskedUint32x4", argLength: 2, commutative: false, aux: "Int8"},
- {name: "SetElemUint32x4", argLength: 2, commutative: false, aux: "Int8"},
- {name: "ShiftAllLeftAndFillUpperFromUint32x4", argLength: 2, commutative: false, aux: "Int8"},
- {name: "ShiftAllLeftAndFillUpperFromMaskedUint32x4", argLength: 3, commutative: false, aux: "Int8"},
+ {name: "ShiftAllRightAndFillUpperFromMaskedUint64x2", argLength: 3, commutative: false, aux: "Int8"},
+ {name: "ShiftAllRightAndFillUpperFromMaskedUint64x4", argLength: 3, commutative: false, aux: "Int8"},
+ {name: "ShiftAllRightAndFillUpperFromMaskedUint64x8", argLength: 3, commutative: false, aux: "Int8"},
+ {name: "ShiftAllRightAndFillUpperFromUint16x8", argLength: 2, commutative: false, aux: "Int8"},
+ {name: "ShiftAllRightAndFillUpperFromUint16x16", argLength: 2, commutative: false, aux: "Int8"},
+ {name: "ShiftAllRightAndFillUpperFromUint16x32", argLength: 2, commutative: false, aux: "Int8"},
{name: "ShiftAllRightAndFillUpperFromUint32x4", argLength: 2, commutative: false, aux: "Int8"},
- {name: "ShiftAllRightAndFillUpperFromMaskedUint32x4", argLength: 3, commutative: false, aux: "Int8"},
- {name: "Get128Uint32x8", argLength: 1, commutative: false, aux: "Int8"},
- {name: "RotateAllLeftUint32x8", argLength: 1, commutative: false, aux: "Int8"},
- {name: "RotateAllLeftMaskedUint32x8", argLength: 2, commutative: false, aux: "Int8"},
- {name: "RotateAllRightUint32x8", argLength: 1, commutative: false, aux: "Int8"},
- {name: "RotateAllRightMaskedUint32x8", argLength: 2, commutative: false, aux: "Int8"},
- {name: "Set128Uint32x8", argLength: 2, commutative: false, aux: "Int8"},
- {name: "ShiftAllLeftAndFillUpperFromUint32x8", argLength: 2, commutative: false, aux: "Int8"},
- {name: "ShiftAllLeftAndFillUpperFromMaskedUint32x8", argLength: 3, commutative: false, aux: "Int8"},
{name: "ShiftAllRightAndFillUpperFromUint32x8", argLength: 2, commutative: false, aux: "Int8"},
- {name: "ShiftAllRightAndFillUpperFromMaskedUint32x8", argLength: 3, commutative: false, aux: "Int8"},
- {name: "GetElemUint64x2", argLength: 1, commutative: false, aux: "Int8"},
- {name: "RotateAllLeftUint64x2", argLength: 1, commutative: false, aux: "Int8"},
- {name: "RotateAllLeftMaskedUint64x2", argLength: 2, commutative: false, aux: "Int8"},
- {name: "RotateAllRightUint64x2", argLength: 1, commutative: false, aux: "Int8"},
- {name: "RotateAllRightMaskedUint64x2", argLength: 2, commutative: false, aux: "Int8"},
- {name: "SetElemUint64x2", argLength: 2, commutative: false, aux: "Int8"},
- {name: "ShiftAllLeftAndFillUpperFromUint64x2", argLength: 2, commutative: false, aux: "Int8"},
- {name: "ShiftAllLeftAndFillUpperFromMaskedUint64x2", argLength: 3, commutative: false, aux: "Int8"},
+ {name: "ShiftAllRightAndFillUpperFromUint32x16", argLength: 2, commutative: false, aux: "Int8"},
{name: "ShiftAllRightAndFillUpperFromUint64x2", argLength: 2, commutative: false, aux: "Int8"},
- {name: "ShiftAllRightAndFillUpperFromMaskedUint64x2", argLength: 3, commutative: false, aux: "Int8"},
- {name: "Get128Uint64x4", argLength: 1, commutative: false, aux: "Int8"},
- {name: "RotateAllLeftUint64x4", argLength: 1, commutative: false, aux: "Int8"},
- {name: "RotateAllLeftMaskedUint64x4", argLength: 2, commutative: false, aux: "Int8"},
- {name: "RotateAllRightUint64x4", argLength: 1, commutative: false, aux: "Int8"},
- {name: "RotateAllRightMaskedUint64x4", argLength: 2, commutative: false, aux: "Int8"},
- {name: "Set128Uint64x4", argLength: 2, commutative: false, aux: "Int8"},
- {name: "ShiftAllLeftAndFillUpperFromUint64x4", argLength: 2, commutative: false, aux: "Int8"},
- {name: "ShiftAllLeftAndFillUpperFromMaskedUint64x4", argLength: 3, commutative: false, aux: "Int8"},
{name: "ShiftAllRightAndFillUpperFromUint64x4", argLength: 2, commutative: false, aux: "Int8"},
- {name: "ShiftAllRightAndFillUpperFromMaskedUint64x4", argLength: 3, commutative: false, aux: "Int8"},
- {name: "RotateAllLeftUint64x8", argLength: 1, commutative: false, aux: "Int8"},
- {name: "RotateAllLeftMaskedUint64x8", argLength: 2, commutative: false, aux: "Int8"},
- {name: "RotateAllRightUint64x8", argLength: 1, commutative: false, aux: "Int8"},
- {name: "RotateAllRightMaskedUint64x8", argLength: 2, commutative: false, aux: "Int8"},
- {name: "ShiftAllLeftAndFillUpperFromUint64x8", argLength: 2, commutative: false, aux: "Int8"},
- {name: "ShiftAllLeftAndFillUpperFromMaskedUint64x8", argLength: 3, commutative: false, aux: "Int8"},
{name: "ShiftAllRightAndFillUpperFromUint64x8", argLength: 2, commutative: false, aux: "Int8"},
- {name: "ShiftAllRightAndFillUpperFromMaskedUint64x8", argLength: 3, commutative: false, aux: "Int8"},
- {name: "GaloisFieldAffineTransformUint8x16", argLength: 2, commutative: false, aux: "Int8"},
- {name: "GaloisFieldAffineTransformInverseUint8x16", argLength: 2, commutative: false, aux: "Int8"},
- {name: "GaloisFieldAffineTransformInverseMaskedUint8x16", argLength: 3, commutative: false, aux: "Int8"},
- {name: "GaloisFieldAffineTransformMaskedUint8x16", argLength: 3, commutative: false, aux: "Int8"},
- {name: "GetElemUint8x16", argLength: 1, commutative: false, aux: "Int8"},
- {name: "SetElemUint8x16", argLength: 2, commutative: false, aux: "Int8"},
- {name: "GaloisFieldAffineTransformUint8x32", argLength: 2, commutative: false, aux: "Int8"},
- {name: "GaloisFieldAffineTransformInverseUint8x32", argLength: 2, commutative: false, aux: "Int8"},
- {name: "GaloisFieldAffineTransformInverseMaskedUint8x32", argLength: 3, commutative: false, aux: "Int8"},
- {name: "GaloisFieldAffineTransformMaskedUint8x32", argLength: 3, commutative: false, aux: "Int8"},
- {name: "Get128Uint8x32", argLength: 1, commutative: false, aux: "Int8"},
- {name: "Set128Uint8x32", argLength: 2, commutative: false, aux: "Int8"},
- {name: "GaloisFieldAffineTransformUint8x64", argLength: 2, commutative: false, aux: "Int8"},
- {name: "GaloisFieldAffineTransformInverseUint8x64", argLength: 2, commutative: false, aux: "Int8"},
- {name: "GaloisFieldAffineTransformInverseMaskedUint8x64", argLength: 3, commutative: false, aux: "Int8"},
- {name: "GaloisFieldAffineTransformMaskedUint8x64", argLength: 3, commutative: false, aux: "Int8"},
+ {name: "TruncWithPrecisionFloat32x4", argLength: 1, commutative: false, aux: "Int8"},
+ {name: "TruncWithPrecisionFloat32x8", argLength: 1, commutative: false, aux: "Int8"},
+ {name: "TruncWithPrecisionFloat32x16", argLength: 1, commutative: false, aux: "Int8"},
+ {name: "TruncWithPrecisionFloat64x2", argLength: 1, commutative: false, aux: "Int8"},
+ {name: "TruncWithPrecisionFloat64x4", argLength: 1, commutative: false, aux: "Int8"},
+ {name: "TruncWithPrecisionFloat64x8", argLength: 1, commutative: false, aux: "Int8"},
+ {name: "TruncWithPrecisionMaskedFloat32x4", argLength: 2, commutative: false, aux: "Int8"},
+ {name: "TruncWithPrecisionMaskedFloat32x8", argLength: 2, commutative: false, aux: "Int8"},
+ {name: "TruncWithPrecisionMaskedFloat32x16", argLength: 2, commutative: false, aux: "Int8"},
+ {name: "TruncWithPrecisionMaskedFloat64x2", argLength: 2, commutative: false, aux: "Int8"},
+ {name: "TruncWithPrecisionMaskedFloat64x4", argLength: 2, commutative: false, aux: "Int8"},
+ {name: "TruncWithPrecisionMaskedFloat64x8", argLength: 2, commutative: false, aux: "Int8"},
}
}
OpAMD64VZEROALL
OpAMD64KMOVQload
OpAMD64KMOVQstore
- OpAMD64VADDPS512
- OpAMD64VADDPSMasked512
- OpAMD64VRCP14PS512
- OpAMD64VRCP14PSMasked512
- OpAMD64VRSQRT14PS512
- OpAMD64VRSQRT14PSMasked512
- OpAMD64VCOMPRESSPSMasked512
- OpAMD64VDIVPS512
- OpAMD64VDIVPSMasked512
- OpAMD64VFMADD213PS512
- OpAMD64VFMADD213PSMasked512
- OpAMD64VFMADDSUB213PS512
- OpAMD64VFMADDSUB213PSMasked512
- OpAMD64VFMSUBADD213PS512
- OpAMD64VFMSUBADD213PSMasked512
- OpAMD64VMAXPS512
- OpAMD64VMAXPSMasked512
- OpAMD64VMINPS512
- OpAMD64VMINPSMasked512
- OpAMD64VMULPS512
- OpAMD64VSCALEFPS512
- OpAMD64VSCALEFPSMasked512
- OpAMD64VMULPSMasked512
- OpAMD64VSQRTPS512
- OpAMD64VSQRTPSMasked512
- OpAMD64VSUBPS512
- OpAMD64VSUBPSMasked512
+ OpAMD64VADDPD128
+ OpAMD64VADDPD256
+ OpAMD64VADDPD512
+ OpAMD64VADDPDMasked128
+ OpAMD64VADDPDMasked256
+ OpAMD64VADDPDMasked512
OpAMD64VADDPS128
- OpAMD64VADDPSMasked128
- OpAMD64VADDSUBPS128
- OpAMD64VRCPPS128
- OpAMD64VRCP14PSMasked128
- OpAMD64VRSQRTPS128
- OpAMD64VRSQRT14PSMasked128
- OpAMD64VCOMPRESSPSMasked128
- OpAMD64VDIVPS128
- OpAMD64VDIVPSMasked128
- OpAMD64VFMADD213PS128
- OpAMD64VFMADD213PSMasked128
- OpAMD64VFMADDSUB213PS128
- OpAMD64VFMADDSUB213PSMasked128
- OpAMD64VFMSUBADD213PS128
- OpAMD64VFMSUBADD213PSMasked128
- OpAMD64VMAXPS128
- OpAMD64VMAXPSMasked128
- OpAMD64VMINPS128
- OpAMD64VMINPSMasked128
- OpAMD64VMULPS128
- OpAMD64VSCALEFPS128
- OpAMD64VSCALEFPSMasked128
- OpAMD64VMULPSMasked128
- OpAMD64VHADDPS128
- OpAMD64VHSUBPS128
- OpAMD64VSQRTPS128
- OpAMD64VSQRTPSMasked128
- OpAMD64VSUBPS128
- OpAMD64VSUBPSMasked128
OpAMD64VADDPS256
+ OpAMD64VADDPS512
+ OpAMD64VADDPSMasked128
OpAMD64VADDPSMasked256
+ OpAMD64VADDPSMasked512
+ OpAMD64VADDSUBPD128
+ OpAMD64VADDSUBPD256
+ OpAMD64VADDSUBPS128
OpAMD64VADDSUBPS256
- OpAMD64VRCPPS256
- OpAMD64VRCP14PSMasked256
- OpAMD64VRSQRTPS256
- OpAMD64VRSQRT14PSMasked256
+ OpAMD64VCOMPRESSPDMasked128
+ OpAMD64VCOMPRESSPDMasked256
+ OpAMD64VCOMPRESSPDMasked512
+ OpAMD64VCOMPRESSPSMasked128
OpAMD64VCOMPRESSPSMasked256
+ OpAMD64VCOMPRESSPSMasked512
+ OpAMD64VDIVPD128
+ OpAMD64VDIVPD256
+ OpAMD64VDIVPD512
+ OpAMD64VDIVPDMasked128
+ OpAMD64VDIVPDMasked256
+ OpAMD64VDIVPDMasked512
+ OpAMD64VDIVPS128
OpAMD64VDIVPS256
+ OpAMD64VDIVPS512
+ OpAMD64VDIVPSMasked128
OpAMD64VDIVPSMasked256
+ OpAMD64VDIVPSMasked512
+ OpAMD64VFMADD213PD128
+ OpAMD64VFMADD213PD256
+ OpAMD64VFMADD213PD512
+ OpAMD64VFMADD213PDMasked128
+ OpAMD64VFMADD213PDMasked256
+ OpAMD64VFMADD213PDMasked512
+ OpAMD64VFMADD213PS128
OpAMD64VFMADD213PS256
+ OpAMD64VFMADD213PS512
+ OpAMD64VFMADD213PSMasked128
OpAMD64VFMADD213PSMasked256
+ OpAMD64VFMADD213PSMasked512
+ OpAMD64VFMADDSUB213PD128
+ OpAMD64VFMADDSUB213PD256
+ OpAMD64VFMADDSUB213PD512
+ OpAMD64VFMADDSUB213PDMasked128
+ OpAMD64VFMADDSUB213PDMasked256
+ OpAMD64VFMADDSUB213PDMasked512
+ OpAMD64VFMADDSUB213PS128
OpAMD64VFMADDSUB213PS256
+ OpAMD64VFMADDSUB213PS512
+ OpAMD64VFMADDSUB213PSMasked128
OpAMD64VFMADDSUB213PSMasked256
+ OpAMD64VFMADDSUB213PSMasked512
+ OpAMD64VFMSUBADD213PD128
+ OpAMD64VFMSUBADD213PD256
+ OpAMD64VFMSUBADD213PD512
+ OpAMD64VFMSUBADD213PDMasked128
+ OpAMD64VFMSUBADD213PDMasked256
+ OpAMD64VFMSUBADD213PDMasked512
+ OpAMD64VFMSUBADD213PS128
OpAMD64VFMSUBADD213PS256
+ OpAMD64VFMSUBADD213PS512
+ OpAMD64VFMSUBADD213PSMasked128
OpAMD64VFMSUBADD213PSMasked256
- OpAMD64VMAXPS256
- OpAMD64VMAXPSMasked256
- OpAMD64VMINPS256
- OpAMD64VMINPSMasked256
- OpAMD64VMULPS256
- OpAMD64VSCALEFPS256
- OpAMD64VSCALEFPSMasked256
- OpAMD64VMULPSMasked256
+ OpAMD64VFMSUBADD213PSMasked512
+ OpAMD64VGF2P8MULB128
+ OpAMD64VGF2P8MULB256
+ OpAMD64VGF2P8MULB512
+ OpAMD64VGF2P8MULBMasked128
+ OpAMD64VGF2P8MULBMasked256
+ OpAMD64VGF2P8MULBMasked512
+ OpAMD64VHADDPD128
+ OpAMD64VHADDPD256
+ OpAMD64VHADDPS128
OpAMD64VHADDPS256
+ OpAMD64VHSUBPD128
+ OpAMD64VHSUBPD256
+ OpAMD64VHSUBPS128
OpAMD64VHSUBPS256
- OpAMD64VSQRTPS256
- OpAMD64VSQRTPSMasked256
- OpAMD64VSUBPS256
- OpAMD64VSUBPSMasked256
- OpAMD64VADDPD128
- OpAMD64VADDPDMasked128
- OpAMD64VADDSUBPD128
- OpAMD64VRCP14PD128
- OpAMD64VRCP14PDMasked128
- OpAMD64VRSQRT14PD128
- OpAMD64VRSQRT14PDMasked128
- OpAMD64VCOMPRESSPDMasked128
- OpAMD64VDIVPD128
- OpAMD64VDIVPDMasked128
- OpAMD64VFMADD213PD128
- OpAMD64VFMADD213PDMasked128
- OpAMD64VFMADDSUB213PD128
- OpAMD64VFMADDSUB213PDMasked128
- OpAMD64VFMSUBADD213PD128
- OpAMD64VFMSUBADD213PDMasked128
OpAMD64VMAXPD128
- OpAMD64VMAXPDMasked128
- OpAMD64VMINPD128
- OpAMD64VMINPDMasked128
- OpAMD64VMULPD128
- OpAMD64VSCALEFPD128
- OpAMD64VSCALEFPDMasked128
- OpAMD64VMULPDMasked128
- OpAMD64VHADDPD128
- OpAMD64VHSUBPD128
- OpAMD64VSQRTPD128
- OpAMD64VSQRTPDMasked128
- OpAMD64VSUBPD128
- OpAMD64VSUBPDMasked128
- OpAMD64VADDPD256
- OpAMD64VADDPDMasked256
- OpAMD64VADDSUBPD256
- OpAMD64VRCP14PD256
- OpAMD64VRCP14PDMasked256
- OpAMD64VRSQRT14PD256
- OpAMD64VRSQRT14PDMasked256
- OpAMD64VCOMPRESSPDMasked256
- OpAMD64VDIVPD256
- OpAMD64VDIVPDMasked256
- OpAMD64VFMADD213PD256
- OpAMD64VFMADD213PDMasked256
- OpAMD64VFMADDSUB213PD256
- OpAMD64VFMADDSUB213PDMasked256
- OpAMD64VFMSUBADD213PD256
- OpAMD64VFMSUBADD213PDMasked256
OpAMD64VMAXPD256
- OpAMD64VMAXPDMasked256
- OpAMD64VMINPD256
- OpAMD64VMINPDMasked256
- OpAMD64VMULPD256
- OpAMD64VSCALEFPD256
- OpAMD64VSCALEFPDMasked256
- OpAMD64VMULPDMasked256
- OpAMD64VHADDPD256
- OpAMD64VHSUBPD256
- OpAMD64VSQRTPD256
- OpAMD64VSQRTPDMasked256
- OpAMD64VSUBPD256
- OpAMD64VSUBPDMasked256
- OpAMD64VADDPD512
- OpAMD64VADDPDMasked512
- OpAMD64VRCP14PD512
- OpAMD64VRCP14PDMasked512
- OpAMD64VRSQRT14PD512
- OpAMD64VRSQRT14PDMasked512
- OpAMD64VCOMPRESSPDMasked512
- OpAMD64VDIVPD512
- OpAMD64VDIVPDMasked512
- OpAMD64VFMADD213PD512
- OpAMD64VFMADD213PDMasked512
- OpAMD64VFMADDSUB213PD512
- OpAMD64VFMADDSUB213PDMasked512
- OpAMD64VFMSUBADD213PD512
- OpAMD64VFMSUBADD213PDMasked512
OpAMD64VMAXPD512
+ OpAMD64VMAXPDMasked128
+ OpAMD64VMAXPDMasked256
OpAMD64VMAXPDMasked512
+ OpAMD64VMAXPS128
+ OpAMD64VMAXPS256
+ OpAMD64VMAXPS512
+ OpAMD64VMAXPSMasked128
+ OpAMD64VMAXPSMasked256
+ OpAMD64VMAXPSMasked512
+ OpAMD64VMINPD128
+ OpAMD64VMINPD256
OpAMD64VMINPD512
+ OpAMD64VMINPDMasked128
+ OpAMD64VMINPDMasked256
OpAMD64VMINPDMasked512
+ OpAMD64VMINPS128
+ OpAMD64VMINPS256
+ OpAMD64VMINPS512
+ OpAMD64VMINPSMasked128
+ OpAMD64VMINPSMasked256
+ OpAMD64VMINPSMasked512
+ OpAMD64VMULPD128
+ OpAMD64VMULPD256
OpAMD64VMULPD512
- OpAMD64VSCALEFPD512
- OpAMD64VSCALEFPDMasked512
+ OpAMD64VMULPDMasked128
+ OpAMD64VMULPDMasked256
OpAMD64VMULPDMasked512
- OpAMD64VSQRTPD512
- OpAMD64VSQRTPDMasked512
- OpAMD64VSUBPD512
- OpAMD64VSUBPDMasked512
+ OpAMD64VMULPS128
+ OpAMD64VMULPS256
+ OpAMD64VMULPS512
+ OpAMD64VMULPSMasked128
+ OpAMD64VMULPSMasked256
+ OpAMD64VMULPSMasked512
+ OpAMD64VPABSB128
+ OpAMD64VPABSB256
+ OpAMD64VPABSB512
+ OpAMD64VPABSBMasked128
+ OpAMD64VPABSBMasked256
+ OpAMD64VPABSBMasked512
+ OpAMD64VPABSD128
+ OpAMD64VPABSD256
+ OpAMD64VPABSD512
+ OpAMD64VPABSDMasked128
+ OpAMD64VPABSDMasked256
+ OpAMD64VPABSDMasked512
+ OpAMD64VPABSQ128
+ OpAMD64VPABSQ256
+ OpAMD64VPABSQ512
+ OpAMD64VPABSQMasked128
+ OpAMD64VPABSQMasked256
+ OpAMD64VPABSQMasked512
+ OpAMD64VPABSW128
OpAMD64VPABSW256
- OpAMD64VPABSWMasked256
- OpAMD64VPADDW256
- OpAMD64VPADDWMasked256
- OpAMD64VPCOMPRESSWMasked256
- OpAMD64VPCMPEQW256
- OpAMD64VPCMPGTW256
- OpAMD64VPMAXSW256
- OpAMD64VPMAXSWMasked256
- OpAMD64VPMINSW256
- OpAMD64VPMINSWMasked256
- OpAMD64VPMULHW256
- OpAMD64VPMULHWMasked256
- OpAMD64VPMULLW256
- OpAMD64VPMULLWMasked256
- OpAMD64VPMADDWD256
- OpAMD64VPMADDWDMasked256
- OpAMD64VPHADDW256
- OpAMD64VPHSUBW256
- OpAMD64VPOPCNTW256
- OpAMD64VPOPCNTWMasked256
- OpAMD64VPADDSW256
- OpAMD64VPADDSWMasked256
- OpAMD64VPHADDSW256
- OpAMD64VPHSUBSW256
- OpAMD64VPSUBSW256
- OpAMD64VPSUBSWMasked256
- OpAMD64VPSLLW256
- OpAMD64VPSLLWMasked256
- OpAMD64VPSRAW256
- OpAMD64VPSRAWMasked256
- OpAMD64VPSLLVW256
- OpAMD64VPSHLDVW256
- OpAMD64VPSHLDVWMasked256
- OpAMD64VPSLLVWMasked256
- OpAMD64VPSRAVW256
- OpAMD64VPSHRDVW256
- OpAMD64VPSHRDVWMasked256
- OpAMD64VPSRAVWMasked256
- OpAMD64VPSIGNW256
- OpAMD64VPSUBW256
- OpAMD64VPSUBWMasked256
OpAMD64VPABSW512
+ OpAMD64VPABSWMasked128
+ OpAMD64VPABSWMasked256
OpAMD64VPABSWMasked512
- OpAMD64VPADDW512
- OpAMD64VPADDWMasked512
- OpAMD64VPCOMPRESSWMasked512
- OpAMD64VPCMPEQW512
- OpAMD64VPCMPGTW512
- OpAMD64VPMAXSW512
- OpAMD64VPMAXSWMasked512
- OpAMD64VPMINSW512
- OpAMD64VPMINSWMasked512
- OpAMD64VPMULHW512
- OpAMD64VPMULHWMasked512
- OpAMD64VPMULLW512
- OpAMD64VPMULLWMasked512
- OpAMD64VPMADDWD512
- OpAMD64VPMADDWDMasked512
- OpAMD64VPOPCNTW512
- OpAMD64VPOPCNTWMasked512
+ OpAMD64VPADDB128
+ OpAMD64VPADDB256
+ OpAMD64VPADDB512
+ OpAMD64VPADDBMasked128
+ OpAMD64VPADDBMasked256
+ OpAMD64VPADDBMasked512
+ OpAMD64VPADDD128
+ OpAMD64VPADDD256
+ OpAMD64VPADDD512
+ OpAMD64VPADDDMasked128
+ OpAMD64VPADDDMasked256
+ OpAMD64VPADDDMasked512
+ OpAMD64VPADDQ128
+ OpAMD64VPADDQ256
+ OpAMD64VPADDQ512
+ OpAMD64VPADDQMasked128
+ OpAMD64VPADDQMasked256
+ OpAMD64VPADDQMasked512
+ OpAMD64VPADDSB128
+ OpAMD64VPADDSB256
+ OpAMD64VPADDSB512
+ OpAMD64VPADDSBMasked128
+ OpAMD64VPADDSBMasked256
+ OpAMD64VPADDSBMasked512
+ OpAMD64VPADDSW128
+ OpAMD64VPADDSW256
OpAMD64VPADDSW512
+ OpAMD64VPADDSWMasked128
+ OpAMD64VPADDSWMasked256
OpAMD64VPADDSWMasked512
- OpAMD64VPSUBSW512
- OpAMD64VPSUBSWMasked512
- OpAMD64VPSLLW512
- OpAMD64VPSLLWMasked512
- OpAMD64VPSRAW512
- OpAMD64VPSRAWMasked512
- OpAMD64VPSLLVW512
- OpAMD64VPSHLDVW512
- OpAMD64VPSHLDVWMasked512
- OpAMD64VPSLLVWMasked512
- OpAMD64VPSRAVW512
- OpAMD64VPSHRDVW512
- OpAMD64VPSHRDVWMasked512
- OpAMD64VPSRAVWMasked512
- OpAMD64VPSUBW512
- OpAMD64VPSUBWMasked512
- OpAMD64VPABSW128
- OpAMD64VPABSWMasked128
OpAMD64VPADDW128
+ OpAMD64VPADDW256
+ OpAMD64VPADDW512
OpAMD64VPADDWMasked128
- OpAMD64VPCOMPRESSWMasked128
- OpAMD64VPCMPEQW128
- OpAMD64VPCMPGTW128
- OpAMD64VPMAXSW128
- OpAMD64VPMAXSWMasked128
- OpAMD64VPMINSW128
- OpAMD64VPMINSWMasked128
- OpAMD64VPMULHW128
- OpAMD64VPMULHWMasked128
- OpAMD64VPMULLW128
- OpAMD64VPMULLWMasked128
- OpAMD64VPMADDWD128
- OpAMD64VPMADDWDMasked128
- OpAMD64VPHADDW128
- OpAMD64VPHSUBW128
- OpAMD64VPOPCNTW128
- OpAMD64VPOPCNTWMasked128
- OpAMD64VPADDSW128
- OpAMD64VPADDSWMasked128
- OpAMD64VPHADDSW128
- OpAMD64VPHSUBSW128
- OpAMD64VPSUBSW128
- OpAMD64VPSUBSWMasked128
- OpAMD64VPSLLW128
- OpAMD64VPSLLWMasked128
- OpAMD64VPSRAW128
- OpAMD64VPSRAWMasked128
- OpAMD64VPSLLVW128
- OpAMD64VPSHLDVW128
- OpAMD64VPSHLDVWMasked128
- OpAMD64VPSLLVWMasked128
- OpAMD64VPSRAVW128
- OpAMD64VPSHRDVW128
- OpAMD64VPSHRDVWMasked128
- OpAMD64VPSRAVWMasked128
- OpAMD64VPSIGNW128
- OpAMD64VPSUBW128
- OpAMD64VPSUBWMasked128
- OpAMD64VPABSD512
- OpAMD64VPABSDMasked512
- OpAMD64VPADDD512
- OpAMD64VPADDDMasked512
+ OpAMD64VPADDWMasked256
+ OpAMD64VPADDWMasked512
+ OpAMD64VPAND128
+ OpAMD64VPAND256
OpAMD64VPANDD512
+ OpAMD64VPANDDMasked128
+ OpAMD64VPANDDMasked256
OpAMD64VPANDDMasked512
+ OpAMD64VPANDN128
+ OpAMD64VPANDN256
OpAMD64VPANDND512
+ OpAMD64VPANDNDMasked128
+ OpAMD64VPANDNDMasked256
OpAMD64VPANDNDMasked512
- OpAMD64VPCOMPRESSDMasked512
+ OpAMD64VPANDNQ512
+ OpAMD64VPANDNQMasked128
+ OpAMD64VPANDNQMasked256
+ OpAMD64VPANDNQMasked512
+ OpAMD64VPANDQ512
+ OpAMD64VPANDQMasked128
+ OpAMD64VPANDQMasked256
+ OpAMD64VPANDQMasked512
+ OpAMD64VPAVGB128
+ OpAMD64VPAVGB256
+ OpAMD64VPAVGB512
+ OpAMD64VPAVGBMasked128
+ OpAMD64VPAVGBMasked256
+ OpAMD64VPAVGBMasked512
+ OpAMD64VPAVGW128
+ OpAMD64VPAVGW256
+ OpAMD64VPAVGW512
+ OpAMD64VPAVGWMasked128
+ OpAMD64VPAVGWMasked256
+ OpAMD64VPAVGWMasked512
+ OpAMD64VPCMPEQB128
+ OpAMD64VPCMPEQB256
+ OpAMD64VPCMPEQB512
+ OpAMD64VPCMPEQD128
+ OpAMD64VPCMPEQD256
OpAMD64VPCMPEQD512
+ OpAMD64VPCMPEQQ128
+ OpAMD64VPCMPEQQ256
+ OpAMD64VPCMPEQQ512
+ OpAMD64VPCMPEQW128
+ OpAMD64VPCMPEQW256
+ OpAMD64VPCMPEQW512
+ OpAMD64VPCMPGTB128
+ OpAMD64VPCMPGTB256
+ OpAMD64VPCMPGTB512
+ OpAMD64VPCMPGTD128
+ OpAMD64VPCMPGTD256
OpAMD64VPCMPGTD512
- OpAMD64VPMAXSD512
- OpAMD64VPMAXSDMasked512
- OpAMD64VPMINSD512
- OpAMD64VPMINSDMasked512
- OpAMD64VPMULLD512
- OpAMD64VPMULLDMasked512
- OpAMD64VPORD512
- OpAMD64VPORDMasked512
- OpAMD64VPDPWSSD512
- OpAMD64VPDPWSSDMasked512
- OpAMD64VPOPCNTD512
- OpAMD64VPOPCNTDMasked512
- OpAMD64VPROLVD512
- OpAMD64VPROLVDMasked512
- OpAMD64VPRORVD512
- OpAMD64VPRORVDMasked512
- OpAMD64VPDPWSSDS512
- OpAMD64VPDPWSSDSMasked512
+ OpAMD64VPCMPGTQ128
+ OpAMD64VPCMPGTQ256
+ OpAMD64VPCMPGTQ512
+ OpAMD64VPCMPGTW128
+ OpAMD64VPCMPGTW256
+ OpAMD64VPCMPGTW512
+ OpAMD64VPCOMPRESSBMasked128
+ OpAMD64VPCOMPRESSBMasked256
+ OpAMD64VPCOMPRESSBMasked512
+ OpAMD64VPCOMPRESSDMasked128
+ OpAMD64VPCOMPRESSDMasked256
+ OpAMD64VPCOMPRESSDMasked512
+ OpAMD64VPCOMPRESSQMasked128
+ OpAMD64VPCOMPRESSQMasked256
+ OpAMD64VPCOMPRESSQMasked512
+ OpAMD64VPCOMPRESSWMasked128
+ OpAMD64VPCOMPRESSWMasked256
+ OpAMD64VPCOMPRESSWMasked512
+ OpAMD64VPDPBUSD128
+ OpAMD64VPDPBUSD256
+ OpAMD64VPDPBUSD512
+ OpAMD64VPDPBUSDMasked128
+ OpAMD64VPDPBUSDMasked256
+ OpAMD64VPDPBUSDMasked512
+ OpAMD64VPDPBUSDS128
+ OpAMD64VPDPBUSDS256
OpAMD64VPDPBUSDS512
+ OpAMD64VPDPBUSDSMasked128
+ OpAMD64VPDPBUSDSMasked256
OpAMD64VPDPBUSDSMasked512
- OpAMD64VPSLLD512
- OpAMD64VPSLLDMasked512
- OpAMD64VPSRAD512
- OpAMD64VPSRADMasked512
- OpAMD64VPSLLVD512
- OpAMD64VPSHLDVD512
- OpAMD64VPSHLDVDMasked512
- OpAMD64VPSLLVDMasked512
- OpAMD64VPSRAVD512
- OpAMD64VPSHRDVD512
- OpAMD64VPSHRDVDMasked512
- OpAMD64VPSRAVDMasked512
- OpAMD64VPSUBD512
- OpAMD64VPSUBDMasked512
- OpAMD64VPDPBUSD512
- OpAMD64VPDPBUSDMasked512
- OpAMD64VPXORD512
- OpAMD64VPXORDMasked512
- OpAMD64VPABSD128
- OpAMD64VPABSDMasked128
- OpAMD64VPADDD128
- OpAMD64VPADDDMasked128
- OpAMD64VPANDDMasked128
- OpAMD64VPANDNDMasked128
- OpAMD64VPCOMPRESSDMasked128
- OpAMD64VPCMPEQD128
- OpAMD64VPCMPGTD128
- OpAMD64VPMAXSD128
- OpAMD64VPMAXSDMasked128
- OpAMD64VPMINSD128
- OpAMD64VPMINSDMasked128
- OpAMD64VPMULDQ128
- OpAMD64VPMULLD128
- OpAMD64VPMULLDMasked128
- OpAMD64VPORDMasked128
OpAMD64VPDPWSSD128
+ OpAMD64VPDPWSSD256
+ OpAMD64VPDPWSSD512
OpAMD64VPDPWSSDMasked128
- OpAMD64VPHADDD128
- OpAMD64VPHSUBD128
- OpAMD64VPOPCNTD128
- OpAMD64VPOPCNTDMasked128
- OpAMD64VPROLVD128
- OpAMD64VPROLVDMasked128
- OpAMD64VPRORVD128
- OpAMD64VPRORVDMasked128
+ OpAMD64VPDPWSSDMasked256
+ OpAMD64VPDPWSSDMasked512
OpAMD64VPDPWSSDS128
+ OpAMD64VPDPWSSDS256
+ OpAMD64VPDPWSSDS512
OpAMD64VPDPWSSDSMasked128
- OpAMD64VPDPBUSDS128
- OpAMD64VPDPBUSDSMasked128
- OpAMD64VPSLLD128
- OpAMD64VPSLLDMasked128
- OpAMD64VPSRAD128
- OpAMD64VPSRADMasked128
- OpAMD64VPSLLVD128
- OpAMD64VPSHLDVD128
- OpAMD64VPSHLDVDMasked128
- OpAMD64VPSLLVDMasked128
- OpAMD64VPSRAVD128
- OpAMD64VPSHRDVD128
- OpAMD64VPSHRDVDMasked128
- OpAMD64VPSRAVDMasked128
- OpAMD64VPSIGND128
- OpAMD64VPSUBD128
- OpAMD64VPSUBDMasked128
- OpAMD64VPDPBUSD128
- OpAMD64VPDPBUSDMasked128
- OpAMD64VPXORDMasked128
- OpAMD64VPABSD256
- OpAMD64VPABSDMasked256
- OpAMD64VPADDD256
- OpAMD64VPADDDMasked256
- OpAMD64VPANDDMasked256
- OpAMD64VPANDNDMasked256
- OpAMD64VPCOMPRESSDMasked256
- OpAMD64VPCMPEQD256
- OpAMD64VPCMPGTD256
+ OpAMD64VPDPWSSDSMasked256
+ OpAMD64VPDPWSSDSMasked512
+ OpAMD64VPERMB128
+ OpAMD64VPERMB256
+ OpAMD64VPERMB512
+ OpAMD64VPERMBMasked128
+ OpAMD64VPERMBMasked256
+ OpAMD64VPERMBMasked512
+ OpAMD64VPERMD256
+ OpAMD64VPERMD512
+ OpAMD64VPERMDMasked256
+ OpAMD64VPERMDMasked512
+ OpAMD64VPERMI2B128
+ OpAMD64VPERMI2B256
+ OpAMD64VPERMI2B512
+ OpAMD64VPERMI2BMasked128
+ OpAMD64VPERMI2BMasked256
+ OpAMD64VPERMI2BMasked512
+ OpAMD64VPERMI2D128
+ OpAMD64VPERMI2D256
+ OpAMD64VPERMI2D512
+ OpAMD64VPERMI2DMasked128
+ OpAMD64VPERMI2DMasked256
+ OpAMD64VPERMI2DMasked512
+ OpAMD64VPERMI2PD128
+ OpAMD64VPERMI2PD256
+ OpAMD64VPERMI2PD512
+ OpAMD64VPERMI2PDMasked128
+ OpAMD64VPERMI2PDMasked256
+ OpAMD64VPERMI2PDMasked512
+ OpAMD64VPERMI2PS128
+ OpAMD64VPERMI2PS256
+ OpAMD64VPERMI2PS512
+ OpAMD64VPERMI2PSMasked128
+ OpAMD64VPERMI2PSMasked256
+ OpAMD64VPERMI2PSMasked512
+ OpAMD64VPERMI2Q128
+ OpAMD64VPERMI2Q256
+ OpAMD64VPERMI2Q512
+ OpAMD64VPERMI2QMasked128
+ OpAMD64VPERMI2QMasked256
+ OpAMD64VPERMI2QMasked512
+ OpAMD64VPERMI2W128
+ OpAMD64VPERMI2W256
+ OpAMD64VPERMI2W512
+ OpAMD64VPERMI2WMasked128
+ OpAMD64VPERMI2WMasked256
+ OpAMD64VPERMI2WMasked512
+ OpAMD64VPERMPD256
+ OpAMD64VPERMPD512
+ OpAMD64VPERMPDMasked256
+ OpAMD64VPERMPDMasked512
+ OpAMD64VPERMPS256
+ OpAMD64VPERMPS512
+ OpAMD64VPERMPSMasked256
+ OpAMD64VPERMPSMasked512
+ OpAMD64VPERMQ256
+ OpAMD64VPERMQ512
+ OpAMD64VPERMQMasked256
+ OpAMD64VPERMQMasked512
+ OpAMD64VPERMW128
+ OpAMD64VPERMW256
+ OpAMD64VPERMW512
+ OpAMD64VPERMWMasked128
+ OpAMD64VPERMWMasked256
+ OpAMD64VPERMWMasked512
+ OpAMD64VPHADDD128
+ OpAMD64VPHADDD256
+ OpAMD64VPHADDSW128
+ OpAMD64VPHADDSW256
+ OpAMD64VPHADDW128
+ OpAMD64VPHADDW256
+ OpAMD64VPHSUBD128
+ OpAMD64VPHSUBD256
+ OpAMD64VPHSUBSW128
+ OpAMD64VPHSUBSW256
+ OpAMD64VPHSUBW128
+ OpAMD64VPHSUBW256
+ OpAMD64VPMADDUBSW128
+ OpAMD64VPMADDUBSW256
+ OpAMD64VPMADDUBSW512
+ OpAMD64VPMADDUBSWMasked128
+ OpAMD64VPMADDUBSWMasked256
+ OpAMD64VPMADDUBSWMasked512
+ OpAMD64VPMADDWD128
+ OpAMD64VPMADDWD256
+ OpAMD64VPMADDWD512
+ OpAMD64VPMADDWDMasked128
+ OpAMD64VPMADDWDMasked256
+ OpAMD64VPMADDWDMasked512
+ OpAMD64VPMAXSB128
+ OpAMD64VPMAXSB256
+ OpAMD64VPMAXSB512
+ OpAMD64VPMAXSBMasked128
+ OpAMD64VPMAXSBMasked256
+ OpAMD64VPMAXSBMasked512
+ OpAMD64VPMAXSD128
OpAMD64VPMAXSD256
+ OpAMD64VPMAXSD512
+ OpAMD64VPMAXSDMasked128
OpAMD64VPMAXSDMasked256
+ OpAMD64VPMAXSDMasked512
+ OpAMD64VPMAXSQ128
+ OpAMD64VPMAXSQ256
+ OpAMD64VPMAXSQ512
+ OpAMD64VPMAXSQMasked128
+ OpAMD64VPMAXSQMasked256
+ OpAMD64VPMAXSQMasked512
+ OpAMD64VPMAXSW128
+ OpAMD64VPMAXSW256
+ OpAMD64VPMAXSW512
+ OpAMD64VPMAXSWMasked128
+ OpAMD64VPMAXSWMasked256
+ OpAMD64VPMAXSWMasked512
+ OpAMD64VPMAXUB128
+ OpAMD64VPMAXUB256
+ OpAMD64VPMAXUB512
+ OpAMD64VPMAXUBMasked128
+ OpAMD64VPMAXUBMasked256
+ OpAMD64VPMAXUBMasked512
+ OpAMD64VPMAXUD128
+ OpAMD64VPMAXUD256
+ OpAMD64VPMAXUD512
+ OpAMD64VPMAXUDMasked128
+ OpAMD64VPMAXUDMasked256
+ OpAMD64VPMAXUDMasked512
+ OpAMD64VPMAXUQ128
+ OpAMD64VPMAXUQ256
+ OpAMD64VPMAXUQ512
+ OpAMD64VPMAXUQMasked128
+ OpAMD64VPMAXUQMasked256
+ OpAMD64VPMAXUQMasked512
+ OpAMD64VPMAXUW128
+ OpAMD64VPMAXUW256
+ OpAMD64VPMAXUW512
+ OpAMD64VPMAXUWMasked128
+ OpAMD64VPMAXUWMasked256
+ OpAMD64VPMAXUWMasked512
+ OpAMD64VPMINSB128
+ OpAMD64VPMINSB256
+ OpAMD64VPMINSB512
+ OpAMD64VPMINSBMasked128
+ OpAMD64VPMINSBMasked256
+ OpAMD64VPMINSBMasked512
+ OpAMD64VPMINSD128
OpAMD64VPMINSD256
+ OpAMD64VPMINSD512
+ OpAMD64VPMINSDMasked128
OpAMD64VPMINSDMasked256
+ OpAMD64VPMINSDMasked512
+ OpAMD64VPMINSQ128
+ OpAMD64VPMINSQ256
+ OpAMD64VPMINSQ512
+ OpAMD64VPMINSQMasked128
+ OpAMD64VPMINSQMasked256
+ OpAMD64VPMINSQMasked512
+ OpAMD64VPMINSW128
+ OpAMD64VPMINSW256
+ OpAMD64VPMINSW512
+ OpAMD64VPMINSWMasked128
+ OpAMD64VPMINSWMasked256
+ OpAMD64VPMINSWMasked512
+ OpAMD64VPMINUB128
+ OpAMD64VPMINUB256
+ OpAMD64VPMINUB512
+ OpAMD64VPMINUBMasked128
+ OpAMD64VPMINUBMasked256
+ OpAMD64VPMINUBMasked512
+ OpAMD64VPMINUD128
+ OpAMD64VPMINUD256
+ OpAMD64VPMINUD512
+ OpAMD64VPMINUDMasked128
+ OpAMD64VPMINUDMasked256
+ OpAMD64VPMINUDMasked512
+ OpAMD64VPMINUQ128
+ OpAMD64VPMINUQ256
+ OpAMD64VPMINUQ512
+ OpAMD64VPMINUQMasked128
+ OpAMD64VPMINUQMasked256
+ OpAMD64VPMINUQMasked512
+ OpAMD64VPMINUW128
+ OpAMD64VPMINUW256
+ OpAMD64VPMINUW512
+ OpAMD64VPMINUWMasked128
+ OpAMD64VPMINUWMasked256
+ OpAMD64VPMINUWMasked512
+ OpAMD64VPMULDQ128
OpAMD64VPMULDQ256
+ OpAMD64VPMULDQ512
+ OpAMD64VPMULDQMasked128
+ OpAMD64VPMULDQMasked256
+ OpAMD64VPMULDQMasked512
+ OpAMD64VPMULHUW128
+ OpAMD64VPMULHUW256
+ OpAMD64VPMULHUW512
+ OpAMD64VPMULHUWMasked128
+ OpAMD64VPMULHUWMasked256
+ OpAMD64VPMULHUWMasked512
+ OpAMD64VPMULHW128
+ OpAMD64VPMULHW256
+ OpAMD64VPMULHW512
+ OpAMD64VPMULHWMasked128
+ OpAMD64VPMULHWMasked256
+ OpAMD64VPMULHWMasked512
+ OpAMD64VPMULLD128
OpAMD64VPMULLD256
+ OpAMD64VPMULLD512
+ OpAMD64VPMULLDMasked128
OpAMD64VPMULLDMasked256
- OpAMD64VPORDMasked256
- OpAMD64VPDPWSSD256
- OpAMD64VPDPWSSDMasked256
- OpAMD64VPHADDD256
- OpAMD64VPHSUBD256
+ OpAMD64VPMULLDMasked512
+ OpAMD64VPMULLQ128
+ OpAMD64VPMULLQ256
+ OpAMD64VPMULLQ512
+ OpAMD64VPMULLQMasked128
+ OpAMD64VPMULLQMasked256
+ OpAMD64VPMULLQMasked512
+ OpAMD64VPMULLW128
+ OpAMD64VPMULLW256
+ OpAMD64VPMULLW512
+ OpAMD64VPMULLWMasked128
+ OpAMD64VPMULLWMasked256
+ OpAMD64VPMULLWMasked512
+ OpAMD64VPMULUDQ128
+ OpAMD64VPMULUDQ256
+ OpAMD64VPMULUDQ512
+ OpAMD64VPMULUDQMasked128
+ OpAMD64VPMULUDQMasked256
+ OpAMD64VPMULUDQMasked512
+ OpAMD64VPOPCNTB128
+ OpAMD64VPOPCNTB256
+ OpAMD64VPOPCNTB512
+ OpAMD64VPOPCNTBMasked128
+ OpAMD64VPOPCNTBMasked256
+ OpAMD64VPOPCNTBMasked512
+ OpAMD64VPOPCNTD128
OpAMD64VPOPCNTD256
+ OpAMD64VPOPCNTD512
+ OpAMD64VPOPCNTDMasked128
OpAMD64VPOPCNTDMasked256
+ OpAMD64VPOPCNTDMasked512
+ OpAMD64VPOPCNTQ128
+ OpAMD64VPOPCNTQ256
+ OpAMD64VPOPCNTQ512
+ OpAMD64VPOPCNTQMasked128
+ OpAMD64VPOPCNTQMasked256
+ OpAMD64VPOPCNTQMasked512
+ OpAMD64VPOPCNTW128
+ OpAMD64VPOPCNTW256
+ OpAMD64VPOPCNTW512
+ OpAMD64VPOPCNTWMasked128
+ OpAMD64VPOPCNTWMasked256
+ OpAMD64VPOPCNTWMasked512
+ OpAMD64VPOR128
+ OpAMD64VPOR256
+ OpAMD64VPORD512
+ OpAMD64VPORDMasked128
+ OpAMD64VPORDMasked256
+ OpAMD64VPORDMasked512
+ OpAMD64VPORQ512
+ OpAMD64VPORQMasked128
+ OpAMD64VPORQMasked256
+ OpAMD64VPORQMasked512
+ OpAMD64VPROLVD128
OpAMD64VPROLVD256
+ OpAMD64VPROLVD512
+ OpAMD64VPROLVDMasked128
OpAMD64VPROLVDMasked256
+ OpAMD64VPROLVDMasked512
+ OpAMD64VPROLVQ128
+ OpAMD64VPROLVQ256
+ OpAMD64VPROLVQ512
+ OpAMD64VPROLVQMasked128
+ OpAMD64VPROLVQMasked256
+ OpAMD64VPROLVQMasked512
+ OpAMD64VPRORVD128
OpAMD64VPRORVD256
+ OpAMD64VPRORVD512
+ OpAMD64VPRORVDMasked128
OpAMD64VPRORVDMasked256
- OpAMD64VPDPWSSDS256
- OpAMD64VPDPWSSDSMasked256
- OpAMD64VPDPBUSDS256
- OpAMD64VPDPBUSDSMasked256
- OpAMD64VPSLLD256
- OpAMD64VPSLLDMasked256
- OpAMD64VPSRAD256
- OpAMD64VPSRADMasked256
- OpAMD64VPSLLVD256
+ OpAMD64VPRORVDMasked512
+ OpAMD64VPRORVQ128
+ OpAMD64VPRORVQ256
+ OpAMD64VPRORVQ512
+ OpAMD64VPRORVQMasked128
+ OpAMD64VPRORVQMasked256
+ OpAMD64VPRORVQMasked512
+ OpAMD64VPSHLDVD128
OpAMD64VPSHLDVD256
+ OpAMD64VPSHLDVD512
+ OpAMD64VPSHLDVDMasked128
OpAMD64VPSHLDVDMasked256
- OpAMD64VPSLLVDMasked256
- OpAMD64VPSRAVD256
+ OpAMD64VPSHLDVDMasked512
+ OpAMD64VPSHLDVQ128
+ OpAMD64VPSHLDVQ256
+ OpAMD64VPSHLDVQ512
+ OpAMD64VPSHLDVQMasked128
+ OpAMD64VPSHLDVQMasked256
+ OpAMD64VPSHLDVQMasked512
+ OpAMD64VPSHLDVW128
+ OpAMD64VPSHLDVW256
+ OpAMD64VPSHLDVW512
+ OpAMD64VPSHLDVWMasked128
+ OpAMD64VPSHLDVWMasked256
+ OpAMD64VPSHLDVWMasked512
+ OpAMD64VPSHRDVD128
OpAMD64VPSHRDVD256
+ OpAMD64VPSHRDVD512
+ OpAMD64VPSHRDVDMasked128
OpAMD64VPSHRDVDMasked256
- OpAMD64VPSRAVDMasked256
+ OpAMD64VPSHRDVDMasked512
+ OpAMD64VPSHRDVQ128
+ OpAMD64VPSHRDVQ256
+ OpAMD64VPSHRDVQ512
+ OpAMD64VPSHRDVQMasked128
+ OpAMD64VPSHRDVQMasked256
+ OpAMD64VPSHRDVQMasked512
+ OpAMD64VPSHRDVW128
+ OpAMD64VPSHRDVW256
+ OpAMD64VPSHRDVW512
+ OpAMD64VPSHRDVWMasked128
+ OpAMD64VPSHRDVWMasked256
+ OpAMD64VPSHRDVWMasked512
+ OpAMD64VPSIGNB128
+ OpAMD64VPSIGNB256
+ OpAMD64VPSIGND128
OpAMD64VPSIGND256
- OpAMD64VPSUBD256
- OpAMD64VPSUBDMasked256
- OpAMD64VPDPBUSD256
- OpAMD64VPDPBUSDMasked256
- OpAMD64VPXORDMasked256
- OpAMD64VPABSQ128
- OpAMD64VPABSQMasked128
- OpAMD64VPADDQ128
- OpAMD64VPADDQMasked128
- OpAMD64VPANDQMasked128
- OpAMD64VPANDNQMasked128
- OpAMD64VPCOMPRESSQMasked128
- OpAMD64VPCMPEQQ128
- OpAMD64VPCMPGTQ128
- OpAMD64VPMAXSQ128
- OpAMD64VPMAXSQMasked128
- OpAMD64VPMINSQ128
- OpAMD64VPMINSQMasked128
- OpAMD64VPMULDQMasked128
- OpAMD64VPMULLQ128
- OpAMD64VPMULLQMasked128
- OpAMD64VPORQMasked128
- OpAMD64VPOPCNTQ128
- OpAMD64VPOPCNTQMasked128
- OpAMD64VPROLVQ128
- OpAMD64VPROLVQMasked128
- OpAMD64VPRORVQ128
- OpAMD64VPRORVQMasked128
+ OpAMD64VPSIGNW128
+ OpAMD64VPSIGNW256
+ OpAMD64VPSLLD128
+ OpAMD64VPSLLD256
+ OpAMD64VPSLLD512
+ OpAMD64VPSLLDMasked128
+ OpAMD64VPSLLDMasked256
+ OpAMD64VPSLLDMasked512
OpAMD64VPSLLQ128
+ OpAMD64VPSLLQ256
+ OpAMD64VPSLLQ512
OpAMD64VPSLLQMasked128
- OpAMD64VPSRAQ128
- OpAMD64VPSRAQMasked128
+ OpAMD64VPSLLQMasked256
+ OpAMD64VPSLLQMasked512
+ OpAMD64VPSLLVD128
+ OpAMD64VPSLLVD256
+ OpAMD64VPSLLVD512
+ OpAMD64VPSLLVDMasked128
+ OpAMD64VPSLLVDMasked256
+ OpAMD64VPSLLVDMasked512
OpAMD64VPSLLVQ128
- OpAMD64VPSHLDVQ128
- OpAMD64VPSHLDVQMasked128
+ OpAMD64VPSLLVQ256
+ OpAMD64VPSLLVQ512
OpAMD64VPSLLVQMasked128
- OpAMD64VPSRAVQ128
- OpAMD64VPSHRDVQ128
- OpAMD64VPSHRDVQMasked128
- OpAMD64VPSRAVQMasked128
- OpAMD64VPSUBQ128
- OpAMD64VPSUBQMasked128
- OpAMD64VPXORQMasked128
- OpAMD64VPABSQ256
- OpAMD64VPABSQMasked256
- OpAMD64VPADDQ256
- OpAMD64VPADDQMasked256
- OpAMD64VPANDQMasked256
- OpAMD64VPANDNQMasked256
- OpAMD64VPCOMPRESSQMasked256
- OpAMD64VPCMPEQQ256
- OpAMD64VPCMPGTQ256
- OpAMD64VPMAXSQ256
- OpAMD64VPMAXSQMasked256
- OpAMD64VPMINSQ256
- OpAMD64VPMINSQMasked256
- OpAMD64VPMULDQMasked256
- OpAMD64VPMULLQ256
- OpAMD64VPMULLQMasked256
- OpAMD64VPORQMasked256
- OpAMD64VPOPCNTQ256
- OpAMD64VPOPCNTQMasked256
- OpAMD64VPROLVQ256
- OpAMD64VPROLVQMasked256
- OpAMD64VPRORVQ256
- OpAMD64VPRORVQMasked256
- OpAMD64VPSLLQ256
- OpAMD64VPSLLQMasked256
+ OpAMD64VPSLLVQMasked256
+ OpAMD64VPSLLVQMasked512
+ OpAMD64VPSLLVW128
+ OpAMD64VPSLLVW256
+ OpAMD64VPSLLVW512
+ OpAMD64VPSLLVWMasked128
+ OpAMD64VPSLLVWMasked256
+ OpAMD64VPSLLVWMasked512
+ OpAMD64VPSLLW128
+ OpAMD64VPSLLW256
+ OpAMD64VPSLLW512
+ OpAMD64VPSLLWMasked128
+ OpAMD64VPSLLWMasked256
+ OpAMD64VPSLLWMasked512
+ OpAMD64VPSRAD128
+ OpAMD64VPSRAD256
+ OpAMD64VPSRAD512
+ OpAMD64VPSRADMasked128
+ OpAMD64VPSRADMasked256
+ OpAMD64VPSRADMasked512
+ OpAMD64VPSRAQ128
OpAMD64VPSRAQ256
+ OpAMD64VPSRAQ512
+ OpAMD64VPSRAQMasked128
OpAMD64VPSRAQMasked256
- OpAMD64VPSLLVQ256
- OpAMD64VPSHLDVQ256
- OpAMD64VPSHLDVQMasked256
- OpAMD64VPSLLVQMasked256
- OpAMD64VPSRAVQ256
- OpAMD64VPSHRDVQ256
- OpAMD64VPSHRDVQMasked256
- OpAMD64VPSRAVQMasked256
- OpAMD64VPSUBQ256
- OpAMD64VPSUBQMasked256
- OpAMD64VPXORQMasked256
- OpAMD64VPABSQ512
- OpAMD64VPABSQMasked512
- OpAMD64VPADDQ512
- OpAMD64VPADDQMasked512
- OpAMD64VPANDQ512
- OpAMD64VPANDQMasked512
- OpAMD64VPANDNQ512
- OpAMD64VPANDNQMasked512
- OpAMD64VPCOMPRESSQMasked512
- OpAMD64VPCMPEQQ512
- OpAMD64VPCMPGTQ512
- OpAMD64VPMAXSQ512
- OpAMD64VPMAXSQMasked512
- OpAMD64VPMINSQ512
- OpAMD64VPMINSQMasked512
- OpAMD64VPMULDQ512
- OpAMD64VPMULDQMasked512
- OpAMD64VPMULLQ512
- OpAMD64VPMULLQMasked512
- OpAMD64VPORQ512
- OpAMD64VPORQMasked512
- OpAMD64VPOPCNTQ512
- OpAMD64VPOPCNTQMasked512
- OpAMD64VPROLVQ512
- OpAMD64VPROLVQMasked512
- OpAMD64VPRORVQ512
- OpAMD64VPRORVQMasked512
- OpAMD64VPSLLQ512
- OpAMD64VPSLLQMasked512
- OpAMD64VPSRAQ512
OpAMD64VPSRAQMasked512
- OpAMD64VPSLLVQ512
- OpAMD64VPSHLDVQ512
- OpAMD64VPSHLDVQMasked512
- OpAMD64VPSLLVQMasked512
+ OpAMD64VPSRAVD128
+ OpAMD64VPSRAVD256
+ OpAMD64VPSRAVD512
+ OpAMD64VPSRAVDMasked128
+ OpAMD64VPSRAVDMasked256
+ OpAMD64VPSRAVDMasked512
+ OpAMD64VPSRAVQ128
+ OpAMD64VPSRAVQ256
OpAMD64VPSRAVQ512
- OpAMD64VPSHRDVQ512
- OpAMD64VPSHRDVQMasked512
+ OpAMD64VPSRAVQMasked128
+ OpAMD64VPSRAVQMasked256
OpAMD64VPSRAVQMasked512
- OpAMD64VPSUBQ512
- OpAMD64VPSUBQMasked512
- OpAMD64VPXORQ512
- OpAMD64VPXORQMasked512
- OpAMD64VPABSB128
- OpAMD64VPABSBMasked128
- OpAMD64VPADDB128
- OpAMD64VPADDBMasked128
- OpAMD64VPAND128
- OpAMD64VPANDN128
- OpAMD64VPCOMPRESSBMasked128
- OpAMD64VPCMPEQB128
- OpAMD64VPCMPGTB128
- OpAMD64VPMAXSB128
- OpAMD64VPMAXSBMasked128
- OpAMD64VPMINSB128
- OpAMD64VPMINSBMasked128
- OpAMD64VPOR128
- OpAMD64VPOPCNTB128
- OpAMD64VPOPCNTBMasked128
- OpAMD64VPADDSB128
- OpAMD64VPADDSBMasked128
- OpAMD64VPSUBSB128
- OpAMD64VPSUBSBMasked128
- OpAMD64VPSIGNB128
- OpAMD64VPSUBB128
- OpAMD64VPSUBBMasked128
- OpAMD64VPXOR128
- OpAMD64VPABSB256
- OpAMD64VPABSBMasked256
- OpAMD64VPADDB256
- OpAMD64VPADDBMasked256
- OpAMD64VPAND256
- OpAMD64VPANDN256
- OpAMD64VPCOMPRESSBMasked256
- OpAMD64VPCMPEQB256
- OpAMD64VPCMPGTB256
- OpAMD64VPMAXSB256
- OpAMD64VPMAXSBMasked256
- OpAMD64VPMINSB256
- OpAMD64VPMINSBMasked256
- OpAMD64VPOR256
- OpAMD64VPOPCNTB256
- OpAMD64VPOPCNTBMasked256
- OpAMD64VPADDSB256
- OpAMD64VPADDSBMasked256
- OpAMD64VPSUBSB256
- OpAMD64VPSUBSBMasked256
- OpAMD64VPSIGNB256
- OpAMD64VPSUBB256
- OpAMD64VPSUBBMasked256
- OpAMD64VPXOR256
- OpAMD64VPABSB512
- OpAMD64VPABSBMasked512
- OpAMD64VPADDB512
- OpAMD64VPADDBMasked512
- OpAMD64VPCOMPRESSBMasked512
- OpAMD64VPCMPEQB512
- OpAMD64VPCMPGTB512
- OpAMD64VPMAXSB512
- OpAMD64VPMAXSBMasked512
- OpAMD64VPMINSB512
- OpAMD64VPMINSBMasked512
- OpAMD64VPOPCNTB512
- OpAMD64VPOPCNTBMasked512
- OpAMD64VPADDSB512
- OpAMD64VPADDSBMasked512
- OpAMD64VPSUBSB512
- OpAMD64VPSUBSBMasked512
- OpAMD64VPSUBB512
- OpAMD64VPSUBBMasked512
- OpAMD64VPAVGW256
- OpAMD64VPAVGWMasked256
- OpAMD64VPMAXUW256
- OpAMD64VPMAXUWMasked256
- OpAMD64VPMINUW256
- OpAMD64VPMINUWMasked256
- OpAMD64VPMULHUW256
- OpAMD64VPMULHUWMasked256
- OpAMD64VPERMW256
- OpAMD64VPERMI2W256
- OpAMD64VPERMI2WMasked256
- OpAMD64VPERMWMasked256
- OpAMD64VPSRLW256
- OpAMD64VPSRLWMasked256
- OpAMD64VPSRLVW256
- OpAMD64VPSRLVWMasked256
- OpAMD64VPAVGW512
- OpAMD64VPAVGWMasked512
- OpAMD64VPMAXUW512
- OpAMD64VPMAXUWMasked512
- OpAMD64VPMINUW512
- OpAMD64VPMINUWMasked512
- OpAMD64VPMULHUW512
- OpAMD64VPMULHUWMasked512
- OpAMD64VPERMW512
- OpAMD64VPERMI2W512
- OpAMD64VPERMI2WMasked512
- OpAMD64VPERMWMasked512
- OpAMD64VPSRLW512
- OpAMD64VPSRLWMasked512
- OpAMD64VPSRLVW512
- OpAMD64VPSRLVWMasked512
- OpAMD64VPAVGW128
- OpAMD64VPAVGWMasked128
- OpAMD64VPMAXUW128
- OpAMD64VPMAXUWMasked128
- OpAMD64VPMINUW128
- OpAMD64VPMINUWMasked128
- OpAMD64VPMULHUW128
- OpAMD64VPMULHUWMasked128
- OpAMD64VPERMW128
- OpAMD64VPERMI2W128
- OpAMD64VPERMI2WMasked128
- OpAMD64VPERMWMasked128
- OpAMD64VPSRLW128
- OpAMD64VPSRLWMasked128
- OpAMD64VPSRLVW128
- OpAMD64VPSRLVWMasked128
- OpAMD64VPMAXUD512
- OpAMD64VPMAXUDMasked512
- OpAMD64VPMINUD512
- OpAMD64VPMINUDMasked512
- OpAMD64VPERMD512
- OpAMD64VPERMPS512
- OpAMD64VPERMI2PS512
- OpAMD64VPERMI2D512
- OpAMD64VPERMI2PSMasked512
- OpAMD64VPERMI2DMasked512
- OpAMD64VPERMPSMasked512
- OpAMD64VPERMDMasked512
- OpAMD64VPSRLD512
- OpAMD64VPSRLDMasked512
- OpAMD64VPSRLVD512
- OpAMD64VPSRLVDMasked512
- OpAMD64VPMAXUD128
- OpAMD64VPMAXUDMasked128
- OpAMD64VPMINUD128
- OpAMD64VPMINUDMasked128
- OpAMD64VPMULUDQ128
- OpAMD64VPERMI2PS128
- OpAMD64VPERMI2D128
- OpAMD64VPERMI2DMasked128
- OpAMD64VPERMI2PSMasked128
+ OpAMD64VPSRAVW128
+ OpAMD64VPSRAVW256
+ OpAMD64VPSRAVW512
+ OpAMD64VPSRAVWMasked128
+ OpAMD64VPSRAVWMasked256
+ OpAMD64VPSRAVWMasked512
+ OpAMD64VPSRAW128
+ OpAMD64VPSRAW256
+ OpAMD64VPSRAW512
+ OpAMD64VPSRAWMasked128
+ OpAMD64VPSRAWMasked256
+ OpAMD64VPSRAWMasked512
OpAMD64VPSRLD128
- OpAMD64VPSRLDMasked128
- OpAMD64VPSRLVD128
- OpAMD64VPSRLVDMasked128
- OpAMD64VPMAXUD256
- OpAMD64VPMAXUDMasked256
- OpAMD64VPMINUD256
- OpAMD64VPMINUDMasked256
- OpAMD64VPMULUDQ256
- OpAMD64VPERMD256
- OpAMD64VPERMPS256
- OpAMD64VPERMI2PS256
- OpAMD64VPERMI2D256
- OpAMD64VPERMI2PSMasked256
- OpAMD64VPERMI2DMasked256
- OpAMD64VPERMPSMasked256
- OpAMD64VPERMDMasked256
OpAMD64VPSRLD256
+ OpAMD64VPSRLD512
+ OpAMD64VPSRLDMasked128
OpAMD64VPSRLDMasked256
- OpAMD64VPSRLVD256
- OpAMD64VPSRLVDMasked256
- OpAMD64VPMAXUQ128
- OpAMD64VPMAXUQMasked128
- OpAMD64VPMINUQ128
- OpAMD64VPMINUQMasked128
- OpAMD64VPMULUDQMasked128
- OpAMD64VPERMI2PD128
- OpAMD64VPERMI2Q128
- OpAMD64VPERMI2PDMasked128
- OpAMD64VPERMI2QMasked128
+ OpAMD64VPSRLDMasked512
OpAMD64VPSRLQ128
- OpAMD64VPSRLQMasked128
- OpAMD64VPSRLVQ128
- OpAMD64VPSRLVQMasked128
- OpAMD64VPMAXUQ256
- OpAMD64VPMAXUQMasked256
- OpAMD64VPMINUQ256
- OpAMD64VPMINUQMasked256
- OpAMD64VPMULUDQMasked256
- OpAMD64VPERMPD256
- OpAMD64VPERMQ256
- OpAMD64VPERMI2PD256
- OpAMD64VPERMI2Q256
- OpAMD64VPERMI2PDMasked256
- OpAMD64VPERMI2QMasked256
- OpAMD64VPERMQMasked256
- OpAMD64VPERMPDMasked256
OpAMD64VPSRLQ256
- OpAMD64VPSRLQMasked256
- OpAMD64VPSRLVQ256
- OpAMD64VPSRLVQMasked256
- OpAMD64VPMAXUQ512
- OpAMD64VPMAXUQMasked512
- OpAMD64VPMINUQ512
- OpAMD64VPMINUQMasked512
- OpAMD64VPMULUDQ512
- OpAMD64VPMULUDQMasked512
- OpAMD64VPERMPD512
- OpAMD64VPERMQ512
- OpAMD64VPERMI2Q512
- OpAMD64VPERMI2PD512
- OpAMD64VPERMI2QMasked512
- OpAMD64VPERMI2PDMasked512
- OpAMD64VPERMPDMasked512
- OpAMD64VPERMQMasked512
OpAMD64VPSRLQ512
+ OpAMD64VPSRLQMasked128
+ OpAMD64VPSRLQMasked256
OpAMD64VPSRLQMasked512
+ OpAMD64VPSRLVD128
+ OpAMD64VPSRLVD256
+ OpAMD64VPSRLVD512
+ OpAMD64VPSRLVDMasked128
+ OpAMD64VPSRLVDMasked256
+ OpAMD64VPSRLVDMasked512
+ OpAMD64VPSRLVQ128
+ OpAMD64VPSRLVQ256
OpAMD64VPSRLVQ512
+ OpAMD64VPSRLVQMasked128
+ OpAMD64VPSRLVQMasked256
OpAMD64VPSRLVQMasked512
- OpAMD64VPAVGB128
- OpAMD64VPAVGBMasked128
- OpAMD64VGF2P8MULB128
- OpAMD64VGF2P8MULBMasked128
- OpAMD64VPMAXUB128
- OpAMD64VPMAXUBMasked128
- OpAMD64VPMINUB128
- OpAMD64VPMINUBMasked128
- OpAMD64VPERMB128
- OpAMD64VPERMI2B128
- OpAMD64VPERMI2BMasked128
- OpAMD64VPERMBMasked128
- OpAMD64VPMADDUBSW128
- OpAMD64VPMADDUBSWMasked128
- OpAMD64VPAVGB256
- OpAMD64VPAVGBMasked256
- OpAMD64VGF2P8MULB256
- OpAMD64VGF2P8MULBMasked256
- OpAMD64VPMAXUB256
- OpAMD64VPMAXUBMasked256
- OpAMD64VPMINUB256
- OpAMD64VPMINUBMasked256
- OpAMD64VPERMB256
- OpAMD64VPERMI2B256
- OpAMD64VPERMI2BMasked256
- OpAMD64VPERMBMasked256
- OpAMD64VPMADDUBSW256
- OpAMD64VPMADDUBSWMasked256
- OpAMD64VPAVGB512
- OpAMD64VPAVGBMasked512
- OpAMD64VGF2P8MULB512
- OpAMD64VGF2P8MULBMasked512
- OpAMD64VPMAXUB512
- OpAMD64VPMAXUBMasked512
- OpAMD64VPMINUB512
- OpAMD64VPMINUBMasked512
- OpAMD64VPERMB512
- OpAMD64VPERMI2B512
- OpAMD64VPERMI2BMasked512
- OpAMD64VPERMBMasked512
- OpAMD64VPMADDUBSW512
- OpAMD64VPMADDUBSWMasked512
- OpAMD64VRNDSCALEPS512
- OpAMD64VRNDSCALEPSMasked512
- OpAMD64VREDUCEPS512
- OpAMD64VREDUCEPSMasked512
- OpAMD64VCMPPS512
- OpAMD64VCMPPSMasked512
+ OpAMD64VPSRLVW128
+ OpAMD64VPSRLVW256
+ OpAMD64VPSRLVW512
+ OpAMD64VPSRLVWMasked128
+ OpAMD64VPSRLVWMasked256
+ OpAMD64VPSRLVWMasked512
+ OpAMD64VPSRLW128
+ OpAMD64VPSRLW256
+ OpAMD64VPSRLW512
+ OpAMD64VPSRLWMasked128
+ OpAMD64VPSRLWMasked256
+ OpAMD64VPSRLWMasked512
+ OpAMD64VPSUBB128
+ OpAMD64VPSUBB256
+ OpAMD64VPSUBB512
+ OpAMD64VPSUBBMasked128
+ OpAMD64VPSUBBMasked256
+ OpAMD64VPSUBBMasked512
+ OpAMD64VPSUBD128
+ OpAMD64VPSUBD256
+ OpAMD64VPSUBD512
+ OpAMD64VPSUBDMasked128
+ OpAMD64VPSUBDMasked256
+ OpAMD64VPSUBDMasked512
+ OpAMD64VPSUBQ128
+ OpAMD64VPSUBQ256
+ OpAMD64VPSUBQ512
+ OpAMD64VPSUBQMasked128
+ OpAMD64VPSUBQMasked256
+ OpAMD64VPSUBQMasked512
+ OpAMD64VPSUBSB128
+ OpAMD64VPSUBSB256
+ OpAMD64VPSUBSB512
+ OpAMD64VPSUBSBMasked128
+ OpAMD64VPSUBSBMasked256
+ OpAMD64VPSUBSBMasked512
+ OpAMD64VPSUBSW128
+ OpAMD64VPSUBSW256
+ OpAMD64VPSUBSW512
+ OpAMD64VPSUBSWMasked128
+ OpAMD64VPSUBSWMasked256
+ OpAMD64VPSUBSWMasked512
+ OpAMD64VPSUBW128
+ OpAMD64VPSUBW256
+ OpAMD64VPSUBW512
+ OpAMD64VPSUBWMasked128
+ OpAMD64VPSUBWMasked256
+ OpAMD64VPSUBWMasked512
+ OpAMD64VPXOR128
+ OpAMD64VPXOR256
+ OpAMD64VPXORD512
+ OpAMD64VPXORDMasked128
+ OpAMD64VPXORDMasked256
+ OpAMD64VPXORDMasked512
+ OpAMD64VPXORQ512
+ OpAMD64VPXORQMasked128
+ OpAMD64VPXORQMasked256
+ OpAMD64VPXORQMasked512
+ OpAMD64VRCP14PD128
+ OpAMD64VRCP14PD256
+ OpAMD64VRCP14PD512
+ OpAMD64VRCP14PDMasked128
+ OpAMD64VRCP14PDMasked256
+ OpAMD64VRCP14PDMasked512
+ OpAMD64VRCP14PS512
+ OpAMD64VRCP14PSMasked128
+ OpAMD64VRCP14PSMasked256
+ OpAMD64VRCP14PSMasked512
+ OpAMD64VRCPPS128
+ OpAMD64VRCPPS256
+ OpAMD64VRSQRT14PD128
+ OpAMD64VRSQRT14PD256
+ OpAMD64VRSQRT14PD512
+ OpAMD64VRSQRT14PDMasked128
+ OpAMD64VRSQRT14PDMasked256
+ OpAMD64VRSQRT14PDMasked512
+ OpAMD64VRSQRT14PS512
+ OpAMD64VRSQRT14PSMasked128
+ OpAMD64VRSQRT14PSMasked256
+ OpAMD64VRSQRT14PSMasked512
+ OpAMD64VRSQRTPS128
+ OpAMD64VRSQRTPS256
+ OpAMD64VSCALEFPD128
+ OpAMD64VSCALEFPD256
+ OpAMD64VSCALEFPD512
+ OpAMD64VSCALEFPDMasked128
+ OpAMD64VSCALEFPDMasked256
+ OpAMD64VSCALEFPDMasked512
+ OpAMD64VSCALEFPS128
+ OpAMD64VSCALEFPS256
+ OpAMD64VSCALEFPS512
+ OpAMD64VSCALEFPSMasked128
+ OpAMD64VSCALEFPSMasked256
+ OpAMD64VSCALEFPSMasked512
+ OpAMD64VSQRTPD128
+ OpAMD64VSQRTPD256
+ OpAMD64VSQRTPD512
+ OpAMD64VSQRTPDMasked128
+ OpAMD64VSQRTPDMasked256
+ OpAMD64VSQRTPDMasked512
+ OpAMD64VSQRTPS128
+ OpAMD64VSQRTPS256
+ OpAMD64VSQRTPS512
+ OpAMD64VSQRTPSMasked128
+ OpAMD64VSQRTPSMasked256
+ OpAMD64VSQRTPSMasked512
+ OpAMD64VSUBPD128
+ OpAMD64VSUBPD256
+ OpAMD64VSUBPD512
+ OpAMD64VSUBPDMasked128
+ OpAMD64VSUBPDMasked256
+ OpAMD64VSUBPDMasked512
+ OpAMD64VSUBPS128
+ OpAMD64VSUBPS256
+ OpAMD64VSUBPS512
+ OpAMD64VSUBPSMasked128
+ OpAMD64VSUBPSMasked256
+ OpAMD64VSUBPSMasked512
OpAMD64VROUNDPS128
- OpAMD64VRNDSCALEPS128
- OpAMD64VRNDSCALEPSMasked128
- OpAMD64VREDUCEPS128
- OpAMD64VREDUCEPSMasked128
- OpAMD64VDPPS128
- OpAMD64VCMPPS128
- OpAMD64VCMPPSMasked128
OpAMD64VROUNDPS256
- OpAMD64VRNDSCALEPS256
- OpAMD64VRNDSCALEPSMasked256
- OpAMD64VREDUCEPS256
- OpAMD64VREDUCEPSMasked256
- OpAMD64VDPPS256
- OpAMD64VCMPPS256
- OpAMD64VCMPPSMasked256
- OpAMD64VEXTRACTF128128
- OpAMD64VINSERTF128256
OpAMD64VROUNDPD128
+ OpAMD64VROUNDPD256
+ OpAMD64VRNDSCALEPS128
+ OpAMD64VRNDSCALEPS256
+ OpAMD64VRNDSCALEPS512
OpAMD64VRNDSCALEPD128
+ OpAMD64VRNDSCALEPD256
+ OpAMD64VRNDSCALEPD512
+ OpAMD64VRNDSCALEPSMasked128
+ OpAMD64VRNDSCALEPSMasked256
+ OpAMD64VRNDSCALEPSMasked512
OpAMD64VRNDSCALEPDMasked128
+ OpAMD64VRNDSCALEPDMasked256
+ OpAMD64VRNDSCALEPDMasked512
+ OpAMD64VREDUCEPS128
+ OpAMD64VREDUCEPS256
+ OpAMD64VREDUCEPS512
OpAMD64VREDUCEPD128
+ OpAMD64VREDUCEPD256
+ OpAMD64VREDUCEPD512
+ OpAMD64VREDUCEPSMasked128
+ OpAMD64VREDUCEPSMasked256
+ OpAMD64VREDUCEPSMasked512
OpAMD64VREDUCEPDMasked128
+ OpAMD64VREDUCEPDMasked256
+ OpAMD64VREDUCEPDMasked512
+ OpAMD64VDPPS128
+ OpAMD64VDPPS256
OpAMD64VDPPD128
+ OpAMD64VCMPPS128
+ OpAMD64VCMPPS256
+ OpAMD64VCMPPS512
OpAMD64VCMPPD128
- OpAMD64VCMPPDMasked128
- OpAMD64VROUNDPD256
- OpAMD64VRNDSCALEPD256
- OpAMD64VRNDSCALEPDMasked256
- OpAMD64VREDUCEPD256
- OpAMD64VREDUCEPDMasked256
OpAMD64VCMPPD256
- OpAMD64VCMPPDMasked256
- OpAMD64VRNDSCALEPD512
- OpAMD64VRNDSCALEPDMasked512
- OpAMD64VREDUCEPD512
- OpAMD64VREDUCEPDMasked512
OpAMD64VCMPPD512
+ OpAMD64VCMPPSMasked128
+ OpAMD64VCMPPSMasked256
+ OpAMD64VCMPPSMasked512
+ OpAMD64VCMPPDMasked128
+ OpAMD64VCMPPDMasked256
OpAMD64VCMPPDMasked512
+ OpAMD64VPCMPBMasked128
+ OpAMD64VPCMPBMasked256
+ OpAMD64VPCMPBMasked512
+ OpAMD64VPCMPWMasked128
OpAMD64VPCMPWMasked256
- OpAMD64VPCMPW256
- OpAMD64VPSHLDW256
- OpAMD64VPSHLDWMasked256
- OpAMD64VPSHRDW256
- OpAMD64VPSHRDWMasked256
OpAMD64VPCMPWMasked512
- OpAMD64VPCMPW512
- OpAMD64VPSHLDW512
- OpAMD64VPSHLDWMasked512
- OpAMD64VPSHRDW512
- OpAMD64VPSHRDWMasked512
- OpAMD64VPCMPWMasked128
- OpAMD64VPEXTRW128
- OpAMD64VPCMPW128
- OpAMD64VPINSRW128
- OpAMD64VPSHLDW128
- OpAMD64VPSHLDWMasked128
- OpAMD64VPSHRDW128
- OpAMD64VPSHRDWMasked128
- OpAMD64VPCMPDMasked512
- OpAMD64VPCMPD512
- OpAMD64VPROLD512
- OpAMD64VPROLDMasked512
- OpAMD64VPRORD512
- OpAMD64VPRORDMasked512
- OpAMD64VPSHLDD512
- OpAMD64VPSHLDDMasked512
- OpAMD64VPSHRDD512
- OpAMD64VPSHRDDMasked512
OpAMD64VPCMPDMasked128
- OpAMD64VPEXTRD128
- OpAMD64VPCMPD128
- OpAMD64VPROLD128
- OpAMD64VPROLDMasked128
- OpAMD64VPRORD128
- OpAMD64VPRORDMasked128
- OpAMD64VPINSRD128
- OpAMD64VPSHLDD128
- OpAMD64VPSHLDDMasked128
- OpAMD64VPSHRDD128
- OpAMD64VPSHRDDMasked128
OpAMD64VPCMPDMasked256
- OpAMD64VPCMPD256
- OpAMD64VPROLD256
- OpAMD64VPROLDMasked256
- OpAMD64VPRORD256
- OpAMD64VPRORDMasked256
- OpAMD64VPSHLDD256
- OpAMD64VPSHLDDMasked256
- OpAMD64VPSHRDD256
- OpAMD64VPSHRDDMasked256
+ OpAMD64VPCMPDMasked512
OpAMD64VPCMPQMasked128
- OpAMD64VPEXTRQ128
- OpAMD64VPCMPQ128
- OpAMD64VPROLQ128
- OpAMD64VPROLQMasked128
- OpAMD64VPRORQ128
- OpAMD64VPRORQMasked128
- OpAMD64VPINSRQ128
- OpAMD64VPSHLDQ128
- OpAMD64VPSHLDQMasked128
- OpAMD64VPSHRDQ128
- OpAMD64VPSHRDQMasked128
OpAMD64VPCMPQMasked256
- OpAMD64VPCMPQ256
- OpAMD64VPROLQ256
- OpAMD64VPROLQMasked256
- OpAMD64VPRORQ256
- OpAMD64VPRORQMasked256
- OpAMD64VPSHLDQ256
- OpAMD64VPSHLDQMasked256
- OpAMD64VPSHRDQ256
- OpAMD64VPSHRDQMasked256
OpAMD64VPCMPQMasked512
- OpAMD64VPCMPQ512
- OpAMD64VPROLQ512
- OpAMD64VPROLQMasked512
- OpAMD64VPRORQ512
- OpAMD64VPRORQMasked512
- OpAMD64VPSHLDQ512
- OpAMD64VPSHLDQMasked512
- OpAMD64VPSHRDQ512
- OpAMD64VPSHRDQMasked512
- OpAMD64VPCMPBMasked128
- OpAMD64VPEXTRB128
- OpAMD64VPCMPB128
- OpAMD64VPINSRB128
- OpAMD64VPCMPBMasked256
- OpAMD64VEXTRACTI128128
- OpAMD64VPCMPB256
- OpAMD64VINSERTI128256
- OpAMD64VPCMPBMasked512
- OpAMD64VPCMPB512
+ OpAMD64VPCMPUBMasked128
+ OpAMD64VPCMPUBMasked256
+ OpAMD64VPCMPUBMasked512
+ OpAMD64VPCMPUWMasked128
OpAMD64VPCMPUWMasked256
- OpAMD64VPCMPUW256
OpAMD64VPCMPUWMasked512
- OpAMD64VPCMPUW512
- OpAMD64VPCMPUWMasked128
- OpAMD64VPCMPUW128
- OpAMD64VPCMPUDMasked512
- OpAMD64VPCMPUD512
OpAMD64VPCMPUDMasked128
- OpAMD64VPCMPUD128
OpAMD64VPCMPUDMasked256
- OpAMD64VPCMPUD256
+ OpAMD64VPCMPUDMasked512
OpAMD64VPCMPUQMasked128
- OpAMD64VPCMPUQ128
OpAMD64VPCMPUQMasked256
- OpAMD64VPCMPUQ256
OpAMD64VPCMPUQMasked512
- OpAMD64VPCMPUQ512
- OpAMD64VPCMPUBMasked128
OpAMD64VGF2P8AFFINEQB128
- OpAMD64VGF2P8AFFINEINVQB128
- OpAMD64VGF2P8AFFINEINVQBMasked128
- OpAMD64VGF2P8AFFINEQBMasked128
- OpAMD64VPCMPUB128
- OpAMD64VPCMPUBMasked256
OpAMD64VGF2P8AFFINEQB256
- OpAMD64VGF2P8AFFINEINVQB256
- OpAMD64VGF2P8AFFINEINVQBMasked256
- OpAMD64VGF2P8AFFINEQBMasked256
- OpAMD64VPCMPUB256
- OpAMD64VPCMPUBMasked512
OpAMD64VGF2P8AFFINEQB512
+ OpAMD64VGF2P8AFFINEINVQB128
+ OpAMD64VGF2P8AFFINEINVQB256
OpAMD64VGF2P8AFFINEINVQB512
+ OpAMD64VGF2P8AFFINEINVQBMasked128
+ OpAMD64VGF2P8AFFINEINVQBMasked256
OpAMD64VGF2P8AFFINEINVQBMasked512
+ OpAMD64VGF2P8AFFINEQBMasked128
+ OpAMD64VGF2P8AFFINEQBMasked256
OpAMD64VGF2P8AFFINEQBMasked512
+ OpAMD64VEXTRACTF128128
+ OpAMD64VEXTRACTI128128
+ OpAMD64VPEXTRB128
+ OpAMD64VPEXTRW128
+ OpAMD64VPEXTRD128
+ OpAMD64VPEXTRQ128
+ OpAMD64VPCMPUB128
+ OpAMD64VPCMPUB256
OpAMD64VPCMPUB512
+ OpAMD64VPCMPUW128
+ OpAMD64VPCMPUW256
+ OpAMD64VPCMPUW512
+ OpAMD64VPCMPUD128
+ OpAMD64VPCMPUD256
+ OpAMD64VPCMPUD512
+ OpAMD64VPCMPUQ128
+ OpAMD64VPCMPUQ256
+ OpAMD64VPCMPUQ512
+ OpAMD64VPCMPB128
+ OpAMD64VPCMPB256
+ OpAMD64VPCMPB512
+ OpAMD64VPCMPW128
+ OpAMD64VPCMPW256
+ OpAMD64VPCMPW512
+ OpAMD64VPCMPD128
+ OpAMD64VPCMPD256
+ OpAMD64VPCMPD512
+ OpAMD64VPCMPQ128
+ OpAMD64VPCMPQ256
+ OpAMD64VPCMPQ512
+ OpAMD64VPROLD128
+ OpAMD64VPROLD256
+ OpAMD64VPROLD512
+ OpAMD64VPROLQ128
+ OpAMD64VPROLQ256
+ OpAMD64VPROLQ512
+ OpAMD64VPROLDMasked128
+ OpAMD64VPROLDMasked256
+ OpAMD64VPROLDMasked512
+ OpAMD64VPROLQMasked128
+ OpAMD64VPROLQMasked256
+ OpAMD64VPROLQMasked512
+ OpAMD64VPRORD128
+ OpAMD64VPRORD256
+ OpAMD64VPRORD512
+ OpAMD64VPRORQ128
+ OpAMD64VPRORQ256
+ OpAMD64VPRORQ512
+ OpAMD64VPRORDMasked128
+ OpAMD64VPRORDMasked256
+ OpAMD64VPRORDMasked512
+ OpAMD64VPRORQMasked128
+ OpAMD64VPRORQMasked256
+ OpAMD64VPRORQMasked512
+ OpAMD64VINSERTF128256
+ OpAMD64VINSERTI128256
+ OpAMD64VPINSRB128
+ OpAMD64VPINSRW128
+ OpAMD64VPINSRD128
+ OpAMD64VPINSRQ128
+ OpAMD64VPSHLDW128
+ OpAMD64VPSHLDW256
+ OpAMD64VPSHLDW512
+ OpAMD64VPSHLDD128
+ OpAMD64VPSHLDD256
+ OpAMD64VPSHLDD512
+ OpAMD64VPSHLDQ128
+ OpAMD64VPSHLDQ256
+ OpAMD64VPSHLDQ512
+ OpAMD64VPSHLDWMasked128
+ OpAMD64VPSHLDWMasked256
+ OpAMD64VPSHLDWMasked512
+ OpAMD64VPSHLDDMasked128
+ OpAMD64VPSHLDDMasked256
+ OpAMD64VPSHLDDMasked512
+ OpAMD64VPSHLDQMasked128
+ OpAMD64VPSHLDQMasked256
+ OpAMD64VPSHLDQMasked512
+ OpAMD64VPSHRDW128
+ OpAMD64VPSHRDW256
+ OpAMD64VPSHRDW512
+ OpAMD64VPSHRDD128
+ OpAMD64VPSHRDD256
+ OpAMD64VPSHRDD512
+ OpAMD64VPSHRDQ128
+ OpAMD64VPSHRDQ256
+ OpAMD64VPSHRDQ512
+ OpAMD64VPSHRDWMasked128
+ OpAMD64VPSHRDWMasked256
+ OpAMD64VPSHRDWMasked512
+ OpAMD64VPSHRDDMasked128
+ OpAMD64VPSHRDDMasked256
+ OpAMD64VPSHRDDMasked512
+ OpAMD64VPSHRDQMasked128
+ OpAMD64VPSHRDQMasked256
+ OpAMD64VPSHRDQMasked512
OpARMADD
OpARMADDconst
OpStoreMask64x2
OpStoreMask64x4
OpStoreMask64x8
- OpAddFloat32x16
- OpAddMaskedFloat32x16
- OpApproximateReciprocalFloat32x16
- OpApproximateReciprocalMaskedFloat32x16
- OpApproximateReciprocalOfSqrtFloat32x16
- OpApproximateReciprocalOfSqrtMaskedFloat32x16
- OpCompressFloat32x16
- OpDivFloat32x16
- OpDivMaskedFloat32x16
- OpEqualFloat32x16
- OpEqualMaskedFloat32x16
- OpFusedMultiplyAddFloat32x16
- OpFusedMultiplyAddMaskedFloat32x16
- OpFusedMultiplyAddSubFloat32x16
- OpFusedMultiplyAddSubMaskedFloat32x16
- OpFusedMultiplySubAddFloat32x16
- OpFusedMultiplySubAddMaskedFloat32x16
- OpGreaterFloat32x16
- OpGreaterEqualFloat32x16
- OpGreaterEqualMaskedFloat32x16
- OpGreaterMaskedFloat32x16
- OpIsNanFloat32x16
- OpIsNanMaskedFloat32x16
- OpLessFloat32x16
- OpLessEqualFloat32x16
- OpLessEqualMaskedFloat32x16
- OpLessMaskedFloat32x16
- OpMaxFloat32x16
- OpMaxMaskedFloat32x16
- OpMinFloat32x16
- OpMinMaskedFloat32x16
- OpMulFloat32x16
- OpMulByPowOf2Float32x16
- OpMulByPowOf2MaskedFloat32x16
- OpMulMaskedFloat32x16
- OpNotEqualFloat32x16
- OpNotEqualMaskedFloat32x16
- OpSqrtFloat32x16
- OpSqrtMaskedFloat32x16
- OpSubFloat32x16
- OpSubMaskedFloat32x16
+ OpAbsoluteInt8x16
+ OpAbsoluteInt8x32
+ OpAbsoluteInt8x64
+ OpAbsoluteInt16x8
+ OpAbsoluteInt16x16
+ OpAbsoluteInt16x32
+ OpAbsoluteInt32x4
+ OpAbsoluteInt32x8
+ OpAbsoluteInt32x16
+ OpAbsoluteInt64x2
+ OpAbsoluteInt64x4
+ OpAbsoluteInt64x8
+ OpAbsoluteMaskedInt8x16
+ OpAbsoluteMaskedInt8x32
+ OpAbsoluteMaskedInt8x64
+ OpAbsoluteMaskedInt16x8
+ OpAbsoluteMaskedInt16x16
+ OpAbsoluteMaskedInt16x32
+ OpAbsoluteMaskedInt32x4
+ OpAbsoluteMaskedInt32x8
+ OpAbsoluteMaskedInt32x16
+ OpAbsoluteMaskedInt64x2
+ OpAbsoluteMaskedInt64x4
+ OpAbsoluteMaskedInt64x8
OpAddFloat32x4
+ OpAddFloat32x8
+ OpAddFloat32x16
+ OpAddFloat64x2
+ OpAddFloat64x4
+ OpAddFloat64x8
+ OpAddInt8x16
+ OpAddInt8x32
+ OpAddInt8x64
+ OpAddInt16x8
+ OpAddInt16x16
+ OpAddInt16x32
+ OpAddInt32x4
+ OpAddInt32x8
+ OpAddInt32x16
+ OpAddInt64x2
+ OpAddInt64x4
+ OpAddInt64x8
OpAddMaskedFloat32x4
+ OpAddMaskedFloat32x8
+ OpAddMaskedFloat32x16
+ OpAddMaskedFloat64x2
+ OpAddMaskedFloat64x4
+ OpAddMaskedFloat64x8
+ OpAddMaskedInt8x16
+ OpAddMaskedInt8x32
+ OpAddMaskedInt8x64
+ OpAddMaskedInt16x8
+ OpAddMaskedInt16x16
+ OpAddMaskedInt16x32
+ OpAddMaskedInt32x4
+ OpAddMaskedInt32x8
+ OpAddMaskedInt32x16
+ OpAddMaskedInt64x2
+ OpAddMaskedInt64x4
+ OpAddMaskedInt64x8
+ OpAddMaskedUint8x16
+ OpAddMaskedUint8x32
+ OpAddMaskedUint8x64
+ OpAddMaskedUint16x8
+ OpAddMaskedUint16x16
+ OpAddMaskedUint16x32
+ OpAddMaskedUint32x4
+ OpAddMaskedUint32x8
+ OpAddMaskedUint32x16
+ OpAddMaskedUint64x2
+ OpAddMaskedUint64x4
+ OpAddMaskedUint64x8
OpAddSubFloat32x4
+ OpAddSubFloat32x8
+ OpAddSubFloat64x2
+ OpAddSubFloat64x4
+ OpAddUint8x16
+ OpAddUint8x32
+ OpAddUint8x64
+ OpAddUint16x8
+ OpAddUint16x16
+ OpAddUint16x32
+ OpAddUint32x4
+ OpAddUint32x8
+ OpAddUint32x16
+ OpAddUint64x2
+ OpAddUint64x4
+ OpAddUint64x8
+ OpAndInt8x16
+ OpAndInt8x32
+ OpAndInt16x8
+ OpAndInt16x16
+ OpAndInt32x4
+ OpAndInt32x8
+ OpAndInt32x16
+ OpAndInt64x2
+ OpAndInt64x4
+ OpAndInt64x8
+ OpAndMaskedInt32x4
+ OpAndMaskedInt32x8
+ OpAndMaskedInt32x16
+ OpAndMaskedInt64x2
+ OpAndMaskedInt64x4
+ OpAndMaskedInt64x8
+ OpAndMaskedUint32x4
+ OpAndMaskedUint32x8
+ OpAndMaskedUint32x16
+ OpAndMaskedUint64x2
+ OpAndMaskedUint64x4
+ OpAndMaskedUint64x8
+ OpAndNotInt8x16
+ OpAndNotInt8x32
+ OpAndNotInt16x8
+ OpAndNotInt16x16
+ OpAndNotInt32x4
+ OpAndNotInt32x8
+ OpAndNotInt32x16
+ OpAndNotInt64x2
+ OpAndNotInt64x4
+ OpAndNotInt64x8
+ OpAndNotMaskedInt32x4
+ OpAndNotMaskedInt32x8
+ OpAndNotMaskedInt32x16
+ OpAndNotMaskedInt64x2
+ OpAndNotMaskedInt64x4
+ OpAndNotMaskedInt64x8
+ OpAndNotMaskedUint32x4
+ OpAndNotMaskedUint32x8
+ OpAndNotMaskedUint32x16
+ OpAndNotMaskedUint64x2
+ OpAndNotMaskedUint64x4
+ OpAndNotMaskedUint64x8
+ OpAndNotUint8x16
+ OpAndNotUint8x32
+ OpAndNotUint16x8
+ OpAndNotUint16x16
+ OpAndNotUint32x4
+ OpAndNotUint32x8
+ OpAndNotUint32x16
+ OpAndNotUint64x2
+ OpAndNotUint64x4
+ OpAndNotUint64x8
+ OpAndUint8x16
+ OpAndUint8x32
+ OpAndUint16x8
+ OpAndUint16x16
+ OpAndUint32x4
+ OpAndUint32x8
+ OpAndUint32x16
+ OpAndUint64x2
+ OpAndUint64x4
+ OpAndUint64x8
OpApproximateReciprocalFloat32x4
+ OpApproximateReciprocalFloat32x8
+ OpApproximateReciprocalFloat32x16
+ OpApproximateReciprocalFloat64x2
+ OpApproximateReciprocalFloat64x4
+ OpApproximateReciprocalFloat64x8
OpApproximateReciprocalMaskedFloat32x4
+ OpApproximateReciprocalMaskedFloat32x8
+ OpApproximateReciprocalMaskedFloat32x16
+ OpApproximateReciprocalMaskedFloat64x2
+ OpApproximateReciprocalMaskedFloat64x4
+ OpApproximateReciprocalMaskedFloat64x8
OpApproximateReciprocalOfSqrtFloat32x4
+ OpApproximateReciprocalOfSqrtFloat32x8
+ OpApproximateReciprocalOfSqrtFloat32x16
+ OpApproximateReciprocalOfSqrtFloat64x2
+ OpApproximateReciprocalOfSqrtFloat64x4
+ OpApproximateReciprocalOfSqrtFloat64x8
OpApproximateReciprocalOfSqrtMaskedFloat32x4
+ OpApproximateReciprocalOfSqrtMaskedFloat32x8
+ OpApproximateReciprocalOfSqrtMaskedFloat32x16
+ OpApproximateReciprocalOfSqrtMaskedFloat64x2
+ OpApproximateReciprocalOfSqrtMaskedFloat64x4
+ OpApproximateReciprocalOfSqrtMaskedFloat64x8
+ OpAverageMaskedUint8x16
+ OpAverageMaskedUint8x32
+ OpAverageMaskedUint8x64
+ OpAverageMaskedUint16x8
+ OpAverageMaskedUint16x16
+ OpAverageMaskedUint16x32
+ OpAverageUint8x16
+ OpAverageUint8x32
+ OpAverageUint8x64
+ OpAverageUint16x8
+ OpAverageUint16x16
+ OpAverageUint16x32
OpCeilFloat32x4
+ OpCeilFloat32x8
+ OpCeilFloat64x2
+ OpCeilFloat64x4
OpCompressFloat32x4
+ OpCompressFloat32x8
+ OpCompressFloat32x16
+ OpCompressFloat64x2
+ OpCompressFloat64x4
+ OpCompressFloat64x8
+ OpCompressInt8x16
+ OpCompressInt8x32
+ OpCompressInt8x64
+ OpCompressInt16x8
+ OpCompressInt16x16
+ OpCompressInt16x32
+ OpCompressInt32x4
+ OpCompressInt32x8
+ OpCompressInt32x16
+ OpCompressInt64x2
+ OpCompressInt64x4
+ OpCompressInt64x8
+ OpCompressUint8x16
+ OpCompressUint8x32
+ OpCompressUint8x64
+ OpCompressUint16x8
+ OpCompressUint16x16
+ OpCompressUint16x32
+ OpCompressUint32x4
+ OpCompressUint32x8
+ OpCompressUint32x16
+ OpCompressUint64x2
+ OpCompressUint64x4
+ OpCompressUint64x8
OpDivFloat32x4
+ OpDivFloat32x8
+ OpDivFloat32x16
+ OpDivFloat64x2
+ OpDivFloat64x4
+ OpDivFloat64x8
OpDivMaskedFloat32x4
+ OpDivMaskedFloat32x8
+ OpDivMaskedFloat32x16
+ OpDivMaskedFloat64x2
+ OpDivMaskedFloat64x4
+ OpDivMaskedFloat64x8
OpDotProdBroadcastFloat32x4
+ OpDotProdBroadcastFloat32x8
+ OpDotProdBroadcastFloat64x2
OpEqualFloat32x4
+ OpEqualFloat32x8
+ OpEqualFloat32x16
+ OpEqualFloat64x2
+ OpEqualFloat64x4
+ OpEqualFloat64x8
+ OpEqualInt8x16
+ OpEqualInt8x32
+ OpEqualInt8x64
+ OpEqualInt16x8
+ OpEqualInt16x16
+ OpEqualInt16x32
+ OpEqualInt32x4
+ OpEqualInt32x8
+ OpEqualInt32x16
+ OpEqualInt64x2
+ OpEqualInt64x4
+ OpEqualInt64x8
OpEqualMaskedFloat32x4
- OpFloorFloat32x4
- OpFusedMultiplyAddFloat32x4
- OpFusedMultiplyAddMaskedFloat32x4
- OpFusedMultiplyAddSubFloat32x4
- OpFusedMultiplyAddSubMaskedFloat32x4
- OpFusedMultiplySubAddFloat32x4
- OpFusedMultiplySubAddMaskedFloat32x4
- OpGreaterFloat32x4
- OpGreaterEqualFloat32x4
- OpGreaterEqualMaskedFloat32x4
- OpGreaterMaskedFloat32x4
- OpIsNanFloat32x4
- OpIsNanMaskedFloat32x4
- OpLessFloat32x4
- OpLessEqualFloat32x4
- OpLessEqualMaskedFloat32x4
- OpLessMaskedFloat32x4
- OpMaxFloat32x4
- OpMaxMaskedFloat32x4
- OpMinFloat32x4
- OpMinMaskedFloat32x4
- OpMulFloat32x4
- OpMulByPowOf2Float32x4
- OpMulByPowOf2MaskedFloat32x4
- OpMulMaskedFloat32x4
- OpNotEqualFloat32x4
- OpNotEqualMaskedFloat32x4
- OpPairwiseAddFloat32x4
- OpPairwiseSubFloat32x4
- OpRoundFloat32x4
- OpSqrtFloat32x4
- OpSqrtMaskedFloat32x4
- OpSubFloat32x4
- OpSubMaskedFloat32x4
- OpTruncFloat32x4
- OpAddFloat32x8
- OpAddMaskedFloat32x8
- OpAddSubFloat32x8
- OpApproximateReciprocalFloat32x8
- OpApproximateReciprocalMaskedFloat32x8
- OpApproximateReciprocalOfSqrtFloat32x8
- OpApproximateReciprocalOfSqrtMaskedFloat32x8
- OpCeilFloat32x8
- OpCompressFloat32x8
- OpDivFloat32x8
- OpDivMaskedFloat32x8
- OpDotProdBroadcastFloat32x8
- OpEqualFloat32x8
OpEqualMaskedFloat32x8
+ OpEqualMaskedFloat32x16
+ OpEqualMaskedFloat64x2
+ OpEqualMaskedFloat64x4
+ OpEqualMaskedFloat64x8
+ OpEqualMaskedInt8x16
+ OpEqualMaskedInt8x32
+ OpEqualMaskedInt8x64
+ OpEqualMaskedInt16x8
+ OpEqualMaskedInt16x16
+ OpEqualMaskedInt16x32
+ OpEqualMaskedInt32x4
+ OpEqualMaskedInt32x8
+ OpEqualMaskedInt32x16
+ OpEqualMaskedInt64x2
+ OpEqualMaskedInt64x4
+ OpEqualMaskedInt64x8
+ OpEqualMaskedUint8x16
+ OpEqualMaskedUint8x32
+ OpEqualMaskedUint8x64
+ OpEqualMaskedUint16x8
+ OpEqualMaskedUint16x16
+ OpEqualMaskedUint16x32
+ OpEqualMaskedUint32x4
+ OpEqualMaskedUint32x8
+ OpEqualMaskedUint32x16
+ OpEqualMaskedUint64x2
+ OpEqualMaskedUint64x4
+ OpEqualMaskedUint64x8
+ OpEqualUint8x16
+ OpEqualUint8x32
+ OpEqualUint8x64
+ OpEqualUint16x8
+ OpEqualUint16x16
+ OpEqualUint16x32
+ OpEqualUint32x4
+ OpEqualUint32x8
+ OpEqualUint32x16
+ OpEqualUint64x2
+ OpEqualUint64x4
+ OpEqualUint64x8
+ OpFloorFloat32x4
OpFloorFloat32x8
+ OpFloorFloat64x2
+ OpFloorFloat64x4
+ OpFusedMultiplyAddFloat32x4
OpFusedMultiplyAddFloat32x8
+ OpFusedMultiplyAddFloat32x16
+ OpFusedMultiplyAddFloat64x2
+ OpFusedMultiplyAddFloat64x4
+ OpFusedMultiplyAddFloat64x8
+ OpFusedMultiplyAddMaskedFloat32x4
OpFusedMultiplyAddMaskedFloat32x8
+ OpFusedMultiplyAddMaskedFloat32x16
+ OpFusedMultiplyAddMaskedFloat64x2
+ OpFusedMultiplyAddMaskedFloat64x4
+ OpFusedMultiplyAddMaskedFloat64x8
+ OpFusedMultiplyAddSubFloat32x4
OpFusedMultiplyAddSubFloat32x8
+ OpFusedMultiplyAddSubFloat32x16
+ OpFusedMultiplyAddSubFloat64x2
+ OpFusedMultiplyAddSubFloat64x4
+ OpFusedMultiplyAddSubFloat64x8
+ OpFusedMultiplyAddSubMaskedFloat32x4
OpFusedMultiplyAddSubMaskedFloat32x8
+ OpFusedMultiplyAddSubMaskedFloat32x16
+ OpFusedMultiplyAddSubMaskedFloat64x2
+ OpFusedMultiplyAddSubMaskedFloat64x4
+ OpFusedMultiplyAddSubMaskedFloat64x8
+ OpFusedMultiplySubAddFloat32x4
OpFusedMultiplySubAddFloat32x8
+ OpFusedMultiplySubAddFloat32x16
+ OpFusedMultiplySubAddFloat64x2
+ OpFusedMultiplySubAddFloat64x4
+ OpFusedMultiplySubAddFloat64x8
+ OpFusedMultiplySubAddMaskedFloat32x4
OpFusedMultiplySubAddMaskedFloat32x8
- OpGreaterFloat32x8
+ OpFusedMultiplySubAddMaskedFloat32x16
+ OpFusedMultiplySubAddMaskedFloat64x2
+ OpFusedMultiplySubAddMaskedFloat64x4
+ OpFusedMultiplySubAddMaskedFloat64x8
+ OpGaloisFieldMulMaskedUint8x16
+ OpGaloisFieldMulMaskedUint8x32
+ OpGaloisFieldMulMaskedUint8x64
+ OpGaloisFieldMulUint8x16
+ OpGaloisFieldMulUint8x32
+ OpGaloisFieldMulUint8x64
+ OpGreaterEqualFloat32x4
OpGreaterEqualFloat32x8
+ OpGreaterEqualFloat32x16
+ OpGreaterEqualFloat64x2
+ OpGreaterEqualFloat64x4
+ OpGreaterEqualFloat64x8
+ OpGreaterEqualInt8x16
+ OpGreaterEqualInt8x32
+ OpGreaterEqualInt8x64
+ OpGreaterEqualInt16x8
+ OpGreaterEqualInt16x16
+ OpGreaterEqualInt16x32
+ OpGreaterEqualInt32x4
+ OpGreaterEqualInt32x8
+ OpGreaterEqualInt32x16
+ OpGreaterEqualInt64x2
+ OpGreaterEqualInt64x4
+ OpGreaterEqualInt64x8
+ OpGreaterEqualMaskedFloat32x4
OpGreaterEqualMaskedFloat32x8
+ OpGreaterEqualMaskedFloat32x16
+ OpGreaterEqualMaskedFloat64x2
+ OpGreaterEqualMaskedFloat64x4
+ OpGreaterEqualMaskedFloat64x8
+ OpGreaterEqualMaskedInt8x16
+ OpGreaterEqualMaskedInt8x32
+ OpGreaterEqualMaskedInt8x64
+ OpGreaterEqualMaskedInt16x8
+ OpGreaterEqualMaskedInt16x16
+ OpGreaterEqualMaskedInt16x32
+ OpGreaterEqualMaskedInt32x4
+ OpGreaterEqualMaskedInt32x8
+ OpGreaterEqualMaskedInt32x16
+ OpGreaterEqualMaskedInt64x2
+ OpGreaterEqualMaskedInt64x4
+ OpGreaterEqualMaskedInt64x8
+ OpGreaterEqualMaskedUint8x16
+ OpGreaterEqualMaskedUint8x32
+ OpGreaterEqualMaskedUint8x64
+ OpGreaterEqualMaskedUint16x8
+ OpGreaterEqualMaskedUint16x16
+ OpGreaterEqualMaskedUint16x32
+ OpGreaterEqualMaskedUint32x4
+ OpGreaterEqualMaskedUint32x8
+ OpGreaterEqualMaskedUint32x16
+ OpGreaterEqualMaskedUint64x2
+ OpGreaterEqualMaskedUint64x4
+ OpGreaterEqualMaskedUint64x8
+ OpGreaterEqualUint8x16
+ OpGreaterEqualUint8x32
+ OpGreaterEqualUint8x64
+ OpGreaterEqualUint16x8
+ OpGreaterEqualUint16x16
+ OpGreaterEqualUint16x32
+ OpGreaterEqualUint32x4
+ OpGreaterEqualUint32x8
+ OpGreaterEqualUint32x16
+ OpGreaterEqualUint64x2
+ OpGreaterEqualUint64x4
+ OpGreaterEqualUint64x8
+ OpGreaterFloat32x4
+ OpGreaterFloat32x8
+ OpGreaterFloat32x16
+ OpGreaterFloat64x2
+ OpGreaterFloat64x4
+ OpGreaterFloat64x8
+ OpGreaterInt8x16
+ OpGreaterInt8x32
+ OpGreaterInt8x64
+ OpGreaterInt16x8
+ OpGreaterInt16x16
+ OpGreaterInt16x32
+ OpGreaterInt32x4
+ OpGreaterInt32x8
+ OpGreaterInt32x16
+ OpGreaterInt64x2
+ OpGreaterInt64x4
+ OpGreaterInt64x8
+ OpGreaterMaskedFloat32x4
OpGreaterMaskedFloat32x8
+ OpGreaterMaskedFloat32x16
+ OpGreaterMaskedFloat64x2
+ OpGreaterMaskedFloat64x4
+ OpGreaterMaskedFloat64x8
+ OpGreaterMaskedInt8x16
+ OpGreaterMaskedInt8x32
+ OpGreaterMaskedInt8x64
+ OpGreaterMaskedInt16x8
+ OpGreaterMaskedInt16x16
+ OpGreaterMaskedInt16x32
+ OpGreaterMaskedInt32x4
+ OpGreaterMaskedInt32x8
+ OpGreaterMaskedInt32x16
+ OpGreaterMaskedInt64x2
+ OpGreaterMaskedInt64x4
+ OpGreaterMaskedInt64x8
+ OpGreaterMaskedUint8x16
+ OpGreaterMaskedUint8x32
+ OpGreaterMaskedUint8x64
+ OpGreaterMaskedUint16x8
+ OpGreaterMaskedUint16x16
+ OpGreaterMaskedUint16x32
+ OpGreaterMaskedUint32x4
+ OpGreaterMaskedUint32x8
+ OpGreaterMaskedUint32x16
+ OpGreaterMaskedUint64x2
+ OpGreaterMaskedUint64x4
+ OpGreaterMaskedUint64x8
+ OpGreaterUint8x16
+ OpGreaterUint8x32
+ OpGreaterUint8x64
+ OpGreaterUint16x8
+ OpGreaterUint16x16
+ OpGreaterUint16x32
+ OpGreaterUint32x4
+ OpGreaterUint32x8
+ OpGreaterUint32x16
+ OpGreaterUint64x2
+ OpGreaterUint64x4
+ OpGreaterUint64x8
+ OpIsNanFloat32x4
OpIsNanFloat32x8
+ OpIsNanFloat32x16
+ OpIsNanFloat64x2
+ OpIsNanFloat64x4
+ OpIsNanFloat64x8
+ OpIsNanMaskedFloat32x4
OpIsNanMaskedFloat32x8
- OpLessFloat32x8
+ OpIsNanMaskedFloat32x16
+ OpIsNanMaskedFloat64x2
+ OpIsNanMaskedFloat64x4
+ OpIsNanMaskedFloat64x8
+ OpLessEqualFloat32x4
OpLessEqualFloat32x8
+ OpLessEqualFloat32x16
+ OpLessEqualFloat64x2
+ OpLessEqualFloat64x4
+ OpLessEqualFloat64x8
+ OpLessEqualInt8x16
+ OpLessEqualInt8x32
+ OpLessEqualInt8x64
+ OpLessEqualInt16x8
+ OpLessEqualInt16x16
+ OpLessEqualInt16x32
+ OpLessEqualInt32x4
+ OpLessEqualInt32x8
+ OpLessEqualInt32x16
+ OpLessEqualInt64x2
+ OpLessEqualInt64x4
+ OpLessEqualInt64x8
+ OpLessEqualMaskedFloat32x4
OpLessEqualMaskedFloat32x8
+ OpLessEqualMaskedFloat32x16
+ OpLessEqualMaskedFloat64x2
+ OpLessEqualMaskedFloat64x4
+ OpLessEqualMaskedFloat64x8
+ OpLessEqualMaskedInt8x16
+ OpLessEqualMaskedInt8x32
+ OpLessEqualMaskedInt8x64
+ OpLessEqualMaskedInt16x8
+ OpLessEqualMaskedInt16x16
+ OpLessEqualMaskedInt16x32
+ OpLessEqualMaskedInt32x4
+ OpLessEqualMaskedInt32x8
+ OpLessEqualMaskedInt32x16
+ OpLessEqualMaskedInt64x2
+ OpLessEqualMaskedInt64x4
+ OpLessEqualMaskedInt64x8
+ OpLessEqualMaskedUint8x16
+ OpLessEqualMaskedUint8x32
+ OpLessEqualMaskedUint8x64
+ OpLessEqualMaskedUint16x8
+ OpLessEqualMaskedUint16x16
+ OpLessEqualMaskedUint16x32
+ OpLessEqualMaskedUint32x4
+ OpLessEqualMaskedUint32x8
+ OpLessEqualMaskedUint32x16
+ OpLessEqualMaskedUint64x2
+ OpLessEqualMaskedUint64x4
+ OpLessEqualMaskedUint64x8
+ OpLessEqualUint8x16
+ OpLessEqualUint8x32
+ OpLessEqualUint8x64
+ OpLessEqualUint16x8
+ OpLessEqualUint16x16
+ OpLessEqualUint16x32
+ OpLessEqualUint32x4
+ OpLessEqualUint32x8
+ OpLessEqualUint32x16
+ OpLessEqualUint64x2
+ OpLessEqualUint64x4
+ OpLessEqualUint64x8
+ OpLessFloat32x4
+ OpLessFloat32x8
+ OpLessFloat32x16
+ OpLessFloat64x2
+ OpLessFloat64x4
+ OpLessFloat64x8
+ OpLessInt8x16
+ OpLessInt8x32
+ OpLessInt8x64
+ OpLessInt16x8
+ OpLessInt16x16
+ OpLessInt16x32
+ OpLessInt32x4
+ OpLessInt32x8
+ OpLessInt32x16
+ OpLessInt64x2
+ OpLessInt64x4
+ OpLessInt64x8
+ OpLessMaskedFloat32x4
OpLessMaskedFloat32x8
+ OpLessMaskedFloat32x16
+ OpLessMaskedFloat64x2
+ OpLessMaskedFloat64x4
+ OpLessMaskedFloat64x8
+ OpLessMaskedInt8x16
+ OpLessMaskedInt8x32
+ OpLessMaskedInt8x64
+ OpLessMaskedInt16x8
+ OpLessMaskedInt16x16
+ OpLessMaskedInt16x32
+ OpLessMaskedInt32x4
+ OpLessMaskedInt32x8
+ OpLessMaskedInt32x16
+ OpLessMaskedInt64x2
+ OpLessMaskedInt64x4
+ OpLessMaskedInt64x8
+ OpLessMaskedUint8x16
+ OpLessMaskedUint8x32
+ OpLessMaskedUint8x64
+ OpLessMaskedUint16x8
+ OpLessMaskedUint16x16
+ OpLessMaskedUint16x32
+ OpLessMaskedUint32x4
+ OpLessMaskedUint32x8
+ OpLessMaskedUint32x16
+ OpLessMaskedUint64x2
+ OpLessMaskedUint64x4
+ OpLessMaskedUint64x8
+ OpLessUint8x16
+ OpLessUint8x32
+ OpLessUint8x64
+ OpLessUint16x8
+ OpLessUint16x16
+ OpLessUint16x32
+ OpLessUint32x4
+ OpLessUint32x8
+ OpLessUint32x16
+ OpLessUint64x2
+ OpLessUint64x4
+ OpLessUint64x8
+ OpMaxFloat32x4
OpMaxFloat32x8
+ OpMaxFloat32x16
+ OpMaxFloat64x2
+ OpMaxFloat64x4
+ OpMaxFloat64x8
+ OpMaxInt8x16
+ OpMaxInt8x32
+ OpMaxInt8x64
+ OpMaxInt16x8
+ OpMaxInt16x16
+ OpMaxInt16x32
+ OpMaxInt32x4
+ OpMaxInt32x8
+ OpMaxInt32x16
+ OpMaxInt64x2
+ OpMaxInt64x4
+ OpMaxInt64x8
+ OpMaxMaskedFloat32x4
OpMaxMaskedFloat32x8
+ OpMaxMaskedFloat32x16
+ OpMaxMaskedFloat64x2
+ OpMaxMaskedFloat64x4
+ OpMaxMaskedFloat64x8
+ OpMaxMaskedInt8x16
+ OpMaxMaskedInt8x32
+ OpMaxMaskedInt8x64
+ OpMaxMaskedInt16x8
+ OpMaxMaskedInt16x16
+ OpMaxMaskedInt16x32
+ OpMaxMaskedInt32x4
+ OpMaxMaskedInt32x8
+ OpMaxMaskedInt32x16
+ OpMaxMaskedInt64x2
+ OpMaxMaskedInt64x4
+ OpMaxMaskedInt64x8
+ OpMaxMaskedUint8x16
+ OpMaxMaskedUint8x32
+ OpMaxMaskedUint8x64
+ OpMaxMaskedUint16x8
+ OpMaxMaskedUint16x16
+ OpMaxMaskedUint16x32
+ OpMaxMaskedUint32x4
+ OpMaxMaskedUint32x8
+ OpMaxMaskedUint32x16
+ OpMaxMaskedUint64x2
+ OpMaxMaskedUint64x4
+ OpMaxMaskedUint64x8
+ OpMaxUint8x16
+ OpMaxUint8x32
+ OpMaxUint8x64
+ OpMaxUint16x8
+ OpMaxUint16x16
+ OpMaxUint16x32
+ OpMaxUint32x4
+ OpMaxUint32x8
+ OpMaxUint32x16
+ OpMaxUint64x2
+ OpMaxUint64x4
+ OpMaxUint64x8
+ OpMinFloat32x4
OpMinFloat32x8
+ OpMinFloat32x16
+ OpMinFloat64x2
+ OpMinFloat64x4
+ OpMinFloat64x8
+ OpMinInt8x16
+ OpMinInt8x32
+ OpMinInt8x64
+ OpMinInt16x8
+ OpMinInt16x16
+ OpMinInt16x32
+ OpMinInt32x4
+ OpMinInt32x8
+ OpMinInt32x16
+ OpMinInt64x2
+ OpMinInt64x4
+ OpMinInt64x8
+ OpMinMaskedFloat32x4
OpMinMaskedFloat32x8
- OpMulFloat32x8
+ OpMinMaskedFloat32x16
+ OpMinMaskedFloat64x2
+ OpMinMaskedFloat64x4
+ OpMinMaskedFloat64x8
+ OpMinMaskedInt8x16
+ OpMinMaskedInt8x32
+ OpMinMaskedInt8x64
+ OpMinMaskedInt16x8
+ OpMinMaskedInt16x16
+ OpMinMaskedInt16x32
+ OpMinMaskedInt32x4
+ OpMinMaskedInt32x8
+ OpMinMaskedInt32x16
+ OpMinMaskedInt64x2
+ OpMinMaskedInt64x4
+ OpMinMaskedInt64x8
+ OpMinMaskedUint8x16
+ OpMinMaskedUint8x32
+ OpMinMaskedUint8x64
+ OpMinMaskedUint16x8
+ OpMinMaskedUint16x16
+ OpMinMaskedUint16x32
+ OpMinMaskedUint32x4
+ OpMinMaskedUint32x8
+ OpMinMaskedUint32x16
+ OpMinMaskedUint64x2
+ OpMinMaskedUint64x4
+ OpMinMaskedUint64x8
+ OpMinUint8x16
+ OpMinUint8x32
+ OpMinUint8x64
+ OpMinUint16x8
+ OpMinUint16x16
+ OpMinUint16x32
+ OpMinUint32x4
+ OpMinUint32x8
+ OpMinUint32x16
+ OpMinUint64x2
+ OpMinUint64x4
+ OpMinUint64x8
+ OpMulByPowOf2Float32x4
OpMulByPowOf2Float32x8
+ OpMulByPowOf2Float32x16
+ OpMulByPowOf2Float64x2
+ OpMulByPowOf2Float64x4
+ OpMulByPowOf2Float64x8
+ OpMulByPowOf2MaskedFloat32x4
OpMulByPowOf2MaskedFloat32x8
- OpMulMaskedFloat32x8
- OpNotEqualFloat32x8
- OpNotEqualMaskedFloat32x8
- OpPairwiseAddFloat32x8
- OpPairwiseSubFloat32x8
- OpRoundFloat32x8
- OpSqrtFloat32x8
- OpSqrtMaskedFloat32x8
- OpSubFloat32x8
- OpSubMaskedFloat32x8
- OpTruncFloat32x8
- OpAddFloat64x2
- OpAddMaskedFloat64x2
- OpAddSubFloat64x2
- OpApproximateReciprocalFloat64x2
- OpApproximateReciprocalMaskedFloat64x2
- OpApproximateReciprocalOfSqrtFloat64x2
- OpApproximateReciprocalOfSqrtMaskedFloat64x2
- OpCeilFloat64x2
- OpCompressFloat64x2
- OpDivFloat64x2
- OpDivMaskedFloat64x2
- OpDotProdBroadcastFloat64x2
- OpEqualFloat64x2
- OpEqualMaskedFloat64x2
- OpFloorFloat64x2
- OpFusedMultiplyAddFloat64x2
- OpFusedMultiplyAddMaskedFloat64x2
- OpFusedMultiplyAddSubFloat64x2
- OpFusedMultiplyAddSubMaskedFloat64x2
- OpFusedMultiplySubAddFloat64x2
- OpFusedMultiplySubAddMaskedFloat64x2
- OpGreaterFloat64x2
- OpGreaterEqualFloat64x2
- OpGreaterEqualMaskedFloat64x2
- OpGreaterMaskedFloat64x2
- OpIsNanFloat64x2
- OpIsNanMaskedFloat64x2
- OpLessFloat64x2
- OpLessEqualFloat64x2
- OpLessEqualMaskedFloat64x2
- OpLessMaskedFloat64x2
- OpMaxFloat64x2
- OpMaxMaskedFloat64x2
- OpMinFloat64x2
- OpMinMaskedFloat64x2
- OpMulFloat64x2
- OpMulByPowOf2Float64x2
+ OpMulByPowOf2MaskedFloat32x16
OpMulByPowOf2MaskedFloat64x2
- OpMulMaskedFloat64x2
- OpNotEqualFloat64x2
- OpNotEqualMaskedFloat64x2
- OpPairwiseAddFloat64x2
- OpPairwiseSubFloat64x2
- OpRoundFloat64x2
- OpSqrtFloat64x2
- OpSqrtMaskedFloat64x2
- OpSubFloat64x2
- OpSubMaskedFloat64x2
- OpTruncFloat64x2
- OpAddFloat64x4
- OpAddMaskedFloat64x4
- OpAddSubFloat64x4
- OpApproximateReciprocalFloat64x4
- OpApproximateReciprocalMaskedFloat64x4
- OpApproximateReciprocalOfSqrtFloat64x4
- OpApproximateReciprocalOfSqrtMaskedFloat64x4
- OpCeilFloat64x4
- OpCompressFloat64x4
- OpDivFloat64x4
- OpDivMaskedFloat64x4
- OpEqualFloat64x4
- OpEqualMaskedFloat64x4
- OpFloorFloat64x4
- OpFusedMultiplyAddFloat64x4
- OpFusedMultiplyAddMaskedFloat64x4
- OpFusedMultiplyAddSubFloat64x4
- OpFusedMultiplyAddSubMaskedFloat64x4
- OpFusedMultiplySubAddFloat64x4
- OpFusedMultiplySubAddMaskedFloat64x4
- OpGreaterFloat64x4
- OpGreaterEqualFloat64x4
- OpGreaterEqualMaskedFloat64x4
- OpGreaterMaskedFloat64x4
- OpIsNanFloat64x4
- OpIsNanMaskedFloat64x4
- OpLessFloat64x4
- OpLessEqualFloat64x4
- OpLessEqualMaskedFloat64x4
- OpLessMaskedFloat64x4
- OpMaxFloat64x4
- OpMaxMaskedFloat64x4
- OpMinFloat64x4
- OpMinMaskedFloat64x4
- OpMulFloat64x4
- OpMulByPowOf2Float64x4
OpMulByPowOf2MaskedFloat64x4
- OpMulMaskedFloat64x4
- OpNotEqualFloat64x4
- OpNotEqualMaskedFloat64x4
- OpPairwiseAddFloat64x4
- OpPairwiseSubFloat64x4
- OpRoundFloat64x4
- OpSqrtFloat64x4
- OpSqrtMaskedFloat64x4
- OpSubFloat64x4
- OpSubMaskedFloat64x4
- OpTruncFloat64x4
- OpAddFloat64x8
- OpAddMaskedFloat64x8
- OpApproximateReciprocalFloat64x8
- OpApproximateReciprocalMaskedFloat64x8
- OpApproximateReciprocalOfSqrtFloat64x8
- OpApproximateReciprocalOfSqrtMaskedFloat64x8
- OpCompressFloat64x8
- OpDivFloat64x8
- OpDivMaskedFloat64x8
- OpEqualFloat64x8
- OpEqualMaskedFloat64x8
- OpFusedMultiplyAddFloat64x8
- OpFusedMultiplyAddMaskedFloat64x8
- OpFusedMultiplyAddSubFloat64x8
- OpFusedMultiplyAddSubMaskedFloat64x8
- OpFusedMultiplySubAddFloat64x8
- OpFusedMultiplySubAddMaskedFloat64x8
- OpGreaterFloat64x8
- OpGreaterEqualFloat64x8
- OpGreaterEqualMaskedFloat64x8
- OpGreaterMaskedFloat64x8
- OpIsNanFloat64x8
- OpIsNanMaskedFloat64x8
- OpLessFloat64x8
- OpLessEqualFloat64x8
- OpLessEqualMaskedFloat64x8
- OpLessMaskedFloat64x8
- OpMaxFloat64x8
- OpMaxMaskedFloat64x8
- OpMinFloat64x8
- OpMinMaskedFloat64x8
- OpMulFloat64x8
- OpMulByPowOf2Float64x8
OpMulByPowOf2MaskedFloat64x8
- OpMulMaskedFloat64x8
- OpNotEqualFloat64x8
- OpNotEqualMaskedFloat64x8
- OpSqrtFloat64x8
- OpSqrtMaskedFloat64x8
- OpSubFloat64x8
- OpSubMaskedFloat64x8
- OpAbsoluteInt16x16
- OpAbsoluteMaskedInt16x16
- OpAddInt16x16
- OpAddMaskedInt16x16
- OpAndInt16x16
- OpAndNotInt16x16
- OpCompressInt16x16
- OpEqualInt16x16
- OpEqualMaskedInt16x16
- OpGreaterInt16x16
- OpGreaterEqualInt16x16
- OpGreaterEqualMaskedInt16x16
- OpGreaterMaskedInt16x16
- OpLessInt16x16
- OpLessEqualInt16x16
- OpLessEqualMaskedInt16x16
- OpLessMaskedInt16x16
- OpMaxInt16x16
- OpMaxMaskedInt16x16
- OpMinInt16x16
- OpMinMaskedInt16x16
+ OpMulEvenWidenInt32x4
+ OpMulEvenWidenInt32x8
+ OpMulEvenWidenInt64x2
+ OpMulEvenWidenInt64x4
+ OpMulEvenWidenInt64x8
+ OpMulEvenWidenMaskedInt64x2
+ OpMulEvenWidenMaskedInt64x4
+ OpMulEvenWidenMaskedInt64x8
+ OpMulEvenWidenMaskedUint64x2
+ OpMulEvenWidenMaskedUint64x4
+ OpMulEvenWidenMaskedUint64x8
+ OpMulEvenWidenUint32x4
+ OpMulEvenWidenUint32x8
+ OpMulEvenWidenUint64x2
+ OpMulEvenWidenUint64x4
+ OpMulEvenWidenUint64x8
+ OpMulFloat32x4
+ OpMulFloat32x8
+ OpMulFloat32x16
+ OpMulFloat64x2
+ OpMulFloat64x4
+ OpMulFloat64x8
+ OpMulHighInt16x8
OpMulHighInt16x16
+ OpMulHighInt16x32
+ OpMulHighMaskedInt16x8
OpMulHighMaskedInt16x16
+ OpMulHighMaskedInt16x32
+ OpMulHighMaskedUint16x8
+ OpMulHighMaskedUint16x16
+ OpMulHighMaskedUint16x32
+ OpMulHighUint16x8
+ OpMulHighUint16x16
+ OpMulHighUint16x32
+ OpMulLowInt16x8
OpMulLowInt16x16
+ OpMulLowInt16x32
+ OpMulLowInt32x4
+ OpMulLowInt32x8
+ OpMulLowInt32x16
+ OpMulLowInt64x2
+ OpMulLowInt64x4
+ OpMulLowInt64x8
+ OpMulLowMaskedInt16x8
OpMulLowMaskedInt16x16
+ OpMulLowMaskedInt16x32
+ OpMulLowMaskedInt32x4
+ OpMulLowMaskedInt32x8
+ OpMulLowMaskedInt32x16
+ OpMulLowMaskedInt64x2
+ OpMulLowMaskedInt64x4
+ OpMulLowMaskedInt64x8
+ OpMulMaskedFloat32x4
+ OpMulMaskedFloat32x8
+ OpMulMaskedFloat32x16
+ OpMulMaskedFloat64x2
+ OpMulMaskedFloat64x4
+ OpMulMaskedFloat64x8
+ OpNotEqualFloat32x4
+ OpNotEqualFloat32x8
+ OpNotEqualFloat32x16
+ OpNotEqualFloat64x2
+ OpNotEqualFloat64x4
+ OpNotEqualFloat64x8
+ OpNotEqualInt8x16
+ OpNotEqualInt8x32
+ OpNotEqualInt8x64
+ OpNotEqualInt16x8
OpNotEqualInt16x16
+ OpNotEqualInt16x32
+ OpNotEqualInt32x4
+ OpNotEqualInt32x8
+ OpNotEqualInt32x16
+ OpNotEqualInt64x2
+ OpNotEqualInt64x4
+ OpNotEqualInt64x8
+ OpNotEqualMaskedFloat32x4
+ OpNotEqualMaskedFloat32x8
+ OpNotEqualMaskedFloat32x16
+ OpNotEqualMaskedFloat64x2
+ OpNotEqualMaskedFloat64x4
+ OpNotEqualMaskedFloat64x8
+ OpNotEqualMaskedInt8x16
+ OpNotEqualMaskedInt8x32
+ OpNotEqualMaskedInt8x64
+ OpNotEqualMaskedInt16x8
OpNotEqualMaskedInt16x16
+ OpNotEqualMaskedInt16x32
+ OpNotEqualMaskedInt32x4
+ OpNotEqualMaskedInt32x8
+ OpNotEqualMaskedInt32x16
+ OpNotEqualMaskedInt64x2
+ OpNotEqualMaskedInt64x4
+ OpNotEqualMaskedInt64x8
+ OpNotEqualMaskedUint8x16
+ OpNotEqualMaskedUint8x32
+ OpNotEqualMaskedUint8x64
+ OpNotEqualMaskedUint16x8
+ OpNotEqualMaskedUint16x16
+ OpNotEqualMaskedUint16x32
+ OpNotEqualMaskedUint32x4
+ OpNotEqualMaskedUint32x8
+ OpNotEqualMaskedUint32x16
+ OpNotEqualMaskedUint64x2
+ OpNotEqualMaskedUint64x4
+ OpNotEqualMaskedUint64x8
+ OpNotEqualUint8x16
+ OpNotEqualUint8x32
+ OpNotEqualUint8x64
+ OpNotEqualUint16x8
+ OpNotEqualUint16x16
+ OpNotEqualUint16x32
+ OpNotEqualUint32x4
+ OpNotEqualUint32x8
+ OpNotEqualUint32x16
+ OpNotEqualUint64x2
+ OpNotEqualUint64x4
+ OpNotEqualUint64x8
+ OpOrInt8x16
+ OpOrInt8x32
+ OpOrInt16x8
OpOrInt16x16
+ OpOrInt32x4
+ OpOrInt32x8
+ OpOrInt32x16
+ OpOrInt64x2
+ OpOrInt64x4
+ OpOrInt64x8
+ OpOrMaskedInt32x4
+ OpOrMaskedInt32x8
+ OpOrMaskedInt32x16
+ OpOrMaskedInt64x2
+ OpOrMaskedInt64x4
+ OpOrMaskedInt64x8
+ OpOrMaskedUint32x4
+ OpOrMaskedUint32x8
+ OpOrMaskedUint32x16
+ OpOrMaskedUint64x2
+ OpOrMaskedUint64x4
+ OpOrMaskedUint64x8
+ OpOrUint8x16
+ OpOrUint8x32
+ OpOrUint16x8
+ OpOrUint16x16
+ OpOrUint32x4
+ OpOrUint32x8
+ OpOrUint32x16
+ OpOrUint64x2
+ OpOrUint64x4
+ OpOrUint64x8
+ OpPairDotProdAccumulateInt32x4
+ OpPairDotProdAccumulateInt32x8
+ OpPairDotProdAccumulateInt32x16
+ OpPairDotProdAccumulateMaskedInt32x4
+ OpPairDotProdAccumulateMaskedInt32x8
+ OpPairDotProdAccumulateMaskedInt32x16
+ OpPairDotProdInt16x8
OpPairDotProdInt16x16
+ OpPairDotProdInt16x32
+ OpPairDotProdMaskedInt16x8
OpPairDotProdMaskedInt16x16
+ OpPairDotProdMaskedInt16x32
+ OpPairwiseAddFloat32x4
+ OpPairwiseAddFloat32x8
+ OpPairwiseAddFloat64x2
+ OpPairwiseAddFloat64x4
+ OpPairwiseAddInt16x8
OpPairwiseAddInt16x16
+ OpPairwiseAddInt32x4
+ OpPairwiseAddInt32x8
+ OpPairwiseAddUint16x8
+ OpPairwiseAddUint16x16
+ OpPairwiseAddUint32x4
+ OpPairwiseAddUint32x8
+ OpPairwiseSubFloat32x4
+ OpPairwiseSubFloat32x8
+ OpPairwiseSubFloat64x2
+ OpPairwiseSubFloat64x4
+ OpPairwiseSubInt16x8
OpPairwiseSubInt16x16
+ OpPairwiseSubInt32x4
+ OpPairwiseSubInt32x8
+ OpPairwiseSubUint16x8
+ OpPairwiseSubUint16x16
+ OpPairwiseSubUint32x4
+ OpPairwiseSubUint32x8
+ OpPermute2Float32x4
+ OpPermute2Float32x8
+ OpPermute2Float32x16
+ OpPermute2Float64x2
+ OpPermute2Float64x4
+ OpPermute2Float64x8
+ OpPermute2Int8x16
+ OpPermute2Int8x32
+ OpPermute2Int8x64
+ OpPermute2Int16x8
+ OpPermute2Int16x16
+ OpPermute2Int16x32
+ OpPermute2Int32x4
+ OpPermute2Int32x8
+ OpPermute2Int32x16
+ OpPermute2Int64x2
+ OpPermute2Int64x4
+ OpPermute2Int64x8
+ OpPermute2MaskedFloat32x4
+ OpPermute2MaskedFloat32x8
+ OpPermute2MaskedFloat32x16
+ OpPermute2MaskedFloat64x2
+ OpPermute2MaskedFloat64x4
+ OpPermute2MaskedFloat64x8
+ OpPermute2MaskedInt8x16
+ OpPermute2MaskedInt8x32
+ OpPermute2MaskedInt8x64
+ OpPermute2MaskedInt16x8
+ OpPermute2MaskedInt16x16
+ OpPermute2MaskedInt16x32
+ OpPermute2MaskedInt32x4
+ OpPermute2MaskedInt32x8
+ OpPermute2MaskedInt32x16
+ OpPermute2MaskedInt64x2
+ OpPermute2MaskedInt64x4
+ OpPermute2MaskedInt64x8
+ OpPermute2MaskedUint8x16
+ OpPermute2MaskedUint8x32
+ OpPermute2MaskedUint8x64
+ OpPermute2MaskedUint16x8
+ OpPermute2MaskedUint16x16
+ OpPermute2MaskedUint16x32
+ OpPermute2MaskedUint32x4
+ OpPermute2MaskedUint32x8
+ OpPermute2MaskedUint32x16
+ OpPermute2MaskedUint64x2
+ OpPermute2MaskedUint64x4
+ OpPermute2MaskedUint64x8
+ OpPermute2Uint8x16
+ OpPermute2Uint8x32
+ OpPermute2Uint8x64
+ OpPermute2Uint16x8
+ OpPermute2Uint16x16
+ OpPermute2Uint16x32
+ OpPermute2Uint32x4
+ OpPermute2Uint32x8
+ OpPermute2Uint32x16
+ OpPermute2Uint64x2
+ OpPermute2Uint64x4
+ OpPermute2Uint64x8
+ OpPermuteFloat32x8
+ OpPermuteFloat32x16
+ OpPermuteFloat64x4
+ OpPermuteFloat64x8
+ OpPermuteInt8x16
+ OpPermuteInt8x32
+ OpPermuteInt8x64
+ OpPermuteInt16x8
+ OpPermuteInt16x16
+ OpPermuteInt16x32
+ OpPermuteInt32x8
+ OpPermuteInt32x16
+ OpPermuteInt64x4
+ OpPermuteInt64x8
+ OpPermuteMaskedFloat32x8
+ OpPermuteMaskedFloat32x16
+ OpPermuteMaskedFloat64x4
+ OpPermuteMaskedFloat64x8
+ OpPermuteMaskedInt8x16
+ OpPermuteMaskedInt8x32
+ OpPermuteMaskedInt8x64
+ OpPermuteMaskedInt16x8
+ OpPermuteMaskedInt16x16
+ OpPermuteMaskedInt16x32
+ OpPermuteMaskedInt32x8
+ OpPermuteMaskedInt32x16
+ OpPermuteMaskedInt64x4
+ OpPermuteMaskedInt64x8
+ OpPermuteMaskedUint8x16
+ OpPermuteMaskedUint8x32
+ OpPermuteMaskedUint8x64
+ OpPermuteMaskedUint16x8
+ OpPermuteMaskedUint16x16
+ OpPermuteMaskedUint16x32
+ OpPermuteMaskedUint32x8
+ OpPermuteMaskedUint32x16
+ OpPermuteMaskedUint64x4
+ OpPermuteMaskedUint64x8
+ OpPermuteUint8x16
+ OpPermuteUint8x32
+ OpPermuteUint8x64
+ OpPermuteUint16x8
+ OpPermuteUint16x16
+ OpPermuteUint16x32
+ OpPermuteUint32x8
+ OpPermuteUint32x16
+ OpPermuteUint64x4
+ OpPermuteUint64x8
+ OpPopCountInt8x16
+ OpPopCountInt8x32
+ OpPopCountInt8x64
+ OpPopCountInt16x8
OpPopCountInt16x16
- OpPopCountMaskedInt16x16
- OpSaturatedAddInt16x16
- OpSaturatedAddMaskedInt16x16
- OpSaturatedPairwiseAddInt16x16
- OpSaturatedPairwiseSubInt16x16
- OpSaturatedSubInt16x16
- OpSaturatedSubMaskedInt16x16
- OpShiftAllLeftInt16x16
- OpShiftAllLeftMaskedInt16x16
- OpShiftAllRightInt16x16
- OpShiftAllRightMaskedInt16x16
- OpShiftLeftInt16x16
- OpShiftLeftAndFillUpperFromInt16x16
- OpShiftLeftAndFillUpperFromMaskedInt16x16
- OpShiftLeftMaskedInt16x16
- OpShiftRightInt16x16
- OpShiftRightAndFillUpperFromInt16x16
- OpShiftRightAndFillUpperFromMaskedInt16x16
- OpShiftRightMaskedInt16x16
- OpSignInt16x16
- OpSubInt16x16
- OpSubMaskedInt16x16
- OpXorInt16x16
- OpAbsoluteInt16x32
- OpAbsoluteMaskedInt16x32
- OpAddInt16x32
- OpAddMaskedInt16x32
- OpCompressInt16x32
- OpEqualInt16x32
- OpEqualMaskedInt16x32
- OpGreaterInt16x32
- OpGreaterEqualInt16x32
- OpGreaterEqualMaskedInt16x32
- OpGreaterMaskedInt16x32
- OpLessInt16x32
- OpLessEqualInt16x32
- OpLessEqualMaskedInt16x32
- OpLessMaskedInt16x32
- OpMaxInt16x32
- OpMaxMaskedInt16x32
- OpMinInt16x32
- OpMinMaskedInt16x32
- OpMulHighInt16x32
- OpMulHighMaskedInt16x32
- OpMulLowInt16x32
- OpMulLowMaskedInt16x32
- OpNotEqualInt16x32
- OpNotEqualMaskedInt16x32
- OpPairDotProdInt16x32
- OpPairDotProdMaskedInt16x32
OpPopCountInt16x32
+ OpPopCountInt32x4
+ OpPopCountInt32x8
+ OpPopCountInt32x16
+ OpPopCountInt64x2
+ OpPopCountInt64x4
+ OpPopCountInt64x8
+ OpPopCountMaskedInt8x16
+ OpPopCountMaskedInt8x32
+ OpPopCountMaskedInt8x64
+ OpPopCountMaskedInt16x8
+ OpPopCountMaskedInt16x16
OpPopCountMaskedInt16x32
- OpSaturatedAddInt16x32
- OpSaturatedAddMaskedInt16x32
- OpSaturatedSubInt16x32
- OpSaturatedSubMaskedInt16x32
- OpShiftAllLeftInt16x32
- OpShiftAllLeftMaskedInt16x32
- OpShiftAllRightInt16x32
- OpShiftAllRightMaskedInt16x32
- OpShiftLeftInt16x32
- OpShiftLeftAndFillUpperFromInt16x32
- OpShiftLeftAndFillUpperFromMaskedInt16x32
- OpShiftLeftMaskedInt16x32
- OpShiftRightInt16x32
- OpShiftRightAndFillUpperFromInt16x32
- OpShiftRightAndFillUpperFromMaskedInt16x32
- OpShiftRightMaskedInt16x32
- OpSubInt16x32
- OpSubMaskedInt16x32
- OpAbsoluteInt16x8
- OpAbsoluteMaskedInt16x8
- OpAddInt16x8
- OpAddMaskedInt16x8
- OpAndInt16x8
- OpAndNotInt16x8
- OpCompressInt16x8
- OpEqualInt16x8
- OpEqualMaskedInt16x8
- OpGreaterInt16x8
- OpGreaterEqualInt16x8
- OpGreaterEqualMaskedInt16x8
- OpGreaterMaskedInt16x8
- OpLessInt16x8
- OpLessEqualInt16x8
- OpLessEqualMaskedInt16x8
- OpLessMaskedInt16x8
- OpMaxInt16x8
- OpMaxMaskedInt16x8
- OpMinInt16x8
- OpMinMaskedInt16x8
- OpMulHighInt16x8
- OpMulHighMaskedInt16x8
- OpMulLowInt16x8
- OpMulLowMaskedInt16x8
- OpNotEqualInt16x8
- OpNotEqualMaskedInt16x8
- OpOrInt16x8
- OpPairDotProdInt16x8
- OpPairDotProdMaskedInt16x8
- OpPairwiseAddInt16x8
- OpPairwiseSubInt16x8
- OpPopCountInt16x8
- OpPopCountMaskedInt16x8
- OpSaturatedAddInt16x8
- OpSaturatedAddMaskedInt16x8
- OpSaturatedPairwiseAddInt16x8
- OpSaturatedPairwiseSubInt16x8
- OpSaturatedSubInt16x8
- OpSaturatedSubMaskedInt16x8
- OpShiftAllLeftInt16x8
- OpShiftAllLeftMaskedInt16x8
- OpShiftAllRightInt16x8
- OpShiftAllRightMaskedInt16x8
- OpShiftLeftInt16x8
- OpShiftLeftAndFillUpperFromInt16x8
- OpShiftLeftAndFillUpperFromMaskedInt16x8
- OpShiftLeftMaskedInt16x8
- OpShiftRightInt16x8
- OpShiftRightAndFillUpperFromInt16x8
- OpShiftRightAndFillUpperFromMaskedInt16x8
- OpShiftRightMaskedInt16x8
- OpSignInt16x8
- OpSubInt16x8
- OpSubMaskedInt16x8
- OpXorInt16x8
- OpAbsoluteInt32x16
- OpAbsoluteMaskedInt32x16
- OpAddInt32x16
- OpAddMaskedInt32x16
- OpAndInt32x16
- OpAndMaskedInt32x16
- OpAndNotInt32x16
- OpAndNotMaskedInt32x16
- OpCompressInt32x16
- OpEqualInt32x16
- OpEqualMaskedInt32x16
- OpGreaterInt32x16
- OpGreaterEqualInt32x16
- OpGreaterEqualMaskedInt32x16
- OpGreaterMaskedInt32x16
- OpLessInt32x16
- OpLessEqualInt32x16
- OpLessEqualMaskedInt32x16
- OpLessMaskedInt32x16
- OpMaxInt32x16
- OpMaxMaskedInt32x16
- OpMinInt32x16
- OpMinMaskedInt32x16
- OpMulLowInt32x16
- OpMulLowMaskedInt32x16
- OpNotEqualInt32x16
- OpNotEqualMaskedInt32x16
- OpOrInt32x16
- OpOrMaskedInt32x16
- OpPairDotProdAccumulateInt32x16
- OpPairDotProdAccumulateMaskedInt32x16
- OpPopCountInt32x16
+ OpPopCountMaskedInt32x4
+ OpPopCountMaskedInt32x8
OpPopCountMaskedInt32x16
+ OpPopCountMaskedInt64x2
+ OpPopCountMaskedInt64x4
+ OpPopCountMaskedInt64x8
+ OpPopCountMaskedUint8x16
+ OpPopCountMaskedUint8x32
+ OpPopCountMaskedUint8x64
+ OpPopCountMaskedUint16x8
+ OpPopCountMaskedUint16x16
+ OpPopCountMaskedUint16x32
+ OpPopCountMaskedUint32x4
+ OpPopCountMaskedUint32x8
+ OpPopCountMaskedUint32x16
+ OpPopCountMaskedUint64x2
+ OpPopCountMaskedUint64x4
+ OpPopCountMaskedUint64x8
+ OpPopCountUint8x16
+ OpPopCountUint8x32
+ OpPopCountUint8x64
+ OpPopCountUint16x8
+ OpPopCountUint16x16
+ OpPopCountUint16x32
+ OpPopCountUint32x4
+ OpPopCountUint32x8
+ OpPopCountUint32x16
+ OpPopCountUint64x2
+ OpPopCountUint64x4
+ OpPopCountUint64x8
+ OpRotateLeftInt32x4
+ OpRotateLeftInt32x8
OpRotateLeftInt32x16
+ OpRotateLeftInt64x2
+ OpRotateLeftInt64x4
+ OpRotateLeftInt64x8
+ OpRotateLeftMaskedInt32x4
+ OpRotateLeftMaskedInt32x8
OpRotateLeftMaskedInt32x16
+ OpRotateLeftMaskedInt64x2
+ OpRotateLeftMaskedInt64x4
+ OpRotateLeftMaskedInt64x8
+ OpRotateLeftMaskedUint32x4
+ OpRotateLeftMaskedUint32x8
+ OpRotateLeftMaskedUint32x16
+ OpRotateLeftMaskedUint64x2
+ OpRotateLeftMaskedUint64x4
+ OpRotateLeftMaskedUint64x8
+ OpRotateLeftUint32x4
+ OpRotateLeftUint32x8
+ OpRotateLeftUint32x16
+ OpRotateLeftUint64x2
+ OpRotateLeftUint64x4
+ OpRotateLeftUint64x8
+ OpRotateRightInt32x4
+ OpRotateRightInt32x8
OpRotateRightInt32x16
+ OpRotateRightInt64x2
+ OpRotateRightInt64x4
+ OpRotateRightInt64x8
+ OpRotateRightMaskedInt32x4
+ OpRotateRightMaskedInt32x8
OpRotateRightMaskedInt32x16
+ OpRotateRightMaskedInt64x2
+ OpRotateRightMaskedInt64x4
+ OpRotateRightMaskedInt64x8
+ OpRotateRightMaskedUint32x4
+ OpRotateRightMaskedUint32x8
+ OpRotateRightMaskedUint32x16
+ OpRotateRightMaskedUint64x2
+ OpRotateRightMaskedUint64x4
+ OpRotateRightMaskedUint64x8
+ OpRotateRightUint32x4
+ OpRotateRightUint32x8
+ OpRotateRightUint32x16
+ OpRotateRightUint64x2
+ OpRotateRightUint64x4
+ OpRotateRightUint64x8
+ OpRoundFloat32x4
+ OpRoundFloat32x8
+ OpRoundFloat64x2
+ OpRoundFloat64x4
+ OpSaturatedAddInt8x16
+ OpSaturatedAddInt8x32
+ OpSaturatedAddInt8x64
+ OpSaturatedAddInt16x8
+ OpSaturatedAddInt16x16
+ OpSaturatedAddInt16x32
+ OpSaturatedAddMaskedInt8x16
+ OpSaturatedAddMaskedInt8x32
+ OpSaturatedAddMaskedInt8x64
+ OpSaturatedAddMaskedInt16x8
+ OpSaturatedAddMaskedInt16x16
+ OpSaturatedAddMaskedInt16x32
+ OpSaturatedAddMaskedUint8x16
+ OpSaturatedAddMaskedUint8x32
+ OpSaturatedAddMaskedUint8x64
+ OpSaturatedAddMaskedUint16x8
+ OpSaturatedAddMaskedUint16x16
+ OpSaturatedAddMaskedUint16x32
+ OpSaturatedAddUint8x16
+ OpSaturatedAddUint8x32
+ OpSaturatedAddUint8x64
+ OpSaturatedAddUint16x8
+ OpSaturatedAddUint16x16
+ OpSaturatedAddUint16x32
+ OpSaturatedPairDotProdAccumulateInt32x4
+ OpSaturatedPairDotProdAccumulateInt32x8
OpSaturatedPairDotProdAccumulateInt32x16
+ OpSaturatedPairDotProdAccumulateMaskedInt32x4
+ OpSaturatedPairDotProdAccumulateMaskedInt32x8
OpSaturatedPairDotProdAccumulateMaskedInt32x16
+ OpSaturatedPairwiseAddInt16x8
+ OpSaturatedPairwiseAddInt16x16
+ OpSaturatedPairwiseSubInt16x8
+ OpSaturatedPairwiseSubInt16x16
+ OpSaturatedSubInt8x16
+ OpSaturatedSubInt8x32
+ OpSaturatedSubInt8x64
+ OpSaturatedSubInt16x8
+ OpSaturatedSubInt16x16
+ OpSaturatedSubInt16x32
+ OpSaturatedSubMaskedInt8x16
+ OpSaturatedSubMaskedInt8x32
+ OpSaturatedSubMaskedInt8x64
+ OpSaturatedSubMaskedInt16x8
+ OpSaturatedSubMaskedInt16x16
+ OpSaturatedSubMaskedInt16x32
+ OpSaturatedSubMaskedUint8x16
+ OpSaturatedSubMaskedUint8x32
+ OpSaturatedSubMaskedUint8x64
+ OpSaturatedSubMaskedUint16x8
+ OpSaturatedSubMaskedUint16x16
+ OpSaturatedSubMaskedUint16x32
+ OpSaturatedSubUint8x16
+ OpSaturatedSubUint8x32
+ OpSaturatedSubUint8x64
+ OpSaturatedSubUint16x8
+ OpSaturatedSubUint16x16
+ OpSaturatedSubUint16x32
+ OpSaturatedUnsignedSignedPairDotProdMaskedUint8x16
+ OpSaturatedUnsignedSignedPairDotProdMaskedUint8x32
+ OpSaturatedUnsignedSignedPairDotProdMaskedUint8x64
+ OpSaturatedUnsignedSignedPairDotProdUint8x16
+ OpSaturatedUnsignedSignedPairDotProdUint8x32
+ OpSaturatedUnsignedSignedPairDotProdUint8x64
+ OpSaturatedUnsignedSignedQuadDotProdAccumulateInt32x4
+ OpSaturatedUnsignedSignedQuadDotProdAccumulateInt32x8
OpSaturatedUnsignedSignedQuadDotProdAccumulateInt32x16
+ OpSaturatedUnsignedSignedQuadDotProdAccumulateMaskedInt32x4
+ OpSaturatedUnsignedSignedQuadDotProdAccumulateMaskedInt32x8
OpSaturatedUnsignedSignedQuadDotProdAccumulateMaskedInt32x16
+ OpShiftAllLeftInt16x8
+ OpShiftAllLeftInt16x16
+ OpShiftAllLeftInt16x32
+ OpShiftAllLeftInt32x4
+ OpShiftAllLeftInt32x8
OpShiftAllLeftInt32x16
+ OpShiftAllLeftInt64x2
+ OpShiftAllLeftInt64x4
+ OpShiftAllLeftInt64x8
+ OpShiftAllLeftMaskedInt16x8
+ OpShiftAllLeftMaskedInt16x16
+ OpShiftAllLeftMaskedInt16x32
+ OpShiftAllLeftMaskedInt32x4
+ OpShiftAllLeftMaskedInt32x8
OpShiftAllLeftMaskedInt32x16
+ OpShiftAllLeftMaskedInt64x2
+ OpShiftAllLeftMaskedInt64x4
+ OpShiftAllLeftMaskedInt64x8
+ OpShiftAllLeftMaskedUint16x8
+ OpShiftAllLeftMaskedUint16x16
+ OpShiftAllLeftMaskedUint16x32
+ OpShiftAllLeftMaskedUint32x4
+ OpShiftAllLeftMaskedUint32x8
+ OpShiftAllLeftMaskedUint32x16
+ OpShiftAllLeftMaskedUint64x2
+ OpShiftAllLeftMaskedUint64x4
+ OpShiftAllLeftMaskedUint64x8
+ OpShiftAllLeftUint16x8
+ OpShiftAllLeftUint16x16
+ OpShiftAllLeftUint16x32
+ OpShiftAllLeftUint32x4
+ OpShiftAllLeftUint32x8
+ OpShiftAllLeftUint32x16
+ OpShiftAllLeftUint64x2
+ OpShiftAllLeftUint64x4
+ OpShiftAllLeftUint64x8
+ OpShiftAllRightInt16x8
+ OpShiftAllRightInt16x16
+ OpShiftAllRightInt16x32
+ OpShiftAllRightInt32x4
+ OpShiftAllRightInt32x8
OpShiftAllRightInt32x16
+ OpShiftAllRightInt64x2
+ OpShiftAllRightInt64x4
+ OpShiftAllRightInt64x8
+ OpShiftAllRightMaskedInt16x8
+ OpShiftAllRightMaskedInt16x16
+ OpShiftAllRightMaskedInt16x32
+ OpShiftAllRightMaskedInt32x4
+ OpShiftAllRightMaskedInt32x8
OpShiftAllRightMaskedInt32x16
- OpShiftLeftInt32x16
+ OpShiftAllRightMaskedInt64x2
+ OpShiftAllRightMaskedInt64x4
+ OpShiftAllRightMaskedInt64x8
+ OpShiftAllRightMaskedUint16x8
+ OpShiftAllRightMaskedUint16x16
+ OpShiftAllRightMaskedUint16x32
+ OpShiftAllRightMaskedUint32x4
+ OpShiftAllRightMaskedUint32x8
+ OpShiftAllRightMaskedUint32x16
+ OpShiftAllRightMaskedUint64x2
+ OpShiftAllRightMaskedUint64x4
+ OpShiftAllRightMaskedUint64x8
+ OpShiftAllRightUint16x8
+ OpShiftAllRightUint16x16
+ OpShiftAllRightUint16x32
+ OpShiftAllRightUint32x4
+ OpShiftAllRightUint32x8
+ OpShiftAllRightUint32x16
+ OpShiftAllRightUint64x2
+ OpShiftAllRightUint64x4
+ OpShiftAllRightUint64x8
+ OpShiftLeftAndFillUpperFromInt16x8
+ OpShiftLeftAndFillUpperFromInt16x16
+ OpShiftLeftAndFillUpperFromInt16x32
+ OpShiftLeftAndFillUpperFromInt32x4
+ OpShiftLeftAndFillUpperFromInt32x8
OpShiftLeftAndFillUpperFromInt32x16
+ OpShiftLeftAndFillUpperFromInt64x2
+ OpShiftLeftAndFillUpperFromInt64x4
+ OpShiftLeftAndFillUpperFromInt64x8
+ OpShiftLeftAndFillUpperFromMaskedInt16x8
+ OpShiftLeftAndFillUpperFromMaskedInt16x16
+ OpShiftLeftAndFillUpperFromMaskedInt16x32
+ OpShiftLeftAndFillUpperFromMaskedInt32x4
+ OpShiftLeftAndFillUpperFromMaskedInt32x8
OpShiftLeftAndFillUpperFromMaskedInt32x16
- OpShiftLeftMaskedInt32x16
- OpShiftRightInt32x16
- OpShiftRightAndFillUpperFromInt32x16
- OpShiftRightAndFillUpperFromMaskedInt32x16
- OpShiftRightMaskedInt32x16
- OpSubInt32x16
- OpSubMaskedInt32x16
- OpUnsignedSignedQuadDotProdAccumulateInt32x16
- OpUnsignedSignedQuadDotProdAccumulateMaskedInt32x16
- OpXorInt32x16
- OpXorMaskedInt32x16
- OpAbsoluteInt32x4
- OpAbsoluteMaskedInt32x4
- OpAddInt32x4
- OpAddMaskedInt32x4
- OpAndInt32x4
- OpAndMaskedInt32x4
- OpAndNotInt32x4
- OpAndNotMaskedInt32x4
- OpCompressInt32x4
- OpEqualInt32x4
- OpEqualMaskedInt32x4
- OpGreaterInt32x4
- OpGreaterEqualInt32x4
- OpGreaterEqualMaskedInt32x4
- OpGreaterMaskedInt32x4
- OpLessInt32x4
- OpLessEqualInt32x4
- OpLessEqualMaskedInt32x4
- OpLessMaskedInt32x4
- OpMaxInt32x4
- OpMaxMaskedInt32x4
- OpMinInt32x4
- OpMinMaskedInt32x4
- OpMulEvenWidenInt32x4
- OpMulLowInt32x4
- OpMulLowMaskedInt32x4
- OpNotEqualInt32x4
- OpNotEqualMaskedInt32x4
- OpOrInt32x4
- OpOrMaskedInt32x4
- OpPairDotProdAccumulateInt32x4
- OpPairDotProdAccumulateMaskedInt32x4
- OpPairwiseAddInt32x4
- OpPairwiseSubInt32x4
- OpPopCountInt32x4
- OpPopCountMaskedInt32x4
- OpRotateLeftInt32x4
- OpRotateLeftMaskedInt32x4
- OpRotateRightInt32x4
- OpRotateRightMaskedInt32x4
- OpSaturatedPairDotProdAccumulateInt32x4
- OpSaturatedPairDotProdAccumulateMaskedInt32x4
- OpSaturatedUnsignedSignedQuadDotProdAccumulateInt32x4
- OpSaturatedUnsignedSignedQuadDotProdAccumulateMaskedInt32x4
- OpShiftAllLeftInt32x4
- OpShiftAllLeftMaskedInt32x4
- OpShiftAllRightInt32x4
- OpShiftAllRightMaskedInt32x4
+ OpShiftLeftAndFillUpperFromMaskedInt64x2
+ OpShiftLeftAndFillUpperFromMaskedInt64x4
+ OpShiftLeftAndFillUpperFromMaskedInt64x8
+ OpShiftLeftAndFillUpperFromMaskedUint16x8
+ OpShiftLeftAndFillUpperFromMaskedUint16x16
+ OpShiftLeftAndFillUpperFromMaskedUint16x32
+ OpShiftLeftAndFillUpperFromMaskedUint32x4
+ OpShiftLeftAndFillUpperFromMaskedUint32x8
+ OpShiftLeftAndFillUpperFromMaskedUint32x16
+ OpShiftLeftAndFillUpperFromMaskedUint64x2
+ OpShiftLeftAndFillUpperFromMaskedUint64x4
+ OpShiftLeftAndFillUpperFromMaskedUint64x8
+ OpShiftLeftAndFillUpperFromUint16x8
+ OpShiftLeftAndFillUpperFromUint16x16
+ OpShiftLeftAndFillUpperFromUint16x32
+ OpShiftLeftAndFillUpperFromUint32x4
+ OpShiftLeftAndFillUpperFromUint32x8
+ OpShiftLeftAndFillUpperFromUint32x16
+ OpShiftLeftAndFillUpperFromUint64x2
+ OpShiftLeftAndFillUpperFromUint64x4
+ OpShiftLeftAndFillUpperFromUint64x8
+ OpShiftLeftInt16x8
+ OpShiftLeftInt16x16
+ OpShiftLeftInt16x32
OpShiftLeftInt32x4
- OpShiftLeftAndFillUpperFromInt32x4
- OpShiftLeftAndFillUpperFromMaskedInt32x4
+ OpShiftLeftInt32x8
+ OpShiftLeftInt32x16
+ OpShiftLeftInt64x2
+ OpShiftLeftInt64x4
+ OpShiftLeftInt64x8
+ OpShiftLeftMaskedInt16x8
+ OpShiftLeftMaskedInt16x16
+ OpShiftLeftMaskedInt16x32
OpShiftLeftMaskedInt32x4
- OpShiftRightInt32x4
+ OpShiftLeftMaskedInt32x8
+ OpShiftLeftMaskedInt32x16
+ OpShiftLeftMaskedInt64x2
+ OpShiftLeftMaskedInt64x4
+ OpShiftLeftMaskedInt64x8
+ OpShiftLeftMaskedUint16x8
+ OpShiftLeftMaskedUint16x16
+ OpShiftLeftMaskedUint16x32
+ OpShiftLeftMaskedUint32x4
+ OpShiftLeftMaskedUint32x8
+ OpShiftLeftMaskedUint32x16
+ OpShiftLeftMaskedUint64x2
+ OpShiftLeftMaskedUint64x4
+ OpShiftLeftMaskedUint64x8
+ OpShiftLeftUint16x8
+ OpShiftLeftUint16x16
+ OpShiftLeftUint16x32
+ OpShiftLeftUint32x4
+ OpShiftLeftUint32x8
+ OpShiftLeftUint32x16
+ OpShiftLeftUint64x2
+ OpShiftLeftUint64x4
+ OpShiftLeftUint64x8
+ OpShiftRightAndFillUpperFromInt16x8
+ OpShiftRightAndFillUpperFromInt16x16
+ OpShiftRightAndFillUpperFromInt16x32
OpShiftRightAndFillUpperFromInt32x4
+ OpShiftRightAndFillUpperFromInt32x8
+ OpShiftRightAndFillUpperFromInt32x16
+ OpShiftRightAndFillUpperFromInt64x2
+ OpShiftRightAndFillUpperFromInt64x4
+ OpShiftRightAndFillUpperFromInt64x8
+ OpShiftRightAndFillUpperFromMaskedInt16x8
+ OpShiftRightAndFillUpperFromMaskedInt16x16
+ OpShiftRightAndFillUpperFromMaskedInt16x32
OpShiftRightAndFillUpperFromMaskedInt32x4
+ OpShiftRightAndFillUpperFromMaskedInt32x8
+ OpShiftRightAndFillUpperFromMaskedInt32x16
+ OpShiftRightAndFillUpperFromMaskedInt64x2
+ OpShiftRightAndFillUpperFromMaskedInt64x4
+ OpShiftRightAndFillUpperFromMaskedInt64x8
+ OpShiftRightAndFillUpperFromMaskedUint16x8
+ OpShiftRightAndFillUpperFromMaskedUint16x16
+ OpShiftRightAndFillUpperFromMaskedUint16x32
+ OpShiftRightAndFillUpperFromMaskedUint32x4
+ OpShiftRightAndFillUpperFromMaskedUint32x8
+ OpShiftRightAndFillUpperFromMaskedUint32x16
+ OpShiftRightAndFillUpperFromMaskedUint64x2
+ OpShiftRightAndFillUpperFromMaskedUint64x4
+ OpShiftRightAndFillUpperFromMaskedUint64x8
+ OpShiftRightAndFillUpperFromUint16x8
+ OpShiftRightAndFillUpperFromUint16x16
+ OpShiftRightAndFillUpperFromUint16x32
+ OpShiftRightAndFillUpperFromUint32x4
+ OpShiftRightAndFillUpperFromUint32x8
+ OpShiftRightAndFillUpperFromUint32x16
+ OpShiftRightAndFillUpperFromUint64x2
+ OpShiftRightAndFillUpperFromUint64x4
+ OpShiftRightAndFillUpperFromUint64x8
+ OpShiftRightInt16x8
+ OpShiftRightInt16x16
+ OpShiftRightInt16x32
+ OpShiftRightInt32x4
+ OpShiftRightInt32x8
+ OpShiftRightInt32x16
+ OpShiftRightInt64x2
+ OpShiftRightInt64x4
+ OpShiftRightInt64x8
+ OpShiftRightMaskedInt16x8
+ OpShiftRightMaskedInt16x16
+ OpShiftRightMaskedInt16x32
OpShiftRightMaskedInt32x4
+ OpShiftRightMaskedInt32x8
+ OpShiftRightMaskedInt32x16
+ OpShiftRightMaskedInt64x2
+ OpShiftRightMaskedInt64x4
+ OpShiftRightMaskedInt64x8
+ OpShiftRightMaskedUint16x8
+ OpShiftRightMaskedUint16x16
+ OpShiftRightMaskedUint16x32
+ OpShiftRightMaskedUint32x4
+ OpShiftRightMaskedUint32x8
+ OpShiftRightMaskedUint32x16
+ OpShiftRightMaskedUint64x2
+ OpShiftRightMaskedUint64x4
+ OpShiftRightMaskedUint64x8
+ OpShiftRightUint16x8
+ OpShiftRightUint16x16
+ OpShiftRightUint16x32
+ OpShiftRightUint32x4
+ OpShiftRightUint32x8
+ OpShiftRightUint32x16
+ OpShiftRightUint64x2
+ OpShiftRightUint64x4
+ OpShiftRightUint64x8
+ OpSignInt8x16
+ OpSignInt8x32
+ OpSignInt16x8
+ OpSignInt16x16
OpSignInt32x4
- OpSubInt32x4
- OpSubMaskedInt32x4
- OpUnsignedSignedQuadDotProdAccumulateInt32x4
- OpUnsignedSignedQuadDotProdAccumulateMaskedInt32x4
- OpXorInt32x4
- OpXorMaskedInt32x4
- OpAbsoluteInt32x8
- OpAbsoluteMaskedInt32x8
- OpAddInt32x8
- OpAddMaskedInt32x8
- OpAndInt32x8
- OpAndMaskedInt32x8
- OpAndNotInt32x8
- OpAndNotMaskedInt32x8
- OpCompressInt32x8
- OpEqualInt32x8
- OpEqualMaskedInt32x8
- OpGreaterInt32x8
- OpGreaterEqualInt32x8
- OpGreaterEqualMaskedInt32x8
- OpGreaterMaskedInt32x8
- OpLessInt32x8
- OpLessEqualInt32x8
- OpLessEqualMaskedInt32x8
- OpLessMaskedInt32x8
- OpMaxInt32x8
- OpMaxMaskedInt32x8
- OpMinInt32x8
- OpMinMaskedInt32x8
- OpMulEvenWidenInt32x8
- OpMulLowInt32x8
- OpMulLowMaskedInt32x8
- OpNotEqualInt32x8
- OpNotEqualMaskedInt32x8
- OpOrInt32x8
- OpOrMaskedInt32x8
- OpPairDotProdAccumulateInt32x8
- OpPairDotProdAccumulateMaskedInt32x8
- OpPairwiseAddInt32x8
- OpPairwiseSubInt32x8
- OpPopCountInt32x8
- OpPopCountMaskedInt32x8
- OpRotateLeftInt32x8
- OpRotateLeftMaskedInt32x8
- OpRotateRightInt32x8
- OpRotateRightMaskedInt32x8
- OpSaturatedPairDotProdAccumulateInt32x8
- OpSaturatedPairDotProdAccumulateMaskedInt32x8
- OpSaturatedUnsignedSignedQuadDotProdAccumulateInt32x8
- OpSaturatedUnsignedSignedQuadDotProdAccumulateMaskedInt32x8
- OpShiftAllLeftInt32x8
- OpShiftAllLeftMaskedInt32x8
- OpShiftAllRightInt32x8
- OpShiftAllRightMaskedInt32x8
- OpShiftLeftInt32x8
- OpShiftLeftAndFillUpperFromInt32x8
- OpShiftLeftAndFillUpperFromMaskedInt32x8
- OpShiftLeftMaskedInt32x8
- OpShiftRightInt32x8
- OpShiftRightAndFillUpperFromInt32x8
- OpShiftRightAndFillUpperFromMaskedInt32x8
- OpShiftRightMaskedInt32x8
OpSignInt32x8
+ OpSqrtFloat32x4
+ OpSqrtFloat32x8
+ OpSqrtFloat32x16
+ OpSqrtFloat64x2
+ OpSqrtFloat64x4
+ OpSqrtFloat64x8
+ OpSqrtMaskedFloat32x4
+ OpSqrtMaskedFloat32x8
+ OpSqrtMaskedFloat32x16
+ OpSqrtMaskedFloat64x2
+ OpSqrtMaskedFloat64x4
+ OpSqrtMaskedFloat64x8
+ OpSubFloat32x4
+ OpSubFloat32x8
+ OpSubFloat32x16
+ OpSubFloat64x2
+ OpSubFloat64x4
+ OpSubFloat64x8
+ OpSubInt8x16
+ OpSubInt8x32
+ OpSubInt8x64
+ OpSubInt16x8
+ OpSubInt16x16
+ OpSubInt16x32
+ OpSubInt32x4
OpSubInt32x8
- OpSubMaskedInt32x8
- OpUnsignedSignedQuadDotProdAccumulateInt32x8
- OpUnsignedSignedQuadDotProdAccumulateMaskedInt32x8
- OpXorInt32x8
- OpXorMaskedInt32x8
- OpAbsoluteInt64x2
- OpAbsoluteMaskedInt64x2
- OpAddInt64x2
- OpAddMaskedInt64x2
- OpAndInt64x2
- OpAndMaskedInt64x2
- OpAndNotInt64x2
- OpAndNotMaskedInt64x2
- OpCompressInt64x2
- OpEqualInt64x2
- OpEqualMaskedInt64x2
- OpGreaterInt64x2
- OpGreaterEqualInt64x2
- OpGreaterEqualMaskedInt64x2
- OpGreaterMaskedInt64x2
- OpLessInt64x2
- OpLessEqualInt64x2
- OpLessEqualMaskedInt64x2
- OpLessMaskedInt64x2
- OpMaxInt64x2
- OpMaxMaskedInt64x2
- OpMinInt64x2
- OpMinMaskedInt64x2
- OpMulEvenWidenInt64x2
- OpMulEvenWidenMaskedInt64x2
- OpMulLowInt64x2
- OpMulLowMaskedInt64x2
- OpNotEqualInt64x2
- OpNotEqualMaskedInt64x2
- OpOrInt64x2
- OpOrMaskedInt64x2
- OpPopCountInt64x2
- OpPopCountMaskedInt64x2
- OpRotateLeftInt64x2
- OpRotateLeftMaskedInt64x2
- OpRotateRightInt64x2
- OpRotateRightMaskedInt64x2
- OpShiftAllLeftInt64x2
- OpShiftAllLeftMaskedInt64x2
- OpShiftAllRightInt64x2
- OpShiftAllRightMaskedInt64x2
- OpShiftLeftInt64x2
- OpShiftLeftAndFillUpperFromInt64x2
- OpShiftLeftAndFillUpperFromMaskedInt64x2
- OpShiftLeftMaskedInt64x2
- OpShiftRightInt64x2
- OpShiftRightAndFillUpperFromInt64x2
- OpShiftRightAndFillUpperFromMaskedInt64x2
- OpShiftRightMaskedInt64x2
+ OpSubInt32x16
OpSubInt64x2
- OpSubMaskedInt64x2
- OpXorInt64x2
- OpXorMaskedInt64x2
- OpAbsoluteInt64x4
- OpAbsoluteMaskedInt64x4
- OpAddInt64x4
- OpAddMaskedInt64x4
- OpAndInt64x4
- OpAndMaskedInt64x4
- OpAndNotInt64x4
- OpAndNotMaskedInt64x4
- OpCompressInt64x4
- OpEqualInt64x4
- OpEqualMaskedInt64x4
- OpGreaterInt64x4
- OpGreaterEqualInt64x4
- OpGreaterEqualMaskedInt64x4
- OpGreaterMaskedInt64x4
- OpLessInt64x4
- OpLessEqualInt64x4
- OpLessEqualMaskedInt64x4
- OpLessMaskedInt64x4
- OpMaxInt64x4
- OpMaxMaskedInt64x4
- OpMinInt64x4
- OpMinMaskedInt64x4
- OpMulEvenWidenInt64x4
- OpMulEvenWidenMaskedInt64x4
- OpMulLowInt64x4
- OpMulLowMaskedInt64x4
- OpNotEqualInt64x4
- OpNotEqualMaskedInt64x4
- OpOrInt64x4
- OpOrMaskedInt64x4
- OpPopCountInt64x4
- OpPopCountMaskedInt64x4
- OpRotateLeftInt64x4
- OpRotateLeftMaskedInt64x4
- OpRotateRightInt64x4
- OpRotateRightMaskedInt64x4
- OpShiftAllLeftInt64x4
- OpShiftAllLeftMaskedInt64x4
- OpShiftAllRightInt64x4
- OpShiftAllRightMaskedInt64x4
- OpShiftLeftInt64x4
- OpShiftLeftAndFillUpperFromInt64x4
- OpShiftLeftAndFillUpperFromMaskedInt64x4
- OpShiftLeftMaskedInt64x4
- OpShiftRightInt64x4
- OpShiftRightAndFillUpperFromInt64x4
- OpShiftRightAndFillUpperFromMaskedInt64x4
- OpShiftRightMaskedInt64x4
OpSubInt64x4
- OpSubMaskedInt64x4
- OpXorInt64x4
- OpXorMaskedInt64x4
- OpAbsoluteInt64x8
- OpAbsoluteMaskedInt64x8
- OpAddInt64x8
- OpAddMaskedInt64x8
- OpAndInt64x8
- OpAndMaskedInt64x8
- OpAndNotInt64x8
- OpAndNotMaskedInt64x8
- OpCompressInt64x8
- OpEqualInt64x8
- OpEqualMaskedInt64x8
- OpGreaterInt64x8
- OpGreaterEqualInt64x8
- OpGreaterEqualMaskedInt64x8
- OpGreaterMaskedInt64x8
- OpLessInt64x8
- OpLessEqualInt64x8
- OpLessEqualMaskedInt64x8
- OpLessMaskedInt64x8
- OpMaxInt64x8
- OpMaxMaskedInt64x8
- OpMinInt64x8
- OpMinMaskedInt64x8
- OpMulEvenWidenInt64x8
- OpMulEvenWidenMaskedInt64x8
- OpMulLowInt64x8
- OpMulLowMaskedInt64x8
- OpNotEqualInt64x8
- OpNotEqualMaskedInt64x8
- OpOrInt64x8
- OpOrMaskedInt64x8
- OpPopCountInt64x8
- OpPopCountMaskedInt64x8
- OpRotateLeftInt64x8
- OpRotateLeftMaskedInt64x8
- OpRotateRightInt64x8
- OpRotateRightMaskedInt64x8
- OpShiftAllLeftInt64x8
- OpShiftAllLeftMaskedInt64x8
- OpShiftAllRightInt64x8
- OpShiftAllRightMaskedInt64x8
- OpShiftLeftInt64x8
- OpShiftLeftAndFillUpperFromInt64x8
- OpShiftLeftAndFillUpperFromMaskedInt64x8
- OpShiftLeftMaskedInt64x8
- OpShiftRightInt64x8
- OpShiftRightAndFillUpperFromInt64x8
- OpShiftRightAndFillUpperFromMaskedInt64x8
- OpShiftRightMaskedInt64x8
OpSubInt64x8
- OpSubMaskedInt64x8
- OpXorInt64x8
- OpXorMaskedInt64x8
- OpAbsoluteInt8x16
- OpAbsoluteMaskedInt8x16
- OpAddInt8x16
- OpAddMaskedInt8x16
- OpAndInt8x16
- OpAndNotInt8x16
- OpCompressInt8x16
- OpEqualInt8x16
- OpEqualMaskedInt8x16
- OpGreaterInt8x16
- OpGreaterEqualInt8x16
- OpGreaterEqualMaskedInt8x16
- OpGreaterMaskedInt8x16
- OpLessInt8x16
- OpLessEqualInt8x16
- OpLessEqualMaskedInt8x16
- OpLessMaskedInt8x16
- OpMaxInt8x16
- OpMaxMaskedInt8x16
- OpMinInt8x16
- OpMinMaskedInt8x16
- OpNotEqualInt8x16
- OpNotEqualMaskedInt8x16
- OpOrInt8x16
- OpPopCountInt8x16
- OpPopCountMaskedInt8x16
- OpSaturatedAddInt8x16
- OpSaturatedAddMaskedInt8x16
- OpSaturatedSubInt8x16
- OpSaturatedSubMaskedInt8x16
- OpSignInt8x16
- OpSubInt8x16
+ OpSubMaskedFloat32x4
+ OpSubMaskedFloat32x8
+ OpSubMaskedFloat32x16
+ OpSubMaskedFloat64x2
+ OpSubMaskedFloat64x4
+ OpSubMaskedFloat64x8
OpSubMaskedInt8x16
- OpXorInt8x16
- OpAbsoluteInt8x32
- OpAbsoluteMaskedInt8x32
- OpAddInt8x32
- OpAddMaskedInt8x32
- OpAndInt8x32
- OpAndNotInt8x32
- OpCompressInt8x32
- OpEqualInt8x32
- OpEqualMaskedInt8x32
- OpGreaterInt8x32
- OpGreaterEqualInt8x32
- OpGreaterEqualMaskedInt8x32
- OpGreaterMaskedInt8x32
- OpLessInt8x32
- OpLessEqualInt8x32
- OpLessEqualMaskedInt8x32
- OpLessMaskedInt8x32
- OpMaxInt8x32
- OpMaxMaskedInt8x32
- OpMinInt8x32
- OpMinMaskedInt8x32
- OpNotEqualInt8x32
- OpNotEqualMaskedInt8x32
- OpOrInt8x32
- OpPopCountInt8x32
- OpPopCountMaskedInt8x32
- OpSaturatedAddInt8x32
- OpSaturatedAddMaskedInt8x32
- OpSaturatedSubInt8x32
- OpSaturatedSubMaskedInt8x32
- OpSignInt8x32
- OpSubInt8x32
OpSubMaskedInt8x32
- OpXorInt8x32
- OpAbsoluteInt8x64
- OpAbsoluteMaskedInt8x64
- OpAddInt8x64
- OpAddMaskedInt8x64
- OpCompressInt8x64
- OpEqualInt8x64
- OpEqualMaskedInt8x64
- OpGreaterInt8x64
- OpGreaterEqualInt8x64
- OpGreaterEqualMaskedInt8x64
- OpGreaterMaskedInt8x64
- OpLessInt8x64
- OpLessEqualInt8x64
- OpLessEqualMaskedInt8x64
- OpLessMaskedInt8x64
- OpMaxInt8x64
- OpMaxMaskedInt8x64
- OpMinInt8x64
- OpMinMaskedInt8x64
- OpNotEqualInt8x64
- OpNotEqualMaskedInt8x64
- OpPopCountInt8x64
- OpPopCountMaskedInt8x64
- OpSaturatedAddInt8x64
- OpSaturatedAddMaskedInt8x64
- OpSaturatedSubInt8x64
- OpSaturatedSubMaskedInt8x64
- OpSubInt8x64
OpSubMaskedInt8x64
- OpAddUint16x16
- OpAddMaskedUint16x16
- OpAndUint16x16
- OpAndNotUint16x16
- OpAverageUint16x16
- OpAverageMaskedUint16x16
- OpCompressUint16x16
- OpEqualUint16x16
- OpEqualMaskedUint16x16
- OpGreaterUint16x16
- OpGreaterEqualUint16x16
- OpGreaterEqualMaskedUint16x16
- OpGreaterMaskedUint16x16
- OpLessUint16x16
- OpLessEqualUint16x16
- OpLessEqualMaskedUint16x16
- OpLessMaskedUint16x16
- OpMaxUint16x16
- OpMaxMaskedUint16x16
- OpMinUint16x16
- OpMinMaskedUint16x16
- OpMulHighUint16x16
- OpMulHighMaskedUint16x16
- OpNotEqualUint16x16
- OpNotEqualMaskedUint16x16
- OpOrUint16x16
- OpPairwiseAddUint16x16
- OpPairwiseSubUint16x16
- OpPermuteInt16x16
- OpPermuteUint16x16
- OpPermute2Uint16x16
- OpPermute2Int16x16
- OpPermute2MaskedUint16x16
- OpPermute2MaskedInt16x16
- OpPermuteMaskedInt16x16
- OpPermuteMaskedUint16x16
- OpPopCountUint16x16
- OpPopCountMaskedUint16x16
- OpSaturatedAddUint16x16
- OpSaturatedAddMaskedUint16x16
- OpSaturatedSubUint16x16
- OpSaturatedSubMaskedUint16x16
- OpShiftAllLeftUint16x16
- OpShiftAllLeftMaskedUint16x16
- OpShiftAllRightUint16x16
- OpShiftAllRightMaskedUint16x16
- OpShiftLeftUint16x16
- OpShiftLeftAndFillUpperFromUint16x16
- OpShiftLeftAndFillUpperFromMaskedUint16x16
- OpShiftLeftMaskedUint16x16
- OpShiftRightUint16x16
- OpShiftRightAndFillUpperFromUint16x16
- OpShiftRightAndFillUpperFromMaskedUint16x16
- OpShiftRightMaskedUint16x16
- OpSubUint16x16
- OpSubMaskedUint16x16
- OpXorUint16x16
- OpAddUint16x32
- OpAddMaskedUint16x32
- OpAverageUint16x32
- OpAverageMaskedUint16x32
- OpCompressUint16x32
- OpEqualUint16x32
- OpEqualMaskedUint16x32
- OpGreaterUint16x32
- OpGreaterEqualUint16x32
- OpGreaterEqualMaskedUint16x32
- OpGreaterMaskedUint16x32
- OpLessUint16x32
- OpLessEqualUint16x32
- OpLessEqualMaskedUint16x32
- OpLessMaskedUint16x32
- OpMaxUint16x32
- OpMaxMaskedUint16x32
- OpMinUint16x32
- OpMinMaskedUint16x32
- OpMulHighUint16x32
- OpMulHighMaskedUint16x32
- OpNotEqualUint16x32
- OpNotEqualMaskedUint16x32
- OpPermuteUint16x32
- OpPermuteInt16x32
- OpPermute2Uint16x32
- OpPermute2Int16x32
- OpPermute2MaskedUint16x32
- OpPermute2MaskedInt16x32
- OpPermuteMaskedInt16x32
- OpPermuteMaskedUint16x32
- OpPopCountUint16x32
- OpPopCountMaskedUint16x32
- OpSaturatedAddUint16x32
- OpSaturatedAddMaskedUint16x32
- OpSaturatedSubUint16x32
- OpSaturatedSubMaskedUint16x32
- OpShiftAllLeftUint16x32
- OpShiftAllLeftMaskedUint16x32
- OpShiftAllRightUint16x32
- OpShiftAllRightMaskedUint16x32
- OpShiftLeftUint16x32
- OpShiftLeftAndFillUpperFromUint16x32
- OpShiftLeftAndFillUpperFromMaskedUint16x32
- OpShiftLeftMaskedUint16x32
- OpShiftRightUint16x32
- OpShiftRightAndFillUpperFromUint16x32
- OpShiftRightAndFillUpperFromMaskedUint16x32
- OpShiftRightMaskedUint16x32
- OpSubUint16x32
- OpSubMaskedUint16x32
- OpAddUint16x8
- OpAddMaskedUint16x8
- OpAndUint16x8
- OpAndNotUint16x8
- OpAverageUint16x8
- OpAverageMaskedUint16x8
- OpCompressUint16x8
- OpEqualUint16x8
- OpEqualMaskedUint16x8
- OpGreaterUint16x8
- OpGreaterEqualUint16x8
- OpGreaterEqualMaskedUint16x8
- OpGreaterMaskedUint16x8
- OpLessUint16x8
- OpLessEqualUint16x8
- OpLessEqualMaskedUint16x8
- OpLessMaskedUint16x8
- OpMaxUint16x8
- OpMaxMaskedUint16x8
- OpMinUint16x8
- OpMinMaskedUint16x8
- OpMulHighUint16x8
- OpMulHighMaskedUint16x8
- OpNotEqualUint16x8
- OpNotEqualMaskedUint16x8
- OpOrUint16x8
- OpPairwiseAddUint16x8
- OpPairwiseSubUint16x8
- OpPermuteInt16x8
- OpPermuteUint16x8
- OpPermute2Uint16x8
- OpPermute2Int16x8
- OpPermute2MaskedInt16x8
- OpPermute2MaskedUint16x8
- OpPermuteMaskedInt16x8
- OpPermuteMaskedUint16x8
- OpPopCountUint16x8
- OpPopCountMaskedUint16x8
- OpSaturatedAddUint16x8
- OpSaturatedAddMaskedUint16x8
- OpSaturatedSubUint16x8
- OpSaturatedSubMaskedUint16x8
- OpShiftAllLeftUint16x8
- OpShiftAllLeftMaskedUint16x8
- OpShiftAllRightUint16x8
- OpShiftAllRightMaskedUint16x8
- OpShiftLeftUint16x8
- OpShiftLeftAndFillUpperFromUint16x8
- OpShiftLeftAndFillUpperFromMaskedUint16x8
- OpShiftLeftMaskedUint16x8
- OpShiftRightUint16x8
- OpShiftRightAndFillUpperFromUint16x8
- OpShiftRightAndFillUpperFromMaskedUint16x8
- OpShiftRightMaskedUint16x8
- OpSubUint16x8
- OpSubMaskedUint16x8
- OpXorUint16x8
- OpAddUint32x16
- OpAddMaskedUint32x16
- OpAndUint32x16
- OpAndMaskedUint32x16
- OpAndNotUint32x16
- OpAndNotMaskedUint32x16
- OpCompressUint32x16
- OpEqualUint32x16
- OpEqualMaskedUint32x16
- OpGreaterUint32x16
- OpGreaterEqualUint32x16
- OpGreaterEqualMaskedUint32x16
- OpGreaterMaskedUint32x16
- OpLessUint32x16
- OpLessEqualUint32x16
- OpLessEqualMaskedUint32x16
- OpLessMaskedUint32x16
- OpMaxUint32x16
- OpMaxMaskedUint32x16
- OpMinUint32x16
- OpMinMaskedUint32x16
- OpNotEqualUint32x16
- OpNotEqualMaskedUint32x16
- OpOrUint32x16
- OpOrMaskedUint32x16
- OpPermuteInt32x16
- OpPermuteFloat32x16
- OpPermuteUint32x16
- OpPermute2Uint32x16
- OpPermute2Float32x16
- OpPermute2Int32x16
- OpPermute2MaskedUint32x16
- OpPermute2MaskedInt32x16
- OpPermute2MaskedFloat32x16
- OpPermuteMaskedFloat32x16
- OpPermuteMaskedInt32x16
- OpPermuteMaskedUint32x16
- OpPopCountUint32x16
- OpPopCountMaskedUint32x16
- OpRotateLeftUint32x16
- OpRotateLeftMaskedUint32x16
- OpRotateRightUint32x16
- OpRotateRightMaskedUint32x16
- OpShiftAllLeftUint32x16
- OpShiftAllLeftMaskedUint32x16
- OpShiftAllRightUint32x16
- OpShiftAllRightMaskedUint32x16
- OpShiftLeftUint32x16
- OpShiftLeftAndFillUpperFromUint32x16
- OpShiftLeftAndFillUpperFromMaskedUint32x16
- OpShiftLeftMaskedUint32x16
- OpShiftRightUint32x16
- OpShiftRightAndFillUpperFromUint32x16
- OpShiftRightAndFillUpperFromMaskedUint32x16
- OpShiftRightMaskedUint32x16
- OpSubUint32x16
- OpSubMaskedUint32x16
- OpXorUint32x16
- OpXorMaskedUint32x16
- OpAddUint32x4
- OpAddMaskedUint32x4
- OpAndUint32x4
- OpAndMaskedUint32x4
- OpAndNotUint32x4
- OpAndNotMaskedUint32x4
- OpCompressUint32x4
- OpEqualUint32x4
- OpEqualMaskedUint32x4
- OpGreaterUint32x4
- OpGreaterEqualUint32x4
- OpGreaterEqualMaskedUint32x4
- OpGreaterMaskedUint32x4
- OpLessUint32x4
- OpLessEqualUint32x4
- OpLessEqualMaskedUint32x4
- OpLessMaskedUint32x4
- OpMaxUint32x4
- OpMaxMaskedUint32x4
- OpMinUint32x4
- OpMinMaskedUint32x4
- OpMulEvenWidenUint32x4
- OpNotEqualUint32x4
- OpNotEqualMaskedUint32x4
- OpOrUint32x4
- OpOrMaskedUint32x4
- OpPairwiseAddUint32x4
- OpPairwiseSubUint32x4
- OpPermute2Float32x4
- OpPermute2Uint32x4
- OpPermute2Int32x4
- OpPermute2MaskedInt32x4
- OpPermute2MaskedUint32x4
- OpPermute2MaskedFloat32x4
- OpPopCountUint32x4
- OpPopCountMaskedUint32x4
- OpRotateLeftUint32x4
- OpRotateLeftMaskedUint32x4
- OpRotateRightUint32x4
- OpRotateRightMaskedUint32x4
- OpShiftAllLeftUint32x4
- OpShiftAllLeftMaskedUint32x4
- OpShiftAllRightUint32x4
- OpShiftAllRightMaskedUint32x4
- OpShiftLeftUint32x4
- OpShiftLeftAndFillUpperFromUint32x4
- OpShiftLeftAndFillUpperFromMaskedUint32x4
- OpShiftLeftMaskedUint32x4
- OpShiftRightUint32x4
- OpShiftRightAndFillUpperFromUint32x4
- OpShiftRightAndFillUpperFromMaskedUint32x4
- OpShiftRightMaskedUint32x4
- OpSubUint32x4
- OpSubMaskedUint32x4
- OpXorUint32x4
- OpXorMaskedUint32x4
- OpAddUint32x8
- OpAddMaskedUint32x8
- OpAndUint32x8
- OpAndMaskedUint32x8
- OpAndNotUint32x8
- OpAndNotMaskedUint32x8
- OpCompressUint32x8
- OpEqualUint32x8
- OpEqualMaskedUint32x8
- OpGreaterUint32x8
- OpGreaterEqualUint32x8
- OpGreaterEqualMaskedUint32x8
- OpGreaterMaskedUint32x8
- OpLessUint32x8
- OpLessEqualUint32x8
- OpLessEqualMaskedUint32x8
- OpLessMaskedUint32x8
- OpMaxUint32x8
- OpMaxMaskedUint32x8
- OpMinUint32x8
- OpMinMaskedUint32x8
- OpMulEvenWidenUint32x8
- OpNotEqualUint32x8
- OpNotEqualMaskedUint32x8
- OpOrUint32x8
- OpOrMaskedUint32x8
- OpPairwiseAddUint32x8
- OpPairwiseSubUint32x8
- OpPermuteUint32x8
- OpPermuteFloat32x8
- OpPermuteInt32x8
- OpPermute2Int32x8
- OpPermute2Float32x8
- OpPermute2Uint32x8
- OpPermute2MaskedFloat32x8
- OpPermute2MaskedUint32x8
- OpPermute2MaskedInt32x8
- OpPermuteMaskedInt32x8
- OpPermuteMaskedUint32x8
- OpPermuteMaskedFloat32x8
- OpPopCountUint32x8
- OpPopCountMaskedUint32x8
- OpRotateLeftUint32x8
- OpRotateLeftMaskedUint32x8
- OpRotateRightUint32x8
- OpRotateRightMaskedUint32x8
- OpShiftAllLeftUint32x8
- OpShiftAllLeftMaskedUint32x8
- OpShiftAllRightUint32x8
- OpShiftAllRightMaskedUint32x8
- OpShiftLeftUint32x8
- OpShiftLeftAndFillUpperFromUint32x8
- OpShiftLeftAndFillUpperFromMaskedUint32x8
- OpShiftLeftMaskedUint32x8
- OpShiftRightUint32x8
- OpShiftRightAndFillUpperFromUint32x8
- OpShiftRightAndFillUpperFromMaskedUint32x8
- OpShiftRightMaskedUint32x8
- OpSubUint32x8
- OpSubMaskedUint32x8
- OpXorUint32x8
- OpXorMaskedUint32x8
- OpAddUint64x2
- OpAddMaskedUint64x2
- OpAndUint64x2
- OpAndMaskedUint64x2
- OpAndNotUint64x2
- OpAndNotMaskedUint64x2
- OpCompressUint64x2
- OpEqualUint64x2
- OpEqualMaskedUint64x2
- OpGreaterUint64x2
- OpGreaterEqualUint64x2
- OpGreaterEqualMaskedUint64x2
- OpGreaterMaskedUint64x2
- OpLessUint64x2
- OpLessEqualUint64x2
- OpLessEqualMaskedUint64x2
- OpLessMaskedUint64x2
- OpMaxUint64x2
- OpMaxMaskedUint64x2
- OpMinUint64x2
- OpMinMaskedUint64x2
- OpMulEvenWidenUint64x2
- OpMulEvenWidenMaskedUint64x2
- OpNotEqualUint64x2
- OpNotEqualMaskedUint64x2
- OpOrUint64x2
- OpOrMaskedUint64x2
- OpPermute2Float64x2
- OpPermute2Uint64x2
- OpPermute2Int64x2
- OpPermute2MaskedInt64x2
- OpPermute2MaskedFloat64x2
- OpPermute2MaskedUint64x2
- OpPopCountUint64x2
- OpPopCountMaskedUint64x2
- OpRotateLeftUint64x2
- OpRotateLeftMaskedUint64x2
- OpRotateRightUint64x2
- OpRotateRightMaskedUint64x2
- OpShiftAllLeftUint64x2
- OpShiftAllLeftMaskedUint64x2
- OpShiftAllRightUint64x2
- OpShiftAllRightMaskedUint64x2
- OpShiftLeftUint64x2
- OpShiftLeftAndFillUpperFromUint64x2
- OpShiftLeftAndFillUpperFromMaskedUint64x2
- OpShiftLeftMaskedUint64x2
- OpShiftRightUint64x2
- OpShiftRightAndFillUpperFromUint64x2
- OpShiftRightAndFillUpperFromMaskedUint64x2
- OpShiftRightMaskedUint64x2
- OpSubUint64x2
- OpSubMaskedUint64x2
- OpXorUint64x2
- OpXorMaskedUint64x2
- OpAddUint64x4
- OpAddMaskedUint64x4
- OpAndUint64x4
- OpAndMaskedUint64x4
- OpAndNotUint64x4
- OpAndNotMaskedUint64x4
- OpCompressUint64x4
- OpEqualUint64x4
- OpEqualMaskedUint64x4
- OpGreaterUint64x4
- OpGreaterEqualUint64x4
- OpGreaterEqualMaskedUint64x4
- OpGreaterMaskedUint64x4
- OpLessUint64x4
- OpLessEqualUint64x4
- OpLessEqualMaskedUint64x4
- OpLessMaskedUint64x4
- OpMaxUint64x4
- OpMaxMaskedUint64x4
- OpMinUint64x4
- OpMinMaskedUint64x4
- OpMulEvenWidenUint64x4
- OpMulEvenWidenMaskedUint64x4
- OpNotEqualUint64x4
- OpNotEqualMaskedUint64x4
- OpOrUint64x4
- OpOrMaskedUint64x4
- OpPermuteUint64x4
- OpPermuteInt64x4
- OpPermuteFloat64x4
- OpPermute2Uint64x4
- OpPermute2Int64x4
- OpPermute2Float64x4
- OpPermute2MaskedUint64x4
- OpPermute2MaskedFloat64x4
- OpPermute2MaskedInt64x4
- OpPermuteMaskedUint64x4
- OpPermuteMaskedFloat64x4
- OpPermuteMaskedInt64x4
- OpPopCountUint64x4
- OpPopCountMaskedUint64x4
- OpRotateLeftUint64x4
- OpRotateLeftMaskedUint64x4
- OpRotateRightUint64x4
- OpRotateRightMaskedUint64x4
- OpShiftAllLeftUint64x4
- OpShiftAllLeftMaskedUint64x4
- OpShiftAllRightUint64x4
- OpShiftAllRightMaskedUint64x4
- OpShiftLeftUint64x4
- OpShiftLeftAndFillUpperFromUint64x4
- OpShiftLeftAndFillUpperFromMaskedUint64x4
- OpShiftLeftMaskedUint64x4
- OpShiftRightUint64x4
- OpShiftRightAndFillUpperFromUint64x4
- OpShiftRightAndFillUpperFromMaskedUint64x4
- OpShiftRightMaskedUint64x4
- OpSubUint64x4
- OpSubMaskedUint64x4
- OpXorUint64x4
- OpXorMaskedUint64x4
- OpAddUint64x8
- OpAddMaskedUint64x8
- OpAndUint64x8
- OpAndMaskedUint64x8
- OpAndNotUint64x8
- OpAndNotMaskedUint64x8
- OpCompressUint64x8
- OpEqualUint64x8
- OpEqualMaskedUint64x8
- OpGreaterUint64x8
- OpGreaterEqualUint64x8
- OpGreaterEqualMaskedUint64x8
- OpGreaterMaskedUint64x8
- OpLessUint64x8
- OpLessEqualUint64x8
- OpLessEqualMaskedUint64x8
- OpLessMaskedUint64x8
- OpMaxUint64x8
- OpMaxMaskedUint64x8
- OpMinUint64x8
- OpMinMaskedUint64x8
- OpMulEvenWidenUint64x8
- OpMulEvenWidenMaskedUint64x8
- OpNotEqualUint64x8
- OpNotEqualMaskedUint64x8
- OpOrUint64x8
- OpOrMaskedUint64x8
- OpPermuteUint64x8
- OpPermuteFloat64x8
- OpPermuteInt64x8
- OpPermute2Float64x8
- OpPermute2Uint64x8
- OpPermute2Int64x8
- OpPermute2MaskedFloat64x8
- OpPermute2MaskedUint64x8
- OpPermute2MaskedInt64x8
- OpPermuteMaskedInt64x8
- OpPermuteMaskedFloat64x8
- OpPermuteMaskedUint64x8
- OpPopCountUint64x8
- OpPopCountMaskedUint64x8
- OpRotateLeftUint64x8
- OpRotateLeftMaskedUint64x8
- OpRotateRightUint64x8
- OpRotateRightMaskedUint64x8
- OpShiftAllLeftUint64x8
- OpShiftAllLeftMaskedUint64x8
- OpShiftAllRightUint64x8
- OpShiftAllRightMaskedUint64x8
- OpShiftLeftUint64x8
- OpShiftLeftAndFillUpperFromUint64x8
- OpShiftLeftAndFillUpperFromMaskedUint64x8
- OpShiftLeftMaskedUint64x8
- OpShiftRightUint64x8
- OpShiftRightAndFillUpperFromUint64x8
- OpShiftRightAndFillUpperFromMaskedUint64x8
- OpShiftRightMaskedUint64x8
- OpSubUint64x8
- OpSubMaskedUint64x8
- OpXorUint64x8
- OpXorMaskedUint64x8
- OpAddUint8x16
- OpAddMaskedUint8x16
- OpAndUint8x16
- OpAndNotUint8x16
- OpAverageUint8x16
- OpAverageMaskedUint8x16
- OpCompressUint8x16
- OpEqualUint8x16
- OpEqualMaskedUint8x16
- OpGaloisFieldMulUint8x16
- OpGaloisFieldMulMaskedUint8x16
- OpGreaterUint8x16
- OpGreaterEqualUint8x16
- OpGreaterEqualMaskedUint8x16
- OpGreaterMaskedUint8x16
- OpLessUint8x16
- OpLessEqualUint8x16
- OpLessEqualMaskedUint8x16
- OpLessMaskedUint8x16
- OpMaxUint8x16
- OpMaxMaskedUint8x16
- OpMinUint8x16
- OpMinMaskedUint8x16
- OpNotEqualUint8x16
- OpNotEqualMaskedUint8x16
- OpOrUint8x16
- OpPermuteUint8x16
- OpPermuteInt8x16
- OpPermute2Uint8x16
- OpPermute2Int8x16
- OpPermute2MaskedInt8x16
- OpPermute2MaskedUint8x16
- OpPermuteMaskedUint8x16
- OpPermuteMaskedInt8x16
- OpPopCountUint8x16
- OpPopCountMaskedUint8x16
- OpSaturatedAddUint8x16
- OpSaturatedAddMaskedUint8x16
- OpSaturatedSubUint8x16
- OpSaturatedSubMaskedUint8x16
- OpSaturatedUnsignedSignedPairDotProdUint8x16
- OpSaturatedUnsignedSignedPairDotProdMaskedUint8x16
- OpSubUint8x16
+ OpSubMaskedInt16x8
+ OpSubMaskedInt16x16
+ OpSubMaskedInt16x32
+ OpSubMaskedInt32x4
+ OpSubMaskedInt32x8
+ OpSubMaskedInt32x16
+ OpSubMaskedInt64x2
+ OpSubMaskedInt64x4
+ OpSubMaskedInt64x8
OpSubMaskedUint8x16
- OpXorUint8x16
- OpAddUint8x32
- OpAddMaskedUint8x32
- OpAndUint8x32
- OpAndNotUint8x32
- OpAverageUint8x32
- OpAverageMaskedUint8x32
- OpCompressUint8x32
- OpEqualUint8x32
- OpEqualMaskedUint8x32
- OpGaloisFieldMulUint8x32
- OpGaloisFieldMulMaskedUint8x32
- OpGreaterUint8x32
- OpGreaterEqualUint8x32
- OpGreaterEqualMaskedUint8x32
- OpGreaterMaskedUint8x32
- OpLessUint8x32
- OpLessEqualUint8x32
- OpLessEqualMaskedUint8x32
- OpLessMaskedUint8x32
- OpMaxUint8x32
- OpMaxMaskedUint8x32
- OpMinUint8x32
- OpMinMaskedUint8x32
- OpNotEqualUint8x32
- OpNotEqualMaskedUint8x32
- OpOrUint8x32
- OpPermuteUint8x32
- OpPermuteInt8x32
- OpPermute2Int8x32
- OpPermute2Uint8x32
- OpPermute2MaskedUint8x32
- OpPermute2MaskedInt8x32
- OpPermuteMaskedUint8x32
- OpPermuteMaskedInt8x32
- OpPopCountUint8x32
- OpPopCountMaskedUint8x32
- OpSaturatedAddUint8x32
- OpSaturatedAddMaskedUint8x32
- OpSaturatedSubUint8x32
- OpSaturatedSubMaskedUint8x32
- OpSaturatedUnsignedSignedPairDotProdUint8x32
- OpSaturatedUnsignedSignedPairDotProdMaskedUint8x32
- OpSubUint8x32
- OpSubMaskedUint8x32
- OpXorUint8x32
- OpAddUint8x64
- OpAddMaskedUint8x64
- OpAverageUint8x64
- OpAverageMaskedUint8x64
- OpCompressUint8x64
- OpEqualUint8x64
- OpEqualMaskedUint8x64
- OpGaloisFieldMulUint8x64
- OpGaloisFieldMulMaskedUint8x64
- OpGreaterUint8x64
- OpGreaterEqualUint8x64
- OpGreaterEqualMaskedUint8x64
- OpGreaterMaskedUint8x64
- OpLessUint8x64
- OpLessEqualUint8x64
- OpLessEqualMaskedUint8x64
- OpLessMaskedUint8x64
- OpMaxUint8x64
- OpMaxMaskedUint8x64
- OpMinUint8x64
- OpMinMaskedUint8x64
- OpNotEqualUint8x64
- OpNotEqualMaskedUint8x64
- OpPermuteInt8x64
- OpPermuteUint8x64
- OpPermute2Uint8x64
- OpPermute2Int8x64
- OpPermute2MaskedUint8x64
- OpPermute2MaskedInt8x64
- OpPermuteMaskedUint8x64
- OpPermuteMaskedInt8x64
- OpPopCountUint8x64
- OpPopCountMaskedUint8x64
- OpSaturatedAddUint8x64
- OpSaturatedAddMaskedUint8x64
- OpSaturatedSubUint8x64
- OpSaturatedSubMaskedUint8x64
- OpSaturatedUnsignedSignedPairDotProdUint8x64
- OpSaturatedUnsignedSignedPairDotProdMaskedUint8x64
- OpSubUint8x64
+ OpSubMaskedUint8x32
OpSubMaskedUint8x64
- OpCeilWithPrecisionFloat32x16
- OpCeilWithPrecisionMaskedFloat32x16
- OpDiffWithCeilWithPrecisionFloat32x16
- OpDiffWithCeilWithPrecisionMaskedFloat32x16
- OpDiffWithFloorWithPrecisionFloat32x16
- OpDiffWithFloorWithPrecisionMaskedFloat32x16
- OpDiffWithRoundWithPrecisionFloat32x16
- OpDiffWithRoundWithPrecisionMaskedFloat32x16
- OpDiffWithTruncWithPrecisionFloat32x16
- OpDiffWithTruncWithPrecisionMaskedFloat32x16
- OpFloorWithPrecisionFloat32x16
- OpFloorWithPrecisionMaskedFloat32x16
- OpRoundWithPrecisionFloat32x16
- OpRoundWithPrecisionMaskedFloat32x16
- OpTruncWithPrecisionFloat32x16
- OpTruncWithPrecisionMaskedFloat32x16
+ OpSubMaskedUint16x8
+ OpSubMaskedUint16x16
+ OpSubMaskedUint16x32
+ OpSubMaskedUint32x4
+ OpSubMaskedUint32x8
+ OpSubMaskedUint32x16
+ OpSubMaskedUint64x2
+ OpSubMaskedUint64x4
+ OpSubMaskedUint64x8
+ OpSubUint8x16
+ OpSubUint8x32
+ OpSubUint8x64
+ OpSubUint16x8
+ OpSubUint16x16
+ OpSubUint16x32
+ OpSubUint32x4
+ OpSubUint32x8
+ OpSubUint32x16
+ OpSubUint64x2
+ OpSubUint64x4
+ OpSubUint64x8
+ OpTruncFloat32x4
+ OpTruncFloat32x8
+ OpTruncFloat64x2
+ OpTruncFloat64x4
+ OpUnsignedSignedQuadDotProdAccumulateInt32x4
+ OpUnsignedSignedQuadDotProdAccumulateInt32x8
+ OpUnsignedSignedQuadDotProdAccumulateInt32x16
+ OpUnsignedSignedQuadDotProdAccumulateMaskedInt32x4
+ OpUnsignedSignedQuadDotProdAccumulateMaskedInt32x8
+ OpUnsignedSignedQuadDotProdAccumulateMaskedInt32x16
+ OpXorInt8x16
+ OpXorInt8x32
+ OpXorInt16x8
+ OpXorInt16x16
+ OpXorInt32x4
+ OpXorInt32x8
+ OpXorInt32x16
+ OpXorInt64x2
+ OpXorInt64x4
+ OpXorInt64x8
+ OpXorMaskedInt32x4
+ OpXorMaskedInt32x8
+ OpXorMaskedInt32x16
+ OpXorMaskedInt64x2
+ OpXorMaskedInt64x4
+ OpXorMaskedInt64x8
+ OpXorMaskedUint32x4
+ OpXorMaskedUint32x8
+ OpXorMaskedUint32x16
+ OpXorMaskedUint64x2
+ OpXorMaskedUint64x4
+ OpXorMaskedUint64x8
+ OpXorUint8x16
+ OpXorUint8x32
+ OpXorUint16x8
+ OpXorUint16x16
+ OpXorUint32x4
+ OpXorUint32x8
+ OpXorUint32x16
+ OpXorUint64x2
+ OpXorUint64x4
+ OpXorUint64x8
OpCeilWithPrecisionFloat32x4
- OpCeilWithPrecisionMaskedFloat32x4
- OpDiffWithCeilWithPrecisionFloat32x4
- OpDiffWithCeilWithPrecisionMaskedFloat32x4
- OpDiffWithFloorWithPrecisionFloat32x4
- OpDiffWithFloorWithPrecisionMaskedFloat32x4
- OpDiffWithRoundWithPrecisionFloat32x4
- OpDiffWithRoundWithPrecisionMaskedFloat32x4
- OpDiffWithTruncWithPrecisionFloat32x4
- OpDiffWithTruncWithPrecisionMaskedFloat32x4
- OpFloorWithPrecisionFloat32x4
- OpFloorWithPrecisionMaskedFloat32x4
- OpRoundWithPrecisionFloat32x4
- OpRoundWithPrecisionMaskedFloat32x4
- OpTruncWithPrecisionFloat32x4
- OpTruncWithPrecisionMaskedFloat32x4
OpCeilWithPrecisionFloat32x8
- OpCeilWithPrecisionMaskedFloat32x8
- OpDiffWithCeilWithPrecisionFloat32x8
- OpDiffWithCeilWithPrecisionMaskedFloat32x8
- OpDiffWithFloorWithPrecisionFloat32x8
- OpDiffWithFloorWithPrecisionMaskedFloat32x8
- OpDiffWithRoundWithPrecisionFloat32x8
- OpDiffWithRoundWithPrecisionMaskedFloat32x8
- OpDiffWithTruncWithPrecisionFloat32x8
- OpDiffWithTruncWithPrecisionMaskedFloat32x8
- OpFloorWithPrecisionFloat32x8
- OpFloorWithPrecisionMaskedFloat32x8
- OpGet128Float32x8
- OpRoundWithPrecisionFloat32x8
- OpRoundWithPrecisionMaskedFloat32x8
- OpSet128Float32x8
- OpTruncWithPrecisionFloat32x8
- OpTruncWithPrecisionMaskedFloat32x8
+ OpCeilWithPrecisionFloat32x16
OpCeilWithPrecisionFloat64x2
- OpCeilWithPrecisionMaskedFloat64x2
- OpDiffWithCeilWithPrecisionFloat64x2
- OpDiffWithCeilWithPrecisionMaskedFloat64x2
- OpDiffWithFloorWithPrecisionFloat64x2
- OpDiffWithFloorWithPrecisionMaskedFloat64x2
- OpDiffWithRoundWithPrecisionFloat64x2
- OpDiffWithRoundWithPrecisionMaskedFloat64x2
- OpDiffWithTruncWithPrecisionFloat64x2
- OpDiffWithTruncWithPrecisionMaskedFloat64x2
- OpFloorWithPrecisionFloat64x2
- OpFloorWithPrecisionMaskedFloat64x2
- OpRoundWithPrecisionFloat64x2
- OpRoundWithPrecisionMaskedFloat64x2
- OpTruncWithPrecisionFloat64x2
- OpTruncWithPrecisionMaskedFloat64x2
OpCeilWithPrecisionFloat64x4
- OpCeilWithPrecisionMaskedFloat64x4
- OpDiffWithCeilWithPrecisionFloat64x4
- OpDiffWithCeilWithPrecisionMaskedFloat64x4
- OpDiffWithFloorWithPrecisionFloat64x4
- OpDiffWithFloorWithPrecisionMaskedFloat64x4
- OpDiffWithRoundWithPrecisionFloat64x4
- OpDiffWithRoundWithPrecisionMaskedFloat64x4
- OpDiffWithTruncWithPrecisionFloat64x4
- OpDiffWithTruncWithPrecisionMaskedFloat64x4
- OpFloorWithPrecisionFloat64x4
- OpFloorWithPrecisionMaskedFloat64x4
- OpGet128Float64x4
- OpRoundWithPrecisionFloat64x4
- OpRoundWithPrecisionMaskedFloat64x4
- OpSet128Float64x4
- OpTruncWithPrecisionFloat64x4
- OpTruncWithPrecisionMaskedFloat64x4
OpCeilWithPrecisionFloat64x8
+ OpCeilWithPrecisionMaskedFloat32x4
+ OpCeilWithPrecisionMaskedFloat32x8
+ OpCeilWithPrecisionMaskedFloat32x16
+ OpCeilWithPrecisionMaskedFloat64x2
+ OpCeilWithPrecisionMaskedFloat64x4
OpCeilWithPrecisionMaskedFloat64x8
+ OpDiffWithCeilWithPrecisionFloat32x4
+ OpDiffWithCeilWithPrecisionFloat32x8
+ OpDiffWithCeilWithPrecisionFloat32x16
+ OpDiffWithCeilWithPrecisionFloat64x2
+ OpDiffWithCeilWithPrecisionFloat64x4
OpDiffWithCeilWithPrecisionFloat64x8
+ OpDiffWithCeilWithPrecisionMaskedFloat32x4
+ OpDiffWithCeilWithPrecisionMaskedFloat32x8
+ OpDiffWithCeilWithPrecisionMaskedFloat32x16
+ OpDiffWithCeilWithPrecisionMaskedFloat64x2
+ OpDiffWithCeilWithPrecisionMaskedFloat64x4
OpDiffWithCeilWithPrecisionMaskedFloat64x8
+ OpDiffWithFloorWithPrecisionFloat32x4
+ OpDiffWithFloorWithPrecisionFloat32x8
+ OpDiffWithFloorWithPrecisionFloat32x16
+ OpDiffWithFloorWithPrecisionFloat64x2
+ OpDiffWithFloorWithPrecisionFloat64x4
OpDiffWithFloorWithPrecisionFloat64x8
+ OpDiffWithFloorWithPrecisionMaskedFloat32x4
+ OpDiffWithFloorWithPrecisionMaskedFloat32x8
+ OpDiffWithFloorWithPrecisionMaskedFloat32x16
+ OpDiffWithFloorWithPrecisionMaskedFloat64x2
+ OpDiffWithFloorWithPrecisionMaskedFloat64x4
OpDiffWithFloorWithPrecisionMaskedFloat64x8
+ OpDiffWithRoundWithPrecisionFloat32x4
+ OpDiffWithRoundWithPrecisionFloat32x8
+ OpDiffWithRoundWithPrecisionFloat32x16
+ OpDiffWithRoundWithPrecisionFloat64x2
+ OpDiffWithRoundWithPrecisionFloat64x4
OpDiffWithRoundWithPrecisionFloat64x8
+ OpDiffWithRoundWithPrecisionMaskedFloat32x4
+ OpDiffWithRoundWithPrecisionMaskedFloat32x8
+ OpDiffWithRoundWithPrecisionMaskedFloat32x16
+ OpDiffWithRoundWithPrecisionMaskedFloat64x2
+ OpDiffWithRoundWithPrecisionMaskedFloat64x4
OpDiffWithRoundWithPrecisionMaskedFloat64x8
+ OpDiffWithTruncWithPrecisionFloat32x4
+ OpDiffWithTruncWithPrecisionFloat32x8
+ OpDiffWithTruncWithPrecisionFloat32x16
+ OpDiffWithTruncWithPrecisionFloat64x2
+ OpDiffWithTruncWithPrecisionFloat64x4
OpDiffWithTruncWithPrecisionFloat64x8
+ OpDiffWithTruncWithPrecisionMaskedFloat32x4
+ OpDiffWithTruncWithPrecisionMaskedFloat32x8
+ OpDiffWithTruncWithPrecisionMaskedFloat32x16
+ OpDiffWithTruncWithPrecisionMaskedFloat64x2
+ OpDiffWithTruncWithPrecisionMaskedFloat64x4
OpDiffWithTruncWithPrecisionMaskedFloat64x8
+ OpFloorWithPrecisionFloat32x4
+ OpFloorWithPrecisionFloat32x8
+ OpFloorWithPrecisionFloat32x16
+ OpFloorWithPrecisionFloat64x2
+ OpFloorWithPrecisionFloat64x4
OpFloorWithPrecisionFloat64x8
+ OpFloorWithPrecisionMaskedFloat32x4
+ OpFloorWithPrecisionMaskedFloat32x8
+ OpFloorWithPrecisionMaskedFloat32x16
+ OpFloorWithPrecisionMaskedFloat64x2
+ OpFloorWithPrecisionMaskedFloat64x4
OpFloorWithPrecisionMaskedFloat64x8
- OpRoundWithPrecisionFloat64x8
- OpRoundWithPrecisionMaskedFloat64x8
- OpTruncWithPrecisionFloat64x8
- OpTruncWithPrecisionMaskedFloat64x8
+ OpGaloisFieldAffineTransformInverseMaskedUint8x16
+ OpGaloisFieldAffineTransformInverseMaskedUint8x32
+ OpGaloisFieldAffineTransformInverseMaskedUint8x64
+ OpGaloisFieldAffineTransformInverseUint8x16
+ OpGaloisFieldAffineTransformInverseUint8x32
+ OpGaloisFieldAffineTransformInverseUint8x64
+ OpGaloisFieldAffineTransformMaskedUint8x16
+ OpGaloisFieldAffineTransformMaskedUint8x32
+ OpGaloisFieldAffineTransformMaskedUint8x64
+ OpGaloisFieldAffineTransformUint8x16
+ OpGaloisFieldAffineTransformUint8x32
+ OpGaloisFieldAffineTransformUint8x64
+ OpGet128Float32x8
+ OpGet128Float64x4
+ OpGet128Int8x32
OpGet128Int16x16
- OpSet128Int16x16
- OpShiftAllLeftAndFillUpperFromInt16x16
- OpShiftAllLeftAndFillUpperFromMaskedInt16x16
- OpShiftAllRightAndFillUpperFromInt16x16
- OpShiftAllRightAndFillUpperFromMaskedInt16x16
- OpShiftAllLeftAndFillUpperFromInt16x32
- OpShiftAllLeftAndFillUpperFromMaskedInt16x32
- OpShiftAllRightAndFillUpperFromInt16x32
- OpShiftAllRightAndFillUpperFromMaskedInt16x32
+ OpGet128Int32x8
+ OpGet128Int64x4
+ OpGet128Uint8x32
+ OpGet128Uint16x16
+ OpGet128Uint32x8
+ OpGet128Uint64x4
+ OpGetElemInt8x16
OpGetElemInt16x8
- OpSetElemInt16x8
- OpShiftAllLeftAndFillUpperFromInt16x8
- OpShiftAllLeftAndFillUpperFromMaskedInt16x8
- OpShiftAllRightAndFillUpperFromInt16x8
- OpShiftAllRightAndFillUpperFromMaskedInt16x8
- OpRotateAllLeftInt32x16
- OpRotateAllLeftMaskedInt32x16
- OpRotateAllRightInt32x16
- OpRotateAllRightMaskedInt32x16
- OpShiftAllLeftAndFillUpperFromInt32x16
- OpShiftAllLeftAndFillUpperFromMaskedInt32x16
- OpShiftAllRightAndFillUpperFromInt32x16
- OpShiftAllRightAndFillUpperFromMaskedInt32x16
OpGetElemInt32x4
+ OpGetElemInt64x2
+ OpGetElemUint8x16
+ OpGetElemUint16x8
+ OpGetElemUint32x4
+ OpGetElemUint64x2
OpRotateAllLeftInt32x4
- OpRotateAllLeftMaskedInt32x4
- OpRotateAllRightInt32x4
- OpRotateAllRightMaskedInt32x4
- OpSetElemInt32x4
- OpShiftAllLeftAndFillUpperFromInt32x4
- OpShiftAllLeftAndFillUpperFromMaskedInt32x4
- OpShiftAllRightAndFillUpperFromInt32x4
- OpShiftAllRightAndFillUpperFromMaskedInt32x4
- OpGet128Int32x8
OpRotateAllLeftInt32x8
- OpRotateAllLeftMaskedInt32x8
- OpRotateAllRightInt32x8
- OpRotateAllRightMaskedInt32x8
- OpSet128Int32x8
- OpShiftAllLeftAndFillUpperFromInt32x8
- OpShiftAllLeftAndFillUpperFromMaskedInt32x8
- OpShiftAllRightAndFillUpperFromInt32x8
- OpShiftAllRightAndFillUpperFromMaskedInt32x8
- OpGetElemInt64x2
+ OpRotateAllLeftInt32x16
OpRotateAllLeftInt64x2
- OpRotateAllLeftMaskedInt64x2
- OpRotateAllRightInt64x2
- OpRotateAllRightMaskedInt64x2
- OpSetElemInt64x2
- OpShiftAllLeftAndFillUpperFromInt64x2
- OpShiftAllLeftAndFillUpperFromMaskedInt64x2
- OpShiftAllRightAndFillUpperFromInt64x2
- OpShiftAllRightAndFillUpperFromMaskedInt64x2
- OpGet128Int64x4
OpRotateAllLeftInt64x4
+ OpRotateAllLeftInt64x8
+ OpRotateAllLeftMaskedInt32x4
+ OpRotateAllLeftMaskedInt32x8
+ OpRotateAllLeftMaskedInt32x16
+ OpRotateAllLeftMaskedInt64x2
OpRotateAllLeftMaskedInt64x4
+ OpRotateAllLeftMaskedInt64x8
+ OpRotateAllLeftMaskedUint32x4
+ OpRotateAllLeftMaskedUint32x8
+ OpRotateAllLeftMaskedUint32x16
+ OpRotateAllLeftMaskedUint64x2
+ OpRotateAllLeftMaskedUint64x4
+ OpRotateAllLeftMaskedUint64x8
+ OpRotateAllLeftUint32x4
+ OpRotateAllLeftUint32x8
+ OpRotateAllLeftUint32x16
+ OpRotateAllLeftUint64x2
+ OpRotateAllLeftUint64x4
+ OpRotateAllLeftUint64x8
+ OpRotateAllRightInt32x4
+ OpRotateAllRightInt32x8
+ OpRotateAllRightInt32x16
+ OpRotateAllRightInt64x2
OpRotateAllRightInt64x4
+ OpRotateAllRightInt64x8
+ OpRotateAllRightMaskedInt32x4
+ OpRotateAllRightMaskedInt32x8
+ OpRotateAllRightMaskedInt32x16
+ OpRotateAllRightMaskedInt64x2
OpRotateAllRightMaskedInt64x4
+ OpRotateAllRightMaskedInt64x8
+ OpRotateAllRightMaskedUint32x4
+ OpRotateAllRightMaskedUint32x8
+ OpRotateAllRightMaskedUint32x16
+ OpRotateAllRightMaskedUint64x2
+ OpRotateAllRightMaskedUint64x4
+ OpRotateAllRightMaskedUint64x8
+ OpRotateAllRightUint32x4
+ OpRotateAllRightUint32x8
+ OpRotateAllRightUint32x16
+ OpRotateAllRightUint64x2
+ OpRotateAllRightUint64x4
+ OpRotateAllRightUint64x8
+ OpRoundWithPrecisionFloat32x4
+ OpRoundWithPrecisionFloat32x8
+ OpRoundWithPrecisionFloat32x16
+ OpRoundWithPrecisionFloat64x2
+ OpRoundWithPrecisionFloat64x4
+ OpRoundWithPrecisionFloat64x8
+ OpRoundWithPrecisionMaskedFloat32x4
+ OpRoundWithPrecisionMaskedFloat32x8
+ OpRoundWithPrecisionMaskedFloat32x16
+ OpRoundWithPrecisionMaskedFloat64x2
+ OpRoundWithPrecisionMaskedFloat64x4
+ OpRoundWithPrecisionMaskedFloat64x8
+ OpSet128Float32x8
+ OpSet128Float64x4
+ OpSet128Int8x32
+ OpSet128Int16x16
+ OpSet128Int32x8
OpSet128Int64x4
+ OpSet128Uint8x32
+ OpSet128Uint16x16
+ OpSet128Uint32x8
+ OpSet128Uint64x4
+ OpSetElemInt8x16
+ OpSetElemInt16x8
+ OpSetElemInt32x4
+ OpSetElemInt64x2
+ OpSetElemUint8x16
+ OpSetElemUint16x8
+ OpSetElemUint32x4
+ OpSetElemUint64x2
+ OpShiftAllLeftAndFillUpperFromInt16x8
+ OpShiftAllLeftAndFillUpperFromInt16x16
+ OpShiftAllLeftAndFillUpperFromInt16x32
+ OpShiftAllLeftAndFillUpperFromInt32x4
+ OpShiftAllLeftAndFillUpperFromInt32x8
+ OpShiftAllLeftAndFillUpperFromInt32x16
+ OpShiftAllLeftAndFillUpperFromInt64x2
OpShiftAllLeftAndFillUpperFromInt64x4
- OpShiftAllLeftAndFillUpperFromMaskedInt64x4
- OpShiftAllRightAndFillUpperFromInt64x4
- OpShiftAllRightAndFillUpperFromMaskedInt64x4
- OpRotateAllLeftInt64x8
- OpRotateAllLeftMaskedInt64x8
- OpRotateAllRightInt64x8
- OpRotateAllRightMaskedInt64x8
OpShiftAllLeftAndFillUpperFromInt64x8
+ OpShiftAllLeftAndFillUpperFromMaskedInt16x8
+ OpShiftAllLeftAndFillUpperFromMaskedInt16x16
+ OpShiftAllLeftAndFillUpperFromMaskedInt16x32
+ OpShiftAllLeftAndFillUpperFromMaskedInt32x4
+ OpShiftAllLeftAndFillUpperFromMaskedInt32x8
+ OpShiftAllLeftAndFillUpperFromMaskedInt32x16
+ OpShiftAllLeftAndFillUpperFromMaskedInt64x2
+ OpShiftAllLeftAndFillUpperFromMaskedInt64x4
OpShiftAllLeftAndFillUpperFromMaskedInt64x8
- OpShiftAllRightAndFillUpperFromInt64x8
- OpShiftAllRightAndFillUpperFromMaskedInt64x8
- OpGetElemInt8x16
- OpSetElemInt8x16
- OpGet128Int8x32
- OpSet128Int8x32
- OpGet128Uint16x16
- OpSet128Uint16x16
- OpShiftAllLeftAndFillUpperFromUint16x16
+ OpShiftAllLeftAndFillUpperFromMaskedUint16x8
OpShiftAllLeftAndFillUpperFromMaskedUint16x16
- OpShiftAllRightAndFillUpperFromUint16x16
- OpShiftAllRightAndFillUpperFromMaskedUint16x16
- OpShiftAllLeftAndFillUpperFromUint16x32
OpShiftAllLeftAndFillUpperFromMaskedUint16x32
- OpShiftAllRightAndFillUpperFromUint16x32
- OpShiftAllRightAndFillUpperFromMaskedUint16x32
- OpGetElemUint16x8
- OpSetElemUint16x8
+ OpShiftAllLeftAndFillUpperFromMaskedUint32x4
+ OpShiftAllLeftAndFillUpperFromMaskedUint32x8
+ OpShiftAllLeftAndFillUpperFromMaskedUint32x16
+ OpShiftAllLeftAndFillUpperFromMaskedUint64x2
+ OpShiftAllLeftAndFillUpperFromMaskedUint64x4
+ OpShiftAllLeftAndFillUpperFromMaskedUint64x8
OpShiftAllLeftAndFillUpperFromUint16x8
- OpShiftAllLeftAndFillUpperFromMaskedUint16x8
- OpShiftAllRightAndFillUpperFromUint16x8
- OpShiftAllRightAndFillUpperFromMaskedUint16x8
- OpRotateAllLeftUint32x16
- OpRotateAllLeftMaskedUint32x16
- OpRotateAllRightUint32x16
- OpRotateAllRightMaskedUint32x16
+ OpShiftAllLeftAndFillUpperFromUint16x16
+ OpShiftAllLeftAndFillUpperFromUint16x32
+ OpShiftAllLeftAndFillUpperFromUint32x4
+ OpShiftAllLeftAndFillUpperFromUint32x8
OpShiftAllLeftAndFillUpperFromUint32x16
- OpShiftAllLeftAndFillUpperFromMaskedUint32x16
- OpShiftAllRightAndFillUpperFromUint32x16
+ OpShiftAllLeftAndFillUpperFromUint64x2
+ OpShiftAllLeftAndFillUpperFromUint64x4
+ OpShiftAllLeftAndFillUpperFromUint64x8
+ OpShiftAllRightAndFillUpperFromInt16x8
+ OpShiftAllRightAndFillUpperFromInt16x16
+ OpShiftAllRightAndFillUpperFromInt16x32
+ OpShiftAllRightAndFillUpperFromInt32x4
+ OpShiftAllRightAndFillUpperFromInt32x8
+ OpShiftAllRightAndFillUpperFromInt32x16
+ OpShiftAllRightAndFillUpperFromInt64x2
+ OpShiftAllRightAndFillUpperFromInt64x4
+ OpShiftAllRightAndFillUpperFromInt64x8
+ OpShiftAllRightAndFillUpperFromMaskedInt16x8
+ OpShiftAllRightAndFillUpperFromMaskedInt16x16
+ OpShiftAllRightAndFillUpperFromMaskedInt16x32
+ OpShiftAllRightAndFillUpperFromMaskedInt32x4
+ OpShiftAllRightAndFillUpperFromMaskedInt32x8
+ OpShiftAllRightAndFillUpperFromMaskedInt32x16
+ OpShiftAllRightAndFillUpperFromMaskedInt64x2
+ OpShiftAllRightAndFillUpperFromMaskedInt64x4
+ OpShiftAllRightAndFillUpperFromMaskedInt64x8
+ OpShiftAllRightAndFillUpperFromMaskedUint16x8
+ OpShiftAllRightAndFillUpperFromMaskedUint16x16
+ OpShiftAllRightAndFillUpperFromMaskedUint16x32
+ OpShiftAllRightAndFillUpperFromMaskedUint32x4
+ OpShiftAllRightAndFillUpperFromMaskedUint32x8
OpShiftAllRightAndFillUpperFromMaskedUint32x16
- OpGetElemUint32x4
- OpRotateAllLeftUint32x4
- OpRotateAllLeftMaskedUint32x4
- OpRotateAllRightUint32x4
- OpRotateAllRightMaskedUint32x4
- OpSetElemUint32x4
- OpShiftAllLeftAndFillUpperFromUint32x4
- OpShiftAllLeftAndFillUpperFromMaskedUint32x4
+ OpShiftAllRightAndFillUpperFromMaskedUint64x2
+ OpShiftAllRightAndFillUpperFromMaskedUint64x4
+ OpShiftAllRightAndFillUpperFromMaskedUint64x8
+ OpShiftAllRightAndFillUpperFromUint16x8
+ OpShiftAllRightAndFillUpperFromUint16x16
+ OpShiftAllRightAndFillUpperFromUint16x32
OpShiftAllRightAndFillUpperFromUint32x4
- OpShiftAllRightAndFillUpperFromMaskedUint32x4
- OpGet128Uint32x8
- OpRotateAllLeftUint32x8
- OpRotateAllLeftMaskedUint32x8
- OpRotateAllRightUint32x8
- OpRotateAllRightMaskedUint32x8
- OpSet128Uint32x8
- OpShiftAllLeftAndFillUpperFromUint32x8
- OpShiftAllLeftAndFillUpperFromMaskedUint32x8
OpShiftAllRightAndFillUpperFromUint32x8
- OpShiftAllRightAndFillUpperFromMaskedUint32x8
- OpGetElemUint64x2
- OpRotateAllLeftUint64x2
- OpRotateAllLeftMaskedUint64x2
- OpRotateAllRightUint64x2
- OpRotateAllRightMaskedUint64x2
- OpSetElemUint64x2
- OpShiftAllLeftAndFillUpperFromUint64x2
- OpShiftAllLeftAndFillUpperFromMaskedUint64x2
+ OpShiftAllRightAndFillUpperFromUint32x16
OpShiftAllRightAndFillUpperFromUint64x2
- OpShiftAllRightAndFillUpperFromMaskedUint64x2
- OpGet128Uint64x4
- OpRotateAllLeftUint64x4
- OpRotateAllLeftMaskedUint64x4
- OpRotateAllRightUint64x4
- OpRotateAllRightMaskedUint64x4
- OpSet128Uint64x4
- OpShiftAllLeftAndFillUpperFromUint64x4
- OpShiftAllLeftAndFillUpperFromMaskedUint64x4
OpShiftAllRightAndFillUpperFromUint64x4
- OpShiftAllRightAndFillUpperFromMaskedUint64x4
- OpRotateAllLeftUint64x8
- OpRotateAllLeftMaskedUint64x8
- OpRotateAllRightUint64x8
- OpRotateAllRightMaskedUint64x8
- OpShiftAllLeftAndFillUpperFromUint64x8
- OpShiftAllLeftAndFillUpperFromMaskedUint64x8
OpShiftAllRightAndFillUpperFromUint64x8
- OpShiftAllRightAndFillUpperFromMaskedUint64x8
- OpGaloisFieldAffineTransformUint8x16
- OpGaloisFieldAffineTransformInverseUint8x16
- OpGaloisFieldAffineTransformInverseMaskedUint8x16
- OpGaloisFieldAffineTransformMaskedUint8x16
- OpGetElemUint8x16
- OpSetElemUint8x16
- OpGaloisFieldAffineTransformUint8x32
- OpGaloisFieldAffineTransformInverseUint8x32
- OpGaloisFieldAffineTransformInverseMaskedUint8x32
- OpGaloisFieldAffineTransformMaskedUint8x32
- OpGet128Uint8x32
- OpSet128Uint8x32
- OpGaloisFieldAffineTransformUint8x64
- OpGaloisFieldAffineTransformInverseUint8x64
- OpGaloisFieldAffineTransformInverseMaskedUint8x64
- OpGaloisFieldAffineTransformMaskedUint8x64
+ OpTruncWithPrecisionFloat32x4
+ OpTruncWithPrecisionFloat32x8
+ OpTruncWithPrecisionFloat32x16
+ OpTruncWithPrecisionFloat64x2
+ OpTruncWithPrecisionFloat64x4
+ OpTruncWithPrecisionFloat64x8
+ OpTruncWithPrecisionMaskedFloat32x4
+ OpTruncWithPrecisionMaskedFloat32x8
+ OpTruncWithPrecisionMaskedFloat32x16
+ OpTruncWithPrecisionMaskedFloat64x2
+ OpTruncWithPrecisionMaskedFloat64x4
+ OpTruncWithPrecisionMaskedFloat64x8
)
var opcodeTable = [...]opInfo{
},
},
{
- name: "VADDPS512",
+ name: "VADDPD128",
argLen: 2,
commutative: true,
- asm: x86.AVADDPS,
+ asm: x86.AVADDPD,
reg: regInfo{
inputs: []inputInfo{
- {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
- {1, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
- {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
},
{
- name: "VADDPSMasked512",
- argLen: 3,
+ name: "VADDPD256",
+ argLen: 2,
commutative: true,
- asm: x86.AVADDPS,
+ asm: x86.AVADDPD,
reg: regInfo{
inputs: []inputInfo{
- {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
{
- name: "VRCP14PS512",
- argLen: 1,
- asm: x86.AVRCP14PS,
+ name: "VADDPD512",
+ argLen: 2,
+ commutative: true,
+ asm: x86.AVADDPD,
reg: regInfo{
inputs: []inputInfo{
{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ {1, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
},
outputs: []outputInfo{
{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
},
},
{
- name: "VRCP14PSMasked512",
- argLen: 2,
- asm: x86.AVRCP14PS,
+ name: "VADDPDMasked128",
+ argLen: 3,
+ commutative: true,
+ asm: x86.AVADDPD,
reg: regInfo{
inputs: []inputInfo{
- {1, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+ {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
{
- name: "VRSQRT14PS512",
- argLen: 1,
- asm: x86.AVRSQRT14PS,
+ name: "VADDPDMasked256",
+ argLen: 3,
+ commutative: true,
+ asm: x86.AVADDPD,
reg: regInfo{
inputs: []inputInfo{
- {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
- {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
},
{
- name: "VRSQRT14PSMasked512",
- argLen: 2,
- asm: x86.AVRSQRT14PS,
+ name: "VADDPDMasked512",
+ argLen: 3,
+ commutative: true,
+ asm: x86.AVADDPD,
reg: regInfo{
inputs: []inputInfo{
- {1, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+ {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
{
- name: "VCOMPRESSPSMasked512",
- argLen: 2,
- asm: x86.AVCOMPRESSPS,
+ name: "VADDPS128",
+ argLen: 2,
+ commutative: true,
+ asm: x86.AVADDPS,
reg: regInfo{
inputs: []inputInfo{
- {1, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
{
- name: "VDIVPS512",
- argLen: 2,
- asm: x86.AVDIVPS,
+ name: "VADDPS256",
+ argLen: 2,
+ commutative: true,
+ asm: x86.AVADDPS,
+ reg: regInfo{
+ inputs: []inputInfo{
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ },
+ outputs: []outputInfo{
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ },
+ },
+ },
+ {
+ name: "VADDPS512",
+ argLen: 2,
+ commutative: true,
+ asm: x86.AVADDPS,
reg: regInfo{
inputs: []inputInfo{
{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
},
},
{
- name: "VDIVPSMasked512",
- argLen: 3,
- asm: x86.AVDIVPS,
+ name: "VADDPSMasked128",
+ argLen: 3,
+ commutative: true,
+ asm: x86.AVADDPS,
reg: regInfo{
inputs: []inputInfo{
{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
},
},
{
- name: "VFMADD213PS512",
- argLen: 3,
- resultInArg0: true,
- asm: x86.AVFMADD213PS,
+ name: "VADDPSMasked256",
+ argLen: 3,
+ commutative: true,
+ asm: x86.AVADDPS,
reg: regInfo{
inputs: []inputInfo{
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
{
- name: "VFMADD213PSMasked512",
- argLen: 4,
- resultInArg0: true,
- asm: x86.AVFMADD213PS,
+ name: "VADDPSMasked512",
+ argLen: 3,
+ commutative: true,
+ asm: x86.AVADDPS,
reg: regInfo{
inputs: []inputInfo{
- {3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+ {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
{
- name: "VFMADDSUB213PS512",
- argLen: 3,
- resultInArg0: true,
- asm: x86.AVFMADDSUB213PS,
+ name: "VADDSUBPD128",
+ argLen: 2,
+ asm: x86.AVADDSUBPD,
reg: regInfo{
inputs: []inputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
{
- name: "VFMADDSUB213PSMasked512",
- argLen: 4,
- resultInArg0: true,
- asm: x86.AVFMADDSUB213PS,
+ name: "VADDSUBPD256",
+ argLen: 2,
+ asm: x86.AVADDSUBPD,
reg: regInfo{
inputs: []inputInfo{
- {3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
{
- name: "VFMSUBADD213PS512",
- argLen: 3,
- resultInArg0: true,
- asm: x86.AVFMSUBADD213PS,
+ name: "VADDSUBPS128",
+ argLen: 2,
+ asm: x86.AVADDSUBPS,
reg: regInfo{
inputs: []inputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
{
- name: "VFMSUBADD213PSMasked512",
- argLen: 4,
- resultInArg0: true,
- asm: x86.AVFMSUBADD213PS,
+ name: "VADDSUBPS256",
+ argLen: 2,
+ asm: x86.AVADDSUBPS,
reg: regInfo{
inputs: []inputInfo{
- {3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ },
+ outputs: []outputInfo{
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ },
+ },
+ },
+ {
+ name: "VCOMPRESSPDMasked128",
+ argLen: 2,
+ asm: x86.AVCOMPRESSPD,
+ reg: regInfo{
+ inputs: []inputInfo{
+ {1, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
{
- name: "VMAXPS512",
- argLen: 2,
- commutative: true,
- asm: x86.AVMAXPS,
+ name: "VCOMPRESSPDMasked256",
+ argLen: 2,
+ asm: x86.AVCOMPRESSPD,
reg: regInfo{
inputs: []inputInfo{
- {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
- {1, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ {1, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
- {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
},
{
- name: "VMAXPSMasked512",
- argLen: 3,
- commutative: true,
- asm: x86.AVMAXPS,
+ name: "VCOMPRESSPDMasked512",
+ argLen: 2,
+ asm: x86.AVCOMPRESSPD,
reg: regInfo{
inputs: []inputInfo{
- {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+ {1, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
{
- name: "VMINPS512",
- argLen: 2,
- commutative: true,
- asm: x86.AVMINPS,
+ name: "VCOMPRESSPSMasked128",
+ argLen: 2,
+ asm: x86.AVCOMPRESSPS,
reg: regInfo{
inputs: []inputInfo{
- {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
- {1, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ {1, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
- {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
},
{
- name: "VMINPSMasked512",
- argLen: 3,
- commutative: true,
- asm: x86.AVMINPS,
+ name: "VCOMPRESSPSMasked256",
+ argLen: 2,
+ asm: x86.AVCOMPRESSPS,
reg: regInfo{
inputs: []inputInfo{
- {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+ {1, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
{
- name: "VMULPS512",
- argLen: 2,
- commutative: true,
- asm: x86.AVMULPS,
+ name: "VCOMPRESSPSMasked512",
+ argLen: 2,
+ asm: x86.AVCOMPRESSPS,
reg: regInfo{
inputs: []inputInfo{
- {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
- {1, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ {1, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
- {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
},
{
- name: "VSCALEFPS512",
+ name: "VDIVPD128",
argLen: 2,
- asm: x86.AVSCALEFPS,
+ asm: x86.AVDIVPD,
+ reg: regInfo{
+ inputs: []inputInfo{
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ },
+ outputs: []outputInfo{
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ },
+ },
+ },
+ {
+ name: "VDIVPD256",
+ argLen: 2,
+ asm: x86.AVDIVPD,
+ reg: regInfo{
+ inputs: []inputInfo{
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ },
+ outputs: []outputInfo{
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ },
+ },
+ },
+ {
+ name: "VDIVPD512",
+ argLen: 2,
+ asm: x86.AVDIVPD,
reg: regInfo{
inputs: []inputInfo{
{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
},
},
{
- name: "VSCALEFPSMasked512",
+ name: "VDIVPDMasked128",
argLen: 3,
- asm: x86.AVSCALEFPS,
+ asm: x86.AVDIVPD,
reg: regInfo{
inputs: []inputInfo{
{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
},
},
{
- name: "VMULPSMasked512",
- argLen: 3,
- commutative: true,
- asm: x86.AVMULPS,
+ name: "VDIVPDMasked256",
+ argLen: 3,
+ asm: x86.AVDIVPD,
reg: regInfo{
inputs: []inputInfo{
{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
},
},
{
- name: "VSQRTPS512",
- argLen: 1,
- asm: x86.AVSQRTPS,
+ name: "VDIVPDMasked512",
+ argLen: 3,
+ asm: x86.AVDIVPD,
reg: regInfo{
inputs: []inputInfo{
- {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
- {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
},
{
- name: "VSQRTPSMasked512",
+ name: "VDIVPS128",
argLen: 2,
- asm: x86.AVSQRTPS,
+ asm: x86.AVDIVPS,
reg: regInfo{
inputs: []inputInfo{
- {1, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
{
- name: "VSUBPS512",
+ name: "VDIVPS256",
argLen: 2,
- asm: x86.AVSUBPS,
+ asm: x86.AVDIVPS,
+ reg: regInfo{
+ inputs: []inputInfo{
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ },
+ outputs: []outputInfo{
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ },
+ },
+ },
+ {
+ name: "VDIVPS512",
+ argLen: 2,
+ asm: x86.AVDIVPS,
reg: regInfo{
inputs: []inputInfo{
{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
{1, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
},
outputs: []outputInfo{
- {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ },
+ },
+ },
+ {
+ name: "VDIVPSMasked128",
+ argLen: 3,
+ asm: x86.AVDIVPS,
+ reg: regInfo{
+ inputs: []inputInfo{
+ {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ },
+ outputs: []outputInfo{
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ },
+ },
+ },
+ {
+ name: "VDIVPSMasked256",
+ argLen: 3,
+ asm: x86.AVDIVPS,
+ reg: regInfo{
+ inputs: []inputInfo{
+ {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ },
+ outputs: []outputInfo{
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
},
{
- name: "VSUBPSMasked512",
+ name: "VDIVPSMasked512",
argLen: 3,
- asm: x86.AVSUBPS,
+ asm: x86.AVDIVPS,
reg: regInfo{
inputs: []inputInfo{
{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
},
},
{
- name: "VADDPS128",
- argLen: 2,
- commutative: true,
- asm: x86.AVADDPS,
+ name: "VFMADD213PD128",
+ argLen: 3,
+ resultInArg0: true,
+ asm: x86.AVFMADD213PD,
reg: regInfo{
inputs: []inputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
{
- name: "VADDPSMasked128",
- argLen: 3,
- commutative: true,
- asm: x86.AVADDPS,
+ name: "VFMADD213PD256",
+ argLen: 3,
+ resultInArg0: true,
+ asm: x86.AVFMADD213PD,
reg: regInfo{
inputs: []inputInfo{
- {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
{
- name: "VADDSUBPS128",
- argLen: 2,
- asm: x86.AVADDSUBPS,
+ name: "VFMADD213PD512",
+ argLen: 3,
+ resultInArg0: true,
+ asm: x86.AVFMADD213PD,
reg: regInfo{
inputs: []inputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
{
- name: "VRCPPS128",
- argLen: 1,
- asm: x86.AVRCPPS,
+ name: "VFMADD213PDMasked128",
+ argLen: 4,
+ resultInArg0: true,
+ asm: x86.AVFMADD213PD,
reg: regInfo{
inputs: []inputInfo{
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
{
- name: "VRCP14PSMasked128",
- argLen: 2,
- asm: x86.AVRCP14PS,
+ name: "VFMADD213PDMasked256",
+ argLen: 4,
+ resultInArg0: true,
+ asm: x86.AVFMADD213PD,
reg: regInfo{
inputs: []inputInfo{
- {1, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+ {3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
{
- name: "VRSQRTPS128",
- argLen: 1,
- asm: x86.AVRSQRTPS,
+ name: "VFMADD213PDMasked512",
+ argLen: 4,
+ resultInArg0: true,
+ asm: x86.AVFMADD213PD,
reg: regInfo{
inputs: []inputInfo{
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
{
- name: "VRSQRT14PSMasked128",
- argLen: 2,
- asm: x86.AVRSQRT14PS,
+ name: "VFMADD213PS128",
+ argLen: 3,
+ resultInArg0: true,
+ asm: x86.AVFMADD213PS,
reg: regInfo{
inputs: []inputInfo{
- {1, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
{
- name: "VCOMPRESSPSMasked128",
- argLen: 2,
- asm: x86.AVCOMPRESSPS,
+ name: "VFMADD213PS256",
+ argLen: 3,
+ resultInArg0: true,
+ asm: x86.AVFMADD213PS,
reg: regInfo{
inputs: []inputInfo{
- {1, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
{
- name: "VDIVPS128",
- argLen: 2,
- asm: x86.AVDIVPS,
+ name: "VFMADD213PS512",
+ argLen: 3,
+ resultInArg0: true,
+ asm: x86.AVFMADD213PS,
reg: regInfo{
inputs: []inputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
{
- name: "VDIVPSMasked128",
- argLen: 3,
- asm: x86.AVDIVPS,
+ name: "VFMADD213PSMasked128",
+ argLen: 4,
+ resultInArg0: true,
+ asm: x86.AVFMADD213PS,
reg: regInfo{
inputs: []inputInfo{
- {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+ {3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
{
- name: "VFMADD213PS128",
- argLen: 3,
+ name: "VFMADD213PSMasked256",
+ argLen: 4,
resultInArg0: true,
asm: x86.AVFMADD213PS,
reg: regInfo{
inputs: []inputInfo{
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
{
- name: "VFMADD213PSMasked128",
+ name: "VFMADD213PSMasked512",
argLen: 4,
resultInArg0: true,
asm: x86.AVFMADD213PS,
},
},
{
- name: "VFMADDSUB213PS128",
+ name: "VFMADDSUB213PD128",
argLen: 3,
resultInArg0: true,
- asm: x86.AVFMADDSUB213PS,
+ asm: x86.AVFMADDSUB213PD,
reg: regInfo{
inputs: []inputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
{
- name: "VFMADDSUB213PSMasked128",
- argLen: 4,
+ name: "VFMADDSUB213PD256",
+ argLen: 3,
resultInArg0: true,
- asm: x86.AVFMADDSUB213PS,
+ asm: x86.AVFMADDSUB213PD,
reg: regInfo{
inputs: []inputInfo{
- {3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
{
- name: "VFMSUBADD213PS128",
+ name: "VFMADDSUB213PD512",
argLen: 3,
resultInArg0: true,
- asm: x86.AVFMSUBADD213PS,
+ asm: x86.AVFMADDSUB213PD,
reg: regInfo{
inputs: []inputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
{
- name: "VFMSUBADD213PSMasked128",
+ name: "VFMADDSUB213PDMasked128",
argLen: 4,
resultInArg0: true,
- asm: x86.AVFMSUBADD213PS,
+ asm: x86.AVFMADDSUB213PD,
reg: regInfo{
inputs: []inputInfo{
{3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
},
},
{
- name: "VMAXPS128",
- argLen: 2,
- commutative: true,
- asm: x86.AVMAXPS,
+ name: "VFMADDSUB213PDMasked256",
+ argLen: 4,
+ resultInArg0: true,
+ asm: x86.AVFMADDSUB213PD,
reg: regInfo{
inputs: []inputInfo{
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
{
- name: "VMAXPSMasked128",
- argLen: 3,
- commutative: true,
- asm: x86.AVMAXPS,
+ name: "VFMADDSUB213PDMasked512",
+ argLen: 4,
+ resultInArg0: true,
+ asm: x86.AVFMADDSUB213PD,
reg: regInfo{
inputs: []inputInfo{
- {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+ {3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
{
- name: "VMINPS128",
- argLen: 2,
- commutative: true,
- asm: x86.AVMINPS,
+ name: "VFMADDSUB213PS128",
+ argLen: 3,
+ resultInArg0: true,
+ asm: x86.AVFMADDSUB213PS,
reg: regInfo{
inputs: []inputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
{
- name: "VMINPSMasked128",
- argLen: 3,
- commutative: true,
- asm: x86.AVMINPS,
+ name: "VFMADDSUB213PS256",
+ argLen: 3,
+ resultInArg0: true,
+ asm: x86.AVFMADDSUB213PS,
reg: regInfo{
inputs: []inputInfo{
- {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
{
- name: "VMULPS128",
- argLen: 2,
- commutative: true,
- asm: x86.AVMULPS,
+ name: "VFMADDSUB213PS512",
+ argLen: 3,
+ resultInArg0: true,
+ asm: x86.AVFMADDSUB213PS,
reg: regInfo{
inputs: []inputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
{
- name: "VSCALEFPS128",
- argLen: 2,
- asm: x86.AVSCALEFPS,
+ name: "VFMADDSUB213PSMasked128",
+ argLen: 4,
+ resultInArg0: true,
+ asm: x86.AVFMADDSUB213PS,
reg: regInfo{
inputs: []inputInfo{
- {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
- {1, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ {3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
- {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
},
{
- name: "VSCALEFPSMasked128",
- argLen: 3,
- asm: x86.AVSCALEFPS,
+ name: "VFMADDSUB213PSMasked256",
+ argLen: 4,
+ resultInArg0: true,
+ asm: x86.AVFMADDSUB213PS,
reg: regInfo{
inputs: []inputInfo{
- {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+ {3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
{
- name: "VMULPSMasked128",
- argLen: 3,
- commutative: true,
- asm: x86.AVMULPS,
+ name: "VFMADDSUB213PSMasked512",
+ argLen: 4,
+ resultInArg0: true,
+ asm: x86.AVFMADDSUB213PS,
reg: regInfo{
inputs: []inputInfo{
- {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+ {3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
{
- name: "VHADDPS128",
- argLen: 2,
- asm: x86.AVHADDPS,
+ name: "VFMSUBADD213PD128",
+ argLen: 3,
+ resultInArg0: true,
+ asm: x86.AVFMSUBADD213PD,
reg: regInfo{
inputs: []inputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
{
- name: "VHSUBPS128",
- argLen: 2,
- asm: x86.AVHSUBPS,
+ name: "VFMSUBADD213PD256",
+ argLen: 3,
+ resultInArg0: true,
+ asm: x86.AVFMSUBADD213PD,
reg: regInfo{
inputs: []inputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
{
- name: "VSQRTPS128",
- argLen: 1,
- asm: x86.AVSQRTPS,
+ name: "VFMSUBADD213PD512",
+ argLen: 3,
+ resultInArg0: true,
+ asm: x86.AVFMSUBADD213PD,
reg: regInfo{
inputs: []inputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
{
- name: "VSQRTPSMasked128",
- argLen: 2,
- asm: x86.AVSQRTPS,
+ name: "VFMSUBADD213PDMasked128",
+ argLen: 4,
+ resultInArg0: true,
+ asm: x86.AVFMSUBADD213PD,
reg: regInfo{
inputs: []inputInfo{
- {1, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+ {3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
{
- name: "VSUBPS128",
- argLen: 2,
- asm: x86.AVSUBPS,
+ name: "VFMSUBADD213PDMasked256",
+ argLen: 4,
+ resultInArg0: true,
+ asm: x86.AVFMSUBADD213PD,
reg: regInfo{
inputs: []inputInfo{
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
{
- name: "VSUBPSMasked128",
- argLen: 3,
- asm: x86.AVSUBPS,
+ name: "VFMSUBADD213PDMasked512",
+ argLen: 4,
+ resultInArg0: true,
+ asm: x86.AVFMSUBADD213PD,
reg: regInfo{
inputs: []inputInfo{
- {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+ {3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
{
- name: "VADDPS256",
- argLen: 2,
- commutative: true,
- asm: x86.AVADDPS,
+ name: "VFMSUBADD213PS128",
+ argLen: 3,
+ resultInArg0: true,
+ asm: x86.AVFMSUBADD213PS,
reg: regInfo{
inputs: []inputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
{
- name: "VADDPSMasked256",
- argLen: 3,
- commutative: true,
- asm: x86.AVADDPS,
+ name: "VFMSUBADD213PS256",
+ argLen: 3,
+ resultInArg0: true,
+ asm: x86.AVFMSUBADD213PS,
reg: regInfo{
inputs: []inputInfo{
- {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
{
- name: "VADDSUBPS256",
- argLen: 2,
- asm: x86.AVADDSUBPS,
+ name: "VFMSUBADD213PS512",
+ argLen: 3,
+ resultInArg0: true,
+ asm: x86.AVFMSUBADD213PS,
reg: regInfo{
inputs: []inputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
{
- name: "VRCPPS256",
- argLen: 1,
- asm: x86.AVRCPPS,
+ name: "VFMSUBADD213PSMasked128",
+ argLen: 4,
+ resultInArg0: true,
+ asm: x86.AVFMSUBADD213PS,
reg: regInfo{
inputs: []inputInfo{
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
{
- name: "VRCP14PSMasked256",
- argLen: 2,
- asm: x86.AVRCP14PS,
+ name: "VFMSUBADD213PSMasked256",
+ argLen: 4,
+ resultInArg0: true,
+ asm: x86.AVFMSUBADD213PS,
reg: regInfo{
inputs: []inputInfo{
- {1, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+ {3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
{
- name: "VRSQRTPS256",
- argLen: 1,
- asm: x86.AVRSQRTPS,
+ name: "VFMSUBADD213PSMasked512",
+ argLen: 4,
+ resultInArg0: true,
+ asm: x86.AVFMSUBADD213PS,
reg: regInfo{
inputs: []inputInfo{
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
{
- name: "VRSQRT14PSMasked256",
+ name: "VGF2P8MULB128",
argLen: 2,
- asm: x86.AVRSQRT14PS,
+ asm: x86.AVGF2P8MULB,
reg: regInfo{
inputs: []inputInfo{
- {1, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ {1, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
},
outputs: []outputInfo{
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
},
},
},
{
- name: "VCOMPRESSPSMasked256",
+ name: "VGF2P8MULB256",
argLen: 2,
- asm: x86.AVCOMPRESSPS,
+ asm: x86.AVGF2P8MULB,
reg: regInfo{
inputs: []inputInfo{
- {1, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ {1, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
},
outputs: []outputInfo{
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
},
},
},
{
- name: "VDIVPS256",
+ name: "VGF2P8MULB512",
argLen: 2,
- asm: x86.AVDIVPS,
+ asm: x86.AVGF2P8MULB,
reg: regInfo{
inputs: []inputInfo{
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ {1, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
},
outputs: []outputInfo{
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
},
},
},
{
- name: "VDIVPSMasked256",
+ name: "VGF2P8MULBMasked128",
argLen: 3,
- asm: x86.AVDIVPS,
+ asm: x86.AVGF2P8MULB,
reg: regInfo{
inputs: []inputInfo{
{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
},
},
{
- name: "VFMADD213PS256",
- argLen: 3,
- resultInArg0: true,
- asm: x86.AVFMADD213PS,
+ name: "VGF2P8MULBMasked256",
+ argLen: 3,
+ asm: x86.AVGF2P8MULB,
reg: regInfo{
inputs: []inputInfo{
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
{
- name: "VFMADD213PSMasked256",
- argLen: 4,
- resultInArg0: true,
- asm: x86.AVFMADD213PS,
+ name: "VGF2P8MULBMasked512",
+ argLen: 3,
+ asm: x86.AVGF2P8MULB,
reg: regInfo{
inputs: []inputInfo{
- {3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+ {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
{
- name: "VFMADDSUB213PS256",
- argLen: 3,
- resultInArg0: true,
- asm: x86.AVFMADDSUB213PS,
+ name: "VHADDPD128",
+ argLen: 2,
+ asm: x86.AVHADDPD,
reg: regInfo{
inputs: []inputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
{
- name: "VFMADDSUB213PSMasked256",
- argLen: 4,
- resultInArg0: true,
- asm: x86.AVFMADDSUB213PS,
+ name: "VHADDPD256",
+ argLen: 2,
+ asm: x86.AVHADDPD,
reg: regInfo{
inputs: []inputInfo{
- {3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
{
- name: "VFMSUBADD213PS256",
- argLen: 3,
- resultInArg0: true,
- asm: x86.AVFMSUBADD213PS,
+ name: "VHADDPS128",
+ argLen: 2,
+ asm: x86.AVHADDPS,
reg: regInfo{
inputs: []inputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
{
- name: "VFMSUBADD213PSMasked256",
- argLen: 4,
- resultInArg0: true,
- asm: x86.AVFMSUBADD213PS,
+ name: "VHADDPS256",
+ argLen: 2,
+ asm: x86.AVHADDPS,
reg: regInfo{
inputs: []inputInfo{
- {3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
{
- name: "VMAXPS256",
- argLen: 2,
- commutative: true,
- asm: x86.AVMAXPS,
+ name: "VHSUBPD128",
+ argLen: 2,
+ asm: x86.AVHSUBPD,
reg: regInfo{
inputs: []inputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
{
- name: "VMAXPSMasked256",
- argLen: 3,
- commutative: true,
- asm: x86.AVMAXPS,
+ name: "VHSUBPD256",
+ argLen: 2,
+ asm: x86.AVHSUBPD,
reg: regInfo{
inputs: []inputInfo{
- {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
{
- name: "VMINPS256",
- argLen: 2,
- commutative: true,
- asm: x86.AVMINPS,
+ name: "VHSUBPS128",
+ argLen: 2,
+ asm: x86.AVHSUBPS,
+ reg: regInfo{
+ inputs: []inputInfo{
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ },
+ outputs: []outputInfo{
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ },
+ },
+ },
+ {
+ name: "VHSUBPS256",
+ argLen: 2,
+ asm: x86.AVHSUBPS,
reg: regInfo{
inputs: []inputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
{
- name: "VMINPSMasked256",
- argLen: 3,
+ name: "VMAXPD128",
+ argLen: 2,
commutative: true,
- asm: x86.AVMINPS,
+ asm: x86.AVMAXPD,
reg: regInfo{
inputs: []inputInfo{
- {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
{
- name: "VMULPS256",
+ name: "VMAXPD256",
argLen: 2,
commutative: true,
- asm: x86.AVMULPS,
+ asm: x86.AVMAXPD,
reg: regInfo{
inputs: []inputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
{
- name: "VSCALEFPS256",
- argLen: 2,
- asm: x86.AVSCALEFPS,
+ name: "VMAXPD512",
+ argLen: 2,
+ commutative: true,
+ asm: x86.AVMAXPD,
reg: regInfo{
inputs: []inputInfo{
{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
},
},
{
- name: "VSCALEFPSMasked256",
- argLen: 3,
- asm: x86.AVSCALEFPS,
+ name: "VMAXPDMasked128",
+ argLen: 3,
+ commutative: true,
+ asm: x86.AVMAXPD,
reg: regInfo{
inputs: []inputInfo{
{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
},
},
{
- name: "VMULPSMasked256",
+ name: "VMAXPDMasked256",
argLen: 3,
commutative: true,
- asm: x86.AVMULPS,
+ asm: x86.AVMAXPD,
reg: regInfo{
inputs: []inputInfo{
{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
},
},
{
- name: "VHADDPS256",
- argLen: 2,
- asm: x86.AVHADDPS,
+ name: "VMAXPDMasked512",
+ argLen: 3,
+ commutative: true,
+ asm: x86.AVMAXPD,
reg: regInfo{
inputs: []inputInfo{
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
{
- name: "VHSUBPS256",
- argLen: 2,
- asm: x86.AVHSUBPS,
+ name: "VMAXPS128",
+ argLen: 2,
+ commutative: true,
+ asm: x86.AVMAXPS,
reg: regInfo{
inputs: []inputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
{
- name: "VSQRTPS256",
- argLen: 1,
- asm: x86.AVSQRTPS,
+ name: "VMAXPS256",
+ argLen: 2,
+ commutative: true,
+ asm: x86.AVMAXPS,
reg: regInfo{
inputs: []inputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
{
- name: "VSQRTPSMasked256",
- argLen: 2,
- asm: x86.AVSQRTPS,
+ name: "VMAXPS512",
+ argLen: 2,
+ commutative: true,
+ asm: x86.AVMAXPS,
reg: regInfo{
inputs: []inputInfo{
- {1, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ {1, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
},
outputs: []outputInfo{
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
},
},
},
{
- name: "VSUBPS256",
- argLen: 2,
- asm: x86.AVSUBPS,
+ name: "VMAXPSMasked128",
+ argLen: 3,
+ commutative: true,
+ asm: x86.AVMAXPS,
reg: regInfo{
inputs: []inputInfo{
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
{
- name: "VSUBPSMasked256",
- argLen: 3,
- asm: x86.AVSUBPS,
+ name: "VMAXPSMasked256",
+ argLen: 3,
+ commutative: true,
+ asm: x86.AVMAXPS,
reg: regInfo{
inputs: []inputInfo{
{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
},
},
{
- name: "VADDPD128",
- argLen: 2,
+ name: "VMAXPSMasked512",
+ argLen: 3,
commutative: true,
- asm: x86.AVADDPD,
+ asm: x86.AVMAXPS,
reg: regInfo{
inputs: []inputInfo{
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
{
- name: "VADDPDMasked128",
- argLen: 3,
+ name: "VMINPD128",
+ argLen: 2,
commutative: true,
- asm: x86.AVADDPD,
+ asm: x86.AVMINPD,
reg: regInfo{
inputs: []inputInfo{
- {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
{
- name: "VADDSUBPD128",
- argLen: 2,
- asm: x86.AVADDSUBPD,
+ name: "VMINPD256",
+ argLen: 2,
+ commutative: true,
+ asm: x86.AVMINPD,
reg: regInfo{
inputs: []inputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
{
- name: "VRCP14PD128",
- argLen: 1,
- asm: x86.AVRCP14PD,
+ name: "VMINPD512",
+ argLen: 2,
+ commutative: true,
+ asm: x86.AVMINPD,
reg: regInfo{
inputs: []inputInfo{
{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ {1, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
},
outputs: []outputInfo{
{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
},
},
{
- name: "VRCP14PDMasked128",
- argLen: 2,
- asm: x86.AVRCP14PD,
+ name: "VMINPDMasked128",
+ argLen: 3,
+ commutative: true,
+ asm: x86.AVMINPD,
reg: regInfo{
inputs: []inputInfo{
- {1, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+ {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
{
- name: "VRSQRT14PD128",
- argLen: 1,
- asm: x86.AVRSQRT14PD,
- reg: regInfo{
- inputs: []inputInfo{
- {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
- },
- outputs: []outputInfo{
- {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
- },
- },
- },
- {
- name: "VRSQRT14PDMasked128",
- argLen: 2,
- asm: x86.AVRSQRT14PD,
+ name: "VMINPDMasked256",
+ argLen: 3,
+ commutative: true,
+ asm: x86.AVMINPD,
reg: regInfo{
inputs: []inputInfo{
- {1, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+ {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
{
- name: "VCOMPRESSPDMasked128",
- argLen: 2,
- asm: x86.AVCOMPRESSPD,
+ name: "VMINPDMasked512",
+ argLen: 3,
+ commutative: true,
+ asm: x86.AVMINPD,
reg: regInfo{
inputs: []inputInfo{
- {1, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+ {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
{
- name: "VDIVPD128",
- argLen: 2,
- asm: x86.AVDIVPD,
+ name: "VMINPS128",
+ argLen: 2,
+ commutative: true,
+ asm: x86.AVMINPS,
reg: regInfo{
inputs: []inputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
{
- name: "VDIVPDMasked128",
- argLen: 3,
- asm: x86.AVDIVPD,
+ name: "VMINPS256",
+ argLen: 2,
+ commutative: true,
+ asm: x86.AVMINPS,
reg: regInfo{
inputs: []inputInfo{
- {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
{
- name: "VFMADD213PD128",
- argLen: 3,
- resultInArg0: true,
- asm: x86.AVFMADD213PD,
+ name: "VMINPS512",
+ argLen: 2,
+ commutative: true,
+ asm: x86.AVMINPS,
reg: regInfo{
inputs: []inputInfo{
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ {1, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
},
outputs: []outputInfo{
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
},
},
},
{
- name: "VFMADD213PDMasked128",
- argLen: 4,
- resultInArg0: true,
- asm: x86.AVFMADD213PD,
+ name: "VMINPSMasked128",
+ argLen: 3,
+ commutative: true,
+ asm: x86.AVMINPS,
reg: regInfo{
inputs: []inputInfo{
- {3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+ {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
{
- name: "VFMADDSUB213PD128",
- argLen: 3,
- resultInArg0: true,
- asm: x86.AVFMADDSUB213PD,
+ name: "VMINPSMasked256",
+ argLen: 3,
+ commutative: true,
+ asm: x86.AVMINPS,
reg: regInfo{
inputs: []inputInfo{
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
{
- name: "VFMADDSUB213PDMasked128",
- argLen: 4,
- resultInArg0: true,
- asm: x86.AVFMADDSUB213PD,
+ name: "VMINPSMasked512",
+ argLen: 3,
+ commutative: true,
+ asm: x86.AVMINPS,
reg: regInfo{
inputs: []inputInfo{
- {3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+ {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
{
- name: "VFMSUBADD213PD128",
- argLen: 3,
- resultInArg0: true,
- asm: x86.AVFMSUBADD213PD,
+ name: "VMULPD128",
+ argLen: 2,
+ commutative: true,
+ asm: x86.AVMULPD,
reg: regInfo{
inputs: []inputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
{
- name: "VFMSUBADD213PDMasked128",
- argLen: 4,
- resultInArg0: true,
- asm: x86.AVFMSUBADD213PD,
+ name: "VMULPD256",
+ argLen: 2,
+ commutative: true,
+ asm: x86.AVMULPD,
reg: regInfo{
inputs: []inputInfo{
- {3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
{
- name: "VMAXPD128",
+ name: "VMULPD512",
argLen: 2,
commutative: true,
- asm: x86.AVMAXPD,
+ asm: x86.AVMULPD,
reg: regInfo{
inputs: []inputInfo{
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ {1, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
},
outputs: []outputInfo{
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
},
},
},
{
- name: "VMAXPDMasked128",
+ name: "VMULPDMasked128",
argLen: 3,
commutative: true,
- asm: x86.AVMAXPD,
+ asm: x86.AVMULPD,
reg: regInfo{
inputs: []inputInfo{
{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
},
},
{
- name: "VMINPD128",
- argLen: 2,
+ name: "VMULPDMasked256",
+ argLen: 3,
commutative: true,
- asm: x86.AVMINPD,
+ asm: x86.AVMULPD,
reg: regInfo{
inputs: []inputInfo{
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
{
- name: "VMINPDMasked128",
+ name: "VMULPDMasked512",
argLen: 3,
commutative: true,
- asm: x86.AVMINPD,
+ asm: x86.AVMULPD,
reg: regInfo{
inputs: []inputInfo{
{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
},
},
{
- name: "VMULPD128",
+ name: "VMULPS128",
argLen: 2,
commutative: true,
- asm: x86.AVMULPD,
+ asm: x86.AVMULPS,
reg: regInfo{
inputs: []inputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
{
- name: "VSCALEFPD128",
- argLen: 2,
- asm: x86.AVSCALEFPD,
+ name: "VMULPS256",
+ argLen: 2,
+ commutative: true,
+ asm: x86.AVMULPS,
reg: regInfo{
inputs: []inputInfo{
- {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
- {1, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
- {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
},
{
- name: "VSCALEFPDMasked128",
- argLen: 3,
- asm: x86.AVSCALEFPD,
+ name: "VMULPS512",
+ argLen: 2,
+ commutative: true,
+ asm: x86.AVMULPS,
reg: regInfo{
inputs: []inputInfo{
- {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ {1, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
},
outputs: []outputInfo{
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
},
},
},
{
- name: "VMULPDMasked128",
+ name: "VMULPSMasked128",
argLen: 3,
commutative: true,
- asm: x86.AVMULPD,
+ asm: x86.AVMULPS,
reg: regInfo{
inputs: []inputInfo{
{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
},
},
{
- name: "VHADDPD128",
- argLen: 2,
- asm: x86.AVHADDPD,
+ name: "VMULPSMasked256",
+ argLen: 3,
+ commutative: true,
+ asm: x86.AVMULPS,
reg: regInfo{
inputs: []inputInfo{
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
{
- name: "VHSUBPD128",
- argLen: 2,
- asm: x86.AVHSUBPD,
+ name: "VMULPSMasked512",
+ argLen: 3,
+ commutative: true,
+ asm: x86.AVMULPS,
reg: regInfo{
inputs: []inputInfo{
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
{
- name: "VSQRTPD128",
+ name: "VPABSB128",
argLen: 1,
- asm: x86.AVSQRTPD,
+ asm: x86.AVPABSB,
reg: regInfo{
inputs: []inputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
{
- name: "VSQRTPDMasked128",
- argLen: 2,
- asm: x86.AVSQRTPD,
+ name: "VPABSB256",
+ argLen: 1,
+ asm: x86.AVPABSB,
reg: regInfo{
inputs: []inputInfo{
- {1, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
{
- name: "VSUBPD128",
- argLen: 2,
- asm: x86.AVSUBPD,
+ name: "VPABSB512",
+ argLen: 1,
+ asm: x86.AVPABSB,
reg: regInfo{
inputs: []inputInfo{
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
},
outputs: []outputInfo{
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
},
},
},
{
- name: "VSUBPDMasked128",
- argLen: 3,
- asm: x86.AVSUBPD,
+ name: "VPABSBMasked128",
+ argLen: 2,
+ asm: x86.AVPABSB,
reg: regInfo{
inputs: []inputInfo{
- {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+ {1, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
{
- name: "VADDPD256",
- argLen: 2,
- commutative: true,
- asm: x86.AVADDPD,
+ name: "VPABSBMasked256",
+ argLen: 2,
+ asm: x86.AVPABSB,
reg: regInfo{
inputs: []inputInfo{
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {1, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
{
- name: "VADDPDMasked256",
- argLen: 3,
- commutative: true,
- asm: x86.AVADDPD,
+ name: "VPABSBMasked512",
+ argLen: 2,
+ asm: x86.AVPABSB,
reg: regInfo{
inputs: []inputInfo{
- {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+ {1, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
{
- name: "VADDSUBPD256",
- argLen: 2,
- asm: x86.AVADDSUBPD,
+ name: "VPABSD128",
+ argLen: 1,
+ asm: x86.AVPABSD,
reg: regInfo{
inputs: []inputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
{
- name: "VRCP14PD256",
+ name: "VPABSD256",
argLen: 1,
- asm: x86.AVRCP14PD,
- reg: regInfo{
- inputs: []inputInfo{
- {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
- },
- outputs: []outputInfo{
- {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
- },
- },
- },
- {
- name: "VRCP14PDMasked256",
- argLen: 2,
- asm: x86.AVRCP14PD,
+ asm: x86.AVPABSD,
reg: regInfo{
inputs: []inputInfo{
- {1, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
{
- name: "VRSQRT14PD256",
+ name: "VPABSD512",
argLen: 1,
- asm: x86.AVRSQRT14PD,
+ asm: x86.AVPABSD,
reg: regInfo{
inputs: []inputInfo{
{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
},
},
{
- name: "VRSQRT14PDMasked256",
+ name: "VPABSDMasked128",
argLen: 2,
- asm: x86.AVRSQRT14PD,
+ asm: x86.AVPABSD,
reg: regInfo{
inputs: []inputInfo{
{1, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
},
},
{
- name: "VCOMPRESSPDMasked256",
+ name: "VPABSDMasked256",
argLen: 2,
- asm: x86.AVCOMPRESSPD,
+ asm: x86.AVPABSD,
reg: regInfo{
inputs: []inputInfo{
{1, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
},
},
{
- name: "VDIVPD256",
+ name: "VPABSDMasked512",
argLen: 2,
- asm: x86.AVDIVPD,
- reg: regInfo{
- inputs: []inputInfo{
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- },
- outputs: []outputInfo{
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- },
- },
- },
- {
- name: "VDIVPDMasked256",
- argLen: 3,
- asm: x86.AVDIVPD,
+ asm: x86.AVPABSD,
reg: regInfo{
inputs: []inputInfo{
- {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+ {1, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
{
- name: "VFMADD213PD256",
- argLen: 3,
- resultInArg0: true,
- asm: x86.AVFMADD213PD,
+ name: "VPABSQ128",
+ argLen: 1,
+ asm: x86.AVPABSQ,
reg: regInfo{
inputs: []inputInfo{
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
},
outputs: []outputInfo{
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
},
},
},
{
- name: "VFMADD213PDMasked256",
- argLen: 4,
- resultInArg0: true,
- asm: x86.AVFMADD213PD,
+ name: "VPABSQ256",
+ argLen: 1,
+ asm: x86.AVPABSQ,
reg: regInfo{
inputs: []inputInfo{
- {3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
},
outputs: []outputInfo{
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
},
},
},
{
- name: "VFMADDSUB213PD256",
- argLen: 3,
- resultInArg0: true,
- asm: x86.AVFMADDSUB213PD,
+ name: "VPABSQ512",
+ argLen: 1,
+ asm: x86.AVPABSQ,
reg: regInfo{
inputs: []inputInfo{
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
},
outputs: []outputInfo{
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
},
},
},
{
- name: "VFMADDSUB213PDMasked256",
- argLen: 4,
- resultInArg0: true,
- asm: x86.AVFMADDSUB213PD,
+ name: "VPABSQMasked128",
+ argLen: 2,
+ asm: x86.AVPABSQ,
reg: regInfo{
inputs: []inputInfo{
- {3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+ {1, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
{
- name: "VFMSUBADD213PD256",
- argLen: 3,
- resultInArg0: true,
- asm: x86.AVFMSUBADD213PD,
+ name: "VPABSQMasked256",
+ argLen: 2,
+ asm: x86.AVPABSQ,
reg: regInfo{
inputs: []inputInfo{
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {1, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
{
- name: "VFMSUBADD213PDMasked256",
- argLen: 4,
- resultInArg0: true,
- asm: x86.AVFMSUBADD213PD,
+ name: "VPABSQMasked512",
+ argLen: 2,
+ asm: x86.AVPABSQ,
reg: regInfo{
inputs: []inputInfo{
- {3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+ {1, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
{
- name: "VMAXPD256",
- argLen: 2,
- commutative: true,
- asm: x86.AVMAXPD,
+ name: "VPABSW128",
+ argLen: 1,
+ asm: x86.AVPABSW,
reg: regInfo{
inputs: []inputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
{
- name: "VMAXPDMasked256",
- argLen: 3,
- commutative: true,
- asm: x86.AVMAXPD,
+ name: "VPABSW256",
+ argLen: 1,
+ asm: x86.AVPABSW,
reg: regInfo{
inputs: []inputInfo{
- {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
{
- name: "VMINPD256",
- argLen: 2,
- commutative: true,
- asm: x86.AVMINPD,
+ name: "VPABSW512",
+ argLen: 1,
+ asm: x86.AVPABSW,
reg: regInfo{
inputs: []inputInfo{
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
},
outputs: []outputInfo{
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
},
},
},
{
- name: "VMINPDMasked256",
- argLen: 3,
- commutative: true,
- asm: x86.AVMINPD,
+ name: "VPABSWMasked128",
+ argLen: 2,
+ asm: x86.AVPABSW,
reg: regInfo{
inputs: []inputInfo{
- {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+ {1, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
{
- name: "VMULPD256",
- argLen: 2,
- commutative: true,
- asm: x86.AVMULPD,
+ name: "VPABSWMasked256",
+ argLen: 2,
+ asm: x86.AVPABSW,
reg: regInfo{
inputs: []inputInfo{
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {1, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
{
- name: "VSCALEFPD256",
+ name: "VPABSWMasked512",
argLen: 2,
- asm: x86.AVSCALEFPD,
+ asm: x86.AVPABSW,
reg: regInfo{
inputs: []inputInfo{
- {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
- {1, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ {1, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
- {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
},
{
- name: "VSCALEFPDMasked256",
- argLen: 3,
- asm: x86.AVSCALEFPD,
+ name: "VPADDB128",
+ argLen: 2,
+ commutative: true,
+ asm: x86.AVPADDB,
reg: regInfo{
inputs: []inputInfo{
- {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
{
- name: "VMULPDMasked256",
- argLen: 3,
+ name: "VPADDB256",
+ argLen: 2,
commutative: true,
- asm: x86.AVMULPD,
+ asm: x86.AVPADDB,
reg: regInfo{
inputs: []inputInfo{
- {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
{
- name: "VHADDPD256",
- argLen: 2,
- asm: x86.AVHADDPD,
+ name: "VPADDB512",
+ argLen: 2,
+ commutative: true,
+ asm: x86.AVPADDB,
reg: regInfo{
inputs: []inputInfo{
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ {1, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
},
outputs: []outputInfo{
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
},
},
},
{
- name: "VHSUBPD256",
- argLen: 2,
- asm: x86.AVHSUBPD,
+ name: "VPADDBMasked128",
+ argLen: 3,
+ commutative: true,
+ asm: x86.AVPADDB,
reg: regInfo{
inputs: []inputInfo{
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
{
- name: "VSQRTPD256",
- argLen: 1,
- asm: x86.AVSQRTPD,
+ name: "VPADDBMasked256",
+ argLen: 3,
+ commutative: true,
+ asm: x86.AVPADDB,
reg: regInfo{
inputs: []inputInfo{
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
{
- name: "VSQRTPDMasked256",
- argLen: 2,
- asm: x86.AVSQRTPD,
+ name: "VPADDBMasked512",
+ argLen: 3,
+ commutative: true,
+ asm: x86.AVPADDB,
reg: regInfo{
inputs: []inputInfo{
- {1, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+ {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
{
- name: "VSUBPD256",
- argLen: 2,
- asm: x86.AVSUBPD,
+ name: "VPADDD128",
+ argLen: 2,
+ commutative: true,
+ asm: x86.AVPADDD,
reg: regInfo{
inputs: []inputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
{
- name: "VSUBPDMasked256",
- argLen: 3,
- asm: x86.AVSUBPD,
+ name: "VPADDD256",
+ argLen: 2,
+ commutative: true,
+ asm: x86.AVPADDD,
reg: regInfo{
inputs: []inputInfo{
- {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
{
- name: "VADDPD512",
+ name: "VPADDD512",
argLen: 2,
commutative: true,
- asm: x86.AVADDPD,
+ asm: x86.AVPADDD,
reg: regInfo{
inputs: []inputInfo{
{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
},
},
{
- name: "VADDPDMasked512",
+ name: "VPADDDMasked128",
argLen: 3,
commutative: true,
- asm: x86.AVADDPD,
+ asm: x86.AVPADDD,
reg: regInfo{
inputs: []inputInfo{
{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
},
},
{
- name: "VRCP14PD512",
- argLen: 1,
- asm: x86.AVRCP14PD,
- reg: regInfo{
- inputs: []inputInfo{
- {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
- },
- outputs: []outputInfo{
- {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
- },
- },
- },
- {
- name: "VRCP14PDMasked512",
- argLen: 2,
- asm: x86.AVRCP14PD,
+ name: "VPADDDMasked256",
+ argLen: 3,
+ commutative: true,
+ asm: x86.AVPADDD,
reg: regInfo{
inputs: []inputInfo{
- {1, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+ {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
{
- name: "VRSQRT14PD512",
- argLen: 1,
- asm: x86.AVRSQRT14PD,
+ name: "VPADDDMasked512",
+ argLen: 3,
+ commutative: true,
+ asm: x86.AVPADDD,
reg: regInfo{
inputs: []inputInfo{
- {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
- {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
},
{
- name: "VRSQRT14PDMasked512",
- argLen: 2,
- asm: x86.AVRSQRT14PD,
+ name: "VPADDQ128",
+ argLen: 2,
+ commutative: true,
+ asm: x86.AVPADDQ,
reg: regInfo{
inputs: []inputInfo{
- {1, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
{
- name: "VCOMPRESSPDMasked512",
- argLen: 2,
- asm: x86.AVCOMPRESSPD,
+ name: "VPADDQ256",
+ argLen: 2,
+ commutative: true,
+ asm: x86.AVPADDQ,
reg: regInfo{
inputs: []inputInfo{
- {1, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
{
- name: "VDIVPD512",
- argLen: 2,
- asm: x86.AVDIVPD,
+ name: "VPADDQ512",
+ argLen: 2,
+ commutative: true,
+ asm: x86.AVPADDQ,
reg: regInfo{
inputs: []inputInfo{
{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
},
},
{
- name: "VDIVPDMasked512",
- argLen: 3,
- asm: x86.AVDIVPD,
+ name: "VPADDQMasked128",
+ argLen: 3,
+ commutative: true,
+ asm: x86.AVPADDQ,
reg: regInfo{
inputs: []inputInfo{
{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
},
},
{
- name: "VFMADD213PD512",
- argLen: 3,
- resultInArg0: true,
- asm: x86.AVFMADD213PD,
+ name: "VPADDQMasked256",
+ argLen: 3,
+ commutative: true,
+ asm: x86.AVPADDQ,
reg: regInfo{
inputs: []inputInfo{
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
{
- name: "VFMADD213PDMasked512",
- argLen: 4,
- resultInArg0: true,
- asm: x86.AVFMADD213PD,
+ name: "VPADDQMasked512",
+ argLen: 3,
+ commutative: true,
+ asm: x86.AVPADDQ,
reg: regInfo{
inputs: []inputInfo{
- {3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+ {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
{
- name: "VFMADDSUB213PD512",
- argLen: 3,
- resultInArg0: true,
- asm: x86.AVFMADDSUB213PD,
+ name: "VPADDSB128",
+ argLen: 2,
+ commutative: true,
+ asm: x86.AVPADDSB,
reg: regInfo{
inputs: []inputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
{
- name: "VFMADDSUB213PDMasked512",
- argLen: 4,
- resultInArg0: true,
- asm: x86.AVFMADDSUB213PD,
+ name: "VPADDSB256",
+ argLen: 2,
+ commutative: true,
+ asm: x86.AVPADDSB,
reg: regInfo{
inputs: []inputInfo{
- {3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
{
- name: "VFMSUBADD213PD512",
- argLen: 3,
- resultInArg0: true,
- asm: x86.AVFMSUBADD213PD,
+ name: "VPADDSB512",
+ argLen: 2,
+ commutative: true,
+ asm: x86.AVPADDSB,
reg: regInfo{
inputs: []inputInfo{
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ {1, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
},
outputs: []outputInfo{
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
},
},
},
{
- name: "VFMSUBADD213PDMasked512",
- argLen: 4,
- resultInArg0: true,
- asm: x86.AVFMSUBADD213PD,
+ name: "VPADDSBMasked128",
+ argLen: 3,
+ commutative: true,
+ asm: x86.AVPADDSB,
reg: regInfo{
inputs: []inputInfo{
- {3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+ {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
{
- name: "VMAXPD512",
- argLen: 2,
+ name: "VPADDSBMasked256",
+ argLen: 3,
commutative: true,
- asm: x86.AVMAXPD,
+ asm: x86.AVPADDSB,
reg: regInfo{
inputs: []inputInfo{
- {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
- {1, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
- {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
},
{
- name: "VMAXPDMasked512",
+ name: "VPADDSBMasked512",
argLen: 3,
commutative: true,
- asm: x86.AVMAXPD,
+ asm: x86.AVPADDSB,
reg: regInfo{
inputs: []inputInfo{
{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
},
},
{
- name: "VMINPD512",
+ name: "VPADDSW128",
argLen: 2,
commutative: true,
- asm: x86.AVMINPD,
+ asm: x86.AVPADDSW,
reg: regInfo{
inputs: []inputInfo{
- {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
- {1, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
- {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
},
{
- name: "VMINPDMasked512",
- argLen: 3,
+ name: "VPADDSW256",
+ argLen: 2,
commutative: true,
- asm: x86.AVMINPD,
+ asm: x86.AVPADDSW,
reg: regInfo{
inputs: []inputInfo{
- {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
{
- name: "VMULPD512",
+ name: "VPADDSW512",
argLen: 2,
commutative: true,
- asm: x86.AVMULPD,
+ asm: x86.AVPADDSW,
reg: regInfo{
inputs: []inputInfo{
{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
},
},
{
- name: "VSCALEFPD512",
- argLen: 2,
- asm: x86.AVSCALEFPD,
+ name: "VPADDSWMasked128",
+ argLen: 3,
+ commutative: true,
+ asm: x86.AVPADDSW,
reg: regInfo{
inputs: []inputInfo{
- {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
- {1, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
- {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
},
{
- name: "VSCALEFPDMasked512",
- argLen: 3,
- asm: x86.AVSCALEFPD,
+ name: "VPADDSWMasked256",
+ argLen: 3,
+ commutative: true,
+ asm: x86.AVPADDSW,
reg: regInfo{
inputs: []inputInfo{
{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
},
},
{
- name: "VMULPDMasked512",
+ name: "VPADDSWMasked512",
argLen: 3,
commutative: true,
- asm: x86.AVMULPD,
+ asm: x86.AVPADDSW,
reg: regInfo{
inputs: []inputInfo{
{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
},
},
{
- name: "VSQRTPD512",
- argLen: 1,
- asm: x86.AVSQRTPD,
+ name: "VPADDW128",
+ argLen: 2,
+ commutative: true,
+ asm: x86.AVPADDW,
reg: regInfo{
inputs: []inputInfo{
- {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
- {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
},
{
- name: "VSQRTPDMasked512",
- argLen: 2,
- asm: x86.AVSQRTPD,
+ name: "VPADDW256",
+ argLen: 2,
+ commutative: true,
+ asm: x86.AVPADDW,
reg: regInfo{
inputs: []inputInfo{
- {1, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
{
- name: "VSUBPD512",
- argLen: 2,
- asm: x86.AVSUBPD,
+ name: "VPADDW512",
+ argLen: 2,
+ commutative: true,
+ asm: x86.AVPADDW,
reg: regInfo{
inputs: []inputInfo{
{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
},
},
{
- name: "VSUBPDMasked512",
- argLen: 3,
- asm: x86.AVSUBPD,
+ name: "VPADDWMasked128",
+ argLen: 3,
+ commutative: true,
+ asm: x86.AVPADDW,
reg: regInfo{
inputs: []inputInfo{
{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
},
},
{
- name: "VPABSW256",
- argLen: 1,
- asm: x86.AVPABSW,
+ name: "VPADDWMasked256",
+ argLen: 3,
+ commutative: true,
+ asm: x86.AVPADDW,
reg: regInfo{
inputs: []inputInfo{
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
{
- name: "VPABSWMasked256",
- argLen: 2,
- asm: x86.AVPABSW,
+ name: "VPADDWMasked512",
+ argLen: 3,
+ commutative: true,
+ asm: x86.AVPADDW,
reg: regInfo{
inputs: []inputInfo{
- {1, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+ {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
{
- name: "VPADDW256",
+ name: "VPAND128",
argLen: 2,
commutative: true,
- asm: x86.AVPADDW,
+ asm: x86.AVPAND,
reg: regInfo{
inputs: []inputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
{
- name: "VPADDWMasked256",
- argLen: 3,
+ name: "VPAND256",
+ argLen: 2,
commutative: true,
- asm: x86.AVPADDW,
+ asm: x86.AVPAND,
reg: regInfo{
inputs: []inputInfo{
- {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- },
- outputs: []outputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- },
- },
- },
- {
- name: "VPCOMPRESSWMasked256",
- argLen: 2,
- asm: x86.AVPCOMPRESSW,
- reg: regInfo{
- inputs: []inputInfo{
- {1, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
{
- name: "VPCMPEQW256",
+ name: "VPANDD512",
argLen: 2,
commutative: true,
- asm: x86.AVPCMPEQW,
+ asm: x86.AVPANDD,
reg: regInfo{
inputs: []inputInfo{
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ {1, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
},
outputs: []outputInfo{
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
},
},
},
{
- name: "VPCMPGTW256",
- argLen: 2,
- asm: x86.AVPCMPGTW,
+ name: "VPANDDMasked128",
+ argLen: 3,
+ commutative: true,
+ asm: x86.AVPANDD,
reg: regInfo{
inputs: []inputInfo{
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
{
- name: "VPMAXSW256",
- argLen: 2,
+ name: "VPANDDMasked256",
+ argLen: 3,
commutative: true,
- asm: x86.AVPMAXSW,
+ asm: x86.AVPANDD,
reg: regInfo{
inputs: []inputInfo{
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
{
- name: "VPMAXSWMasked256",
+ name: "VPANDDMasked512",
argLen: 3,
commutative: true,
- asm: x86.AVPMAXSW,
+ asm: x86.AVPANDD,
reg: regInfo{
inputs: []inputInfo{
{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
},
},
{
- name: "VPMINSW256",
- argLen: 2,
- commutative: true,
- asm: x86.AVPMINSW,
+ name: "VPANDN128",
+ argLen: 2,
+ asm: x86.AVPANDN,
reg: regInfo{
inputs: []inputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
{
- name: "VPMINSWMasked256",
- argLen: 3,
- commutative: true,
- asm: x86.AVPMINSW,
+ name: "VPANDN256",
+ argLen: 2,
+ asm: x86.AVPANDN,
reg: regInfo{
inputs: []inputInfo{
- {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
{
- name: "VPMULHW256",
- argLen: 2,
- commutative: true,
- asm: x86.AVPMULHW,
+ name: "VPANDND512",
+ argLen: 2,
+ asm: x86.AVPANDND,
reg: regInfo{
inputs: []inputInfo{
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ {1, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
},
outputs: []outputInfo{
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
},
},
},
{
- name: "VPMULHWMasked256",
- argLen: 3,
- commutative: true,
- asm: x86.AVPMULHW,
+ name: "VPANDNDMasked128",
+ argLen: 3,
+ asm: x86.AVPANDND,
reg: regInfo{
inputs: []inputInfo{
{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
},
},
{
- name: "VPMULLW256",
- argLen: 2,
- commutative: true,
- asm: x86.AVPMULLW,
+ name: "VPANDNDMasked256",
+ argLen: 3,
+ asm: x86.AVPANDND,
reg: regInfo{
inputs: []inputInfo{
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
{
- name: "VPMULLWMasked256",
- argLen: 3,
- commutative: true,
- asm: x86.AVPMULLW,
+ name: "VPANDNDMasked512",
+ argLen: 3,
+ asm: x86.AVPANDND,
reg: regInfo{
inputs: []inputInfo{
{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
},
},
{
- name: "VPMADDWD256",
+ name: "VPANDNQ512",
argLen: 2,
- asm: x86.AVPMADDWD,
+ asm: x86.AVPANDNQ,
reg: regInfo{
inputs: []inputInfo{
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ {1, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
},
outputs: []outputInfo{
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
},
},
},
{
- name: "VPMADDWDMasked256",
+ name: "VPANDNQMasked128",
argLen: 3,
- asm: x86.AVPMADDWD,
+ asm: x86.AVPANDNQ,
reg: regInfo{
inputs: []inputInfo{
{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
},
},
{
- name: "VPHADDW256",
- argLen: 2,
- asm: x86.AVPHADDW,
+ name: "VPANDNQMasked256",
+ argLen: 3,
+ asm: x86.AVPANDNQ,
reg: regInfo{
inputs: []inputInfo{
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
{
- name: "VPHSUBW256",
- argLen: 2,
- asm: x86.AVPHSUBW,
+ name: "VPANDNQMasked512",
+ argLen: 3,
+ asm: x86.AVPANDNQ,
reg: regInfo{
inputs: []inputInfo{
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
{
- name: "VPOPCNTW256",
- argLen: 1,
- asm: x86.AVPOPCNTW,
+ name: "VPANDQ512",
+ argLen: 2,
+ commutative: true,
+ asm: x86.AVPANDQ,
reg: regInfo{
inputs: []inputInfo{
{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ {1, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
},
outputs: []outputInfo{
{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
},
},
{
- name: "VPOPCNTWMasked256",
- argLen: 2,
- asm: x86.AVPOPCNTW,
+ name: "VPANDQMasked128",
+ argLen: 3,
+ commutative: true,
+ asm: x86.AVPANDQ,
reg: regInfo{
inputs: []inputInfo{
- {1, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+ {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
{
- name: "VPADDSW256",
- argLen: 2,
+ name: "VPANDQMasked256",
+ argLen: 3,
commutative: true,
- asm: x86.AVPADDSW,
+ asm: x86.AVPANDQ,
reg: regInfo{
inputs: []inputInfo{
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
{
- name: "VPADDSWMasked256",
+ name: "VPANDQMasked512",
argLen: 3,
commutative: true,
- asm: x86.AVPADDSW,
+ asm: x86.AVPANDQ,
reg: regInfo{
inputs: []inputInfo{
{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
},
},
{
- name: "VPHADDSW256",
- argLen: 2,
- asm: x86.AVPHADDSW,
+ name: "VPAVGB128",
+ argLen: 2,
+ commutative: true,
+ asm: x86.AVPAVGB,
reg: regInfo{
inputs: []inputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
{
- name: "VPHSUBSW256",
- argLen: 2,
- asm: x86.AVPHSUBSW,
+ name: "VPAVGB256",
+ argLen: 2,
+ commutative: true,
+ asm: x86.AVPAVGB,
reg: regInfo{
inputs: []inputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
{
- name: "VPSUBSW256",
- argLen: 2,
- asm: x86.AVPSUBSW,
+ name: "VPAVGB512",
+ argLen: 2,
+ commutative: true,
+ asm: x86.AVPAVGB,
reg: regInfo{
inputs: []inputInfo{
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ {1, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
},
outputs: []outputInfo{
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
},
},
},
{
- name: "VPSUBSWMasked256",
- argLen: 3,
- asm: x86.AVPSUBSW,
+ name: "VPAVGBMasked128",
+ argLen: 3,
+ commutative: true,
+ asm: x86.AVPAVGB,
reg: regInfo{
inputs: []inputInfo{
{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
},
},
{
- name: "VPSLLW256",
- argLen: 2,
- asm: x86.AVPSLLW,
+ name: "VPAVGBMasked256",
+ argLen: 3,
+ commutative: true,
+ asm: x86.AVPAVGB,
reg: regInfo{
inputs: []inputInfo{
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
{
- name: "VPSLLWMasked256",
- argLen: 3,
- asm: x86.AVPSLLW,
+ name: "VPAVGBMasked512",
+ argLen: 3,
+ commutative: true,
+ asm: x86.AVPAVGB,
reg: regInfo{
inputs: []inputInfo{
{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
},
outputs: []outputInfo{
- {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
},
{
- name: "VPSRAW256",
- argLen: 2,
- asm: x86.AVPSRAW,
+ name: "VPAVGW128",
+ argLen: 2,
+ commutative: true,
+ asm: x86.AVPAVGW,
reg: regInfo{
inputs: []inputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
{
- name: "VPSRAWMasked256",
- argLen: 3,
- asm: x86.AVPSRAW,
+ name: "VPAVGW256",
+ argLen: 2,
+ commutative: true,
+ asm: x86.AVPAVGW,
reg: regInfo{
inputs: []inputInfo{
- {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
- {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
- {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
},
{
- name: "VPSLLVW256",
- argLen: 2,
- asm: x86.AVPSLLVW,
+ name: "VPAVGW512",
+ argLen: 2,
+ commutative: true,
+ asm: x86.AVPAVGW,
reg: regInfo{
inputs: []inputInfo{
{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
},
},
{
- name: "VPSHLDVW256",
- argLen: 3,
- resultInArg0: true,
- asm: x86.AVPSHLDVW,
+ name: "VPAVGWMasked128",
+ argLen: 3,
+ commutative: true,
+ asm: x86.AVPAVGW,
reg: regInfo{
inputs: []inputInfo{
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
{
- name: "VPSHLDVWMasked256",
- argLen: 4,
- resultInArg0: true,
- asm: x86.AVPSHLDVW,
+ name: "VPAVGWMasked256",
+ argLen: 3,
+ commutative: true,
+ asm: x86.AVPAVGW,
reg: regInfo{
inputs: []inputInfo{
- {3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+ {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
{
- name: "VPSLLVWMasked256",
- argLen: 3,
- asm: x86.AVPSLLVW,
+ name: "VPAVGWMasked512",
+ argLen: 3,
+ commutative: true,
+ asm: x86.AVPAVGW,
reg: regInfo{
inputs: []inputInfo{
{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
},
},
{
- name: "VPSRAVW256",
- argLen: 2,
- asm: x86.AVPSRAVW,
- reg: regInfo{
- inputs: []inputInfo{
- {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
- {1, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
- },
- outputs: []outputInfo{
- {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
- },
- },
- },
- {
- name: "VPSHRDVW256",
- argLen: 3,
- resultInArg0: true,
- asm: x86.AVPSHRDVW,
+ name: "VPCMPEQB128",
+ argLen: 2,
+ commutative: true,
+ asm: x86.AVPCMPEQB,
reg: regInfo{
inputs: []inputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
{
- name: "VPSHRDVWMasked256",
- argLen: 4,
- resultInArg0: true,
- asm: x86.AVPSHRDVW,
+ name: "VPCMPEQB256",
+ argLen: 2,
+ commutative: true,
+ asm: x86.AVPCMPEQB,
reg: regInfo{
inputs: []inputInfo{
- {3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
{
- name: "VPSRAVWMasked256",
- argLen: 3,
- asm: x86.AVPSRAVW,
+ name: "VPCMPEQB512",
+ argLen: 2,
+ commutative: true,
+ asm: x86.AVPCMPEQB,
reg: regInfo{
inputs: []inputInfo{
- {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {0, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
},
},
},
{
- name: "VPSIGNW256",
- argLen: 2,
- asm: x86.AVPSIGNW,
+ name: "VPCMPEQD128",
+ argLen: 2,
+ commutative: true,
+ asm: x86.AVPCMPEQD,
reg: regInfo{
inputs: []inputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
{
- name: "VPSUBW256",
- argLen: 2,
- asm: x86.AVPSUBW,
+ name: "VPCMPEQD256",
+ argLen: 2,
+ commutative: true,
+ asm: x86.AVPCMPEQD,
reg: regInfo{
inputs: []inputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
{
- name: "VPSUBWMasked256",
- argLen: 3,
- asm: x86.AVPSUBW,
+ name: "VPCMPEQD512",
+ argLen: 2,
+ commutative: true,
+ asm: x86.AVPCMPEQD,
reg: regInfo{
inputs: []inputInfo{
- {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {0, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
},
},
},
{
- name: "VPABSW512",
- argLen: 1,
- asm: x86.AVPABSW,
+ name: "VPCMPEQQ128",
+ argLen: 2,
+ commutative: true,
+ asm: x86.AVPCMPEQQ,
reg: regInfo{
inputs: []inputInfo{
- {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
- {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
},
{
- name: "VPABSWMasked512",
- argLen: 2,
- asm: x86.AVPABSW,
+ name: "VPCMPEQQ256",
+ argLen: 2,
+ commutative: true,
+ asm: x86.AVPCMPEQQ,
reg: regInfo{
inputs: []inputInfo{
- {1, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
{
- name: "VPADDW512",
+ name: "VPCMPEQQ512",
argLen: 2,
commutative: true,
- asm: x86.AVPADDW,
+ asm: x86.AVPCMPEQQ,
reg: regInfo{
inputs: []inputInfo{
- {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
- {1, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
- {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ {0, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
},
},
},
{
- name: "VPADDWMasked512",
- argLen: 3,
+ name: "VPCMPEQW128",
+ argLen: 2,
commutative: true,
- asm: x86.AVPADDW,
+ asm: x86.AVPCMPEQW,
reg: regInfo{
inputs: []inputInfo{
- {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
{
- name: "VPCOMPRESSWMasked512",
- argLen: 2,
- asm: x86.AVPCOMPRESSW,
+ name: "VPCMPEQW256",
+ argLen: 2,
+ commutative: true,
+ asm: x86.AVPCMPEQW,
reg: regInfo{
inputs: []inputInfo{
- {1, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
{
- name: "VPCMPGTW512",
+ name: "VPCMPGTB128",
argLen: 2,
- asm: x86.AVPCMPGTW,
+ asm: x86.AVPCMPGTB,
reg: regInfo{
inputs: []inputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
- {0, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
},
{
- name: "VPMAXSW512",
- argLen: 2,
- commutative: true,
- asm: x86.AVPMAXSW,
+ name: "VPCMPGTB256",
+ argLen: 2,
+ asm: x86.AVPCMPGTB,
reg: regInfo{
inputs: []inputInfo{
- {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
- {1, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
- {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
},
{
- name: "VPMAXSWMasked512",
- argLen: 3,
- commutative: true,
- asm: x86.AVPMAXSW,
+ name: "VPCMPGTB512",
+ argLen: 2,
+ asm: x86.AVPCMPGTB,
reg: regInfo{
inputs: []inputInfo{
- {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {0, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
},
},
},
{
- name: "VPMINSW512",
- argLen: 2,
- commutative: true,
- asm: x86.AVPMINSW,
+ name: "VPCMPGTD128",
+ argLen: 2,
+ asm: x86.AVPCMPGTD,
reg: regInfo{
inputs: []inputInfo{
- {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
- {1, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
- {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
},
{
- name: "VPMINSWMasked512",
- argLen: 3,
- commutative: true,
- asm: x86.AVPMINSW,
+ name: "VPCMPGTD256",
+ argLen: 2,
+ asm: x86.AVPCMPGTD,
reg: regInfo{
inputs: []inputInfo{
- {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
{
- name: "VPMULHW512",
- argLen: 2,
- commutative: true,
- asm: x86.AVPMULHW,
+ name: "VPCMPGTD512",
+ argLen: 2,
+ asm: x86.AVPCMPGTD,
reg: regInfo{
inputs: []inputInfo{
- {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
- {1, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
- {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ {0, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
},
},
},
{
- name: "VPMULHWMasked512",
- argLen: 3,
- commutative: true,
- asm: x86.AVPMULHW,
+ name: "VPCMPGTQ128",
+ argLen: 2,
+ asm: x86.AVPCMPGTQ,
reg: regInfo{
inputs: []inputInfo{
- {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
{
- name: "VPMULLW512",
- argLen: 2,
- commutative: true,
- asm: x86.AVPMULLW,
+ name: "VPCMPGTQ256",
+ argLen: 2,
+ asm: x86.AVPCMPGTQ,
reg: regInfo{
inputs: []inputInfo{
- {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
- {1, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
- {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
},
{
- name: "VPMULLWMasked512",
- argLen: 3,
- commutative: true,
- asm: x86.AVPMULLW,
+ name: "VPCMPGTQ512",
+ argLen: 2,
+ asm: x86.AVPCMPGTQ,
reg: regInfo{
inputs: []inputInfo{
- {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {0, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
},
},
},
{
- name: "VPMADDWD512",
+ name: "VPCMPGTW128",
argLen: 2,
- asm: x86.AVPMADDWD,
+ asm: x86.AVPCMPGTW,
reg: regInfo{
inputs: []inputInfo{
- {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
- {1, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
- {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
},
- {
- name: "VPMADDWDMasked512",
- argLen: 3,
- asm: x86.AVPMADDWD,
+ {
+ name: "VPCMPGTW256",
+ argLen: 2,
+ asm: x86.AVPCMPGTW,
reg: regInfo{
inputs: []inputInfo{
- {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
{
- name: "VPOPCNTW512",
- argLen: 1,
- asm: x86.AVPOPCNTW,
+ name: "VPCMPGTW512",
+ argLen: 2,
+ asm: x86.AVPCMPGTW,
reg: regInfo{
inputs: []inputInfo{
- {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
- {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ {0, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
},
},
},
{
- name: "VPOPCNTWMasked512",
+ name: "VPCOMPRESSBMasked128",
argLen: 2,
- asm: x86.AVPOPCNTW,
+ asm: x86.AVPCOMPRESSB,
reg: regInfo{
inputs: []inputInfo{
{1, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
},
},
{
- name: "VPADDSW512",
- argLen: 2,
- commutative: true,
- asm: x86.AVPADDSW,
+ name: "VPCOMPRESSBMasked256",
+ argLen: 2,
+ asm: x86.AVPCOMPRESSB,
reg: regInfo{
inputs: []inputInfo{
- {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
- {1, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ {1, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
- {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
},
{
- name: "VPADDSWMasked512",
- argLen: 3,
- commutative: true,
- asm: x86.AVPADDSW,
+ name: "VPCOMPRESSBMasked512",
+ argLen: 2,
+ asm: x86.AVPCOMPRESSB,
reg: regInfo{
inputs: []inputInfo{
- {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+ {1, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
{
- name: "VPSUBSW512",
+ name: "VPCOMPRESSDMasked128",
argLen: 2,
- asm: x86.AVPSUBSW,
+ asm: x86.AVPCOMPRESSD,
reg: regInfo{
inputs: []inputInfo{
- {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
- {1, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ {1, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
- {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
},
{
- name: "VPSUBSWMasked512",
- argLen: 3,
- asm: x86.AVPSUBSW,
+ name: "VPCOMPRESSDMasked256",
+ argLen: 2,
+ asm: x86.AVPCOMPRESSD,
reg: regInfo{
inputs: []inputInfo{
- {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+ {1, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
{
- name: "VPSLLW512",
+ name: "VPCOMPRESSDMasked512",
argLen: 2,
- asm: x86.AVPSLLW,
+ asm: x86.AVPCOMPRESSD,
reg: regInfo{
inputs: []inputInfo{
- {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ {1, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
- {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
},
{
- name: "VPSLLWMasked512",
- argLen: 3,
- asm: x86.AVPSLLW,
+ name: "VPCOMPRESSQMasked128",
+ argLen: 2,
+ asm: x86.AVPCOMPRESSQ,
reg: regInfo{
inputs: []inputInfo{
- {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
- {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ {1, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
- {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
},
{
- name: "VPSRAW512",
+ name: "VPCOMPRESSQMasked256",
argLen: 2,
- asm: x86.AVPSRAW,
+ asm: x86.AVPCOMPRESSQ,
reg: regInfo{
inputs: []inputInfo{
- {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ {1, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
- {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
},
{
- name: "VPSRAWMasked512",
- argLen: 3,
- asm: x86.AVPSRAW,
+ name: "VPCOMPRESSQMasked512",
+ argLen: 2,
+ asm: x86.AVPCOMPRESSQ,
reg: regInfo{
inputs: []inputInfo{
- {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
- {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ {1, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
- {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
},
{
- name: "VPSLLVW512",
+ name: "VPCOMPRESSWMasked128",
argLen: 2,
- asm: x86.AVPSLLVW,
+ asm: x86.AVPCOMPRESSW,
reg: regInfo{
inputs: []inputInfo{
- {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
- {1, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ {1, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
- {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
},
{
- name: "VPSHLDVW512",
- argLen: 3,
- resultInArg0: true,
- asm: x86.AVPSHLDVW,
+ name: "VPCOMPRESSWMasked256",
+ argLen: 2,
+ asm: x86.AVPCOMPRESSW,
reg: regInfo{
inputs: []inputInfo{
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {1, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
{
- name: "VPSHLDVWMasked512",
- argLen: 4,
- resultInArg0: true,
- asm: x86.AVPSHLDVW,
+ name: "VPCOMPRESSWMasked512",
+ argLen: 2,
+ asm: x86.AVPCOMPRESSW,
reg: regInfo{
inputs: []inputInfo{
- {3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+ {1, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
{
- name: "VPSLLVWMasked512",
- argLen: 3,
- asm: x86.AVPSLLVW,
+ name: "VPDPBUSD128",
+ argLen: 3,
+ resultInArg0: true,
+ asm: x86.AVPDPBUSD,
reg: regInfo{
inputs: []inputInfo{
- {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
{
- name: "VPSRAVW512",
- argLen: 2,
- asm: x86.AVPSRAVW,
+ name: "VPDPBUSD256",
+ argLen: 3,
+ resultInArg0: true,
+ asm: x86.AVPDPBUSD,
reg: regInfo{
inputs: []inputInfo{
- {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
- {1, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
- {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
},
{
- name: "VPSHRDVW512",
+ name: "VPDPBUSD512",
argLen: 3,
resultInArg0: true,
- asm: x86.AVPSHRDVW,
+ asm: x86.AVPDPBUSD,
reg: regInfo{
inputs: []inputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
{
- name: "VPSHRDVWMasked512",
+ name: "VPDPBUSDMasked128",
argLen: 4,
resultInArg0: true,
- asm: x86.AVPSHRDVW,
+ asm: x86.AVPDPBUSD,
reg: regInfo{
inputs: []inputInfo{
{3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
},
},
{
- name: "VPSRAVWMasked512",
- argLen: 3,
- asm: x86.AVPSRAVW,
+ name: "VPDPBUSDMasked256",
+ argLen: 4,
+ resultInArg0: true,
+ asm: x86.AVPDPBUSD,
reg: regInfo{
inputs: []inputInfo{
- {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+ {3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
{
- name: "VPSUBW512",
- argLen: 2,
- asm: x86.AVPSUBW,
+ name: "VPDPBUSDMasked512",
+ argLen: 4,
+ resultInArg0: true,
+ asm: x86.AVPDPBUSD,
reg: regInfo{
inputs: []inputInfo{
- {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
- {1, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ {3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
- {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
},
{
- name: "VPSUBWMasked512",
- argLen: 3,
- asm: x86.AVPSUBW,
+ name: "VPDPBUSDS128",
+ argLen: 3,
+ resultInArg0: true,
+ asm: x86.AVPDPBUSDS,
reg: regInfo{
inputs: []inputInfo{
- {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
{
- name: "VPABSW128",
- argLen: 1,
- asm: x86.AVPABSW,
+ name: "VPDPBUSDS256",
+ argLen: 3,
+ resultInArg0: true,
+ asm: x86.AVPDPBUSDS,
reg: regInfo{
inputs: []inputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
{
- name: "VPABSWMasked128",
- argLen: 2,
- asm: x86.AVPABSW,
+ name: "VPDPBUSDS512",
+ argLen: 3,
+ resultInArg0: true,
+ asm: x86.AVPDPBUSDS,
reg: regInfo{
inputs: []inputInfo{
- {1, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
{
- name: "VPADDW128",
- argLen: 2,
- commutative: true,
- asm: x86.AVPADDW,
+ name: "VPDPBUSDSMasked128",
+ argLen: 4,
+ resultInArg0: true,
+ asm: x86.AVPDPBUSDS,
reg: regInfo{
inputs: []inputInfo{
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
{
- name: "VPADDWMasked128",
- argLen: 3,
- commutative: true,
- asm: x86.AVPADDW,
+ name: "VPDPBUSDSMasked256",
+ argLen: 4,
+ resultInArg0: true,
+ asm: x86.AVPDPBUSDS,
reg: regInfo{
inputs: []inputInfo{
- {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+ {3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
{
- name: "VPCOMPRESSWMasked128",
- argLen: 2,
- asm: x86.AVPCOMPRESSW,
+ name: "VPDPBUSDSMasked512",
+ argLen: 4,
+ resultInArg0: true,
+ asm: x86.AVPDPBUSDS,
reg: regInfo{
inputs: []inputInfo{
- {1, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+ {3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
{
- name: "VPCMPEQW128",
- argLen: 2,
- commutative: true,
- asm: x86.AVPCMPEQW,
+ name: "VPDPWSSD128",
+ argLen: 3,
+ resultInArg0: true,
+ asm: x86.AVPDPWSSD,
reg: regInfo{
inputs: []inputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
{
- name: "VPCMPGTW128",
- argLen: 2,
- asm: x86.AVPCMPGTW,
+ name: "VPDPWSSD256",
+ argLen: 3,
+ resultInArg0: true,
+ asm: x86.AVPDPWSSD,
reg: regInfo{
inputs: []inputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
{
- name: "VPMAXSW128",
- argLen: 2,
- commutative: true,
- asm: x86.AVPMAXSW,
+ name: "VPDPWSSD512",
+ argLen: 3,
+ resultInArg0: true,
+ asm: x86.AVPDPWSSD,
reg: regInfo{
inputs: []inputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
{
- name: "VPMAXSWMasked128",
- argLen: 3,
- commutative: true,
- asm: x86.AVPMAXSW,
+ name: "VPDPWSSDMasked128",
+ argLen: 4,
+ resultInArg0: true,
+ asm: x86.AVPDPWSSD,
reg: regInfo{
inputs: []inputInfo{
- {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+ {3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
{
- name: "VPMINSW128",
- argLen: 2,
- commutative: true,
- asm: x86.AVPMINSW,
+ name: "VPDPWSSDMasked256",
+ argLen: 4,
+ resultInArg0: true,
+ asm: x86.AVPDPWSSD,
reg: regInfo{
inputs: []inputInfo{
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
{
- name: "VPMINSWMasked128",
- argLen: 3,
- commutative: true,
- asm: x86.AVPMINSW,
+ name: "VPDPWSSDMasked512",
+ argLen: 4,
+ resultInArg0: true,
+ asm: x86.AVPDPWSSD,
reg: regInfo{
inputs: []inputInfo{
- {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+ {3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
{
- name: "VPMULHW128",
- argLen: 2,
- commutative: true,
- asm: x86.AVPMULHW,
+ name: "VPDPWSSDS128",
+ argLen: 3,
+ resultInArg0: true,
+ asm: x86.AVPDPWSSDS,
reg: regInfo{
inputs: []inputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
{
- name: "VPMULHWMasked128",
- argLen: 3,
- commutative: true,
- asm: x86.AVPMULHW,
+ name: "VPDPWSSDS256",
+ argLen: 3,
+ resultInArg0: true,
+ asm: x86.AVPDPWSSDS,
reg: regInfo{
inputs: []inputInfo{
- {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
{
- name: "VPMULLW128",
- argLen: 2,
- commutative: true,
- asm: x86.AVPMULLW,
+ name: "VPDPWSSDS512",
+ argLen: 3,
+ resultInArg0: true,
+ asm: x86.AVPDPWSSDS,
reg: regInfo{
inputs: []inputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
{
- name: "VPMULLWMasked128",
- argLen: 3,
- commutative: true,
- asm: x86.AVPMULLW,
+ name: "VPDPWSSDSMasked128",
+ argLen: 4,
+ resultInArg0: true,
+ asm: x86.AVPDPWSSDS,
reg: regInfo{
inputs: []inputInfo{
- {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+ {3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
{
- name: "VPMADDWD128",
- argLen: 2,
- asm: x86.AVPMADDWD,
+ name: "VPDPWSSDSMasked256",
+ argLen: 4,
+ resultInArg0: true,
+ asm: x86.AVPDPWSSDS,
reg: regInfo{
inputs: []inputInfo{
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
{
- name: "VPMADDWDMasked128",
- argLen: 3,
- asm: x86.AVPMADDWD,
+ name: "VPDPWSSDSMasked512",
+ argLen: 4,
+ resultInArg0: true,
+ asm: x86.AVPDPWSSDS,
reg: regInfo{
inputs: []inputInfo{
- {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+ {3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
{
- name: "VPHADDW128",
+ name: "VPERMB128",
argLen: 2,
- asm: x86.AVPHADDW,
+ asm: x86.AVPERMB,
reg: regInfo{
inputs: []inputInfo{
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ {1, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
},
outputs: []outputInfo{
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
},
},
},
{
- name: "VPHSUBW128",
+ name: "VPERMB256",
argLen: 2,
- asm: x86.AVPHSUBW,
- reg: regInfo{
- inputs: []inputInfo{
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- },
- outputs: []outputInfo{
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- },
- },
- },
- {
- name: "VPOPCNTW128",
- argLen: 1,
- asm: x86.AVPOPCNTW,
+ asm: x86.AVPERMB,
reg: regInfo{
inputs: []inputInfo{
{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ {1, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
},
outputs: []outputInfo{
{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
},
},
{
- name: "VPOPCNTWMasked128",
+ name: "VPERMB512",
argLen: 2,
- asm: x86.AVPOPCNTW,
+ asm: x86.AVPERMB,
reg: regInfo{
inputs: []inputInfo{
- {1, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ {1, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
},
outputs: []outputInfo{
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
},
},
},
{
- name: "VPADDSW128",
- argLen: 2,
- commutative: true,
- asm: x86.AVPADDSW,
+ name: "VPERMBMasked128",
+ argLen: 3,
+ asm: x86.AVPERMB,
reg: regInfo{
inputs: []inputInfo{
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
{
- name: "VPADDSWMasked128",
- argLen: 3,
- commutative: true,
- asm: x86.AVPADDSW,
+ name: "VPERMBMasked256",
+ argLen: 3,
+ asm: x86.AVPERMB,
reg: regInfo{
inputs: []inputInfo{
{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
},
},
{
- name: "VPHADDSW128",
- argLen: 2,
- asm: x86.AVPHADDSW,
+ name: "VPERMBMasked512",
+ argLen: 3,
+ asm: x86.AVPERMB,
reg: regInfo{
inputs: []inputInfo{
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
{
- name: "VPHSUBSW128",
+ name: "VPERMD256",
argLen: 2,
- asm: x86.AVPHSUBSW,
+ asm: x86.AVPERMD,
reg: regInfo{
inputs: []inputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
{
- name: "VPSUBSW128",
+ name: "VPERMD512",
argLen: 2,
- asm: x86.AVPSUBSW,
+ asm: x86.AVPERMD,
reg: regInfo{
inputs: []inputInfo{
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ {1, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
},
outputs: []outputInfo{
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
},
},
},
{
- name: "VPSUBSWMasked128",
+ name: "VPERMDMasked256",
argLen: 3,
- asm: x86.AVPSUBSW,
+ asm: x86.AVPERMD,
reg: regInfo{
inputs: []inputInfo{
{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
},
},
{
- name: "VPSLLW128",
- argLen: 2,
- asm: x86.AVPSLLW,
+ name: "VPERMDMasked512",
+ argLen: 3,
+ asm: x86.AVPERMD,
reg: regInfo{
inputs: []inputInfo{
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
{
- name: "VPSLLWMasked128",
- argLen: 3,
- asm: x86.AVPSLLW,
+ name: "VPERMI2B128",
+ argLen: 3,
+ resultInArg0: true,
+ asm: x86.AVPERMI2B,
reg: regInfo{
- inputs: []inputInfo{
- {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
- {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ inputs: []inputInfo{
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
- {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
},
{
- name: "VPSRAW128",
- argLen: 2,
- asm: x86.AVPSRAW,
+ name: "VPERMI2B256",
+ argLen: 3,
+ resultInArg0: true,
+ asm: x86.AVPERMI2B,
reg: regInfo{
inputs: []inputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
{
- name: "VPSRAWMasked128",
- argLen: 3,
- asm: x86.AVPSRAW,
+ name: "VPERMI2B512",
+ argLen: 3,
+ resultInArg0: true,
+ asm: x86.AVPERMI2B,
reg: regInfo{
inputs: []inputInfo{
- {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
- {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
- {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
},
{
- name: "VPSLLVW128",
- argLen: 2,
- asm: x86.AVPSLLVW,
+ name: "VPERMI2BMasked128",
+ argLen: 4,
+ resultInArg0: true,
+ asm: x86.AVPERMI2B,
reg: regInfo{
inputs: []inputInfo{
- {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
- {1, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ {3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
- {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
},
{
- name: "VPSHLDVW128",
- argLen: 3,
+ name: "VPERMI2BMasked256",
+ argLen: 4,
resultInArg0: true,
- asm: x86.AVPSHLDVW,
+ asm: x86.AVPERMI2B,
reg: regInfo{
inputs: []inputInfo{
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
{
- name: "VPSHLDVWMasked128",
+ name: "VPERMI2BMasked512",
argLen: 4,
resultInArg0: true,
- asm: x86.AVPSHLDVW,
+ asm: x86.AVPERMI2B,
reg: regInfo{
inputs: []inputInfo{
{3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
},
},
{
- name: "VPSLLVWMasked128",
- argLen: 3,
- asm: x86.AVPSLLVW,
+ name: "VPERMI2D128",
+ argLen: 3,
+ resultInArg0: true,
+ asm: x86.AVPERMI2D,
reg: regInfo{
inputs: []inputInfo{
- {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
{
- name: "VPSRAVW128",
- argLen: 2,
- asm: x86.AVPSRAVW,
+ name: "VPERMI2D256",
+ argLen: 3,
+ resultInArg0: true,
+ asm: x86.AVPERMI2D,
reg: regInfo{
inputs: []inputInfo{
- {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
- {1, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
- {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
},
{
- name: "VPSHRDVW128",
+ name: "VPERMI2D512",
argLen: 3,
resultInArg0: true,
- asm: x86.AVPSHRDVW,
+ asm: x86.AVPERMI2D,
reg: regInfo{
inputs: []inputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
{
- name: "VPSHRDVWMasked128",
+ name: "VPERMI2DMasked128",
argLen: 4,
resultInArg0: true,
- asm: x86.AVPSHRDVW,
+ asm: x86.AVPERMI2D,
reg: regInfo{
inputs: []inputInfo{
{3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
},
},
{
- name: "VPSRAVWMasked128",
- argLen: 3,
- asm: x86.AVPSRAVW,
+ name: "VPERMI2DMasked256",
+ argLen: 4,
+ resultInArg0: true,
+ asm: x86.AVPERMI2D,
reg: regInfo{
inputs: []inputInfo{
- {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+ {3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
{
- name: "VPSIGNW128",
- argLen: 2,
- asm: x86.AVPSIGNW,
+ name: "VPERMI2DMasked512",
+ argLen: 4,
+ resultInArg0: true,
+ asm: x86.AVPERMI2D,
reg: regInfo{
inputs: []inputInfo{
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
{
- name: "VPSUBW128",
- argLen: 2,
- asm: x86.AVPSUBW,
+ name: "VPERMI2PD128",
+ argLen: 3,
+ resultInArg0: true,
+ asm: x86.AVPERMI2PD,
reg: regInfo{
inputs: []inputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
{
- name: "VPSUBWMasked128",
- argLen: 3,
- asm: x86.AVPSUBW,
+ name: "VPERMI2PD256",
+ argLen: 3,
+ resultInArg0: true,
+ asm: x86.AVPERMI2PD,
reg: regInfo{
inputs: []inputInfo{
- {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
{
- name: "VPABSD512",
- argLen: 1,
- asm: x86.AVPABSD,
+ name: "VPERMI2PD512",
+ argLen: 3,
+ resultInArg0: true,
+ asm: x86.AVPERMI2PD,
reg: regInfo{
inputs: []inputInfo{
- {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
- {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
},
{
- name: "VPABSDMasked512",
- argLen: 2,
- asm: x86.AVPABSD,
+ name: "VPERMI2PDMasked128",
+ argLen: 4,
+ resultInArg0: true,
+ asm: x86.AVPERMI2PD,
reg: regInfo{
inputs: []inputInfo{
- {1, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+ {3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
{
- name: "VPADDD512",
- argLen: 2,
- commutative: true,
- asm: x86.AVPADDD,
+ name: "VPERMI2PDMasked256",
+ argLen: 4,
+ resultInArg0: true,
+ asm: x86.AVPERMI2PD,
reg: regInfo{
inputs: []inputInfo{
- {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
- {1, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ {3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
- {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
},
{
- name: "VPADDDMasked512",
- argLen: 3,
- commutative: true,
- asm: x86.AVPADDD,
+ name: "VPERMI2PDMasked512",
+ argLen: 4,
+ resultInArg0: true,
+ asm: x86.AVPERMI2PD,
reg: regInfo{
inputs: []inputInfo{
- {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+ {3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
{
- name: "VPANDD512",
- argLen: 2,
- commutative: true,
- asm: x86.AVPANDD,
+ name: "VPERMI2PS128",
+ argLen: 3,
+ resultInArg0: true,
+ asm: x86.AVPERMI2PS,
reg: regInfo{
inputs: []inputInfo{
- {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
- {1, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
- {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
},
{
- name: "VPANDDMasked512",
- argLen: 3,
- commutative: true,
- asm: x86.AVPANDD,
+ name: "VPERMI2PS256",
+ argLen: 3,
+ resultInArg0: true,
+ asm: x86.AVPERMI2PS,
reg: regInfo{
inputs: []inputInfo{
- {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
{
- name: "VPANDND512",
- argLen: 2,
- asm: x86.AVPANDND,
+ name: "VPERMI2PS512",
+ argLen: 3,
+ resultInArg0: true,
+ asm: x86.AVPERMI2PS,
reg: regInfo{
inputs: []inputInfo{
- {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
- {1, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
- {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
},
{
- name: "VPANDNDMasked512",
- argLen: 3,
- asm: x86.AVPANDND,
+ name: "VPERMI2PSMasked128",
+ argLen: 4,
+ resultInArg0: true,
+ asm: x86.AVPERMI2PS,
reg: regInfo{
inputs: []inputInfo{
- {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+ {3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
{
- name: "VPCOMPRESSDMasked512",
- argLen: 2,
- asm: x86.AVPCOMPRESSD,
+ name: "VPERMI2PSMasked256",
+ argLen: 4,
+ resultInArg0: true,
+ asm: x86.AVPERMI2PS,
reg: regInfo{
inputs: []inputInfo{
- {1, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+ {3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
{
- name: "VPCMPEQD512",
- argLen: 2,
- commutative: true,
- asm: x86.AVPCMPEQD,
+ name: "VPERMI2PSMasked512",
+ argLen: 4,
+ resultInArg0: true,
+ asm: x86.AVPERMI2PS,
+ reg: regInfo{
+ inputs: []inputInfo{
+ {3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ },
+ outputs: []outputInfo{
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ },
+ },
+ },
+ {
+ name: "VPERMI2Q128",
+ argLen: 3,
+ resultInArg0: true,
+ asm: x86.AVPERMI2Q,
reg: regInfo{
inputs: []inputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
- {0, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
},
{
- name: "VPCMPGTD512",
- argLen: 2,
- asm: x86.AVPCMPGTD,
+ name: "VPERMI2Q256",
+ argLen: 3,
+ resultInArg0: true,
+ asm: x86.AVPERMI2Q,
reg: regInfo{
inputs: []inputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
- {0, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
},
{
- name: "VPMAXSD512",
- argLen: 2,
- commutative: true,
- asm: x86.AVPMAXSD,
+ name: "VPERMI2Q512",
+ argLen: 3,
+ resultInArg0: true,
+ asm: x86.AVPERMI2Q,
reg: regInfo{
inputs: []inputInfo{
- {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
- {1, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
- {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
},
{
- name: "VPMAXSDMasked512",
- argLen: 3,
- commutative: true,
- asm: x86.AVPMAXSD,
+ name: "VPERMI2QMasked128",
+ argLen: 4,
+ resultInArg0: true,
+ asm: x86.AVPERMI2Q,
reg: regInfo{
inputs: []inputInfo{
- {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+ {3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
{
- name: "VPMINSD512",
- argLen: 2,
- commutative: true,
- asm: x86.AVPMINSD,
+ name: "VPERMI2QMasked256",
+ argLen: 4,
+ resultInArg0: true,
+ asm: x86.AVPERMI2Q,
reg: regInfo{
inputs: []inputInfo{
- {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
- {1, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ {3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
- {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
},
{
- name: "VPMINSDMasked512",
- argLen: 3,
- commutative: true,
- asm: x86.AVPMINSD,
+ name: "VPERMI2QMasked512",
+ argLen: 4,
+ resultInArg0: true,
+ asm: x86.AVPERMI2Q,
reg: regInfo{
inputs: []inputInfo{
- {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+ {3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
{
- name: "VPMULLD512",
- argLen: 2,
- commutative: true,
- asm: x86.AVPMULLD,
+ name: "VPERMI2W128",
+ argLen: 3,
+ resultInArg0: true,
+ asm: x86.AVPERMI2W,
reg: regInfo{
inputs: []inputInfo{
- {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
- {1, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
- {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
},
{
- name: "VPMULLDMasked512",
- argLen: 3,
- commutative: true,
- asm: x86.AVPMULLD,
+ name: "VPERMI2W256",
+ argLen: 3,
+ resultInArg0: true,
+ asm: x86.AVPERMI2W,
reg: regInfo{
inputs: []inputInfo{
- {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
{
- name: "VPORD512",
- argLen: 2,
- commutative: true,
- asm: x86.AVPORD,
+ name: "VPERMI2W512",
+ argLen: 3,
+ resultInArg0: true,
+ asm: x86.AVPERMI2W,
reg: regInfo{
inputs: []inputInfo{
- {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
- {1, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
- {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
},
{
- name: "VPORDMasked512",
- argLen: 3,
- commutative: true,
- asm: x86.AVPORD,
+ name: "VPERMI2WMasked128",
+ argLen: 4,
+ resultInArg0: true,
+ asm: x86.AVPERMI2W,
reg: regInfo{
inputs: []inputInfo{
- {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+ {3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
{
- name: "VPDPWSSD512",
- argLen: 3,
+ name: "VPERMI2WMasked256",
+ argLen: 4,
resultInArg0: true,
- asm: x86.AVPDPWSSD,
+ asm: x86.AVPERMI2W,
reg: regInfo{
inputs: []inputInfo{
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
{
- name: "VPDPWSSDMasked512",
+ name: "VPERMI2WMasked512",
argLen: 4,
resultInArg0: true,
- asm: x86.AVPDPWSSD,
+ asm: x86.AVPERMI2W,
reg: regInfo{
inputs: []inputInfo{
{3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
},
},
{
- name: "VPOPCNTD512",
- argLen: 1,
- asm: x86.AVPOPCNTD,
+ name: "VPERMPD256",
+ argLen: 2,
+ asm: x86.AVPERMPD,
reg: regInfo{
inputs: []inputInfo{
{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ {1, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
},
outputs: []outputInfo{
{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
},
},
{
- name: "VPOPCNTDMasked512",
+ name: "VPERMPD512",
argLen: 2,
- asm: x86.AVPOPCNTD,
+ asm: x86.AVPERMPD,
reg: regInfo{
inputs: []inputInfo{
- {1, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ {1, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
},
outputs: []outputInfo{
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
},
},
},
{
- name: "VPROLVD512",
- argLen: 2,
- asm: x86.AVPROLVD,
+ name: "VPERMPDMasked256",
+ argLen: 3,
+ asm: x86.AVPERMPD,
reg: regInfo{
inputs: []inputInfo{
- {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
- {1, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
- {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
},
{
- name: "VPROLVDMasked512",
+ name: "VPERMPDMasked512",
argLen: 3,
- asm: x86.AVPROLVD,
+ asm: x86.AVPERMPD,
reg: regInfo{
inputs: []inputInfo{
{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
},
},
{
- name: "VPRORVD512",
+ name: "VPERMPS256",
argLen: 2,
- asm: x86.AVPRORVD,
+ asm: x86.AVPERMPS,
reg: regInfo{
inputs: []inputInfo{
- {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
- {1, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
- {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
},
{
- name: "VPRORVDMasked512",
- argLen: 3,
- asm: x86.AVPRORVD,
+ name: "VPERMPS512",
+ argLen: 2,
+ asm: x86.AVPERMPS,
reg: regInfo{
inputs: []inputInfo{
- {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ {1, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
},
outputs: []outputInfo{
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
},
},
},
{
- name: "VPDPWSSDS512",
- argLen: 3,
- resultInArg0: true,
- asm: x86.AVPDPWSSDS,
+ name: "VPERMPSMasked256",
+ argLen: 3,
+ asm: x86.AVPERMPS,
reg: regInfo{
inputs: []inputInfo{
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
{
- name: "VPDPWSSDSMasked512",
- argLen: 4,
- resultInArg0: true,
- asm: x86.AVPDPWSSDS,
+ name: "VPERMPSMasked512",
+ argLen: 3,
+ asm: x86.AVPERMPS,
reg: regInfo{
inputs: []inputInfo{
- {3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+ {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
{
- name: "VPDPBUSDS512",
- argLen: 3,
- resultInArg0: true,
- asm: x86.AVPDPBUSDS,
+ name: "VPERMQ256",
+ argLen: 2,
+ asm: x86.AVPERMQ,
reg: regInfo{
inputs: []inputInfo{
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ {1, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
},
outputs: []outputInfo{
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
},
},
},
{
- name: "VPDPBUSDSMasked512",
- argLen: 4,
- resultInArg0: true,
- asm: x86.AVPDPBUSDS,
+ name: "VPERMQ512",
+ argLen: 2,
+ asm: x86.AVPERMQ,
reg: regInfo{
inputs: []inputInfo{
- {3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ {1, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
},
outputs: []outputInfo{
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
},
},
},
{
- name: "VPSLLD512",
- argLen: 2,
- asm: x86.AVPSLLD,
+ name: "VPERMQMasked256",
+ argLen: 3,
+ asm: x86.AVPERMQ,
reg: regInfo{
inputs: []inputInfo{
- {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
- {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
},
{
- name: "VPSLLDMasked512",
+ name: "VPERMQMasked512",
argLen: 3,
- asm: x86.AVPSLLD,
+ asm: x86.AVPERMQ,
reg: regInfo{
inputs: []inputInfo{
{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
},
outputs: []outputInfo{
- {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
},
{
- name: "VPSRAD512",
+ name: "VPERMW128",
argLen: 2,
- asm: x86.AVPSRAD,
+ asm: x86.AVPERMW,
reg: regInfo{
inputs: []inputInfo{
- {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ {1, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
},
outputs: []outputInfo{
{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
},
},
{
- name: "VPSRADMasked512",
- argLen: 3,
- asm: x86.AVPSRAD,
+ name: "VPERMW256",
+ argLen: 2,
+ asm: x86.AVPERMW,
reg: regInfo{
inputs: []inputInfo{
- {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
- {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ {1, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
},
outputs: []outputInfo{
{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
},
},
{
- name: "VPSLLVD512",
+ name: "VPERMW512",
argLen: 2,
- asm: x86.AVPSLLVD,
+ asm: x86.AVPERMW,
reg: regInfo{
inputs: []inputInfo{
{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
},
},
{
- name: "VPSHLDVD512",
- argLen: 3,
- resultInArg0: true,
- asm: x86.AVPSHLDVD,
+ name: "VPERMWMasked128",
+ argLen: 3,
+ asm: x86.AVPERMW,
reg: regInfo{
inputs: []inputInfo{
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
{
- name: "VPSHLDVDMasked512",
- argLen: 4,
- resultInArg0: true,
- asm: x86.AVPSHLDVD,
+ name: "VPERMWMasked256",
+ argLen: 3,
+ asm: x86.AVPERMW,
reg: regInfo{
inputs: []inputInfo{
- {3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+ {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
{
- name: "VPSLLVDMasked512",
+ name: "VPERMWMasked512",
argLen: 3,
- asm: x86.AVPSLLVD,
+ asm: x86.AVPERMW,
reg: regInfo{
inputs: []inputInfo{
{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
},
},
{
- name: "VPSRAVD512",
+ name: "VPHADDD128",
argLen: 2,
- asm: x86.AVPSRAVD,
+ asm: x86.AVPHADDD,
reg: regInfo{
inputs: []inputInfo{
- {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
- {1, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
- {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
},
{
- name: "VPSHRDVD512",
- argLen: 3,
- resultInArg0: true,
- asm: x86.AVPSHRDVD,
+ name: "VPHADDD256",
+ argLen: 2,
+ asm: x86.AVPHADDD,
reg: regInfo{
inputs: []inputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
{
- name: "VPSHRDVDMasked512",
- argLen: 4,
- resultInArg0: true,
- asm: x86.AVPSHRDVD,
+ name: "VPHADDSW128",
+ argLen: 2,
+ asm: x86.AVPHADDSW,
reg: regInfo{
inputs: []inputInfo{
- {3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
{
- name: "VPSRAVDMasked512",
- argLen: 3,
- asm: x86.AVPSRAVD,
+ name: "VPHADDSW256",
+ argLen: 2,
+ asm: x86.AVPHADDSW,
reg: regInfo{
inputs: []inputInfo{
- {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
{
- name: "VPSUBD512",
+ name: "VPHADDW128",
argLen: 2,
- asm: x86.AVPSUBD,
+ asm: x86.AVPHADDW,
reg: regInfo{
inputs: []inputInfo{
- {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
- {1, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
- {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
},
{
- name: "VPSUBDMasked512",
- argLen: 3,
- asm: x86.AVPSUBD,
+ name: "VPHADDW256",
+ argLen: 2,
+ asm: x86.AVPHADDW,
reg: regInfo{
inputs: []inputInfo{
- {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
{
- name: "VPDPBUSD512",
- argLen: 3,
- resultInArg0: true,
- asm: x86.AVPDPBUSD,
+ name: "VPHSUBD128",
+ argLen: 2,
+ asm: x86.AVPHSUBD,
reg: regInfo{
inputs: []inputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
{
- name: "VPDPBUSDMasked512",
- argLen: 4,
- resultInArg0: true,
- asm: x86.AVPDPBUSD,
+ name: "VPHSUBD256",
+ argLen: 2,
+ asm: x86.AVPHSUBD,
reg: regInfo{
inputs: []inputInfo{
- {3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
{
- name: "VPXORD512",
- argLen: 2,
- commutative: true,
- asm: x86.AVPXORD,
+ name: "VPHSUBSW128",
+ argLen: 2,
+ asm: x86.AVPHSUBSW,
reg: regInfo{
inputs: []inputInfo{
- {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
- {1, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
- {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
},
{
- name: "VPXORDMasked512",
- argLen: 3,
- commutative: true,
- asm: x86.AVPXORD,
+ name: "VPHSUBSW256",
+ argLen: 2,
+ asm: x86.AVPHSUBSW,
reg: regInfo{
inputs: []inputInfo{
- {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
{
- name: "VPABSD128",
- argLen: 1,
- asm: x86.AVPABSD,
+ name: "VPHSUBW128",
+ argLen: 2,
+ asm: x86.AVPHSUBW,
reg: regInfo{
inputs: []inputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
{
- name: "VPABSDMasked128",
+ name: "VPHSUBW256",
argLen: 2,
- asm: x86.AVPABSD,
+ asm: x86.AVPHSUBW,
reg: regInfo{
inputs: []inputInfo{
- {1, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
{
- name: "VPADDD128",
- argLen: 2,
- commutative: true,
- asm: x86.AVPADDD,
+ name: "VPMADDUBSW128",
+ argLen: 2,
+ asm: x86.AVPMADDUBSW,
reg: regInfo{
inputs: []inputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
{
- name: "VPADDDMasked128",
- argLen: 3,
- commutative: true,
- asm: x86.AVPADDD,
+ name: "VPMADDUBSW256",
+ argLen: 2,
+ asm: x86.AVPMADDUBSW,
reg: regInfo{
inputs: []inputInfo{
- {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
{
- name: "VPANDDMasked128",
- argLen: 3,
- commutative: true,
- asm: x86.AVPANDD,
+ name: "VPMADDUBSW512",
+ argLen: 2,
+ asm: x86.AVPMADDUBSW,
+ reg: regInfo{
+ inputs: []inputInfo{
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ {1, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ },
+ outputs: []outputInfo{
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ },
+ },
+ },
+ {
+ name: "VPMADDUBSWMasked128",
+ argLen: 3,
+ asm: x86.AVPMADDUBSW,
reg: regInfo{
inputs: []inputInfo{
{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
},
},
{
- name: "VPANDNDMasked128",
+ name: "VPMADDUBSWMasked256",
argLen: 3,
- asm: x86.AVPANDND,
+ asm: x86.AVPMADDUBSW,
reg: regInfo{
inputs: []inputInfo{
{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
},
},
{
- name: "VPCOMPRESSDMasked128",
- argLen: 2,
- asm: x86.AVPCOMPRESSD,
+ name: "VPMADDUBSWMasked512",
+ argLen: 3,
+ asm: x86.AVPMADDUBSW,
reg: regInfo{
inputs: []inputInfo{
- {1, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+ {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
{
- name: "VPCMPEQD128",
- argLen: 2,
- commutative: true,
- asm: x86.AVPCMPEQD,
+ name: "VPMADDWD128",
+ argLen: 2,
+ asm: x86.AVPMADDWD,
reg: regInfo{
inputs: []inputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
{
- name: "VPCMPGTD128",
+ name: "VPMADDWD256",
argLen: 2,
- asm: x86.AVPCMPGTD,
+ asm: x86.AVPMADDWD,
reg: regInfo{
inputs: []inputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
{
- name: "VPMAXSD128",
- argLen: 2,
- commutative: true,
- asm: x86.AVPMAXSD,
+ name: "VPMADDWD512",
+ argLen: 2,
+ asm: x86.AVPMADDWD,
reg: regInfo{
inputs: []inputInfo{
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ {1, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
},
outputs: []outputInfo{
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
},
},
},
{
- name: "VPMAXSDMasked128",
- argLen: 3,
- commutative: true,
- asm: x86.AVPMAXSD,
+ name: "VPMADDWDMasked128",
+ argLen: 3,
+ asm: x86.AVPMADDWD,
reg: regInfo{
inputs: []inputInfo{
{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
},
},
{
- name: "VPMINSD128",
- argLen: 2,
- commutative: true,
- asm: x86.AVPMINSD,
+ name: "VPMADDWDMasked256",
+ argLen: 3,
+ asm: x86.AVPMADDWD,
reg: regInfo{
inputs: []inputInfo{
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
{
- name: "VPMINSDMasked128",
- argLen: 3,
- commutative: true,
- asm: x86.AVPMINSD,
+ name: "VPMADDWDMasked512",
+ argLen: 3,
+ asm: x86.AVPMADDWD,
reg: regInfo{
inputs: []inputInfo{
{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
},
},
{
- name: "VPMULDQ128",
+ name: "VPMAXSB128",
argLen: 2,
commutative: true,
- asm: x86.AVPMULDQ,
+ asm: x86.AVPMAXSB,
reg: regInfo{
inputs: []inputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
{
- name: "VPMULLD128",
+ name: "VPMAXSB256",
argLen: 2,
commutative: true,
- asm: x86.AVPMULLD,
+ asm: x86.AVPMAXSB,
reg: regInfo{
inputs: []inputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
{
- name: "VPMULLDMasked128",
- argLen: 3,
+ name: "VPMAXSB512",
+ argLen: 2,
commutative: true,
- asm: x86.AVPMULLD,
+ asm: x86.AVPMAXSB,
reg: regInfo{
inputs: []inputInfo{
- {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ {1, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
},
outputs: []outputInfo{
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
},
},
},
{
- name: "VPORDMasked128",
+ name: "VPMAXSBMasked128",
argLen: 3,
commutative: true,
- asm: x86.AVPORD,
+ asm: x86.AVPMAXSB,
reg: regInfo{
inputs: []inputInfo{
{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
},
},
{
- name: "VPDPWSSD128",
- argLen: 3,
- resultInArg0: true,
- asm: x86.AVPDPWSSD,
+ name: "VPMAXSBMasked256",
+ argLen: 3,
+ commutative: true,
+ asm: x86.AVPMAXSB,
reg: regInfo{
inputs: []inputInfo{
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
{
- name: "VPDPWSSDMasked128",
- argLen: 4,
- resultInArg0: true,
- asm: x86.AVPDPWSSD,
+ name: "VPMAXSBMasked512",
+ argLen: 3,
+ commutative: true,
+ asm: x86.AVPMAXSB,
reg: regInfo{
inputs: []inputInfo{
- {3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+ {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
{
- name: "VPHADDD128",
- argLen: 2,
- asm: x86.AVPHADDD,
+ name: "VPMAXSD128",
+ argLen: 2,
+ commutative: true,
+ asm: x86.AVPMAXSD,
reg: regInfo{
inputs: []inputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
{
- name: "VPHSUBD128",
- argLen: 2,
- asm: x86.AVPHSUBD,
+ name: "VPMAXSD256",
+ argLen: 2,
+ commutative: true,
+ asm: x86.AVPMAXSD,
reg: regInfo{
inputs: []inputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
{
- name: "VPOPCNTD128",
- argLen: 1,
- asm: x86.AVPOPCNTD,
+ name: "VPMAXSD512",
+ argLen: 2,
+ commutative: true,
+ asm: x86.AVPMAXSD,
reg: regInfo{
inputs: []inputInfo{
{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ {1, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
},
outputs: []outputInfo{
{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
},
},
{
- name: "VPOPCNTDMasked128",
- argLen: 2,
- asm: x86.AVPOPCNTD,
+ name: "VPMAXSDMasked128",
+ argLen: 3,
+ commutative: true,
+ asm: x86.AVPMAXSD,
reg: regInfo{
inputs: []inputInfo{
- {1, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+ {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
{
- name: "VPROLVD128",
- argLen: 2,
- asm: x86.AVPROLVD,
+ name: "VPMAXSDMasked256",
+ argLen: 3,
+ commutative: true,
+ asm: x86.AVPMAXSD,
reg: regInfo{
inputs: []inputInfo{
- {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
- {1, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
- {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
},
{
- name: "VPROLVDMasked128",
- argLen: 3,
- asm: x86.AVPROLVD,
+ name: "VPMAXSDMasked512",
+ argLen: 3,
+ commutative: true,
+ asm: x86.AVPMAXSD,
reg: regInfo{
inputs: []inputInfo{
{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
},
},
{
- name: "VPRORVD128",
- argLen: 2,
- asm: x86.AVPRORVD,
+ name: "VPMAXSQ128",
+ argLen: 2,
+ commutative: true,
+ asm: x86.AVPMAXSQ,
reg: regInfo{
inputs: []inputInfo{
{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
},
},
{
- name: "VPRORVDMasked128",
- argLen: 3,
- asm: x86.AVPRORVD,
+ name: "VPMAXSQ256",
+ argLen: 2,
+ commutative: true,
+ asm: x86.AVPMAXSQ,
reg: regInfo{
inputs: []inputInfo{
- {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ {1, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
},
outputs: []outputInfo{
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
},
},
},
{
- name: "VPDPWSSDS128",
- argLen: 3,
- resultInArg0: true,
- asm: x86.AVPDPWSSDS,
+ name: "VPMAXSQ512",
+ argLen: 2,
+ commutative: true,
+ asm: x86.AVPMAXSQ,
reg: regInfo{
inputs: []inputInfo{
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ {1, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
},
outputs: []outputInfo{
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
},
},
},
{
- name: "VPDPWSSDSMasked128",
- argLen: 4,
- resultInArg0: true,
- asm: x86.AVPDPWSSDS,
+ name: "VPMAXSQMasked128",
+ argLen: 3,
+ commutative: true,
+ asm: x86.AVPMAXSQ,
reg: regInfo{
inputs: []inputInfo{
- {3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+ {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- },
- outputs: []outputInfo{
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- },
- },
- },
- {
- name: "VPDPBUSDS128",
- argLen: 3,
- resultInArg0: true,
- asm: x86.AVPDPBUSDS,
- reg: regInfo{
- inputs: []inputInfo{
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
{
- name: "VPDPBUSDSMasked128",
- argLen: 4,
- resultInArg0: true,
- asm: x86.AVPDPBUSDS,
+ name: "VPMAXSQMasked256",
+ argLen: 3,
+ commutative: true,
+ asm: x86.AVPMAXSQ,
reg: regInfo{
inputs: []inputInfo{
- {3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+ {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
{
- name: "VPSLLD128",
- argLen: 2,
- asm: x86.AVPSLLD,
+ name: "VPMAXSQMasked512",
+ argLen: 3,
+ commutative: true,
+ asm: x86.AVPMAXSQ,
reg: regInfo{
inputs: []inputInfo{
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
{
- name: "VPSLLDMasked128",
- argLen: 3,
- asm: x86.AVPSLLD,
- reg: regInfo{
- inputs: []inputInfo{
- {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
- {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ name: "VPMAXSW128",
+ argLen: 2,
+ commutative: true,
+ asm: x86.AVPMAXSW,
+ reg: regInfo{
+ inputs: []inputInfo{
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
- {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
},
{
- name: "VPSRAD128",
- argLen: 2,
- asm: x86.AVPSRAD,
+ name: "VPMAXSW256",
+ argLen: 2,
+ commutative: true,
+ asm: x86.AVPMAXSW,
reg: regInfo{
inputs: []inputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
{
- name: "VPSRADMasked128",
- argLen: 3,
- asm: x86.AVPSRAD,
+ name: "VPMAXSW512",
+ argLen: 2,
+ commutative: true,
+ asm: x86.AVPMAXSW,
reg: regInfo{
inputs: []inputInfo{
- {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
- {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ {1, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
},
outputs: []outputInfo{
{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
},
},
{
- name: "VPSLLVD128",
- argLen: 2,
- asm: x86.AVPSLLVD,
+ name: "VPMAXSWMasked128",
+ argLen: 3,
+ commutative: true,
+ asm: x86.AVPMAXSW,
reg: regInfo{
inputs: []inputInfo{
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
{
- name: "VPSHLDVD128",
- argLen: 3,
- resultInArg0: true,
- asm: x86.AVPSHLDVD,
+ name: "VPMAXSWMasked256",
+ argLen: 3,
+ commutative: true,
+ asm: x86.AVPMAXSW,
reg: regInfo{
inputs: []inputInfo{
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
{
- name: "VPSHLDVDMasked128",
- argLen: 4,
- resultInArg0: true,
- asm: x86.AVPSHLDVD,
+ name: "VPMAXSWMasked512",
+ argLen: 3,
+ commutative: true,
+ asm: x86.AVPMAXSW,
reg: regInfo{
inputs: []inputInfo{
- {3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+ {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
{
- name: "VPSLLVDMasked128",
- argLen: 3,
- asm: x86.AVPSLLVD,
+ name: "VPMAXUB128",
+ argLen: 2,
+ commutative: true,
+ asm: x86.AVPMAXUB,
reg: regInfo{
inputs: []inputInfo{
- {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
{
- name: "VPSRAVD128",
- argLen: 2,
- asm: x86.AVPSRAVD,
+ name: "VPMAXUB256",
+ argLen: 2,
+ commutative: true,
+ asm: x86.AVPMAXUB,
reg: regInfo{
inputs: []inputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
{
- name: "VPSHRDVD128",
- argLen: 3,
- resultInArg0: true,
- asm: x86.AVPSHRDVD,
+ name: "VPMAXUB512",
+ argLen: 2,
+ commutative: true,
+ asm: x86.AVPMAXUB,
reg: regInfo{
inputs: []inputInfo{
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ {1, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
},
outputs: []outputInfo{
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
},
},
},
{
- name: "VPSHRDVDMasked128",
- argLen: 4,
- resultInArg0: true,
- asm: x86.AVPSHRDVD,
+ name: "VPMAXUBMasked128",
+ argLen: 3,
+ commutative: true,
+ asm: x86.AVPMAXUB,
reg: regInfo{
inputs: []inputInfo{
- {3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+ {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
{
- name: "VPSRAVDMasked128",
- argLen: 3,
- asm: x86.AVPSRAVD,
+ name: "VPMAXUBMasked256",
+ argLen: 3,
+ commutative: true,
+ asm: x86.AVPMAXUB,
reg: regInfo{
inputs: []inputInfo{
{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
},
},
{
- name: "VPSIGND128",
- argLen: 2,
- asm: x86.AVPSIGND,
+ name: "VPMAXUBMasked512",
+ argLen: 3,
+ commutative: true,
+ asm: x86.AVPMAXUB,
reg: regInfo{
inputs: []inputInfo{
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
{
- name: "VPSUBD128",
- argLen: 2,
- asm: x86.AVPSUBD,
+ name: "VPMAXUD128",
+ argLen: 2,
+ commutative: true,
+ asm: x86.AVPMAXUD,
reg: regInfo{
inputs: []inputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
{
- name: "VPSUBDMasked128",
- argLen: 3,
- asm: x86.AVPSUBD,
+ name: "VPMAXUD256",
+ argLen: 2,
+ commutative: true,
+ asm: x86.AVPMAXUD,
reg: regInfo{
inputs: []inputInfo{
- {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
{
- name: "VPDPBUSD128",
- argLen: 3,
- resultInArg0: true,
- asm: x86.AVPDPBUSD,
+ name: "VPMAXUD512",
+ argLen: 2,
+ commutative: true,
+ asm: x86.AVPMAXUD,
reg: regInfo{
inputs: []inputInfo{
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ {1, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
},
outputs: []outputInfo{
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
},
},
},
{
- name: "VPDPBUSDMasked128",
- argLen: 4,
- resultInArg0: true,
- asm: x86.AVPDPBUSD,
+ name: "VPMAXUDMasked128",
+ argLen: 3,
+ commutative: true,
+ asm: x86.AVPMAXUD,
reg: regInfo{
inputs: []inputInfo{
- {3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+ {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
{
- name: "VPXORDMasked128",
+ name: "VPMAXUDMasked256",
argLen: 3,
commutative: true,
- asm: x86.AVPXORD,
+ asm: x86.AVPMAXUD,
reg: regInfo{
inputs: []inputInfo{
{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
},
},
{
- name: "VPABSD256",
- argLen: 1,
- asm: x86.AVPABSD,
+ name: "VPMAXUDMasked512",
+ argLen: 3,
+ commutative: true,
+ asm: x86.AVPMAXUD,
reg: regInfo{
inputs: []inputInfo{
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
{
- name: "VPABSDMasked256",
- argLen: 2,
- asm: x86.AVPABSD,
+ name: "VPMAXUQ128",
+ argLen: 2,
+ commutative: true,
+ asm: x86.AVPMAXUQ,
reg: regInfo{
inputs: []inputInfo{
- {1, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ {1, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
},
outputs: []outputInfo{
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
},
},
},
{
- name: "VPADDD256",
+ name: "VPMAXUQ256",
argLen: 2,
commutative: true,
- asm: x86.AVPADDD,
+ asm: x86.AVPMAXUQ,
reg: regInfo{
inputs: []inputInfo{
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ {1, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
},
outputs: []outputInfo{
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
},
},
},
{
- name: "VPADDDMasked256",
- argLen: 3,
+ name: "VPMAXUQ512",
+ argLen: 2,
commutative: true,
- asm: x86.AVPADDD,
+ asm: x86.AVPMAXUQ,
reg: regInfo{
inputs: []inputInfo{
- {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ {1, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
},
outputs: []outputInfo{
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
},
},
},
{
- name: "VPANDDMasked256",
+ name: "VPMAXUQMasked128",
argLen: 3,
commutative: true,
- asm: x86.AVPANDD,
+ asm: x86.AVPMAXUQ,
reg: regInfo{
inputs: []inputInfo{
{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
},
},
{
- name: "VPANDNDMasked256",
- argLen: 3,
- asm: x86.AVPANDND,
+ name: "VPMAXUQMasked256",
+ argLen: 3,
+ commutative: true,
+ asm: x86.AVPMAXUQ,
reg: regInfo{
inputs: []inputInfo{
{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
},
},
{
- name: "VPCOMPRESSDMasked256",
- argLen: 2,
- asm: x86.AVPCOMPRESSD,
+ name: "VPMAXUQMasked512",
+ argLen: 3,
+ commutative: true,
+ asm: x86.AVPMAXUQ,
reg: regInfo{
inputs: []inputInfo{
- {1, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+ {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
{
- name: "VPCMPEQD256",
+ name: "VPMAXUW128",
argLen: 2,
commutative: true,
- asm: x86.AVPCMPEQD,
+ asm: x86.AVPMAXUW,
reg: regInfo{
inputs: []inputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
{
- name: "VPCMPGTD256",
- argLen: 2,
- asm: x86.AVPCMPGTD,
+ name: "VPMAXUW256",
+ argLen: 2,
+ commutative: true,
+ asm: x86.AVPMAXUW,
reg: regInfo{
inputs: []inputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
{
- name: "VPMAXSD256",
+ name: "VPMAXUW512",
argLen: 2,
commutative: true,
- asm: x86.AVPMAXSD,
+ asm: x86.AVPMAXUW,
reg: regInfo{
inputs: []inputInfo{
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ {1, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
},
outputs: []outputInfo{
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
},
},
},
{
- name: "VPMAXSDMasked256",
+ name: "VPMAXUWMasked128",
argLen: 3,
commutative: true,
- asm: x86.AVPMAXSD,
+ asm: x86.AVPMAXUW,
reg: regInfo{
inputs: []inputInfo{
{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
},
},
{
- name: "VPMINSD256",
- argLen: 2,
+ name: "VPMAXUWMasked256",
+ argLen: 3,
commutative: true,
- asm: x86.AVPMINSD,
+ asm: x86.AVPMAXUW,
reg: regInfo{
inputs: []inputInfo{
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
{
- name: "VPMINSDMasked256",
+ name: "VPMAXUWMasked512",
argLen: 3,
commutative: true,
- asm: x86.AVPMINSD,
+ asm: x86.AVPMAXUW,
reg: regInfo{
inputs: []inputInfo{
{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
},
},
{
- name: "VPMULDQ256",
+ name: "VPMINSB128",
argLen: 2,
commutative: true,
- asm: x86.AVPMULDQ,
+ asm: x86.AVPMINSB,
reg: regInfo{
inputs: []inputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
{
- name: "VPMULLD256",
+ name: "VPMINSB256",
argLen: 2,
commutative: true,
- asm: x86.AVPMULLD,
+ asm: x86.AVPMINSB,
reg: regInfo{
inputs: []inputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
{
- name: "VPMULLDMasked256",
- argLen: 3,
+ name: "VPMINSB512",
+ argLen: 2,
commutative: true,
- asm: x86.AVPMULLD,
+ asm: x86.AVPMINSB,
reg: regInfo{
inputs: []inputInfo{
- {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ {1, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
},
outputs: []outputInfo{
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
},
},
},
{
- name: "VPORDMasked256",
+ name: "VPMINSBMasked128",
argLen: 3,
commutative: true,
- asm: x86.AVPORD,
+ asm: x86.AVPMINSB,
reg: regInfo{
inputs: []inputInfo{
{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
},
},
{
- name: "VPDPWSSD256",
- argLen: 3,
- resultInArg0: true,
- asm: x86.AVPDPWSSD,
+ name: "VPMINSBMasked256",
+ argLen: 3,
+ commutative: true,
+ asm: x86.AVPMINSB,
reg: regInfo{
inputs: []inputInfo{
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
{
- name: "VPDPWSSDMasked256",
- argLen: 4,
- resultInArg0: true,
- asm: x86.AVPDPWSSD,
+ name: "VPMINSBMasked512",
+ argLen: 3,
+ commutative: true,
+ asm: x86.AVPMINSB,
reg: regInfo{
inputs: []inputInfo{
- {3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+ {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
{
- name: "VPHADDD256",
- argLen: 2,
- asm: x86.AVPHADDD,
+ name: "VPMINSD128",
+ argLen: 2,
+ commutative: true,
+ asm: x86.AVPMINSD,
reg: regInfo{
inputs: []inputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
{
- name: "VPHSUBD256",
- argLen: 2,
- asm: x86.AVPHSUBD,
+ name: "VPMINSD256",
+ argLen: 2,
+ commutative: true,
+ asm: x86.AVPMINSD,
reg: regInfo{
inputs: []inputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
{
- name: "VPOPCNTD256",
- argLen: 1,
- asm: x86.AVPOPCNTD,
+ name: "VPMINSD512",
+ argLen: 2,
+ commutative: true,
+ asm: x86.AVPMINSD,
reg: regInfo{
inputs: []inputInfo{
{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ {1, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
},
outputs: []outputInfo{
{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
},
},
{
- name: "VPOPCNTDMasked256",
- argLen: 2,
- asm: x86.AVPOPCNTD,
+ name: "VPMINSDMasked128",
+ argLen: 3,
+ commutative: true,
+ asm: x86.AVPMINSD,
reg: regInfo{
inputs: []inputInfo{
- {1, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+ {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
{
- name: "VPROLVD256",
- argLen: 2,
- asm: x86.AVPROLVD,
+ name: "VPMINSDMasked256",
+ argLen: 3,
+ commutative: true,
+ asm: x86.AVPMINSD,
reg: regInfo{
inputs: []inputInfo{
- {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
- {1, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
- {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
},
{
- name: "VPROLVDMasked256",
- argLen: 3,
- asm: x86.AVPROLVD,
+ name: "VPMINSDMasked512",
+ argLen: 3,
+ commutative: true,
+ asm: x86.AVPMINSD,
reg: regInfo{
inputs: []inputInfo{
{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
},
},
{
- name: "VPRORVD256",
- argLen: 2,
- asm: x86.AVPRORVD,
+ name: "VPMINSQ128",
+ argLen: 2,
+ commutative: true,
+ asm: x86.AVPMINSQ,
reg: regInfo{
inputs: []inputInfo{
{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
},
},
{
- name: "VPRORVDMasked256",
- argLen: 3,
- asm: x86.AVPRORVD,
+ name: "VPMINSQ256",
+ argLen: 2,
+ commutative: true,
+ asm: x86.AVPMINSQ,
reg: regInfo{
inputs: []inputInfo{
- {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ {1, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
},
outputs: []outputInfo{
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
},
},
},
{
- name: "VPDPWSSDS256",
- argLen: 3,
- resultInArg0: true,
- asm: x86.AVPDPWSSDS,
+ name: "VPMINSQ512",
+ argLen: 2,
+ commutative: true,
+ asm: x86.AVPMINSQ,
reg: regInfo{
inputs: []inputInfo{
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ {1, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
},
outputs: []outputInfo{
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
},
},
},
{
- name: "VPDPWSSDSMasked256",
- argLen: 4,
- resultInArg0: true,
- asm: x86.AVPDPWSSDS,
+ name: "VPMINSQMasked128",
+ argLen: 3,
+ commutative: true,
+ asm: x86.AVPMINSQ,
reg: regInfo{
inputs: []inputInfo{
- {3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+ {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
{
- name: "VPDPBUSDS256",
- argLen: 3,
- resultInArg0: true,
- asm: x86.AVPDPBUSDS,
+ name: "VPMINSQMasked256",
+ argLen: 3,
+ commutative: true,
+ asm: x86.AVPMINSQ,
reg: regInfo{
inputs: []inputInfo{
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
{
- name: "VPDPBUSDSMasked256",
- argLen: 4,
- resultInArg0: true,
- asm: x86.AVPDPBUSDS,
+ name: "VPMINSQMasked512",
+ argLen: 3,
+ commutative: true,
+ asm: x86.AVPMINSQ,
reg: regInfo{
inputs: []inputInfo{
- {3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+ {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
{
- name: "VPSLLD256",
- argLen: 2,
- asm: x86.AVPSLLD,
+ name: "VPMINSW128",
+ argLen: 2,
+ commutative: true,
+ asm: x86.AVPMINSW,
reg: regInfo{
inputs: []inputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
{
- name: "VPSLLDMasked256",
- argLen: 3,
- asm: x86.AVPSLLD,
- reg: regInfo{
- inputs: []inputInfo{
- {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
- {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
- },
- outputs: []outputInfo{
- {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
- },
- },
- },
- {
- name: "VPSRAD256",
- argLen: 2,
- asm: x86.AVPSRAD,
+ name: "VPMINSW256",
+ argLen: 2,
+ commutative: true,
+ asm: x86.AVPMINSW,
reg: regInfo{
inputs: []inputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
{
- name: "VPSRADMasked256",
- argLen: 3,
- asm: x86.AVPSRAD,
+ name: "VPMINSW512",
+ argLen: 2,
+ commutative: true,
+ asm: x86.AVPMINSW,
reg: regInfo{
inputs: []inputInfo{
- {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
- {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
- },
- outputs: []outputInfo{
{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
- },
- },
- },
- {
- name: "VPSLLVD256",
- argLen: 2,
- asm: x86.AVPSLLVD,
- reg: regInfo{
- inputs: []inputInfo{
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {1, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
},
outputs: []outputInfo{
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
},
},
},
{
- name: "VPSHLDVD256",
- argLen: 3,
- resultInArg0: true,
- asm: x86.AVPSHLDVD,
+ name: "VPMINSWMasked128",
+ argLen: 3,
+ commutative: true,
+ asm: x86.AVPMINSW,
reg: regInfo{
inputs: []inputInfo{
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
{
- name: "VPSHLDVDMasked256",
- argLen: 4,
- resultInArg0: true,
- asm: x86.AVPSHLDVD,
+ name: "VPMINSWMasked256",
+ argLen: 3,
+ commutative: true,
+ asm: x86.AVPMINSW,
reg: regInfo{
inputs: []inputInfo{
- {3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+ {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
{
- name: "VPSLLVDMasked256",
- argLen: 3,
- asm: x86.AVPSLLVD,
+ name: "VPMINSWMasked512",
+ argLen: 3,
+ commutative: true,
+ asm: x86.AVPMINSW,
reg: regInfo{
inputs: []inputInfo{
{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
},
},
{
- name: "VPSRAVD256",
- argLen: 2,
- asm: x86.AVPSRAVD,
+ name: "VPMINUB128",
+ argLen: 2,
+ commutative: true,
+ asm: x86.AVPMINUB,
reg: regInfo{
inputs: []inputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
{
- name: "VPSHRDVD256",
- argLen: 3,
- resultInArg0: true,
- asm: x86.AVPSHRDVD,
+ name: "VPMINUB256",
+ argLen: 2,
+ commutative: true,
+ asm: x86.AVPMINUB,
reg: regInfo{
inputs: []inputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
{
- name: "VPSHRDVDMasked256",
- argLen: 4,
- resultInArg0: true,
- asm: x86.AVPSHRDVD,
+ name: "VPMINUB512",
+ argLen: 2,
+ commutative: true,
+ asm: x86.AVPMINUB,
reg: regInfo{
inputs: []inputInfo{
- {3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ {1, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ },
+ outputs: []outputInfo{
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ },
+ },
+ },
+ {
+ name: "VPMINUBMasked128",
+ argLen: 3,
+ commutative: true,
+ asm: x86.AVPMINUB,
+ reg: regInfo{
+ inputs: []inputInfo{
+ {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
{
- name: "VPSRAVDMasked256",
- argLen: 3,
- asm: x86.AVPSRAVD,
+ name: "VPMINUBMasked256",
+ argLen: 3,
+ commutative: true,
+ asm: x86.AVPMINUB,
reg: regInfo{
inputs: []inputInfo{
{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
},
},
{
- name: "VPSIGND256",
- argLen: 2,
- asm: x86.AVPSIGND,
+ name: "VPMINUBMasked512",
+ argLen: 3,
+ commutative: true,
+ asm: x86.AVPMINUB,
reg: regInfo{
inputs: []inputInfo{
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
{
- name: "VPSUBD256",
- argLen: 2,
- asm: x86.AVPSUBD,
+ name: "VPMINUD128",
+ argLen: 2,
+ commutative: true,
+ asm: x86.AVPMINUD,
reg: regInfo{
inputs: []inputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
{
- name: "VPSUBDMasked256",
- argLen: 3,
- asm: x86.AVPSUBD,
+ name: "VPMINUD256",
+ argLen: 2,
+ commutative: true,
+ asm: x86.AVPMINUD,
reg: regInfo{
inputs: []inputInfo{
- {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
{
- name: "VPDPBUSD256",
- argLen: 3,
- resultInArg0: true,
- asm: x86.AVPDPBUSD,
+ name: "VPMINUD512",
+ argLen: 2,
+ commutative: true,
+ asm: x86.AVPMINUD,
reg: regInfo{
inputs: []inputInfo{
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ {1, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
},
outputs: []outputInfo{
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
},
},
},
{
- name: "VPDPBUSDMasked256",
- argLen: 4,
- resultInArg0: true,
- asm: x86.AVPDPBUSD,
+ name: "VPMINUDMasked128",
+ argLen: 3,
+ commutative: true,
+ asm: x86.AVPMINUD,
reg: regInfo{
inputs: []inputInfo{
- {3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+ {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
{
- name: "VPXORDMasked256",
+ name: "VPMINUDMasked256",
argLen: 3,
commutative: true,
- asm: x86.AVPXORD,
+ asm: x86.AVPMINUD,
reg: regInfo{
inputs: []inputInfo{
{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
},
},
{
- name: "VPABSQ128",
- argLen: 1,
- asm: x86.AVPABSQ,
+ name: "VPMINUDMasked512",
+ argLen: 3,
+ commutative: true,
+ asm: x86.AVPMINUD,
reg: regInfo{
inputs: []inputInfo{
- {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
- {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
},
{
- name: "VPABSQMasked128",
- argLen: 2,
- asm: x86.AVPABSQ,
+ name: "VPMINUQ128",
+ argLen: 2,
+ commutative: true,
+ asm: x86.AVPMINUQ,
reg: regInfo{
inputs: []inputInfo{
- {1, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ {1, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
},
outputs: []outputInfo{
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
},
},
},
{
- name: "VPADDQ128",
+ name: "VPMINUQ256",
argLen: 2,
commutative: true,
- asm: x86.AVPADDQ,
+ asm: x86.AVPMINUQ,
reg: regInfo{
inputs: []inputInfo{
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ {1, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
},
outputs: []outputInfo{
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
},
},
},
{
- name: "VPADDQMasked128",
- argLen: 3,
+ name: "VPMINUQ512",
+ argLen: 2,
commutative: true,
- asm: x86.AVPADDQ,
+ asm: x86.AVPMINUQ,
reg: regInfo{
inputs: []inputInfo{
- {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ {1, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
},
outputs: []outputInfo{
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
},
},
},
{
- name: "VPANDQMasked128",
+ name: "VPMINUQMasked128",
argLen: 3,
commutative: true,
- asm: x86.AVPANDQ,
+ asm: x86.AVPMINUQ,
reg: regInfo{
inputs: []inputInfo{
{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
},
},
{
- name: "VPANDNQMasked128",
- argLen: 3,
- asm: x86.AVPANDNQ,
+ name: "VPMINUQMasked256",
+ argLen: 3,
+ commutative: true,
+ asm: x86.AVPMINUQ,
reg: regInfo{
inputs: []inputInfo{
{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
},
},
{
- name: "VPCOMPRESSQMasked128",
- argLen: 2,
- asm: x86.AVPCOMPRESSQ,
+ name: "VPMINUQMasked512",
+ argLen: 3,
+ commutative: true,
+ asm: x86.AVPMINUQ,
reg: regInfo{
inputs: []inputInfo{
- {1, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+ {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
{
- name: "VPCMPEQQ128",
+ name: "VPMINUW128",
argLen: 2,
commutative: true,
- asm: x86.AVPCMPEQQ,
+ asm: x86.AVPMINUW,
reg: regInfo{
inputs: []inputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
{
- name: "VPCMPGTQ128",
- argLen: 2,
- asm: x86.AVPCMPGTQ,
+ name: "VPMINUW256",
+ argLen: 2,
+ commutative: true,
+ asm: x86.AVPMINUW,
reg: regInfo{
inputs: []inputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
{
- name: "VPMAXSQ128",
+ name: "VPMINUW512",
argLen: 2,
commutative: true,
- asm: x86.AVPMAXSQ,
+ asm: x86.AVPMINUW,
reg: regInfo{
inputs: []inputInfo{
{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
},
},
{
- name: "VPMAXSQMasked128",
+ name: "VPMINUWMasked128",
argLen: 3,
commutative: true,
- asm: x86.AVPMAXSQ,
+ asm: x86.AVPMINUW,
reg: regInfo{
inputs: []inputInfo{
{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
},
},
{
- name: "VPMINSQ128",
- argLen: 2,
+ name: "VPMINUWMasked256",
+ argLen: 3,
commutative: true,
- asm: x86.AVPMINSQ,
+ asm: x86.AVPMINUW,
reg: regInfo{
inputs: []inputInfo{
- {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
- {1, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
- {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
},
{
- name: "VPMINSQMasked128",
+ name: "VPMINUWMasked512",
argLen: 3,
commutative: true,
- asm: x86.AVPMINSQ,
+ asm: x86.AVPMINUW,
reg: regInfo{
inputs: []inputInfo{
{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
},
},
{
- name: "VPMULDQMasked128",
- argLen: 3,
+ name: "VPMULDQ128",
+ argLen: 2,
commutative: true,
asm: x86.AVPMULDQ,
reg: regInfo{
inputs: []inputInfo{
- {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
{
- name: "VPMULLQ128",
+ name: "VPMULDQ256",
argLen: 2,
commutative: true,
- asm: x86.AVPMULLQ,
+ asm: x86.AVPMULDQ,
reg: regInfo{
inputs: []inputInfo{
- {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
- {1, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
- {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
},
{
- name: "VPMULLQMasked128",
- argLen: 3,
+ name: "VPMULDQ512",
+ argLen: 2,
commutative: true,
- asm: x86.AVPMULLQ,
+ asm: x86.AVPMULDQ,
reg: regInfo{
inputs: []inputInfo{
- {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ {1, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
},
outputs: []outputInfo{
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
},
},
},
{
- name: "VPORQMasked128",
+ name: "VPMULDQMasked128",
argLen: 3,
commutative: true,
- asm: x86.AVPORQ,
+ asm: x86.AVPMULDQ,
reg: regInfo{
inputs: []inputInfo{
{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
},
},
{
- name: "VPOPCNTQ128",
- argLen: 1,
- asm: x86.AVPOPCNTQ,
+ name: "VPMULDQMasked256",
+ argLen: 3,
+ commutative: true,
+ asm: x86.AVPMULDQ,
reg: regInfo{
inputs: []inputInfo{
- {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
- {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
},
{
- name: "VPOPCNTQMasked128",
- argLen: 2,
- asm: x86.AVPOPCNTQ,
+ name: "VPMULDQMasked512",
+ argLen: 3,
+ commutative: true,
+ asm: x86.AVPMULDQ,
reg: regInfo{
inputs: []inputInfo{
- {1, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+ {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
{
- name: "VPROLVQ128",
- argLen: 2,
- asm: x86.AVPROLVQ,
+ name: "VPMULHUW128",
+ argLen: 2,
+ commutative: true,
+ asm: x86.AVPMULHUW,
reg: regInfo{
inputs: []inputInfo{
- {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
- {1, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
- {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
},
{
- name: "VPROLVQMasked128",
- argLen: 3,
- asm: x86.AVPROLVQ,
+ name: "VPMULHUW256",
+ argLen: 2,
+ commutative: true,
+ asm: x86.AVPMULHUW,
reg: regInfo{
inputs: []inputInfo{
- {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
{
- name: "VPRORVQ128",
- argLen: 2,
- asm: x86.AVPRORVQ,
+ name: "VPMULHUW512",
+ argLen: 2,
+ commutative: true,
+ asm: x86.AVPMULHUW,
reg: regInfo{
inputs: []inputInfo{
{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
},
},
{
- name: "VPRORVQMasked128",
- argLen: 3,
- asm: x86.AVPRORVQ,
+ name: "VPMULHUWMasked128",
+ argLen: 3,
+ commutative: true,
+ asm: x86.AVPMULHUW,
reg: regInfo{
inputs: []inputInfo{
{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
},
},
{
- name: "VPSLLQ128",
- argLen: 2,
- asm: x86.AVPSLLQ,
+ name: "VPMULHUWMasked256",
+ argLen: 3,
+ commutative: true,
+ asm: x86.AVPMULHUW,
reg: regInfo{
inputs: []inputInfo{
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
{
- name: "VPSLLQMasked128",
- argLen: 3,
- asm: x86.AVPSLLQ,
+ name: "VPMULHUWMasked512",
+ argLen: 3,
+ commutative: true,
+ asm: x86.AVPMULHUW,
reg: regInfo{
inputs: []inputInfo{
{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
},
outputs: []outputInfo{
- {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
- },
- },
- },
- {
- name: "VPSRAQ128",
- argLen: 2,
- asm: x86.AVPSRAQ,
- reg: regInfo{
- inputs: []inputInfo{
- {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
- },
- outputs: []outputInfo{
- {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
},
{
- name: "VPSRAQMasked128",
- argLen: 3,
- asm: x86.AVPSRAQ,
+ name: "VPMULHW128",
+ argLen: 2,
+ commutative: true,
+ asm: x86.AVPMULHW,
reg: regInfo{
inputs: []inputInfo{
- {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
- {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
- {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
},
{
- name: "VPSLLVQ128",
- argLen: 2,
- asm: x86.AVPSLLVQ,
+ name: "VPMULHW256",
+ argLen: 2,
+ commutative: true,
+ asm: x86.AVPMULHW,
reg: regInfo{
inputs: []inputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
{
- name: "VPSHLDVQ128",
- argLen: 3,
- resultInArg0: true,
- asm: x86.AVPSHLDVQ,
+ name: "VPMULHW512",
+ argLen: 2,
+ commutative: true,
+ asm: x86.AVPMULHW,
reg: regInfo{
inputs: []inputInfo{
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ {1, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
},
outputs: []outputInfo{
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
},
},
},
{
- name: "VPSHLDVQMasked128",
- argLen: 4,
- resultInArg0: true,
- asm: x86.AVPSHLDVQ,
+ name: "VPMULHWMasked128",
+ argLen: 3,
+ commutative: true,
+ asm: x86.AVPMULHW,
reg: regInfo{
inputs: []inputInfo{
- {3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+ {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
{
- name: "VPSLLVQMasked128",
- argLen: 3,
- asm: x86.AVPSLLVQ,
+ name: "VPMULHWMasked256",
+ argLen: 3,
+ commutative: true,
+ asm: x86.AVPMULHW,
reg: regInfo{
inputs: []inputInfo{
{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
},
},
{
- name: "VPSRAVQ128",
- argLen: 2,
- asm: x86.AVPSRAVQ,
+ name: "VPMULHWMasked512",
+ argLen: 3,
+ commutative: true,
+ asm: x86.AVPMULHW,
reg: regInfo{
inputs: []inputInfo{
- {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
- {1, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
- {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
},
{
- name: "VPSHRDVQ128",
- argLen: 3,
- resultInArg0: true,
- asm: x86.AVPSHRDVQ,
+ name: "VPMULLD128",
+ argLen: 2,
+ commutative: true,
+ asm: x86.AVPMULLD,
reg: regInfo{
inputs: []inputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
{
- name: "VPSHRDVQMasked128",
- argLen: 4,
- resultInArg0: true,
- asm: x86.AVPSHRDVQ,
+ name: "VPMULLD256",
+ argLen: 2,
+ commutative: true,
+ asm: x86.AVPMULLD,
reg: regInfo{
inputs: []inputInfo{
- {3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
{
- name: "VPSRAVQMasked128",
- argLen: 3,
- asm: x86.AVPSRAVQ,
+ name: "VPMULLD512",
+ argLen: 2,
+ commutative: true,
+ asm: x86.AVPMULLD,
reg: regInfo{
inputs: []inputInfo{
- {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ {1, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
},
outputs: []outputInfo{
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
},
},
},
{
- name: "VPSUBQ128",
- argLen: 2,
- asm: x86.AVPSUBQ,
+ name: "VPMULLDMasked128",
+ argLen: 3,
+ commutative: true,
+ asm: x86.AVPMULLD,
reg: regInfo{
inputs: []inputInfo{
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
{
- name: "VPSUBQMasked128",
- argLen: 3,
- asm: x86.AVPSUBQ,
+ name: "VPMULLDMasked256",
+ argLen: 3,
+ commutative: true,
+ asm: x86.AVPMULLD,
reg: regInfo{
inputs: []inputInfo{
{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
},
},
{
- name: "VPXORQMasked128",
+ name: "VPMULLDMasked512",
argLen: 3,
commutative: true,
- asm: x86.AVPXORQ,
+ asm: x86.AVPMULLD,
reg: regInfo{
inputs: []inputInfo{
{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
},
},
{
- name: "VPABSQ256",
- argLen: 1,
- asm: x86.AVPABSQ,
+ name: "VPMULLQ128",
+ argLen: 2,
+ commutative: true,
+ asm: x86.AVPMULLQ,
reg: regInfo{
inputs: []inputInfo{
{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ {1, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
},
outputs: []outputInfo{
{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
},
},
{
- name: "VPABSQMasked256",
- argLen: 2,
- asm: x86.AVPABSQ,
+ name: "VPMULLQ256",
+ argLen: 2,
+ commutative: true,
+ asm: x86.AVPMULLQ,
reg: regInfo{
inputs: []inputInfo{
- {1, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ {1, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
},
outputs: []outputInfo{
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
},
},
},
{
- name: "VPADDQ256",
+ name: "VPMULLQ512",
argLen: 2,
commutative: true,
- asm: x86.AVPADDQ,
+ asm: x86.AVPMULLQ,
reg: regInfo{
inputs: []inputInfo{
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ {1, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
},
outputs: []outputInfo{
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
},
},
},
{
- name: "VPADDQMasked256",
+ name: "VPMULLQMasked128",
argLen: 3,
commutative: true,
- asm: x86.AVPADDQ,
+ asm: x86.AVPMULLQ,
reg: regInfo{
inputs: []inputInfo{
{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
},
},
{
- name: "VPANDQMasked256",
+ name: "VPMULLQMasked256",
argLen: 3,
commutative: true,
- asm: x86.AVPANDQ,
+ asm: x86.AVPMULLQ,
reg: regInfo{
inputs: []inputInfo{
{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
},
},
{
- name: "VPANDNQMasked256",
- argLen: 3,
- asm: x86.AVPANDNQ,
+ name: "VPMULLQMasked512",
+ argLen: 3,
+ commutative: true,
+ asm: x86.AVPMULLQ,
reg: regInfo{
inputs: []inputInfo{
{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
},
},
{
- name: "VPCOMPRESSQMasked256",
- argLen: 2,
- asm: x86.AVPCOMPRESSQ,
- reg: regInfo{
- inputs: []inputInfo{
- {1, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- },
- outputs: []outputInfo{
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- },
- },
- },
- {
- name: "VPCMPEQQ256",
+ name: "VPMULLW128",
argLen: 2,
commutative: true,
- asm: x86.AVPCMPEQQ,
+ asm: x86.AVPMULLW,
reg: regInfo{
inputs: []inputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
{
- name: "VPCMPGTQ256",
- argLen: 2,
- asm: x86.AVPCMPGTQ,
+ name: "VPMULLW256",
+ argLen: 2,
+ commutative: true,
+ asm: x86.AVPMULLW,
reg: regInfo{
inputs: []inputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
{
- name: "VPMAXSQ256",
+ name: "VPMULLW512",
argLen: 2,
commutative: true,
- asm: x86.AVPMAXSQ,
+ asm: x86.AVPMULLW,
reg: regInfo{
inputs: []inputInfo{
{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
},
},
{
- name: "VPMAXSQMasked256",
+ name: "VPMULLWMasked128",
argLen: 3,
commutative: true,
- asm: x86.AVPMAXSQ,
+ asm: x86.AVPMULLW,
reg: regInfo{
inputs: []inputInfo{
{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
},
},
{
- name: "VPMINSQ256",
- argLen: 2,
+ name: "VPMULLWMasked256",
+ argLen: 3,
commutative: true,
- asm: x86.AVPMINSQ,
+ asm: x86.AVPMULLW,
reg: regInfo{
inputs: []inputInfo{
- {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
- {1, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
- {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
},
{
- name: "VPMINSQMasked256",
+ name: "VPMULLWMasked512",
argLen: 3,
commutative: true,
- asm: x86.AVPMINSQ,
+ asm: x86.AVPMULLW,
reg: regInfo{
inputs: []inputInfo{
{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
},
},
{
- name: "VPMULDQMasked256",
- argLen: 3,
+ name: "VPMULUDQ128",
+ argLen: 2,
commutative: true,
- asm: x86.AVPMULDQ,
+ asm: x86.AVPMULUDQ,
reg: regInfo{
inputs: []inputInfo{
- {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
{
- name: "VPMULLQ256",
+ name: "VPMULUDQ256",
argLen: 2,
commutative: true,
- asm: x86.AVPMULLQ,
+ asm: x86.AVPMULUDQ,
+ reg: regInfo{
+ inputs: []inputInfo{
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ },
+ outputs: []outputInfo{
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ },
+ },
+ },
+ {
+ name: "VPMULUDQ512",
+ argLen: 2,
+ commutative: true,
+ asm: x86.AVPMULUDQ,
reg: regInfo{
inputs: []inputInfo{
{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
},
},
{
- name: "VPMULLQMasked256",
+ name: "VPMULUDQMasked128",
argLen: 3,
commutative: true,
- asm: x86.AVPMULLQ,
+ asm: x86.AVPMULUDQ,
reg: regInfo{
inputs: []inputInfo{
{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
},
},
{
- name: "VPORQMasked256",
+ name: "VPMULUDQMasked256",
argLen: 3,
commutative: true,
- asm: x86.AVPORQ,
+ asm: x86.AVPMULUDQ,
reg: regInfo{
inputs: []inputInfo{
{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
},
},
{
- name: "VPOPCNTQ256",
- argLen: 1,
- asm: x86.AVPOPCNTQ,
+ name: "VPMULUDQMasked512",
+ argLen: 3,
+ commutative: true,
+ asm: x86.AVPMULUDQ,
reg: regInfo{
inputs: []inputInfo{
- {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
- {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
},
{
- name: "VPOPCNTQMasked256",
- argLen: 2,
- asm: x86.AVPOPCNTQ,
+ name: "VPOPCNTB128",
+ argLen: 1,
+ asm: x86.AVPOPCNTB,
reg: regInfo{
inputs: []inputInfo{
- {1, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
},
outputs: []outputInfo{
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
},
},
},
{
- name: "VPROLVQ256",
- argLen: 2,
- asm: x86.AVPROLVQ,
+ name: "VPOPCNTB256",
+ argLen: 1,
+ asm: x86.AVPOPCNTB,
reg: regInfo{
inputs: []inputInfo{
{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
- {1, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
},
outputs: []outputInfo{
{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
},
},
{
- name: "VPROLVQMasked256",
- argLen: 3,
- asm: x86.AVPROLVQ,
+ name: "VPOPCNTB512",
+ argLen: 1,
+ asm: x86.AVPOPCNTB,
reg: regInfo{
inputs: []inputInfo{
- {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
},
outputs: []outputInfo{
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
},
},
},
{
- name: "VPRORVQ256",
+ name: "VPOPCNTBMasked128",
argLen: 2,
- asm: x86.AVPRORVQ,
+ asm: x86.AVPOPCNTB,
reg: regInfo{
inputs: []inputInfo{
- {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
- {1, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ {1, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
- {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
},
{
- name: "VPRORVQMasked256",
- argLen: 3,
- asm: x86.AVPRORVQ,
+ name: "VPOPCNTBMasked256",
+ argLen: 2,
+ asm: x86.AVPOPCNTB,
reg: regInfo{
inputs: []inputInfo{
- {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+ {1, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
{
- name: "VPSLLQ256",
+ name: "VPOPCNTBMasked512",
argLen: 2,
- asm: x86.AVPSLLQ,
+ asm: x86.AVPOPCNTB,
reg: regInfo{
inputs: []inputInfo{
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {1, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
{
- name: "VPSLLQMasked256",
- argLen: 3,
- asm: x86.AVPSLLQ,
+ name: "VPOPCNTD128",
+ argLen: 1,
+ asm: x86.AVPOPCNTD,
reg: regInfo{
inputs: []inputInfo{
- {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
- {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
},
outputs: []outputInfo{
{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
},
},
{
- name: "VPSRAQ256",
- argLen: 2,
- asm: x86.AVPSRAQ,
+ name: "VPOPCNTD256",
+ argLen: 1,
+ asm: x86.AVPOPCNTD,
reg: regInfo{
inputs: []inputInfo{
- {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
},
outputs: []outputInfo{
},
},
{
- name: "VPSRAQMasked256",
- argLen: 3,
- asm: x86.AVPSRAQ,
+ name: "VPOPCNTD512",
+ argLen: 1,
+ asm: x86.AVPOPCNTD,
reg: regInfo{
inputs: []inputInfo{
- {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
- {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
},
outputs: []outputInfo{
{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
},
},
{
- name: "VPSLLVQ256",
+ name: "VPOPCNTDMasked128",
argLen: 2,
- asm: x86.AVPSLLVQ,
+ asm: x86.AVPOPCNTD,
reg: regInfo{
inputs: []inputInfo{
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {1, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
{
- name: "VPSHLDVQ256",
- argLen: 3,
- resultInArg0: true,
- asm: x86.AVPSHLDVQ,
+ name: "VPOPCNTDMasked256",
+ argLen: 2,
+ asm: x86.AVPOPCNTD,
reg: regInfo{
inputs: []inputInfo{
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {1, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
{
- name: "VPSHLDVQMasked256",
- argLen: 4,
- resultInArg0: true,
- asm: x86.AVPSHLDVQ,
+ name: "VPOPCNTDMasked512",
+ argLen: 2,
+ asm: x86.AVPOPCNTD,
reg: regInfo{
inputs: []inputInfo{
- {3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+ {1, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
{
- name: "VPSLLVQMasked256",
- argLen: 3,
- asm: x86.AVPSLLVQ,
+ name: "VPOPCNTQ128",
+ argLen: 1,
+ asm: x86.AVPOPCNTQ,
reg: regInfo{
inputs: []inputInfo{
- {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
},
outputs: []outputInfo{
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
},
},
},
{
- name: "VPSRAVQ256",
- argLen: 2,
- asm: x86.AVPSRAVQ,
+ name: "VPOPCNTQ256",
+ argLen: 1,
+ asm: x86.AVPOPCNTQ,
reg: regInfo{
inputs: []inputInfo{
{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
- {1, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
},
outputs: []outputInfo{
{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
},
},
{
- name: "VPSHRDVQ256",
- argLen: 3,
- resultInArg0: true,
- asm: x86.AVPSHRDVQ,
+ name: "VPOPCNTQ512",
+ argLen: 1,
+ asm: x86.AVPOPCNTQ,
reg: regInfo{
inputs: []inputInfo{
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
},
outputs: []outputInfo{
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
},
},
},
{
- name: "VPSHRDVQMasked256",
- argLen: 4,
- resultInArg0: true,
- asm: x86.AVPSHRDVQ,
+ name: "VPOPCNTQMasked128",
+ argLen: 2,
+ asm: x86.AVPOPCNTQ,
reg: regInfo{
inputs: []inputInfo{
- {3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+ {1, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
{
- name: "VPSRAVQMasked256",
- argLen: 3,
- asm: x86.AVPSRAVQ,
+ name: "VPOPCNTQMasked256",
+ argLen: 2,
+ asm: x86.AVPOPCNTQ,
reg: regInfo{
inputs: []inputInfo{
- {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+ {1, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
{
- name: "VPSUBQ256",
+ name: "VPOPCNTQMasked512",
argLen: 2,
- asm: x86.AVPSUBQ,
+ asm: x86.AVPOPCNTQ,
reg: regInfo{
inputs: []inputInfo{
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {1, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
{
- name: "VPSUBQMasked256",
- argLen: 3,
- asm: x86.AVPSUBQ,
+ name: "VPOPCNTW128",
+ argLen: 1,
+ asm: x86.AVPOPCNTW,
reg: regInfo{
inputs: []inputInfo{
- {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
},
outputs: []outputInfo{
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
},
},
},
{
- name: "VPXORQMasked256",
- argLen: 3,
- commutative: true,
- asm: x86.AVPXORQ,
+ name: "VPOPCNTW256",
+ argLen: 1,
+ asm: x86.AVPOPCNTW,
reg: regInfo{
inputs: []inputInfo{
- {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
},
outputs: []outputInfo{
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
},
},
},
{
- name: "VPABSQ512",
+ name: "VPOPCNTW512",
argLen: 1,
- asm: x86.AVPABSQ,
+ asm: x86.AVPOPCNTW,
reg: regInfo{
inputs: []inputInfo{
{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
},
},
{
- name: "VPABSQMasked512",
+ name: "VPOPCNTWMasked128",
argLen: 2,
- asm: x86.AVPABSQ,
+ asm: x86.AVPOPCNTW,
reg: regInfo{
inputs: []inputInfo{
{1, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
},
},
{
- name: "VPADDQ512",
- argLen: 2,
- commutative: true,
- asm: x86.AVPADDQ,
+ name: "VPOPCNTWMasked256",
+ argLen: 2,
+ asm: x86.AVPOPCNTW,
reg: regInfo{
inputs: []inputInfo{
- {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
- {1, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ {1, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
- {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
},
{
- name: "VPADDQMasked512",
- argLen: 3,
- commutative: true,
- asm: x86.AVPADDQ,
+ name: "VPOPCNTWMasked512",
+ argLen: 2,
+ asm: x86.AVPOPCNTW,
reg: regInfo{
inputs: []inputInfo{
- {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+ {1, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
{
- name: "VPANDQ512",
+ name: "VPOR128",
argLen: 2,
commutative: true,
- asm: x86.AVPANDQ,
+ asm: x86.AVPOR,
reg: regInfo{
inputs: []inputInfo{
- {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
- {1, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
- {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
},
{
- name: "VPANDQMasked512",
- argLen: 3,
+ name: "VPOR256",
+ argLen: 2,
commutative: true,
- asm: x86.AVPANDQ,
+ asm: x86.AVPOR,
reg: regInfo{
inputs: []inputInfo{
- {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
{
- name: "VPANDNQ512",
- argLen: 2,
- asm: x86.AVPANDNQ,
+ name: "VPORD512",
+ argLen: 2,
+ commutative: true,
+ asm: x86.AVPORD,
reg: regInfo{
inputs: []inputInfo{
{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
},
},
{
- name: "VPANDNQMasked512",
- argLen: 3,
- asm: x86.AVPANDNQ,
+ name: "VPORDMasked128",
+ argLen: 3,
+ commutative: true,
+ asm: x86.AVPORD,
reg: regInfo{
inputs: []inputInfo{
{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
},
},
{
- name: "VPCOMPRESSQMasked512",
- argLen: 2,
- asm: x86.AVPCOMPRESSQ,
+ name: "VPORDMasked256",
+ argLen: 3,
+ commutative: true,
+ asm: x86.AVPORD,
reg: regInfo{
inputs: []inputInfo{
- {1, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+ {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
{
- name: "VPCMPEQQ512",
- argLen: 2,
+ name: "VPORDMasked512",
+ argLen: 3,
commutative: true,
- asm: x86.AVPCMPEQQ,
+ asm: x86.AVPORD,
reg: regInfo{
inputs: []inputInfo{
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
- {0, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
- },
- },
- },
- {
- name: "VPCMPGTQ512",
- argLen: 2,
- asm: x86.AVPCMPGTQ,
- reg: regInfo{
- inputs: []inputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- },
- outputs: []outputInfo{
- {0, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
},
},
},
{
- name: "VPMAXSQ512",
+ name: "VPORQ512",
argLen: 2,
commutative: true,
- asm: x86.AVPMAXSQ,
+ asm: x86.AVPORQ,
reg: regInfo{
inputs: []inputInfo{
{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
},
},
{
- name: "VPMAXSQMasked512",
+ name: "VPORQMasked128",
argLen: 3,
commutative: true,
- asm: x86.AVPMAXSQ,
+ asm: x86.AVPORQ,
reg: regInfo{
inputs: []inputInfo{
{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
},
},
{
- name: "VPMINSQ512",
- argLen: 2,
- commutative: true,
- asm: x86.AVPMINSQ,
- reg: regInfo{
- inputs: []inputInfo{
- {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
- {1, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
- },
- outputs: []outputInfo{
- {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
- },
- },
- },
- {
- name: "VPMINSQMasked512",
+ name: "VPORQMasked256",
argLen: 3,
commutative: true,
- asm: x86.AVPMINSQ,
+ asm: x86.AVPORQ,
reg: regInfo{
inputs: []inputInfo{
{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
},
},
{
- name: "VPMULDQ512",
- argLen: 2,
- commutative: true,
- asm: x86.AVPMULDQ,
- reg: regInfo{
- inputs: []inputInfo{
- {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
- {1, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
- },
- outputs: []outputInfo{
- {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
- },
- },
- },
- {
- name: "VPMULDQMasked512",
+ name: "VPORQMasked512",
argLen: 3,
commutative: true,
- asm: x86.AVPMULDQ,
+ asm: x86.AVPORQ,
reg: regInfo{
inputs: []inputInfo{
{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
},
},
{
- name: "VPMULLQ512",
- argLen: 2,
- commutative: true,
- asm: x86.AVPMULLQ,
+ name: "VPROLVD128",
+ argLen: 2,
+ asm: x86.AVPROLVD,
reg: regInfo{
inputs: []inputInfo{
{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
},
},
{
- name: "VPMULLQMasked512",
- argLen: 3,
- commutative: true,
- asm: x86.AVPMULLQ,
+ name: "VPROLVD256",
+ argLen: 2,
+ asm: x86.AVPROLVD,
reg: regInfo{
inputs: []inputInfo{
- {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ {1, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
},
outputs: []outputInfo{
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
},
},
},
{
- name: "VPORQ512",
- argLen: 2,
- commutative: true,
- asm: x86.AVPORQ,
+ name: "VPROLVD512",
+ argLen: 2,
+ asm: x86.AVPROLVD,
reg: regInfo{
inputs: []inputInfo{
{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
},
},
{
- name: "VPORQMasked512",
- argLen: 3,
- commutative: true,
- asm: x86.AVPORQ,
+ name: "VPROLVDMasked128",
+ argLen: 3,
+ asm: x86.AVPROLVD,
reg: regInfo{
inputs: []inputInfo{
{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
},
},
{
- name: "VPOPCNTQ512",
- argLen: 1,
- asm: x86.AVPOPCNTQ,
+ name: "VPROLVDMasked256",
+ argLen: 3,
+ asm: x86.AVPROLVD,
reg: regInfo{
inputs: []inputInfo{
- {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
- {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
},
{
- name: "VPOPCNTQMasked512",
- argLen: 2,
- asm: x86.AVPOPCNTQ,
+ name: "VPROLVDMasked512",
+ argLen: 3,
+ asm: x86.AVPROLVD,
reg: regInfo{
inputs: []inputInfo{
- {1, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+ {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
{
- name: "VPROLVQ512",
+ name: "VPROLVQ128",
argLen: 2,
asm: x86.AVPROLVQ,
reg: regInfo{
},
},
{
- name: "VPROLVQMasked512",
- argLen: 3,
+ name: "VPROLVQ256",
+ argLen: 2,
asm: x86.AVPROLVQ,
reg: regInfo{
inputs: []inputInfo{
- {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ {1, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
},
outputs: []outputInfo{
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
},
},
},
{
- name: "VPRORVQ512",
+ name: "VPROLVQ512",
argLen: 2,
- asm: x86.AVPRORVQ,
+ asm: x86.AVPROLVQ,
reg: regInfo{
inputs: []inputInfo{
{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
},
},
{
- name: "VPRORVQMasked512",
+ name: "VPROLVQMasked128",
argLen: 3,
- asm: x86.AVPRORVQ,
+ asm: x86.AVPROLVQ,
reg: regInfo{
inputs: []inputInfo{
{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
},
},
{
- name: "VPSLLQ512",
- argLen: 2,
- asm: x86.AVPSLLQ,
+ name: "VPROLVQMasked256",
+ argLen: 3,
+ asm: x86.AVPROLVQ,
reg: regInfo{
inputs: []inputInfo{
- {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
- {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
},
{
- name: "VPSLLQMasked512",
+ name: "VPROLVQMasked512",
argLen: 3,
- asm: x86.AVPSLLQ,
+ asm: x86.AVPROLVQ,
reg: regInfo{
inputs: []inputInfo{
{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
},
outputs: []outputInfo{
- {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
},
{
- name: "VPSRAQ512",
+ name: "VPRORVD128",
argLen: 2,
- asm: x86.AVPSRAQ,
+ asm: x86.AVPRORVD,
reg: regInfo{
inputs: []inputInfo{
- {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ {1, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
},
outputs: []outputInfo{
{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
},
},
{
- name: "VPSRAQMasked512",
- argLen: 3,
- asm: x86.AVPSRAQ,
+ name: "VPRORVD256",
+ argLen: 2,
+ asm: x86.AVPRORVD,
reg: regInfo{
inputs: []inputInfo{
- {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
- {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ {1, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
},
outputs: []outputInfo{
{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
},
},
{
- name: "VPSLLVQ512",
+ name: "VPRORVD512",
argLen: 2,
- asm: x86.AVPSLLVQ,
+ asm: x86.AVPRORVD,
reg: regInfo{
inputs: []inputInfo{
{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
},
},
{
- name: "VPSHLDVQ512",
- argLen: 3,
- resultInArg0: true,
- asm: x86.AVPSHLDVQ,
+ name: "VPRORVDMasked128",
+ argLen: 3,
+ asm: x86.AVPRORVD,
reg: regInfo{
inputs: []inputInfo{
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
{
- name: "VPSHLDVQMasked512",
- argLen: 4,
- resultInArg0: true,
- asm: x86.AVPSHLDVQ,
+ name: "VPRORVDMasked256",
+ argLen: 3,
+ asm: x86.AVPRORVD,
reg: regInfo{
inputs: []inputInfo{
- {3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+ {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
{
- name: "VPSLLVQMasked512",
+ name: "VPRORVDMasked512",
argLen: 3,
- asm: x86.AVPSLLVQ,
+ asm: x86.AVPRORVD,
reg: regInfo{
inputs: []inputInfo{
{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
},
},
{
- name: "VPSRAVQ512",
+ name: "VPRORVQ128",
argLen: 2,
- asm: x86.AVPSRAVQ,
+ asm: x86.AVPRORVQ,
reg: regInfo{
inputs: []inputInfo{
{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
},
},
{
- name: "VPSHRDVQ512",
- argLen: 3,
- resultInArg0: true,
- asm: x86.AVPSHRDVQ,
+ name: "VPRORVQ256",
+ argLen: 2,
+ asm: x86.AVPRORVQ,
reg: regInfo{
inputs: []inputInfo{
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ {1, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
},
outputs: []outputInfo{
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
},
},
},
{
- name: "VPSHRDVQMasked512",
- argLen: 4,
- resultInArg0: true,
- asm: x86.AVPSHRDVQ,
+ name: "VPRORVQ512",
+ argLen: 2,
+ asm: x86.AVPRORVQ,
reg: regInfo{
inputs: []inputInfo{
- {3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ {1, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
},
outputs: []outputInfo{
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
},
},
},
{
- name: "VPSRAVQMasked512",
+ name: "VPRORVQMasked128",
argLen: 3,
- asm: x86.AVPSRAVQ,
+ asm: x86.AVPRORVQ,
reg: regInfo{
inputs: []inputInfo{
{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
},
},
{
- name: "VPSUBQ512",
- argLen: 2,
- asm: x86.AVPSUBQ,
+ name: "VPRORVQMasked256",
+ argLen: 3,
+ asm: x86.AVPRORVQ,
reg: regInfo{
inputs: []inputInfo{
- {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
- {1, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
- {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
},
{
- name: "VPSUBQMasked512",
+ name: "VPRORVQMasked512",
argLen: 3,
- asm: x86.AVPSUBQ,
+ asm: x86.AVPRORVQ,
reg: regInfo{
inputs: []inputInfo{
{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
},
},
{
- name: "VPXORQ512",
- argLen: 2,
- commutative: true,
- asm: x86.AVPXORQ,
+ name: "VPSHLDVD128",
+ argLen: 3,
+ resultInArg0: true,
+ asm: x86.AVPSHLDVD,
reg: regInfo{
inputs: []inputInfo{
- {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
- {1, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
- {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
},
{
- name: "VPXORQMasked512",
- argLen: 3,
- commutative: true,
- asm: x86.AVPXORQ,
+ name: "VPSHLDVD256",
+ argLen: 3,
+ resultInArg0: true,
+ asm: x86.AVPSHLDVD,
reg: regInfo{
inputs: []inputInfo{
- {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
{
- name: "VPABSB128",
- argLen: 1,
- asm: x86.AVPABSB,
+ name: "VPSHLDVD512",
+ argLen: 3,
+ resultInArg0: true,
+ asm: x86.AVPSHLDVD,
reg: regInfo{
inputs: []inputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
{
- name: "VPABSBMasked128",
- argLen: 2,
- asm: x86.AVPABSB,
+ name: "VPSHLDVDMasked128",
+ argLen: 4,
+ resultInArg0: true,
+ asm: x86.AVPSHLDVD,
reg: regInfo{
inputs: []inputInfo{
- {1, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+ {3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
{
- name: "VPADDB128",
- argLen: 2,
- commutative: true,
- asm: x86.AVPADDB,
+ name: "VPSHLDVDMasked256",
+ argLen: 4,
+ resultInArg0: true,
+ asm: x86.AVPSHLDVD,
reg: regInfo{
inputs: []inputInfo{
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
{
- name: "VPADDBMasked128",
- argLen: 3,
- commutative: true,
- asm: x86.AVPADDB,
+ name: "VPSHLDVDMasked512",
+ argLen: 4,
+ resultInArg0: true,
+ asm: x86.AVPSHLDVD,
reg: regInfo{
inputs: []inputInfo{
- {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+ {3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
{
- name: "VPAND128",
- argLen: 2,
- commutative: true,
- asm: x86.AVPAND,
+ name: "VPSHLDVQ128",
+ argLen: 3,
+ resultInArg0: true,
+ asm: x86.AVPSHLDVQ,
reg: regInfo{
inputs: []inputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
{
- name: "VPANDN128",
- argLen: 2,
- asm: x86.AVPANDN,
+ name: "VPSHLDVQ256",
+ argLen: 3,
+ resultInArg0: true,
+ asm: x86.AVPSHLDVQ,
reg: regInfo{
inputs: []inputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
{
- name: "VPCOMPRESSBMasked128",
- argLen: 2,
- asm: x86.AVPCOMPRESSB,
- reg: regInfo{
- inputs: []inputInfo{
- {1, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- },
- outputs: []outputInfo{
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- },
- },
- },
- {
- name: "VPCMPEQB128",
- argLen: 2,
- commutative: true,
- asm: x86.AVPCMPEQB,
+ name: "VPSHLDVQ512",
+ argLen: 3,
+ resultInArg0: true,
+ asm: x86.AVPSHLDVQ,
reg: regInfo{
inputs: []inputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
{
- name: "VPCMPGTB128",
- argLen: 2,
- asm: x86.AVPCMPGTB,
+ name: "VPSHLDVQMasked128",
+ argLen: 4,
+ resultInArg0: true,
+ asm: x86.AVPSHLDVQ,
reg: regInfo{
inputs: []inputInfo{
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
{
- name: "VPMAXSB128",
- argLen: 2,
- commutative: true,
- asm: x86.AVPMAXSB,
+ name: "VPSHLDVQMasked256",
+ argLen: 4,
+ resultInArg0: true,
+ asm: x86.AVPSHLDVQ,
reg: regInfo{
inputs: []inputInfo{
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
{
- name: "VPMAXSBMasked128",
- argLen: 3,
- commutative: true,
- asm: x86.AVPMAXSB,
+ name: "VPSHLDVQMasked512",
+ argLen: 4,
+ resultInArg0: true,
+ asm: x86.AVPSHLDVQ,
reg: regInfo{
inputs: []inputInfo{
- {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+ {3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
{
- name: "VPMINSB128",
- argLen: 2,
- commutative: true,
- asm: x86.AVPMINSB,
+ name: "VPSHLDVW128",
+ argLen: 3,
+ resultInArg0: true,
+ asm: x86.AVPSHLDVW,
reg: regInfo{
inputs: []inputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
{
- name: "VPMINSBMasked128",
- argLen: 3,
- commutative: true,
- asm: x86.AVPMINSB,
+ name: "VPSHLDVW256",
+ argLen: 3,
+ resultInArg0: true,
+ asm: x86.AVPSHLDVW,
reg: regInfo{
inputs: []inputInfo{
- {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
{
- name: "VPOR128",
- argLen: 2,
- commutative: true,
- asm: x86.AVPOR,
+ name: "VPSHLDVW512",
+ argLen: 3,
+ resultInArg0: true,
+ asm: x86.AVPSHLDVW,
reg: regInfo{
inputs: []inputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
{
- name: "VPOPCNTB128",
- argLen: 1,
- asm: x86.AVPOPCNTB,
+ name: "VPSHLDVWMasked128",
+ argLen: 4,
+ resultInArg0: true,
+ asm: x86.AVPSHLDVW,
reg: regInfo{
inputs: []inputInfo{
- {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ {3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
- {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
},
{
- name: "VPOPCNTBMasked128",
- argLen: 2,
- asm: x86.AVPOPCNTB,
+ name: "VPSHLDVWMasked256",
+ argLen: 4,
+ resultInArg0: true,
+ asm: x86.AVPSHLDVW,
reg: regInfo{
inputs: []inputInfo{
- {1, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+ {3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
{
- name: "VPADDSB128",
- argLen: 2,
- commutative: true,
- asm: x86.AVPADDSB,
+ name: "VPSHLDVWMasked512",
+ argLen: 4,
+ resultInArg0: true,
+ asm: x86.AVPSHLDVW,
reg: regInfo{
inputs: []inputInfo{
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
{
- name: "VPADDSBMasked128",
- argLen: 3,
- commutative: true,
- asm: x86.AVPADDSB,
+ name: "VPSHRDVD128",
+ argLen: 3,
+ resultInArg0: true,
+ asm: x86.AVPSHRDVD,
reg: regInfo{
inputs: []inputInfo{
- {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
{
- name: "VPSUBSB128",
- argLen: 2,
- asm: x86.AVPSUBSB,
+ name: "VPSHRDVD256",
+ argLen: 3,
+ resultInArg0: true,
+ asm: x86.AVPSHRDVD,
reg: regInfo{
inputs: []inputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
{
- name: "VPSUBSBMasked128",
- argLen: 3,
- asm: x86.AVPSUBSB,
+ name: "VPSHRDVD512",
+ argLen: 3,
+ resultInArg0: true,
+ asm: x86.AVPSHRDVD,
reg: regInfo{
inputs: []inputInfo{
- {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
{
- name: "VPSIGNB128",
- argLen: 2,
- asm: x86.AVPSIGNB,
+ name: "VPSHRDVDMasked128",
+ argLen: 4,
+ resultInArg0: true,
+ asm: x86.AVPSHRDVD,
reg: regInfo{
inputs: []inputInfo{
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
{
- name: "VPSUBB128",
- argLen: 2,
- asm: x86.AVPSUBB,
+ name: "VPSHRDVDMasked256",
+ argLen: 4,
+ resultInArg0: true,
+ asm: x86.AVPSHRDVD,
reg: regInfo{
inputs: []inputInfo{
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
{
- name: "VPSUBBMasked128",
- argLen: 3,
- asm: x86.AVPSUBB,
+ name: "VPSHRDVDMasked512",
+ argLen: 4,
+ resultInArg0: true,
+ asm: x86.AVPSHRDVD,
reg: regInfo{
inputs: []inputInfo{
- {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+ {3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
{
- name: "VPXOR128",
- argLen: 2,
- commutative: true,
- asm: x86.AVPXOR,
+ name: "VPSHRDVQ128",
+ argLen: 3,
+ resultInArg0: true,
+ asm: x86.AVPSHRDVQ,
reg: regInfo{
inputs: []inputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
{
- name: "VPABSB256",
- argLen: 1,
- asm: x86.AVPABSB,
+ name: "VPSHRDVQ256",
+ argLen: 3,
+ resultInArg0: true,
+ asm: x86.AVPSHRDVQ,
reg: regInfo{
inputs: []inputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
{
- name: "VPABSBMasked256",
- argLen: 2,
- asm: x86.AVPABSB,
+ name: "VPSHRDVQ512",
+ argLen: 3,
+ resultInArg0: true,
+ asm: x86.AVPSHRDVQ,
reg: regInfo{
inputs: []inputInfo{
- {1, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
- },
- {
- name: "VPADDB256",
- argLen: 2,
- commutative: true,
- asm: x86.AVPADDB,
+ },
+ {
+ name: "VPSHRDVQMasked128",
+ argLen: 4,
+ resultInArg0: true,
+ asm: x86.AVPSHRDVQ,
reg: regInfo{
inputs: []inputInfo{
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
{
- name: "VPADDBMasked256",
- argLen: 3,
- commutative: true,
- asm: x86.AVPADDB,
+ name: "VPSHRDVQMasked256",
+ argLen: 4,
+ resultInArg0: true,
+ asm: x86.AVPSHRDVQ,
reg: regInfo{
inputs: []inputInfo{
- {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+ {3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
{
- name: "VPAND256",
- argLen: 2,
- commutative: true,
- asm: x86.AVPAND,
+ name: "VPSHRDVQMasked512",
+ argLen: 4,
+ resultInArg0: true,
+ asm: x86.AVPSHRDVQ,
reg: regInfo{
inputs: []inputInfo{
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
{
- name: "VPANDN256",
- argLen: 2,
- asm: x86.AVPANDN,
+ name: "VPSHRDVW128",
+ argLen: 3,
+ resultInArg0: true,
+ asm: x86.AVPSHRDVW,
reg: regInfo{
inputs: []inputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
{
- name: "VPCOMPRESSBMasked256",
- argLen: 2,
- asm: x86.AVPCOMPRESSB,
+ name: "VPSHRDVW256",
+ argLen: 3,
+ resultInArg0: true,
+ asm: x86.AVPSHRDVW,
reg: regInfo{
inputs: []inputInfo{
- {1, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
{
- name: "VPCMPEQB256",
- argLen: 2,
- commutative: true,
- asm: x86.AVPCMPEQB,
+ name: "VPSHRDVW512",
+ argLen: 3,
+ resultInArg0: true,
+ asm: x86.AVPSHRDVW,
reg: regInfo{
inputs: []inputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
{
- name: "VPCMPGTB256",
- argLen: 2,
- asm: x86.AVPCMPGTB,
+ name: "VPSHRDVWMasked128",
+ argLen: 4,
+ resultInArg0: true,
+ asm: x86.AVPSHRDVW,
reg: regInfo{
inputs: []inputInfo{
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
{
- name: "VPMAXSB256",
- argLen: 2,
- commutative: true,
- asm: x86.AVPMAXSB,
+ name: "VPSHRDVWMasked256",
+ argLen: 4,
+ resultInArg0: true,
+ asm: x86.AVPSHRDVW,
reg: regInfo{
inputs: []inputInfo{
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
{
- name: "VPMAXSBMasked256",
- argLen: 3,
- commutative: true,
- asm: x86.AVPMAXSB,
+ name: "VPSHRDVWMasked512",
+ argLen: 4,
+ resultInArg0: true,
+ asm: x86.AVPSHRDVW,
reg: regInfo{
inputs: []inputInfo{
- {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+ {3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
{
- name: "VPMINSB256",
- argLen: 2,
- commutative: true,
- asm: x86.AVPMINSB,
+ name: "VPSIGNB128",
+ argLen: 2,
+ asm: x86.AVPSIGNB,
reg: regInfo{
inputs: []inputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
{
- name: "VPMINSBMasked256",
- argLen: 3,
- commutative: true,
- asm: x86.AVPMINSB,
+ name: "VPSIGNB256",
+ argLen: 2,
+ asm: x86.AVPSIGNB,
reg: regInfo{
inputs: []inputInfo{
- {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
{
- name: "VPOR256",
- argLen: 2,
- commutative: true,
- asm: x86.AVPOR,
+ name: "VPSIGND128",
+ argLen: 2,
+ asm: x86.AVPSIGND,
reg: regInfo{
inputs: []inputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
{
- name: "VPOPCNTB256",
- argLen: 1,
- asm: x86.AVPOPCNTB,
+ name: "VPSIGND256",
+ argLen: 2,
+ asm: x86.AVPSIGND,
reg: regInfo{
inputs: []inputInfo{
- {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
- {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
},
{
- name: "VPOPCNTBMasked256",
+ name: "VPSIGNW128",
argLen: 2,
- asm: x86.AVPOPCNTB,
+ asm: x86.AVPSIGNW,
reg: regInfo{
inputs: []inputInfo{
- {1, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
{
- name: "VPADDSB256",
- argLen: 2,
- commutative: true,
- asm: x86.AVPADDSB,
+ name: "VPSIGNW256",
+ argLen: 2,
+ asm: x86.AVPSIGNW,
reg: regInfo{
inputs: []inputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
{
- name: "VPADDSBMasked256",
- argLen: 3,
- commutative: true,
- asm: x86.AVPADDSB,
+ name: "VPSLLD128",
+ argLen: 2,
+ asm: x86.AVPSLLD,
reg: regInfo{
inputs: []inputInfo{
- {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
{
- name: "VPSUBSB256",
+ name: "VPSLLD256",
argLen: 2,
- asm: x86.AVPSUBSB,
+ asm: x86.AVPSLLD,
reg: regInfo{
inputs: []inputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
{
- name: "VPSUBSBMasked256",
- argLen: 3,
- asm: x86.AVPSUBSB,
+ name: "VPSLLD512",
+ argLen: 2,
+ asm: x86.AVPSLLD,
reg: regInfo{
inputs: []inputInfo{
- {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
},
outputs: []outputInfo{
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
},
},
},
{
- name: "VPSIGNB256",
- argLen: 2,
- asm: x86.AVPSIGNB,
+ name: "VPSLLDMasked128",
+ argLen: 3,
+ asm: x86.AVPSLLD,
reg: regInfo{
inputs: []inputInfo{
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+ {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
},
outputs: []outputInfo{
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
},
},
},
{
- name: "VPSUBB256",
- argLen: 2,
- asm: x86.AVPSUBB,
+ name: "VPSLLDMasked256",
+ argLen: 3,
+ asm: x86.AVPSLLD,
reg: regInfo{
inputs: []inputInfo{
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+ {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
},
outputs: []outputInfo{
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
},
},
},
{
- name: "VPSUBBMasked256",
+ name: "VPSLLDMasked512",
argLen: 3,
- asm: x86.AVPSUBB,
+ asm: x86.AVPSLLD,
reg: regInfo{
inputs: []inputInfo{
{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
},
outputs: []outputInfo{
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
},
},
},
{
- name: "VPXOR256",
- argLen: 2,
- commutative: true,
- asm: x86.AVPXOR,
+ name: "VPSLLQ128",
+ argLen: 2,
+ asm: x86.AVPSLLQ,
reg: regInfo{
inputs: []inputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
{
- name: "VPABSB512",
- argLen: 1,
- asm: x86.AVPABSB,
+ name: "VPSLLQ256",
+ argLen: 2,
+ asm: x86.AVPSLLQ,
reg: regInfo{
inputs: []inputInfo{
- {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
- {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
},
{
- name: "VPABSBMasked512",
+ name: "VPSLLQ512",
argLen: 2,
- asm: x86.AVPABSB,
+ asm: x86.AVPSLLQ,
reg: regInfo{
inputs: []inputInfo{
- {1, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
},
outputs: []outputInfo{
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
},
},
},
{
- name: "VPADDB512",
- argLen: 2,
- commutative: true,
- asm: x86.AVPADDB,
+ name: "VPSLLQMasked128",
+ argLen: 3,
+ asm: x86.AVPSLLQ,
reg: regInfo{
inputs: []inputInfo{
- {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
- {1, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+ {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
},
outputs: []outputInfo{
{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
},
},
{
- name: "VPADDBMasked512",
- argLen: 3,
- commutative: true,
- asm: x86.AVPADDB,
+ name: "VPSLLQMasked256",
+ argLen: 3,
+ asm: x86.AVPSLLQ,
reg: regInfo{
inputs: []inputInfo{
{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
},
outputs: []outputInfo{
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
},
},
},
{
- name: "VPCOMPRESSBMasked512",
- argLen: 2,
- asm: x86.AVPCOMPRESSB,
+ name: "VPSLLQMasked512",
+ argLen: 3,
+ asm: x86.AVPSLLQ,
reg: regInfo{
inputs: []inputInfo{
- {1, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+ {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
},
outputs: []outputInfo{
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
},
},
},
{
- name: "VPCMPEQB512",
- argLen: 2,
- commutative: true,
- asm: x86.AVPCMPEQB,
+ name: "VPSLLVD128",
+ argLen: 2,
+ asm: x86.AVPSLLVD,
reg: regInfo{
inputs: []inputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
- {0, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
},
{
- name: "VPCMPGTB512",
+ name: "VPSLLVD256",
argLen: 2,
- asm: x86.AVPCMPGTB,
+ asm: x86.AVPSLLVD,
reg: regInfo{
inputs: []inputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
- {0, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
},
{
- name: "VPMAXSB512",
- argLen: 2,
- commutative: true,
- asm: x86.AVPMAXSB,
+ name: "VPSLLVD512",
+ argLen: 2,
+ asm: x86.AVPSLLVD,
reg: regInfo{
inputs: []inputInfo{
{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
},
},
{
- name: "VPMAXSBMasked512",
- argLen: 3,
- commutative: true,
- asm: x86.AVPMAXSB,
+ name: "VPSLLVDMasked128",
+ argLen: 3,
+ asm: x86.AVPSLLVD,
reg: regInfo{
inputs: []inputInfo{
{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
},
},
{
- name: "VPMINSB512",
- argLen: 2,
- commutative: true,
- asm: x86.AVPMINSB,
+ name: "VPSLLVDMasked256",
+ argLen: 3,
+ asm: x86.AVPSLLVD,
reg: regInfo{
inputs: []inputInfo{
- {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
- {1, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
- {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
},
{
- name: "VPMINSBMasked512",
- argLen: 3,
- commutative: true,
- asm: x86.AVPMINSB,
+ name: "VPSLLVDMasked512",
+ argLen: 3,
+ asm: x86.AVPSLLVD,
reg: regInfo{
inputs: []inputInfo{
{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
},
},
{
- name: "VPOPCNTB512",
- argLen: 1,
- asm: x86.AVPOPCNTB,
+ name: "VPSLLVQ128",
+ argLen: 2,
+ asm: x86.AVPSLLVQ,
reg: regInfo{
inputs: []inputInfo{
- {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
- {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
},
{
- name: "VPOPCNTBMasked512",
+ name: "VPSLLVQ256",
argLen: 2,
- asm: x86.AVPOPCNTB,
+ asm: x86.AVPSLLVQ,
reg: regInfo{
inputs: []inputInfo{
- {1, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
{
- name: "VPADDSB512",
- argLen: 2,
- commutative: true,
- asm: x86.AVPADDSB,
+ name: "VPSLLVQ512",
+ argLen: 2,
+ asm: x86.AVPSLLVQ,
reg: regInfo{
inputs: []inputInfo{
{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
},
},
{
- name: "VPADDSBMasked512",
- argLen: 3,
- commutative: true,
- asm: x86.AVPADDSB,
+ name: "VPSLLVQMasked128",
+ argLen: 3,
+ asm: x86.AVPSLLVQ,
reg: regInfo{
inputs: []inputInfo{
{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
},
},
{
- name: "VPSUBSB512",
- argLen: 2,
- asm: x86.AVPSUBSB,
+ name: "VPSLLVQMasked256",
+ argLen: 3,
+ asm: x86.AVPSLLVQ,
reg: regInfo{
inputs: []inputInfo{
- {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
- {1, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
- {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
},
{
- name: "VPSUBSBMasked512",
+ name: "VPSLLVQMasked512",
argLen: 3,
- asm: x86.AVPSUBSB,
+ asm: x86.AVPSLLVQ,
reg: regInfo{
inputs: []inputInfo{
{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
},
},
{
- name: "VPSUBB512",
+ name: "VPSLLVW128",
argLen: 2,
- asm: x86.AVPSUBB,
+ asm: x86.AVPSLLVW,
reg: regInfo{
inputs: []inputInfo{
{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
},
},
{
- name: "VPSUBBMasked512",
- argLen: 3,
- asm: x86.AVPSUBB,
+ name: "VPSLLVW256",
+ argLen: 2,
+ asm: x86.AVPSLLVW,
reg: regInfo{
inputs: []inputInfo{
- {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ {1, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
},
outputs: []outputInfo{
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
},
},
},
{
- name: "VPAVGW256",
- argLen: 2,
- commutative: true,
- asm: x86.AVPAVGW,
+ name: "VPSLLVW512",
+ argLen: 2,
+ asm: x86.AVPSLLVW,
reg: regInfo{
inputs: []inputInfo{
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ {1, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
},
outputs: []outputInfo{
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
},
},
},
{
- name: "VPAVGWMasked256",
- argLen: 3,
- commutative: true,
- asm: x86.AVPAVGW,
+ name: "VPSLLVWMasked128",
+ argLen: 3,
+ asm: x86.AVPSLLVW,
reg: regInfo{
inputs: []inputInfo{
{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
},
},
{
- name: "VPMAXUW256",
- argLen: 2,
- commutative: true,
- asm: x86.AVPMAXUW,
+ name: "VPSLLVWMasked256",
+ argLen: 3,
+ asm: x86.AVPSLLVW,
reg: regInfo{
inputs: []inputInfo{
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
{
- name: "VPMAXUWMasked256",
- argLen: 3,
- commutative: true,
- asm: x86.AVPMAXUW,
+ name: "VPSLLVWMasked512",
+ argLen: 3,
+ asm: x86.AVPSLLVW,
reg: regInfo{
inputs: []inputInfo{
{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
},
},
{
- name: "VPMINUW256",
- argLen: 2,
- commutative: true,
- asm: x86.AVPMINUW,
+ name: "VPSLLW128",
+ argLen: 2,
+ asm: x86.AVPSLLW,
reg: regInfo{
inputs: []inputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
{
- name: "VPMINUWMasked256",
- argLen: 3,
- commutative: true,
- asm: x86.AVPMINUW,
+ name: "VPSLLW256",
+ argLen: 2,
+ asm: x86.AVPSLLW,
reg: regInfo{
inputs: []inputInfo{
- {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
{
- name: "VPMULHUW256",
- argLen: 2,
- commutative: true,
- asm: x86.AVPMULHUW,
+ name: "VPSLLW512",
+ argLen: 2,
+ asm: x86.AVPSLLW,
reg: regInfo{
inputs: []inputInfo{
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
},
outputs: []outputInfo{
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
},
},
},
{
- name: "VPMULHUWMasked256",
- argLen: 3,
- commutative: true,
- asm: x86.AVPMULHUW,
+ name: "VPSLLWMasked128",
+ argLen: 3,
+ asm: x86.AVPSLLW,
reg: regInfo{
inputs: []inputInfo{
{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
},
outputs: []outputInfo{
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
},
},
},
{
- name: "VPERMW256",
- argLen: 2,
- asm: x86.AVPERMW,
+ name: "VPSLLWMasked256",
+ argLen: 3,
+ asm: x86.AVPSLLW,
reg: regInfo{
inputs: []inputInfo{
- {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
- {1, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+ {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
},
outputs: []outputInfo{
{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
},
},
{
- name: "VPERMI2W256",
- argLen: 3,
- resultInArg0: true,
- asm: x86.AVPERMI2W,
+ name: "VPSLLWMasked512",
+ argLen: 3,
+ asm: x86.AVPSLLW,
reg: regInfo{
inputs: []inputInfo{
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+ {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
},
outputs: []outputInfo{
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
},
},
},
{
- name: "VPERMI2WMasked256",
- argLen: 4,
- resultInArg0: true,
- asm: x86.AVPERMI2W,
+ name: "VPSRAD128",
+ argLen: 2,
+ asm: x86.AVPSRAD,
reg: regInfo{
inputs: []inputInfo{
- {3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
{
- name: "VPERMWMasked256",
- argLen: 3,
- asm: x86.AVPERMW,
+ name: "VPSRAD256",
+ argLen: 2,
+ asm: x86.AVPSRAD,
reg: regInfo{
inputs: []inputInfo{
- {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
{
- name: "VPSRLW256",
+ name: "VPSRAD512",
argLen: 2,
- asm: x86.AVPSRLW,
+ asm: x86.AVPSRAD,
reg: regInfo{
inputs: []inputInfo{
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
},
outputs: []outputInfo{
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
},
},
},
{
- name: "VPSRLWMasked256",
+ name: "VPSRADMasked128",
argLen: 3,
- asm: x86.AVPSRLW,
+ asm: x86.AVPSRAD,
reg: regInfo{
inputs: []inputInfo{
{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
},
},
{
- name: "VPSRLVW256",
- argLen: 2,
- asm: x86.AVPSRLVW,
+ name: "VPSRADMasked256",
+ argLen: 3,
+ asm: x86.AVPSRAD,
reg: regInfo{
inputs: []inputInfo{
- {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
- {1, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+ {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
},
outputs: []outputInfo{
{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
},
},
{
- name: "VPSRLVWMasked256",
+ name: "VPSRADMasked512",
argLen: 3,
- asm: x86.AVPSRLVW,
+ asm: x86.AVPSRAD,
reg: regInfo{
inputs: []inputInfo{
{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
},
outputs: []outputInfo{
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
},
},
},
{
- name: "VPAVGW512",
- argLen: 2,
- commutative: true,
- asm: x86.AVPAVGW,
+ name: "VPSRAQ128",
+ argLen: 2,
+ asm: x86.AVPSRAQ,
reg: regInfo{
inputs: []inputInfo{
+ {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
- {1, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
},
outputs: []outputInfo{
{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
},
},
{
- name: "VPAVGWMasked512",
- argLen: 3,
- commutative: true,
- asm: x86.AVPAVGW,
+ name: "VPSRAQ256",
+ argLen: 2,
+ asm: x86.AVPSRAQ,
reg: regInfo{
inputs: []inputInfo{
- {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
},
outputs: []outputInfo{
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
},
},
},
{
- name: "VPMAXUW512",
- argLen: 2,
- commutative: true,
- asm: x86.AVPMAXUW,
+ name: "VPSRAQ512",
+ argLen: 2,
+ asm: x86.AVPSRAQ,
reg: regInfo{
inputs: []inputInfo{
+ {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
- {1, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
},
outputs: []outputInfo{
{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
},
},
{
- name: "VPMAXUWMasked512",
- argLen: 3,
- commutative: true,
- asm: x86.AVPMAXUW,
+ name: "VPSRAQMasked128",
+ argLen: 3,
+ asm: x86.AVPSRAQ,
reg: regInfo{
inputs: []inputInfo{
{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
},
outputs: []outputInfo{
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
},
},
},
{
- name: "VPMINUW512",
- argLen: 2,
- commutative: true,
- asm: x86.AVPMINUW,
+ name: "VPSRAQMasked256",
+ argLen: 3,
+ asm: x86.AVPSRAQ,
reg: regInfo{
inputs: []inputInfo{
- {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
- {1, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+ {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
},
outputs: []outputInfo{
{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
},
},
{
- name: "VPMINUWMasked512",
- argLen: 3,
- commutative: true,
- asm: x86.AVPMINUW,
+ name: "VPSRAQMasked512",
+ argLen: 3,
+ asm: x86.AVPSRAQ,
reg: regInfo{
inputs: []inputInfo{
{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
},
outputs: []outputInfo{
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
},
},
},
{
- name: "VPMULHUW512",
- argLen: 2,
- commutative: true,
- asm: x86.AVPMULHUW,
+ name: "VPSRAVD128",
+ argLen: 2,
+ asm: x86.AVPSRAVD,
reg: regInfo{
inputs: []inputInfo{
- {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
- {1, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
- {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
},
{
- name: "VPMULHUWMasked512",
- argLen: 3,
- commutative: true,
- asm: x86.AVPMULHUW,
+ name: "VPSRAVD256",
+ argLen: 2,
+ asm: x86.AVPSRAVD,
reg: regInfo{
inputs: []inputInfo{
- {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
{
- name: "VPERMW512",
+ name: "VPSRAVD512",
argLen: 2,
- asm: x86.AVPERMW,
+ asm: x86.AVPSRAVD,
reg: regInfo{
inputs: []inputInfo{
{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
},
},
{
- name: "VPERMI2W512",
- argLen: 3,
- resultInArg0: true,
- asm: x86.AVPERMI2W,
+ name: "VPSRAVDMasked128",
+ argLen: 3,
+ asm: x86.AVPSRAVD,
reg: regInfo{
inputs: []inputInfo{
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
{
- name: "VPERMI2WMasked512",
- argLen: 4,
- resultInArg0: true,
- asm: x86.AVPERMI2W,
+ name: "VPSRAVDMasked256",
+ argLen: 3,
+ asm: x86.AVPSRAVD,
reg: regInfo{
inputs: []inputInfo{
- {3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+ {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
{
- name: "VPERMWMasked512",
+ name: "VPSRAVDMasked512",
argLen: 3,
- asm: x86.AVPERMW,
+ asm: x86.AVPSRAVD,
reg: regInfo{
inputs: []inputInfo{
{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
},
},
{
- name: "VPSRLW512",
+ name: "VPSRAVQ128",
argLen: 2,
- asm: x86.AVPSRLW,
+ asm: x86.AVPSRAVQ,
reg: regInfo{
inputs: []inputInfo{
- {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ {1, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
},
outputs: []outputInfo{
{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
},
},
{
- name: "VPSRLWMasked512",
- argLen: 3,
- asm: x86.AVPSRLW,
+ name: "VPSRAVQ256",
+ argLen: 2,
+ asm: x86.AVPSRAVQ,
reg: regInfo{
inputs: []inputInfo{
- {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
- {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ {1, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
},
outputs: []outputInfo{
{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
},
},
{
- name: "VPSRLVW512",
+ name: "VPSRAVQ512",
argLen: 2,
- asm: x86.AVPSRLVW,
+ asm: x86.AVPSRAVQ,
reg: regInfo{
inputs: []inputInfo{
{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
},
},
{
- name: "VPSRLVWMasked512",
+ name: "VPSRAVQMasked128",
argLen: 3,
- asm: x86.AVPSRLVW,
+ asm: x86.AVPSRAVQ,
reg: regInfo{
inputs: []inputInfo{
{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
},
},
{
- name: "VPAVGW128",
- argLen: 2,
- commutative: true,
- asm: x86.AVPAVGW,
+ name: "VPSRAVQMasked256",
+ argLen: 3,
+ asm: x86.AVPSRAVQ,
reg: regInfo{
inputs: []inputInfo{
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
{
- name: "VPAVGWMasked128",
- argLen: 3,
- commutative: true,
- asm: x86.AVPAVGW,
+ name: "VPSRAVQMasked512",
+ argLen: 3,
+ asm: x86.AVPSRAVQ,
reg: regInfo{
inputs: []inputInfo{
{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
},
},
{
- name: "VPMAXUW128",
- argLen: 2,
- commutative: true,
- asm: x86.AVPMAXUW,
+ name: "VPSRAVW128",
+ argLen: 2,
+ asm: x86.AVPSRAVW,
reg: regInfo{
inputs: []inputInfo{
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ {1, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
},
outputs: []outputInfo{
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
},
},
},
{
- name: "VPMAXUWMasked128",
- argLen: 3,
- commutative: true,
- asm: x86.AVPMAXUW,
+ name: "VPSRAVW256",
+ argLen: 2,
+ asm: x86.AVPSRAVW,
reg: regInfo{
inputs: []inputInfo{
- {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ {1, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
},
outputs: []outputInfo{
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
},
},
},
{
- name: "VPMINUW128",
- argLen: 2,
- commutative: true,
- asm: x86.AVPMINUW,
+ name: "VPSRAVW512",
+ argLen: 2,
+ asm: x86.AVPSRAVW,
reg: regInfo{
inputs: []inputInfo{
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ {1, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
},
outputs: []outputInfo{
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
},
},
},
{
- name: "VPMINUWMasked128",
- argLen: 3,
- commutative: true,
- asm: x86.AVPMINUW,
+ name: "VPSRAVWMasked128",
+ argLen: 3,
+ asm: x86.AVPSRAVW,
reg: regInfo{
inputs: []inputInfo{
{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
},
},
{
- name: "VPMULHUW128",
- argLen: 2,
- commutative: true,
- asm: x86.AVPMULHUW,
+ name: "VPSRAVWMasked256",
+ argLen: 3,
+ asm: x86.AVPSRAVW,
reg: regInfo{
inputs: []inputInfo{
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
{
- name: "VPMULHUWMasked128",
- argLen: 3,
- commutative: true,
- asm: x86.AVPMULHUW,
+ name: "VPSRAVWMasked512",
+ argLen: 3,
+ asm: x86.AVPSRAVW,
reg: regInfo{
inputs: []inputInfo{
{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
},
},
{
- name: "VPERMW128",
+ name: "VPSRAW128",
argLen: 2,
- asm: x86.AVPERMW,
- reg: regInfo{
- inputs: []inputInfo{
- {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
- {1, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
- },
- outputs: []outputInfo{
- {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
- },
- },
- },
- {
- name: "VPERMI2W128",
- argLen: 3,
- resultInArg0: true,
- asm: x86.AVPERMI2W,
+ asm: x86.AVPSRAW,
reg: regInfo{
inputs: []inputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
{
- name: "VPERMI2WMasked128",
- argLen: 4,
- resultInArg0: true,
- asm: x86.AVPERMI2W,
+ name: "VPSRAW256",
+ argLen: 2,
+ asm: x86.AVPSRAW,
reg: regInfo{
inputs: []inputInfo{
- {3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- },
- outputs: []outputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- },
- },
- },
- {
- name: "VPERMWMasked128",
- argLen: 3,
- asm: x86.AVPERMW,
- reg: regInfo{
- inputs: []inputInfo{
- {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
{
- name: "VPSRLW128",
+ name: "VPSRAW512",
argLen: 2,
- asm: x86.AVPSRLW,
+ asm: x86.AVPSRAW,
reg: regInfo{
inputs: []inputInfo{
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
},
outputs: []outputInfo{
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
},
},
},
{
- name: "VPSRLWMasked128",
+ name: "VPSRAWMasked128",
argLen: 3,
- asm: x86.AVPSRLW,
+ asm: x86.AVPSRAW,
reg: regInfo{
inputs: []inputInfo{
{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
},
},
{
- name: "VPSRLVW128",
- argLen: 2,
- asm: x86.AVPSRLVW,
+ name: "VPSRAWMasked256",
+ argLen: 3,
+ asm: x86.AVPSRAW,
reg: regInfo{
inputs: []inputInfo{
- {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
- {1, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+ {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
},
outputs: []outputInfo{
{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
},
},
{
- name: "VPSRLVWMasked128",
+ name: "VPSRAWMasked512",
argLen: 3,
- asm: x86.AVPSRLVW,
+ asm: x86.AVPSRAW,
reg: regInfo{
inputs: []inputInfo{
{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
},
outputs: []outputInfo{
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
},
},
},
{
- name: "VPMAXUD512",
- argLen: 2,
- commutative: true,
- asm: x86.AVPMAXUD,
+ name: "VPSRLD128",
+ argLen: 2,
+ asm: x86.AVPSRLD,
reg: regInfo{
inputs: []inputInfo{
- {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
- {1, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
- {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
},
{
- name: "VPMAXUDMasked512",
- argLen: 3,
- commutative: true,
- asm: x86.AVPMAXUD,
+ name: "VPSRLD256",
+ argLen: 2,
+ asm: x86.AVPSRLD,
reg: regInfo{
inputs: []inputInfo{
- {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
{
- name: "VPMINUD512",
- argLen: 2,
- commutative: true,
- asm: x86.AVPMINUD,
+ name: "VPSRLD512",
+ argLen: 2,
+ asm: x86.AVPSRLD,
reg: regInfo{
inputs: []inputInfo{
+ {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
- {1, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
},
outputs: []outputInfo{
{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
},
},
{
- name: "VPMINUDMasked512",
- argLen: 3,
- commutative: true,
- asm: x86.AVPMINUD,
+ name: "VPSRLDMasked128",
+ argLen: 3,
+ asm: x86.AVPSRLD,
reg: regInfo{
inputs: []inputInfo{
{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
},
outputs: []outputInfo{
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
},
},
},
{
- name: "VPERMD512",
- argLen: 2,
- asm: x86.AVPERMD,
+ name: "VPSRLDMasked256",
+ argLen: 3,
+ asm: x86.AVPSRLD,
reg: regInfo{
inputs: []inputInfo{
- {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
- {1, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+ {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
},
outputs: []outputInfo{
{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
},
},
{
- name: "VPERMPS512",
- argLen: 2,
- asm: x86.AVPERMPS,
+ name: "VPSRLDMasked512",
+ argLen: 3,
+ asm: x86.AVPSRLD,
reg: regInfo{
inputs: []inputInfo{
- {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
- {1, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+ {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
},
outputs: []outputInfo{
{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
},
},
{
- name: "VPERMI2PS512",
- argLen: 3,
- resultInArg0: true,
- asm: x86.AVPERMI2PS,
+ name: "VPSRLQ128",
+ argLen: 2,
+ asm: x86.AVPSRLQ,
reg: regInfo{
inputs: []inputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
{
- name: "VPERMI2D512",
- argLen: 3,
- resultInArg0: true,
- asm: x86.AVPERMI2D,
+ name: "VPSRLQ256",
+ argLen: 2,
+ asm: x86.AVPSRLQ,
reg: regInfo{
inputs: []inputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
{
- name: "VPERMI2PSMasked512",
- argLen: 4,
- resultInArg0: true,
- asm: x86.AVPERMI2PS,
+ name: "VPSRLQ512",
+ argLen: 2,
+ asm: x86.AVPSRLQ,
reg: regInfo{
inputs: []inputInfo{
- {3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
},
outputs: []outputInfo{
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
},
},
},
{
- name: "VPERMI2DMasked512",
- argLen: 4,
- resultInArg0: true,
- asm: x86.AVPERMI2D,
+ name: "VPSRLQMasked128",
+ argLen: 3,
+ asm: x86.AVPSRLQ,
reg: regInfo{
inputs: []inputInfo{
- {3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
},
outputs: []outputInfo{
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
},
},
},
{
- name: "VPERMPSMasked512",
+ name: "VPSRLQMasked256",
argLen: 3,
- asm: x86.AVPERMPS,
+ asm: x86.AVPSRLQ,
reg: regInfo{
inputs: []inputInfo{
{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
},
outputs: []outputInfo{
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
},
},
},
{
- name: "VPERMDMasked512",
+ name: "VPSRLQMasked512",
argLen: 3,
- asm: x86.AVPERMD,
+ asm: x86.AVPSRLQ,
reg: regInfo{
inputs: []inputInfo{
{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
},
outputs: []outputInfo{
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
},
},
},
{
- name: "VPSRLD512",
+ name: "VPSRLVD128",
argLen: 2,
- asm: x86.AVPSRLD,
+ asm: x86.AVPSRLVD,
reg: regInfo{
inputs: []inputInfo{
- {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
- {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
},
{
- name: "VPSRLDMasked512",
- argLen: 3,
- asm: x86.AVPSRLD,
+ name: "VPSRLVD256",
+ argLen: 2,
+ asm: x86.AVPSRLVD,
reg: regInfo{
- inputs: []inputInfo{
- {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
- {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ inputs: []inputInfo{
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
- {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
},
},
},
{
- name: "VPSRLVDMasked512",
+ name: "VPSRLVDMasked128",
argLen: 3,
asm: x86.AVPSRLVD,
reg: regInfo{
},
},
{
- name: "VPMAXUD128",
- argLen: 2,
- commutative: true,
- asm: x86.AVPMAXUD,
+ name: "VPSRLVDMasked256",
+ argLen: 3,
+ asm: x86.AVPSRLVD,
reg: regInfo{
inputs: []inputInfo{
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
{
- name: "VPMAXUDMasked128",
- argLen: 3,
- commutative: true,
- asm: x86.AVPMAXUD,
+ name: "VPSRLVDMasked512",
+ argLen: 3,
+ asm: x86.AVPSRLVD,
reg: regInfo{
inputs: []inputInfo{
{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
},
},
{
- name: "VPMINUD128",
- argLen: 2,
- commutative: true,
- asm: x86.AVPMINUD,
+ name: "VPSRLVQ128",
+ argLen: 2,
+ asm: x86.AVPSRLVQ,
reg: regInfo{
inputs: []inputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
{
- name: "VPMINUDMasked128",
- argLen: 3,
- commutative: true,
- asm: x86.AVPMINUD,
- reg: regInfo{
- inputs: []inputInfo{
- {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- },
- outputs: []outputInfo{
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- },
- },
- },
- {
- name: "VPMULUDQ128",
- argLen: 2,
- commutative: true,
- asm: x86.AVPMULUDQ,
+ name: "VPSRLVQ256",
+ argLen: 2,
+ asm: x86.AVPSRLVQ,
reg: regInfo{
inputs: []inputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
{
- name: "VPERMI2PS128",
- argLen: 3,
- resultInArg0: true,
- asm: x86.AVPERMI2PS,
+ name: "VPSRLVQ512",
+ argLen: 2,
+ asm: x86.AVPSRLVQ,
reg: regInfo{
inputs: []inputInfo{
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ {1, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
},
outputs: []outputInfo{
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
},
},
},
{
- name: "VPERMI2D128",
- argLen: 3,
- resultInArg0: true,
- asm: x86.AVPERMI2D,
+ name: "VPSRLVQMasked128",
+ argLen: 3,
+ asm: x86.AVPSRLVQ,
reg: regInfo{
inputs: []inputInfo{
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
{
- name: "VPERMI2DMasked128",
- argLen: 4,
- resultInArg0: true,
- asm: x86.AVPERMI2D,
+ name: "VPSRLVQMasked256",
+ argLen: 3,
+ asm: x86.AVPSRLVQ,
reg: regInfo{
inputs: []inputInfo{
- {3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+ {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
{
- name: "VPERMI2PSMasked128",
- argLen: 4,
- resultInArg0: true,
- asm: x86.AVPERMI2PS,
+ name: "VPSRLVQMasked512",
+ argLen: 3,
+ asm: x86.AVPSRLVQ,
reg: regInfo{
inputs: []inputInfo{
- {3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+ {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
{
- name: "VPSRLD128",
+ name: "VPSRLVW128",
argLen: 2,
- asm: x86.AVPSRLD,
+ asm: x86.AVPSRLVW,
reg: regInfo{
inputs: []inputInfo{
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ {1, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
},
outputs: []outputInfo{
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
},
},
},
{
- name: "VPSRLDMasked128",
- argLen: 3,
- asm: x86.AVPSRLD,
+ name: "VPSRLVW256",
+ argLen: 2,
+ asm: x86.AVPSRLVW,
reg: regInfo{
inputs: []inputInfo{
- {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
- {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ {1, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
},
outputs: []outputInfo{
{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
},
},
{
- name: "VPSRLVD128",
+ name: "VPSRLVW512",
argLen: 2,
- asm: x86.AVPSRLVD,
+ asm: x86.AVPSRLVW,
reg: regInfo{
inputs: []inputInfo{
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ {1, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
},
outputs: []outputInfo{
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
},
},
},
{
- name: "VPSRLVDMasked128",
+ name: "VPSRLVWMasked128",
argLen: 3,
- asm: x86.AVPSRLVD,
+ asm: x86.AVPSRLVW,
reg: regInfo{
inputs: []inputInfo{
{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
},
},
{
- name: "VPMAXUD256",
- argLen: 2,
- commutative: true,
- asm: x86.AVPMAXUD,
+ name: "VPSRLVWMasked256",
+ argLen: 3,
+ asm: x86.AVPSRLVW,
reg: regInfo{
inputs: []inputInfo{
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
{
- name: "VPMAXUDMasked256",
- argLen: 3,
- commutative: true,
- asm: x86.AVPMAXUD,
+ name: "VPSRLVWMasked512",
+ argLen: 3,
+ asm: x86.AVPSRLVW,
reg: regInfo{
inputs: []inputInfo{
{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
},
},
{
- name: "VPMINUD256",
- argLen: 2,
- commutative: true,
- asm: x86.AVPMINUD,
+ name: "VPSRLW128",
+ argLen: 2,
+ asm: x86.AVPSRLW,
reg: regInfo{
inputs: []inputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
{
- name: "VPMINUDMasked256",
- argLen: 3,
- commutative: true,
- asm: x86.AVPMINUD,
+ name: "VPSRLW256",
+ argLen: 2,
+ asm: x86.AVPSRLW,
reg: regInfo{
inputs: []inputInfo{
- {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
{
- name: "VPMULUDQ256",
- argLen: 2,
- commutative: true,
- asm: x86.AVPMULUDQ,
+ name: "VPSRLW512",
+ argLen: 2,
+ asm: x86.AVPSRLW,
reg: regInfo{
inputs: []inputInfo{
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
},
outputs: []outputInfo{
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
},
},
},
{
- name: "VPERMD256",
- argLen: 2,
- asm: x86.AVPERMD,
+ name: "VPSRLWMasked128",
+ argLen: 3,
+ asm: x86.AVPSRLW,
reg: regInfo{
inputs: []inputInfo{
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+ {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
},
outputs: []outputInfo{
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
},
},
},
{
- name: "VPERMPS256",
- argLen: 2,
- asm: x86.AVPERMPS,
+ name: "VPSRLWMasked256",
+ argLen: 3,
+ asm: x86.AVPSRLW,
reg: regInfo{
inputs: []inputInfo{
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+ {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
},
outputs: []outputInfo{
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
},
},
},
{
- name: "VPERMI2PS256",
- argLen: 3,
- resultInArg0: true,
- asm: x86.AVPERMI2PS,
+ name: "VPSRLWMasked512",
+ argLen: 3,
+ asm: x86.AVPSRLW,
+ reg: regInfo{
+ inputs: []inputInfo{
+ {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+ {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ },
+ outputs: []outputInfo{
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ },
+ },
+ },
+ {
+ name: "VPSUBB128",
+ argLen: 2,
+ asm: x86.AVPSUBB,
reg: regInfo{
inputs: []inputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
{
- name: "VPERMI2D256",
- argLen: 3,
- resultInArg0: true,
- asm: x86.AVPERMI2D,
+ name: "VPSUBB256",
+ argLen: 2,
+ asm: x86.AVPSUBB,
reg: regInfo{
inputs: []inputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
{
- name: "VPERMI2PSMasked256",
- argLen: 4,
- resultInArg0: true,
- asm: x86.AVPERMI2PS,
+ name: "VPSUBB512",
+ argLen: 2,
+ asm: x86.AVPSUBB,
reg: regInfo{
inputs: []inputInfo{
- {3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ {1, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
},
outputs: []outputInfo{
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
},
},
},
{
- name: "VPERMI2DMasked256",
- argLen: 4,
- resultInArg0: true,
- asm: x86.AVPERMI2D,
+ name: "VPSUBBMasked128",
+ argLen: 3,
+ asm: x86.AVPSUBB,
reg: regInfo{
inputs: []inputInfo{
- {3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+ {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
{
- name: "VPERMPSMasked256",
+ name: "VPSUBBMasked256",
argLen: 3,
- asm: x86.AVPERMPS,
+ asm: x86.AVPSUBB,
reg: regInfo{
inputs: []inputInfo{
{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
},
},
{
- name: "VPERMDMasked256",
+ name: "VPSUBBMasked512",
argLen: 3,
- asm: x86.AVPERMD,
+ asm: x86.AVPSUBB,
reg: regInfo{
inputs: []inputInfo{
{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
},
},
{
- name: "VPSRLD256",
+ name: "VPSUBD128",
argLen: 2,
- asm: x86.AVPSRLD,
+ asm: x86.AVPSUBD,
reg: regInfo{
inputs: []inputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
{
- name: "VPSRLDMasked256",
- argLen: 3,
- asm: x86.AVPSRLD,
+ name: "VPSUBD256",
+ argLen: 2,
+ asm: x86.AVPSUBD,
reg: regInfo{
inputs: []inputInfo{
- {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
- {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
- {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
},
{
- name: "VPSRLVD256",
+ name: "VPSUBD512",
argLen: 2,
- asm: x86.AVPSRLVD,
+ asm: x86.AVPSUBD,
reg: regInfo{
inputs: []inputInfo{
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ {1, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
},
outputs: []outputInfo{
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
},
},
},
{
- name: "VPSRLVDMasked256",
+ name: "VPSUBDMasked128",
argLen: 3,
- asm: x86.AVPSRLVD,
+ asm: x86.AVPSUBD,
reg: regInfo{
inputs: []inputInfo{
{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
},
},
{
- name: "VPMAXUQ128",
- argLen: 2,
- commutative: true,
- asm: x86.AVPMAXUQ,
+ name: "VPSUBDMasked256",
+ argLen: 3,
+ asm: x86.AVPSUBD,
reg: regInfo{
inputs: []inputInfo{
- {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
- {1, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
- {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
},
{
- name: "VPMAXUQMasked128",
- argLen: 3,
- commutative: true,
- asm: x86.AVPMAXUQ,
+ name: "VPSUBDMasked512",
+ argLen: 3,
+ asm: x86.AVPSUBD,
reg: regInfo{
inputs: []inputInfo{
{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
},
},
{
- name: "VPMINUQ128",
- argLen: 2,
- commutative: true,
- asm: x86.AVPMINUQ,
+ name: "VPSUBQ128",
+ argLen: 2,
+ asm: x86.AVPSUBQ,
reg: regInfo{
inputs: []inputInfo{
- {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
- {1, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
- {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
},
{
- name: "VPMINUQMasked128",
- argLen: 3,
- commutative: true,
- asm: x86.AVPMINUQ,
+ name: "VPSUBQ256",
+ argLen: 2,
+ asm: x86.AVPSUBQ,
reg: regInfo{
inputs: []inputInfo{
- {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
{
- name: "VPMULUDQMasked128",
- argLen: 3,
- commutative: true,
- asm: x86.AVPMULUDQ,
+ name: "VPSUBQ512",
+ argLen: 2,
+ asm: x86.AVPSUBQ,
reg: regInfo{
inputs: []inputInfo{
- {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ {1, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
},
outputs: []outputInfo{
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
},
},
},
{
- name: "VPERMI2PD128",
- argLen: 3,
- resultInArg0: true,
- asm: x86.AVPERMI2PD,
+ name: "VPSUBQMasked128",
+ argLen: 3,
+ asm: x86.AVPSUBQ,
reg: regInfo{
inputs: []inputInfo{
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
{
- name: "VPERMI2Q128",
- argLen: 3,
- resultInArg0: true,
- asm: x86.AVPERMI2Q,
+ name: "VPSUBQMasked256",
+ argLen: 3,
+ asm: x86.AVPSUBQ,
reg: regInfo{
inputs: []inputInfo{
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
{
- name: "VPERMI2PDMasked128",
- argLen: 4,
- resultInArg0: true,
- asm: x86.AVPERMI2PD,
+ name: "VPSUBQMasked512",
+ argLen: 3,
+ asm: x86.AVPSUBQ,
reg: regInfo{
inputs: []inputInfo{
- {3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+ {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
{
- name: "VPERMI2QMasked128",
- argLen: 4,
- resultInArg0: true,
- asm: x86.AVPERMI2Q,
+ name: "VPSUBSB128",
+ argLen: 2,
+ asm: x86.AVPSUBSB,
reg: regInfo{
inputs: []inputInfo{
- {3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
{
- name: "VPSRLQ128",
+ name: "VPSUBSB256",
argLen: 2,
- asm: x86.AVPSRLQ,
+ asm: x86.AVPSUBSB,
reg: regInfo{
inputs: []inputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
{
- name: "VPSRLQMasked128",
- argLen: 3,
- asm: x86.AVPSRLQ,
+ name: "VPSUBSB512",
+ argLen: 2,
+ asm: x86.AVPSUBSB,
reg: regInfo{
inputs: []inputInfo{
- {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
- {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ {1, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
},
outputs: []outputInfo{
{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
},
},
{
- name: "VPSRLVQ128",
- argLen: 2,
- asm: x86.AVPSRLVQ,
+ name: "VPSUBSBMasked128",
+ argLen: 3,
+ asm: x86.AVPSUBSB,
reg: regInfo{
inputs: []inputInfo{
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
{
- name: "VPSRLVQMasked128",
+ name: "VPSUBSBMasked256",
argLen: 3,
- asm: x86.AVPSRLVQ,
+ asm: x86.AVPSUBSB,
reg: regInfo{
inputs: []inputInfo{
{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
},
},
{
- name: "VPMAXUQ256",
- argLen: 2,
- commutative: true,
- asm: x86.AVPMAXUQ,
+ name: "VPSUBSBMasked512",
+ argLen: 3,
+ asm: x86.AVPSUBSB,
reg: regInfo{
inputs: []inputInfo{
- {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
- {1, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
- {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
},
{
- name: "VPMAXUQMasked256",
- argLen: 3,
- commutative: true,
- asm: x86.AVPMAXUQ,
+ name: "VPSUBSW128",
+ argLen: 2,
+ asm: x86.AVPSUBSW,
reg: regInfo{
inputs: []inputInfo{
- {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
{
- name: "VPMINUQ256",
- argLen: 2,
- commutative: true,
- asm: x86.AVPMINUQ,
+ name: "VPSUBSW256",
+ argLen: 2,
+ asm: x86.AVPSUBSW,
reg: regInfo{
inputs: []inputInfo{
- {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
- {1, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
- {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
},
{
- name: "VPMINUQMasked256",
- argLen: 3,
- commutative: true,
- asm: x86.AVPMINUQ,
+ name: "VPSUBSW512",
+ argLen: 2,
+ asm: x86.AVPSUBSW,
reg: regInfo{
inputs: []inputInfo{
- {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ {1, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
},
outputs: []outputInfo{
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
},
},
},
{
- name: "VPMULUDQMasked256",
- argLen: 3,
- commutative: true,
- asm: x86.AVPMULUDQ,
+ name: "VPSUBSWMasked128",
+ argLen: 3,
+ asm: x86.AVPSUBSW,
reg: regInfo{
inputs: []inputInfo{
{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
},
},
{
- name: "VPERMPD256",
- argLen: 2,
- asm: x86.AVPERMPD,
+ name: "VPSUBSWMasked256",
+ argLen: 3,
+ asm: x86.AVPSUBSW,
reg: regInfo{
inputs: []inputInfo{
- {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
- {1, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
- {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
},
{
- name: "VPERMQ256",
- argLen: 2,
- asm: x86.AVPERMQ,
+ name: "VPSUBSWMasked512",
+ argLen: 3,
+ asm: x86.AVPSUBSW,
reg: regInfo{
inputs: []inputInfo{
- {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
- {1, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
- {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
},
{
- name: "VPERMI2PD256",
- argLen: 3,
- resultInArg0: true,
- asm: x86.AVPERMI2PD,
+ name: "VPSUBW128",
+ argLen: 2,
+ asm: x86.AVPSUBW,
reg: regInfo{
inputs: []inputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
{
- name: "VPERMI2Q256",
- argLen: 3,
- resultInArg0: true,
- asm: x86.AVPERMI2Q,
+ name: "VPSUBW256",
+ argLen: 2,
+ asm: x86.AVPSUBW,
reg: regInfo{
inputs: []inputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
{
- name: "VPERMI2PDMasked256",
- argLen: 4,
- resultInArg0: true,
- asm: x86.AVPERMI2PD,
+ name: "VPSUBW512",
+ argLen: 2,
+ asm: x86.AVPSUBW,
reg: regInfo{
inputs: []inputInfo{
- {3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ {1, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
},
outputs: []outputInfo{
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
},
},
},
{
- name: "VPERMI2QMasked256",
- argLen: 4,
- resultInArg0: true,
- asm: x86.AVPERMI2Q,
+ name: "VPSUBWMasked128",
+ argLen: 3,
+ asm: x86.AVPSUBW,
reg: regInfo{
inputs: []inputInfo{
- {3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+ {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
{
- name: "VPERMQMasked256",
+ name: "VPSUBWMasked256",
argLen: 3,
- asm: x86.AVPERMQ,
+ asm: x86.AVPSUBW,
reg: regInfo{
inputs: []inputInfo{
{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
},
},
{
- name: "VPERMPDMasked256",
+ name: "VPSUBWMasked512",
argLen: 3,
- asm: x86.AVPERMPD,
+ asm: x86.AVPSUBW,
reg: regInfo{
inputs: []inputInfo{
{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
},
},
{
- name: "VPSRLQ256",
- argLen: 2,
- asm: x86.AVPSRLQ,
+ name: "VPXOR128",
+ argLen: 2,
+ commutative: true,
+ asm: x86.AVPXOR,
reg: regInfo{
inputs: []inputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
{
- name: "VPSRLQMasked256",
- argLen: 3,
- asm: x86.AVPSRLQ,
+ name: "VPXOR256",
+ argLen: 2,
+ commutative: true,
+ asm: x86.AVPXOR,
reg: regInfo{
inputs: []inputInfo{
- {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
- {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
- {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
},
{
- name: "VPSRLVQ256",
- argLen: 2,
- asm: x86.AVPSRLVQ,
+ name: "VPXORD512",
+ argLen: 2,
+ commutative: true,
+ asm: x86.AVPXORD,
reg: regInfo{
inputs: []inputInfo{
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ {1, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
},
outputs: []outputInfo{
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
},
},
},
{
- name: "VPSRLVQMasked256",
- argLen: 3,
- asm: x86.AVPSRLVQ,
+ name: "VPXORDMasked128",
+ argLen: 3,
+ commutative: true,
+ asm: x86.AVPXORD,
reg: regInfo{
inputs: []inputInfo{
{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
},
},
{
- name: "VPMAXUQ512",
- argLen: 2,
+ name: "VPXORDMasked256",
+ argLen: 3,
commutative: true,
- asm: x86.AVPMAXUQ,
+ asm: x86.AVPXORD,
reg: regInfo{
inputs: []inputInfo{
- {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
- {1, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
- {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
},
{
- name: "VPMAXUQMasked512",
+ name: "VPXORDMasked512",
argLen: 3,
commutative: true,
- asm: x86.AVPMAXUQ,
+ asm: x86.AVPXORD,
reg: regInfo{
inputs: []inputInfo{
{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
},
},
{
- name: "VPMINUQ512",
+ name: "VPXORQ512",
argLen: 2,
commutative: true,
- asm: x86.AVPMINUQ,
+ asm: x86.AVPXORQ,
reg: regInfo{
inputs: []inputInfo{
{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
},
},
{
- name: "VPMINUQMasked512",
+ name: "VPXORQMasked128",
argLen: 3,
commutative: true,
- asm: x86.AVPMINUQ,
+ asm: x86.AVPXORQ,
reg: regInfo{
inputs: []inputInfo{
{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
},
},
{
- name: "VPMULUDQ512",
- argLen: 2,
+ name: "VPXORQMasked256",
+ argLen: 3,
commutative: true,
- asm: x86.AVPMULUDQ,
+ asm: x86.AVPXORQ,
reg: regInfo{
inputs: []inputInfo{
- {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
- {1, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
- {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
},
{
- name: "VPMULUDQMasked512",
+ name: "VPXORQMasked512",
argLen: 3,
commutative: true,
- asm: x86.AVPMULUDQ,
+ asm: x86.AVPXORQ,
reg: regInfo{
inputs: []inputInfo{
{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
},
},
{
- name: "VPERMPD512",
- argLen: 2,
- asm: x86.AVPERMPD,
+ name: "VRCP14PD128",
+ argLen: 1,
+ asm: x86.AVRCP14PD,
reg: regInfo{
inputs: []inputInfo{
{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
- {1, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
},
outputs: []outputInfo{
{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
},
},
{
- name: "VPERMQ512",
- argLen: 2,
- asm: x86.AVPERMQ,
+ name: "VRCP14PD256",
+ argLen: 1,
+ asm: x86.AVRCP14PD,
reg: regInfo{
inputs: []inputInfo{
{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
- {1, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
},
outputs: []outputInfo{
{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
},
},
{
- name: "VPERMI2Q512",
- argLen: 3,
- resultInArg0: true,
- asm: x86.AVPERMI2Q,
+ name: "VRCP14PD512",
+ argLen: 1,
+ asm: x86.AVRCP14PD,
reg: regInfo{
inputs: []inputInfo{
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
},
outputs: []outputInfo{
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
},
},
},
{
- name: "VPERMI2PD512",
- argLen: 3,
- resultInArg0: true,
- asm: x86.AVPERMI2PD,
+ name: "VRCP14PDMasked128",
+ argLen: 2,
+ asm: x86.AVRCP14PD,
reg: regInfo{
inputs: []inputInfo{
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {1, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
{
- name: "VPERMI2QMasked512",
- argLen: 4,
- resultInArg0: true,
- asm: x86.AVPERMI2Q,
+ name: "VRCP14PDMasked256",
+ argLen: 2,
+ asm: x86.AVRCP14PD,
reg: regInfo{
inputs: []inputInfo{
- {3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+ {1, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
{
- name: "VPERMI2PDMasked512",
- argLen: 4,
- resultInArg0: true,
- asm: x86.AVPERMI2PD,
+ name: "VRCP14PDMasked512",
+ argLen: 2,
+ asm: x86.AVRCP14PD,
reg: regInfo{
inputs: []inputInfo{
- {3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+ {1, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
{
- name: "VPERMPDMasked512",
- argLen: 3,
- asm: x86.AVPERMPD,
+ name: "VRCP14PS512",
+ argLen: 1,
+ asm: x86.AVRCP14PS,
reg: regInfo{
inputs: []inputInfo{
- {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ },
+ outputs: []outputInfo{
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ },
+ },
+ },
+ {
+ name: "VRCP14PSMasked128",
+ argLen: 2,
+ asm: x86.AVRCP14PS,
+ reg: regInfo{
+ inputs: []inputInfo{
+ {1, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
{
- name: "VPERMQMasked512",
- argLen: 3,
- asm: x86.AVPERMQ,
+ name: "VRCP14PSMasked256",
+ argLen: 2,
+ asm: x86.AVRCP14PS,
reg: regInfo{
inputs: []inputInfo{
- {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+ {1, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
{
- name: "VPSRLQ512",
+ name: "VRCP14PSMasked512",
argLen: 2,
- asm: x86.AVPSRLQ,
+ asm: x86.AVRCP14PS,
+ reg: regInfo{
+ inputs: []inputInfo{
+ {1, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ },
+ outputs: []outputInfo{
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ },
+ },
+ },
+ {
+ name: "VRCPPS128",
+ argLen: 1,
+ asm: x86.AVRCPPS,
+ reg: regInfo{
+ inputs: []inputInfo{
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ },
+ outputs: []outputInfo{
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ },
+ },
+ },
+ {
+ name: "VRCPPS256",
+ argLen: 1,
+ asm: x86.AVRCPPS,
+ reg: regInfo{
+ inputs: []inputInfo{
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ },
+ outputs: []outputInfo{
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ },
+ },
+ },
+ {
+ name: "VRSQRT14PD128",
+ argLen: 1,
+ asm: x86.AVRSQRT14PD,
reg: regInfo{
inputs: []inputInfo{
- {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
},
outputs: []outputInfo{
},
},
{
- name: "VPSRLQMasked512",
- argLen: 3,
- asm: x86.AVPSRLQ,
+ name: "VRSQRT14PD256",
+ argLen: 1,
+ asm: x86.AVRSQRT14PD,
reg: regInfo{
inputs: []inputInfo{
- {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
- {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
},
outputs: []outputInfo{
{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
},
},
{
- name: "VPSRLVQ512",
- argLen: 2,
- asm: x86.AVPSRLVQ,
+ name: "VRSQRT14PD512",
+ argLen: 1,
+ asm: x86.AVRSQRT14PD,
reg: regInfo{
inputs: []inputInfo{
{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
- {1, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
},
outputs: []outputInfo{
{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
},
},
{
- name: "VPSRLVQMasked512",
- argLen: 3,
- asm: x86.AVPSRLVQ,
+ name: "VRSQRT14PDMasked128",
+ argLen: 2,
+ asm: x86.AVRSQRT14PD,
reg: regInfo{
inputs: []inputInfo{
- {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+ {1, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
{
- name: "VPAVGB128",
- argLen: 2,
- commutative: true,
- asm: x86.AVPAVGB,
+ name: "VRSQRT14PDMasked256",
+ argLen: 2,
+ asm: x86.AVRSQRT14PD,
reg: regInfo{
inputs: []inputInfo{
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {1, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
{
- name: "VPAVGBMasked128",
- argLen: 3,
- commutative: true,
- asm: x86.AVPAVGB,
+ name: "VRSQRT14PDMasked512",
+ argLen: 2,
+ asm: x86.AVRSQRT14PD,
reg: regInfo{
inputs: []inputInfo{
- {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+ {1, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
{
- name: "VGF2P8MULB128",
- argLen: 2,
- asm: x86.AVGF2P8MULB,
+ name: "VRSQRT14PS512",
+ argLen: 1,
+ asm: x86.AVRSQRT14PS,
reg: regInfo{
inputs: []inputInfo{
{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
- {1, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
},
outputs: []outputInfo{
{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
},
},
{
- name: "VGF2P8MULBMasked128",
- argLen: 3,
- asm: x86.AVGF2P8MULB,
+ name: "VRSQRT14PSMasked128",
+ argLen: 2,
+ asm: x86.AVRSQRT14PS,
reg: regInfo{
inputs: []inputInfo{
- {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+ {1, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
{
- name: "VPMAXUB128",
- argLen: 2,
- commutative: true,
- asm: x86.AVPMAXUB,
+ name: "VRSQRT14PSMasked256",
+ argLen: 2,
+ asm: x86.AVRSQRT14PS,
reg: regInfo{
inputs: []inputInfo{
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {1, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
{
- name: "VPMAXUBMasked128",
- argLen: 3,
- commutative: true,
- asm: x86.AVPMAXUB,
+ name: "VRSQRT14PSMasked512",
+ argLen: 2,
+ asm: x86.AVRSQRT14PS,
reg: regInfo{
inputs: []inputInfo{
- {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+ {1, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
{
- name: "VPMINUB128",
- argLen: 2,
- commutative: true,
- asm: x86.AVPMINUB,
+ name: "VRSQRTPS128",
+ argLen: 1,
+ asm: x86.AVRSQRTPS,
reg: regInfo{
inputs: []inputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
{
- name: "VPMINUBMasked128",
- argLen: 3,
- commutative: true,
- asm: x86.AVPMINUB,
+ name: "VRSQRTPS256",
+ argLen: 1,
+ asm: x86.AVRSQRTPS,
reg: regInfo{
inputs: []inputInfo{
- {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
{
- name: "VPERMB128",
+ name: "VSCALEFPD128",
argLen: 2,
- asm: x86.AVPERMB,
+ asm: x86.AVSCALEFPD,
reg: regInfo{
inputs: []inputInfo{
{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
},
},
{
- name: "VPERMI2B128",
- argLen: 3,
- resultInArg0: true,
- asm: x86.AVPERMI2B,
+ name: "VSCALEFPD256",
+ argLen: 2,
+ asm: x86.AVSCALEFPD,
reg: regInfo{
inputs: []inputInfo{
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ {1, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
},
outputs: []outputInfo{
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
},
},
},
{
- name: "VPERMI2BMasked128",
- argLen: 4,
- resultInArg0: true,
- asm: x86.AVPERMI2B,
+ name: "VSCALEFPD512",
+ argLen: 2,
+ asm: x86.AVSCALEFPD,
reg: regInfo{
inputs: []inputInfo{
- {3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ {1, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
},
outputs: []outputInfo{
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
},
},
},
{
- name: "VPERMBMasked128",
+ name: "VSCALEFPDMasked128",
argLen: 3,
- asm: x86.AVPERMB,
+ asm: x86.AVSCALEFPD,
reg: regInfo{
inputs: []inputInfo{
{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
},
},
{
- name: "VPMADDUBSW128",
- argLen: 2,
- asm: x86.AVPMADDUBSW,
+ name: "VSCALEFPDMasked256",
+ argLen: 3,
+ asm: x86.AVSCALEFPD,
reg: regInfo{
inputs: []inputInfo{
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
{
- name: "VPMADDUBSWMasked128",
+ name: "VSCALEFPDMasked512",
argLen: 3,
- asm: x86.AVPMADDUBSW,
+ asm: x86.AVSCALEFPD,
reg: regInfo{
inputs: []inputInfo{
{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
},
},
{
- name: "VPAVGB256",
- argLen: 2,
- commutative: true,
- asm: x86.AVPAVGB,
+ name: "VSCALEFPS128",
+ argLen: 2,
+ asm: x86.AVSCALEFPS,
reg: regInfo{
inputs: []inputInfo{
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ {1, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
},
outputs: []outputInfo{
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
},
},
},
{
- name: "VPAVGBMasked256",
- argLen: 3,
- commutative: true,
- asm: x86.AVPAVGB,
+ name: "VSCALEFPS256",
+ argLen: 2,
+ asm: x86.AVSCALEFPS,
reg: regInfo{
inputs: []inputInfo{
- {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ {1, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
},
outputs: []outputInfo{
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
},
},
},
{
- name: "VGF2P8MULB256",
+ name: "VSCALEFPS512",
argLen: 2,
- asm: x86.AVGF2P8MULB,
+ asm: x86.AVSCALEFPS,
reg: regInfo{
inputs: []inputInfo{
{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
},
},
{
- name: "VGF2P8MULBMasked256",
+ name: "VSCALEFPSMasked128",
argLen: 3,
- asm: x86.AVGF2P8MULB,
+ asm: x86.AVSCALEFPS,
+ reg: regInfo{
+ inputs: []inputInfo{
+ {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ },
+ outputs: []outputInfo{
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ },
+ },
+ },
+ {
+ name: "VSCALEFPSMasked256",
+ argLen: 3,
+ asm: x86.AVSCALEFPS,
+ reg: regInfo{
+ inputs: []inputInfo{
+ {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ },
+ outputs: []outputInfo{
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ },
+ },
+ },
+ {
+ name: "VSCALEFPSMasked512",
+ argLen: 3,
+ asm: x86.AVSCALEFPS,
reg: regInfo{
inputs: []inputInfo{
{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
},
},
{
- name: "VPMAXUB256",
- argLen: 2,
- commutative: true,
- asm: x86.AVPMAXUB,
+ name: "VSQRTPD128",
+ argLen: 1,
+ asm: x86.AVSQRTPD,
reg: regInfo{
inputs: []inputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
{
- name: "VPMAXUBMasked256",
- argLen: 3,
- commutative: true,
- asm: x86.AVPMAXUB,
+ name: "VSQRTPD256",
+ argLen: 1,
+ asm: x86.AVSQRTPD,
reg: regInfo{
inputs: []inputInfo{
- {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
{
- name: "VPMINUB256",
- argLen: 2,
- commutative: true,
- asm: x86.AVPMINUB,
+ name: "VSQRTPD512",
+ argLen: 1,
+ asm: x86.AVSQRTPD,
reg: regInfo{
inputs: []inputInfo{
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
},
outputs: []outputInfo{
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
},
},
},
{
- name: "VPMINUBMasked256",
- argLen: 3,
- commutative: true,
- asm: x86.AVPMINUB,
+ name: "VSQRTPDMasked128",
+ argLen: 2,
+ asm: x86.AVSQRTPD,
reg: regInfo{
inputs: []inputInfo{
- {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+ {1, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
{
- name: "VPERMB256",
+ name: "VSQRTPDMasked256",
argLen: 2,
- asm: x86.AVPERMB,
+ asm: x86.AVSQRTPD,
reg: regInfo{
inputs: []inputInfo{
- {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
- {1, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ {1, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
- {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
},
{
- name: "VPERMI2B256",
- argLen: 3,
- resultInArg0: true,
- asm: x86.AVPERMI2B,
+ name: "VSQRTPDMasked512",
+ argLen: 2,
+ asm: x86.AVSQRTPD,
reg: regInfo{
inputs: []inputInfo{
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {1, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
{
- name: "VPERMI2BMasked256",
- argLen: 4,
- resultInArg0: true,
- asm: x86.AVPERMI2B,
+ name: "VSQRTPS128",
+ argLen: 1,
+ asm: x86.AVSQRTPS,
reg: regInfo{
inputs: []inputInfo{
- {3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
{
- name: "VPERMBMasked256",
- argLen: 3,
- asm: x86.AVPERMB,
+ name: "VSQRTPS256",
+ argLen: 1,
+ asm: x86.AVSQRTPS,
reg: regInfo{
inputs: []inputInfo{
- {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
{
- name: "VPMADDUBSW256",
- argLen: 2,
- asm: x86.AVPMADDUBSW,
+ name: "VSQRTPS512",
+ argLen: 1,
+ asm: x86.AVSQRTPS,
reg: regInfo{
inputs: []inputInfo{
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
},
outputs: []outputInfo{
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
},
},
},
{
- name: "VPMADDUBSWMasked256",
- argLen: 3,
- asm: x86.AVPMADDUBSW,
+ name: "VSQRTPSMasked128",
+ argLen: 2,
+ asm: x86.AVSQRTPS,
reg: regInfo{
inputs: []inputInfo{
- {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+ {1, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
{
- name: "VPAVGB512",
- argLen: 2,
- commutative: true,
- asm: x86.AVPAVGB,
+ name: "VSQRTPSMasked256",
+ argLen: 2,
+ asm: x86.AVSQRTPS,
reg: regInfo{
inputs: []inputInfo{
- {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
- {1, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ {1, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
- {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
},
{
- name: "VPAVGBMasked512",
- argLen: 3,
- commutative: true,
- asm: x86.AVPAVGB,
+ name: "VSQRTPSMasked512",
+ argLen: 2,
+ asm: x86.AVSQRTPS,
reg: regInfo{
inputs: []inputInfo{
- {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+ {1, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
{
- name: "VGF2P8MULB512",
+ name: "VSUBPD128",
argLen: 2,
- asm: x86.AVGF2P8MULB,
+ asm: x86.AVSUBPD,
reg: regInfo{
inputs: []inputInfo{
- {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
- {1, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
- {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
},
{
- name: "VGF2P8MULBMasked512",
- argLen: 3,
- asm: x86.AVGF2P8MULB,
+ name: "VSUBPD256",
+ argLen: 2,
+ asm: x86.AVSUBPD,
reg: regInfo{
inputs: []inputInfo{
- {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
{
- name: "VPMAXUB512",
- argLen: 2,
- commutative: true,
- asm: x86.AVPMAXUB,
+ name: "VSUBPD512",
+ argLen: 2,
+ asm: x86.AVSUBPD,
reg: regInfo{
inputs: []inputInfo{
{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
},
},
{
- name: "VPMAXUBMasked512",
- argLen: 3,
- commutative: true,
- asm: x86.AVPMAXUB,
+ name: "VSUBPDMasked128",
+ argLen: 3,
+ asm: x86.AVSUBPD,
reg: regInfo{
inputs: []inputInfo{
{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
},
},
{
- name: "VPMINUB512",
- argLen: 2,
- commutative: true,
- asm: x86.AVPMINUB,
+ name: "VSUBPDMasked256",
+ argLen: 3,
+ asm: x86.AVSUBPD,
reg: regInfo{
inputs: []inputInfo{
- {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
- {1, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
- {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
},
{
- name: "VPMINUBMasked512",
- argLen: 3,
- commutative: true,
- asm: x86.AVPMINUB,
+ name: "VSUBPDMasked512",
+ argLen: 3,
+ asm: x86.AVSUBPD,
reg: regInfo{
inputs: []inputInfo{
{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
},
},
{
- name: "VPERMB512",
+ name: "VSUBPS128",
argLen: 2,
- asm: x86.AVPERMB,
+ asm: x86.AVSUBPS,
reg: regInfo{
inputs: []inputInfo{
- {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
- {1, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
- {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
},
{
- name: "VPERMI2B512",
- argLen: 3,
- resultInArg0: true,
- asm: x86.AVPERMI2B,
+ name: "VSUBPS256",
+ argLen: 2,
+ asm: x86.AVSUBPS,
reg: regInfo{
inputs: []inputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
{
- name: "VPERMI2BMasked512",
- argLen: 4,
- resultInArg0: true,
- asm: x86.AVPERMI2B,
+ name: "VSUBPS512",
+ argLen: 2,
+ asm: x86.AVSUBPS,
reg: regInfo{
inputs: []inputInfo{
- {3, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ {1, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
},
outputs: []outputInfo{
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
},
},
},
{
- name: "VPERMBMasked512",
+ name: "VSUBPSMasked128",
argLen: 3,
- asm: x86.AVPERMB,
+ asm: x86.AVSUBPS,
reg: regInfo{
inputs: []inputInfo{
{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
},
},
{
- name: "VPMADDUBSW512",
- argLen: 2,
- asm: x86.AVPMADDUBSW,
+ name: "VSUBPSMasked256",
+ argLen: 3,
+ asm: x86.AVSUBPS,
reg: regInfo{
inputs: []inputInfo{
- {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
- {1, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
- {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
},
{
- name: "VPMADDUBSWMasked512",
+ name: "VSUBPSMasked512",
argLen: 3,
- asm: x86.AVPMADDUBSW,
+ asm: x86.AVSUBPS,
reg: regInfo{
inputs: []inputInfo{
{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
},
},
{
- name: "VRNDSCALEPS512",
+ name: "VROUNDPS128",
auxType: auxInt8,
argLen: 1,
- asm: x86.AVRNDSCALEPS,
+ asm: x86.AVROUNDPS,
reg: regInfo{
inputs: []inputInfo{
- {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
- {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
},
{
- name: "VRNDSCALEPSMasked512",
+ name: "VROUNDPS256",
auxType: auxInt8,
- argLen: 2,
- asm: x86.AVRNDSCALEPS,
+ argLen: 1,
+ asm: x86.AVROUNDPS,
reg: regInfo{
inputs: []inputInfo{
- {1, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
{
- name: "VREDUCEPS512",
+ name: "VROUNDPD128",
auxType: auxInt8,
argLen: 1,
- asm: x86.AVREDUCEPS,
+ asm: x86.AVROUNDPD,
reg: regInfo{
inputs: []inputInfo{
- {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
- {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
},
{
- name: "VREDUCEPSMasked512",
+ name: "VROUNDPD256",
auxType: auxInt8,
- argLen: 2,
- asm: x86.AVREDUCEPS,
+ argLen: 1,
+ asm: x86.AVROUNDPD,
reg: regInfo{
inputs: []inputInfo{
- {1, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
{
- name: "VCMPPS512",
- auxType: auxInt8,
- argLen: 2,
- commutative: true,
- asm: x86.AVCMPPS,
+ name: "VRNDSCALEPS128",
+ auxType: auxInt8,
+ argLen: 1,
+ asm: x86.AVRNDSCALEPS,
reg: regInfo{
inputs: []inputInfo{
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
},
outputs: []outputInfo{
- {0, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
},
},
},
{
- name: "VCMPPSMasked512",
- auxType: auxInt8,
- argLen: 3,
- commutative: true,
- asm: x86.AVCMPPS,
+ name: "VRNDSCALEPS256",
+ auxType: auxInt8,
+ argLen: 1,
+ asm: x86.AVRNDSCALEPS,
reg: regInfo{
inputs: []inputInfo{
- {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
},
outputs: []outputInfo{
- {0, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
},
},
},
{
- name: "VROUNDPS128",
+ name: "VRNDSCALEPS512",
auxType: auxInt8,
argLen: 1,
- asm: x86.AVROUNDPS,
+ asm: x86.AVRNDSCALEPS,
reg: regInfo{
inputs: []inputInfo{
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
},
outputs: []outputInfo{
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
},
},
},
{
- name: "VRNDSCALEPS128",
+ name: "VRNDSCALEPD128",
auxType: auxInt8,
argLen: 1,
- asm: x86.AVRNDSCALEPS,
+ asm: x86.AVRNDSCALEPD,
reg: regInfo{
inputs: []inputInfo{
{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
},
},
{
- name: "VRNDSCALEPSMasked128",
+ name: "VRNDSCALEPD256",
auxType: auxInt8,
- argLen: 2,
- asm: x86.AVRNDSCALEPS,
+ argLen: 1,
+ asm: x86.AVRNDSCALEPD,
reg: regInfo{
inputs: []inputInfo{
- {1, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
},
outputs: []outputInfo{
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
},
},
},
{
- name: "VREDUCEPS128",
+ name: "VRNDSCALEPD512",
auxType: auxInt8,
argLen: 1,
- asm: x86.AVREDUCEPS,
+ asm: x86.AVRNDSCALEPD,
reg: regInfo{
inputs: []inputInfo{
{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
},
},
{
- name: "VREDUCEPSMasked128",
+ name: "VRNDSCALEPSMasked128",
auxType: auxInt8,
argLen: 2,
- asm: x86.AVREDUCEPS,
+ asm: x86.AVRNDSCALEPS,
reg: regInfo{
inputs: []inputInfo{
{1, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
},
},
{
- name: "VDPPS128",
- auxType: auxInt8,
- argLen: 2,
- commutative: true,
- asm: x86.AVDPPS,
- reg: regInfo{
- inputs: []inputInfo{
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- },
- outputs: []outputInfo{
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- },
- },
- },
- {
- name: "VCMPPS128",
- auxType: auxInt8,
- argLen: 2,
- commutative: true,
- asm: x86.AVCMPPS,
+ name: "VRNDSCALEPSMasked256",
+ auxType: auxInt8,
+ argLen: 2,
+ asm: x86.AVRNDSCALEPS,
reg: regInfo{
inputs: []inputInfo{
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {1, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
{
- name: "VCMPPSMasked128",
- auxType: auxInt8,
- argLen: 3,
- commutative: true,
- asm: x86.AVCMPPS,
+ name: "VRNDSCALEPSMasked512",
+ auxType: auxInt8,
+ argLen: 2,
+ asm: x86.AVRNDSCALEPS,
reg: regInfo{
inputs: []inputInfo{
- {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+ {1, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
- {0, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
},
{
- name: "VROUNDPS256",
+ name: "VRNDSCALEPDMasked128",
auxType: auxInt8,
- argLen: 1,
- asm: x86.AVROUNDPS,
+ argLen: 2,
+ asm: x86.AVRNDSCALEPD,
reg: regInfo{
inputs: []inputInfo{
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {1, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
{
- name: "VRNDSCALEPS256",
+ name: "VRNDSCALEPDMasked256",
auxType: auxInt8,
- argLen: 1,
- asm: x86.AVRNDSCALEPS,
+ argLen: 2,
+ asm: x86.AVRNDSCALEPD,
reg: regInfo{
inputs: []inputInfo{
- {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ {1, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
- {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
},
{
- name: "VRNDSCALEPSMasked256",
+ name: "VRNDSCALEPDMasked512",
auxType: auxInt8,
argLen: 2,
- asm: x86.AVRNDSCALEPS,
+ asm: x86.AVRNDSCALEPD,
reg: regInfo{
inputs: []inputInfo{
{1, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
},
},
{
- name: "VREDUCEPS256",
+ name: "VREDUCEPS128",
auxType: auxInt8,
argLen: 1,
asm: x86.AVREDUCEPS,
},
},
{
- name: "VREDUCEPSMasked256",
+ name: "VREDUCEPS256",
auxType: auxInt8,
- argLen: 2,
+ argLen: 1,
asm: x86.AVREDUCEPS,
reg: regInfo{
inputs: []inputInfo{
- {1, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
},
outputs: []outputInfo{
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
},
},
},
{
- name: "VDPPS256",
- auxType: auxInt8,
- argLen: 2,
- commutative: true,
- asm: x86.AVDPPS,
+ name: "VREDUCEPS512",
+ auxType: auxInt8,
+ argLen: 1,
+ asm: x86.AVREDUCEPS,
reg: regInfo{
inputs: []inputInfo{
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
},
outputs: []outputInfo{
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
},
},
},
{
- name: "VCMPPS256",
- auxType: auxInt8,
- argLen: 2,
- commutative: true,
- asm: x86.AVCMPPS,
+ name: "VREDUCEPD128",
+ auxType: auxInt8,
+ argLen: 1,
+ asm: x86.AVREDUCEPD,
reg: regInfo{
inputs: []inputInfo{
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
},
outputs: []outputInfo{
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
},
},
},
{
- name: "VCMPPSMasked256",
- auxType: auxInt8,
- argLen: 3,
- commutative: true,
- asm: x86.AVCMPPS,
+ name: "VREDUCEPD256",
+ auxType: auxInt8,
+ argLen: 1,
+ asm: x86.AVREDUCEPD,
reg: regInfo{
inputs: []inputInfo{
- {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
},
outputs: []outputInfo{
- {0, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
},
},
},
{
- name: "VEXTRACTF128128",
+ name: "VREDUCEPD512",
auxType: auxInt8,
argLen: 1,
- asm: x86.AVEXTRACTF128,
+ asm: x86.AVREDUCEPD,
reg: regInfo{
inputs: []inputInfo{
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
},
outputs: []outputInfo{
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
},
},
},
{
- name: "VINSERTF128256",
+ name: "VREDUCEPSMasked128",
auxType: auxInt8,
argLen: 2,
- asm: x86.AVINSERTF128,
+ asm: x86.AVREDUCEPS,
reg: regInfo{
inputs: []inputInfo{
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {1, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
{
- name: "VROUNDPD128",
+ name: "VREDUCEPSMasked256",
auxType: auxInt8,
- argLen: 1,
- asm: x86.AVROUNDPD,
+ argLen: 2,
+ asm: x86.AVREDUCEPS,
reg: regInfo{
inputs: []inputInfo{
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {1, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
{
- name: "VRNDSCALEPD128",
+ name: "VREDUCEPSMasked512",
auxType: auxInt8,
- argLen: 1,
- asm: x86.AVRNDSCALEPD,
+ argLen: 2,
+ asm: x86.AVREDUCEPS,
reg: regInfo{
inputs: []inputInfo{
- {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ {1, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
- {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
},
{
- name: "VRNDSCALEPDMasked128",
+ name: "VREDUCEPDMasked128",
auxType: auxInt8,
argLen: 2,
- asm: x86.AVRNDSCALEPD,
+ asm: x86.AVREDUCEPD,
reg: regInfo{
inputs: []inputInfo{
{1, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
},
},
{
- name: "VREDUCEPD128",
+ name: "VREDUCEPDMasked256",
auxType: auxInt8,
- argLen: 1,
+ argLen: 2,
asm: x86.AVREDUCEPD,
reg: regInfo{
inputs: []inputInfo{
- {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ {1, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
- {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
},
{
- name: "VREDUCEPDMasked128",
+ name: "VREDUCEPDMasked512",
auxType: auxInt8,
argLen: 2,
asm: x86.AVREDUCEPD,
},
},
{
- name: "VDPPD128",
+ name: "VDPPS128",
auxType: auxInt8,
argLen: 2,
commutative: true,
- asm: x86.AVDPPD,
+ asm: x86.AVDPPS,
reg: regInfo{
inputs: []inputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
{
- name: "VCMPPD128",
+ name: "VDPPS256",
auxType: auxInt8,
argLen: 2,
commutative: true,
- asm: x86.AVCMPPD,
+ asm: x86.AVDPPS,
reg: regInfo{
inputs: []inputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
{
- name: "VCMPPDMasked128",
+ name: "VDPPD128",
auxType: auxInt8,
- argLen: 3,
+ argLen: 2,
commutative: true,
- asm: x86.AVCMPPD,
+ asm: x86.AVDPPD,
reg: regInfo{
inputs: []inputInfo{
- {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
- {0, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
},
{
- name: "VROUNDPD256",
- auxType: auxInt8,
- argLen: 1,
- asm: x86.AVROUNDPD,
+ name: "VCMPPS128",
+ auxType: auxInt8,
+ argLen: 2,
+ commutative: true,
+ asm: x86.AVCMPPS,
reg: regInfo{
inputs: []inputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
{
- name: "VRNDSCALEPD256",
- auxType: auxInt8,
- argLen: 1,
- asm: x86.AVRNDSCALEPD,
+ name: "VCMPPS256",
+ auxType: auxInt8,
+ argLen: 2,
+ commutative: true,
+ asm: x86.AVCMPPS,
reg: regInfo{
inputs: []inputInfo{
- {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
- {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
},
{
- name: "VRNDSCALEPDMasked256",
- auxType: auxInt8,
- argLen: 2,
- asm: x86.AVRNDSCALEPD,
+ name: "VCMPPS512",
+ auxType: auxInt8,
+ argLen: 2,
+ commutative: true,
+ asm: x86.AVCMPPS,
reg: regInfo{
inputs: []inputInfo{
- {1, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {0, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
},
},
},
{
- name: "VREDUCEPD256",
- auxType: auxInt8,
- argLen: 1,
- asm: x86.AVREDUCEPD,
+ name: "VCMPPD128",
+ auxType: auxInt8,
+ argLen: 2,
+ commutative: true,
+ asm: x86.AVCMPPD,
reg: regInfo{
inputs: []inputInfo{
- {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
- {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
},
{
- name: "VREDUCEPDMasked256",
- auxType: auxInt8,
- argLen: 2,
- asm: x86.AVREDUCEPD,
+ name: "VCMPPD256",
+ auxType: auxInt8,
+ argLen: 2,
+ commutative: true,
+ asm: x86.AVCMPPD,
reg: regInfo{
inputs: []inputInfo{
- {1, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
{
- name: "VCMPPD256",
+ name: "VCMPPD512",
auxType: auxInt8,
argLen: 2,
commutative: true,
{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {0, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
},
},
},
{
- name: "VCMPPDMasked256",
+ name: "VCMPPSMasked128",
auxType: auxInt8,
argLen: 3,
commutative: true,
- asm: x86.AVCMPPD,
+ asm: x86.AVCMPPS,
reg: regInfo{
inputs: []inputInfo{
{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
},
},
{
- name: "VRNDSCALEPD512",
- auxType: auxInt8,
- argLen: 1,
- asm: x86.AVRNDSCALEPD,
+ name: "VCMPPSMasked256",
+ auxType: auxInt8,
+ argLen: 3,
+ commutative: true,
+ asm: x86.AVCMPPS,
reg: regInfo{
inputs: []inputInfo{
- {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
- {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ {0, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
},
},
},
{
- name: "VRNDSCALEPDMasked512",
- auxType: auxInt8,
- argLen: 2,
- asm: x86.AVRNDSCALEPD,
+ name: "VCMPPSMasked512",
+ auxType: auxInt8,
+ argLen: 3,
+ commutative: true,
+ asm: x86.AVCMPPS,
reg: regInfo{
inputs: []inputInfo{
- {1, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+ {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {0, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
},
},
},
{
- name: "VREDUCEPD512",
- auxType: auxInt8,
- argLen: 1,
- asm: x86.AVREDUCEPD,
+ name: "VCMPPDMasked128",
+ auxType: auxInt8,
+ argLen: 3,
+ commutative: true,
+ asm: x86.AVCMPPD,
reg: regInfo{
inputs: []inputInfo{
- {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
- {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ {0, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
},
},
},
{
- name: "VREDUCEPDMasked512",
- auxType: auxInt8,
- argLen: 2,
- asm: x86.AVREDUCEPD,
+ name: "VCMPPDMasked256",
+ auxType: auxInt8,
+ argLen: 3,
+ commutative: true,
+ asm: x86.AVCMPPD,
reg: regInfo{
inputs: []inputInfo{
- {1, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+ {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {0, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
},
},
},
{
- name: "VCMPPD512",
+ name: "VCMPPDMasked512",
auxType: auxInt8,
- argLen: 2,
+ argLen: 3,
commutative: true,
asm: x86.AVCMPPD,
reg: regInfo{
inputs: []inputInfo{
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
{0, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
},
},
{
- name: "VCMPPDMasked512",
+ name: "VPCMPBMasked128",
auxType: auxInt8,
argLen: 3,
commutative: true,
- asm: x86.AVCMPPD,
+ asm: x86.AVPCMPB,
reg: regInfo{
inputs: []inputInfo{
{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
},
},
{
- name: "VPCMPWMasked256",
+ name: "VPCMPBMasked256",
auxType: auxInt8,
argLen: 3,
commutative: true,
- asm: x86.AVPCMPW,
+ asm: x86.AVPCMPB,
reg: regInfo{
inputs: []inputInfo{
{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
},
},
{
- name: "VPCMPW256",
- auxType: auxInt8,
- argLen: 2,
- asm: x86.AVPCMPW,
+ name: "VPCMPBMasked512",
+ auxType: auxInt8,
+ argLen: 3,
+ commutative: true,
+ asm: x86.AVPCMPB,
reg: regInfo{
inputs: []inputInfo{
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
{0, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
},
},
{
- name: "VPSHLDW256",
- auxType: auxInt8,
- argLen: 2,
- asm: x86.AVPSHLDW,
+ name: "VPCMPWMasked128",
+ auxType: auxInt8,
+ argLen: 3,
+ commutative: true,
+ asm: x86.AVPCMPW,
reg: regInfo{
inputs: []inputInfo{
- {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
- {1, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
- {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ {0, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
},
},
},
{
- name: "VPSHLDWMasked256",
- auxType: auxInt8,
- argLen: 3,
- asm: x86.AVPSHLDW,
+ name: "VPCMPWMasked256",
+ auxType: auxInt8,
+ argLen: 3,
+ commutative: true,
+ asm: x86.AVPCMPW,
reg: regInfo{
inputs: []inputInfo{
{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {0, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
},
},
},
{
- name: "VPSHRDW256",
- auxType: auxInt8,
- argLen: 2,
- asm: x86.AVPSHRDW,
+ name: "VPCMPWMasked512",
+ auxType: auxInt8,
+ argLen: 3,
+ commutative: true,
+ asm: x86.AVPCMPW,
reg: regInfo{
inputs: []inputInfo{
- {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
- {1, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
- {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ {0, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
},
},
},
{
- name: "VPSHRDWMasked256",
- auxType: auxInt8,
- argLen: 3,
- asm: x86.AVPSHRDW,
+ name: "VPCMPDMasked128",
+ auxType: auxInt8,
+ argLen: 3,
+ commutative: true,
+ asm: x86.AVPCMPD,
reg: regInfo{
inputs: []inputInfo{
{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {0, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
},
},
},
{
- name: "VPCMPWMasked512",
+ name: "VPCMPDMasked256",
auxType: auxInt8,
argLen: 3,
commutative: true,
- asm: x86.AVPCMPW,
+ asm: x86.AVPCMPD,
reg: regInfo{
inputs: []inputInfo{
{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
},
},
{
- name: "VPCMPW512",
- auxType: auxInt8,
- argLen: 2,
- asm: x86.AVPCMPW,
+ name: "VPCMPDMasked512",
+ auxType: auxInt8,
+ argLen: 3,
+ commutative: true,
+ asm: x86.AVPCMPD,
reg: regInfo{
inputs: []inputInfo{
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
{0, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
},
},
{
- name: "VPSHLDW512",
- auxType: auxInt8,
- argLen: 2,
- asm: x86.AVPSHLDW,
+ name: "VPCMPQMasked128",
+ auxType: auxInt8,
+ argLen: 3,
+ commutative: true,
+ asm: x86.AVPCMPQ,
reg: regInfo{
inputs: []inputInfo{
- {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
- {1, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
- {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ {0, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
},
},
},
{
- name: "VPSHLDWMasked512",
- auxType: auxInt8,
- argLen: 3,
- asm: x86.AVPSHLDW,
+ name: "VPCMPQMasked256",
+ auxType: auxInt8,
+ argLen: 3,
+ commutative: true,
+ asm: x86.AVPCMPQ,
reg: regInfo{
inputs: []inputInfo{
{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {0, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
},
},
},
{
- name: "VPSHRDW512",
- auxType: auxInt8,
- argLen: 2,
- asm: x86.AVPSHRDW,
+ name: "VPCMPQMasked512",
+ auxType: auxInt8,
+ argLen: 3,
+ commutative: true,
+ asm: x86.AVPCMPQ,
reg: regInfo{
inputs: []inputInfo{
- {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
- {1, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
- {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ {0, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
},
},
},
{
- name: "VPSHRDWMasked512",
- auxType: auxInt8,
- argLen: 3,
- asm: x86.AVPSHRDW,
+ name: "VPCMPUBMasked128",
+ auxType: auxInt8,
+ argLen: 3,
+ commutative: true,
+ asm: x86.AVPCMPUB,
reg: regInfo{
inputs: []inputInfo{
{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {0, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
},
},
},
{
- name: "VPCMPWMasked128",
+ name: "VPCMPUBMasked256",
auxType: auxInt8,
argLen: 3,
commutative: true,
- asm: x86.AVPCMPW,
+ asm: x86.AVPCMPUB,
reg: regInfo{
inputs: []inputInfo{
{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
},
},
{
- name: "VPEXTRW128",
- auxType: auxInt8,
- argLen: 1,
- asm: x86.AVPEXTRW,
+ name: "VPCMPUBMasked512",
+ auxType: auxInt8,
+ argLen: 3,
+ commutative: true,
+ asm: x86.AVPCMPUB,
reg: regInfo{
inputs: []inputInfo{
- {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
- {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
+ {0, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
},
},
},
{
- name: "VPCMPW128",
- auxType: auxInt8,
- argLen: 2,
- asm: x86.AVPCMPW,
+ name: "VPCMPUWMasked128",
+ auxType: auxInt8,
+ argLen: 3,
+ commutative: true,
+ asm: x86.AVPCMPUW,
reg: regInfo{
inputs: []inputInfo{
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
{0, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
},
},
{
- name: "VPINSRW128",
- auxType: auxInt8,
- argLen: 2,
- asm: x86.AVPINSRW,
+ name: "VPCMPUWMasked256",
+ auxType: auxInt8,
+ argLen: 3,
+ commutative: true,
+ asm: x86.AVPCMPUW,
reg: regInfo{
inputs: []inputInfo{
- {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {0, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
},
},
},
{
- name: "VPSHLDW128",
- auxType: auxInt8,
- argLen: 2,
- asm: x86.AVPSHLDW,
+ name: "VPCMPUWMasked512",
+ auxType: auxInt8,
+ argLen: 3,
+ commutative: true,
+ asm: x86.AVPCMPUW,
reg: regInfo{
inputs: []inputInfo{
- {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
- {1, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
- {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ {0, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
},
},
},
{
- name: "VPSHLDWMasked128",
- auxType: auxInt8,
- argLen: 3,
- asm: x86.AVPSHLDW,
+ name: "VPCMPUDMasked128",
+ auxType: auxInt8,
+ argLen: 3,
+ commutative: true,
+ asm: x86.AVPCMPUD,
reg: regInfo{
inputs: []inputInfo{
{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {0, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
},
},
},
{
- name: "VPSHRDW128",
- auxType: auxInt8,
- argLen: 2,
- asm: x86.AVPSHRDW,
+ name: "VPCMPUDMasked256",
+ auxType: auxInt8,
+ argLen: 3,
+ commutative: true,
+ asm: x86.AVPCMPUD,
reg: regInfo{
inputs: []inputInfo{
- {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
- {1, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
- {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ {0, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
},
},
},
{
- name: "VPSHRDWMasked128",
- auxType: auxInt8,
- argLen: 3,
- asm: x86.AVPSHRDW,
+ name: "VPCMPUDMasked512",
+ auxType: auxInt8,
+ argLen: 3,
+ commutative: true,
+ asm: x86.AVPCMPUD,
reg: regInfo{
inputs: []inputInfo{
{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {0, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
},
},
},
{
- name: "VPCMPDMasked512",
+ name: "VPCMPUQMasked128",
auxType: auxInt8,
argLen: 3,
commutative: true,
- asm: x86.AVPCMPD,
+ asm: x86.AVPCMPUQ,
reg: regInfo{
inputs: []inputInfo{
{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
},
},
{
- name: "VPCMPD512",
- auxType: auxInt8,
- argLen: 2,
- asm: x86.AVPCMPD,
+ name: "VPCMPUQMasked256",
+ auxType: auxInt8,
+ argLen: 3,
+ commutative: true,
+ asm: x86.AVPCMPUQ,
reg: regInfo{
inputs: []inputInfo{
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
{0, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
},
},
{
- name: "VPROLD512",
- auxType: auxInt8,
- argLen: 1,
- asm: x86.AVPROLD,
+ name: "VPCMPUQMasked512",
+ auxType: auxInt8,
+ argLen: 3,
+ commutative: true,
+ asm: x86.AVPCMPUQ,
reg: regInfo{
inputs: []inputInfo{
- {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
- {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ {0, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
},
},
},
{
- name: "VPROLDMasked512",
+ name: "VGF2P8AFFINEQB128",
auxType: auxInt8,
argLen: 2,
- asm: x86.AVPROLD,
+ asm: x86.AVGF2P8AFFINEQB,
reg: regInfo{
inputs: []inputInfo{
- {1, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ {1, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
},
outputs: []outputInfo{
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
},
},
},
{
- name: "VPRORD512",
+ name: "VGF2P8AFFINEQB256",
auxType: auxInt8,
- argLen: 1,
- asm: x86.AVPRORD,
+ argLen: 2,
+ asm: x86.AVGF2P8AFFINEQB,
reg: regInfo{
inputs: []inputInfo{
{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ {1, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
},
outputs: []outputInfo{
{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
},
},
{
- name: "VPRORDMasked512",
+ name: "VGF2P8AFFINEQB512",
auxType: auxInt8,
argLen: 2,
- asm: x86.AVPRORD,
+ asm: x86.AVGF2P8AFFINEQB,
reg: regInfo{
inputs: []inputInfo{
- {1, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ {1, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
},
outputs: []outputInfo{
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
},
},
},
{
- name: "VPSHLDD512",
+ name: "VGF2P8AFFINEINVQB128",
auxType: auxInt8,
argLen: 2,
- asm: x86.AVPSHLDD,
+ asm: x86.AVGF2P8AFFINEINVQB,
reg: regInfo{
inputs: []inputInfo{
{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
},
},
{
- name: "VPSHLDDMasked512",
+ name: "VGF2P8AFFINEINVQB256",
auxType: auxInt8,
- argLen: 3,
- asm: x86.AVPSHLDD,
+ argLen: 2,
+ asm: x86.AVGF2P8AFFINEINVQB,
reg: regInfo{
inputs: []inputInfo{
- {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ {1, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
},
outputs: []outputInfo{
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
},
},
},
{
- name: "VPSHRDD512",
+ name: "VGF2P8AFFINEINVQB512",
auxType: auxInt8,
argLen: 2,
- asm: x86.AVPSHRDD,
+ asm: x86.AVGF2P8AFFINEINVQB,
reg: regInfo{
inputs: []inputInfo{
{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
},
},
{
- name: "VPSHRDDMasked512",
+ name: "VGF2P8AFFINEINVQBMasked128",
auxType: auxInt8,
argLen: 3,
- asm: x86.AVPSHRDD,
+ asm: x86.AVGF2P8AFFINEINVQB,
reg: regInfo{
inputs: []inputInfo{
{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
},
},
{
- name: "VPCMPDMasked128",
- auxType: auxInt8,
- argLen: 3,
- commutative: true,
- asm: x86.AVPCMPD,
- reg: regInfo{
- inputs: []inputInfo{
- {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- },
- outputs: []outputInfo{
- {0, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
- },
- },
- },
- {
- name: "VPEXTRD128",
- auxType: auxInt8,
- argLen: 1,
- asm: x86.AVPEXTRD,
+ name: "VGF2P8AFFINEINVQBMasked256",
+ auxType: auxInt8,
+ argLen: 3,
+ asm: x86.AVGF2P8AFFINEINVQB,
reg: regInfo{
inputs: []inputInfo{
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
- {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
},
{
- name: "VPCMPD128",
+ name: "VGF2P8AFFINEINVQBMasked512",
auxType: auxInt8,
- argLen: 2,
- asm: x86.AVPCMPD,
+ argLen: 3,
+ asm: x86.AVGF2P8AFFINEINVQB,
reg: regInfo{
inputs: []inputInfo{
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
- {0, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
},
{
- name: "VPROLD128",
+ name: "VGF2P8AFFINEQBMasked128",
auxType: auxInt8,
- argLen: 1,
- asm: x86.AVPROLD,
+ argLen: 3,
+ asm: x86.AVGF2P8AFFINEQB,
reg: regInfo{
inputs: []inputInfo{
- {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
- {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
},
{
- name: "VPROLDMasked128",
+ name: "VGF2P8AFFINEQBMasked256",
auxType: auxInt8,
- argLen: 2,
- asm: x86.AVPROLD,
+ argLen: 3,
+ asm: x86.AVGF2P8AFFINEQB,
reg: regInfo{
inputs: []inputInfo{
- {1, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+ {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
{
- name: "VPRORD128",
+ name: "VGF2P8AFFINEQBMasked512",
auxType: auxInt8,
- argLen: 1,
- asm: x86.AVPRORD,
+ argLen: 3,
+ asm: x86.AVGF2P8AFFINEQB,
reg: regInfo{
inputs: []inputInfo{
- {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
- {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
},
{
- name: "VPRORDMasked128",
+ name: "VEXTRACTF128128",
auxType: auxInt8,
- argLen: 2,
- asm: x86.AVPRORD,
+ argLen: 1,
+ asm: x86.AVEXTRACTF128,
reg: regInfo{
inputs: []inputInfo{
- {1, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
{
- name: "VPINSRD128",
+ name: "VEXTRACTI128128",
auxType: auxInt8,
- argLen: 2,
- asm: x86.AVPINSRD,
+ argLen: 1,
+ asm: x86.AVEXTRACTI128,
reg: regInfo{
inputs: []inputInfo{
- {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
},
},
{
- name: "VPSHLDD128",
+ name: "VPEXTRB128",
auxType: auxInt8,
- argLen: 2,
- asm: x86.AVPSHLDD,
+ argLen: 1,
+ asm: x86.AVPEXTRB,
reg: regInfo{
inputs: []inputInfo{
{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
- {1, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
},
outputs: []outputInfo{
- {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
},
},
},
{
- name: "VPSHLDDMasked128",
+ name: "VPEXTRW128",
auxType: auxInt8,
- argLen: 3,
- asm: x86.AVPSHLDD,
+ argLen: 1,
+ asm: x86.AVPEXTRW,
reg: regInfo{
inputs: []inputInfo{
- {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
},
outputs: []outputInfo{
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
},
},
},
{
- name: "VPSHRDD128",
+ name: "VPEXTRD128",
auxType: auxInt8,
- argLen: 2,
- asm: x86.AVPSHRDD,
+ argLen: 1,
+ asm: x86.AVPEXTRD,
reg: regInfo{
inputs: []inputInfo{
- {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
- {1, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
- {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
},
},
},
{
- name: "VPSHRDDMasked128",
+ name: "VPEXTRQ128",
auxType: auxInt8,
- argLen: 3,
- asm: x86.AVPSHRDD,
+ argLen: 1,
+ asm: x86.AVPEXTRQ,
reg: regInfo{
inputs: []inputInfo{
- {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
},
},
},
{
- name: "VPCMPDMasked256",
- auxType: auxInt8,
- argLen: 3,
- commutative: true,
- asm: x86.AVPCMPD,
+ name: "VPCMPUB128",
+ auxType: auxInt8,
+ argLen: 2,
+ asm: x86.AVPCMPUB,
reg: regInfo{
inputs: []inputInfo{
- {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
{0, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
},
},
{
- name: "VPCMPD256",
+ name: "VPCMPUB256",
auxType: auxInt8,
argLen: 2,
- asm: x86.AVPCMPD,
+ asm: x86.AVPCMPUB,
reg: regInfo{
inputs: []inputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
{
- name: "VPROLD256",
+ name: "VPCMPUB512",
auxType: auxInt8,
- argLen: 1,
- asm: x86.AVPROLD,
+ argLen: 2,
+ asm: x86.AVPCMPUB,
reg: regInfo{
inputs: []inputInfo{
- {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
- {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ {0, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
},
},
},
{
- name: "VPROLDMasked256",
+ name: "VPCMPUW128",
auxType: auxInt8,
argLen: 2,
- asm: x86.AVPROLD,
+ asm: x86.AVPCMPUW,
reg: regInfo{
inputs: []inputInfo{
- {1, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {0, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
},
},
},
{
- name: "VPRORD256",
+ name: "VPCMPUW256",
auxType: auxInt8,
- argLen: 1,
- asm: x86.AVPRORD,
+ argLen: 2,
+ asm: x86.AVPCMPUW,
reg: regInfo{
inputs: []inputInfo{
- {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
- {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ {0, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
},
},
},
{
- name: "VPRORDMasked256",
+ name: "VPCMPUW512",
auxType: auxInt8,
argLen: 2,
- asm: x86.AVPRORD,
+ asm: x86.AVPCMPUW,
reg: regInfo{
inputs: []inputInfo{
- {1, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {0, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
},
},
},
{
- name: "VPSHLDD256",
+ name: "VPCMPUD128",
auxType: auxInt8,
argLen: 2,
- asm: x86.AVPSHLDD,
+ asm: x86.AVPCMPUD,
reg: regInfo{
inputs: []inputInfo{
- {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
- {1, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
- {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ {0, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
},
},
},
{
- name: "VPSHLDDMasked256",
+ name: "VPCMPUD256",
auxType: auxInt8,
- argLen: 3,
- asm: x86.AVPSHLDD,
+ argLen: 2,
+ asm: x86.AVPCMPUD,
reg: regInfo{
inputs: []inputInfo{
- {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {0, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
},
},
},
{
- name: "VPSHRDD256",
+ name: "VPCMPUD512",
auxType: auxInt8,
argLen: 2,
- asm: x86.AVPSHRDD,
+ asm: x86.AVPCMPUD,
reg: regInfo{
inputs: []inputInfo{
- {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
- {1, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
- {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ {0, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
},
},
},
{
- name: "VPSHRDDMasked256",
+ name: "VPCMPUQ128",
auxType: auxInt8,
- argLen: 3,
- asm: x86.AVPSHRDD,
+ argLen: 2,
+ asm: x86.AVPCMPUQ,
reg: regInfo{
inputs: []inputInfo{
- {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {0, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
},
},
},
{
- name: "VPCMPQMasked128",
- auxType: auxInt8,
- argLen: 3,
- commutative: true,
- asm: x86.AVPCMPQ,
+ name: "VPCMPUQ256",
+ auxType: auxInt8,
+ argLen: 2,
+ asm: x86.AVPCMPUQ,
reg: regInfo{
inputs: []inputInfo{
- {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
{0, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
},
},
{
- name: "VPEXTRQ128",
+ name: "VPCMPUQ512",
auxType: auxInt8,
- argLen: 1,
- asm: x86.AVPEXTRQ,
+ argLen: 2,
+ asm: x86.AVPCMPUQ,
reg: regInfo{
inputs: []inputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
- {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
+ {0, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
},
},
},
{
- name: "VPCMPQ128",
+ name: "VPCMPB128",
auxType: auxInt8,
argLen: 2,
- asm: x86.AVPCMPQ,
+ asm: x86.AVPCMPB,
reg: regInfo{
inputs: []inputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
{
- name: "VPROLQ128",
+ name: "VPCMPB256",
auxType: auxInt8,
- argLen: 1,
- asm: x86.AVPROLQ,
+ argLen: 2,
+ asm: x86.AVPCMPB,
reg: regInfo{
inputs: []inputInfo{
- {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
- {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ {0, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
},
},
},
{
- name: "VPROLQMasked128",
+ name: "VPCMPB512",
auxType: auxInt8,
argLen: 2,
- asm: x86.AVPROLQ,
+ asm: x86.AVPCMPB,
reg: regInfo{
inputs: []inputInfo{
- {1, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {0, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
},
},
},
{
- name: "VPRORQ128",
+ name: "VPCMPW128",
auxType: auxInt8,
- argLen: 1,
- asm: x86.AVPRORQ,
+ argLen: 2,
+ asm: x86.AVPCMPW,
reg: regInfo{
inputs: []inputInfo{
- {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
- {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ {0, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
},
},
},
{
- name: "VPRORQMasked128",
+ name: "VPCMPW256",
auxType: auxInt8,
argLen: 2,
- asm: x86.AVPRORQ,
+ asm: x86.AVPCMPW,
reg: regInfo{
inputs: []inputInfo{
- {1, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {0, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
},
},
},
{
- name: "VPINSRQ128",
+ name: "VPCMPW512",
auxType: auxInt8,
argLen: 2,
- asm: x86.AVPINSRQ,
+ asm: x86.AVPCMPW,
reg: regInfo{
inputs: []inputInfo{
- {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {0, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
},
},
},
{
- name: "VPSHLDQ128",
+ name: "VPCMPD128",
auxType: auxInt8,
argLen: 2,
- asm: x86.AVPSHLDQ,
+ asm: x86.AVPCMPD,
reg: regInfo{
inputs: []inputInfo{
- {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
- {1, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
- {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ {0, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
},
},
},
{
- name: "VPSHLDQMasked128",
+ name: "VPCMPD256",
auxType: auxInt8,
- argLen: 3,
- asm: x86.AVPSHLDQ,
+ argLen: 2,
+ asm: x86.AVPCMPD,
reg: regInfo{
inputs: []inputInfo{
- {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {0, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
},
},
},
{
- name: "VPSHRDQ128",
+ name: "VPCMPD512",
auxType: auxInt8,
argLen: 2,
- asm: x86.AVPSHRDQ,
+ asm: x86.AVPCMPD,
reg: regInfo{
inputs: []inputInfo{
- {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
- {1, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
- {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ {0, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
},
},
},
{
- name: "VPSHRDQMasked128",
+ name: "VPCMPQ128",
auxType: auxInt8,
- argLen: 3,
- asm: x86.AVPSHRDQ,
+ argLen: 2,
+ asm: x86.AVPCMPQ,
reg: regInfo{
inputs: []inputInfo{
- {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {0, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
},
},
},
{
- name: "VPCMPQMasked256",
- auxType: auxInt8,
- argLen: 3,
- commutative: true,
- asm: x86.AVPCMPQ,
+ name: "VPCMPQ256",
+ auxType: auxInt8,
+ argLen: 2,
+ asm: x86.AVPCMPQ,
reg: regInfo{
inputs: []inputInfo{
- {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
{0, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
},
},
{
- name: "VPCMPQ256",
+ name: "VPCMPQ512",
auxType: auxInt8,
argLen: 2,
asm: x86.AVPCMPQ,
},
},
{
- name: "VPROLQ256",
+ name: "VPROLD128",
auxType: auxInt8,
argLen: 1,
- asm: x86.AVPROLQ,
+ asm: x86.AVPROLD,
reg: regInfo{
inputs: []inputInfo{
{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
},
},
{
- name: "VPROLQMasked256",
+ name: "VPROLD256",
auxType: auxInt8,
- argLen: 2,
- asm: x86.AVPROLQ,
+ argLen: 1,
+ asm: x86.AVPROLD,
reg: regInfo{
inputs: []inputInfo{
- {1, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
},
outputs: []outputInfo{
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
},
},
},
{
- name: "VPRORQ256",
+ name: "VPROLD512",
auxType: auxInt8,
argLen: 1,
- asm: x86.AVPRORQ,
+ asm: x86.AVPROLD,
reg: regInfo{
inputs: []inputInfo{
{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
},
},
{
- name: "VPRORQMasked256",
+ name: "VPROLQ128",
auxType: auxInt8,
- argLen: 2,
- asm: x86.AVPRORQ,
+ argLen: 1,
+ asm: x86.AVPROLQ,
reg: regInfo{
inputs: []inputInfo{
- {1, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
},
outputs: []outputInfo{
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
},
},
},
{
- name: "VPSHLDQ256",
+ name: "VPROLQ256",
auxType: auxInt8,
- argLen: 2,
- asm: x86.AVPSHLDQ,
+ argLen: 1,
+ asm: x86.AVPROLQ,
reg: regInfo{
inputs: []inputInfo{
{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
- {1, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
},
outputs: []outputInfo{
{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
},
},
{
- name: "VPSHLDQMasked256",
+ name: "VPROLQ512",
auxType: auxInt8,
- argLen: 3,
- asm: x86.AVPSHLDQ,
+ argLen: 1,
+ asm: x86.AVPROLQ,
reg: regInfo{
inputs: []inputInfo{
- {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
},
outputs: []outputInfo{
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
},
},
},
{
- name: "VPSHRDQ256",
+ name: "VPROLDMasked128",
auxType: auxInt8,
argLen: 2,
- asm: x86.AVPSHRDQ,
+ asm: x86.AVPROLD,
reg: regInfo{
inputs: []inputInfo{
- {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
- {1, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ {1, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
- {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
},
{
- name: "VPSHRDQMasked256",
+ name: "VPROLDMasked256",
auxType: auxInt8,
- argLen: 3,
- asm: x86.AVPSHRDQ,
+ argLen: 2,
+ asm: x86.AVPROLD,
reg: regInfo{
inputs: []inputInfo{
- {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+ {1, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
{
- name: "VPCMPQMasked512",
- auxType: auxInt8,
- argLen: 3,
- commutative: true,
- asm: x86.AVPCMPQ,
+ name: "VPROLDMasked512",
+ auxType: auxInt8,
+ argLen: 2,
+ asm: x86.AVPROLD,
reg: regInfo{
inputs: []inputInfo{
- {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+ {1, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
- {0, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
},
{
- name: "VPCMPQ512",
+ name: "VPROLQMasked128",
auxType: auxInt8,
argLen: 2,
- asm: x86.AVPCMPQ,
+ asm: x86.AVPROLQ,
reg: regInfo{
inputs: []inputInfo{
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {1, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
- {0, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
},
{
- name: "VPROLQ512",
+ name: "VPROLQMasked256",
auxType: auxInt8,
- argLen: 1,
+ argLen: 2,
asm: x86.AVPROLQ,
reg: regInfo{
inputs: []inputInfo{
- {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ {1, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
- {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
},
},
},
{
- name: "VPRORQ512",
+ name: "VPRORD128",
auxType: auxInt8,
argLen: 1,
- asm: x86.AVPRORQ,
+ asm: x86.AVPRORD,
reg: regInfo{
inputs: []inputInfo{
{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
},
},
{
- name: "VPRORQMasked512",
+ name: "VPRORD256",
auxType: auxInt8,
- argLen: 2,
- asm: x86.AVPRORQ,
+ argLen: 1,
+ asm: x86.AVPRORD,
reg: regInfo{
inputs: []inputInfo{
- {1, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
},
outputs: []outputInfo{
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
},
},
},
{
- name: "VPSHLDQ512",
+ name: "VPRORD512",
auxType: auxInt8,
- argLen: 2,
- asm: x86.AVPSHLDQ,
+ argLen: 1,
+ asm: x86.AVPRORD,
reg: regInfo{
inputs: []inputInfo{
{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
- {1, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
},
outputs: []outputInfo{
{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
},
},
{
- name: "VPSHLDQMasked512",
+ name: "VPRORQ128",
auxType: auxInt8,
- argLen: 3,
- asm: x86.AVPSHLDQ,
+ argLen: 1,
+ asm: x86.AVPRORQ,
reg: regInfo{
inputs: []inputInfo{
- {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
},
outputs: []outputInfo{
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
},
},
},
{
- name: "VPSHRDQ512",
+ name: "VPRORQ256",
auxType: auxInt8,
- argLen: 2,
- asm: x86.AVPSHRDQ,
+ argLen: 1,
+ asm: x86.AVPRORQ,
+ reg: regInfo{
+ inputs: []inputInfo{
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ },
+ outputs: []outputInfo{
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ },
+ },
+ },
+ {
+ name: "VPRORQ512",
+ auxType: auxInt8,
+ argLen: 1,
+ asm: x86.AVPRORQ,
reg: regInfo{
inputs: []inputInfo{
{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
- {1, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
},
outputs: []outputInfo{
{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
},
},
{
- name: "VPSHRDQMasked512",
+ name: "VPRORDMasked128",
auxType: auxInt8,
- argLen: 3,
- asm: x86.AVPSHRDQ,
+ argLen: 2,
+ asm: x86.AVPRORD,
reg: regInfo{
inputs: []inputInfo{
- {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+ {1, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
{
- name: "VPCMPBMasked128",
- auxType: auxInt8,
- argLen: 3,
- commutative: true,
- asm: x86.AVPCMPB,
+ name: "VPRORDMasked256",
+ auxType: auxInt8,
+ argLen: 2,
+ asm: x86.AVPRORD,
reg: regInfo{
inputs: []inputInfo{
- {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+ {1, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
- {0, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
},
{
- name: "VPEXTRB128",
+ name: "VPRORDMasked512",
auxType: auxInt8,
- argLen: 1,
- asm: x86.AVPEXTRB,
+ argLen: 2,
+ asm: x86.AVPRORD,
reg: regInfo{
inputs: []inputInfo{
- {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ {1, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
- {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
},
{
- name: "VPCMPB128",
+ name: "VPRORQMasked128",
auxType: auxInt8,
argLen: 2,
- asm: x86.AVPCMPB,
+ asm: x86.AVPRORQ,
reg: regInfo{
inputs: []inputInfo{
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {1, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
- {0, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
},
{
- name: "VPINSRB128",
+ name: "VPRORQMasked256",
auxType: auxInt8,
argLen: 2,
- asm: x86.AVPINSRB,
+ asm: x86.AVPRORQ,
reg: regInfo{
inputs: []inputInfo{
- {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {1, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
{
- name: "VPCMPBMasked256",
- auxType: auxInt8,
- argLen: 3,
- commutative: true,
- asm: x86.AVPCMPB,
+ name: "VPRORQMasked512",
+ auxType: auxInt8,
+ argLen: 2,
+ asm: x86.AVPRORQ,
reg: regInfo{
inputs: []inputInfo{
- {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+ {1, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
- {0, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
},
{
- name: "VEXTRACTI128128",
+ name: "VINSERTF128256",
auxType: auxInt8,
- argLen: 1,
- asm: x86.AVEXTRACTI128,
+ argLen: 2,
+ asm: x86.AVINSERTF128,
reg: regInfo{
inputs: []inputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
{
- name: "VPCMPB256",
+ name: "VINSERTI128256",
auxType: auxInt8,
argLen: 2,
- asm: x86.AVPCMPB,
+ asm: x86.AVINSERTI128,
reg: regInfo{
inputs: []inputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
- {0, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
},
{
- name: "VINSERTI128256",
+ name: "VPINSRB128",
auxType: auxInt8,
argLen: 2,
- asm: x86.AVINSERTI128,
+ asm: x86.AVPINSRB,
reg: regInfo{
inputs: []inputInfo{
+ {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
{
- name: "VPCMPBMasked512",
- auxType: auxInt8,
- argLen: 3,
- commutative: true,
- asm: x86.AVPCMPB,
+ name: "VPINSRW128",
+ auxType: auxInt8,
+ argLen: 2,
+ asm: x86.AVPINSRW,
reg: regInfo{
inputs: []inputInfo{
- {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
- {0, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
},
{
- name: "VPCMPB512",
+ name: "VPINSRD128",
auxType: auxInt8,
argLen: 2,
- asm: x86.AVPCMPB,
+ asm: x86.AVPINSRD,
reg: regInfo{
inputs: []inputInfo{
+ {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
- {0, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
},
{
- name: "VPCMPUWMasked256",
- auxType: auxInt8,
- argLen: 3,
- commutative: true,
- asm: x86.AVPCMPUW,
+ name: "VPINSRQ128",
+ auxType: auxInt8,
+ argLen: 2,
+ asm: x86.AVPINSRQ,
reg: regInfo{
inputs: []inputInfo{
- {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
- {0, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
},
{
- name: "VPCMPUW256",
+ name: "VPSHLDW128",
auxType: auxInt8,
argLen: 2,
- asm: x86.AVPCMPUW,
+ asm: x86.AVPSHLDW,
reg: regInfo{
inputs: []inputInfo{
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ {1, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
},
outputs: []outputInfo{
- {0, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
},
},
},
{
- name: "VPCMPUWMasked512",
- auxType: auxInt8,
- argLen: 3,
- commutative: true,
- asm: x86.AVPCMPUW,
+ name: "VPSHLDW256",
+ auxType: auxInt8,
+ argLen: 2,
+ asm: x86.AVPSHLDW,
reg: regInfo{
inputs: []inputInfo{
- {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ {1, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
},
outputs: []outputInfo{
- {0, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
},
},
},
{
- name: "VPCMPUW512",
+ name: "VPSHLDW512",
auxType: auxInt8,
argLen: 2,
- asm: x86.AVPCMPUW,
+ asm: x86.AVPSHLDW,
reg: regInfo{
inputs: []inputInfo{
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ {1, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
},
outputs: []outputInfo{
- {0, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
},
},
},
{
- name: "VPCMPUWMasked128",
- auxType: auxInt8,
- argLen: 3,
- commutative: true,
- asm: x86.AVPCMPUW,
+ name: "VPSHLDD128",
+ auxType: auxInt8,
+ argLen: 2,
+ asm: x86.AVPSHLDD,
reg: regInfo{
inputs: []inputInfo{
- {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ {1, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
},
outputs: []outputInfo{
- {0, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
},
},
},
{
- name: "VPCMPUW128",
+ name: "VPSHLDD256",
auxType: auxInt8,
argLen: 2,
- asm: x86.AVPCMPUW,
+ asm: x86.AVPSHLDD,
reg: regInfo{
inputs: []inputInfo{
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ {1, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
},
outputs: []outputInfo{
- {0, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
},
},
},
{
- name: "VPCMPUDMasked512",
- auxType: auxInt8,
- argLen: 3,
- commutative: true,
- asm: x86.AVPCMPUD,
+ name: "VPSHLDD512",
+ auxType: auxInt8,
+ argLen: 2,
+ asm: x86.AVPSHLDD,
reg: regInfo{
inputs: []inputInfo{
- {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ {1, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
},
outputs: []outputInfo{
- {0, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
},
},
},
{
- name: "VPCMPUD512",
+ name: "VPSHLDQ128",
auxType: auxInt8,
argLen: 2,
- asm: x86.AVPCMPUD,
+ asm: x86.AVPSHLDQ,
reg: regInfo{
inputs: []inputInfo{
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ {1, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
},
outputs: []outputInfo{
- {0, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
},
},
},
{
- name: "VPCMPUDMasked128",
- auxType: auxInt8,
- argLen: 3,
- commutative: true,
- asm: x86.AVPCMPUD,
+ name: "VPSHLDQ256",
+ auxType: auxInt8,
+ argLen: 2,
+ asm: x86.AVPSHLDQ,
reg: regInfo{
inputs: []inputInfo{
- {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ {1, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
},
outputs: []outputInfo{
- {0, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
},
},
},
{
- name: "VPCMPUD128",
+ name: "VPSHLDQ512",
auxType: auxInt8,
argLen: 2,
- asm: x86.AVPCMPUD,
+ asm: x86.AVPSHLDQ,
reg: regInfo{
inputs: []inputInfo{
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ {1, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
},
outputs: []outputInfo{
- {0, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
},
},
},
{
- name: "VPCMPUDMasked256",
- auxType: auxInt8,
- argLen: 3,
- commutative: true,
- asm: x86.AVPCMPUD,
+ name: "VPSHLDWMasked128",
+ auxType: auxInt8,
+ argLen: 3,
+ asm: x86.AVPSHLDW,
reg: regInfo{
inputs: []inputInfo{
{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
- {0, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
},
{
- name: "VPCMPUD256",
+ name: "VPSHLDWMasked256",
auxType: auxInt8,
- argLen: 2,
- asm: x86.AVPCMPUD,
+ argLen: 3,
+ asm: x86.AVPSHLDW,
reg: regInfo{
inputs: []inputInfo{
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
- {0, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
},
{
- name: "VPCMPUQMasked128",
- auxType: auxInt8,
- argLen: 3,
- commutative: true,
- asm: x86.AVPCMPUQ,
+ name: "VPSHLDWMasked512",
+ auxType: auxInt8,
+ argLen: 3,
+ asm: x86.AVPSHLDW,
reg: regInfo{
inputs: []inputInfo{
{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
- {0, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
},
{
- name: "VPCMPUQ128",
+ name: "VPSHLDDMasked128",
auxType: auxInt8,
- argLen: 2,
- asm: x86.AVPCMPUQ,
+ argLen: 3,
+ asm: x86.AVPSHLDD,
reg: regInfo{
inputs: []inputInfo{
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
- {0, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
},
{
- name: "VPCMPUQMasked256",
- auxType: auxInt8,
- argLen: 3,
- commutative: true,
- asm: x86.AVPCMPUQ,
+ name: "VPSHLDDMasked256",
+ auxType: auxInt8,
+ argLen: 3,
+ asm: x86.AVPSHLDD,
reg: regInfo{
inputs: []inputInfo{
{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
- {0, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
},
{
- name: "VPCMPUQ256",
+ name: "VPSHLDDMasked512",
auxType: auxInt8,
- argLen: 2,
- asm: x86.AVPCMPUQ,
+ argLen: 3,
+ asm: x86.AVPSHLDD,
reg: regInfo{
inputs: []inputInfo{
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
- {0, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
},
{
- name: "VPCMPUQMasked512",
- auxType: auxInt8,
- argLen: 3,
- commutative: true,
- asm: x86.AVPCMPUQ,
+ name: "VPSHLDQMasked128",
+ auxType: auxInt8,
+ argLen: 3,
+ asm: x86.AVPSHLDQ,
reg: regInfo{
inputs: []inputInfo{
{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
- {0, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
},
{
- name: "VPCMPUQ512",
+ name: "VPSHLDQMasked256",
auxType: auxInt8,
- argLen: 2,
- asm: x86.AVPCMPUQ,
+ argLen: 3,
+ asm: x86.AVPSHLDQ,
reg: regInfo{
inputs: []inputInfo{
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
- {0, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
},
{
- name: "VPCMPUBMasked128",
- auxType: auxInt8,
- argLen: 3,
- commutative: true,
- asm: x86.AVPCMPUB,
+ name: "VPSHLDQMasked512",
+ auxType: auxInt8,
+ argLen: 3,
+ asm: x86.AVPSHLDQ,
reg: regInfo{
inputs: []inputInfo{
{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
- {0, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
},
{
- name: "VGF2P8AFFINEQB128",
+ name: "VPSHRDW128",
auxType: auxInt8,
argLen: 2,
- asm: x86.AVGF2P8AFFINEQB,
+ asm: x86.AVPSHRDW,
reg: regInfo{
inputs: []inputInfo{
{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
},
},
{
- name: "VGF2P8AFFINEINVQB128",
+ name: "VPSHRDW256",
auxType: auxInt8,
argLen: 2,
- asm: x86.AVGF2P8AFFINEINVQB,
+ asm: x86.AVPSHRDW,
reg: regInfo{
inputs: []inputInfo{
{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
},
},
{
- name: "VGF2P8AFFINEINVQBMasked128",
+ name: "VPSHRDW512",
auxType: auxInt8,
- argLen: 3,
- asm: x86.AVGF2P8AFFINEINVQB,
+ argLen: 2,
+ asm: x86.AVPSHRDW,
reg: regInfo{
inputs: []inputInfo{
- {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ {1, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
},
outputs: []outputInfo{
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
},
},
},
{
- name: "VGF2P8AFFINEQBMasked128",
+ name: "VPSHRDD128",
auxType: auxInt8,
- argLen: 3,
- asm: x86.AVGF2P8AFFINEQB,
+ argLen: 2,
+ asm: x86.AVPSHRDD,
reg: regInfo{
inputs: []inputInfo{
- {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ {1, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
},
outputs: []outputInfo{
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
},
},
},
{
- name: "VPCMPUB128",
+ name: "VPSHRDD256",
auxType: auxInt8,
argLen: 2,
- asm: x86.AVPCMPUB,
+ asm: x86.AVPSHRDD,
reg: regInfo{
inputs: []inputInfo{
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ {1, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
},
outputs: []outputInfo{
- {0, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
},
},
},
{
- name: "VPCMPUBMasked256",
- auxType: auxInt8,
- argLen: 3,
- commutative: true,
- asm: x86.AVPCMPUB,
+ name: "VPSHRDD512",
+ auxType: auxInt8,
+ argLen: 2,
+ asm: x86.AVPSHRDD,
reg: regInfo{
inputs: []inputInfo{
- {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ {1, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
},
outputs: []outputInfo{
- {0, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
},
},
},
{
- name: "VGF2P8AFFINEQB256",
+ name: "VPSHRDQ128",
auxType: auxInt8,
argLen: 2,
- asm: x86.AVGF2P8AFFINEQB,
+ asm: x86.AVPSHRDQ,
reg: regInfo{
inputs: []inputInfo{
{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
},
},
{
- name: "VGF2P8AFFINEINVQB256",
+ name: "VPSHRDQ256",
auxType: auxInt8,
argLen: 2,
- asm: x86.AVGF2P8AFFINEINVQB,
+ asm: x86.AVPSHRDQ,
reg: regInfo{
inputs: []inputInfo{
{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
},
},
{
- name: "VGF2P8AFFINEINVQBMasked256",
+ name: "VPSHRDQ512",
+ auxType: auxInt8,
+ argLen: 2,
+ asm: x86.AVPSHRDQ,
+ reg: regInfo{
+ inputs: []inputInfo{
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ {1, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ },
+ outputs: []outputInfo{
+ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ },
+ },
+ },
+ {
+ name: "VPSHRDWMasked128",
auxType: auxInt8,
argLen: 3,
- asm: x86.AVGF2P8AFFINEINVQB,
+ asm: x86.AVPSHRDW,
reg: regInfo{
inputs: []inputInfo{
{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
},
},
{
- name: "VGF2P8AFFINEQBMasked256",
+ name: "VPSHRDWMasked256",
auxType: auxInt8,
argLen: 3,
- asm: x86.AVGF2P8AFFINEQB,
+ asm: x86.AVPSHRDW,
reg: regInfo{
inputs: []inputInfo{
{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
},
},
{
- name: "VPCMPUB256",
+ name: "VPSHRDWMasked512",
auxType: auxInt8,
- argLen: 2,
- asm: x86.AVPCMPUB,
+ argLen: 3,
+ asm: x86.AVPSHRDW,
reg: regInfo{
inputs: []inputInfo{
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
- {0, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
},
{
- name: "VPCMPUBMasked512",
- auxType: auxInt8,
- argLen: 3,
- commutative: true,
- asm: x86.AVPCMPUB,
+ name: "VPSHRDDMasked128",
+ auxType: auxInt8,
+ argLen: 3,
+ asm: x86.AVPSHRDD,
reg: regInfo{
inputs: []inputInfo{
{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
- {0, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
},
{
- name: "VGF2P8AFFINEQB512",
+ name: "VPSHRDDMasked256",
auxType: auxInt8,
- argLen: 2,
- asm: x86.AVGF2P8AFFINEQB,
+ argLen: 3,
+ asm: x86.AVPSHRDD,
reg: regInfo{
inputs: []inputInfo{
- {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
- {1, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
- {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
},
{
- name: "VGF2P8AFFINEINVQB512",
+ name: "VPSHRDDMasked512",
auxType: auxInt8,
- argLen: 2,
- asm: x86.AVGF2P8AFFINEINVQB,
+ argLen: 3,
+ asm: x86.AVPSHRDD,
reg: regInfo{
inputs: []inputInfo{
- {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
- {1, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
- {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
},
{
- name: "VGF2P8AFFINEINVQBMasked512",
+ name: "VPSHRDQMasked128",
auxType: auxInt8,
argLen: 3,
- asm: x86.AVGF2P8AFFINEINVQB,
+ asm: x86.AVPSHRDQ,
reg: regInfo{
inputs: []inputInfo{
{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
},
},
{
- name: "VGF2P8AFFINEQBMasked512",
+ name: "VPSHRDQMasked256",
auxType: auxInt8,
argLen: 3,
- asm: x86.AVGF2P8AFFINEQB,
+ asm: x86.AVPSHRDQ,
reg: regInfo{
inputs: []inputInfo{
{2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
},
},
{
- name: "VPCMPUB512",
+ name: "VPSHRDQMasked512",
auxType: auxInt8,
- argLen: 2,
- asm: x86.AVPCMPUB,
+ argLen: 3,
+ asm: x86.AVPSHRDQ,
reg: regInfo{
inputs: []inputInfo{
- {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
- {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+ {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
outputs: []outputInfo{
- {0, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
+ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
},
generic: true,
},
{
- name: "AtomicOr8value",
- argLen: 3,
- hasSideEffects: true,
- generic: true,
+ name: "AtomicOr8value",
+ argLen: 3,
+ hasSideEffects: true,
+ generic: true,
+ },
+ {
+ name: "AtomicStore8Variant",
+ argLen: 3,
+ hasSideEffects: true,
+ generic: true,
+ },
+ {
+ name: "AtomicStore32Variant",
+ argLen: 3,
+ hasSideEffects: true,
+ generic: true,
+ },
+ {
+ name: "AtomicStore64Variant",
+ argLen: 3,
+ hasSideEffects: true,
+ generic: true,
+ },
+ {
+ name: "AtomicAdd32Variant",
+ argLen: 3,
+ hasSideEffects: true,
+ generic: true,
+ },
+ {
+ name: "AtomicAdd64Variant",
+ argLen: 3,
+ hasSideEffects: true,
+ generic: true,
+ },
+ {
+ name: "AtomicExchange8Variant",
+ argLen: 3,
+ hasSideEffects: true,
+ generic: true,
+ },
+ {
+ name: "AtomicExchange32Variant",
+ argLen: 3,
+ hasSideEffects: true,
+ generic: true,
+ },
+ {
+ name: "AtomicExchange64Variant",
+ argLen: 3,
+ hasSideEffects: true,
+ generic: true,
+ },
+ {
+ name: "AtomicCompareAndSwap32Variant",
+ argLen: 4,
+ hasSideEffects: true,
+ generic: true,
+ },
+ {
+ name: "AtomicCompareAndSwap64Variant",
+ argLen: 4,
+ hasSideEffects: true,
+ generic: true,
+ },
+ {
+ name: "AtomicAnd64valueVariant",
+ argLen: 3,
+ hasSideEffects: true,
+ generic: true,
+ },
+ {
+ name: "AtomicOr64valueVariant",
+ argLen: 3,
+ hasSideEffects: true,
+ generic: true,
+ },
+ {
+ name: "AtomicAnd32valueVariant",
+ argLen: 3,
+ hasSideEffects: true,
+ generic: true,
+ },
+ {
+ name: "AtomicOr32valueVariant",
+ argLen: 3,
+ hasSideEffects: true,
+ generic: true,
+ },
+ {
+ name: "AtomicAnd8valueVariant",
+ argLen: 3,
+ hasSideEffects: true,
+ generic: true,
+ },
+ {
+ name: "AtomicOr8valueVariant",
+ argLen: 3,
+ hasSideEffects: true,
+ generic: true,
+ },
+ {
+ name: "PubBarrier",
+ argLen: 1,
+ hasSideEffects: true,
+ generic: true,
+ },
+ {
+ name: "Clobber",
+ auxType: auxSymOff,
+ argLen: 0,
+ symEffect: SymNone,
+ generic: true,
+ },
+ {
+ name: "ClobberReg",
+ argLen: 0,
+ generic: true,
+ },
+ {
+ name: "PrefetchCache",
+ argLen: 2,
+ hasSideEffects: true,
+ generic: true,
+ },
+ {
+ name: "PrefetchCacheStreamed",
+ argLen: 2,
+ hasSideEffects: true,
+ generic: true,
+ },
+ {
+ name: "Add32x4",
+ argLen: 2,
+ generic: true,
+ },
+ {
+ name: "ZeroSIMD",
+ argLen: 0,
+ generic: true,
+ },
+ {
+ name: "LoadMask8x16",
+ argLen: 2,
+ generic: true,
+ },
+ {
+ name: "LoadMask8x32",
+ argLen: 2,
+ generic: true,
+ },
+ {
+ name: "LoadMask8x64",
+ argLen: 2,
+ generic: true,
+ },
+ {
+ name: "LoadMask16x8",
+ argLen: 2,
+ generic: true,
+ },
+ {
+ name: "LoadMask16x16",
+ argLen: 2,
+ generic: true,
+ },
+ {
+ name: "LoadMask16x32",
+ argLen: 2,
+ generic: true,
+ },
+ {
+ name: "LoadMask32x4",
+ argLen: 2,
+ generic: true,
+ },
+ {
+ name: "LoadMask32x8",
+ argLen: 2,
+ generic: true,
+ },
+ {
+ name: "LoadMask32x16",
+ argLen: 2,
+ generic: true,
+ },
+ {
+ name: "LoadMask64x2",
+ argLen: 2,
+ generic: true,
+ },
+ {
+ name: "LoadMask64x4",
+ argLen: 2,
+ generic: true,
+ },
+ {
+ name: "LoadMask64x8",
+ argLen: 2,
+ generic: true,
+ },
+ {
+ name: "StoreMask8x16",
+ auxType: auxTyp,
+ argLen: 3,
+ generic: true,
+ },
+ {
+ name: "StoreMask8x32",
+ auxType: auxTyp,
+ argLen: 3,
+ generic: true,
+ },
+ {
+ name: "StoreMask8x64",
+ auxType: auxTyp,
+ argLen: 3,
+ generic: true,
+ },
+ {
+ name: "StoreMask16x8",
+ auxType: auxTyp,
+ argLen: 3,
+ generic: true,
+ },
+ {
+ name: "StoreMask16x16",
+ auxType: auxTyp,
+ argLen: 3,
+ generic: true,
+ },
+ {
+ name: "StoreMask16x32",
+ auxType: auxTyp,
+ argLen: 3,
+ generic: true,
+ },
+ {
+ name: "StoreMask32x4",
+ auxType: auxTyp,
+ argLen: 3,
+ generic: true,
+ },
+ {
+ name: "StoreMask32x8",
+ auxType: auxTyp,
+ argLen: 3,
+ generic: true,
+ },
+ {
+ name: "StoreMask32x16",
+ auxType: auxTyp,
+ argLen: 3,
+ generic: true,
+ },
+ {
+ name: "StoreMask64x2",
+ auxType: auxTyp,
+ argLen: 3,
+ generic: true,
+ },
+ {
+ name: "StoreMask64x4",
+ auxType: auxTyp,
+ argLen: 3,
+ generic: true,
+ },
+ {
+ name: "StoreMask64x8",
+ auxType: auxTyp,
+ argLen: 3,
+ generic: true,
+ },
+ {
+ name: "AbsoluteInt8x16",
+ argLen: 1,
+ generic: true,
+ },
+ {
+ name: "AbsoluteInt8x32",
+ argLen: 1,
+ generic: true,
+ },
+ {
+ name: "AbsoluteInt8x64",
+ argLen: 1,
+ generic: true,
+ },
+ {
+ name: "AbsoluteInt16x8",
+ argLen: 1,
+ generic: true,
+ },
+ {
+ name: "AbsoluteInt16x16",
+ argLen: 1,
+ generic: true,
+ },
+ {
+ name: "AbsoluteInt16x32",
+ argLen: 1,
+ generic: true,
+ },
+ {
+ name: "AbsoluteInt32x4",
+ argLen: 1,
+ generic: true,
+ },
+ {
+ name: "AbsoluteInt32x8",
+ argLen: 1,
+ generic: true,
+ },
+ {
+ name: "AbsoluteInt32x16",
+ argLen: 1,
+ generic: true,
+ },
+ {
+ name: "AbsoluteInt64x2",
+ argLen: 1,
+ generic: true,
+ },
+ {
+ name: "AbsoluteInt64x4",
+ argLen: 1,
+ generic: true,
+ },
+ {
+ name: "AbsoluteInt64x8",
+ argLen: 1,
+ generic: true,
+ },
+ {
+ name: "AbsoluteMaskedInt8x16",
+ argLen: 2,
+ generic: true,
+ },
+ {
+ name: "AbsoluteMaskedInt8x32",
+ argLen: 2,
+ generic: true,
+ },
+ {
+ name: "AbsoluteMaskedInt8x64",
+ argLen: 2,
+ generic: true,
+ },
+ {
+ name: "AbsoluteMaskedInt16x8",
+ argLen: 2,
+ generic: true,
+ },
+ {
+ name: "AbsoluteMaskedInt16x16",
+ argLen: 2,
+ generic: true,
+ },
+ {
+ name: "AbsoluteMaskedInt16x32",
+ argLen: 2,
+ generic: true,
+ },
+ {
+ name: "AbsoluteMaskedInt32x4",
+ argLen: 2,
+ generic: true,
+ },
+ {
+ name: "AbsoluteMaskedInt32x8",
+ argLen: 2,
+ generic: true,
+ },
+ {
+ name: "AbsoluteMaskedInt32x16",
+ argLen: 2,
+ generic: true,
+ },
+ {
+ name: "AbsoluteMaskedInt64x2",
+ argLen: 2,
+ generic: true,
},
{
- name: "AtomicStore8Variant",
- argLen: 3,
- hasSideEffects: true,
- generic: true,
+ name: "AbsoluteMaskedInt64x4",
+ argLen: 2,
+ generic: true,
},
{
- name: "AtomicStore32Variant",
- argLen: 3,
- hasSideEffects: true,
- generic: true,
+ name: "AbsoluteMaskedInt64x8",
+ argLen: 2,
+ generic: true,
},
{
- name: "AtomicStore64Variant",
- argLen: 3,
- hasSideEffects: true,
- generic: true,
+ name: "AddFloat32x4",
+ argLen: 2,
+ commutative: true,
+ generic: true,
},
{
- name: "AtomicAdd32Variant",
- argLen: 3,
- hasSideEffects: true,
- generic: true,
+ name: "AddFloat32x8",
+ argLen: 2,
+ commutative: true,
+ generic: true,
},
{
- name: "AtomicAdd64Variant",
- argLen: 3,
- hasSideEffects: true,
- generic: true,
+ name: "AddFloat32x16",
+ argLen: 2,
+ commutative: true,
+ generic: true,
},
{
- name: "AtomicExchange8Variant",
- argLen: 3,
- hasSideEffects: true,
- generic: true,
+ name: "AddFloat64x2",
+ argLen: 2,
+ commutative: true,
+ generic: true,
},
{
- name: "AtomicExchange32Variant",
- argLen: 3,
- hasSideEffects: true,
- generic: true,
+ name: "AddFloat64x4",
+ argLen: 2,
+ commutative: true,
+ generic: true,
},
{
- name: "AtomicExchange64Variant",
- argLen: 3,
- hasSideEffects: true,
- generic: true,
+ name: "AddFloat64x8",
+ argLen: 2,
+ commutative: true,
+ generic: true,
},
{
- name: "AtomicCompareAndSwap32Variant",
- argLen: 4,
- hasSideEffects: true,
- generic: true,
+ name: "AddInt8x16",
+ argLen: 2,
+ commutative: true,
+ generic: true,
},
{
- name: "AtomicCompareAndSwap64Variant",
- argLen: 4,
- hasSideEffects: true,
- generic: true,
+ name: "AddInt8x32",
+ argLen: 2,
+ commutative: true,
+ generic: true,
},
{
- name: "AtomicAnd64valueVariant",
- argLen: 3,
- hasSideEffects: true,
- generic: true,
+ name: "AddInt8x64",
+ argLen: 2,
+ commutative: true,
+ generic: true,
},
{
- name: "AtomicOr64valueVariant",
- argLen: 3,
- hasSideEffects: true,
- generic: true,
+ name: "AddInt16x8",
+ argLen: 2,
+ commutative: true,
+ generic: true,
},
{
- name: "AtomicAnd32valueVariant",
- argLen: 3,
- hasSideEffects: true,
- generic: true,
+ name: "AddInt16x16",
+ argLen: 2,
+ commutative: true,
+ generic: true,
},
{
- name: "AtomicOr32valueVariant",
- argLen: 3,
- hasSideEffects: true,
- generic: true,
+ name: "AddInt16x32",
+ argLen: 2,
+ commutative: true,
+ generic: true,
},
{
- name: "AtomicAnd8valueVariant",
- argLen: 3,
- hasSideEffects: true,
- generic: true,
+ name: "AddInt32x4",
+ argLen: 2,
+ commutative: true,
+ generic: true,
},
{
- name: "AtomicOr8valueVariant",
- argLen: 3,
- hasSideEffects: true,
- generic: true,
+ name: "AddInt32x8",
+ argLen: 2,
+ commutative: true,
+ generic: true,
},
{
- name: "PubBarrier",
- argLen: 1,
- hasSideEffects: true,
- generic: true,
+ name: "AddInt32x16",
+ argLen: 2,
+ commutative: true,
+ generic: true,
},
{
- name: "Clobber",
- auxType: auxSymOff,
- argLen: 0,
- symEffect: SymNone,
- generic: true,
+ name: "AddInt64x2",
+ argLen: 2,
+ commutative: true,
+ generic: true,
},
{
- name: "ClobberReg",
- argLen: 0,
- generic: true,
+ name: "AddInt64x4",
+ argLen: 2,
+ commutative: true,
+ generic: true,
},
{
- name: "PrefetchCache",
- argLen: 2,
- hasSideEffects: true,
- generic: true,
+ name: "AddInt64x8",
+ argLen: 2,
+ commutative: true,
+ generic: true,
},
{
- name: "PrefetchCacheStreamed",
- argLen: 2,
- hasSideEffects: true,
- generic: true,
+ name: "AddMaskedFloat32x4",
+ argLen: 3,
+ commutative: true,
+ generic: true,
},
{
- name: "Add32x4",
- argLen: 2,
- generic: true,
+ name: "AddMaskedFloat32x8",
+ argLen: 3,
+ commutative: true,
+ generic: true,
},
{
- name: "ZeroSIMD",
- argLen: 0,
- generic: true,
+ name: "AddMaskedFloat32x16",
+ argLen: 3,
+ commutative: true,
+ generic: true,
},
{
- name: "LoadMask8x16",
- argLen: 2,
- generic: true,
+ name: "AddMaskedFloat64x2",
+ argLen: 3,
+ commutative: true,
+ generic: true,
},
{
- name: "LoadMask8x32",
- argLen: 2,
- generic: true,
+ name: "AddMaskedFloat64x4",
+ argLen: 3,
+ commutative: true,
+ generic: true,
},
{
- name: "LoadMask8x64",
- argLen: 2,
- generic: true,
+ name: "AddMaskedFloat64x8",
+ argLen: 3,
+ commutative: true,
+ generic: true,
},
{
- name: "LoadMask16x8",
- argLen: 2,
- generic: true,
+ name: "AddMaskedInt8x16",
+ argLen: 3,
+ commutative: true,
+ generic: true,
},
{
- name: "LoadMask16x16",
- argLen: 2,
- generic: true,
+ name: "AddMaskedInt8x32",
+ argLen: 3,
+ commutative: true,
+ generic: true,
},
{
- name: "LoadMask16x32",
- argLen: 2,
- generic: true,
+ name: "AddMaskedInt8x64",
+ argLen: 3,
+ commutative: true,
+ generic: true,
},
{
- name: "LoadMask32x4",
- argLen: 2,
- generic: true,
+ name: "AddMaskedInt16x8",
+ argLen: 3,
+ commutative: true,
+ generic: true,
},
{
- name: "LoadMask32x8",
- argLen: 2,
- generic: true,
+ name: "AddMaskedInt16x16",
+ argLen: 3,
+ commutative: true,
+ generic: true,
},
{
- name: "LoadMask32x16",
- argLen: 2,
- generic: true,
+ name: "AddMaskedInt16x32",
+ argLen: 3,
+ commutative: true,
+ generic: true,
},
{
- name: "LoadMask64x2",
- argLen: 2,
- generic: true,
+ name: "AddMaskedInt32x4",
+ argLen: 3,
+ commutative: true,
+ generic: true,
},
{
- name: "LoadMask64x4",
- argLen: 2,
- generic: true,
+ name: "AddMaskedInt32x8",
+ argLen: 3,
+ commutative: true,
+ generic: true,
},
{
- name: "LoadMask64x8",
- argLen: 2,
- generic: true,
+ name: "AddMaskedInt32x16",
+ argLen: 3,
+ commutative: true,
+ generic: true,
},
{
- name: "StoreMask8x16",
- auxType: auxTyp,
- argLen: 3,
- generic: true,
+ name: "AddMaskedInt64x2",
+ argLen: 3,
+ commutative: true,
+ generic: true,
},
{
- name: "StoreMask8x32",
- auxType: auxTyp,
- argLen: 3,
- generic: true,
+ name: "AddMaskedInt64x4",
+ argLen: 3,
+ commutative: true,
+ generic: true,
},
{
- name: "StoreMask8x64",
- auxType: auxTyp,
- argLen: 3,
- generic: true,
+ name: "AddMaskedInt64x8",
+ argLen: 3,
+ commutative: true,
+ generic: true,
},
{
- name: "StoreMask16x8",
- auxType: auxTyp,
- argLen: 3,
- generic: true,
+ name: "AddMaskedUint8x16",
+ argLen: 3,
+ commutative: true,
+ generic: true,
},
{
- name: "StoreMask16x16",
- auxType: auxTyp,
- argLen: 3,
- generic: true,
+ name: "AddMaskedUint8x32",
+ argLen: 3,
+ commutative: true,
+ generic: true,
},
{
- name: "StoreMask16x32",
- auxType: auxTyp,
- argLen: 3,
- generic: true,
+ name: "AddMaskedUint8x64",
+ argLen: 3,
+ commutative: true,
+ generic: true,
},
{
- name: "StoreMask32x4",
- auxType: auxTyp,
- argLen: 3,
- generic: true,
+ name: "AddMaskedUint16x8",
+ argLen: 3,
+ commutative: true,
+ generic: true,
},
{
- name: "StoreMask32x8",
- auxType: auxTyp,
- argLen: 3,
- generic: true,
+ name: "AddMaskedUint16x16",
+ argLen: 3,
+ commutative: true,
+ generic: true,
},
{
- name: "StoreMask32x16",
- auxType: auxTyp,
- argLen: 3,
- generic: true,
+ name: "AddMaskedUint16x32",
+ argLen: 3,
+ commutative: true,
+ generic: true,
},
{
- name: "StoreMask64x2",
- auxType: auxTyp,
- argLen: 3,
- generic: true,
+ name: "AddMaskedUint32x4",
+ argLen: 3,
+ commutative: true,
+ generic: true,
},
{
- name: "StoreMask64x4",
- auxType: auxTyp,
- argLen: 3,
- generic: true,
+ name: "AddMaskedUint32x8",
+ argLen: 3,
+ commutative: true,
+ generic: true,
},
{
- name: "StoreMask64x8",
- auxType: auxTyp,
- argLen: 3,
- generic: true,
+ name: "AddMaskedUint32x16",
+ argLen: 3,
+ commutative: true,
+ generic: true,
},
{
- name: "AddFloat32x16",
- argLen: 2,
+ name: "AddMaskedUint64x2",
+ argLen: 3,
commutative: true,
generic: true,
},
{
- name: "AddMaskedFloat32x16",
+ name: "AddMaskedUint64x4",
argLen: 3,
commutative: true,
generic: true,
},
{
- name: "ApproximateReciprocalFloat32x16",
- argLen: 1,
- generic: true,
+ name: "AddMaskedUint64x8",
+ argLen: 3,
+ commutative: true,
+ generic: true,
},
{
- name: "ApproximateReciprocalMaskedFloat32x16",
+ name: "AddSubFloat32x4",
argLen: 2,
generic: true,
},
{
- name: "ApproximateReciprocalOfSqrtFloat32x16",
- argLen: 1,
+ name: "AddSubFloat32x8",
+ argLen: 2,
generic: true,
},
{
- name: "ApproximateReciprocalOfSqrtMaskedFloat32x16",
+ name: "AddSubFloat64x2",
argLen: 2,
generic: true,
},
{
- name: "CompressFloat32x16",
+ name: "AddSubFloat64x4",
argLen: 2,
generic: true,
},
{
- name: "DivFloat32x16",
- argLen: 2,
- generic: true,
+ name: "AddUint8x16",
+ argLen: 2,
+ commutative: true,
+ generic: true,
},
{
- name: "DivMaskedFloat32x16",
- argLen: 3,
- generic: true,
+ name: "AddUint8x32",
+ argLen: 2,
+ commutative: true,
+ generic: true,
},
{
- name: "EqualFloat32x16",
+ name: "AddUint8x64",
argLen: 2,
commutative: true,
generic: true,
},
{
- name: "EqualMaskedFloat32x16",
- argLen: 3,
+ name: "AddUint16x8",
+ argLen: 2,
commutative: true,
generic: true,
},
{
- name: "FusedMultiplyAddFloat32x16",
- argLen: 3,
- generic: true,
+ name: "AddUint16x16",
+ argLen: 2,
+ commutative: true,
+ generic: true,
},
{
- name: "FusedMultiplyAddMaskedFloat32x16",
- argLen: 4,
- generic: true,
+ name: "AddUint16x32",
+ argLen: 2,
+ commutative: true,
+ generic: true,
},
{
- name: "FusedMultiplyAddSubFloat32x16",
- argLen: 3,
- generic: true,
+ name: "AddUint32x4",
+ argLen: 2,
+ commutative: true,
+ generic: true,
},
{
- name: "FusedMultiplyAddSubMaskedFloat32x16",
- argLen: 4,
- generic: true,
+ name: "AddUint32x8",
+ argLen: 2,
+ commutative: true,
+ generic: true,
},
{
- name: "FusedMultiplySubAddFloat32x16",
- argLen: 3,
- generic: true,
+ name: "AddUint32x16",
+ argLen: 2,
+ commutative: true,
+ generic: true,
},
{
- name: "FusedMultiplySubAddMaskedFloat32x16",
- argLen: 4,
- generic: true,
+ name: "AddUint64x2",
+ argLen: 2,
+ commutative: true,
+ generic: true,
},
{
- name: "GreaterFloat32x16",
- argLen: 2,
- generic: true,
+ name: "AddUint64x4",
+ argLen: 2,
+ commutative: true,
+ generic: true,
},
{
- name: "GreaterEqualFloat32x16",
- argLen: 2,
- generic: true,
+ name: "AddUint64x8",
+ argLen: 2,
+ commutative: true,
+ generic: true,
},
{
- name: "GreaterEqualMaskedFloat32x16",
- argLen: 3,
- generic: true,
+ name: "AndInt8x16",
+ argLen: 2,
+ commutative: true,
+ generic: true,
},
{
- name: "GreaterMaskedFloat32x16",
- argLen: 3,
- generic: true,
+ name: "AndInt8x32",
+ argLen: 2,
+ commutative: true,
+ generic: true,
},
{
- name: "IsNanFloat32x16",
+ name: "AndInt16x8",
argLen: 2,
commutative: true,
generic: true,
},
{
- name: "IsNanMaskedFloat32x16",
- argLen: 3,
+ name: "AndInt16x16",
+ argLen: 2,
commutative: true,
generic: true,
},
{
- name: "LessFloat32x16",
- argLen: 2,
- generic: true,
+ name: "AndInt32x4",
+ argLen: 2,
+ commutative: true,
+ generic: true,
+ },
+ {
+ name: "AndInt32x8",
+ argLen: 2,
+ commutative: true,
+ generic: true,
+ },
+ {
+ name: "AndInt32x16",
+ argLen: 2,
+ commutative: true,
+ generic: true,
+ },
+ {
+ name: "AndInt64x2",
+ argLen: 2,
+ commutative: true,
+ generic: true,
},
{
- name: "LessEqualFloat32x16",
- argLen: 2,
- generic: true,
+ name: "AndInt64x4",
+ argLen: 2,
+ commutative: true,
+ generic: true,
},
{
- name: "LessEqualMaskedFloat32x16",
- argLen: 3,
- generic: true,
+ name: "AndInt64x8",
+ argLen: 2,
+ commutative: true,
+ generic: true,
},
{
- name: "LessMaskedFloat32x16",
- argLen: 3,
- generic: true,
+ name: "AndMaskedInt32x4",
+ argLen: 3,
+ commutative: true,
+ generic: true,
},
{
- name: "MaxFloat32x16",
- argLen: 2,
+ name: "AndMaskedInt32x8",
+ argLen: 3,
commutative: true,
generic: true,
},
{
- name: "MaxMaskedFloat32x16",
+ name: "AndMaskedInt32x16",
argLen: 3,
commutative: true,
generic: true,
},
{
- name: "MinFloat32x16",
- argLen: 2,
+ name: "AndMaskedInt64x2",
+ argLen: 3,
commutative: true,
generic: true,
},
{
- name: "MinMaskedFloat32x16",
+ name: "AndMaskedInt64x4",
argLen: 3,
commutative: true,
generic: true,
},
{
- name: "MulFloat32x16",
- argLen: 2,
+ name: "AndMaskedInt64x8",
+ argLen: 3,
commutative: true,
generic: true,
},
{
- name: "MulByPowOf2Float32x16",
- argLen: 2,
- generic: true,
+ name: "AndMaskedUint32x4",
+ argLen: 3,
+ commutative: true,
+ generic: true,
},
{
- name: "MulByPowOf2MaskedFloat32x16",
- argLen: 3,
- generic: true,
+ name: "AndMaskedUint32x8",
+ argLen: 3,
+ commutative: true,
+ generic: true,
},
{
- name: "MulMaskedFloat32x16",
+ name: "AndMaskedUint32x16",
argLen: 3,
commutative: true,
generic: true,
},
{
- name: "NotEqualFloat32x16",
- argLen: 2,
+ name: "AndMaskedUint64x2",
+ argLen: 3,
commutative: true,
generic: true,
},
{
- name: "NotEqualMaskedFloat32x16",
+ name: "AndMaskedUint64x4",
argLen: 3,
commutative: true,
generic: true,
},
{
- name: "SqrtFloat32x16",
- argLen: 1,
- generic: true,
+ name: "AndMaskedUint64x8",
+ argLen: 3,
+ commutative: true,
+ generic: true,
},
{
- name: "SqrtMaskedFloat32x16",
+ name: "AndNotInt8x16",
argLen: 2,
generic: true,
},
{
- name: "SubFloat32x16",
+ name: "AndNotInt8x32",
argLen: 2,
generic: true,
},
{
- name: "SubMaskedFloat32x16",
- argLen: 3,
+ name: "AndNotInt16x8",
+ argLen: 2,
generic: true,
},
{
- name: "AddFloat32x4",
- argLen: 2,
- commutative: true,
- generic: true,
- },
- {
- name: "AddMaskedFloat32x4",
- argLen: 3,
- commutative: true,
- generic: true,
- },
- {
- name: "AddSubFloat32x4",
+ name: "AndNotInt16x16",
argLen: 2,
generic: true,
},
{
- name: "ApproximateReciprocalFloat32x4",
- argLen: 1,
+ name: "AndNotInt32x4",
+ argLen: 2,
generic: true,
},
{
- name: "ApproximateReciprocalMaskedFloat32x4",
+ name: "AndNotInt32x8",
argLen: 2,
generic: true,
},
{
- name: "ApproximateReciprocalOfSqrtFloat32x4",
- argLen: 1,
+ name: "AndNotInt32x16",
+ argLen: 2,
generic: true,
},
{
- name: "ApproximateReciprocalOfSqrtMaskedFloat32x4",
+ name: "AndNotInt64x2",
argLen: 2,
generic: true,
},
{
- name: "CeilFloat32x4",
- argLen: 1,
+ name: "AndNotInt64x4",
+ argLen: 2,
generic: true,
},
{
- name: "CompressFloat32x4",
+ name: "AndNotInt64x8",
argLen: 2,
generic: true,
},
{
- name: "DivFloat32x4",
- argLen: 2,
+ name: "AndNotMaskedInt32x4",
+ argLen: 3,
generic: true,
},
{
- name: "DivMaskedFloat32x4",
+ name: "AndNotMaskedInt32x8",
argLen: 3,
generic: true,
},
{
- name: "DotProdBroadcastFloat32x4",
- argLen: 2,
- commutative: true,
- generic: true,
+ name: "AndNotMaskedInt32x16",
+ argLen: 3,
+ generic: true,
},
{
- name: "EqualFloat32x4",
- argLen: 2,
- commutative: true,
- generic: true,
+ name: "AndNotMaskedInt64x2",
+ argLen: 3,
+ generic: true,
},
{
- name: "EqualMaskedFloat32x4",
- argLen: 3,
- commutative: true,
- generic: true,
+ name: "AndNotMaskedInt64x4",
+ argLen: 3,
+ generic: true,
},
{
- name: "FloorFloat32x4",
- argLen: 1,
+ name: "AndNotMaskedInt64x8",
+ argLen: 3,
generic: true,
},
{
- name: "FusedMultiplyAddFloat32x4",
+ name: "AndNotMaskedUint32x4",
argLen: 3,
generic: true,
},
{
- name: "FusedMultiplyAddMaskedFloat32x4",
- argLen: 4,
+ name: "AndNotMaskedUint32x8",
+ argLen: 3,
generic: true,
},
{
- name: "FusedMultiplyAddSubFloat32x4",
+ name: "AndNotMaskedUint32x16",
argLen: 3,
generic: true,
},
{
- name: "FusedMultiplyAddSubMaskedFloat32x4",
- argLen: 4,
+ name: "AndNotMaskedUint64x2",
+ argLen: 3,
generic: true,
},
{
- name: "FusedMultiplySubAddFloat32x4",
+ name: "AndNotMaskedUint64x4",
argLen: 3,
generic: true,
},
{
- name: "FusedMultiplySubAddMaskedFloat32x4",
- argLen: 4,
+ name: "AndNotMaskedUint64x8",
+ argLen: 3,
generic: true,
},
{
- name: "GreaterFloat32x4",
+ name: "AndNotUint8x16",
argLen: 2,
generic: true,
},
{
- name: "GreaterEqualFloat32x4",
+ name: "AndNotUint8x32",
argLen: 2,
generic: true,
},
{
- name: "GreaterEqualMaskedFloat32x4",
- argLen: 3,
+ name: "AndNotUint16x8",
+ argLen: 2,
generic: true,
},
{
- name: "GreaterMaskedFloat32x4",
- argLen: 3,
+ name: "AndNotUint16x16",
+ argLen: 2,
generic: true,
},
{
- name: "IsNanFloat32x4",
- argLen: 2,
- commutative: true,
- generic: true,
+ name: "AndNotUint32x4",
+ argLen: 2,
+ generic: true,
},
{
- name: "IsNanMaskedFloat32x4",
- argLen: 3,
- commutative: true,
- generic: true,
+ name: "AndNotUint32x8",
+ argLen: 2,
+ generic: true,
},
{
- name: "LessFloat32x4",
+ name: "AndNotUint32x16",
argLen: 2,
generic: true,
},
{
- name: "LessEqualFloat32x4",
+ name: "AndNotUint64x2",
argLen: 2,
generic: true,
},
{
- name: "LessEqualMaskedFloat32x4",
- argLen: 3,
+ name: "AndNotUint64x4",
+ argLen: 2,
generic: true,
},
{
- name: "LessMaskedFloat32x4",
- argLen: 3,
+ name: "AndNotUint64x8",
+ argLen: 2,
generic: true,
},
{
- name: "MaxFloat32x4",
+ name: "AndUint8x16",
argLen: 2,
commutative: true,
generic: true,
},
{
- name: "MaxMaskedFloat32x4",
- argLen: 3,
+ name: "AndUint8x32",
+ argLen: 2,
commutative: true,
generic: true,
},
{
- name: "MinFloat32x4",
+ name: "AndUint16x8",
argLen: 2,
commutative: true,
generic: true,
},
{
- name: "MinMaskedFloat32x4",
- argLen: 3,
+ name: "AndUint16x16",
+ argLen: 2,
commutative: true,
generic: true,
},
{
- name: "MulFloat32x4",
+ name: "AndUint32x4",
argLen: 2,
commutative: true,
generic: true,
},
{
- name: "MulByPowOf2Float32x4",
- argLen: 2,
- generic: true,
- },
- {
- name: "MulByPowOf2MaskedFloat32x4",
- argLen: 3,
- generic: true,
- },
- {
- name: "MulMaskedFloat32x4",
- argLen: 3,
+ name: "AndUint32x8",
+ argLen: 2,
commutative: true,
generic: true,
},
{
- name: "NotEqualFloat32x4",
+ name: "AndUint32x16",
argLen: 2,
commutative: true,
generic: true,
},
{
- name: "NotEqualMaskedFloat32x4",
- argLen: 3,
+ name: "AndUint64x2",
+ argLen: 2,
commutative: true,
generic: true,
},
{
- name: "PairwiseAddFloat32x4",
- argLen: 2,
- generic: true,
+ name: "AndUint64x4",
+ argLen: 2,
+ commutative: true,
+ generic: true,
},
{
- name: "PairwiseSubFloat32x4",
- argLen: 2,
- generic: true,
+ name: "AndUint64x8",
+ argLen: 2,
+ commutative: true,
+ generic: true,
},
{
- name: "RoundFloat32x4",
+ name: "ApproximateReciprocalFloat32x4",
argLen: 1,
generic: true,
},
{
- name: "SqrtFloat32x4",
+ name: "ApproximateReciprocalFloat32x8",
argLen: 1,
generic: true,
},
{
- name: "SqrtMaskedFloat32x4",
- argLen: 2,
+ name: "ApproximateReciprocalFloat32x16",
+ argLen: 1,
generic: true,
},
{
- name: "SubFloat32x4",
- argLen: 2,
+ name: "ApproximateReciprocalFloat64x2",
+ argLen: 1,
generic: true,
},
{
- name: "SubMaskedFloat32x4",
- argLen: 3,
+ name: "ApproximateReciprocalFloat64x4",
+ argLen: 1,
generic: true,
},
{
- name: "TruncFloat32x4",
+ name: "ApproximateReciprocalFloat64x8",
argLen: 1,
generic: true,
},
{
- name: "AddFloat32x8",
- argLen: 2,
- commutative: true,
- generic: true,
- },
- {
- name: "AddMaskedFloat32x8",
- argLen: 3,
- commutative: true,
- generic: true,
- },
- {
- name: "AddSubFloat32x8",
+ name: "ApproximateReciprocalMaskedFloat32x4",
argLen: 2,
generic: true,
},
- {
- name: "ApproximateReciprocalFloat32x8",
- argLen: 1,
- generic: true,
- },
{
name: "ApproximateReciprocalMaskedFloat32x8",
argLen: 2,
generic: true,
},
{
- name: "ApproximateReciprocalOfSqrtFloat32x8",
- argLen: 1,
- generic: true,
- },
- {
- name: "ApproximateReciprocalOfSqrtMaskedFloat32x8",
+ name: "ApproximateReciprocalMaskedFloat32x16",
argLen: 2,
generic: true,
},
{
- name: "CeilFloat32x8",
- argLen: 1,
+ name: "ApproximateReciprocalMaskedFloat64x2",
+ argLen: 2,
generic: true,
},
{
- name: "CompressFloat32x8",
+ name: "ApproximateReciprocalMaskedFloat64x4",
argLen: 2,
generic: true,
},
{
- name: "DivFloat32x8",
+ name: "ApproximateReciprocalMaskedFloat64x8",
argLen: 2,
generic: true,
},
{
- name: "DivMaskedFloat32x8",
- argLen: 3,
+ name: "ApproximateReciprocalOfSqrtFloat32x4",
+ argLen: 1,
generic: true,
},
{
- name: "DotProdBroadcastFloat32x8",
- argLen: 2,
- commutative: true,
- generic: true,
- },
- {
- name: "EqualFloat32x8",
- argLen: 2,
- commutative: true,
- generic: true,
- },
- {
- name: "EqualMaskedFloat32x8",
- argLen: 3,
- commutative: true,
- generic: true,
+ name: "ApproximateReciprocalOfSqrtFloat32x8",
+ argLen: 1,
+ generic: true,
},
{
- name: "FloorFloat32x8",
+ name: "ApproximateReciprocalOfSqrtFloat32x16",
argLen: 1,
generic: true,
},
{
- name: "FusedMultiplyAddFloat32x8",
- argLen: 3,
+ name: "ApproximateReciprocalOfSqrtFloat64x2",
+ argLen: 1,
generic: true,
},
{
- name: "FusedMultiplyAddMaskedFloat32x8",
- argLen: 4,
+ name: "ApproximateReciprocalOfSqrtFloat64x4",
+ argLen: 1,
generic: true,
},
{
- name: "FusedMultiplyAddSubFloat32x8",
- argLen: 3,
+ name: "ApproximateReciprocalOfSqrtFloat64x8",
+ argLen: 1,
generic: true,
},
{
- name: "FusedMultiplyAddSubMaskedFloat32x8",
- argLen: 4,
+ name: "ApproximateReciprocalOfSqrtMaskedFloat32x4",
+ argLen: 2,
generic: true,
},
{
- name: "FusedMultiplySubAddFloat32x8",
- argLen: 3,
+ name: "ApproximateReciprocalOfSqrtMaskedFloat32x8",
+ argLen: 2,
generic: true,
},
{
- name: "FusedMultiplySubAddMaskedFloat32x8",
- argLen: 4,
+ name: "ApproximateReciprocalOfSqrtMaskedFloat32x16",
+ argLen: 2,
generic: true,
},
{
- name: "GreaterFloat32x8",
+ name: "ApproximateReciprocalOfSqrtMaskedFloat64x2",
argLen: 2,
generic: true,
},
{
- name: "GreaterEqualFloat32x8",
+ name: "ApproximateReciprocalOfSqrtMaskedFloat64x4",
argLen: 2,
generic: true,
},
{
- name: "GreaterEqualMaskedFloat32x8",
- argLen: 3,
+ name: "ApproximateReciprocalOfSqrtMaskedFloat64x8",
+ argLen: 2,
generic: true,
},
{
- name: "GreaterMaskedFloat32x8",
- argLen: 3,
- generic: true,
+ name: "AverageMaskedUint8x16",
+ argLen: 3,
+ commutative: true,
+ generic: true,
},
{
- name: "IsNanFloat32x8",
- argLen: 2,
+ name: "AverageMaskedUint8x32",
+ argLen: 3,
commutative: true,
generic: true,
},
{
- name: "IsNanMaskedFloat32x8",
+ name: "AverageMaskedUint8x64",
argLen: 3,
commutative: true,
generic: true,
},
{
- name: "LessFloat32x8",
- argLen: 2,
- generic: true,
+ name: "AverageMaskedUint16x8",
+ argLen: 3,
+ commutative: true,
+ generic: true,
},
{
- name: "LessEqualFloat32x8",
- argLen: 2,
- generic: true,
+ name: "AverageMaskedUint16x16",
+ argLen: 3,
+ commutative: true,
+ generic: true,
},
{
- name: "LessEqualMaskedFloat32x8",
- argLen: 3,
- generic: true,
+ name: "AverageMaskedUint16x32",
+ argLen: 3,
+ commutative: true,
+ generic: true,
},
{
- name: "LessMaskedFloat32x8",
- argLen: 3,
- generic: true,
+ name: "AverageUint8x16",
+ argLen: 2,
+ commutative: true,
+ generic: true,
},
{
- name: "MaxFloat32x8",
+ name: "AverageUint8x32",
argLen: 2,
commutative: true,
generic: true,
},
{
- name: "MaxMaskedFloat32x8",
- argLen: 3,
+ name: "AverageUint8x64",
+ argLen: 2,
commutative: true,
generic: true,
},
{
- name: "MinFloat32x8",
+ name: "AverageUint16x8",
argLen: 2,
commutative: true,
generic: true,
},
{
- name: "MinMaskedFloat32x8",
- argLen: 3,
+ name: "AverageUint16x16",
+ argLen: 2,
commutative: true,
generic: true,
},
{
- name: "MulFloat32x8",
+ name: "AverageUint16x32",
argLen: 2,
commutative: true,
generic: true,
},
{
- name: "MulByPowOf2Float32x8",
+ name: "CeilFloat32x4",
+ argLen: 1,
+ generic: true,
+ },
+ {
+ name: "CeilFloat32x8",
+ argLen: 1,
+ generic: true,
+ },
+ {
+ name: "CeilFloat64x2",
+ argLen: 1,
+ generic: true,
+ },
+ {
+ name: "CeilFloat64x4",
+ argLen: 1,
+ generic: true,
+ },
+ {
+ name: "CompressFloat32x4",
argLen: 2,
generic: true,
},
{
- name: "MulByPowOf2MaskedFloat32x8",
- argLen: 3,
+ name: "CompressFloat32x8",
+ argLen: 2,
generic: true,
},
{
- name: "MulMaskedFloat32x8",
- argLen: 3,
- commutative: true,
- generic: true,
+ name: "CompressFloat32x16",
+ argLen: 2,
+ generic: true,
},
{
- name: "NotEqualFloat32x8",
- argLen: 2,
- commutative: true,
- generic: true,
+ name: "CompressFloat64x2",
+ argLen: 2,
+ generic: true,
},
{
- name: "NotEqualMaskedFloat32x8",
- argLen: 3,
- commutative: true,
- generic: true,
+ name: "CompressFloat64x4",
+ argLen: 2,
+ generic: true,
},
{
- name: "PairwiseAddFloat32x8",
+ name: "CompressFloat64x8",
argLen: 2,
generic: true,
},
{
- name: "PairwiseSubFloat32x8",
+ name: "CompressInt8x16",
argLen: 2,
generic: true,
},
{
- name: "RoundFloat32x8",
- argLen: 1,
+ name: "CompressInt8x32",
+ argLen: 2,
generic: true,
},
{
- name: "SqrtFloat32x8",
- argLen: 1,
+ name: "CompressInt8x64",
+ argLen: 2,
generic: true,
},
{
- name: "SqrtMaskedFloat32x8",
+ name: "CompressInt16x8",
argLen: 2,
generic: true,
},
{
- name: "SubFloat32x8",
+ name: "CompressInt16x16",
argLen: 2,
generic: true,
},
{
- name: "SubMaskedFloat32x8",
- argLen: 3,
+ name: "CompressInt16x32",
+ argLen: 2,
generic: true,
},
{
- name: "TruncFloat32x8",
- argLen: 1,
+ name: "CompressInt32x4",
+ argLen: 2,
generic: true,
},
{
- name: "AddFloat64x2",
- argLen: 2,
- commutative: true,
- generic: true,
+ name: "CompressInt32x8",
+ argLen: 2,
+ generic: true,
},
{
- name: "AddMaskedFloat64x2",
- argLen: 3,
- commutative: true,
- generic: true,
+ name: "CompressInt32x16",
+ argLen: 2,
+ generic: true,
},
{
- name: "AddSubFloat64x2",
+ name: "CompressInt64x2",
+ argLen: 2,
+ generic: true,
+ },
+ {
+ name: "CompressInt64x4",
+ argLen: 2,
+ generic: true,
+ },
+ {
+ name: "CompressInt64x8",
+ argLen: 2,
+ generic: true,
+ },
+ {
+ name: "CompressUint8x16",
+ argLen: 2,
+ generic: true,
+ },
+ {
+ name: "CompressUint8x32",
argLen: 2,
generic: true,
},
{
- name: "ApproximateReciprocalFloat64x2",
- argLen: 1,
+ name: "CompressUint8x64",
+ argLen: 2,
generic: true,
},
{
- name: "ApproximateReciprocalMaskedFloat64x2",
+ name: "CompressUint16x8",
argLen: 2,
generic: true,
},
{
- name: "ApproximateReciprocalOfSqrtFloat64x2",
- argLen: 1,
+ name: "CompressUint16x16",
+ argLen: 2,
generic: true,
},
{
- name: "ApproximateReciprocalOfSqrtMaskedFloat64x2",
+ name: "CompressUint16x32",
argLen: 2,
generic: true,
},
{
- name: "CeilFloat64x2",
- argLen: 1,
+ name: "CompressUint32x4",
+ argLen: 2,
generic: true,
},
{
- name: "CompressFloat64x2",
+ name: "CompressUint32x8",
argLen: 2,
generic: true,
},
{
- name: "DivFloat64x2",
+ name: "CompressUint32x16",
argLen: 2,
generic: true,
},
{
- name: "DivMaskedFloat64x2",
- argLen: 3,
+ name: "CompressUint64x2",
+ argLen: 2,
generic: true,
},
{
- name: "DotProdBroadcastFloat64x2",
- argLen: 2,
- commutative: true,
- generic: true,
+ name: "CompressUint64x4",
+ argLen: 2,
+ generic: true,
},
{
- name: "EqualFloat64x2",
- argLen: 2,
- commutative: true,
- generic: true,
+ name: "CompressUint64x8",
+ argLen: 2,
+ generic: true,
},
{
- name: "EqualMaskedFloat64x2",
- argLen: 3,
- commutative: true,
- generic: true,
+ name: "DivFloat32x4",
+ argLen: 2,
+ generic: true,
},
{
- name: "FloorFloat64x2",
- argLen: 1,
+ name: "DivFloat32x8",
+ argLen: 2,
generic: true,
},
{
- name: "FusedMultiplyAddFloat64x2",
- argLen: 3,
+ name: "DivFloat32x16",
+ argLen: 2,
generic: true,
},
{
- name: "FusedMultiplyAddMaskedFloat64x2",
- argLen: 4,
+ name: "DivFloat64x2",
+ argLen: 2,
generic: true,
},
{
- name: "FusedMultiplyAddSubFloat64x2",
- argLen: 3,
+ name: "DivFloat64x4",
+ argLen: 2,
generic: true,
},
{
- name: "FusedMultiplyAddSubMaskedFloat64x2",
- argLen: 4,
+ name: "DivFloat64x8",
+ argLen: 2,
generic: true,
},
{
- name: "FusedMultiplySubAddFloat64x2",
+ name: "DivMaskedFloat32x4",
argLen: 3,
generic: true,
},
{
- name: "FusedMultiplySubAddMaskedFloat64x2",
- argLen: 4,
+ name: "DivMaskedFloat32x8",
+ argLen: 3,
generic: true,
},
{
- name: "GreaterFloat64x2",
- argLen: 2,
+ name: "DivMaskedFloat32x16",
+ argLen: 3,
generic: true,
},
{
- name: "GreaterEqualFloat64x2",
- argLen: 2,
+ name: "DivMaskedFloat64x2",
+ argLen: 3,
generic: true,
},
{
- name: "GreaterEqualMaskedFloat64x2",
+ name: "DivMaskedFloat64x4",
argLen: 3,
generic: true,
},
{
- name: "GreaterMaskedFloat64x2",
+ name: "DivMaskedFloat64x8",
argLen: 3,
generic: true,
},
{
- name: "IsNanFloat64x2",
+ name: "DotProdBroadcastFloat32x4",
argLen: 2,
commutative: true,
generic: true,
},
{
- name: "IsNanMaskedFloat64x2",
- argLen: 3,
+ name: "DotProdBroadcastFloat32x8",
+ argLen: 2,
commutative: true,
generic: true,
},
{
- name: "LessFloat64x2",
- argLen: 2,
- generic: true,
- },
- {
- name: "LessEqualFloat64x2",
- argLen: 2,
- generic: true,
+ name: "DotProdBroadcastFloat64x2",
+ argLen: 2,
+ commutative: true,
+ generic: true,
},
{
- name: "LessEqualMaskedFloat64x2",
- argLen: 3,
- generic: true,
+ name: "EqualFloat32x4",
+ argLen: 2,
+ commutative: true,
+ generic: true,
},
{
- name: "LessMaskedFloat64x2",
- argLen: 3,
- generic: true,
+ name: "EqualFloat32x8",
+ argLen: 2,
+ commutative: true,
+ generic: true,
},
{
- name: "MaxFloat64x2",
+ name: "EqualFloat32x16",
argLen: 2,
commutative: true,
generic: true,
},
{
- name: "MaxMaskedFloat64x2",
- argLen: 3,
+ name: "EqualFloat64x2",
+ argLen: 2,
commutative: true,
generic: true,
},
{
- name: "MinFloat64x2",
+ name: "EqualFloat64x4",
argLen: 2,
commutative: true,
generic: true,
},
{
- name: "MinMaskedFloat64x2",
- argLen: 3,
+ name: "EqualFloat64x8",
+ argLen: 2,
commutative: true,
generic: true,
},
{
- name: "MulFloat64x2",
+ name: "EqualInt8x16",
argLen: 2,
commutative: true,
generic: true,
},
{
- name: "MulByPowOf2Float64x2",
- argLen: 2,
- generic: true,
+ name: "EqualInt8x32",
+ argLen: 2,
+ commutative: true,
+ generic: true,
},
{
- name: "MulByPowOf2MaskedFloat64x2",
- argLen: 3,
- generic: true,
+ name: "EqualInt8x64",
+ argLen: 2,
+ commutative: true,
+ generic: true,
},
{
- name: "MulMaskedFloat64x2",
- argLen: 3,
+ name: "EqualInt16x8",
+ argLen: 2,
commutative: true,
generic: true,
},
{
- name: "NotEqualFloat64x2",
+ name: "EqualInt16x16",
argLen: 2,
commutative: true,
generic: true,
},
{
- name: "NotEqualMaskedFloat64x2",
- argLen: 3,
+ name: "EqualInt16x32",
+ argLen: 2,
commutative: true,
generic: true,
},
{
- name: "PairwiseAddFloat64x2",
- argLen: 2,
- generic: true,
+ name: "EqualInt32x4",
+ argLen: 2,
+ commutative: true,
+ generic: true,
},
{
- name: "PairwiseSubFloat64x2",
- argLen: 2,
- generic: true,
+ name: "EqualInt32x8",
+ argLen: 2,
+ commutative: true,
+ generic: true,
},
{
- name: "RoundFloat64x2",
- argLen: 1,
- generic: true,
+ name: "EqualInt32x16",
+ argLen: 2,
+ commutative: true,
+ generic: true,
},
{
- name: "SqrtFloat64x2",
- argLen: 1,
- generic: true,
+ name: "EqualInt64x2",
+ argLen: 2,
+ commutative: true,
+ generic: true,
},
{
- name: "SqrtMaskedFloat64x2",
- argLen: 2,
- generic: true,
+ name: "EqualInt64x4",
+ argLen: 2,
+ commutative: true,
+ generic: true,
},
{
- name: "SubFloat64x2",
- argLen: 2,
- generic: true,
+ name: "EqualInt64x8",
+ argLen: 2,
+ commutative: true,
+ generic: true,
},
{
- name: "SubMaskedFloat64x2",
- argLen: 3,
- generic: true,
+ name: "EqualMaskedFloat32x4",
+ argLen: 3,
+ commutative: true,
+ generic: true,
},
{
- name: "TruncFloat64x2",
- argLen: 1,
- generic: true,
+ name: "EqualMaskedFloat32x8",
+ argLen: 3,
+ commutative: true,
+ generic: true,
},
{
- name: "AddFloat64x4",
- argLen: 2,
+ name: "EqualMaskedFloat32x16",
+ argLen: 3,
commutative: true,
generic: true,
},
{
- name: "AddMaskedFloat64x4",
+ name: "EqualMaskedFloat64x2",
argLen: 3,
commutative: true,
generic: true,
},
{
- name: "AddSubFloat64x4",
- argLen: 2,
- generic: true,
+ name: "EqualMaskedFloat64x4",
+ argLen: 3,
+ commutative: true,
+ generic: true,
},
{
- name: "ApproximateReciprocalFloat64x4",
- argLen: 1,
- generic: true,
+ name: "EqualMaskedFloat64x8",
+ argLen: 3,
+ commutative: true,
+ generic: true,
},
{
- name: "ApproximateReciprocalMaskedFloat64x4",
- argLen: 2,
- generic: true,
+ name: "EqualMaskedInt8x16",
+ argLen: 3,
+ commutative: true,
+ generic: true,
},
{
- name: "ApproximateReciprocalOfSqrtFloat64x4",
- argLen: 1,
- generic: true,
+ name: "EqualMaskedInt8x32",
+ argLen: 3,
+ commutative: true,
+ generic: true,
},
{
- name: "ApproximateReciprocalOfSqrtMaskedFloat64x4",
- argLen: 2,
- generic: true,
+ name: "EqualMaskedInt8x64",
+ argLen: 3,
+ commutative: true,
+ generic: true,
},
{
- name: "CeilFloat64x4",
- argLen: 1,
- generic: true,
+ name: "EqualMaskedInt16x8",
+ argLen: 3,
+ commutative: true,
+ generic: true,
},
{
- name: "CompressFloat64x4",
- argLen: 2,
- generic: true,
+ name: "EqualMaskedInt16x16",
+ argLen: 3,
+ commutative: true,
+ generic: true,
},
{
- name: "DivFloat64x4",
- argLen: 2,
- generic: true,
+ name: "EqualMaskedInt16x32",
+ argLen: 3,
+ commutative: true,
+ generic: true,
},
{
- name: "DivMaskedFloat64x4",
- argLen: 3,
- generic: true,
+ name: "EqualMaskedInt32x4",
+ argLen: 3,
+ commutative: true,
+ generic: true,
},
{
- name: "EqualFloat64x4",
- argLen: 2,
+ name: "EqualMaskedInt32x8",
+ argLen: 3,
commutative: true,
generic: true,
},
{
- name: "EqualMaskedFloat64x4",
+ name: "EqualMaskedInt32x16",
argLen: 3,
commutative: true,
generic: true,
},
{
- name: "FloorFloat64x4",
- argLen: 1,
- generic: true,
+ name: "EqualMaskedInt64x2",
+ argLen: 3,
+ commutative: true,
+ generic: true,
},
{
- name: "FusedMultiplyAddFloat64x4",
- argLen: 3,
- generic: true,
+ name: "EqualMaskedInt64x4",
+ argLen: 3,
+ commutative: true,
+ generic: true,
},
{
- name: "FusedMultiplyAddMaskedFloat64x4",
- argLen: 4,
- generic: true,
+ name: "EqualMaskedInt64x8",
+ argLen: 3,
+ commutative: true,
+ generic: true,
},
{
- name: "FusedMultiplyAddSubFloat64x4",
- argLen: 3,
- generic: true,
+ name: "EqualMaskedUint8x16",
+ argLen: 3,
+ commutative: true,
+ generic: true,
},
{
- name: "FusedMultiplyAddSubMaskedFloat64x4",
- argLen: 4,
- generic: true,
+ name: "EqualMaskedUint8x32",
+ argLen: 3,
+ commutative: true,
+ generic: true,
},
{
- name: "FusedMultiplySubAddFloat64x4",
- argLen: 3,
- generic: true,
+ name: "EqualMaskedUint8x64",
+ argLen: 3,
+ commutative: true,
+ generic: true,
},
{
- name: "FusedMultiplySubAddMaskedFloat64x4",
- argLen: 4,
- generic: true,
+ name: "EqualMaskedUint16x8",
+ argLen: 3,
+ commutative: true,
+ generic: true,
},
{
- name: "GreaterFloat64x4",
- argLen: 2,
- generic: true,
+ name: "EqualMaskedUint16x16",
+ argLen: 3,
+ commutative: true,
+ generic: true,
},
{
- name: "GreaterEqualFloat64x4",
- argLen: 2,
- generic: true,
+ name: "EqualMaskedUint16x32",
+ argLen: 3,
+ commutative: true,
+ generic: true,
},
{
- name: "GreaterEqualMaskedFloat64x4",
- argLen: 3,
- generic: true,
+ name: "EqualMaskedUint32x4",
+ argLen: 3,
+ commutative: true,
+ generic: true,
},
{
- name: "GreaterMaskedFloat64x4",
- argLen: 3,
- generic: true,
+ name: "EqualMaskedUint32x8",
+ argLen: 3,
+ commutative: true,
+ generic: true,
},
{
- name: "IsNanFloat64x4",
- argLen: 2,
+ name: "EqualMaskedUint32x16",
+ argLen: 3,
commutative: true,
generic: true,
},
{
- name: "IsNanMaskedFloat64x4",
+ name: "EqualMaskedUint64x2",
argLen: 3,
commutative: true,
generic: true,
},
{
- name: "LessFloat64x4",
- argLen: 2,
- generic: true,
+ name: "EqualMaskedUint64x4",
+ argLen: 3,
+ commutative: true,
+ generic: true,
},
{
- name: "LessEqualFloat64x4",
- argLen: 2,
- generic: true,
+ name: "EqualMaskedUint64x8",
+ argLen: 3,
+ commutative: true,
+ generic: true,
},
{
- name: "LessEqualMaskedFloat64x4",
- argLen: 3,
- generic: true,
+ name: "EqualUint8x16",
+ argLen: 2,
+ commutative: true,
+ generic: true,
},
{
- name: "LessMaskedFloat64x4",
- argLen: 3,
- generic: true,
+ name: "EqualUint8x32",
+ argLen: 2,
+ commutative: true,
+ generic: true,
},
{
- name: "MaxFloat64x4",
+ name: "EqualUint8x64",
argLen: 2,
commutative: true,
generic: true,
},
{
- name: "MaxMaskedFloat64x4",
- argLen: 3,
+ name: "EqualUint16x8",
+ argLen: 2,
commutative: true,
generic: true,
},
{
- name: "MinFloat64x4",
+ name: "EqualUint16x16",
argLen: 2,
commutative: true,
generic: true,
},
{
- name: "MinMaskedFloat64x4",
- argLen: 3,
+ name: "EqualUint16x32",
+ argLen: 2,
commutative: true,
generic: true,
},
{
- name: "MulFloat64x4",
+ name: "EqualUint32x4",
argLen: 2,
commutative: true,
generic: true,
},
{
- name: "MulByPowOf2Float64x4",
- argLen: 2,
- generic: true,
+ name: "EqualUint32x8",
+ argLen: 2,
+ commutative: true,
+ generic: true,
},
{
- name: "MulByPowOf2MaskedFloat64x4",
- argLen: 3,
- generic: true,
+ name: "EqualUint32x16",
+ argLen: 2,
+ commutative: true,
+ generic: true,
},
{
- name: "MulMaskedFloat64x4",
- argLen: 3,
+ name: "EqualUint64x2",
+ argLen: 2,
commutative: true,
generic: true,
},
{
- name: "NotEqualFloat64x4",
+ name: "EqualUint64x4",
argLen: 2,
commutative: true,
generic: true,
},
{
- name: "NotEqualMaskedFloat64x4",
- argLen: 3,
+ name: "EqualUint64x8",
+ argLen: 2,
commutative: true,
generic: true,
},
{
- name: "PairwiseAddFloat64x4",
- argLen: 2,
+ name: "FloorFloat32x4",
+ argLen: 1,
generic: true,
},
{
- name: "PairwiseSubFloat64x4",
- argLen: 2,
+ name: "FloorFloat32x8",
+ argLen: 1,
generic: true,
},
{
- name: "RoundFloat64x4",
+ name: "FloorFloat64x2",
argLen: 1,
generic: true,
},
{
- name: "SqrtFloat64x4",
+ name: "FloorFloat64x4",
argLen: 1,
generic: true,
},
{
- name: "SqrtMaskedFloat64x4",
- argLen: 2,
+ name: "FusedMultiplyAddFloat32x4",
+ argLen: 3,
generic: true,
},
{
- name: "SubFloat64x4",
- argLen: 2,
+ name: "FusedMultiplyAddFloat32x8",
+ argLen: 3,
generic: true,
},
{
- name: "SubMaskedFloat64x4",
+ name: "FusedMultiplyAddFloat32x16",
argLen: 3,
generic: true,
},
{
- name: "TruncFloat64x4",
- argLen: 1,
+ name: "FusedMultiplyAddFloat64x2",
+ argLen: 3,
generic: true,
},
{
- name: "AddFloat64x8",
- argLen: 2,
- commutative: true,
- generic: true,
+ name: "FusedMultiplyAddFloat64x4",
+ argLen: 3,
+ generic: true,
},
{
- name: "AddMaskedFloat64x8",
- argLen: 3,
- commutative: true,
- generic: true,
+ name: "FusedMultiplyAddFloat64x8",
+ argLen: 3,
+ generic: true,
},
{
- name: "ApproximateReciprocalFloat64x8",
- argLen: 1,
+ name: "FusedMultiplyAddMaskedFloat32x4",
+ argLen: 4,
generic: true,
},
{
- name: "ApproximateReciprocalMaskedFloat64x8",
- argLen: 2,
+ name: "FusedMultiplyAddMaskedFloat32x8",
+ argLen: 4,
generic: true,
},
{
- name: "ApproximateReciprocalOfSqrtFloat64x8",
- argLen: 1,
+ name: "FusedMultiplyAddMaskedFloat32x16",
+ argLen: 4,
generic: true,
},
{
- name: "ApproximateReciprocalOfSqrtMaskedFloat64x8",
- argLen: 2,
+ name: "FusedMultiplyAddMaskedFloat64x2",
+ argLen: 4,
generic: true,
},
{
- name: "CompressFloat64x8",
- argLen: 2,
+ name: "FusedMultiplyAddMaskedFloat64x4",
+ argLen: 4,
generic: true,
},
{
- name: "DivFloat64x8",
- argLen: 2,
+ name: "FusedMultiplyAddMaskedFloat64x8",
+ argLen: 4,
generic: true,
},
{
- name: "DivMaskedFloat64x8",
+ name: "FusedMultiplyAddSubFloat32x4",
argLen: 3,
generic: true,
},
{
- name: "EqualFloat64x8",
- argLen: 2,
- commutative: true,
- generic: true,
+ name: "FusedMultiplyAddSubFloat32x8",
+ argLen: 3,
+ generic: true,
},
{
- name: "EqualMaskedFloat64x8",
- argLen: 3,
- commutative: true,
- generic: true,
+ name: "FusedMultiplyAddSubFloat32x16",
+ argLen: 3,
+ generic: true,
},
{
- name: "FusedMultiplyAddFloat64x8",
+ name: "FusedMultiplyAddSubFloat64x2",
argLen: 3,
generic: true,
},
{
- name: "FusedMultiplyAddMaskedFloat64x8",
- argLen: 4,
+ name: "FusedMultiplyAddSubFloat64x4",
+ argLen: 3,
generic: true,
},
{
generic: true,
},
{
- name: "FusedMultiplyAddSubMaskedFloat64x8",
+ name: "FusedMultiplyAddSubMaskedFloat32x4",
argLen: 4,
generic: true,
},
{
- name: "FusedMultiplySubAddFloat64x8",
- argLen: 3,
+ name: "FusedMultiplyAddSubMaskedFloat32x8",
+ argLen: 4,
generic: true,
},
{
- name: "FusedMultiplySubAddMaskedFloat64x8",
+ name: "FusedMultiplyAddSubMaskedFloat32x16",
argLen: 4,
generic: true,
},
{
- name: "GreaterFloat64x8",
- argLen: 2,
+ name: "FusedMultiplyAddSubMaskedFloat64x2",
+ argLen: 4,
generic: true,
},
{
- name: "GreaterEqualFloat64x8",
- argLen: 2,
+ name: "FusedMultiplyAddSubMaskedFloat64x4",
+ argLen: 4,
generic: true,
},
{
- name: "GreaterEqualMaskedFloat64x8",
- argLen: 3,
+ name: "FusedMultiplyAddSubMaskedFloat64x8",
+ argLen: 4,
generic: true,
},
{
- name: "GreaterMaskedFloat64x8",
+ name: "FusedMultiplySubAddFloat32x4",
argLen: 3,
generic: true,
},
{
- name: "IsNanFloat64x8",
- argLen: 2,
- commutative: true,
- generic: true,
- },
- {
- name: "IsNanMaskedFloat64x8",
- argLen: 3,
- commutative: true,
- generic: true,
+ name: "FusedMultiplySubAddFloat32x8",
+ argLen: 3,
+ generic: true,
},
{
- name: "LessFloat64x8",
- argLen: 2,
+ name: "FusedMultiplySubAddFloat32x16",
+ argLen: 3,
generic: true,
},
{
- name: "LessEqualFloat64x8",
- argLen: 2,
+ name: "FusedMultiplySubAddFloat64x2",
+ argLen: 3,
generic: true,
},
{
- name: "LessEqualMaskedFloat64x8",
+ name: "FusedMultiplySubAddFloat64x4",
argLen: 3,
generic: true,
},
{
- name: "LessMaskedFloat64x8",
+ name: "FusedMultiplySubAddFloat64x8",
argLen: 3,
generic: true,
},
{
- name: "MaxFloat64x8",
- argLen: 2,
- commutative: true,
- generic: true,
+ name: "FusedMultiplySubAddMaskedFloat32x4",
+ argLen: 4,
+ generic: true,
},
{
- name: "MaxMaskedFloat64x8",
- argLen: 3,
- commutative: true,
- generic: true,
+ name: "FusedMultiplySubAddMaskedFloat32x8",
+ argLen: 4,
+ generic: true,
},
{
- name: "MinFloat64x8",
- argLen: 2,
- commutative: true,
- generic: true,
+ name: "FusedMultiplySubAddMaskedFloat32x16",
+ argLen: 4,
+ generic: true,
},
{
- name: "MinMaskedFloat64x8",
- argLen: 3,
- commutative: true,
- generic: true,
+ name: "FusedMultiplySubAddMaskedFloat64x2",
+ argLen: 4,
+ generic: true,
},
{
- name: "MulFloat64x8",
- argLen: 2,
- commutative: true,
- generic: true,
+ name: "FusedMultiplySubAddMaskedFloat64x4",
+ argLen: 4,
+ generic: true,
},
{
- name: "MulByPowOf2Float64x8",
- argLen: 2,
+ name: "FusedMultiplySubAddMaskedFloat64x8",
+ argLen: 4,
generic: true,
},
{
- name: "MulByPowOf2MaskedFloat64x8",
+ name: "GaloisFieldMulMaskedUint8x16",
argLen: 3,
generic: true,
},
{
- name: "MulMaskedFloat64x8",
- argLen: 3,
- commutative: true,
- generic: true,
+ name: "GaloisFieldMulMaskedUint8x32",
+ argLen: 3,
+ generic: true,
},
{
- name: "NotEqualFloat64x8",
- argLen: 2,
- commutative: true,
- generic: true,
+ name: "GaloisFieldMulMaskedUint8x64",
+ argLen: 3,
+ generic: true,
},
{
- name: "NotEqualMaskedFloat64x8",
- argLen: 3,
- commutative: true,
- generic: true,
+ name: "GaloisFieldMulUint8x16",
+ argLen: 2,
+ generic: true,
},
{
- name: "SqrtFloat64x8",
- argLen: 1,
+ name: "GaloisFieldMulUint8x32",
+ argLen: 2,
generic: true,
},
{
- name: "SqrtMaskedFloat64x8",
+ name: "GaloisFieldMulUint8x64",
argLen: 2,
generic: true,
},
{
- name: "SubFloat64x8",
+ name: "GreaterEqualFloat32x4",
argLen: 2,
generic: true,
},
{
- name: "SubMaskedFloat64x8",
- argLen: 3,
+ name: "GreaterEqualFloat32x8",
+ argLen: 2,
generic: true,
},
{
- name: "AbsoluteInt16x16",
- argLen: 1,
+ name: "GreaterEqualFloat32x16",
+ argLen: 2,
generic: true,
},
{
- name: "AbsoluteMaskedInt16x16",
+ name: "GreaterEqualFloat64x2",
argLen: 2,
generic: true,
},
{
- name: "AddInt16x16",
- argLen: 2,
- commutative: true,
- generic: true,
+ name: "GreaterEqualFloat64x4",
+ argLen: 2,
+ generic: true,
},
{
- name: "AddMaskedInt16x16",
- argLen: 3,
- commutative: true,
- generic: true,
+ name: "GreaterEqualFloat64x8",
+ argLen: 2,
+ generic: true,
},
{
- name: "AndInt16x16",
- argLen: 2,
- commutative: true,
- generic: true,
+ name: "GreaterEqualInt8x16",
+ argLen: 2,
+ generic: true,
},
{
- name: "AndNotInt16x16",
+ name: "GreaterEqualInt8x32",
argLen: 2,
generic: true,
},
{
- name: "CompressInt16x16",
+ name: "GreaterEqualInt8x64",
argLen: 2,
generic: true,
},
{
- name: "EqualInt16x16",
- argLen: 2,
- commutative: true,
- generic: true,
+ name: "GreaterEqualInt16x8",
+ argLen: 2,
+ generic: true,
},
{
- name: "EqualMaskedInt16x16",
- argLen: 3,
- commutative: true,
- generic: true,
+ name: "GreaterEqualInt16x16",
+ argLen: 2,
+ generic: true,
},
{
- name: "GreaterInt16x16",
+ name: "GreaterEqualInt16x32",
argLen: 2,
generic: true,
},
{
- name: "GreaterEqualInt16x16",
+ name: "GreaterEqualInt32x4",
argLen: 2,
generic: true,
},
{
- name: "GreaterEqualMaskedInt16x16",
- argLen: 3,
+ name: "GreaterEqualInt32x8",
+ argLen: 2,
generic: true,
},
{
- name: "GreaterMaskedInt16x16",
- argLen: 3,
+ name: "GreaterEqualInt32x16",
+ argLen: 2,
generic: true,
},
{
- name: "LessInt16x16",
+ name: "GreaterEqualInt64x2",
argLen: 2,
generic: true,
},
{
- name: "LessEqualInt16x16",
+ name: "GreaterEqualInt64x4",
argLen: 2,
generic: true,
},
{
- name: "LessEqualMaskedInt16x16",
- argLen: 3,
+ name: "GreaterEqualInt64x8",
+ argLen: 2,
generic: true,
},
{
- name: "LessMaskedInt16x16",
+ name: "GreaterEqualMaskedFloat32x4",
argLen: 3,
generic: true,
},
{
- name: "MaxInt16x16",
- argLen: 2,
- commutative: true,
- generic: true,
- },
- {
- name: "MaxMaskedInt16x16",
- argLen: 3,
- commutative: true,
- generic: true,
+ name: "GreaterEqualMaskedFloat32x8",
+ argLen: 3,
+ generic: true,
},
{
- name: "MinInt16x16",
- argLen: 2,
- commutative: true,
- generic: true,
+ name: "GreaterEqualMaskedFloat32x16",
+ argLen: 3,
+ generic: true,
},
{
- name: "MinMaskedInt16x16",
- argLen: 3,
- commutative: true,
- generic: true,
+ name: "GreaterEqualMaskedFloat64x2",
+ argLen: 3,
+ generic: true,
},
{
- name: "MulHighInt16x16",
- argLen: 2,
- commutative: true,
- generic: true,
+ name: "GreaterEqualMaskedFloat64x4",
+ argLen: 3,
+ generic: true,
},
{
- name: "MulHighMaskedInt16x16",
- argLen: 3,
- commutative: true,
- generic: true,
+ name: "GreaterEqualMaskedFloat64x8",
+ argLen: 3,
+ generic: true,
},
{
- name: "MulLowInt16x16",
- argLen: 2,
- commutative: true,
- generic: true,
+ name: "GreaterEqualMaskedInt8x16",
+ argLen: 3,
+ generic: true,
},
{
- name: "MulLowMaskedInt16x16",
- argLen: 3,
- commutative: true,
- generic: true,
+ name: "GreaterEqualMaskedInt8x32",
+ argLen: 3,
+ generic: true,
},
{
- name: "NotEqualInt16x16",
- argLen: 2,
- commutative: true,
- generic: true,
+ name: "GreaterEqualMaskedInt8x64",
+ argLen: 3,
+ generic: true,
},
{
- name: "NotEqualMaskedInt16x16",
- argLen: 3,
- commutative: true,
- generic: true,
+ name: "GreaterEqualMaskedInt16x8",
+ argLen: 3,
+ generic: true,
},
{
- name: "OrInt16x16",
- argLen: 2,
- commutative: true,
- generic: true,
+ name: "GreaterEqualMaskedInt16x16",
+ argLen: 3,
+ generic: true,
},
{
- name: "PairDotProdInt16x16",
- argLen: 2,
+ name: "GreaterEqualMaskedInt16x32",
+ argLen: 3,
generic: true,
},
{
- name: "PairDotProdMaskedInt16x16",
+ name: "GreaterEqualMaskedInt32x4",
argLen: 3,
generic: true,
},
{
- name: "PairwiseAddInt16x16",
- argLen: 2,
+ name: "GreaterEqualMaskedInt32x8",
+ argLen: 3,
generic: true,
},
{
- name: "PairwiseSubInt16x16",
- argLen: 2,
+ name: "GreaterEqualMaskedInt32x16",
+ argLen: 3,
generic: true,
},
{
- name: "PopCountInt16x16",
- argLen: 1,
+ name: "GreaterEqualMaskedInt64x2",
+ argLen: 3,
generic: true,
},
{
- name: "PopCountMaskedInt16x16",
- argLen: 2,
+ name: "GreaterEqualMaskedInt64x4",
+ argLen: 3,
generic: true,
},
{
- name: "SaturatedAddInt16x16",
- argLen: 2,
- commutative: true,
- generic: true,
+ name: "GreaterEqualMaskedInt64x8",
+ argLen: 3,
+ generic: true,
},
{
- name: "SaturatedAddMaskedInt16x16",
- argLen: 3,
- commutative: true,
- generic: true,
+ name: "GreaterEqualMaskedUint8x16",
+ argLen: 3,
+ generic: true,
},
{
- name: "SaturatedPairwiseAddInt16x16",
- argLen: 2,
+ name: "GreaterEqualMaskedUint8x32",
+ argLen: 3,
generic: true,
},
{
- name: "SaturatedPairwiseSubInt16x16",
- argLen: 2,
+ name: "GreaterEqualMaskedUint8x64",
+ argLen: 3,
generic: true,
},
{
- name: "SaturatedSubInt16x16",
- argLen: 2,
+ name: "GreaterEqualMaskedUint16x8",
+ argLen: 3,
generic: true,
},
{
- name: "SaturatedSubMaskedInt16x16",
+ name: "GreaterEqualMaskedUint16x16",
argLen: 3,
generic: true,
},
{
- name: "ShiftAllLeftInt16x16",
- argLen: 2,
+ name: "GreaterEqualMaskedUint16x32",
+ argLen: 3,
generic: true,
},
{
- name: "ShiftAllLeftMaskedInt16x16",
+ name: "GreaterEqualMaskedUint32x4",
argLen: 3,
generic: true,
},
{
- name: "ShiftAllRightInt16x16",
- argLen: 2,
+ name: "GreaterEqualMaskedUint32x8",
+ argLen: 3,
generic: true,
},
{
- name: "ShiftAllRightMaskedInt16x16",
+ name: "GreaterEqualMaskedUint32x16",
argLen: 3,
generic: true,
},
{
- name: "ShiftLeftInt16x16",
- argLen: 2,
+ name: "GreaterEqualMaskedUint64x2",
+ argLen: 3,
generic: true,
},
{
- name: "ShiftLeftAndFillUpperFromInt16x16",
+ name: "GreaterEqualMaskedUint64x4",
argLen: 3,
generic: true,
},
{
- name: "ShiftLeftAndFillUpperFromMaskedInt16x16",
- argLen: 4,
+ name: "GreaterEqualMaskedUint64x8",
+ argLen: 3,
generic: true,
},
{
- name: "ShiftLeftMaskedInt16x16",
- argLen: 3,
+ name: "GreaterEqualUint8x16",
+ argLen: 2,
generic: true,
},
{
- name: "ShiftRightInt16x16",
+ name: "GreaterEqualUint8x32",
argLen: 2,
generic: true,
},
{
- name: "ShiftRightAndFillUpperFromInt16x16",
- argLen: 3,
+ name: "GreaterEqualUint8x64",
+ argLen: 2,
generic: true,
},
{
- name: "ShiftRightAndFillUpperFromMaskedInt16x16",
- argLen: 4,
+ name: "GreaterEqualUint16x8",
+ argLen: 2,
generic: true,
},
{
- name: "ShiftRightMaskedInt16x16",
- argLen: 3,
+ name: "GreaterEqualUint16x16",
+ argLen: 2,
generic: true,
},
{
- name: "SignInt16x16",
+ name: "GreaterEqualUint16x32",
argLen: 2,
generic: true,
},
{
- name: "SubInt16x16",
+ name: "GreaterEqualUint32x4",
argLen: 2,
generic: true,
},
{
- name: "SubMaskedInt16x16",
- argLen: 3,
+ name: "GreaterEqualUint32x8",
+ argLen: 2,
generic: true,
},
{
- name: "XorInt16x16",
- argLen: 2,
- commutative: true,
- generic: true,
+ name: "GreaterEqualUint32x16",
+ argLen: 2,
+ generic: true,
},
{
- name: "AbsoluteInt16x32",
- argLen: 1,
+ name: "GreaterEqualUint64x2",
+ argLen: 2,
generic: true,
},
{
- name: "AbsoluteMaskedInt16x32",
+ name: "GreaterEqualUint64x4",
argLen: 2,
generic: true,
},
{
- name: "AddInt16x32",
- argLen: 2,
- commutative: true,
- generic: true,
+ name: "GreaterEqualUint64x8",
+ argLen: 2,
+ generic: true,
},
{
- name: "AddMaskedInt16x32",
- argLen: 3,
- commutative: true,
- generic: true,
+ name: "GreaterFloat32x4",
+ argLen: 2,
+ generic: true,
},
{
- name: "CompressInt16x32",
+ name: "GreaterFloat32x8",
argLen: 2,
generic: true,
},
{
- name: "EqualInt16x32",
- argLen: 2,
- commutative: true,
- generic: true,
+ name: "GreaterFloat32x16",
+ argLen: 2,
+ generic: true,
},
{
- name: "EqualMaskedInt16x32",
- argLen: 3,
- commutative: true,
- generic: true,
+ name: "GreaterFloat64x2",
+ argLen: 2,
+ generic: true,
},
{
- name: "GreaterInt16x32",
+ name: "GreaterFloat64x4",
argLen: 2,
generic: true,
},
{
- name: "GreaterEqualInt16x32",
+ name: "GreaterFloat64x8",
argLen: 2,
generic: true,
},
{
- name: "GreaterEqualMaskedInt16x32",
- argLen: 3,
+ name: "GreaterInt8x16",
+ argLen: 2,
generic: true,
},
{
- name: "GreaterMaskedInt16x32",
- argLen: 3,
+ name: "GreaterInt8x32",
+ argLen: 2,
generic: true,
},
{
- name: "LessInt16x32",
+ name: "GreaterInt8x64",
argLen: 2,
generic: true,
},
{
- name: "LessEqualInt16x32",
+ name: "GreaterInt16x8",
argLen: 2,
generic: true,
},
{
- name: "LessEqualMaskedInt16x32",
- argLen: 3,
+ name: "GreaterInt16x16",
+ argLen: 2,
generic: true,
},
{
- name: "LessMaskedInt16x32",
- argLen: 3,
+ name: "GreaterInt16x32",
+ argLen: 2,
generic: true,
},
{
- name: "MaxInt16x32",
- argLen: 2,
- commutative: true,
- generic: true,
+ name: "GreaterInt32x4",
+ argLen: 2,
+ generic: true,
},
{
- name: "MaxMaskedInt16x32",
- argLen: 3,
- commutative: true,
- generic: true,
+ name: "GreaterInt32x8",
+ argLen: 2,
+ generic: true,
},
{
- name: "MinInt16x32",
- argLen: 2,
- commutative: true,
- generic: true,
+ name: "GreaterInt32x16",
+ argLen: 2,
+ generic: true,
},
{
- name: "MinMaskedInt16x32",
- argLen: 3,
- commutative: true,
- generic: true,
+ name: "GreaterInt64x2",
+ argLen: 2,
+ generic: true,
},
{
- name: "MulHighInt16x32",
- argLen: 2,
- commutative: true,
- generic: true,
+ name: "GreaterInt64x4",
+ argLen: 2,
+ generic: true,
},
{
- name: "MulHighMaskedInt16x32",
- argLen: 3,
- commutative: true,
- generic: true,
+ name: "GreaterInt64x8",
+ argLen: 2,
+ generic: true,
},
{
- name: "MulLowInt16x32",
- argLen: 2,
- commutative: true,
- generic: true,
+ name: "GreaterMaskedFloat32x4",
+ argLen: 3,
+ generic: true,
},
{
- name: "MulLowMaskedInt16x32",
- argLen: 3,
- commutative: true,
- generic: true,
+ name: "GreaterMaskedFloat32x8",
+ argLen: 3,
+ generic: true,
},
{
- name: "NotEqualInt16x32",
- argLen: 2,
- commutative: true,
- generic: true,
+ name: "GreaterMaskedFloat32x16",
+ argLen: 3,
+ generic: true,
},
{
- name: "NotEqualMaskedInt16x32",
- argLen: 3,
- commutative: true,
- generic: true,
+ name: "GreaterMaskedFloat64x2",
+ argLen: 3,
+ generic: true,
},
{
- name: "PairDotProdInt16x32",
- argLen: 2,
+ name: "GreaterMaskedFloat64x4",
+ argLen: 3,
generic: true,
},
{
- name: "PairDotProdMaskedInt16x32",
+ name: "GreaterMaskedFloat64x8",
argLen: 3,
generic: true,
},
{
- name: "PopCountInt16x32",
- argLen: 1,
+ name: "GreaterMaskedInt8x16",
+ argLen: 3,
generic: true,
},
{
- name: "PopCountMaskedInt16x32",
- argLen: 2,
+ name: "GreaterMaskedInt8x32",
+ argLen: 3,
generic: true,
},
{
- name: "SaturatedAddInt16x32",
- argLen: 2,
- commutative: true,
- generic: true,
- },
- {
- name: "SaturatedAddMaskedInt16x32",
- argLen: 3,
- commutative: true,
- generic: true,
+ name: "GreaterMaskedInt8x64",
+ argLen: 3,
+ generic: true,
},
{
- name: "SaturatedSubInt16x32",
- argLen: 2,
+ name: "GreaterMaskedInt16x8",
+ argLen: 3,
generic: true,
},
{
- name: "SaturatedSubMaskedInt16x32",
+ name: "GreaterMaskedInt16x16",
argLen: 3,
generic: true,
},
{
- name: "ShiftAllLeftInt16x32",
- argLen: 2,
+ name: "GreaterMaskedInt16x32",
+ argLen: 3,
generic: true,
},
{
- name: "ShiftAllLeftMaskedInt16x32",
+ name: "GreaterMaskedInt32x4",
argLen: 3,
generic: true,
},
{
- name: "ShiftAllRightInt16x32",
- argLen: 2,
+ name: "GreaterMaskedInt32x8",
+ argLen: 3,
generic: true,
},
{
- name: "ShiftAllRightMaskedInt16x32",
+ name: "GreaterMaskedInt32x16",
argLen: 3,
generic: true,
},
{
- name: "ShiftLeftInt16x32",
- argLen: 2,
+ name: "GreaterMaskedInt64x2",
+ argLen: 3,
generic: true,
},
{
- name: "ShiftLeftAndFillUpperFromInt16x32",
+ name: "GreaterMaskedInt64x4",
argLen: 3,
generic: true,
},
{
- name: "ShiftLeftAndFillUpperFromMaskedInt16x32",
- argLen: 4,
+ name: "GreaterMaskedInt64x8",
+ argLen: 3,
generic: true,
},
{
- name: "ShiftLeftMaskedInt16x32",
+ name: "GreaterMaskedUint8x16",
argLen: 3,
generic: true,
},
{
- name: "ShiftRightInt16x32",
- argLen: 2,
+ name: "GreaterMaskedUint8x32",
+ argLen: 3,
generic: true,
},
{
- name: "ShiftRightAndFillUpperFromInt16x32",
+ name: "GreaterMaskedUint8x64",
argLen: 3,
generic: true,
},
{
- name: "ShiftRightAndFillUpperFromMaskedInt16x32",
- argLen: 4,
+ name: "GreaterMaskedUint16x8",
+ argLen: 3,
generic: true,
},
{
- name: "ShiftRightMaskedInt16x32",
+ name: "GreaterMaskedUint16x16",
argLen: 3,
generic: true,
},
{
- name: "SubInt16x32",
- argLen: 2,
+ name: "GreaterMaskedUint16x32",
+ argLen: 3,
generic: true,
},
{
- name: "SubMaskedInt16x32",
+ name: "GreaterMaskedUint32x4",
argLen: 3,
generic: true,
},
{
- name: "AbsoluteInt16x8",
- argLen: 1,
+ name: "GreaterMaskedUint32x8",
+ argLen: 3,
generic: true,
},
{
- name: "AbsoluteMaskedInt16x8",
- argLen: 2,
+ name: "GreaterMaskedUint32x16",
+ argLen: 3,
generic: true,
},
{
- name: "AddInt16x8",
- argLen: 2,
- commutative: true,
- generic: true,
+ name: "GreaterMaskedUint64x2",
+ argLen: 3,
+ generic: true,
},
{
- name: "AddMaskedInt16x8",
- argLen: 3,
- commutative: true,
- generic: true,
+ name: "GreaterMaskedUint64x4",
+ argLen: 3,
+ generic: true,
},
{
- name: "AndInt16x8",
- argLen: 2,
- commutative: true,
- generic: true,
+ name: "GreaterMaskedUint64x8",
+ argLen: 3,
+ generic: true,
},
{
- name: "AndNotInt16x8",
+ name: "GreaterUint8x16",
argLen: 2,
generic: true,
},
{
- name: "CompressInt16x8",
+ name: "GreaterUint8x32",
argLen: 2,
generic: true,
},
{
- name: "EqualInt16x8",
- argLen: 2,
- commutative: true,
- generic: true,
+ name: "GreaterUint8x64",
+ argLen: 2,
+ generic: true,
},
{
- name: "EqualMaskedInt16x8",
- argLen: 3,
- commutative: true,
- generic: true,
+ name: "GreaterUint16x8",
+ argLen: 2,
+ generic: true,
},
{
- name: "GreaterInt16x8",
+ name: "GreaterUint16x16",
argLen: 2,
generic: true,
},
{
- name: "GreaterEqualInt16x8",
+ name: "GreaterUint16x32",
argLen: 2,
generic: true,
},
{
- name: "GreaterEqualMaskedInt16x8",
- argLen: 3,
+ name: "GreaterUint32x4",
+ argLen: 2,
generic: true,
},
{
- name: "GreaterMaskedInt16x8",
- argLen: 3,
+ name: "GreaterUint32x8",
+ argLen: 2,
generic: true,
},
{
- name: "LessInt16x8",
+ name: "GreaterUint32x16",
argLen: 2,
generic: true,
},
{
- name: "LessEqualInt16x8",
+ name: "GreaterUint64x2",
argLen: 2,
generic: true,
},
{
- name: "LessEqualMaskedInt16x8",
- argLen: 3,
+ name: "GreaterUint64x4",
+ argLen: 2,
generic: true,
},
{
- name: "LessMaskedInt16x8",
- argLen: 3,
+ name: "GreaterUint64x8",
+ argLen: 2,
generic: true,
},
{
- name: "MaxInt16x8",
+ name: "IsNanFloat32x4",
argLen: 2,
commutative: true,
generic: true,
},
{
- name: "MaxMaskedInt16x8",
- argLen: 3,
- commutative: true,
- generic: true,
- },
- {
- name: "MinInt16x8",
+ name: "IsNanFloat32x8",
argLen: 2,
commutative: true,
generic: true,
},
{
- name: "MinMaskedInt16x8",
- argLen: 3,
+ name: "IsNanFloat32x16",
+ argLen: 2,
commutative: true,
generic: true,
},
{
- name: "MulHighInt16x8",
+ name: "IsNanFloat64x2",
argLen: 2,
commutative: true,
generic: true,
},
{
- name: "MulHighMaskedInt16x8",
- argLen: 3,
+ name: "IsNanFloat64x4",
+ argLen: 2,
commutative: true,
generic: true,
},
{
- name: "MulLowInt16x8",
+ name: "IsNanFloat64x8",
argLen: 2,
commutative: true,
generic: true,
},
{
- name: "MulLowMaskedInt16x8",
+ name: "IsNanMaskedFloat32x4",
argLen: 3,
commutative: true,
generic: true,
},
{
- name: "NotEqualInt16x8",
- argLen: 2,
+ name: "IsNanMaskedFloat32x8",
+ argLen: 3,
commutative: true,
generic: true,
},
{
- name: "NotEqualMaskedInt16x8",
+ name: "IsNanMaskedFloat32x16",
argLen: 3,
commutative: true,
generic: true,
},
{
- name: "OrInt16x8",
- argLen: 2,
+ name: "IsNanMaskedFloat64x2",
+ argLen: 3,
commutative: true,
generic: true,
},
{
- name: "PairDotProdInt16x8",
- argLen: 2,
- generic: true,
- },
- {
- name: "PairDotProdMaskedInt16x8",
- argLen: 3,
- generic: true,
- },
- {
- name: "PairwiseAddInt16x8",
- argLen: 2,
- generic: true,
- },
- {
- name: "PairwiseSubInt16x8",
- argLen: 2,
- generic: true,
- },
- {
- name: "PopCountInt16x8",
- argLen: 1,
- generic: true,
- },
- {
- name: "PopCountMaskedInt16x8",
- argLen: 2,
- generic: true,
- },
- {
- name: "SaturatedAddInt16x8",
- argLen: 2,
+ name: "IsNanMaskedFloat64x4",
+ argLen: 3,
commutative: true,
generic: true,
},
{
- name: "SaturatedAddMaskedInt16x8",
+ name: "IsNanMaskedFloat64x8",
argLen: 3,
commutative: true,
generic: true,
},
{
- name: "SaturatedPairwiseAddInt16x8",
+ name: "LessEqualFloat32x4",
argLen: 2,
generic: true,
},
{
- name: "SaturatedPairwiseSubInt16x8",
+ name: "LessEqualFloat32x8",
argLen: 2,
generic: true,
},
{
- name: "SaturatedSubInt16x8",
+ name: "LessEqualFloat32x16",
argLen: 2,
generic: true,
},
{
- name: "SaturatedSubMaskedInt16x8",
- argLen: 3,
- generic: true,
- },
- {
- name: "ShiftAllLeftInt16x8",
+ name: "LessEqualFloat64x2",
argLen: 2,
generic: true,
},
{
- name: "ShiftAllLeftMaskedInt16x8",
- argLen: 3,
- generic: true,
- },
- {
- name: "ShiftAllRightInt16x8",
+ name: "LessEqualFloat64x4",
argLen: 2,
generic: true,
},
{
- name: "ShiftAllRightMaskedInt16x8",
- argLen: 3,
- generic: true,
- },
- {
- name: "ShiftLeftInt16x8",
+ name: "LessEqualFloat64x8",
argLen: 2,
generic: true,
},
{
- name: "ShiftLeftAndFillUpperFromInt16x8",
- argLen: 3,
- generic: true,
- },
- {
- name: "ShiftLeftAndFillUpperFromMaskedInt16x8",
- argLen: 4,
- generic: true,
- },
- {
- name: "ShiftLeftMaskedInt16x8",
- argLen: 3,
- generic: true,
- },
- {
- name: "ShiftRightInt16x8",
+ name: "LessEqualInt8x16",
argLen: 2,
generic: true,
},
{
- name: "ShiftRightAndFillUpperFromInt16x8",
- argLen: 3,
- generic: true,
- },
- {
- name: "ShiftRightAndFillUpperFromMaskedInt16x8",
- argLen: 4,
- generic: true,
- },
- {
- name: "ShiftRightMaskedInt16x8",
- argLen: 3,
+ name: "LessEqualInt8x32",
+ argLen: 2,
generic: true,
},
{
- name: "SignInt16x8",
+ name: "LessEqualInt8x64",
argLen: 2,
generic: true,
},
{
- name: "SubInt16x8",
+ name: "LessEqualInt16x8",
argLen: 2,
generic: true,
},
{
- name: "SubMaskedInt16x8",
- argLen: 3,
+ name: "LessEqualInt16x16",
+ argLen: 2,
generic: true,
},
{
- name: "XorInt16x8",
- argLen: 2,
- commutative: true,
- generic: true,
- },
- {
- name: "AbsoluteInt32x16",
- argLen: 1,
+ name: "LessEqualInt16x32",
+ argLen: 2,
generic: true,
},
{
- name: "AbsoluteMaskedInt32x16",
+ name: "LessEqualInt32x4",
argLen: 2,
generic: true,
},
{
- name: "AddInt32x16",
- argLen: 2,
- commutative: true,
- generic: true,
- },
- {
- name: "AddMaskedInt32x16",
- argLen: 3,
- commutative: true,
- generic: true,
- },
- {
- name: "AndInt32x16",
- argLen: 2,
- commutative: true,
- generic: true,
- },
- {
- name: "AndMaskedInt32x16",
- argLen: 3,
- commutative: true,
- generic: true,
- },
- {
- name: "AndNotInt32x16",
+ name: "LessEqualInt32x8",
argLen: 2,
generic: true,
},
{
- name: "AndNotMaskedInt32x16",
- argLen: 3,
+ name: "LessEqualInt32x16",
+ argLen: 2,
generic: true,
},
{
- name: "CompressInt32x16",
+ name: "LessEqualInt64x2",
argLen: 2,
generic: true,
},
{
- name: "EqualInt32x16",
- argLen: 2,
- commutative: true,
- generic: true,
- },
- {
- name: "EqualMaskedInt32x16",
- argLen: 3,
- commutative: true,
- generic: true,
- },
- {
- name: "GreaterInt32x16",
+ name: "LessEqualInt64x4",
argLen: 2,
generic: true,
},
{
- name: "GreaterEqualInt32x16",
+ name: "LessEqualInt64x8",
argLen: 2,
generic: true,
},
{
- name: "GreaterEqualMaskedInt32x16",
+ name: "LessEqualMaskedFloat32x4",
argLen: 3,
generic: true,
},
{
- name: "GreaterMaskedInt32x16",
+ name: "LessEqualMaskedFloat32x8",
argLen: 3,
generic: true,
},
{
- name: "LessInt32x16",
- argLen: 2,
+ name: "LessEqualMaskedFloat32x16",
+ argLen: 3,
generic: true,
},
{
- name: "LessEqualInt32x16",
- argLen: 2,
+ name: "LessEqualMaskedFloat64x2",
+ argLen: 3,
generic: true,
},
{
- name: "LessEqualMaskedInt32x16",
+ name: "LessEqualMaskedFloat64x4",
argLen: 3,
generic: true,
},
{
- name: "LessMaskedInt32x16",
+ name: "LessEqualMaskedFloat64x8",
argLen: 3,
generic: true,
},
{
- name: "MaxInt32x16",
- argLen: 2,
- commutative: true,
- generic: true,
- },
- {
- name: "MaxMaskedInt32x16",
- argLen: 3,
- commutative: true,
- generic: true,
- },
- {
- name: "MinInt32x16",
- argLen: 2,
- commutative: true,
- generic: true,
- },
- {
- name: "MinMaskedInt32x16",
- argLen: 3,
- commutative: true,
- generic: true,
- },
- {
- name: "MulLowInt32x16",
- argLen: 2,
- commutative: true,
- generic: true,
- },
- {
- name: "MulLowMaskedInt32x16",
- argLen: 3,
- commutative: true,
- generic: true,
- },
- {
- name: "NotEqualInt32x16",
- argLen: 2,
- commutative: true,
- generic: true,
- },
- {
- name: "NotEqualMaskedInt32x16",
- argLen: 3,
- commutative: true,
- generic: true,
- },
- {
- name: "OrInt32x16",
- argLen: 2,
- commutative: true,
- generic: true,
- },
- {
- name: "OrMaskedInt32x16",
- argLen: 3,
- commutative: true,
- generic: true,
- },
- {
- name: "PairDotProdAccumulateInt32x16",
+ name: "LessEqualMaskedInt8x16",
argLen: 3,
generic: true,
},
{
- name: "PairDotProdAccumulateMaskedInt32x16",
- argLen: 4,
+ name: "LessEqualMaskedInt8x32",
+ argLen: 3,
generic: true,
},
{
- name: "PopCountInt32x16",
- argLen: 1,
+ name: "LessEqualMaskedInt8x64",
+ argLen: 3,
generic: true,
},
{
- name: "PopCountMaskedInt32x16",
- argLen: 2,
+ name: "LessEqualMaskedInt16x8",
+ argLen: 3,
generic: true,
},
{
- name: "RotateLeftInt32x16",
- argLen: 2,
+ name: "LessEqualMaskedInt16x16",
+ argLen: 3,
generic: true,
},
{
- name: "RotateLeftMaskedInt32x16",
+ name: "LessEqualMaskedInt16x32",
argLen: 3,
generic: true,
},
{
- name: "RotateRightInt32x16",
- argLen: 2,
+ name: "LessEqualMaskedInt32x4",
+ argLen: 3,
generic: true,
},
{
- name: "RotateRightMaskedInt32x16",
+ name: "LessEqualMaskedInt32x8",
argLen: 3,
generic: true,
},
{
- name: "SaturatedPairDotProdAccumulateInt32x16",
+ name: "LessEqualMaskedInt32x16",
argLen: 3,
generic: true,
},
{
- name: "SaturatedPairDotProdAccumulateMaskedInt32x16",
- argLen: 4,
+ name: "LessEqualMaskedInt64x2",
+ argLen: 3,
generic: true,
},
{
- name: "SaturatedUnsignedSignedQuadDotProdAccumulateInt32x16",
+ name: "LessEqualMaskedInt64x4",
argLen: 3,
generic: true,
},
{
- name: "SaturatedUnsignedSignedQuadDotProdAccumulateMaskedInt32x16",
- argLen: 4,
+ name: "LessEqualMaskedInt64x8",
+ argLen: 3,
generic: true,
},
{
- name: "ShiftAllLeftInt32x16",
- argLen: 2,
+ name: "LessEqualMaskedUint8x16",
+ argLen: 3,
generic: true,
},
{
- name: "ShiftAllLeftMaskedInt32x16",
+ name: "LessEqualMaskedUint8x32",
argLen: 3,
generic: true,
},
{
- name: "ShiftAllRightInt32x16",
- argLen: 2,
+ name: "LessEqualMaskedUint8x64",
+ argLen: 3,
generic: true,
},
{
- name: "ShiftAllRightMaskedInt32x16",
+ name: "LessEqualMaskedUint16x8",
argLen: 3,
generic: true,
},
{
- name: "ShiftLeftInt32x16",
- argLen: 2,
+ name: "LessEqualMaskedUint16x16",
+ argLen: 3,
generic: true,
},
{
- name: "ShiftLeftAndFillUpperFromInt32x16",
+ name: "LessEqualMaskedUint16x32",
argLen: 3,
generic: true,
},
{
- name: "ShiftLeftAndFillUpperFromMaskedInt32x16",
- argLen: 4,
+ name: "LessEqualMaskedUint32x4",
+ argLen: 3,
generic: true,
},
{
- name: "ShiftLeftMaskedInt32x16",
+ name: "LessEqualMaskedUint32x8",
argLen: 3,
generic: true,
},
{
- name: "ShiftRightInt32x16",
- argLen: 2,
+ name: "LessEqualMaskedUint32x16",
+ argLen: 3,
generic: true,
},
{
- name: "ShiftRightAndFillUpperFromInt32x16",
+ name: "LessEqualMaskedUint64x2",
argLen: 3,
generic: true,
},
{
- name: "ShiftRightAndFillUpperFromMaskedInt32x16",
- argLen: 4,
+ name: "LessEqualMaskedUint64x4",
+ argLen: 3,
generic: true,
},
{
- name: "ShiftRightMaskedInt32x16",
+ name: "LessEqualMaskedUint64x8",
argLen: 3,
generic: true,
},
{
- name: "SubInt32x16",
+ name: "LessEqualUint8x16",
argLen: 2,
generic: true,
},
{
- name: "SubMaskedInt32x16",
- argLen: 3,
+ name: "LessEqualUint8x32",
+ argLen: 2,
generic: true,
},
{
- name: "UnsignedSignedQuadDotProdAccumulateInt32x16",
- argLen: 3,
+ name: "LessEqualUint8x64",
+ argLen: 2,
generic: true,
},
{
- name: "UnsignedSignedQuadDotProdAccumulateMaskedInt32x16",
- argLen: 4,
+ name: "LessEqualUint16x8",
+ argLen: 2,
generic: true,
},
{
- name: "XorInt32x16",
- argLen: 2,
- commutative: true,
- generic: true,
+ name: "LessEqualUint16x16",
+ argLen: 2,
+ generic: true,
},
{
- name: "XorMaskedInt32x16",
- argLen: 3,
- commutative: true,
- generic: true,
+ name: "LessEqualUint16x32",
+ argLen: 2,
+ generic: true,
},
{
- name: "AbsoluteInt32x4",
- argLen: 1,
+ name: "LessEqualUint32x4",
+ argLen: 2,
generic: true,
},
{
- name: "AbsoluteMaskedInt32x4",
+ name: "LessEqualUint32x8",
argLen: 2,
generic: true,
},
{
- name: "AddInt32x4",
- argLen: 2,
- commutative: true,
- generic: true,
+ name: "LessEqualUint32x16",
+ argLen: 2,
+ generic: true,
},
{
- name: "AddMaskedInt32x4",
- argLen: 3,
- commutative: true,
- generic: true,
+ name: "LessEqualUint64x2",
+ argLen: 2,
+ generic: true,
},
{
- name: "AndInt32x4",
- argLen: 2,
- commutative: true,
- generic: true,
+ name: "LessEqualUint64x4",
+ argLen: 2,
+ generic: true,
},
{
- name: "AndMaskedInt32x4",
- argLen: 3,
- commutative: true,
- generic: true,
+ name: "LessEqualUint64x8",
+ argLen: 2,
+ generic: true,
},
{
- name: "AndNotInt32x4",
+ name: "LessFloat32x4",
argLen: 2,
generic: true,
},
{
- name: "AndNotMaskedInt32x4",
- argLen: 3,
+ name: "LessFloat32x8",
+ argLen: 2,
generic: true,
},
{
- name: "CompressInt32x4",
+ name: "LessFloat32x16",
argLen: 2,
generic: true,
},
{
- name: "EqualInt32x4",
- argLen: 2,
- commutative: true,
- generic: true,
+ name: "LessFloat64x2",
+ argLen: 2,
+ generic: true,
},
{
- name: "EqualMaskedInt32x4",
- argLen: 3,
- commutative: true,
- generic: true,
+ name: "LessFloat64x4",
+ argLen: 2,
+ generic: true,
},
{
- name: "GreaterInt32x4",
+ name: "LessFloat64x8",
argLen: 2,
generic: true,
},
{
- name: "GreaterEqualInt32x4",
+ name: "LessInt8x16",
argLen: 2,
generic: true,
},
{
- name: "GreaterEqualMaskedInt32x4",
- argLen: 3,
+ name: "LessInt8x32",
+ argLen: 2,
generic: true,
},
{
- name: "GreaterMaskedInt32x4",
- argLen: 3,
+ name: "LessInt8x64",
+ argLen: 2,
generic: true,
},
{
- name: "LessInt32x4",
+ name: "LessInt16x8",
argLen: 2,
generic: true,
},
{
- name: "LessEqualInt32x4",
+ name: "LessInt16x16",
argLen: 2,
generic: true,
},
{
- name: "LessEqualMaskedInt32x4",
- argLen: 3,
+ name: "LessInt16x32",
+ argLen: 2,
generic: true,
},
{
- name: "LessMaskedInt32x4",
- argLen: 3,
+ name: "LessInt32x4",
+ argLen: 2,
generic: true,
},
{
- name: "MaxInt32x4",
- argLen: 2,
- commutative: true,
- generic: true,
+ name: "LessInt32x8",
+ argLen: 2,
+ generic: true,
},
{
- name: "MaxMaskedInt32x4",
- argLen: 3,
- commutative: true,
- generic: true,
+ name: "LessInt32x16",
+ argLen: 2,
+ generic: true,
},
{
- name: "MinInt32x4",
- argLen: 2,
- commutative: true,
- generic: true,
+ name: "LessInt64x2",
+ argLen: 2,
+ generic: true,
},
{
- name: "MinMaskedInt32x4",
- argLen: 3,
- commutative: true,
- generic: true,
+ name: "LessInt64x4",
+ argLen: 2,
+ generic: true,
},
{
- name: "MulEvenWidenInt32x4",
- argLen: 2,
- commutative: true,
- generic: true,
+ name: "LessInt64x8",
+ argLen: 2,
+ generic: true,
},
{
- name: "MulLowInt32x4",
- argLen: 2,
- commutative: true,
- generic: true,
+ name: "LessMaskedFloat32x4",
+ argLen: 3,
+ generic: true,
},
{
- name: "MulLowMaskedInt32x4",
- argLen: 3,
- commutative: true,
- generic: true,
+ name: "LessMaskedFloat32x8",
+ argLen: 3,
+ generic: true,
},
{
- name: "NotEqualInt32x4",
- argLen: 2,
- commutative: true,
- generic: true,
+ name: "LessMaskedFloat32x16",
+ argLen: 3,
+ generic: true,
},
{
- name: "NotEqualMaskedInt32x4",
- argLen: 3,
- commutative: true,
- generic: true,
+ name: "LessMaskedFloat64x2",
+ argLen: 3,
+ generic: true,
},
{
- name: "OrInt32x4",
- argLen: 2,
- commutative: true,
- generic: true,
+ name: "LessMaskedFloat64x4",
+ argLen: 3,
+ generic: true,
},
{
- name: "OrMaskedInt32x4",
- argLen: 3,
- commutative: true,
- generic: true,
+ name: "LessMaskedFloat64x8",
+ argLen: 3,
+ generic: true,
},
{
- name: "PairDotProdAccumulateInt32x4",
+ name: "LessMaskedInt8x16",
argLen: 3,
generic: true,
},
{
- name: "PairDotProdAccumulateMaskedInt32x4",
- argLen: 4,
+ name: "LessMaskedInt8x32",
+ argLen: 3,
generic: true,
},
{
- name: "PairwiseAddInt32x4",
- argLen: 2,
+ name: "LessMaskedInt8x64",
+ argLen: 3,
generic: true,
},
{
- name: "PairwiseSubInt32x4",
- argLen: 2,
+ name: "LessMaskedInt16x8",
+ argLen: 3,
generic: true,
},
{
- name: "PopCountInt32x4",
- argLen: 1,
+ name: "LessMaskedInt16x16",
+ argLen: 3,
generic: true,
},
{
- name: "PopCountMaskedInt32x4",
- argLen: 2,
+ name: "LessMaskedInt16x32",
+ argLen: 3,
generic: true,
},
{
- name: "RotateLeftInt32x4",
- argLen: 2,
+ name: "LessMaskedInt32x4",
+ argLen: 3,
generic: true,
},
{
- name: "RotateLeftMaskedInt32x4",
+ name: "LessMaskedInt32x8",
argLen: 3,
generic: true,
},
{
- name: "RotateRightInt32x4",
- argLen: 2,
+ name: "LessMaskedInt32x16",
+ argLen: 3,
generic: true,
},
{
- name: "RotateRightMaskedInt32x4",
+ name: "LessMaskedInt64x2",
argLen: 3,
generic: true,
},
{
- name: "SaturatedPairDotProdAccumulateInt32x4",
+ name: "LessMaskedInt64x4",
argLen: 3,
generic: true,
},
{
- name: "SaturatedPairDotProdAccumulateMaskedInt32x4",
- argLen: 4,
+ name: "LessMaskedInt64x8",
+ argLen: 3,
generic: true,
},
{
- name: "SaturatedUnsignedSignedQuadDotProdAccumulateInt32x4",
+ name: "LessMaskedUint8x16",
argLen: 3,
generic: true,
},
{
- name: "SaturatedUnsignedSignedQuadDotProdAccumulateMaskedInt32x4",
- argLen: 4,
+ name: "LessMaskedUint8x32",
+ argLen: 3,
generic: true,
},
{
- name: "ShiftAllLeftInt32x4",
- argLen: 2,
+ name: "LessMaskedUint8x64",
+ argLen: 3,
generic: true,
},
{
- name: "ShiftAllLeftMaskedInt32x4",
+ name: "LessMaskedUint16x8",
argLen: 3,
generic: true,
},
{
- name: "ShiftAllRightInt32x4",
- argLen: 2,
+ name: "LessMaskedUint16x16",
+ argLen: 3,
generic: true,
},
{
- name: "ShiftAllRightMaskedInt32x4",
+ name: "LessMaskedUint16x32",
argLen: 3,
generic: true,
},
{
- name: "ShiftLeftInt32x4",
- argLen: 2,
+ name: "LessMaskedUint32x4",
+ argLen: 3,
generic: true,
},
{
- name: "ShiftLeftAndFillUpperFromInt32x4",
+ name: "LessMaskedUint32x8",
argLen: 3,
generic: true,
},
{
- name: "ShiftLeftAndFillUpperFromMaskedInt32x4",
- argLen: 4,
+ name: "LessMaskedUint32x16",
+ argLen: 3,
generic: true,
},
{
- name: "ShiftLeftMaskedInt32x4",
+ name: "LessMaskedUint64x2",
argLen: 3,
generic: true,
},
{
- name: "ShiftRightInt32x4",
- argLen: 2,
+ name: "LessMaskedUint64x4",
+ argLen: 3,
generic: true,
},
{
- name: "ShiftRightAndFillUpperFromInt32x4",
+ name: "LessMaskedUint64x8",
argLen: 3,
generic: true,
},
{
- name: "ShiftRightAndFillUpperFromMaskedInt32x4",
- argLen: 4,
+ name: "LessUint8x16",
+ argLen: 2,
generic: true,
},
{
- name: "ShiftRightMaskedInt32x4",
- argLen: 3,
+ name: "LessUint8x32",
+ argLen: 2,
generic: true,
},
{
- name: "SignInt32x4",
+ name: "LessUint8x64",
argLen: 2,
generic: true,
},
{
- name: "SubInt32x4",
+ name: "LessUint16x8",
argLen: 2,
generic: true,
},
{
- name: "SubMaskedInt32x4",
- argLen: 3,
+ name: "LessUint16x16",
+ argLen: 2,
generic: true,
},
{
- name: "UnsignedSignedQuadDotProdAccumulateInt32x4",
- argLen: 3,
+ name: "LessUint16x32",
+ argLen: 2,
generic: true,
},
{
- name: "UnsignedSignedQuadDotProdAccumulateMaskedInt32x4",
- argLen: 4,
+ name: "LessUint32x4",
+ argLen: 2,
generic: true,
},
{
- name: "XorInt32x4",
- argLen: 2,
- commutative: true,
- generic: true,
+ name: "LessUint32x8",
+ argLen: 2,
+ generic: true,
},
{
- name: "XorMaskedInt32x4",
- argLen: 3,
- commutative: true,
- generic: true,
+ name: "LessUint32x16",
+ argLen: 2,
+ generic: true,
},
{
- name: "AbsoluteInt32x8",
- argLen: 1,
+ name: "LessUint64x2",
+ argLen: 2,
generic: true,
},
{
- name: "AbsoluteMaskedInt32x8",
+ name: "LessUint64x4",
argLen: 2,
generic: true,
},
{
- name: "AddInt32x8",
+ name: "LessUint64x8",
+ argLen: 2,
+ generic: true,
+ },
+ {
+ name: "MaxFloat32x4",
argLen: 2,
commutative: true,
generic: true,
},
{
- name: "AddMaskedInt32x8",
- argLen: 3,
+ name: "MaxFloat32x8",
+ argLen: 2,
commutative: true,
generic: true,
},
{
- name: "AndInt32x8",
+ name: "MaxFloat32x16",
argLen: 2,
commutative: true,
generic: true,
},
{
- name: "AndMaskedInt32x8",
- argLen: 3,
+ name: "MaxFloat64x2",
+ argLen: 2,
commutative: true,
generic: true,
},
{
- name: "AndNotInt32x8",
- argLen: 2,
- generic: true,
+ name: "MaxFloat64x4",
+ argLen: 2,
+ commutative: true,
+ generic: true,
},
{
- name: "AndNotMaskedInt32x8",
- argLen: 3,
- generic: true,
+ name: "MaxFloat64x8",
+ argLen: 2,
+ commutative: true,
+ generic: true,
},
{
- name: "CompressInt32x8",
- argLen: 2,
- generic: true,
+ name: "MaxInt8x16",
+ argLen: 2,
+ commutative: true,
+ generic: true,
},
{
- name: "EqualInt32x8",
+ name: "MaxInt8x32",
argLen: 2,
commutative: true,
generic: true,
},
{
- name: "EqualMaskedInt32x8",
- argLen: 3,
+ name: "MaxInt8x64",
+ argLen: 2,
commutative: true,
generic: true,
},
{
- name: "GreaterInt32x8",
- argLen: 2,
- generic: true,
+ name: "MaxInt16x8",
+ argLen: 2,
+ commutative: true,
+ generic: true,
},
{
- name: "GreaterEqualInt32x8",
- argLen: 2,
- generic: true,
+ name: "MaxInt16x16",
+ argLen: 2,
+ commutative: true,
+ generic: true,
},
{
- name: "GreaterEqualMaskedInt32x8",
- argLen: 3,
- generic: true,
+ name: "MaxInt16x32",
+ argLen: 2,
+ commutative: true,
+ generic: true,
},
{
- name: "GreaterMaskedInt32x8",
- argLen: 3,
- generic: true,
+ name: "MaxInt32x4",
+ argLen: 2,
+ commutative: true,
+ generic: true,
},
{
- name: "LessInt32x8",
- argLen: 2,
- generic: true,
+ name: "MaxInt32x8",
+ argLen: 2,
+ commutative: true,
+ generic: true,
},
{
- name: "LessEqualInt32x8",
- argLen: 2,
- generic: true,
+ name: "MaxInt32x16",
+ argLen: 2,
+ commutative: true,
+ generic: true,
},
{
- name: "LessEqualMaskedInt32x8",
- argLen: 3,
- generic: true,
+ name: "MaxInt64x2",
+ argLen: 2,
+ commutative: true,
+ generic: true,
},
{
- name: "LessMaskedInt32x8",
- argLen: 3,
- generic: true,
+ name: "MaxInt64x4",
+ argLen: 2,
+ commutative: true,
+ generic: true,
},
{
- name: "MaxInt32x8",
+ name: "MaxInt64x8",
argLen: 2,
commutative: true,
generic: true,
},
{
- name: "MaxMaskedInt32x8",
+ name: "MaxMaskedFloat32x4",
argLen: 3,
commutative: true,
generic: true,
},
{
- name: "MinInt32x8",
- argLen: 2,
+ name: "MaxMaskedFloat32x8",
+ argLen: 3,
commutative: true,
generic: true,
},
{
- name: "MinMaskedInt32x8",
+ name: "MaxMaskedFloat32x16",
argLen: 3,
commutative: true,
generic: true,
},
{
- name: "MulEvenWidenInt32x8",
- argLen: 2,
+ name: "MaxMaskedFloat64x2",
+ argLen: 3,
commutative: true,
generic: true,
},
{
- name: "MulLowInt32x8",
- argLen: 2,
+ name: "MaxMaskedFloat64x4",
+ argLen: 3,
commutative: true,
generic: true,
},
{
- name: "MulLowMaskedInt32x8",
+ name: "MaxMaskedFloat64x8",
argLen: 3,
commutative: true,
generic: true,
},
{
- name: "NotEqualInt32x8",
- argLen: 2,
+ name: "MaxMaskedInt8x16",
+ argLen: 3,
commutative: true,
generic: true,
},
{
- name: "NotEqualMaskedInt32x8",
+ name: "MaxMaskedInt8x32",
argLen: 3,
commutative: true,
generic: true,
},
{
- name: "OrInt32x8",
- argLen: 2,
+ name: "MaxMaskedInt8x64",
+ argLen: 3,
commutative: true,
generic: true,
},
{
- name: "OrMaskedInt32x8",
+ name: "MaxMaskedInt16x8",
argLen: 3,
commutative: true,
generic: true,
},
{
- name: "PairDotProdAccumulateInt32x8",
- argLen: 3,
- generic: true,
+ name: "MaxMaskedInt16x16",
+ argLen: 3,
+ commutative: true,
+ generic: true,
},
{
- name: "PairDotProdAccumulateMaskedInt32x8",
- argLen: 4,
- generic: true,
+ name: "MaxMaskedInt16x32",
+ argLen: 3,
+ commutative: true,
+ generic: true,
},
{
- name: "PairwiseAddInt32x8",
- argLen: 2,
- generic: true,
+ name: "MaxMaskedInt32x4",
+ argLen: 3,
+ commutative: true,
+ generic: true,
},
{
- name: "PairwiseSubInt32x8",
- argLen: 2,
- generic: true,
+ name: "MaxMaskedInt32x8",
+ argLen: 3,
+ commutative: true,
+ generic: true,
},
{
- name: "PopCountInt32x8",
- argLen: 1,
- generic: true,
+ name: "MaxMaskedInt32x16",
+ argLen: 3,
+ commutative: true,
+ generic: true,
},
{
- name: "PopCountMaskedInt32x8",
- argLen: 2,
- generic: true,
+ name: "MaxMaskedInt64x2",
+ argLen: 3,
+ commutative: true,
+ generic: true,
},
{
- name: "RotateLeftInt32x8",
- argLen: 2,
- generic: true,
+ name: "MaxMaskedInt64x4",
+ argLen: 3,
+ commutative: true,
+ generic: true,
},
{
- name: "RotateLeftMaskedInt32x8",
- argLen: 3,
- generic: true,
+ name: "MaxMaskedInt64x8",
+ argLen: 3,
+ commutative: true,
+ generic: true,
},
{
- name: "RotateRightInt32x8",
- argLen: 2,
- generic: true,
+ name: "MaxMaskedUint8x16",
+ argLen: 3,
+ commutative: true,
+ generic: true,
},
{
- name: "RotateRightMaskedInt32x8",
- argLen: 3,
- generic: true,
+ name: "MaxMaskedUint8x32",
+ argLen: 3,
+ commutative: true,
+ generic: true,
},
{
- name: "SaturatedPairDotProdAccumulateInt32x8",
- argLen: 3,
- generic: true,
+ name: "MaxMaskedUint8x64",
+ argLen: 3,
+ commutative: true,
+ generic: true,
},
{
- name: "SaturatedPairDotProdAccumulateMaskedInt32x8",
- argLen: 4,
- generic: true,
+ name: "MaxMaskedUint16x8",
+ argLen: 3,
+ commutative: true,
+ generic: true,
},
{
- name: "SaturatedUnsignedSignedQuadDotProdAccumulateInt32x8",
- argLen: 3,
- generic: true,
+ name: "MaxMaskedUint16x16",
+ argLen: 3,
+ commutative: true,
+ generic: true,
},
{
- name: "SaturatedUnsignedSignedQuadDotProdAccumulateMaskedInt32x8",
- argLen: 4,
- generic: true,
+ name: "MaxMaskedUint16x32",
+ argLen: 3,
+ commutative: true,
+ generic: true,
},
{
- name: "ShiftAllLeftInt32x8",
- argLen: 2,
- generic: true,
+ name: "MaxMaskedUint32x4",
+ argLen: 3,
+ commutative: true,
+ generic: true,
},
{
- name: "ShiftAllLeftMaskedInt32x8",
- argLen: 3,
- generic: true,
+ name: "MaxMaskedUint32x8",
+ argLen: 3,
+ commutative: true,
+ generic: true,
},
{
- name: "ShiftAllRightInt32x8",
- argLen: 2,
- generic: true,
+ name: "MaxMaskedUint32x16",
+ argLen: 3,
+ commutative: true,
+ generic: true,
},
{
- name: "ShiftAllRightMaskedInt32x8",
- argLen: 3,
- generic: true,
+ name: "MaxMaskedUint64x2",
+ argLen: 3,
+ commutative: true,
+ generic: true,
},
{
- name: "ShiftLeftInt32x8",
- argLen: 2,
- generic: true,
+ name: "MaxMaskedUint64x4",
+ argLen: 3,
+ commutative: true,
+ generic: true,
},
{
- name: "ShiftLeftAndFillUpperFromInt32x8",
- argLen: 3,
- generic: true,
+ name: "MaxMaskedUint64x8",
+ argLen: 3,
+ commutative: true,
+ generic: true,
},
{
- name: "ShiftLeftAndFillUpperFromMaskedInt32x8",
- argLen: 4,
- generic: true,
+ name: "MaxUint8x16",
+ argLen: 2,
+ commutative: true,
+ generic: true,
},
{
- name: "ShiftLeftMaskedInt32x8",
- argLen: 3,
- generic: true,
+ name: "MaxUint8x32",
+ argLen: 2,
+ commutative: true,
+ generic: true,
},
{
- name: "ShiftRightInt32x8",
- argLen: 2,
- generic: true,
+ name: "MaxUint8x64",
+ argLen: 2,
+ commutative: true,
+ generic: true,
},
{
- name: "ShiftRightAndFillUpperFromInt32x8",
- argLen: 3,
- generic: true,
+ name: "MaxUint16x8",
+ argLen: 2,
+ commutative: true,
+ generic: true,
},
{
- name: "ShiftRightAndFillUpperFromMaskedInt32x8",
- argLen: 4,
- generic: true,
+ name: "MaxUint16x16",
+ argLen: 2,
+ commutative: true,
+ generic: true,
},
{
- name: "ShiftRightMaskedInt32x8",
- argLen: 3,
- generic: true,
+ name: "MaxUint16x32",
+ argLen: 2,
+ commutative: true,
+ generic: true,
},
{
- name: "SignInt32x8",
- argLen: 2,
- generic: true,
+ name: "MaxUint32x4",
+ argLen: 2,
+ commutative: true,
+ generic: true,
},
{
- name: "SubInt32x8",
- argLen: 2,
- generic: true,
+ name: "MaxUint32x8",
+ argLen: 2,
+ commutative: true,
+ generic: true,
},
{
- name: "SubMaskedInt32x8",
- argLen: 3,
- generic: true,
+ name: "MaxUint32x16",
+ argLen: 2,
+ commutative: true,
+ generic: true,
},
{
- name: "UnsignedSignedQuadDotProdAccumulateInt32x8",
- argLen: 3,
- generic: true,
+ name: "MaxUint64x2",
+ argLen: 2,
+ commutative: true,
+ generic: true,
},
{
- name: "UnsignedSignedQuadDotProdAccumulateMaskedInt32x8",
- argLen: 4,
- generic: true,
+ name: "MaxUint64x4",
+ argLen: 2,
+ commutative: true,
+ generic: true,
},
{
- name: "XorInt32x8",
+ name: "MaxUint64x8",
argLen: 2,
commutative: true,
generic: true,
},
{
- name: "XorMaskedInt32x8",
- argLen: 3,
+ name: "MinFloat32x4",
+ argLen: 2,
commutative: true,
generic: true,
},
{
- name: "AbsoluteInt64x2",
- argLen: 1,
- generic: true,
+ name: "MinFloat32x8",
+ argLen: 2,
+ commutative: true,
+ generic: true,
},
{
- name: "AbsoluteMaskedInt64x2",
- argLen: 2,
- generic: true,
+ name: "MinFloat32x16",
+ argLen: 2,
+ commutative: true,
+ generic: true,
},
{
- name: "AddInt64x2",
+ name: "MinFloat64x2",
argLen: 2,
commutative: true,
generic: true,
},
{
- name: "AddMaskedInt64x2",
- argLen: 3,
+ name: "MinFloat64x4",
+ argLen: 2,
commutative: true,
generic: true,
},
{
- name: "AndInt64x2",
+ name: "MinFloat64x8",
argLen: 2,
commutative: true,
generic: true,
},
{
- name: "AndMaskedInt64x2",
- argLen: 3,
+ name: "MinInt8x16",
+ argLen: 2,
commutative: true,
generic: true,
},
{
- name: "AndNotInt64x2",
- argLen: 2,
- generic: true,
+ name: "MinInt8x32",
+ argLen: 2,
+ commutative: true,
+ generic: true,
},
{
- name: "AndNotMaskedInt64x2",
- argLen: 3,
- generic: true,
+ name: "MinInt8x64",
+ argLen: 2,
+ commutative: true,
+ generic: true,
},
{
- name: "CompressInt64x2",
- argLen: 2,
- generic: true,
+ name: "MinInt16x8",
+ argLen: 2,
+ commutative: true,
+ generic: true,
},
{
- name: "EqualInt64x2",
+ name: "MinInt16x16",
argLen: 2,
commutative: true,
generic: true,
},
{
- name: "EqualMaskedInt64x2",
- argLen: 3,
+ name: "MinInt16x32",
+ argLen: 2,
commutative: true,
generic: true,
},
{
- name: "GreaterInt64x2",
- argLen: 2,
- generic: true,
+ name: "MinInt32x4",
+ argLen: 2,
+ commutative: true,
+ generic: true,
},
{
- name: "GreaterEqualInt64x2",
- argLen: 2,
- generic: true,
+ name: "MinInt32x8",
+ argLen: 2,
+ commutative: true,
+ generic: true,
},
{
- name: "GreaterEqualMaskedInt64x2",
- argLen: 3,
- generic: true,
+ name: "MinInt32x16",
+ argLen: 2,
+ commutative: true,
+ generic: true,
},
{
- name: "GreaterMaskedInt64x2",
- argLen: 3,
- generic: true,
+ name: "MinInt64x2",
+ argLen: 2,
+ commutative: true,
+ generic: true,
},
{
- name: "LessInt64x2",
- argLen: 2,
- generic: true,
+ name: "MinInt64x4",
+ argLen: 2,
+ commutative: true,
+ generic: true,
},
{
- name: "LessEqualInt64x2",
- argLen: 2,
- generic: true,
+ name: "MinInt64x8",
+ argLen: 2,
+ commutative: true,
+ generic: true,
},
{
- name: "LessEqualMaskedInt64x2",
- argLen: 3,
- generic: true,
+ name: "MinMaskedFloat32x4",
+ argLen: 3,
+ commutative: true,
+ generic: true,
},
{
- name: "LessMaskedInt64x2",
- argLen: 3,
- generic: true,
+ name: "MinMaskedFloat32x8",
+ argLen: 3,
+ commutative: true,
+ generic: true,
},
{
- name: "MaxInt64x2",
- argLen: 2,
+ name: "MinMaskedFloat32x16",
+ argLen: 3,
commutative: true,
generic: true,
},
{
- name: "MaxMaskedInt64x2",
+ name: "MinMaskedFloat64x2",
argLen: 3,
commutative: true,
generic: true,
},
{
- name: "MinInt64x2",
- argLen: 2,
+ name: "MinMaskedFloat64x4",
+ argLen: 3,
commutative: true,
generic: true,
},
{
- name: "MinMaskedInt64x2",
+ name: "MinMaskedFloat64x8",
argLen: 3,
commutative: true,
generic: true,
},
{
- name: "MulEvenWidenInt64x2",
- argLen: 2,
+ name: "MinMaskedInt8x16",
+ argLen: 3,
commutative: true,
generic: true,
},
{
- name: "MulEvenWidenMaskedInt64x2",
+ name: "MinMaskedInt8x32",
argLen: 3,
commutative: true,
generic: true,
},
{
- name: "MulLowInt64x2",
- argLen: 2,
+ name: "MinMaskedInt8x64",
+ argLen: 3,
commutative: true,
generic: true,
},
{
- name: "MulLowMaskedInt64x2",
+ name: "MinMaskedInt16x8",
argLen: 3,
commutative: true,
generic: true,
},
{
- name: "NotEqualInt64x2",
- argLen: 2,
+ name: "MinMaskedInt16x16",
+ argLen: 3,
commutative: true,
generic: true,
},
{
- name: "NotEqualMaskedInt64x2",
+ name: "MinMaskedInt16x32",
argLen: 3,
commutative: true,
generic: true,
},
{
- name: "OrInt64x2",
- argLen: 2,
+ name: "MinMaskedInt32x4",
+ argLen: 3,
commutative: true,
generic: true,
},
{
- name: "OrMaskedInt64x2",
+ name: "MinMaskedInt32x8",
argLen: 3,
commutative: true,
generic: true,
},
{
- name: "PopCountInt64x2",
- argLen: 1,
- generic: true,
+ name: "MinMaskedInt32x16",
+ argLen: 3,
+ commutative: true,
+ generic: true,
},
{
- name: "PopCountMaskedInt64x2",
- argLen: 2,
- generic: true,
+ name: "MinMaskedInt64x2",
+ argLen: 3,
+ commutative: true,
+ generic: true,
},
{
- name: "RotateLeftInt64x2",
- argLen: 2,
- generic: true,
+ name: "MinMaskedInt64x4",
+ argLen: 3,
+ commutative: true,
+ generic: true,
},
{
- name: "RotateLeftMaskedInt64x2",
- argLen: 3,
- generic: true,
+ name: "MinMaskedInt64x8",
+ argLen: 3,
+ commutative: true,
+ generic: true,
},
{
- name: "RotateRightInt64x2",
- argLen: 2,
- generic: true,
+ name: "MinMaskedUint8x16",
+ argLen: 3,
+ commutative: true,
+ generic: true,
},
{
- name: "RotateRightMaskedInt64x2",
- argLen: 3,
- generic: true,
+ name: "MinMaskedUint8x32",
+ argLen: 3,
+ commutative: true,
+ generic: true,
},
{
- name: "ShiftAllLeftInt64x2",
- argLen: 2,
- generic: true,
+ name: "MinMaskedUint8x64",
+ argLen: 3,
+ commutative: true,
+ generic: true,
},
{
- name: "ShiftAllLeftMaskedInt64x2",
- argLen: 3,
- generic: true,
+ name: "MinMaskedUint16x8",
+ argLen: 3,
+ commutative: true,
+ generic: true,
},
{
- name: "ShiftAllRightInt64x2",
- argLen: 2,
- generic: true,
+ name: "MinMaskedUint16x16",
+ argLen: 3,
+ commutative: true,
+ generic: true,
},
{
- name: "ShiftAllRightMaskedInt64x2",
- argLen: 3,
- generic: true,
+ name: "MinMaskedUint16x32",
+ argLen: 3,
+ commutative: true,
+ generic: true,
},
{
- name: "ShiftLeftInt64x2",
- argLen: 2,
- generic: true,
+ name: "MinMaskedUint32x4",
+ argLen: 3,
+ commutative: true,
+ generic: true,
},
{
- name: "ShiftLeftAndFillUpperFromInt64x2",
- argLen: 3,
- generic: true,
+ name: "MinMaskedUint32x8",
+ argLen: 3,
+ commutative: true,
+ generic: true,
},
{
- name: "ShiftLeftAndFillUpperFromMaskedInt64x2",
- argLen: 4,
- generic: true,
+ name: "MinMaskedUint32x16",
+ argLen: 3,
+ commutative: true,
+ generic: true,
},
{
- name: "ShiftLeftMaskedInt64x2",
- argLen: 3,
- generic: true,
+ name: "MinMaskedUint64x2",
+ argLen: 3,
+ commutative: true,
+ generic: true,
},
{
- name: "ShiftRightInt64x2",
- argLen: 2,
- generic: true,
+ name: "MinMaskedUint64x4",
+ argLen: 3,
+ commutative: true,
+ generic: true,
},
{
- name: "ShiftRightAndFillUpperFromInt64x2",
- argLen: 3,
- generic: true,
+ name: "MinMaskedUint64x8",
+ argLen: 3,
+ commutative: true,
+ generic: true,
},
{
- name: "ShiftRightAndFillUpperFromMaskedInt64x2",
- argLen: 4,
- generic: true,
+ name: "MinUint8x16",
+ argLen: 2,
+ commutative: true,
+ generic: true,
},
{
- name: "ShiftRightMaskedInt64x2",
- argLen: 3,
- generic: true,
+ name: "MinUint8x32",
+ argLen: 2,
+ commutative: true,
+ generic: true,
},
{
- name: "SubInt64x2",
- argLen: 2,
- generic: true,
+ name: "MinUint8x64",
+ argLen: 2,
+ commutative: true,
+ generic: true,
},
{
- name: "SubMaskedInt64x2",
- argLen: 3,
- generic: true,
+ name: "MinUint16x8",
+ argLen: 2,
+ commutative: true,
+ generic: true,
},
{
- name: "XorInt64x2",
+ name: "MinUint16x16",
argLen: 2,
commutative: true,
generic: true,
},
{
- name: "XorMaskedInt64x2",
- argLen: 3,
+ name: "MinUint16x32",
+ argLen: 2,
commutative: true,
generic: true,
},
{
- name: "AbsoluteInt64x4",
- argLen: 1,
- generic: true,
+ name: "MinUint32x4",
+ argLen: 2,
+ commutative: true,
+ generic: true,
},
{
- name: "AbsoluteMaskedInt64x4",
- argLen: 2,
- generic: true,
+ name: "MinUint32x8",
+ argLen: 2,
+ commutative: true,
+ generic: true,
},
{
- name: "AddInt64x4",
+ name: "MinUint32x16",
argLen: 2,
commutative: true,
generic: true,
},
{
- name: "AddMaskedInt64x4",
- argLen: 3,
+ name: "MinUint64x2",
+ argLen: 2,
commutative: true,
generic: true,
},
{
- name: "AndInt64x4",
+ name: "MinUint64x4",
argLen: 2,
commutative: true,
generic: true,
},
{
- name: "AndMaskedInt64x4",
- argLen: 3,
+ name: "MinUint64x8",
+ argLen: 2,
commutative: true,
generic: true,
},
{
- name: "AndNotInt64x4",
+ name: "MulByPowOf2Float32x4",
argLen: 2,
generic: true,
},
{
- name: "AndNotMaskedInt64x4",
- argLen: 3,
+ name: "MulByPowOf2Float32x8",
+ argLen: 2,
generic: true,
},
{
- name: "CompressInt64x4",
+ name: "MulByPowOf2Float32x16",
argLen: 2,
generic: true,
},
{
- name: "EqualInt64x4",
- argLen: 2,
- commutative: true,
- generic: true,
+ name: "MulByPowOf2Float64x2",
+ argLen: 2,
+ generic: true,
},
{
- name: "EqualMaskedInt64x4",
- argLen: 3,
- commutative: true,
- generic: true,
+ name: "MulByPowOf2Float64x4",
+ argLen: 2,
+ generic: true,
},
{
- name: "GreaterInt64x4",
+ name: "MulByPowOf2Float64x8",
argLen: 2,
generic: true,
},
{
- name: "GreaterEqualInt64x4",
- argLen: 2,
+ name: "MulByPowOf2MaskedFloat32x4",
+ argLen: 3,
generic: true,
},
{
- name: "GreaterEqualMaskedInt64x4",
+ name: "MulByPowOf2MaskedFloat32x8",
argLen: 3,
generic: true,
},
{
- name: "GreaterMaskedInt64x4",
+ name: "MulByPowOf2MaskedFloat32x16",
argLen: 3,
generic: true,
},
{
- name: "LessInt64x4",
- argLen: 2,
+ name: "MulByPowOf2MaskedFloat64x2",
+ argLen: 3,
generic: true,
},
{
- name: "LessEqualInt64x4",
- argLen: 2,
+ name: "MulByPowOf2MaskedFloat64x4",
+ argLen: 3,
+ generic: true,
+ },
+ {
+ name: "MulByPowOf2MaskedFloat64x8",
+ argLen: 3,
generic: true,
},
{
- name: "LessEqualMaskedInt64x4",
- argLen: 3,
- generic: true,
+ name: "MulEvenWidenInt32x4",
+ argLen: 2,
+ commutative: true,
+ generic: true,
+ },
+ {
+ name: "MulEvenWidenInt32x8",
+ argLen: 2,
+ commutative: true,
+ generic: true,
+ },
+ {
+ name: "MulEvenWidenInt64x2",
+ argLen: 2,
+ commutative: true,
+ generic: true,
+ },
+ {
+ name: "MulEvenWidenInt64x4",
+ argLen: 2,
+ commutative: true,
+ generic: true,
+ },
+ {
+ name: "MulEvenWidenInt64x8",
+ argLen: 2,
+ commutative: true,
+ generic: true,
+ },
+ {
+ name: "MulEvenWidenMaskedInt64x2",
+ argLen: 3,
+ commutative: true,
+ generic: true,
},
{
- name: "LessMaskedInt64x4",
- argLen: 3,
- generic: true,
+ name: "MulEvenWidenMaskedInt64x4",
+ argLen: 3,
+ commutative: true,
+ generic: true,
},
{
- name: "MaxInt64x4",
- argLen: 2,
+ name: "MulEvenWidenMaskedInt64x8",
+ argLen: 3,
commutative: true,
generic: true,
},
{
- name: "MaxMaskedInt64x4",
+ name: "MulEvenWidenMaskedUint64x2",
argLen: 3,
commutative: true,
generic: true,
},
{
- name: "MinInt64x4",
- argLen: 2,
+ name: "MulEvenWidenMaskedUint64x4",
+ argLen: 3,
commutative: true,
generic: true,
},
{
- name: "MinMaskedInt64x4",
+ name: "MulEvenWidenMaskedUint64x8",
argLen: 3,
commutative: true,
generic: true,
},
{
- name: "MulEvenWidenInt64x4",
+ name: "MulEvenWidenUint32x4",
argLen: 2,
commutative: true,
generic: true,
},
{
- name: "MulEvenWidenMaskedInt64x4",
- argLen: 3,
+ name: "MulEvenWidenUint32x8",
+ argLen: 2,
commutative: true,
generic: true,
},
{
- name: "MulLowInt64x4",
+ name: "MulEvenWidenUint64x2",
argLen: 2,
commutative: true,
generic: true,
},
{
- name: "MulLowMaskedInt64x4",
- argLen: 3,
+ name: "MulEvenWidenUint64x4",
+ argLen: 2,
commutative: true,
generic: true,
},
{
- name: "NotEqualInt64x4",
+ name: "MulEvenWidenUint64x8",
argLen: 2,
commutative: true,
generic: true,
},
{
- name: "NotEqualMaskedInt64x4",
- argLen: 3,
+ name: "MulFloat32x4",
+ argLen: 2,
commutative: true,
generic: true,
},
{
- name: "OrInt64x4",
+ name: "MulFloat32x8",
argLen: 2,
commutative: true,
generic: true,
},
{
- name: "OrMaskedInt64x4",
- argLen: 3,
+ name: "MulFloat32x16",
+ argLen: 2,
commutative: true,
generic: true,
},
{
- name: "PopCountInt64x4",
- argLen: 1,
- generic: true,
+ name: "MulFloat64x2",
+ argLen: 2,
+ commutative: true,
+ generic: true,
},
{
- name: "PopCountMaskedInt64x4",
- argLen: 2,
- generic: true,
+ name: "MulFloat64x4",
+ argLen: 2,
+ commutative: true,
+ generic: true,
},
{
- name: "RotateLeftInt64x4",
- argLen: 2,
- generic: true,
+ name: "MulFloat64x8",
+ argLen: 2,
+ commutative: true,
+ generic: true,
},
{
- name: "RotateLeftMaskedInt64x4",
- argLen: 3,
- generic: true,
+ name: "MulHighInt16x8",
+ argLen: 2,
+ commutative: true,
+ generic: true,
},
{
- name: "RotateRightInt64x4",
- argLen: 2,
- generic: true,
+ name: "MulHighInt16x16",
+ argLen: 2,
+ commutative: true,
+ generic: true,
},
{
- name: "RotateRightMaskedInt64x4",
- argLen: 3,
- generic: true,
+ name: "MulHighInt16x32",
+ argLen: 2,
+ commutative: true,
+ generic: true,
},
{
- name: "ShiftAllLeftInt64x4",
- argLen: 2,
- generic: true,
+ name: "MulHighMaskedInt16x8",
+ argLen: 3,
+ commutative: true,
+ generic: true,
},
{
- name: "ShiftAllLeftMaskedInt64x4",
- argLen: 3,
- generic: true,
+ name: "MulHighMaskedInt16x16",
+ argLen: 3,
+ commutative: true,
+ generic: true,
},
{
- name: "ShiftAllRightInt64x4",
- argLen: 2,
- generic: true,
+ name: "MulHighMaskedInt16x32",
+ argLen: 3,
+ commutative: true,
+ generic: true,
},
{
- name: "ShiftAllRightMaskedInt64x4",
- argLen: 3,
- generic: true,
+ name: "MulHighMaskedUint16x8",
+ argLen: 3,
+ commutative: true,
+ generic: true,
},
{
- name: "ShiftLeftInt64x4",
- argLen: 2,
- generic: true,
+ name: "MulHighMaskedUint16x16",
+ argLen: 3,
+ commutative: true,
+ generic: true,
},
{
- name: "ShiftLeftAndFillUpperFromInt64x4",
- argLen: 3,
- generic: true,
+ name: "MulHighMaskedUint16x32",
+ argLen: 3,
+ commutative: true,
+ generic: true,
},
{
- name: "ShiftLeftAndFillUpperFromMaskedInt64x4",
- argLen: 4,
- generic: true,
+ name: "MulHighUint16x8",
+ argLen: 2,
+ commutative: true,
+ generic: true,
},
{
- name: "ShiftLeftMaskedInt64x4",
- argLen: 3,
- generic: true,
+ name: "MulHighUint16x16",
+ argLen: 2,
+ commutative: true,
+ generic: true,
},
{
- name: "ShiftRightInt64x4",
- argLen: 2,
- generic: true,
+ name: "MulHighUint16x32",
+ argLen: 2,
+ commutative: true,
+ generic: true,
},
{
- name: "ShiftRightAndFillUpperFromInt64x4",
- argLen: 3,
- generic: true,
+ name: "MulLowInt16x8",
+ argLen: 2,
+ commutative: true,
+ generic: true,
},
{
- name: "ShiftRightAndFillUpperFromMaskedInt64x4",
- argLen: 4,
- generic: true,
+ name: "MulLowInt16x16",
+ argLen: 2,
+ commutative: true,
+ generic: true,
},
{
- name: "ShiftRightMaskedInt64x4",
- argLen: 3,
- generic: true,
+ name: "MulLowInt16x32",
+ argLen: 2,
+ commutative: true,
+ generic: true,
},
{
- name: "SubInt64x4",
- argLen: 2,
- generic: true,
+ name: "MulLowInt32x4",
+ argLen: 2,
+ commutative: true,
+ generic: true,
},
{
- name: "SubMaskedInt64x4",
- argLen: 3,
- generic: true,
+ name: "MulLowInt32x8",
+ argLen: 2,
+ commutative: true,
+ generic: true,
},
{
- name: "XorInt64x4",
+ name: "MulLowInt32x16",
argLen: 2,
commutative: true,
generic: true,
},
{
- name: "XorMaskedInt64x4",
- argLen: 3,
+ name: "MulLowInt64x2",
+ argLen: 2,
commutative: true,
generic: true,
},
{
- name: "AbsoluteInt64x8",
- argLen: 1,
- generic: true,
+ name: "MulLowInt64x4",
+ argLen: 2,
+ commutative: true,
+ generic: true,
},
{
- name: "AbsoluteMaskedInt64x8",
- argLen: 2,
- generic: true,
+ name: "MulLowInt64x8",
+ argLen: 2,
+ commutative: true,
+ generic: true,
},
{
- name: "AddInt64x8",
- argLen: 2,
+ name: "MulLowMaskedInt16x8",
+ argLen: 3,
commutative: true,
generic: true,
},
{
- name: "AddMaskedInt64x8",
+ name: "MulLowMaskedInt16x16",
argLen: 3,
commutative: true,
generic: true,
},
{
- name: "AndInt64x8",
- argLen: 2,
+ name: "MulLowMaskedInt16x32",
+ argLen: 3,
commutative: true,
generic: true,
},
{
- name: "AndMaskedInt64x8",
+ name: "MulLowMaskedInt32x4",
argLen: 3,
commutative: true,
generic: true,
},
{
- name: "AndNotInt64x8",
- argLen: 2,
- generic: true,
+ name: "MulLowMaskedInt32x8",
+ argLen: 3,
+ commutative: true,
+ generic: true,
},
{
- name: "AndNotMaskedInt64x8",
- argLen: 3,
- generic: true,
+ name: "MulLowMaskedInt32x16",
+ argLen: 3,
+ commutative: true,
+ generic: true,
},
{
- name: "CompressInt64x8",
- argLen: 2,
- generic: true,
+ name: "MulLowMaskedInt64x2",
+ argLen: 3,
+ commutative: true,
+ generic: true,
},
{
- name: "EqualInt64x8",
- argLen: 2,
+ name: "MulLowMaskedInt64x4",
+ argLen: 3,
commutative: true,
generic: true,
},
{
- name: "EqualMaskedInt64x8",
+ name: "MulLowMaskedInt64x8",
argLen: 3,
commutative: true,
generic: true,
},
{
- name: "GreaterInt64x8",
- argLen: 2,
- generic: true,
+ name: "MulMaskedFloat32x4",
+ argLen: 3,
+ commutative: true,
+ generic: true,
},
{
- name: "GreaterEqualInt64x8",
- argLen: 2,
- generic: true,
+ name: "MulMaskedFloat32x8",
+ argLen: 3,
+ commutative: true,
+ generic: true,
},
{
- name: "GreaterEqualMaskedInt64x8",
- argLen: 3,
- generic: true,
+ name: "MulMaskedFloat32x16",
+ argLen: 3,
+ commutative: true,
+ generic: true,
},
{
- name: "GreaterMaskedInt64x8",
- argLen: 3,
- generic: true,
+ name: "MulMaskedFloat64x2",
+ argLen: 3,
+ commutative: true,
+ generic: true,
},
{
- name: "LessInt64x8",
- argLen: 2,
- generic: true,
+ name: "MulMaskedFloat64x4",
+ argLen: 3,
+ commutative: true,
+ generic: true,
},
{
- name: "LessEqualInt64x8",
- argLen: 2,
- generic: true,
+ name: "MulMaskedFloat64x8",
+ argLen: 3,
+ commutative: true,
+ generic: true,
},
{
- name: "LessEqualMaskedInt64x8",
- argLen: 3,
- generic: true,
+ name: "NotEqualFloat32x4",
+ argLen: 2,
+ commutative: true,
+ generic: true,
},
{
- name: "LessMaskedInt64x8",
- argLen: 3,
- generic: true,
+ name: "NotEqualFloat32x8",
+ argLen: 2,
+ commutative: true,
+ generic: true,
},
{
- name: "MaxInt64x8",
+ name: "NotEqualFloat32x16",
argLen: 2,
commutative: true,
generic: true,
},
{
- name: "MaxMaskedInt64x8",
- argLen: 3,
+ name: "NotEqualFloat64x2",
+ argLen: 2,
commutative: true,
generic: true,
},
{
- name: "MinInt64x8",
+ name: "NotEqualFloat64x4",
argLen: 2,
commutative: true,
generic: true,
},
{
- name: "MinMaskedInt64x8",
- argLen: 3,
+ name: "NotEqualFloat64x8",
+ argLen: 2,
commutative: true,
generic: true,
},
{
- name: "MulEvenWidenInt64x8",
+ name: "NotEqualInt8x16",
argLen: 2,
commutative: true,
generic: true,
},
{
- name: "MulEvenWidenMaskedInt64x8",
- argLen: 3,
+ name: "NotEqualInt8x32",
+ argLen: 2,
commutative: true,
generic: true,
},
{
- name: "MulLowInt64x8",
+ name: "NotEqualInt8x64",
argLen: 2,
commutative: true,
generic: true,
},
{
- name: "MulLowMaskedInt64x8",
- argLen: 3,
+ name: "NotEqualInt16x8",
+ argLen: 2,
commutative: true,
generic: true,
},
{
- name: "NotEqualInt64x8",
+ name: "NotEqualInt16x16",
argLen: 2,
commutative: true,
generic: true,
},
{
- name: "NotEqualMaskedInt64x8",
- argLen: 3,
+ name: "NotEqualInt16x32",
+ argLen: 2,
commutative: true,
generic: true,
},
{
- name: "OrInt64x8",
+ name: "NotEqualInt32x4",
argLen: 2,
commutative: true,
generic: true,
},
{
- name: "OrMaskedInt64x8",
- argLen: 3,
+ name: "NotEqualInt32x8",
+ argLen: 2,
commutative: true,
generic: true,
},
{
- name: "PopCountInt64x8",
- argLen: 1,
- generic: true,
+ name: "NotEqualInt32x16",
+ argLen: 2,
+ commutative: true,
+ generic: true,
},
{
- name: "PopCountMaskedInt64x8",
- argLen: 2,
- generic: true,
+ name: "NotEqualInt64x2",
+ argLen: 2,
+ commutative: true,
+ generic: true,
},
{
- name: "RotateLeftInt64x8",
- argLen: 2,
- generic: true,
+ name: "NotEqualInt64x4",
+ argLen: 2,
+ commutative: true,
+ generic: true,
},
{
- name: "RotateLeftMaskedInt64x8",
- argLen: 3,
- generic: true,
+ name: "NotEqualInt64x8",
+ argLen: 2,
+ commutative: true,
+ generic: true,
},
{
- name: "RotateRightInt64x8",
- argLen: 2,
- generic: true,
+ name: "NotEqualMaskedFloat32x4",
+ argLen: 3,
+ commutative: true,
+ generic: true,
},
{
- name: "RotateRightMaskedInt64x8",
- argLen: 3,
- generic: true,
+ name: "NotEqualMaskedFloat32x8",
+ argLen: 3,
+ commutative: true,
+ generic: true,
},
{
- name: "ShiftAllLeftInt64x8",
- argLen: 2,
- generic: true,
+ name: "NotEqualMaskedFloat32x16",
+ argLen: 3,
+ commutative: true,
+ generic: true,
},
{
- name: "ShiftAllLeftMaskedInt64x8",
- argLen: 3,
- generic: true,
+ name: "NotEqualMaskedFloat64x2",
+ argLen: 3,
+ commutative: true,
+ generic: true,
},
{
- name: "ShiftAllRightInt64x8",
- argLen: 2,
- generic: true,
+ name: "NotEqualMaskedFloat64x4",
+ argLen: 3,
+ commutative: true,
+ generic: true,
},
{
- name: "ShiftAllRightMaskedInt64x8",
- argLen: 3,
- generic: true,
+ name: "NotEqualMaskedFloat64x8",
+ argLen: 3,
+ commutative: true,
+ generic: true,
},
{
- name: "ShiftLeftInt64x8",
- argLen: 2,
- generic: true,
+ name: "NotEqualMaskedInt8x16",
+ argLen: 3,
+ commutative: true,
+ generic: true,
},
{
- name: "ShiftLeftAndFillUpperFromInt64x8",
- argLen: 3,
- generic: true,
+ name: "NotEqualMaskedInt8x32",
+ argLen: 3,
+ commutative: true,
+ generic: true,
},
{
- name: "ShiftLeftAndFillUpperFromMaskedInt64x8",
- argLen: 4,
- generic: true,
+ name: "NotEqualMaskedInt8x64",
+ argLen: 3,
+ commutative: true,
+ generic: true,
},
{
- name: "ShiftLeftMaskedInt64x8",
- argLen: 3,
- generic: true,
+ name: "NotEqualMaskedInt16x8",
+ argLen: 3,
+ commutative: true,
+ generic: true,
},
{
- name: "ShiftRightInt64x8",
- argLen: 2,
- generic: true,
+ name: "NotEqualMaskedInt16x16",
+ argLen: 3,
+ commutative: true,
+ generic: true,
},
{
- name: "ShiftRightAndFillUpperFromInt64x8",
- argLen: 3,
- generic: true,
+ name: "NotEqualMaskedInt16x32",
+ argLen: 3,
+ commutative: true,
+ generic: true,
},
{
- name: "ShiftRightAndFillUpperFromMaskedInt64x8",
- argLen: 4,
- generic: true,
+ name: "NotEqualMaskedInt32x4",
+ argLen: 3,
+ commutative: true,
+ generic: true,
},
{
- name: "ShiftRightMaskedInt64x8",
- argLen: 3,
- generic: true,
+ name: "NotEqualMaskedInt32x8",
+ argLen: 3,
+ commutative: true,
+ generic: true,
},
{
- name: "SubInt64x8",
- argLen: 2,
- generic: true,
+ name: "NotEqualMaskedInt32x16",
+ argLen: 3,
+ commutative: true,
+ generic: true,
},
{
- name: "SubMaskedInt64x8",
- argLen: 3,
- generic: true,
+ name: "NotEqualMaskedInt64x2",
+ argLen: 3,
+ commutative: true,
+ generic: true,
},
{
- name: "XorInt64x8",
- argLen: 2,
+ name: "NotEqualMaskedInt64x4",
+ argLen: 3,
commutative: true,
generic: true,
},
{
- name: "XorMaskedInt64x8",
+ name: "NotEqualMaskedInt64x8",
argLen: 3,
commutative: true,
generic: true,
},
{
- name: "AbsoluteInt8x16",
- argLen: 1,
- generic: true,
+ name: "NotEqualMaskedUint8x16",
+ argLen: 3,
+ commutative: true,
+ generic: true,
},
{
- name: "AbsoluteMaskedInt8x16",
- argLen: 2,
- generic: true,
+ name: "NotEqualMaskedUint8x32",
+ argLen: 3,
+ commutative: true,
+ generic: true,
},
{
- name: "AddInt8x16",
- argLen: 2,
+ name: "NotEqualMaskedUint8x64",
+ argLen: 3,
+ commutative: true,
+ generic: true,
+ },
+ {
+ name: "NotEqualMaskedUint16x8",
+ argLen: 3,
commutative: true,
generic: true,
},
{
- name: "AddMaskedInt8x16",
+ name: "NotEqualMaskedUint16x16",
argLen: 3,
commutative: true,
generic: true,
},
{
- name: "AndInt8x16",
- argLen: 2,
+ name: "NotEqualMaskedUint16x32",
+ argLen: 3,
commutative: true,
generic: true,
},
{
- name: "AndNotInt8x16",
- argLen: 2,
- generic: true,
+ name: "NotEqualMaskedUint32x4",
+ argLen: 3,
+ commutative: true,
+ generic: true,
},
{
- name: "CompressInt8x16",
- argLen: 2,
- generic: true,
+ name: "NotEqualMaskedUint32x8",
+ argLen: 3,
+ commutative: true,
+ generic: true,
},
{
- name: "EqualInt8x16",
- argLen: 2,
+ name: "NotEqualMaskedUint32x16",
+ argLen: 3,
commutative: true,
generic: true,
},
{
- name: "EqualMaskedInt8x16",
+ name: "NotEqualMaskedUint64x2",
argLen: 3,
commutative: true,
generic: true,
},
{
- name: "GreaterInt8x16",
- argLen: 2,
- generic: true,
+ name: "NotEqualMaskedUint64x4",
+ argLen: 3,
+ commutative: true,
+ generic: true,
},
{
- name: "GreaterEqualInt8x16",
- argLen: 2,
- generic: true,
+ name: "NotEqualMaskedUint64x8",
+ argLen: 3,
+ commutative: true,
+ generic: true,
},
{
- name: "GreaterEqualMaskedInt8x16",
- argLen: 3,
- generic: true,
+ name: "NotEqualUint8x16",
+ argLen: 2,
+ commutative: true,
+ generic: true,
},
{
- name: "GreaterMaskedInt8x16",
- argLen: 3,
- generic: true,
+ name: "NotEqualUint8x32",
+ argLen: 2,
+ commutative: true,
+ generic: true,
},
{
- name: "LessInt8x16",
- argLen: 2,
- generic: true,
+ name: "NotEqualUint8x64",
+ argLen: 2,
+ commutative: true,
+ generic: true,
},
{
- name: "LessEqualInt8x16",
- argLen: 2,
- generic: true,
+ name: "NotEqualUint16x8",
+ argLen: 2,
+ commutative: true,
+ generic: true,
},
{
- name: "LessEqualMaskedInt8x16",
- argLen: 3,
- generic: true,
+ name: "NotEqualUint16x16",
+ argLen: 2,
+ commutative: true,
+ generic: true,
},
{
- name: "LessMaskedInt8x16",
- argLen: 3,
- generic: true,
+ name: "NotEqualUint16x32",
+ argLen: 2,
+ commutative: true,
+ generic: true,
},
{
- name: "MaxInt8x16",
+ name: "NotEqualUint32x4",
argLen: 2,
commutative: true,
generic: true,
},
{
- name: "MaxMaskedInt8x16",
- argLen: 3,
+ name: "NotEqualUint32x8",
+ argLen: 2,
commutative: true,
generic: true,
},
{
- name: "MinInt8x16",
+ name: "NotEqualUint32x16",
argLen: 2,
commutative: true,
generic: true,
},
{
- name: "MinMaskedInt8x16",
- argLen: 3,
+ name: "NotEqualUint64x2",
+ argLen: 2,
commutative: true,
generic: true,
},
{
- name: "NotEqualInt8x16",
+ name: "NotEqualUint64x4",
argLen: 2,
commutative: true,
generic: true,
},
{
- name: "NotEqualMaskedInt8x16",
- argLen: 3,
+ name: "NotEqualUint64x8",
+ argLen: 2,
commutative: true,
generic: true,
},
generic: true,
},
{
- name: "PopCountInt8x16",
- argLen: 1,
- generic: true,
- },
- {
- name: "PopCountMaskedInt8x16",
- argLen: 2,
- generic: true,
- },
- {
- name: "SaturatedAddInt8x16",
+ name: "OrInt8x32",
argLen: 2,
commutative: true,
generic: true,
},
{
- name: "SaturatedAddMaskedInt8x16",
- argLen: 3,
+ name: "OrInt16x8",
+ argLen: 2,
commutative: true,
generic: true,
},
{
- name: "SaturatedSubInt8x16",
- argLen: 2,
- generic: true,
- },
- {
- name: "SaturatedSubMaskedInt8x16",
- argLen: 3,
- generic: true,
- },
- {
- name: "SignInt8x16",
- argLen: 2,
- generic: true,
- },
- {
- name: "SubInt8x16",
- argLen: 2,
- generic: true,
- },
- {
- name: "SubMaskedInt8x16",
- argLen: 3,
- generic: true,
+ name: "OrInt16x16",
+ argLen: 2,
+ commutative: true,
+ generic: true,
},
{
- name: "XorInt8x16",
+ name: "OrInt32x4",
argLen: 2,
commutative: true,
generic: true,
},
{
- name: "AbsoluteInt8x32",
- argLen: 1,
- generic: true,
+ name: "OrInt32x8",
+ argLen: 2,
+ commutative: true,
+ generic: true,
},
{
- name: "AbsoluteMaskedInt8x32",
- argLen: 2,
- generic: true,
+ name: "OrInt32x16",
+ argLen: 2,
+ commutative: true,
+ generic: true,
},
{
- name: "AddInt8x32",
+ name: "OrInt64x2",
argLen: 2,
commutative: true,
generic: true,
},
{
- name: "AddMaskedInt8x32",
- argLen: 3,
+ name: "OrInt64x4",
+ argLen: 2,
commutative: true,
generic: true,
},
{
- name: "AndInt8x32",
+ name: "OrInt64x8",
argLen: 2,
commutative: true,
generic: true,
},
{
- name: "AndNotInt8x32",
- argLen: 2,
- generic: true,
+ name: "OrMaskedInt32x4",
+ argLen: 3,
+ commutative: true,
+ generic: true,
},
{
- name: "CompressInt8x32",
- argLen: 2,
- generic: true,
+ name: "OrMaskedInt32x8",
+ argLen: 3,
+ commutative: true,
+ generic: true,
},
{
- name: "EqualInt8x32",
- argLen: 2,
+ name: "OrMaskedInt32x16",
+ argLen: 3,
commutative: true,
generic: true,
},
{
- name: "EqualMaskedInt8x32",
+ name: "OrMaskedInt64x2",
argLen: 3,
commutative: true,
generic: true,
},
{
- name: "GreaterInt8x32",
- argLen: 2,
- generic: true,
+ name: "OrMaskedInt64x4",
+ argLen: 3,
+ commutative: true,
+ generic: true,
},
{
- name: "GreaterEqualInt8x32",
- argLen: 2,
- generic: true,
+ name: "OrMaskedInt64x8",
+ argLen: 3,
+ commutative: true,
+ generic: true,
},
{
- name: "GreaterEqualMaskedInt8x32",
- argLen: 3,
- generic: true,
+ name: "OrMaskedUint32x4",
+ argLen: 3,
+ commutative: true,
+ generic: true,
},
{
- name: "GreaterMaskedInt8x32",
- argLen: 3,
- generic: true,
+ name: "OrMaskedUint32x8",
+ argLen: 3,
+ commutative: true,
+ generic: true,
},
{
- name: "LessInt8x32",
- argLen: 2,
- generic: true,
+ name: "OrMaskedUint32x16",
+ argLen: 3,
+ commutative: true,
+ generic: true,
},
{
- name: "LessEqualInt8x32",
- argLen: 2,
- generic: true,
+ name: "OrMaskedUint64x2",
+ argLen: 3,
+ commutative: true,
+ generic: true,
},
{
- name: "LessEqualMaskedInt8x32",
- argLen: 3,
- generic: true,
+ name: "OrMaskedUint64x4",
+ argLen: 3,
+ commutative: true,
+ generic: true,
},
{
- name: "LessMaskedInt8x32",
- argLen: 3,
- generic: true,
+ name: "OrMaskedUint64x8",
+ argLen: 3,
+ commutative: true,
+ generic: true,
},
{
- name: "MaxInt8x32",
+ name: "OrUint8x16",
argLen: 2,
commutative: true,
generic: true,
},
{
- name: "MaxMaskedInt8x32",
- argLen: 3,
+ name: "OrUint8x32",
+ argLen: 2,
commutative: true,
generic: true,
},
{
- name: "MinInt8x32",
+ name: "OrUint16x8",
argLen: 2,
commutative: true,
generic: true,
},
{
- name: "MinMaskedInt8x32",
- argLen: 3,
+ name: "OrUint16x16",
+ argLen: 2,
commutative: true,
generic: true,
},
{
- name: "NotEqualInt8x32",
+ name: "OrUint32x4",
argLen: 2,
commutative: true,
generic: true,
},
{
- name: "NotEqualMaskedInt8x32",
- argLen: 3,
+ name: "OrUint32x8",
+ argLen: 2,
commutative: true,
generic: true,
},
{
- name: "OrInt8x32",
+ name: "OrUint32x16",
argLen: 2,
commutative: true,
generic: true,
},
{
- name: "PopCountInt8x32",
- argLen: 1,
- generic: true,
- },
- {
- name: "PopCountMaskedInt8x32",
- argLen: 2,
- generic: true,
+ name: "OrUint64x2",
+ argLen: 2,
+ commutative: true,
+ generic: true,
},
{
- name: "SaturatedAddInt8x32",
+ name: "OrUint64x4",
argLen: 2,
commutative: true,
generic: true,
},
{
- name: "SaturatedAddMaskedInt8x32",
- argLen: 3,
+ name: "OrUint64x8",
+ argLen: 2,
commutative: true,
generic: true,
},
{
- name: "SaturatedSubInt8x32",
- argLen: 2,
+ name: "PairDotProdAccumulateInt32x4",
+ argLen: 3,
generic: true,
},
{
- name: "SaturatedSubMaskedInt8x32",
+ name: "PairDotProdAccumulateInt32x8",
argLen: 3,
generic: true,
},
{
- name: "SignInt8x32",
- argLen: 2,
+ name: "PairDotProdAccumulateInt32x16",
+ argLen: 3,
generic: true,
},
{
- name: "SubInt8x32",
- argLen: 2,
+ name: "PairDotProdAccumulateMaskedInt32x4",
+ argLen: 4,
generic: true,
},
{
- name: "SubMaskedInt8x32",
- argLen: 3,
+ name: "PairDotProdAccumulateMaskedInt32x8",
+ argLen: 4,
generic: true,
},
{
- name: "XorInt8x32",
- argLen: 2,
- commutative: true,
- generic: true,
- },
- {
- name: "AbsoluteInt8x64",
- argLen: 1,
+ name: "PairDotProdAccumulateMaskedInt32x16",
+ argLen: 4,
generic: true,
},
{
- name: "AbsoluteMaskedInt8x64",
+ name: "PairDotProdInt16x8",
argLen: 2,
generic: true,
},
{
- name: "AddInt8x64",
- argLen: 2,
- commutative: true,
- generic: true,
- },
- {
- name: "AddMaskedInt8x64",
- argLen: 3,
- commutative: true,
- generic: true,
- },
- {
- name: "CompressInt8x64",
+ name: "PairDotProdInt16x16",
argLen: 2,
generic: true,
},
{
- name: "EqualInt8x64",
- argLen: 2,
- commutative: true,
- generic: true,
- },
- {
- name: "EqualMaskedInt8x64",
- argLen: 3,
- commutative: true,
- generic: true,
- },
- {
- name: "GreaterInt8x64",
+ name: "PairDotProdInt16x32",
argLen: 2,
generic: true,
},
{
- name: "GreaterEqualInt8x64",
- argLen: 2,
+ name: "PairDotProdMaskedInt16x8",
+ argLen: 3,
generic: true,
},
{
- name: "GreaterEqualMaskedInt8x64",
+ name: "PairDotProdMaskedInt16x16",
argLen: 3,
generic: true,
},
{
- name: "GreaterMaskedInt8x64",
+ name: "PairDotProdMaskedInt16x32",
argLen: 3,
generic: true,
},
{
- name: "LessInt8x64",
+ name: "PairwiseAddFloat32x4",
argLen: 2,
generic: true,
},
{
- name: "LessEqualInt8x64",
+ name: "PairwiseAddFloat32x8",
argLen: 2,
generic: true,
},
{
- name: "LessEqualMaskedInt8x64",
- argLen: 3,
+ name: "PairwiseAddFloat64x2",
+ argLen: 2,
generic: true,
},
{
- name: "LessMaskedInt8x64",
- argLen: 3,
+ name: "PairwiseAddFloat64x4",
+ argLen: 2,
generic: true,
},
{
- name: "MaxInt8x64",
- argLen: 2,
- commutative: true,
- generic: true,
+ name: "PairwiseAddInt16x8",
+ argLen: 2,
+ generic: true,
},
{
- name: "MaxMaskedInt8x64",
- argLen: 3,
- commutative: true,
- generic: true,
+ name: "PairwiseAddInt16x16",
+ argLen: 2,
+ generic: true,
},
{
- name: "MinInt8x64",
- argLen: 2,
- commutative: true,
- generic: true,
+ name: "PairwiseAddInt32x4",
+ argLen: 2,
+ generic: true,
},
{
- name: "MinMaskedInt8x64",
- argLen: 3,
- commutative: true,
- generic: true,
+ name: "PairwiseAddInt32x8",
+ argLen: 2,
+ generic: true,
},
{
- name: "NotEqualInt8x64",
- argLen: 2,
- commutative: true,
- generic: true,
+ name: "PairwiseAddUint16x8",
+ argLen: 2,
+ generic: true,
},
{
- name: "NotEqualMaskedInt8x64",
- argLen: 3,
- commutative: true,
- generic: true,
+ name: "PairwiseAddUint16x16",
+ argLen: 2,
+ generic: true,
},
{
- name: "PopCountInt8x64",
- argLen: 1,
+ name: "PairwiseAddUint32x4",
+ argLen: 2,
generic: true,
},
{
- name: "PopCountMaskedInt8x64",
+ name: "PairwiseAddUint32x8",
argLen: 2,
generic: true,
},
{
- name: "SaturatedAddInt8x64",
- argLen: 2,
- commutative: true,
- generic: true,
+ name: "PairwiseSubFloat32x4",
+ argLen: 2,
+ generic: true,
},
{
- name: "SaturatedAddMaskedInt8x64",
- argLen: 3,
- commutative: true,
- generic: true,
+ name: "PairwiseSubFloat32x8",
+ argLen: 2,
+ generic: true,
},
{
- name: "SaturatedSubInt8x64",
+ name: "PairwiseSubFloat64x2",
argLen: 2,
generic: true,
},
{
- name: "SaturatedSubMaskedInt8x64",
- argLen: 3,
+ name: "PairwiseSubFloat64x4",
+ argLen: 2,
generic: true,
},
{
- name: "SubInt8x64",
+ name: "PairwiseSubInt16x8",
argLen: 2,
generic: true,
},
{
- name: "SubMaskedInt8x64",
- argLen: 3,
+ name: "PairwiseSubInt16x16",
+ argLen: 2,
generic: true,
},
{
- name: "AddUint16x16",
- argLen: 2,
- commutative: true,
- generic: true,
+ name: "PairwiseSubInt32x4",
+ argLen: 2,
+ generic: true,
},
{
- name: "AddMaskedUint16x16",
- argLen: 3,
- commutative: true,
- generic: true,
+ name: "PairwiseSubInt32x8",
+ argLen: 2,
+ generic: true,
},
{
- name: "AndUint16x16",
- argLen: 2,
- commutative: true,
- generic: true,
+ name: "PairwiseSubUint16x8",
+ argLen: 2,
+ generic: true,
},
{
- name: "AndNotUint16x16",
+ name: "PairwiseSubUint16x16",
argLen: 2,
generic: true,
},
{
- name: "AverageUint16x16",
- argLen: 2,
- commutative: true,
- generic: true,
+ name: "PairwiseSubUint32x4",
+ argLen: 2,
+ generic: true,
},
{
- name: "AverageMaskedUint16x16",
- argLen: 3,
- commutative: true,
- generic: true,
+ name: "PairwiseSubUint32x8",
+ argLen: 2,
+ generic: true,
},
{
- name: "CompressUint16x16",
- argLen: 2,
+ name: "Permute2Float32x4",
+ argLen: 3,
generic: true,
},
{
- name: "EqualUint16x16",
- argLen: 2,
- commutative: true,
- generic: true,
+ name: "Permute2Float32x8",
+ argLen: 3,
+ generic: true,
},
{
- name: "EqualMaskedUint16x16",
- argLen: 3,
- commutative: true,
- generic: true,
+ name: "Permute2Float32x16",
+ argLen: 3,
+ generic: true,
},
{
- name: "GreaterUint16x16",
- argLen: 2,
+ name: "Permute2Float64x2",
+ argLen: 3,
generic: true,
},
{
- name: "GreaterEqualUint16x16",
- argLen: 2,
+ name: "Permute2Float64x4",
+ argLen: 3,
generic: true,
},
{
- name: "GreaterEqualMaskedUint16x16",
+ name: "Permute2Float64x8",
argLen: 3,
generic: true,
},
{
- name: "GreaterMaskedUint16x16",
+ name: "Permute2Int8x16",
argLen: 3,
generic: true,
},
{
- name: "LessUint16x16",
- argLen: 2,
+ name: "Permute2Int8x32",
+ argLen: 3,
generic: true,
},
{
- name: "LessEqualUint16x16",
- argLen: 2,
+ name: "Permute2Int8x64",
+ argLen: 3,
+ generic: true,
+ },
+ {
+ name: "Permute2Int16x8",
+ argLen: 3,
generic: true,
},
{
- name: "LessEqualMaskedUint16x16",
+ name: "Permute2Int16x16",
argLen: 3,
generic: true,
},
{
- name: "LessMaskedUint16x16",
+ name: "Permute2Int16x32",
argLen: 3,
generic: true,
},
{
- name: "MaxUint16x16",
- argLen: 2,
- commutative: true,
- generic: true,
+ name: "Permute2Int32x4",
+ argLen: 3,
+ generic: true,
},
{
- name: "MaxMaskedUint16x16",
- argLen: 3,
- commutative: true,
- generic: true,
+ name: "Permute2Int32x8",
+ argLen: 3,
+ generic: true,
},
{
- name: "MinUint16x16",
- argLen: 2,
- commutative: true,
- generic: true,
+ name: "Permute2Int32x16",
+ argLen: 3,
+ generic: true,
},
{
- name: "MinMaskedUint16x16",
- argLen: 3,
- commutative: true,
- generic: true,
+ name: "Permute2Int64x2",
+ argLen: 3,
+ generic: true,
},
{
- name: "MulHighUint16x16",
- argLen: 2,
- commutative: true,
- generic: true,
+ name: "Permute2Int64x4",
+ argLen: 3,
+ generic: true,
},
{
- name: "MulHighMaskedUint16x16",
- argLen: 3,
- commutative: true,
- generic: true,
+ name: "Permute2Int64x8",
+ argLen: 3,
+ generic: true,
},
{
- name: "NotEqualUint16x16",
- argLen: 2,
- commutative: true,
- generic: true,
+ name: "Permute2MaskedFloat32x4",
+ argLen: 4,
+ generic: true,
},
{
- name: "NotEqualMaskedUint16x16",
- argLen: 3,
- commutative: true,
- generic: true,
+ name: "Permute2MaskedFloat32x8",
+ argLen: 4,
+ generic: true,
},
{
- name: "OrUint16x16",
- argLen: 2,
- commutative: true,
- generic: true,
+ name: "Permute2MaskedFloat32x16",
+ argLen: 4,
+ generic: true,
},
{
- name: "PairwiseAddUint16x16",
- argLen: 2,
+ name: "Permute2MaskedFloat64x2",
+ argLen: 4,
generic: true,
},
{
- name: "PairwiseSubUint16x16",
- argLen: 2,
+ name: "Permute2MaskedFloat64x4",
+ argLen: 4,
generic: true,
},
{
- name: "PermuteInt16x16",
- argLen: 2,
+ name: "Permute2MaskedFloat64x8",
+ argLen: 4,
generic: true,
},
{
- name: "PermuteUint16x16",
- argLen: 2,
+ name: "Permute2MaskedInt8x16",
+ argLen: 4,
generic: true,
},
{
- name: "Permute2Uint16x16",
- argLen: 3,
+ name: "Permute2MaskedInt8x32",
+ argLen: 4,
generic: true,
},
{
- name: "Permute2Int16x16",
- argLen: 3,
+ name: "Permute2MaskedInt8x64",
+ argLen: 4,
generic: true,
},
{
- name: "Permute2MaskedUint16x16",
+ name: "Permute2MaskedInt16x8",
argLen: 4,
generic: true,
},
generic: true,
},
{
- name: "PermuteMaskedInt16x16",
- argLen: 3,
+ name: "Permute2MaskedInt16x32",
+ argLen: 4,
generic: true,
},
{
- name: "PermuteMaskedUint16x16",
- argLen: 3,
+ name: "Permute2MaskedInt32x4",
+ argLen: 4,
generic: true,
},
{
- name: "PopCountUint16x16",
- argLen: 1,
+ name: "Permute2MaskedInt32x8",
+ argLen: 4,
generic: true,
},
{
- name: "PopCountMaskedUint16x16",
- argLen: 2,
+ name: "Permute2MaskedInt32x16",
+ argLen: 4,
generic: true,
},
{
- name: "SaturatedAddUint16x16",
- argLen: 2,
- commutative: true,
- generic: true,
+ name: "Permute2MaskedInt64x2",
+ argLen: 4,
+ generic: true,
},
{
- name: "SaturatedAddMaskedUint16x16",
- argLen: 3,
- commutative: true,
- generic: true,
+ name: "Permute2MaskedInt64x4",
+ argLen: 4,
+ generic: true,
},
{
- name: "SaturatedSubUint16x16",
- argLen: 2,
+ name: "Permute2MaskedInt64x8",
+ argLen: 4,
generic: true,
},
{
- name: "SaturatedSubMaskedUint16x16",
- argLen: 3,
+ name: "Permute2MaskedUint8x16",
+ argLen: 4,
generic: true,
},
{
- name: "ShiftAllLeftUint16x16",
- argLen: 2,
+ name: "Permute2MaskedUint8x32",
+ argLen: 4,
generic: true,
},
{
- name: "ShiftAllLeftMaskedUint16x16",
- argLen: 3,
+ name: "Permute2MaskedUint8x64",
+ argLen: 4,
generic: true,
},
{
- name: "ShiftAllRightUint16x16",
- argLen: 2,
+ name: "Permute2MaskedUint16x8",
+ argLen: 4,
generic: true,
},
{
- name: "ShiftAllRightMaskedUint16x16",
- argLen: 3,
+ name: "Permute2MaskedUint16x16",
+ argLen: 4,
generic: true,
},
{
- name: "ShiftLeftUint16x16",
- argLen: 2,
+ name: "Permute2MaskedUint16x32",
+ argLen: 4,
generic: true,
},
{
- name: "ShiftLeftAndFillUpperFromUint16x16",
- argLen: 3,
+ name: "Permute2MaskedUint32x4",
+ argLen: 4,
generic: true,
},
{
- name: "ShiftLeftAndFillUpperFromMaskedUint16x16",
+ name: "Permute2MaskedUint32x8",
argLen: 4,
generic: true,
},
{
- name: "ShiftLeftMaskedUint16x16",
- argLen: 3,
+ name: "Permute2MaskedUint32x16",
+ argLen: 4,
generic: true,
},
{
- name: "ShiftRightUint16x16",
- argLen: 2,
+ name: "Permute2MaskedUint64x2",
+ argLen: 4,
generic: true,
},
{
- name: "ShiftRightAndFillUpperFromUint16x16",
- argLen: 3,
+ name: "Permute2MaskedUint64x4",
+ argLen: 4,
generic: true,
},
{
- name: "ShiftRightAndFillUpperFromMaskedUint16x16",
+ name: "Permute2MaskedUint64x8",
argLen: 4,
generic: true,
},
{
- name: "ShiftRightMaskedUint16x16",
+ name: "Permute2Uint8x16",
argLen: 3,
generic: true,
},
{
- name: "SubUint16x16",
- argLen: 2,
+ name: "Permute2Uint8x32",
+ argLen: 3,
generic: true,
},
{
- name: "SubMaskedUint16x16",
+ name: "Permute2Uint8x64",
argLen: 3,
generic: true,
},
{
- name: "XorUint16x16",
- argLen: 2,
- commutative: true,
- generic: true,
- },
- {
- name: "AddUint16x32",
- argLen: 2,
- commutative: true,
- generic: true,
- },
- {
- name: "AddMaskedUint16x32",
- argLen: 3,
- commutative: true,
- generic: true,
- },
- {
- name: "AverageUint16x32",
- argLen: 2,
- commutative: true,
- generic: true,
+ name: "Permute2Uint16x8",
+ argLen: 3,
+ generic: true,
},
{
- name: "AverageMaskedUint16x32",
- argLen: 3,
- commutative: true,
- generic: true,
+ name: "Permute2Uint16x16",
+ argLen: 3,
+ generic: true,
},
{
- name: "CompressUint16x32",
- argLen: 2,
+ name: "Permute2Uint16x32",
+ argLen: 3,
generic: true,
},
{
- name: "EqualUint16x32",
- argLen: 2,
- commutative: true,
- generic: true,
+ name: "Permute2Uint32x4",
+ argLen: 3,
+ generic: true,
},
{
- name: "EqualMaskedUint16x32",
- argLen: 3,
- commutative: true,
- generic: true,
+ name: "Permute2Uint32x8",
+ argLen: 3,
+ generic: true,
},
{
- name: "GreaterUint16x32",
- argLen: 2,
+ name: "Permute2Uint32x16",
+ argLen: 3,
generic: true,
},
{
- name: "GreaterEqualUint16x32",
- argLen: 2,
+ name: "Permute2Uint64x2",
+ argLen: 3,
generic: true,
},
{
- name: "GreaterEqualMaskedUint16x32",
+ name: "Permute2Uint64x4",
argLen: 3,
generic: true,
},
{
- name: "GreaterMaskedUint16x32",
+ name: "Permute2Uint64x8",
argLen: 3,
generic: true,
},
{
- name: "LessUint16x32",
+ name: "PermuteFloat32x8",
argLen: 2,
generic: true,
},
{
- name: "LessEqualUint16x32",
+ name: "PermuteFloat32x16",
argLen: 2,
generic: true,
},
{
- name: "LessEqualMaskedUint16x32",
- argLen: 3,
+ name: "PermuteFloat64x4",
+ argLen: 2,
generic: true,
},
{
- name: "LessMaskedUint16x32",
- argLen: 3,
+ name: "PermuteFloat64x8",
+ argLen: 2,
generic: true,
},
{
- name: "MaxUint16x32",
- argLen: 2,
- commutative: true,
- generic: true,
+ name: "PermuteInt8x16",
+ argLen: 2,
+ generic: true,
},
{
- name: "MaxMaskedUint16x32",
- argLen: 3,
- commutative: true,
- generic: true,
+ name: "PermuteInt8x32",
+ argLen: 2,
+ generic: true,
},
{
- name: "MinUint16x32",
- argLen: 2,
- commutative: true,
- generic: true,
+ name: "PermuteInt8x64",
+ argLen: 2,
+ generic: true,
},
{
- name: "MinMaskedUint16x32",
- argLen: 3,
- commutative: true,
- generic: true,
+ name: "PermuteInt16x8",
+ argLen: 2,
+ generic: true,
},
{
- name: "MulHighUint16x32",
- argLen: 2,
- commutative: true,
- generic: true,
+ name: "PermuteInt16x16",
+ argLen: 2,
+ generic: true,
},
{
- name: "MulHighMaskedUint16x32",
- argLen: 3,
- commutative: true,
- generic: true,
+ name: "PermuteInt16x32",
+ argLen: 2,
+ generic: true,
},
{
- name: "NotEqualUint16x32",
- argLen: 2,
- commutative: true,
- generic: true,
+ name: "PermuteInt32x8",
+ argLen: 2,
+ generic: true,
},
{
- name: "NotEqualMaskedUint16x32",
- argLen: 3,
- commutative: true,
- generic: true,
+ name: "PermuteInt32x16",
+ argLen: 2,
+ generic: true,
},
{
- name: "PermuteUint16x32",
+ name: "PermuteInt64x4",
argLen: 2,
generic: true,
},
{
- name: "PermuteInt16x32",
+ name: "PermuteInt64x8",
argLen: 2,
generic: true,
},
{
- name: "Permute2Uint16x32",
+ name: "PermuteMaskedFloat32x8",
argLen: 3,
generic: true,
},
{
- name: "Permute2Int16x32",
+ name: "PermuteMaskedFloat32x16",
argLen: 3,
generic: true,
},
{
- name: "Permute2MaskedUint16x32",
- argLen: 4,
+ name: "PermuteMaskedFloat64x4",
+ argLen: 3,
generic: true,
},
{
- name: "Permute2MaskedInt16x32",
- argLen: 4,
+ name: "PermuteMaskedFloat64x8",
+ argLen: 3,
generic: true,
},
{
- name: "PermuteMaskedInt16x32",
+ name: "PermuteMaskedInt8x16",
argLen: 3,
generic: true,
},
{
- name: "PermuteMaskedUint16x32",
+ name: "PermuteMaskedInt8x32",
argLen: 3,
generic: true,
},
{
- name: "PopCountUint16x32",
- argLen: 1,
+ name: "PermuteMaskedInt8x64",
+ argLen: 3,
generic: true,
},
{
- name: "PopCountMaskedUint16x32",
- argLen: 2,
+ name: "PermuteMaskedInt16x8",
+ argLen: 3,
generic: true,
},
{
- name: "SaturatedAddUint16x32",
- argLen: 2,
- commutative: true,
- generic: true,
- },
- {
- name: "SaturatedAddMaskedUint16x32",
- argLen: 3,
- commutative: true,
- generic: true,
- },
- {
- name: "SaturatedSubUint16x32",
- argLen: 2,
+ name: "PermuteMaskedInt16x16",
+ argLen: 3,
generic: true,
},
{
- name: "SaturatedSubMaskedUint16x32",
+ name: "PermuteMaskedInt16x32",
argLen: 3,
generic: true,
},
{
- name: "ShiftAllLeftUint16x32",
- argLen: 2,
+ name: "PermuteMaskedInt32x8",
+ argLen: 3,
generic: true,
},
{
- name: "ShiftAllLeftMaskedUint16x32",
+ name: "PermuteMaskedInt32x16",
argLen: 3,
generic: true,
},
{
- name: "ShiftAllRightUint16x32",
- argLen: 2,
+ name: "PermuteMaskedInt64x4",
+ argLen: 3,
generic: true,
},
{
- name: "ShiftAllRightMaskedUint16x32",
+ name: "PermuteMaskedInt64x8",
argLen: 3,
generic: true,
},
{
- name: "ShiftLeftUint16x32",
- argLen: 2,
+ name: "PermuteMaskedUint8x16",
+ argLen: 3,
generic: true,
},
{
- name: "ShiftLeftAndFillUpperFromUint16x32",
+ name: "PermuteMaskedUint8x32",
argLen: 3,
generic: true,
},
{
- name: "ShiftLeftAndFillUpperFromMaskedUint16x32",
- argLen: 4,
+ name: "PermuteMaskedUint8x64",
+ argLen: 3,
generic: true,
},
{
- name: "ShiftLeftMaskedUint16x32",
+ name: "PermuteMaskedUint16x8",
argLen: 3,
generic: true,
},
{
- name: "ShiftRightUint16x32",
- argLen: 2,
+ name: "PermuteMaskedUint16x16",
+ argLen: 3,
generic: true,
},
{
- name: "ShiftRightAndFillUpperFromUint16x32",
+ name: "PermuteMaskedUint16x32",
argLen: 3,
generic: true,
},
{
- name: "ShiftRightAndFillUpperFromMaskedUint16x32",
- argLen: 4,
+ name: "PermuteMaskedUint32x8",
+ argLen: 3,
generic: true,
},
{
- name: "ShiftRightMaskedUint16x32",
+ name: "PermuteMaskedUint32x16",
argLen: 3,
generic: true,
},
{
- name: "SubUint16x32",
- argLen: 2,
+ name: "PermuteMaskedUint64x4",
+ argLen: 3,
generic: true,
},
{
- name: "SubMaskedUint16x32",
+ name: "PermuteMaskedUint64x8",
argLen: 3,
generic: true,
},
{
- name: "AddUint16x8",
- argLen: 2,
- commutative: true,
- generic: true,
- },
- {
- name: "AddMaskedUint16x8",
- argLen: 3,
- commutative: true,
- generic: true,
- },
- {
- name: "AndUint16x8",
- argLen: 2,
- commutative: true,
- generic: true,
- },
- {
- name: "AndNotUint16x8",
+ name: "PermuteUint8x16",
argLen: 2,
generic: true,
},
{
- name: "AverageUint16x8",
- argLen: 2,
- commutative: true,
- generic: true,
+ name: "PermuteUint8x32",
+ argLen: 2,
+ generic: true,
},
{
- name: "AverageMaskedUint16x8",
- argLen: 3,
- commutative: true,
- generic: true,
+ name: "PermuteUint8x64",
+ argLen: 2,
+ generic: true,
},
{
- name: "CompressUint16x8",
+ name: "PermuteUint16x8",
argLen: 2,
generic: true,
},
{
- name: "EqualUint16x8",
- argLen: 2,
- commutative: true,
- generic: true,
+ name: "PermuteUint16x16",
+ argLen: 2,
+ generic: true,
},
{
- name: "EqualMaskedUint16x8",
- argLen: 3,
- commutative: true,
- generic: true,
+ name: "PermuteUint16x32",
+ argLen: 2,
+ generic: true,
},
{
- name: "GreaterUint16x8",
+ name: "PermuteUint32x8",
argLen: 2,
generic: true,
},
{
- name: "GreaterEqualUint16x8",
+ name: "PermuteUint32x16",
argLen: 2,
generic: true,
},
{
- name: "GreaterEqualMaskedUint16x8",
- argLen: 3,
+ name: "PermuteUint64x4",
+ argLen: 2,
generic: true,
},
{
- name: "GreaterMaskedUint16x8",
- argLen: 3,
+ name: "PermuteUint64x8",
+ argLen: 2,
generic: true,
},
{
- name: "LessUint16x8",
- argLen: 2,
+ name: "PopCountInt8x16",
+ argLen: 1,
generic: true,
},
{
- name: "LessEqualUint16x8",
- argLen: 2,
+ name: "PopCountInt8x32",
+ argLen: 1,
generic: true,
},
{
- name: "LessEqualMaskedUint16x8",
- argLen: 3,
+ name: "PopCountInt8x64",
+ argLen: 1,
generic: true,
},
{
- name: "LessMaskedUint16x8",
- argLen: 3,
+ name: "PopCountInt16x8",
+ argLen: 1,
generic: true,
},
{
- name: "MaxUint16x8",
- argLen: 2,
- commutative: true,
- generic: true,
+ name: "PopCountInt16x16",
+ argLen: 1,
+ generic: true,
},
{
- name: "MaxMaskedUint16x8",
- argLen: 3,
- commutative: true,
- generic: true,
+ name: "PopCountInt16x32",
+ argLen: 1,
+ generic: true,
},
{
- name: "MinUint16x8",
- argLen: 2,
- commutative: true,
- generic: true,
+ name: "PopCountInt32x4",
+ argLen: 1,
+ generic: true,
},
{
- name: "MinMaskedUint16x8",
- argLen: 3,
- commutative: true,
- generic: true,
+ name: "PopCountInt32x8",
+ argLen: 1,
+ generic: true,
},
{
- name: "MulHighUint16x8",
- argLen: 2,
- commutative: true,
- generic: true,
+ name: "PopCountInt32x16",
+ argLen: 1,
+ generic: true,
},
{
- name: "MulHighMaskedUint16x8",
- argLen: 3,
- commutative: true,
- generic: true,
+ name: "PopCountInt64x2",
+ argLen: 1,
+ generic: true,
},
{
- name: "NotEqualUint16x8",
- argLen: 2,
- commutative: true,
- generic: true,
+ name: "PopCountInt64x4",
+ argLen: 1,
+ generic: true,
},
{
- name: "NotEqualMaskedUint16x8",
- argLen: 3,
- commutative: true,
- generic: true,
+ name: "PopCountInt64x8",
+ argLen: 1,
+ generic: true,
},
{
- name: "OrUint16x8",
- argLen: 2,
- commutative: true,
- generic: true,
+ name: "PopCountMaskedInt8x16",
+ argLen: 2,
+ generic: true,
},
{
- name: "PairwiseAddUint16x8",
+ name: "PopCountMaskedInt8x32",
argLen: 2,
generic: true,
},
{
- name: "PairwiseSubUint16x8",
+ name: "PopCountMaskedInt8x64",
argLen: 2,
generic: true,
},
{
- name: "PermuteInt16x8",
+ name: "PopCountMaskedInt16x8",
argLen: 2,
generic: true,
},
{
- name: "PermuteUint16x8",
+ name: "PopCountMaskedInt16x16",
argLen: 2,
generic: true,
},
{
- name: "Permute2Uint16x8",
- argLen: 3,
+ name: "PopCountMaskedInt16x32",
+ argLen: 2,
generic: true,
},
{
- name: "Permute2Int16x8",
- argLen: 3,
+ name: "PopCountMaskedInt32x4",
+ argLen: 2,
generic: true,
},
{
- name: "Permute2MaskedInt16x8",
- argLen: 4,
+ name: "PopCountMaskedInt32x8",
+ argLen: 2,
generic: true,
},
{
- name: "Permute2MaskedUint16x8",
- argLen: 4,
+ name: "PopCountMaskedInt32x16",
+ argLen: 2,
generic: true,
},
{
- name: "PermuteMaskedInt16x8",
- argLen: 3,
+ name: "PopCountMaskedInt64x2",
+ argLen: 2,
generic: true,
},
{
- name: "PermuteMaskedUint16x8",
- argLen: 3,
+ name: "PopCountMaskedInt64x4",
+ argLen: 2,
generic: true,
},
{
- name: "PopCountUint16x8",
- argLen: 1,
+ name: "PopCountMaskedInt64x8",
+ argLen: 2,
generic: true,
},
{
- name: "PopCountMaskedUint16x8",
+ name: "PopCountMaskedUint8x16",
argLen: 2,
generic: true,
},
{
- name: "SaturatedAddUint16x8",
- argLen: 2,
- commutative: true,
- generic: true,
+ name: "PopCountMaskedUint8x32",
+ argLen: 2,
+ generic: true,
},
{
- name: "SaturatedAddMaskedUint16x8",
- argLen: 3,
- commutative: true,
- generic: true,
+ name: "PopCountMaskedUint8x64",
+ argLen: 2,
+ generic: true,
},
{
- name: "SaturatedSubUint16x8",
+ name: "PopCountMaskedUint16x8",
argLen: 2,
generic: true,
},
{
- name: "SaturatedSubMaskedUint16x8",
- argLen: 3,
+ name: "PopCountMaskedUint16x16",
+ argLen: 2,
generic: true,
},
{
- name: "ShiftAllLeftUint16x8",
+ name: "PopCountMaskedUint16x32",
argLen: 2,
generic: true,
},
{
- name: "ShiftAllLeftMaskedUint16x8",
- argLen: 3,
+ name: "PopCountMaskedUint32x4",
+ argLen: 2,
generic: true,
},
{
- name: "ShiftAllRightUint16x8",
+ name: "PopCountMaskedUint32x8",
argLen: 2,
generic: true,
},
{
- name: "ShiftAllRightMaskedUint16x8",
- argLen: 3,
+ name: "PopCountMaskedUint32x16",
+ argLen: 2,
generic: true,
},
{
- name: "ShiftLeftUint16x8",
+ name: "PopCountMaskedUint64x2",
argLen: 2,
generic: true,
},
{
- name: "ShiftLeftAndFillUpperFromUint16x8",
- argLen: 3,
+ name: "PopCountMaskedUint64x4",
+ argLen: 2,
generic: true,
},
{
- name: "ShiftLeftAndFillUpperFromMaskedUint16x8",
- argLen: 4,
+ name: "PopCountMaskedUint64x8",
+ argLen: 2,
generic: true,
},
{
- name: "ShiftLeftMaskedUint16x8",
- argLen: 3,
+ name: "PopCountUint8x16",
+ argLen: 1,
generic: true,
},
{
- name: "ShiftRightUint16x8",
- argLen: 2,
+ name: "PopCountUint8x32",
+ argLen: 1,
generic: true,
},
{
- name: "ShiftRightAndFillUpperFromUint16x8",
- argLen: 3,
+ name: "PopCountUint8x64",
+ argLen: 1,
generic: true,
},
{
- name: "ShiftRightAndFillUpperFromMaskedUint16x8",
- argLen: 4,
+ name: "PopCountUint16x8",
+ argLen: 1,
generic: true,
},
{
- name: "ShiftRightMaskedUint16x8",
- argLen: 3,
+ name: "PopCountUint16x16",
+ argLen: 1,
generic: true,
},
{
- name: "SubUint16x8",
- argLen: 2,
+ name: "PopCountUint16x32",
+ argLen: 1,
generic: true,
},
{
- name: "SubMaskedUint16x8",
- argLen: 3,
+ name: "PopCountUint32x4",
+ argLen: 1,
generic: true,
},
{
- name: "XorUint16x8",
- argLen: 2,
- commutative: true,
- generic: true,
+ name: "PopCountUint32x8",
+ argLen: 1,
+ generic: true,
},
{
- name: "AddUint32x16",
- argLen: 2,
- commutative: true,
- generic: true,
+ name: "PopCountUint32x16",
+ argLen: 1,
+ generic: true,
},
{
- name: "AddMaskedUint32x16",
- argLen: 3,
- commutative: true,
- generic: true,
+ name: "PopCountUint64x2",
+ argLen: 1,
+ generic: true,
},
{
- name: "AndUint32x16",
- argLen: 2,
- commutative: true,
- generic: true,
+ name: "PopCountUint64x4",
+ argLen: 1,
+ generic: true,
},
{
- name: "AndMaskedUint32x16",
- argLen: 3,
- commutative: true,
- generic: true,
+ name: "PopCountUint64x8",
+ argLen: 1,
+ generic: true,
},
{
- name: "AndNotUint32x16",
+ name: "RotateLeftInt32x4",
argLen: 2,
generic: true,
},
{
- name: "AndNotMaskedUint32x16",
- argLen: 3,
+ name: "RotateLeftInt32x8",
+ argLen: 2,
generic: true,
},
{
- name: "CompressUint32x16",
+ name: "RotateLeftInt32x16",
argLen: 2,
generic: true,
},
{
- name: "EqualUint32x16",
- argLen: 2,
- commutative: true,
- generic: true,
- },
- {
- name: "EqualMaskedUint32x16",
- argLen: 3,
- commutative: true,
- generic: true,
+ name: "RotateLeftInt64x2",
+ argLen: 2,
+ generic: true,
},
{
- name: "GreaterUint32x16",
+ name: "RotateLeftInt64x4",
argLen: 2,
generic: true,
},
{
- name: "GreaterEqualUint32x16",
+ name: "RotateLeftInt64x8",
argLen: 2,
generic: true,
},
{
- name: "GreaterEqualMaskedUint32x16",
+ name: "RotateLeftMaskedInt32x4",
argLen: 3,
generic: true,
},
{
- name: "GreaterMaskedUint32x16",
+ name: "RotateLeftMaskedInt32x8",
argLen: 3,
generic: true,
},
{
- name: "LessUint32x16",
- argLen: 2,
+ name: "RotateLeftMaskedInt32x16",
+ argLen: 3,
generic: true,
},
{
- name: "LessEqualUint32x16",
- argLen: 2,
+ name: "RotateLeftMaskedInt64x2",
+ argLen: 3,
generic: true,
},
{
- name: "LessEqualMaskedUint32x16",
+ name: "RotateLeftMaskedInt64x4",
argLen: 3,
generic: true,
},
{
- name: "LessMaskedUint32x16",
+ name: "RotateLeftMaskedInt64x8",
argLen: 3,
generic: true,
},
{
- name: "MaxUint32x16",
- argLen: 2,
- commutative: true,
- generic: true,
+ name: "RotateLeftMaskedUint32x4",
+ argLen: 3,
+ generic: true,
},
{
- name: "MaxMaskedUint32x16",
- argLen: 3,
- commutative: true,
- generic: true,
+ name: "RotateLeftMaskedUint32x8",
+ argLen: 3,
+ generic: true,
},
{
- name: "MinUint32x16",
- argLen: 2,
- commutative: true,
- generic: true,
+ name: "RotateLeftMaskedUint32x16",
+ argLen: 3,
+ generic: true,
},
{
- name: "MinMaskedUint32x16",
- argLen: 3,
- commutative: true,
- generic: true,
+ name: "RotateLeftMaskedUint64x2",
+ argLen: 3,
+ generic: true,
},
{
- name: "NotEqualUint32x16",
- argLen: 2,
- commutative: true,
- generic: true,
+ name: "RotateLeftMaskedUint64x4",
+ argLen: 3,
+ generic: true,
},
{
- name: "NotEqualMaskedUint32x16",
- argLen: 3,
- commutative: true,
- generic: true,
+ name: "RotateLeftMaskedUint64x8",
+ argLen: 3,
+ generic: true,
},
{
- name: "OrUint32x16",
- argLen: 2,
- commutative: true,
- generic: true,
+ name: "RotateLeftUint32x4",
+ argLen: 2,
+ generic: true,
},
{
- name: "OrMaskedUint32x16",
- argLen: 3,
- commutative: true,
- generic: true,
+ name: "RotateLeftUint32x8",
+ argLen: 2,
+ generic: true,
},
{
- name: "PermuteInt32x16",
+ name: "RotateLeftUint32x16",
argLen: 2,
generic: true,
},
{
- name: "PermuteFloat32x16",
+ name: "RotateLeftUint64x2",
argLen: 2,
generic: true,
},
{
- name: "PermuteUint32x16",
+ name: "RotateLeftUint64x4",
argLen: 2,
generic: true,
},
{
- name: "Permute2Uint32x16",
- argLen: 3,
+ name: "RotateLeftUint64x8",
+ argLen: 2,
generic: true,
},
{
- name: "Permute2Float32x16",
- argLen: 3,
+ name: "RotateRightInt32x4",
+ argLen: 2,
generic: true,
},
{
- name: "Permute2Int32x16",
- argLen: 3,
+ name: "RotateRightInt32x8",
+ argLen: 2,
generic: true,
},
{
- name: "Permute2MaskedUint32x16",
- argLen: 4,
+ name: "RotateRightInt32x16",
+ argLen: 2,
generic: true,
},
{
- name: "Permute2MaskedInt32x16",
- argLen: 4,
+ name: "RotateRightInt64x2",
+ argLen: 2,
generic: true,
},
{
- name: "Permute2MaskedFloat32x16",
- argLen: 4,
+ name: "RotateRightInt64x4",
+ argLen: 2,
generic: true,
},
{
- name: "PermuteMaskedFloat32x16",
- argLen: 3,
+ name: "RotateRightInt64x8",
+ argLen: 2,
generic: true,
},
{
- name: "PermuteMaskedInt32x16",
+ name: "RotateRightMaskedInt32x4",
argLen: 3,
generic: true,
},
{
- name: "PermuteMaskedUint32x16",
+ name: "RotateRightMaskedInt32x8",
argLen: 3,
generic: true,
},
{
- name: "PopCountUint32x16",
- argLen: 1,
+ name: "RotateRightMaskedInt32x16",
+ argLen: 3,
generic: true,
},
{
- name: "PopCountMaskedUint32x16",
- argLen: 2,
+ name: "RotateRightMaskedInt64x2",
+ argLen: 3,
generic: true,
},
{
- name: "RotateLeftUint32x16",
- argLen: 2,
+ name: "RotateRightMaskedInt64x4",
+ argLen: 3,
generic: true,
},
{
- name: "RotateLeftMaskedUint32x16",
+ name: "RotateRightMaskedInt64x8",
argLen: 3,
generic: true,
},
{
- name: "RotateRightUint32x16",
- argLen: 2,
+ name: "RotateRightMaskedUint32x4",
+ argLen: 3,
generic: true,
},
{
- name: "RotateRightMaskedUint32x16",
+ name: "RotateRightMaskedUint32x8",
argLen: 3,
generic: true,
},
{
- name: "ShiftAllLeftUint32x16",
- argLen: 2,
+ name: "RotateRightMaskedUint32x16",
+ argLen: 3,
generic: true,
},
{
- name: "ShiftAllLeftMaskedUint32x16",
+ name: "RotateRightMaskedUint64x2",
argLen: 3,
generic: true,
},
{
- name: "ShiftAllRightUint32x16",
- argLen: 2,
+ name: "RotateRightMaskedUint64x4",
+ argLen: 3,
generic: true,
},
{
- name: "ShiftAllRightMaskedUint32x16",
+ name: "RotateRightMaskedUint64x8",
argLen: 3,
generic: true,
},
{
- name: "ShiftLeftUint32x16",
+ name: "RotateRightUint32x4",
argLen: 2,
generic: true,
},
{
- name: "ShiftLeftAndFillUpperFromUint32x16",
- argLen: 3,
+ name: "RotateRightUint32x8",
+ argLen: 2,
generic: true,
},
{
- name: "ShiftLeftAndFillUpperFromMaskedUint32x16",
- argLen: 4,
+ name: "RotateRightUint32x16",
+ argLen: 2,
generic: true,
},
{
- name: "ShiftLeftMaskedUint32x16",
- argLen: 3,
+ name: "RotateRightUint64x2",
+ argLen: 2,
generic: true,
},
{
- name: "ShiftRightUint32x16",
+ name: "RotateRightUint64x4",
argLen: 2,
generic: true,
},
{
- name: "ShiftRightAndFillUpperFromUint32x16",
- argLen: 3,
+ name: "RotateRightUint64x8",
+ argLen: 2,
generic: true,
},
{
- name: "ShiftRightAndFillUpperFromMaskedUint32x16",
- argLen: 4,
+ name: "RoundFloat32x4",
+ argLen: 1,
generic: true,
},
{
- name: "ShiftRightMaskedUint32x16",
- argLen: 3,
+ name: "RoundFloat32x8",
+ argLen: 1,
generic: true,
},
{
- name: "SubUint32x16",
- argLen: 2,
+ name: "RoundFloat64x2",
+ argLen: 1,
generic: true,
},
{
- name: "SubMaskedUint32x16",
- argLen: 3,
+ name: "RoundFloat64x4",
+ argLen: 1,
generic: true,
},
{
- name: "XorUint32x16",
+ name: "SaturatedAddInt8x16",
argLen: 2,
commutative: true,
generic: true,
},
{
- name: "XorMaskedUint32x16",
- argLen: 3,
+ name: "SaturatedAddInt8x32",
+ argLen: 2,
commutative: true,
generic: true,
},
{
- name: "AddUint32x4",
+ name: "SaturatedAddInt8x64",
argLen: 2,
commutative: true,
generic: true,
},
{
- name: "AddMaskedUint32x4",
- argLen: 3,
+ name: "SaturatedAddInt16x8",
+ argLen: 2,
commutative: true,
generic: true,
},
{
- name: "AndUint32x4",
+ name: "SaturatedAddInt16x16",
argLen: 2,
commutative: true,
generic: true,
},
{
- name: "AndMaskedUint32x4",
- argLen: 3,
+ name: "SaturatedAddInt16x32",
+ argLen: 2,
commutative: true,
generic: true,
},
{
- name: "AndNotUint32x4",
- argLen: 2,
- generic: true,
- },
- {
- name: "AndNotMaskedUint32x4",
- argLen: 3,
- generic: true,
- },
- {
- name: "CompressUint32x4",
- argLen: 2,
- generic: true,
- },
- {
- name: "EqualUint32x4",
- argLen: 2,
+ name: "SaturatedAddMaskedInt8x16",
+ argLen: 3,
commutative: true,
generic: true,
},
{
- name: "EqualMaskedUint32x4",
+ name: "SaturatedAddMaskedInt8x32",
argLen: 3,
commutative: true,
generic: true,
},
{
- name: "GreaterUint32x4",
- argLen: 2,
- generic: true,
- },
- {
- name: "GreaterEqualUint32x4",
- argLen: 2,
- generic: true,
- },
- {
- name: "GreaterEqualMaskedUint32x4",
- argLen: 3,
- generic: true,
+ name: "SaturatedAddMaskedInt8x64",
+ argLen: 3,
+ commutative: true,
+ generic: true,
},
{
- name: "GreaterMaskedUint32x4",
- argLen: 3,
- generic: true,
+ name: "SaturatedAddMaskedInt16x8",
+ argLen: 3,
+ commutative: true,
+ generic: true,
},
{
- name: "LessUint32x4",
- argLen: 2,
- generic: true,
+ name: "SaturatedAddMaskedInt16x16",
+ argLen: 3,
+ commutative: true,
+ generic: true,
},
{
- name: "LessEqualUint32x4",
- argLen: 2,
- generic: true,
+ name: "SaturatedAddMaskedInt16x32",
+ argLen: 3,
+ commutative: true,
+ generic: true,
},
{
- name: "LessEqualMaskedUint32x4",
- argLen: 3,
- generic: true,
+ name: "SaturatedAddMaskedUint8x16",
+ argLen: 3,
+ commutative: true,
+ generic: true,
},
{
- name: "LessMaskedUint32x4",
- argLen: 3,
- generic: true,
+ name: "SaturatedAddMaskedUint8x32",
+ argLen: 3,
+ commutative: true,
+ generic: true,
},
{
- name: "MaxUint32x4",
- argLen: 2,
+ name: "SaturatedAddMaskedUint8x64",
+ argLen: 3,
commutative: true,
generic: true,
},
{
- name: "MaxMaskedUint32x4",
+ name: "SaturatedAddMaskedUint16x8",
argLen: 3,
commutative: true,
generic: true,
},
{
- name: "MinUint32x4",
- argLen: 2,
+ name: "SaturatedAddMaskedUint16x16",
+ argLen: 3,
commutative: true,
generic: true,
},
{
- name: "MinMaskedUint32x4",
+ name: "SaturatedAddMaskedUint16x32",
argLen: 3,
commutative: true,
generic: true,
},
{
- name: "MulEvenWidenUint32x4",
+ name: "SaturatedAddUint8x16",
argLen: 2,
commutative: true,
generic: true,
},
{
- name: "NotEqualUint32x4",
+ name: "SaturatedAddUint8x32",
argLen: 2,
commutative: true,
generic: true,
},
{
- name: "NotEqualMaskedUint32x4",
- argLen: 3,
+ name: "SaturatedAddUint8x64",
+ argLen: 2,
commutative: true,
generic: true,
},
{
- name: "OrUint32x4",
+ name: "SaturatedAddUint16x8",
argLen: 2,
commutative: true,
generic: true,
},
{
- name: "OrMaskedUint32x4",
- argLen: 3,
+ name: "SaturatedAddUint16x16",
+ argLen: 2,
commutative: true,
generic: true,
},
{
- name: "PairwiseAddUint32x4",
- argLen: 2,
- generic: true,
- },
- {
- name: "PairwiseSubUint32x4",
- argLen: 2,
- generic: true,
- },
- {
- name: "Permute2Float32x4",
- argLen: 3,
- generic: true,
+ name: "SaturatedAddUint16x32",
+ argLen: 2,
+ commutative: true,
+ generic: true,
},
{
- name: "Permute2Uint32x4",
+ name: "SaturatedPairDotProdAccumulateInt32x4",
argLen: 3,
generic: true,
},
{
- name: "Permute2Int32x4",
+ name: "SaturatedPairDotProdAccumulateInt32x8",
argLen: 3,
generic: true,
},
{
- name: "Permute2MaskedInt32x4",
- argLen: 4,
+ name: "SaturatedPairDotProdAccumulateInt32x16",
+ argLen: 3,
generic: true,
},
{
- name: "Permute2MaskedUint32x4",
+ name: "SaturatedPairDotProdAccumulateMaskedInt32x4",
argLen: 4,
generic: true,
},
{
- name: "Permute2MaskedFloat32x4",
+ name: "SaturatedPairDotProdAccumulateMaskedInt32x8",
argLen: 4,
generic: true,
},
{
- name: "PopCountUint32x4",
- argLen: 1,
+ name: "SaturatedPairDotProdAccumulateMaskedInt32x16",
+ argLen: 4,
generic: true,
},
{
- name: "PopCountMaskedUint32x4",
+ name: "SaturatedPairwiseAddInt16x8",
argLen: 2,
generic: true,
},
{
- name: "RotateLeftUint32x4",
+ name: "SaturatedPairwiseAddInt16x16",
argLen: 2,
generic: true,
},
{
- name: "RotateLeftMaskedUint32x4",
- argLen: 3,
+ name: "SaturatedPairwiseSubInt16x8",
+ argLen: 2,
generic: true,
},
{
- name: "RotateRightUint32x4",
+ name: "SaturatedPairwiseSubInt16x16",
argLen: 2,
generic: true,
},
{
- name: "RotateRightMaskedUint32x4",
- argLen: 3,
+ name: "SaturatedSubInt8x16",
+ argLen: 2,
generic: true,
},
{
- name: "ShiftAllLeftUint32x4",
+ name: "SaturatedSubInt8x32",
argLen: 2,
generic: true,
},
{
- name: "ShiftAllLeftMaskedUint32x4",
- argLen: 3,
+ name: "SaturatedSubInt8x64",
+ argLen: 2,
generic: true,
},
{
- name: "ShiftAllRightUint32x4",
+ name: "SaturatedSubInt16x8",
argLen: 2,
generic: true,
},
{
- name: "ShiftAllRightMaskedUint32x4",
- argLen: 3,
+ name: "SaturatedSubInt16x16",
+ argLen: 2,
generic: true,
},
{
- name: "ShiftLeftUint32x4",
+ name: "SaturatedSubInt16x32",
argLen: 2,
generic: true,
},
{
- name: "ShiftLeftAndFillUpperFromUint32x4",
+ name: "SaturatedSubMaskedInt8x16",
argLen: 3,
generic: true,
},
{
- name: "ShiftLeftAndFillUpperFromMaskedUint32x4",
- argLen: 4,
+ name: "SaturatedSubMaskedInt8x32",
+ argLen: 3,
generic: true,
},
{
- name: "ShiftLeftMaskedUint32x4",
+ name: "SaturatedSubMaskedInt8x64",
argLen: 3,
generic: true,
},
{
- name: "ShiftRightUint32x4",
- argLen: 2,
+ name: "SaturatedSubMaskedInt16x8",
+ argLen: 3,
generic: true,
},
{
- name: "ShiftRightAndFillUpperFromUint32x4",
+ name: "SaturatedSubMaskedInt16x16",
argLen: 3,
generic: true,
},
{
- name: "ShiftRightAndFillUpperFromMaskedUint32x4",
- argLen: 4,
+ name: "SaturatedSubMaskedInt16x32",
+ argLen: 3,
generic: true,
},
{
- name: "ShiftRightMaskedUint32x4",
+ name: "SaturatedSubMaskedUint8x16",
argLen: 3,
generic: true,
},
{
- name: "SubUint32x4",
- argLen: 2,
+ name: "SaturatedSubMaskedUint8x32",
+ argLen: 3,
generic: true,
},
{
- name: "SubMaskedUint32x4",
+ name: "SaturatedSubMaskedUint8x64",
argLen: 3,
generic: true,
},
{
- name: "XorUint32x4",
- argLen: 2,
- commutative: true,
- generic: true,
- },
- {
- name: "XorMaskedUint32x4",
- argLen: 3,
- commutative: true,
- generic: true,
- },
- {
- name: "AddUint32x8",
- argLen: 2,
- commutative: true,
- generic: true,
- },
- {
- name: "AddMaskedUint32x8",
- argLen: 3,
- commutative: true,
- generic: true,
+ name: "SaturatedSubMaskedUint16x8",
+ argLen: 3,
+ generic: true,
},
{
- name: "AndUint32x8",
- argLen: 2,
- commutative: true,
- generic: true,
+ name: "SaturatedSubMaskedUint16x16",
+ argLen: 3,
+ generic: true,
},
{
- name: "AndMaskedUint32x8",
- argLen: 3,
- commutative: true,
- generic: true,
+ name: "SaturatedSubMaskedUint16x32",
+ argLen: 3,
+ generic: true,
},
{
- name: "AndNotUint32x8",
+ name: "SaturatedSubUint8x16",
argLen: 2,
generic: true,
},
{
- name: "AndNotMaskedUint32x8",
- argLen: 3,
+ name: "SaturatedSubUint8x32",
+ argLen: 2,
generic: true,
},
{
- name: "CompressUint32x8",
+ name: "SaturatedSubUint8x64",
argLen: 2,
generic: true,
},
{
- name: "EqualUint32x8",
- argLen: 2,
- commutative: true,
- generic: true,
+ name: "SaturatedSubUint16x8",
+ argLen: 2,
+ generic: true,
},
{
- name: "EqualMaskedUint32x8",
- argLen: 3,
- commutative: true,
- generic: true,
+ name: "SaturatedSubUint16x16",
+ argLen: 2,
+ generic: true,
},
{
- name: "GreaterUint32x8",
+ name: "SaturatedSubUint16x32",
argLen: 2,
generic: true,
},
{
- name: "GreaterEqualUint32x8",
- argLen: 2,
+ name: "SaturatedUnsignedSignedPairDotProdMaskedUint8x16",
+ argLen: 3,
generic: true,
},
{
- name: "GreaterEqualMaskedUint32x8",
+ name: "SaturatedUnsignedSignedPairDotProdMaskedUint8x32",
argLen: 3,
generic: true,
},
{
- name: "GreaterMaskedUint32x8",
+ name: "SaturatedUnsignedSignedPairDotProdMaskedUint8x64",
argLen: 3,
generic: true,
},
{
- name: "LessUint32x8",
+ name: "SaturatedUnsignedSignedPairDotProdUint8x16",
argLen: 2,
generic: true,
},
{
- name: "LessEqualUint32x8",
+ name: "SaturatedUnsignedSignedPairDotProdUint8x32",
argLen: 2,
generic: true,
},
{
- name: "LessEqualMaskedUint32x8",
- argLen: 3,
+ name: "SaturatedUnsignedSignedPairDotProdUint8x64",
+ argLen: 2,
generic: true,
},
{
- name: "LessMaskedUint32x8",
+ name: "SaturatedUnsignedSignedQuadDotProdAccumulateInt32x4",
argLen: 3,
generic: true,
},
{
- name: "MaxUint32x8",
- argLen: 2,
- commutative: true,
- generic: true,
- },
- {
- name: "MaxMaskedUint32x8",
- argLen: 3,
- commutative: true,
- generic: true,
+ name: "SaturatedUnsignedSignedQuadDotProdAccumulateInt32x8",
+ argLen: 3,
+ generic: true,
},
{
- name: "MinUint32x8",
- argLen: 2,
- commutative: true,
- generic: true,
+ name: "SaturatedUnsignedSignedQuadDotProdAccumulateInt32x16",
+ argLen: 3,
+ generic: true,
},
{
- name: "MinMaskedUint32x8",
- argLen: 3,
- commutative: true,
- generic: true,
+ name: "SaturatedUnsignedSignedQuadDotProdAccumulateMaskedInt32x4",
+ argLen: 4,
+ generic: true,
},
{
- name: "MulEvenWidenUint32x8",
- argLen: 2,
- commutative: true,
- generic: true,
+ name: "SaturatedUnsignedSignedQuadDotProdAccumulateMaskedInt32x8",
+ argLen: 4,
+ generic: true,
},
{
- name: "NotEqualUint32x8",
- argLen: 2,
- commutative: true,
- generic: true,
+ name: "SaturatedUnsignedSignedQuadDotProdAccumulateMaskedInt32x16",
+ argLen: 4,
+ generic: true,
},
{
- name: "NotEqualMaskedUint32x8",
- argLen: 3,
- commutative: true,
- generic: true,
+ name: "ShiftAllLeftInt16x8",
+ argLen: 2,
+ generic: true,
},
{
- name: "OrUint32x8",
- argLen: 2,
- commutative: true,
- generic: true,
+ name: "ShiftAllLeftInt16x16",
+ argLen: 2,
+ generic: true,
},
{
- name: "OrMaskedUint32x8",
- argLen: 3,
- commutative: true,
- generic: true,
+ name: "ShiftAllLeftInt16x32",
+ argLen: 2,
+ generic: true,
},
{
- name: "PairwiseAddUint32x8",
+ name: "ShiftAllLeftInt32x4",
argLen: 2,
generic: true,
},
{
- name: "PairwiseSubUint32x8",
+ name: "ShiftAllLeftInt32x8",
argLen: 2,
generic: true,
},
{
- name: "PermuteUint32x8",
+ name: "ShiftAllLeftInt32x16",
argLen: 2,
generic: true,
},
{
- name: "PermuteFloat32x8",
+ name: "ShiftAllLeftInt64x2",
argLen: 2,
generic: true,
},
{
- name: "PermuteInt32x8",
+ name: "ShiftAllLeftInt64x4",
argLen: 2,
generic: true,
},
{
- name: "Permute2Int32x8",
- argLen: 3,
+ name: "ShiftAllLeftInt64x8",
+ argLen: 2,
generic: true,
},
{
- name: "Permute2Float32x8",
+ name: "ShiftAllLeftMaskedInt16x8",
argLen: 3,
generic: true,
},
{
- name: "Permute2Uint32x8",
+ name: "ShiftAllLeftMaskedInt16x16",
argLen: 3,
generic: true,
},
{
- name: "Permute2MaskedFloat32x8",
- argLen: 4,
+ name: "ShiftAllLeftMaskedInt16x32",
+ argLen: 3,
generic: true,
},
{
- name: "Permute2MaskedUint32x8",
- argLen: 4,
+ name: "ShiftAllLeftMaskedInt32x4",
+ argLen: 3,
generic: true,
},
{
- name: "Permute2MaskedInt32x8",
- argLen: 4,
+ name: "ShiftAllLeftMaskedInt32x8",
+ argLen: 3,
generic: true,
},
{
- name: "PermuteMaskedInt32x8",
+ name: "ShiftAllLeftMaskedInt32x16",
argLen: 3,
generic: true,
},
{
- name: "PermuteMaskedUint32x8",
+ name: "ShiftAllLeftMaskedInt64x2",
argLen: 3,
generic: true,
},
{
- name: "PermuteMaskedFloat32x8",
+ name: "ShiftAllLeftMaskedInt64x4",
argLen: 3,
generic: true,
},
{
- name: "PopCountUint32x8",
- argLen: 1,
+ name: "ShiftAllLeftMaskedInt64x8",
+ argLen: 3,
generic: true,
},
{
- name: "PopCountMaskedUint32x8",
- argLen: 2,
+ name: "ShiftAllLeftMaskedUint16x8",
+ argLen: 3,
generic: true,
},
{
- name: "RotateLeftUint32x8",
- argLen: 2,
+ name: "ShiftAllLeftMaskedUint16x16",
+ argLen: 3,
generic: true,
},
{
- name: "RotateLeftMaskedUint32x8",
+ name: "ShiftAllLeftMaskedUint16x32",
argLen: 3,
generic: true,
},
{
- name: "RotateRightUint32x8",
- argLen: 2,
+ name: "ShiftAllLeftMaskedUint32x4",
+ argLen: 3,
generic: true,
},
{
- name: "RotateRightMaskedUint32x8",
+ name: "ShiftAllLeftMaskedUint32x8",
argLen: 3,
generic: true,
},
{
- name: "ShiftAllLeftUint32x8",
- argLen: 2,
+ name: "ShiftAllLeftMaskedUint32x16",
+ argLen: 3,
generic: true,
},
{
- name: "ShiftAllLeftMaskedUint32x8",
+ name: "ShiftAllLeftMaskedUint64x2",
argLen: 3,
generic: true,
},
{
- name: "ShiftAllRightUint32x8",
- argLen: 2,
+ name: "ShiftAllLeftMaskedUint64x4",
+ argLen: 3,
generic: true,
},
{
- name: "ShiftAllRightMaskedUint32x8",
+ name: "ShiftAllLeftMaskedUint64x8",
argLen: 3,
generic: true,
},
{
- name: "ShiftLeftUint32x8",
+ name: "ShiftAllLeftUint16x8",
argLen: 2,
generic: true,
},
{
- name: "ShiftLeftAndFillUpperFromUint32x8",
- argLen: 3,
+ name: "ShiftAllLeftUint16x16",
+ argLen: 2,
generic: true,
},
{
- name: "ShiftLeftAndFillUpperFromMaskedUint32x8",
- argLen: 4,
+ name: "ShiftAllLeftUint16x32",
+ argLen: 2,
generic: true,
},
{
- name: "ShiftLeftMaskedUint32x8",
- argLen: 3,
+ name: "ShiftAllLeftUint32x4",
+ argLen: 2,
generic: true,
},
{
- name: "ShiftRightUint32x8",
+ name: "ShiftAllLeftUint32x8",
argLen: 2,
generic: true,
},
{
- name: "ShiftRightAndFillUpperFromUint32x8",
- argLen: 3,
+ name: "ShiftAllLeftUint32x16",
+ argLen: 2,
generic: true,
},
{
- name: "ShiftRightAndFillUpperFromMaskedUint32x8",
- argLen: 4,
+ name: "ShiftAllLeftUint64x2",
+ argLen: 2,
generic: true,
},
{
- name: "ShiftRightMaskedUint32x8",
- argLen: 3,
+ name: "ShiftAllLeftUint64x4",
+ argLen: 2,
generic: true,
},
{
- name: "SubUint32x8",
+ name: "ShiftAllLeftUint64x8",
argLen: 2,
generic: true,
},
{
- name: "SubMaskedUint32x8",
- argLen: 3,
+ name: "ShiftAllRightInt16x8",
+ argLen: 2,
generic: true,
},
{
- name: "XorUint32x8",
- argLen: 2,
- commutative: true,
- generic: true,
- },
- {
- name: "XorMaskedUint32x8",
- argLen: 3,
- commutative: true,
- generic: true,
- },
- {
- name: "AddUint64x2",
- argLen: 2,
- commutative: true,
- generic: true,
- },
- {
- name: "AddMaskedUint64x2",
- argLen: 3,
- commutative: true,
- generic: true,
- },
- {
- name: "AndUint64x2",
- argLen: 2,
- commutative: true,
- generic: true,
- },
- {
- name: "AndMaskedUint64x2",
- argLen: 3,
- commutative: true,
- generic: true,
+ name: "ShiftAllRightInt16x16",
+ argLen: 2,
+ generic: true,
},
{
- name: "AndNotUint64x2",
+ name: "ShiftAllRightInt16x32",
argLen: 2,
generic: true,
},
{
- name: "AndNotMaskedUint64x2",
- argLen: 3,
+ name: "ShiftAllRightInt32x4",
+ argLen: 2,
generic: true,
},
{
- name: "CompressUint64x2",
+ name: "ShiftAllRightInt32x8",
argLen: 2,
generic: true,
},
{
- name: "EqualUint64x2",
- argLen: 2,
- commutative: true,
- generic: true,
+ name: "ShiftAllRightInt32x16",
+ argLen: 2,
+ generic: true,
},
{
- name: "EqualMaskedUint64x2",
- argLen: 3,
- commutative: true,
- generic: true,
+ name: "ShiftAllRightInt64x2",
+ argLen: 2,
+ generic: true,
},
{
- name: "GreaterUint64x2",
+ name: "ShiftAllRightInt64x4",
argLen: 2,
generic: true,
},
{
- name: "GreaterEqualUint64x2",
+ name: "ShiftAllRightInt64x8",
argLen: 2,
generic: true,
},
{
- name: "GreaterEqualMaskedUint64x2",
+ name: "ShiftAllRightMaskedInt16x8",
argLen: 3,
generic: true,
},
{
- name: "GreaterMaskedUint64x2",
+ name: "ShiftAllRightMaskedInt16x16",
argLen: 3,
generic: true,
},
{
- name: "LessUint64x2",
- argLen: 2,
+ name: "ShiftAllRightMaskedInt16x32",
+ argLen: 3,
generic: true,
},
{
- name: "LessEqualUint64x2",
- argLen: 2,
+ name: "ShiftAllRightMaskedInt32x4",
+ argLen: 3,
generic: true,
},
{
- name: "LessEqualMaskedUint64x2",
+ name: "ShiftAllRightMaskedInt32x8",
argLen: 3,
generic: true,
},
{
- name: "LessMaskedUint64x2",
+ name: "ShiftAllRightMaskedInt32x16",
argLen: 3,
generic: true,
},
{
- name: "MaxUint64x2",
- argLen: 2,
- commutative: true,
- generic: true,
- },
- {
- name: "MaxMaskedUint64x2",
- argLen: 3,
- commutative: true,
- generic: true,
- },
- {
- name: "MinUint64x2",
- argLen: 2,
- commutative: true,
- generic: true,
+ name: "ShiftAllRightMaskedInt64x2",
+ argLen: 3,
+ generic: true,
},
{
- name: "MinMaskedUint64x2",
- argLen: 3,
- commutative: true,
- generic: true,
+ name: "ShiftAllRightMaskedInt64x4",
+ argLen: 3,
+ generic: true,
},
{
- name: "MulEvenWidenUint64x2",
- argLen: 2,
- commutative: true,
- generic: true,
+ name: "ShiftAllRightMaskedInt64x8",
+ argLen: 3,
+ generic: true,
},
{
- name: "MulEvenWidenMaskedUint64x2",
- argLen: 3,
- commutative: true,
- generic: true,
+ name: "ShiftAllRightMaskedUint16x8",
+ argLen: 3,
+ generic: true,
},
{
- name: "NotEqualUint64x2",
- argLen: 2,
- commutative: true,
- generic: true,
+ name: "ShiftAllRightMaskedUint16x16",
+ argLen: 3,
+ generic: true,
},
{
- name: "NotEqualMaskedUint64x2",
- argLen: 3,
- commutative: true,
- generic: true,
+ name: "ShiftAllRightMaskedUint16x32",
+ argLen: 3,
+ generic: true,
},
{
- name: "OrUint64x2",
- argLen: 2,
- commutative: true,
- generic: true,
+ name: "ShiftAllRightMaskedUint32x4",
+ argLen: 3,
+ generic: true,
},
{
- name: "OrMaskedUint64x2",
- argLen: 3,
- commutative: true,
- generic: true,
+ name: "ShiftAllRightMaskedUint32x8",
+ argLen: 3,
+ generic: true,
},
{
- name: "Permute2Float64x2",
+ name: "ShiftAllRightMaskedUint32x16",
argLen: 3,
generic: true,
},
{
- name: "Permute2Uint64x2",
+ name: "ShiftAllRightMaskedUint64x2",
argLen: 3,
generic: true,
},
{
- name: "Permute2Int64x2",
+ name: "ShiftAllRightMaskedUint64x4",
argLen: 3,
generic: true,
},
{
- name: "Permute2MaskedInt64x2",
- argLen: 4,
+ name: "ShiftAllRightMaskedUint64x8",
+ argLen: 3,
generic: true,
},
{
- name: "Permute2MaskedFloat64x2",
- argLen: 4,
+ name: "ShiftAllRightUint16x8",
+ argLen: 2,
generic: true,
},
{
- name: "Permute2MaskedUint64x2",
- argLen: 4,
+ name: "ShiftAllRightUint16x16",
+ argLen: 2,
generic: true,
},
{
- name: "PopCountUint64x2",
- argLen: 1,
+ name: "ShiftAllRightUint16x32",
+ argLen: 2,
generic: true,
},
{
- name: "PopCountMaskedUint64x2",
+ name: "ShiftAllRightUint32x4",
argLen: 2,
generic: true,
},
{
- name: "RotateLeftUint64x2",
+ name: "ShiftAllRightUint32x8",
argLen: 2,
generic: true,
},
{
- name: "RotateLeftMaskedUint64x2",
- argLen: 3,
+ name: "ShiftAllRightUint32x16",
+ argLen: 2,
generic: true,
},
{
- name: "RotateRightUint64x2",
+ name: "ShiftAllRightUint64x2",
argLen: 2,
generic: true,
},
{
- name: "RotateRightMaskedUint64x2",
- argLen: 3,
+ name: "ShiftAllRightUint64x4",
+ argLen: 2,
generic: true,
},
{
- name: "ShiftAllLeftUint64x2",
+ name: "ShiftAllRightUint64x8",
argLen: 2,
generic: true,
},
{
- name: "ShiftAllLeftMaskedUint64x2",
+ name: "ShiftLeftAndFillUpperFromInt16x8",
argLen: 3,
generic: true,
},
{
- name: "ShiftAllRightUint64x2",
- argLen: 2,
+ name: "ShiftLeftAndFillUpperFromInt16x16",
+ argLen: 3,
generic: true,
},
{
- name: "ShiftAllRightMaskedUint64x2",
+ name: "ShiftLeftAndFillUpperFromInt16x32",
argLen: 3,
generic: true,
},
{
- name: "ShiftLeftUint64x2",
- argLen: 2,
+ name: "ShiftLeftAndFillUpperFromInt32x4",
+ argLen: 3,
generic: true,
},
{
- name: "ShiftLeftAndFillUpperFromUint64x2",
+ name: "ShiftLeftAndFillUpperFromInt32x8",
argLen: 3,
generic: true,
},
{
- name: "ShiftLeftAndFillUpperFromMaskedUint64x2",
- argLen: 4,
+ name: "ShiftLeftAndFillUpperFromInt32x16",
+ argLen: 3,
generic: true,
},
{
- name: "ShiftLeftMaskedUint64x2",
+ name: "ShiftLeftAndFillUpperFromInt64x2",
argLen: 3,
generic: true,
},
{
- name: "ShiftRightUint64x2",
- argLen: 2,
+ name: "ShiftLeftAndFillUpperFromInt64x4",
+ argLen: 3,
generic: true,
},
{
- name: "ShiftRightAndFillUpperFromUint64x2",
+ name: "ShiftLeftAndFillUpperFromInt64x8",
argLen: 3,
generic: true,
},
{
- name: "ShiftRightAndFillUpperFromMaskedUint64x2",
+ name: "ShiftLeftAndFillUpperFromMaskedInt16x8",
argLen: 4,
generic: true,
},
{
- name: "ShiftRightMaskedUint64x2",
- argLen: 3,
+ name: "ShiftLeftAndFillUpperFromMaskedInt16x16",
+ argLen: 4,
generic: true,
},
{
- name: "SubUint64x2",
- argLen: 2,
+ name: "ShiftLeftAndFillUpperFromMaskedInt16x32",
+ argLen: 4,
generic: true,
},
{
- name: "SubMaskedUint64x2",
- argLen: 3,
+ name: "ShiftLeftAndFillUpperFromMaskedInt32x4",
+ argLen: 4,
generic: true,
},
{
- name: "XorUint64x2",
- argLen: 2,
- commutative: true,
- generic: true,
+ name: "ShiftLeftAndFillUpperFromMaskedInt32x8",
+ argLen: 4,
+ generic: true,
},
{
- name: "XorMaskedUint64x2",
- argLen: 3,
- commutative: true,
- generic: true,
+ name: "ShiftLeftAndFillUpperFromMaskedInt32x16",
+ argLen: 4,
+ generic: true,
},
{
- name: "AddUint64x4",
- argLen: 2,
- commutative: true,
- generic: true,
+ name: "ShiftLeftAndFillUpperFromMaskedInt64x2",
+ argLen: 4,
+ generic: true,
},
{
- name: "AddMaskedUint64x4",
- argLen: 3,
- commutative: true,
- generic: true,
+ name: "ShiftLeftAndFillUpperFromMaskedInt64x4",
+ argLen: 4,
+ generic: true,
},
{
- name: "AndUint64x4",
- argLen: 2,
- commutative: true,
- generic: true,
+ name: "ShiftLeftAndFillUpperFromMaskedInt64x8",
+ argLen: 4,
+ generic: true,
},
{
- name: "AndMaskedUint64x4",
- argLen: 3,
- commutative: true,
- generic: true,
+ name: "ShiftLeftAndFillUpperFromMaskedUint16x8",
+ argLen: 4,
+ generic: true,
},
{
- name: "AndNotUint64x4",
- argLen: 2,
+ name: "ShiftLeftAndFillUpperFromMaskedUint16x16",
+ argLen: 4,
generic: true,
},
{
- name: "AndNotMaskedUint64x4",
- argLen: 3,
+ name: "ShiftLeftAndFillUpperFromMaskedUint16x32",
+ argLen: 4,
generic: true,
},
{
- name: "CompressUint64x4",
- argLen: 2,
+ name: "ShiftLeftAndFillUpperFromMaskedUint32x4",
+ argLen: 4,
generic: true,
},
{
- name: "EqualUint64x4",
- argLen: 2,
- commutative: true,
- generic: true,
+ name: "ShiftLeftAndFillUpperFromMaskedUint32x8",
+ argLen: 4,
+ generic: true,
},
{
- name: "EqualMaskedUint64x4",
- argLen: 3,
- commutative: true,
- generic: true,
+ name: "ShiftLeftAndFillUpperFromMaskedUint32x16",
+ argLen: 4,
+ generic: true,
},
{
- name: "GreaterUint64x4",
- argLen: 2,
+ name: "ShiftLeftAndFillUpperFromMaskedUint64x2",
+ argLen: 4,
generic: true,
},
{
- name: "GreaterEqualUint64x4",
- argLen: 2,
+ name: "ShiftLeftAndFillUpperFromMaskedUint64x4",
+ argLen: 4,
generic: true,
},
{
- name: "GreaterEqualMaskedUint64x4",
- argLen: 3,
+ name: "ShiftLeftAndFillUpperFromMaskedUint64x8",
+ argLen: 4,
generic: true,
},
{
- name: "GreaterMaskedUint64x4",
+ name: "ShiftLeftAndFillUpperFromUint16x8",
argLen: 3,
generic: true,
},
{
- name: "LessUint64x4",
- argLen: 2,
+ name: "ShiftLeftAndFillUpperFromUint16x16",
+ argLen: 3,
generic: true,
},
{
- name: "LessEqualUint64x4",
- argLen: 2,
+ name: "ShiftLeftAndFillUpperFromUint16x32",
+ argLen: 3,
generic: true,
},
{
- name: "LessEqualMaskedUint64x4",
+ name: "ShiftLeftAndFillUpperFromUint32x4",
argLen: 3,
generic: true,
},
{
- name: "LessMaskedUint64x4",
+ name: "ShiftLeftAndFillUpperFromUint32x8",
argLen: 3,
generic: true,
},
{
- name: "MaxUint64x4",
- argLen: 2,
- commutative: true,
- generic: true,
- },
- {
- name: "MaxMaskedUint64x4",
- argLen: 3,
- commutative: true,
- generic: true,
+ name: "ShiftLeftAndFillUpperFromUint32x16",
+ argLen: 3,
+ generic: true,
},
{
- name: "MinUint64x4",
- argLen: 2,
- commutative: true,
- generic: true,
+ name: "ShiftLeftAndFillUpperFromUint64x2",
+ argLen: 3,
+ generic: true,
},
{
- name: "MinMaskedUint64x4",
- argLen: 3,
- commutative: true,
- generic: true,
+ name: "ShiftLeftAndFillUpperFromUint64x4",
+ argLen: 3,
+ generic: true,
},
{
- name: "MulEvenWidenUint64x4",
- argLen: 2,
- commutative: true,
- generic: true,
+ name: "ShiftLeftAndFillUpperFromUint64x8",
+ argLen: 3,
+ generic: true,
},
{
- name: "MulEvenWidenMaskedUint64x4",
- argLen: 3,
- commutative: true,
- generic: true,
+ name: "ShiftLeftInt16x8",
+ argLen: 2,
+ generic: true,
},
{
- name: "NotEqualUint64x4",
- argLen: 2,
- commutative: true,
- generic: true,
+ name: "ShiftLeftInt16x16",
+ argLen: 2,
+ generic: true,
},
{
- name: "NotEqualMaskedUint64x4",
- argLen: 3,
- commutative: true,
- generic: true,
+ name: "ShiftLeftInt16x32",
+ argLen: 2,
+ generic: true,
},
{
- name: "OrUint64x4",
- argLen: 2,
- commutative: true,
- generic: true,
+ name: "ShiftLeftInt32x4",
+ argLen: 2,
+ generic: true,
},
{
- name: "OrMaskedUint64x4",
- argLen: 3,
- commutative: true,
- generic: true,
+ name: "ShiftLeftInt32x8",
+ argLen: 2,
+ generic: true,
},
{
- name: "PermuteUint64x4",
+ name: "ShiftLeftInt32x16",
argLen: 2,
generic: true,
},
{
- name: "PermuteInt64x4",
+ name: "ShiftLeftInt64x2",
argLen: 2,
generic: true,
},
{
- name: "PermuteFloat64x4",
+ name: "ShiftLeftInt64x4",
argLen: 2,
generic: true,
},
{
- name: "Permute2Uint64x4",
- argLen: 3,
+ name: "ShiftLeftInt64x8",
+ argLen: 2,
generic: true,
},
{
- name: "Permute2Int64x4",
+ name: "ShiftLeftMaskedInt16x8",
argLen: 3,
generic: true,
},
{
- name: "Permute2Float64x4",
+ name: "ShiftLeftMaskedInt16x16",
argLen: 3,
generic: true,
},
{
- name: "Permute2MaskedUint64x4",
- argLen: 4,
+ name: "ShiftLeftMaskedInt16x32",
+ argLen: 3,
generic: true,
},
{
- name: "Permute2MaskedFloat64x4",
- argLen: 4,
+ name: "ShiftLeftMaskedInt32x4",
+ argLen: 3,
generic: true,
},
{
- name: "Permute2MaskedInt64x4",
- argLen: 4,
+ name: "ShiftLeftMaskedInt32x8",
+ argLen: 3,
generic: true,
},
{
- name: "PermuteMaskedUint64x4",
+ name: "ShiftLeftMaskedInt32x16",
argLen: 3,
generic: true,
},
{
- name: "PermuteMaskedFloat64x4",
+ name: "ShiftLeftMaskedInt64x2",
argLen: 3,
generic: true,
},
{
- name: "PermuteMaskedInt64x4",
+ name: "ShiftLeftMaskedInt64x4",
argLen: 3,
generic: true,
},
{
- name: "PopCountUint64x4",
- argLen: 1,
+ name: "ShiftLeftMaskedInt64x8",
+ argLen: 3,
generic: true,
},
{
- name: "PopCountMaskedUint64x4",
- argLen: 2,
+ name: "ShiftLeftMaskedUint16x8",
+ argLen: 3,
generic: true,
},
{
- name: "RotateLeftUint64x4",
- argLen: 2,
+ name: "ShiftLeftMaskedUint16x16",
+ argLen: 3,
generic: true,
},
{
- name: "RotateLeftMaskedUint64x4",
+ name: "ShiftLeftMaskedUint16x32",
argLen: 3,
generic: true,
},
{
- name: "RotateRightUint64x4",
- argLen: 2,
+ name: "ShiftLeftMaskedUint32x4",
+ argLen: 3,
generic: true,
},
{
- name: "RotateRightMaskedUint64x4",
+ name: "ShiftLeftMaskedUint32x8",
argLen: 3,
generic: true,
},
{
- name: "ShiftAllLeftUint64x4",
- argLen: 2,
+ name: "ShiftLeftMaskedUint32x16",
+ argLen: 3,
generic: true,
},
{
- name: "ShiftAllLeftMaskedUint64x4",
+ name: "ShiftLeftMaskedUint64x2",
argLen: 3,
generic: true,
},
{
- name: "ShiftAllRightUint64x4",
- argLen: 2,
+ name: "ShiftLeftMaskedUint64x4",
+ argLen: 3,
generic: true,
},
{
- name: "ShiftAllRightMaskedUint64x4",
+ name: "ShiftLeftMaskedUint64x8",
argLen: 3,
generic: true,
},
{
- name: "ShiftLeftUint64x4",
+ name: "ShiftLeftUint16x8",
argLen: 2,
generic: true,
},
{
- name: "ShiftLeftAndFillUpperFromUint64x4",
- argLen: 3,
+ name: "ShiftLeftUint16x16",
+ argLen: 2,
generic: true,
},
{
- name: "ShiftLeftAndFillUpperFromMaskedUint64x4",
- argLen: 4,
+ name: "ShiftLeftUint16x32",
+ argLen: 2,
generic: true,
},
{
- name: "ShiftLeftMaskedUint64x4",
- argLen: 3,
+ name: "ShiftLeftUint32x4",
+ argLen: 2,
generic: true,
},
{
- name: "ShiftRightUint64x4",
+ name: "ShiftLeftUint32x8",
argLen: 2,
generic: true,
},
{
- name: "ShiftRightAndFillUpperFromUint64x4",
- argLen: 3,
+ name: "ShiftLeftUint32x16",
+ argLen: 2,
generic: true,
},
{
- name: "ShiftRightAndFillUpperFromMaskedUint64x4",
- argLen: 4,
+ name: "ShiftLeftUint64x2",
+ argLen: 2,
generic: true,
},
{
- name: "ShiftRightMaskedUint64x4",
- argLen: 3,
+ name: "ShiftLeftUint64x4",
+ argLen: 2,
generic: true,
},
{
- name: "SubUint64x4",
+ name: "ShiftLeftUint64x8",
argLen: 2,
generic: true,
},
{
- name: "SubMaskedUint64x4",
+ name: "ShiftRightAndFillUpperFromInt16x8",
argLen: 3,
generic: true,
},
{
- name: "XorUint64x4",
- argLen: 2,
- commutative: true,
- generic: true,
- },
- {
- name: "XorMaskedUint64x4",
- argLen: 3,
- commutative: true,
- generic: true,
- },
- {
- name: "AddUint64x8",
- argLen: 2,
- commutative: true,
- generic: true,
- },
- {
- name: "AddMaskedUint64x8",
- argLen: 3,
- commutative: true,
- generic: true,
- },
- {
- name: "AndUint64x8",
- argLen: 2,
- commutative: true,
- generic: true,
+ name: "ShiftRightAndFillUpperFromInt16x16",
+ argLen: 3,
+ generic: true,
},
{
- name: "AndMaskedUint64x8",
- argLen: 3,
- commutative: true,
- generic: true,
+ name: "ShiftRightAndFillUpperFromInt16x32",
+ argLen: 3,
+ generic: true,
},
{
- name: "AndNotUint64x8",
- argLen: 2,
+ name: "ShiftRightAndFillUpperFromInt32x4",
+ argLen: 3,
generic: true,
},
{
- name: "AndNotMaskedUint64x8",
+ name: "ShiftRightAndFillUpperFromInt32x8",
argLen: 3,
generic: true,
},
{
- name: "CompressUint64x8",
- argLen: 2,
+ name: "ShiftRightAndFillUpperFromInt32x16",
+ argLen: 3,
generic: true,
},
{
- name: "EqualUint64x8",
- argLen: 2,
- commutative: true,
- generic: true,
+ name: "ShiftRightAndFillUpperFromInt64x2",
+ argLen: 3,
+ generic: true,
},
{
- name: "EqualMaskedUint64x8",
- argLen: 3,
- commutative: true,
- generic: true,
+ name: "ShiftRightAndFillUpperFromInt64x4",
+ argLen: 3,
+ generic: true,
},
{
- name: "GreaterUint64x8",
- argLen: 2,
+ name: "ShiftRightAndFillUpperFromInt64x8",
+ argLen: 3,
generic: true,
},
{
- name: "GreaterEqualUint64x8",
- argLen: 2,
+ name: "ShiftRightAndFillUpperFromMaskedInt16x8",
+ argLen: 4,
generic: true,
},
{
- name: "GreaterEqualMaskedUint64x8",
- argLen: 3,
+ name: "ShiftRightAndFillUpperFromMaskedInt16x16",
+ argLen: 4,
generic: true,
},
{
- name: "GreaterMaskedUint64x8",
- argLen: 3,
+ name: "ShiftRightAndFillUpperFromMaskedInt16x32",
+ argLen: 4,
generic: true,
},
{
- name: "LessUint64x8",
- argLen: 2,
+ name: "ShiftRightAndFillUpperFromMaskedInt32x4",
+ argLen: 4,
generic: true,
},
{
- name: "LessEqualUint64x8",
- argLen: 2,
+ name: "ShiftRightAndFillUpperFromMaskedInt32x8",
+ argLen: 4,
generic: true,
},
{
- name: "LessEqualMaskedUint64x8",
- argLen: 3,
+ name: "ShiftRightAndFillUpperFromMaskedInt32x16",
+ argLen: 4,
generic: true,
},
{
- name: "LessMaskedUint64x8",
- argLen: 3,
+ name: "ShiftRightAndFillUpperFromMaskedInt64x2",
+ argLen: 4,
generic: true,
},
{
- name: "MaxUint64x8",
- argLen: 2,
- commutative: true,
- generic: true,
+ name: "ShiftRightAndFillUpperFromMaskedInt64x4",
+ argLen: 4,
+ generic: true,
},
{
- name: "MaxMaskedUint64x8",
- argLen: 3,
- commutative: true,
- generic: true,
+ name: "ShiftRightAndFillUpperFromMaskedInt64x8",
+ argLen: 4,
+ generic: true,
},
{
- name: "MinUint64x8",
- argLen: 2,
- commutative: true,
- generic: true,
+ name: "ShiftRightAndFillUpperFromMaskedUint16x8",
+ argLen: 4,
+ generic: true,
},
{
- name: "MinMaskedUint64x8",
- argLen: 3,
- commutative: true,
- generic: true,
+ name: "ShiftRightAndFillUpperFromMaskedUint16x16",
+ argLen: 4,
+ generic: true,
},
{
- name: "MulEvenWidenUint64x8",
- argLen: 2,
- commutative: true,
- generic: true,
+ name: "ShiftRightAndFillUpperFromMaskedUint16x32",
+ argLen: 4,
+ generic: true,
},
{
- name: "MulEvenWidenMaskedUint64x8",
- argLen: 3,
- commutative: true,
- generic: true,
+ name: "ShiftRightAndFillUpperFromMaskedUint32x4",
+ argLen: 4,
+ generic: true,
},
{
- name: "NotEqualUint64x8",
- argLen: 2,
- commutative: true,
- generic: true,
+ name: "ShiftRightAndFillUpperFromMaskedUint32x8",
+ argLen: 4,
+ generic: true,
},
{
- name: "NotEqualMaskedUint64x8",
- argLen: 3,
- commutative: true,
- generic: true,
+ name: "ShiftRightAndFillUpperFromMaskedUint32x16",
+ argLen: 4,
+ generic: true,
},
{
- name: "OrUint64x8",
- argLen: 2,
- commutative: true,
- generic: true,
+ name: "ShiftRightAndFillUpperFromMaskedUint64x2",
+ argLen: 4,
+ generic: true,
},
{
- name: "OrMaskedUint64x8",
- argLen: 3,
- commutative: true,
- generic: true,
+ name: "ShiftRightAndFillUpperFromMaskedUint64x4",
+ argLen: 4,
+ generic: true,
},
{
- name: "PermuteUint64x8",
- argLen: 2,
+ name: "ShiftRightAndFillUpperFromMaskedUint64x8",
+ argLen: 4,
generic: true,
},
{
- name: "PermuteFloat64x8",
- argLen: 2,
+ name: "ShiftRightAndFillUpperFromUint16x8",
+ argLen: 3,
generic: true,
},
{
- name: "PermuteInt64x8",
- argLen: 2,
+ name: "ShiftRightAndFillUpperFromUint16x16",
+ argLen: 3,
generic: true,
},
{
- name: "Permute2Float64x8",
+ name: "ShiftRightAndFillUpperFromUint16x32",
argLen: 3,
generic: true,
},
{
- name: "Permute2Uint64x8",
+ name: "ShiftRightAndFillUpperFromUint32x4",
argLen: 3,
generic: true,
},
{
- name: "Permute2Int64x8",
+ name: "ShiftRightAndFillUpperFromUint32x8",
argLen: 3,
generic: true,
},
{
- name: "Permute2MaskedFloat64x8",
- argLen: 4,
+ name: "ShiftRightAndFillUpperFromUint32x16",
+ argLen: 3,
generic: true,
},
{
- name: "Permute2MaskedUint64x8",
- argLen: 4,
+ name: "ShiftRightAndFillUpperFromUint64x2",
+ argLen: 3,
generic: true,
},
{
- name: "Permute2MaskedInt64x8",
- argLen: 4,
+ name: "ShiftRightAndFillUpperFromUint64x4",
+ argLen: 3,
generic: true,
},
{
- name: "PermuteMaskedInt64x8",
+ name: "ShiftRightAndFillUpperFromUint64x8",
argLen: 3,
generic: true,
},
{
- name: "PermuteMaskedFloat64x8",
- argLen: 3,
+ name: "ShiftRightInt16x8",
+ argLen: 2,
generic: true,
},
{
- name: "PermuteMaskedUint64x8",
- argLen: 3,
+ name: "ShiftRightInt16x16",
+ argLen: 2,
generic: true,
},
{
- name: "PopCountUint64x8",
- argLen: 1,
+ name: "ShiftRightInt16x32",
+ argLen: 2,
generic: true,
},
{
- name: "PopCountMaskedUint64x8",
+ name: "ShiftRightInt32x4",
argLen: 2,
generic: true,
},
{
- name: "RotateLeftUint64x8",
+ name: "ShiftRightInt32x8",
argLen: 2,
generic: true,
},
{
- name: "RotateLeftMaskedUint64x8",
- argLen: 3,
+ name: "ShiftRightInt32x16",
+ argLen: 2,
generic: true,
},
{
- name: "RotateRightUint64x8",
+ name: "ShiftRightInt64x2",
argLen: 2,
generic: true,
},
{
- name: "RotateRightMaskedUint64x8",
- argLen: 3,
+ name: "ShiftRightInt64x4",
+ argLen: 2,
generic: true,
},
{
- name: "ShiftAllLeftUint64x8",
+ name: "ShiftRightInt64x8",
argLen: 2,
generic: true,
},
{
- name: "ShiftAllLeftMaskedUint64x8",
+ name: "ShiftRightMaskedInt16x8",
argLen: 3,
generic: true,
},
{
- name: "ShiftAllRightUint64x8",
- argLen: 2,
+ name: "ShiftRightMaskedInt16x16",
+ argLen: 3,
generic: true,
},
{
- name: "ShiftAllRightMaskedUint64x8",
+ name: "ShiftRightMaskedInt16x32",
argLen: 3,
generic: true,
},
{
- name: "ShiftLeftUint64x8",
- argLen: 2,
+ name: "ShiftRightMaskedInt32x4",
+ argLen: 3,
generic: true,
},
{
- name: "ShiftLeftAndFillUpperFromUint64x8",
+ name: "ShiftRightMaskedInt32x8",
argLen: 3,
generic: true,
},
{
- name: "ShiftLeftAndFillUpperFromMaskedUint64x8",
- argLen: 4,
+ name: "ShiftRightMaskedInt32x16",
+ argLen: 3,
generic: true,
},
{
- name: "ShiftLeftMaskedUint64x8",
+ name: "ShiftRightMaskedInt64x2",
argLen: 3,
generic: true,
},
{
- name: "ShiftRightUint64x8",
- argLen: 2,
+ name: "ShiftRightMaskedInt64x4",
+ argLen: 3,
generic: true,
},
{
- name: "ShiftRightAndFillUpperFromUint64x8",
+ name: "ShiftRightMaskedInt64x8",
argLen: 3,
generic: true,
},
{
- name: "ShiftRightAndFillUpperFromMaskedUint64x8",
- argLen: 4,
+ name: "ShiftRightMaskedUint16x8",
+ argLen: 3,
generic: true,
},
{
- name: "ShiftRightMaskedUint64x8",
+ name: "ShiftRightMaskedUint16x16",
argLen: 3,
generic: true,
},
{
- name: "SubUint64x8",
- argLen: 2,
+ name: "ShiftRightMaskedUint16x32",
+ argLen: 3,
generic: true,
},
{
- name: "SubMaskedUint64x8",
+ name: "ShiftRightMaskedUint32x4",
argLen: 3,
generic: true,
},
{
- name: "XorUint64x8",
- argLen: 2,
- commutative: true,
- generic: true,
+ name: "ShiftRightMaskedUint32x8",
+ argLen: 3,
+ generic: true,
},
{
- name: "XorMaskedUint64x8",
- argLen: 3,
- commutative: true,
- generic: true,
+ name: "ShiftRightMaskedUint32x16",
+ argLen: 3,
+ generic: true,
},
{
- name: "AddUint8x16",
- argLen: 2,
- commutative: true,
- generic: true,
+ name: "ShiftRightMaskedUint64x2",
+ argLen: 3,
+ generic: true,
},
{
- name: "AddMaskedUint8x16",
- argLen: 3,
- commutative: true,
- generic: true,
+ name: "ShiftRightMaskedUint64x4",
+ argLen: 3,
+ generic: true,
},
{
- name: "AndUint8x16",
- argLen: 2,
- commutative: true,
- generic: true,
+ name: "ShiftRightMaskedUint64x8",
+ argLen: 3,
+ generic: true,
},
{
- name: "AndNotUint8x16",
+ name: "ShiftRightUint16x8",
argLen: 2,
generic: true,
},
{
- name: "AverageUint8x16",
- argLen: 2,
- commutative: true,
- generic: true,
- },
- {
- name: "AverageMaskedUint8x16",
- argLen: 3,
- commutative: true,
- generic: true,
+ name: "ShiftRightUint16x16",
+ argLen: 2,
+ generic: true,
},
{
- name: "CompressUint8x16",
+ name: "ShiftRightUint16x32",
argLen: 2,
generic: true,
},
{
- name: "EqualUint8x16",
- argLen: 2,
- commutative: true,
- generic: true,
+ name: "ShiftRightUint32x4",
+ argLen: 2,
+ generic: true,
},
{
- name: "EqualMaskedUint8x16",
- argLen: 3,
- commutative: true,
- generic: true,
+ name: "ShiftRightUint32x8",
+ argLen: 2,
+ generic: true,
},
{
- name: "GaloisFieldMulUint8x16",
+ name: "ShiftRightUint32x16",
argLen: 2,
generic: true,
},
{
- name: "GaloisFieldMulMaskedUint8x16",
- argLen: 3,
+ name: "ShiftRightUint64x2",
+ argLen: 2,
generic: true,
},
{
- name: "GreaterUint8x16",
+ name: "ShiftRightUint64x4",
argLen: 2,
generic: true,
},
{
- name: "GreaterEqualUint8x16",
+ name: "ShiftRightUint64x8",
argLen: 2,
generic: true,
},
{
- name: "GreaterEqualMaskedUint8x16",
- argLen: 3,
+ name: "SignInt8x16",
+ argLen: 2,
generic: true,
},
{
- name: "GreaterMaskedUint8x16",
- argLen: 3,
+ name: "SignInt8x32",
+ argLen: 2,
generic: true,
},
{
- name: "LessUint8x16",
+ name: "SignInt16x8",
argLen: 2,
generic: true,
},
{
- name: "LessEqualUint8x16",
+ name: "SignInt16x16",
argLen: 2,
generic: true,
},
{
- name: "LessEqualMaskedUint8x16",
- argLen: 3,
+ name: "SignInt32x4",
+ argLen: 2,
generic: true,
},
{
- name: "LessMaskedUint8x16",
- argLen: 3,
+ name: "SignInt32x8",
+ argLen: 2,
generic: true,
},
{
- name: "MaxUint8x16",
- argLen: 2,
- commutative: true,
- generic: true,
+ name: "SqrtFloat32x4",
+ argLen: 1,
+ generic: true,
},
{
- name: "MaxMaskedUint8x16",
- argLen: 3,
- commutative: true,
- generic: true,
+ name: "SqrtFloat32x8",
+ argLen: 1,
+ generic: true,
},
{
- name: "MinUint8x16",
- argLen: 2,
- commutative: true,
- generic: true,
+ name: "SqrtFloat32x16",
+ argLen: 1,
+ generic: true,
},
{
- name: "MinMaskedUint8x16",
- argLen: 3,
- commutative: true,
- generic: true,
+ name: "SqrtFloat64x2",
+ argLen: 1,
+ generic: true,
},
{
- name: "NotEqualUint8x16",
- argLen: 2,
- commutative: true,
- generic: true,
+ name: "SqrtFloat64x4",
+ argLen: 1,
+ generic: true,
},
{
- name: "NotEqualMaskedUint8x16",
- argLen: 3,
- commutative: true,
- generic: true,
+ name: "SqrtFloat64x8",
+ argLen: 1,
+ generic: true,
},
{
- name: "OrUint8x16",
- argLen: 2,
- commutative: true,
- generic: true,
+ name: "SqrtMaskedFloat32x4",
+ argLen: 2,
+ generic: true,
},
{
- name: "PermuteUint8x16",
+ name: "SqrtMaskedFloat32x8",
argLen: 2,
generic: true,
},
{
- name: "PermuteInt8x16",
+ name: "SqrtMaskedFloat32x16",
argLen: 2,
generic: true,
},
{
- name: "Permute2Uint8x16",
- argLen: 3,
+ name: "SqrtMaskedFloat64x2",
+ argLen: 2,
generic: true,
},
{
- name: "Permute2Int8x16",
- argLen: 3,
+ name: "SqrtMaskedFloat64x4",
+ argLen: 2,
generic: true,
},
{
- name: "Permute2MaskedInt8x16",
- argLen: 4,
+ name: "SqrtMaskedFloat64x8",
+ argLen: 2,
generic: true,
},
{
- name: "Permute2MaskedUint8x16",
- argLen: 4,
+ name: "SubFloat32x4",
+ argLen: 2,
generic: true,
},
{
- name: "PermuteMaskedUint8x16",
- argLen: 3,
+ name: "SubFloat32x8",
+ argLen: 2,
generic: true,
},
{
- name: "PermuteMaskedInt8x16",
- argLen: 3,
+ name: "SubFloat32x16",
+ argLen: 2,
generic: true,
},
{
- name: "PopCountUint8x16",
- argLen: 1,
+ name: "SubFloat64x2",
+ argLen: 2,
generic: true,
},
{
- name: "PopCountMaskedUint8x16",
+ name: "SubFloat64x4",
argLen: 2,
generic: true,
},
{
- name: "SaturatedAddUint8x16",
- argLen: 2,
- commutative: true,
- generic: true,
+ name: "SubFloat64x8",
+ argLen: 2,
+ generic: true,
},
{
- name: "SaturatedAddMaskedUint8x16",
- argLen: 3,
- commutative: true,
- generic: true,
+ name: "SubInt8x16",
+ argLen: 2,
+ generic: true,
},
{
- name: "SaturatedSubUint8x16",
+ name: "SubInt8x32",
argLen: 2,
generic: true,
},
{
- name: "SaturatedSubMaskedUint8x16",
- argLen: 3,
+ name: "SubInt8x64",
+ argLen: 2,
generic: true,
},
{
- name: "SaturatedUnsignedSignedPairDotProdUint8x16",
+ name: "SubInt16x8",
argLen: 2,
generic: true,
},
{
- name: "SaturatedUnsignedSignedPairDotProdMaskedUint8x16",
- argLen: 3,
+ name: "SubInt16x16",
+ argLen: 2,
generic: true,
},
{
- name: "SubUint8x16",
+ name: "SubInt16x32",
argLen: 2,
generic: true,
},
{
- name: "SubMaskedUint8x16",
- argLen: 3,
+ name: "SubInt32x4",
+ argLen: 2,
generic: true,
},
{
- name: "XorUint8x16",
- argLen: 2,
- commutative: true,
- generic: true,
+ name: "SubInt32x8",
+ argLen: 2,
+ generic: true,
},
{
- name: "AddUint8x32",
- argLen: 2,
- commutative: true,
- generic: true,
+ name: "SubInt32x16",
+ argLen: 2,
+ generic: true,
},
{
- name: "AddMaskedUint8x32",
- argLen: 3,
- commutative: true,
- generic: true,
+ name: "SubInt64x2",
+ argLen: 2,
+ generic: true,
},
{
- name: "AndUint8x32",
- argLen: 2,
- commutative: true,
- generic: true,
+ name: "SubInt64x4",
+ argLen: 2,
+ generic: true,
},
{
- name: "AndNotUint8x32",
+ name: "SubInt64x8",
argLen: 2,
generic: true,
},
{
- name: "AverageUint8x32",
- argLen: 2,
- commutative: true,
- generic: true,
+ name: "SubMaskedFloat32x4",
+ argLen: 3,
+ generic: true,
},
{
- name: "AverageMaskedUint8x32",
- argLen: 3,
- commutative: true,
- generic: true,
+ name: "SubMaskedFloat32x8",
+ argLen: 3,
+ generic: true,
},
{
- name: "CompressUint8x32",
- argLen: 2,
+ name: "SubMaskedFloat32x16",
+ argLen: 3,
generic: true,
},
{
- name: "EqualUint8x32",
- argLen: 2,
- commutative: true,
- generic: true,
+ name: "SubMaskedFloat64x2",
+ argLen: 3,
+ generic: true,
},
{
- name: "EqualMaskedUint8x32",
- argLen: 3,
- commutative: true,
- generic: true,
+ name: "SubMaskedFloat64x4",
+ argLen: 3,
+ generic: true,
},
{
- name: "GaloisFieldMulUint8x32",
- argLen: 2,
+ name: "SubMaskedFloat64x8",
+ argLen: 3,
generic: true,
},
{
- name: "GaloisFieldMulMaskedUint8x32",
+ name: "SubMaskedInt8x16",
argLen: 3,
generic: true,
},
{
- name: "GreaterUint8x32",
- argLen: 2,
+ name: "SubMaskedInt8x32",
+ argLen: 3,
generic: true,
},
{
- name: "GreaterEqualUint8x32",
- argLen: 2,
+ name: "SubMaskedInt8x64",
+ argLen: 3,
generic: true,
},
{
- name: "GreaterEqualMaskedUint8x32",
+ name: "SubMaskedInt16x8",
argLen: 3,
generic: true,
},
{
- name: "GreaterMaskedUint8x32",
+ name: "SubMaskedInt16x16",
argLen: 3,
generic: true,
},
{
- name: "LessUint8x32",
- argLen: 2,
+ name: "SubMaskedInt16x32",
+ argLen: 3,
generic: true,
},
{
- name: "LessEqualUint8x32",
- argLen: 2,
+ name: "SubMaskedInt32x4",
+ argLen: 3,
generic: true,
},
{
- name: "LessEqualMaskedUint8x32",
+ name: "SubMaskedInt32x8",
argLen: 3,
generic: true,
},
{
- name: "LessMaskedUint8x32",
+ name: "SubMaskedInt32x16",
argLen: 3,
generic: true,
},
{
- name: "MaxUint8x32",
- argLen: 2,
- commutative: true,
- generic: true,
+ name: "SubMaskedInt64x2",
+ argLen: 3,
+ generic: true,
},
{
- name: "MaxMaskedUint8x32",
- argLen: 3,
- commutative: true,
- generic: true,
+ name: "SubMaskedInt64x4",
+ argLen: 3,
+ generic: true,
},
{
- name: "MinUint8x32",
- argLen: 2,
- commutative: true,
- generic: true,
+ name: "SubMaskedInt64x8",
+ argLen: 3,
+ generic: true,
},
{
- name: "MinMaskedUint8x32",
- argLen: 3,
- commutative: true,
- generic: true,
+ name: "SubMaskedUint8x16",
+ argLen: 3,
+ generic: true,
},
{
- name: "NotEqualUint8x32",
- argLen: 2,
- commutative: true,
- generic: true,
+ name: "SubMaskedUint8x32",
+ argLen: 3,
+ generic: true,
},
{
- name: "NotEqualMaskedUint8x32",
- argLen: 3,
- commutative: true,
- generic: true,
+ name: "SubMaskedUint8x64",
+ argLen: 3,
+ generic: true,
},
{
- name: "OrUint8x32",
- argLen: 2,
- commutative: true,
- generic: true,
+ name: "SubMaskedUint16x8",
+ argLen: 3,
+ generic: true,
},
{
- name: "PermuteUint8x32",
- argLen: 2,
+ name: "SubMaskedUint16x16",
+ argLen: 3,
generic: true,
},
{
- name: "PermuteInt8x32",
- argLen: 2,
+ name: "SubMaskedUint16x32",
+ argLen: 3,
generic: true,
},
{
- name: "Permute2Int8x32",
+ name: "SubMaskedUint32x4",
argLen: 3,
generic: true,
},
{
- name: "Permute2Uint8x32",
+ name: "SubMaskedUint32x8",
argLen: 3,
generic: true,
},
{
- name: "Permute2MaskedUint8x32",
- argLen: 4,
+ name: "SubMaskedUint32x16",
+ argLen: 3,
generic: true,
},
{
- name: "Permute2MaskedInt8x32",
- argLen: 4,
+ name: "SubMaskedUint64x2",
+ argLen: 3,
generic: true,
},
{
- name: "PermuteMaskedUint8x32",
+ name: "SubMaskedUint64x4",
argLen: 3,
generic: true,
},
{
- name: "PermuteMaskedInt8x32",
+ name: "SubMaskedUint64x8",
argLen: 3,
generic: true,
},
{
- name: "PopCountUint8x32",
- argLen: 1,
+ name: "SubUint8x16",
+ argLen: 2,
generic: true,
},
{
- name: "PopCountMaskedUint8x32",
+ name: "SubUint8x32",
argLen: 2,
generic: true,
},
{
- name: "SaturatedAddUint8x32",
- argLen: 2,
- commutative: true,
- generic: true,
+ name: "SubUint8x64",
+ argLen: 2,
+ generic: true,
},
{
- name: "SaturatedAddMaskedUint8x32",
- argLen: 3,
- commutative: true,
- generic: true,
+ name: "SubUint16x8",
+ argLen: 2,
+ generic: true,
},
{
- name: "SaturatedSubUint8x32",
+ name: "SubUint16x16",
argLen: 2,
generic: true,
},
{
- name: "SaturatedSubMaskedUint8x32",
- argLen: 3,
+ name: "SubUint16x32",
+ argLen: 2,
generic: true,
},
{
- name: "SaturatedUnsignedSignedPairDotProdUint8x32",
+ name: "SubUint32x4",
argLen: 2,
generic: true,
},
{
- name: "SaturatedUnsignedSignedPairDotProdMaskedUint8x32",
- argLen: 3,
+ name: "SubUint32x8",
+ argLen: 2,
generic: true,
},
{
- name: "SubUint8x32",
+ name: "SubUint32x16",
argLen: 2,
generic: true,
},
{
- name: "SubMaskedUint8x32",
- argLen: 3,
+ name: "SubUint64x2",
+ argLen: 2,
generic: true,
},
{
- name: "XorUint8x32",
- argLen: 2,
- commutative: true,
- generic: true,
+ name: "SubUint64x4",
+ argLen: 2,
+ generic: true,
},
{
- name: "AddUint8x64",
- argLen: 2,
- commutative: true,
- generic: true,
+ name: "SubUint64x8",
+ argLen: 2,
+ generic: true,
},
{
- name: "AddMaskedUint8x64",
- argLen: 3,
- commutative: true,
- generic: true,
+ name: "TruncFloat32x4",
+ argLen: 1,
+ generic: true,
},
{
- name: "AverageUint8x64",
- argLen: 2,
- commutative: true,
- generic: true,
+ name: "TruncFloat32x8",
+ argLen: 1,
+ generic: true,
},
{
- name: "AverageMaskedUint8x64",
- argLen: 3,
- commutative: true,
- generic: true,
+ name: "TruncFloat64x2",
+ argLen: 1,
+ generic: true,
},
{
- name: "CompressUint8x64",
- argLen: 2,
+ name: "TruncFloat64x4",
+ argLen: 1,
generic: true,
},
{
- name: "EqualUint8x64",
- argLen: 2,
- commutative: true,
- generic: true,
+ name: "UnsignedSignedQuadDotProdAccumulateInt32x4",
+ argLen: 3,
+ generic: true,
},
{
- name: "EqualMaskedUint8x64",
- argLen: 3,
- commutative: true,
- generic: true,
+ name: "UnsignedSignedQuadDotProdAccumulateInt32x8",
+ argLen: 3,
+ generic: true,
},
{
- name: "GaloisFieldMulUint8x64",
- argLen: 2,
+ name: "UnsignedSignedQuadDotProdAccumulateInt32x16",
+ argLen: 3,
generic: true,
},
{
- name: "GaloisFieldMulMaskedUint8x64",
- argLen: 3,
+ name: "UnsignedSignedQuadDotProdAccumulateMaskedInt32x4",
+ argLen: 4,
generic: true,
},
{
- name: "GreaterUint8x64",
- argLen: 2,
+ name: "UnsignedSignedQuadDotProdAccumulateMaskedInt32x8",
+ argLen: 4,
generic: true,
},
{
- name: "GreaterEqualUint8x64",
- argLen: 2,
+ name: "UnsignedSignedQuadDotProdAccumulateMaskedInt32x16",
+ argLen: 4,
generic: true,
},
{
- name: "GreaterEqualMaskedUint8x64",
- argLen: 3,
- generic: true,
+ name: "XorInt8x16",
+ argLen: 2,
+ commutative: true,
+ generic: true,
},
{
- name: "GreaterMaskedUint8x64",
- argLen: 3,
- generic: true,
+ name: "XorInt8x32",
+ argLen: 2,
+ commutative: true,
+ generic: true,
},
{
- name: "LessUint8x64",
- argLen: 2,
- generic: true,
+ name: "XorInt16x8",
+ argLen: 2,
+ commutative: true,
+ generic: true,
},
{
- name: "LessEqualUint8x64",
- argLen: 2,
- generic: true,
+ name: "XorInt16x16",
+ argLen: 2,
+ commutative: true,
+ generic: true,
},
{
- name: "LessEqualMaskedUint8x64",
- argLen: 3,
- generic: true,
+ name: "XorInt32x4",
+ argLen: 2,
+ commutative: true,
+ generic: true,
},
{
- name: "LessMaskedUint8x64",
- argLen: 3,
- generic: true,
+ name: "XorInt32x8",
+ argLen: 2,
+ commutative: true,
+ generic: true,
},
{
- name: "MaxUint8x64",
+ name: "XorInt32x16",
argLen: 2,
commutative: true,
generic: true,
},
{
- name: "MaxMaskedUint8x64",
- argLen: 3,
+ name: "XorInt64x2",
+ argLen: 2,
commutative: true,
generic: true,
},
{
- name: "MinUint8x64",
+ name: "XorInt64x4",
argLen: 2,
commutative: true,
generic: true,
},
{
- name: "MinMaskedUint8x64",
+ name: "XorInt64x8",
+ argLen: 2,
+ commutative: true,
+ generic: true,
+ },
+ {
+ name: "XorMaskedInt32x4",
argLen: 3,
commutative: true,
generic: true,
},
{
- name: "NotEqualUint8x64",
- argLen: 2,
+ name: "XorMaskedInt32x8",
+ argLen: 3,
commutative: true,
generic: true,
},
{
- name: "NotEqualMaskedUint8x64",
+ name: "XorMaskedInt32x16",
argLen: 3,
commutative: true,
generic: true,
},
{
- name: "PermuteInt8x64",
- argLen: 2,
- generic: true,
+ name: "XorMaskedInt64x2",
+ argLen: 3,
+ commutative: true,
+ generic: true,
},
{
- name: "PermuteUint8x64",
- argLen: 2,
- generic: true,
+ name: "XorMaskedInt64x4",
+ argLen: 3,
+ commutative: true,
+ generic: true,
},
{
- name: "Permute2Uint8x64",
- argLen: 3,
- generic: true,
+ name: "XorMaskedInt64x8",
+ argLen: 3,
+ commutative: true,
+ generic: true,
},
{
- name: "Permute2Int8x64",
- argLen: 3,
- generic: true,
+ name: "XorMaskedUint32x4",
+ argLen: 3,
+ commutative: true,
+ generic: true,
},
{
- name: "Permute2MaskedUint8x64",
- argLen: 4,
- generic: true,
+ name: "XorMaskedUint32x8",
+ argLen: 3,
+ commutative: true,
+ generic: true,
},
{
- name: "Permute2MaskedInt8x64",
- argLen: 4,
- generic: true,
+ name: "XorMaskedUint32x16",
+ argLen: 3,
+ commutative: true,
+ generic: true,
},
{
- name: "PermuteMaskedUint8x64",
- argLen: 3,
- generic: true,
+ name: "XorMaskedUint64x2",
+ argLen: 3,
+ commutative: true,
+ generic: true,
},
{
- name: "PermuteMaskedInt8x64",
- argLen: 3,
- generic: true,
+ name: "XorMaskedUint64x4",
+ argLen: 3,
+ commutative: true,
+ generic: true,
},
{
- name: "PopCountUint8x64",
- argLen: 1,
- generic: true,
+ name: "XorMaskedUint64x8",
+ argLen: 3,
+ commutative: true,
+ generic: true,
},
{
- name: "PopCountMaskedUint8x64",
- argLen: 2,
- generic: true,
+ name: "XorUint8x16",
+ argLen: 2,
+ commutative: true,
+ generic: true,
},
{
- name: "SaturatedAddUint8x64",
+ name: "XorUint8x32",
argLen: 2,
commutative: true,
generic: true,
},
{
- name: "SaturatedAddMaskedUint8x64",
- argLen: 3,
+ name: "XorUint16x8",
+ argLen: 2,
commutative: true,
generic: true,
},
{
- name: "SaturatedSubUint8x64",
- argLen: 2,
- generic: true,
+ name: "XorUint16x16",
+ argLen: 2,
+ commutative: true,
+ generic: true,
},
{
- name: "SaturatedSubMaskedUint8x64",
- argLen: 3,
- generic: true,
+ name: "XorUint32x4",
+ argLen: 2,
+ commutative: true,
+ generic: true,
},
{
- name: "SaturatedUnsignedSignedPairDotProdUint8x64",
- argLen: 2,
- generic: true,
+ name: "XorUint32x8",
+ argLen: 2,
+ commutative: true,
+ generic: true,
},
{
- name: "SaturatedUnsignedSignedPairDotProdMaskedUint8x64",
- argLen: 3,
- generic: true,
+ name: "XorUint32x16",
+ argLen: 2,
+ commutative: true,
+ generic: true,
},
{
- name: "SubUint8x64",
- argLen: 2,
- generic: true,
+ name: "XorUint64x2",
+ argLen: 2,
+ commutative: true,
+ generic: true,
},
{
- name: "SubMaskedUint8x64",
- argLen: 3,
- generic: true,
+ name: "XorUint64x4",
+ argLen: 2,
+ commutative: true,
+ generic: true,
},
{
- name: "CeilWithPrecisionFloat32x16",
- auxType: auxInt8,
- argLen: 1,
- generic: true,
+ name: "XorUint64x8",
+ argLen: 2,
+ commutative: true,
+ generic: true,
},
{
- name: "CeilWithPrecisionMaskedFloat32x16",
+ name: "CeilWithPrecisionFloat32x4",
auxType: auxInt8,
- argLen: 2,
+ argLen: 1,
generic: true,
},
{
- name: "DiffWithCeilWithPrecisionFloat32x16",
+ name: "CeilWithPrecisionFloat32x8",
auxType: auxInt8,
argLen: 1,
generic: true,
},
{
- name: "DiffWithCeilWithPrecisionMaskedFloat32x16",
+ name: "CeilWithPrecisionFloat32x16",
auxType: auxInt8,
- argLen: 2,
+ argLen: 1,
generic: true,
},
{
- name: "DiffWithFloorWithPrecisionFloat32x16",
+ name: "CeilWithPrecisionFloat64x2",
auxType: auxInt8,
argLen: 1,
generic: true,
},
{
- name: "DiffWithFloorWithPrecisionMaskedFloat32x16",
+ name: "CeilWithPrecisionFloat64x4",
auxType: auxInt8,
- argLen: 2,
+ argLen: 1,
generic: true,
},
{
- name: "DiffWithRoundWithPrecisionFloat32x16",
+ name: "CeilWithPrecisionFloat64x8",
auxType: auxInt8,
argLen: 1,
generic: true,
},
{
- name: "DiffWithRoundWithPrecisionMaskedFloat32x16",
+ name: "CeilWithPrecisionMaskedFloat32x4",
auxType: auxInt8,
argLen: 2,
generic: true,
},
{
- name: "DiffWithTruncWithPrecisionFloat32x16",
+ name: "CeilWithPrecisionMaskedFloat32x8",
auxType: auxInt8,
- argLen: 1,
+ argLen: 2,
generic: true,
},
{
- name: "DiffWithTruncWithPrecisionMaskedFloat32x16",
+ name: "CeilWithPrecisionMaskedFloat32x16",
auxType: auxInt8,
argLen: 2,
generic: true,
},
{
- name: "FloorWithPrecisionFloat32x16",
+ name: "CeilWithPrecisionMaskedFloat64x2",
auxType: auxInt8,
- argLen: 1,
+ argLen: 2,
generic: true,
},
{
- name: "FloorWithPrecisionMaskedFloat32x16",
+ name: "CeilWithPrecisionMaskedFloat64x4",
auxType: auxInt8,
argLen: 2,
generic: true,
},
{
- name: "RoundWithPrecisionFloat32x16",
+ name: "CeilWithPrecisionMaskedFloat64x8",
auxType: auxInt8,
- argLen: 1,
+ argLen: 2,
generic: true,
},
{
- name: "RoundWithPrecisionMaskedFloat32x16",
+ name: "DiffWithCeilWithPrecisionFloat32x4",
auxType: auxInt8,
- argLen: 2,
+ argLen: 1,
generic: true,
},
{
- name: "TruncWithPrecisionFloat32x16",
+ name: "DiffWithCeilWithPrecisionFloat32x8",
auxType: auxInt8,
argLen: 1,
generic: true,
},
{
- name: "TruncWithPrecisionMaskedFloat32x16",
+ name: "DiffWithCeilWithPrecisionFloat32x16",
auxType: auxInt8,
- argLen: 2,
+ argLen: 1,
generic: true,
},
{
- name: "CeilWithPrecisionFloat32x4",
+ name: "DiffWithCeilWithPrecisionFloat64x2",
auxType: auxInt8,
argLen: 1,
generic: true,
},
{
- name: "CeilWithPrecisionMaskedFloat32x4",
+ name: "DiffWithCeilWithPrecisionFloat64x4",
auxType: auxInt8,
- argLen: 2,
+ argLen: 1,
generic: true,
},
{
- name: "DiffWithCeilWithPrecisionFloat32x4",
+ name: "DiffWithCeilWithPrecisionFloat64x8",
auxType: auxInt8,
argLen: 1,
generic: true,
generic: true,
},
{
- name: "DiffWithFloorWithPrecisionFloat32x4",
+ name: "DiffWithCeilWithPrecisionMaskedFloat32x8",
auxType: auxInt8,
- argLen: 1,
+ argLen: 2,
generic: true,
},
{
- name: "DiffWithFloorWithPrecisionMaskedFloat32x4",
+ name: "DiffWithCeilWithPrecisionMaskedFloat32x16",
auxType: auxInt8,
argLen: 2,
generic: true,
},
{
- name: "DiffWithRoundWithPrecisionFloat32x4",
+ name: "DiffWithCeilWithPrecisionMaskedFloat64x2",
auxType: auxInt8,
- argLen: 1,
+ argLen: 2,
generic: true,
},
{
- name: "DiffWithRoundWithPrecisionMaskedFloat32x4",
+ name: "DiffWithCeilWithPrecisionMaskedFloat64x4",
auxType: auxInt8,
argLen: 2,
generic: true,
},
{
- name: "DiffWithTruncWithPrecisionFloat32x4",
+ name: "DiffWithCeilWithPrecisionMaskedFloat64x8",
auxType: auxInt8,
- argLen: 1,
+ argLen: 2,
generic: true,
},
{
- name: "DiffWithTruncWithPrecisionMaskedFloat32x4",
+ name: "DiffWithFloorWithPrecisionFloat32x4",
auxType: auxInt8,
- argLen: 2,
+ argLen: 1,
generic: true,
},
{
- name: "FloorWithPrecisionFloat32x4",
+ name: "DiffWithFloorWithPrecisionFloat32x8",
auxType: auxInt8,
argLen: 1,
generic: true,
},
{
- name: "FloorWithPrecisionMaskedFloat32x4",
+ name: "DiffWithFloorWithPrecisionFloat32x16",
auxType: auxInt8,
- argLen: 2,
+ argLen: 1,
generic: true,
},
{
- name: "RoundWithPrecisionFloat32x4",
+ name: "DiffWithFloorWithPrecisionFloat64x2",
auxType: auxInt8,
argLen: 1,
generic: true,
},
{
- name: "RoundWithPrecisionMaskedFloat32x4",
+ name: "DiffWithFloorWithPrecisionFloat64x4",
auxType: auxInt8,
- argLen: 2,
+ argLen: 1,
generic: true,
},
{
- name: "TruncWithPrecisionFloat32x4",
+ name: "DiffWithFloorWithPrecisionFloat64x8",
auxType: auxInt8,
argLen: 1,
generic: true,
},
{
- name: "TruncWithPrecisionMaskedFloat32x4",
+ name: "DiffWithFloorWithPrecisionMaskedFloat32x4",
auxType: auxInt8,
argLen: 2,
generic: true,
},
{
- name: "CeilWithPrecisionFloat32x8",
+ name: "DiffWithFloorWithPrecisionMaskedFloat32x8",
auxType: auxInt8,
- argLen: 1,
+ argLen: 2,
generic: true,
},
{
- name: "CeilWithPrecisionMaskedFloat32x8",
+ name: "DiffWithFloorWithPrecisionMaskedFloat32x16",
auxType: auxInt8,
argLen: 2,
generic: true,
},
{
- name: "DiffWithCeilWithPrecisionFloat32x8",
+ name: "DiffWithFloorWithPrecisionMaskedFloat64x2",
auxType: auxInt8,
- argLen: 1,
+ argLen: 2,
generic: true,
},
{
- name: "DiffWithCeilWithPrecisionMaskedFloat32x8",
+ name: "DiffWithFloorWithPrecisionMaskedFloat64x4",
auxType: auxInt8,
argLen: 2,
generic: true,
},
{
- name: "DiffWithFloorWithPrecisionFloat32x8",
+ name: "DiffWithFloorWithPrecisionMaskedFloat64x8",
auxType: auxInt8,
- argLen: 1,
+ argLen: 2,
generic: true,
},
{
- name: "DiffWithFloorWithPrecisionMaskedFloat32x8",
+ name: "DiffWithRoundWithPrecisionFloat32x4",
auxType: auxInt8,
- argLen: 2,
+ argLen: 1,
generic: true,
},
{
generic: true,
},
{
- name: "DiffWithRoundWithPrecisionMaskedFloat32x8",
+ name: "DiffWithRoundWithPrecisionFloat32x16",
auxType: auxInt8,
- argLen: 2,
+ argLen: 1,
generic: true,
},
{
- name: "DiffWithTruncWithPrecisionFloat32x8",
+ name: "DiffWithRoundWithPrecisionFloat64x2",
auxType: auxInt8,
argLen: 1,
generic: true,
},
{
- name: "DiffWithTruncWithPrecisionMaskedFloat32x8",
+ name: "DiffWithRoundWithPrecisionFloat64x4",
auxType: auxInt8,
- argLen: 2,
+ argLen: 1,
generic: true,
},
{
- name: "FloorWithPrecisionFloat32x8",
+ name: "DiffWithRoundWithPrecisionFloat64x8",
auxType: auxInt8,
argLen: 1,
generic: true,
},
{
- name: "FloorWithPrecisionMaskedFloat32x8",
+ name: "DiffWithRoundWithPrecisionMaskedFloat32x4",
auxType: auxInt8,
argLen: 2,
generic: true,
},
{
- name: "Get128Float32x8",
+ name: "DiffWithRoundWithPrecisionMaskedFloat32x8",
auxType: auxInt8,
- argLen: 1,
+ argLen: 2,
generic: true,
},
{
- name: "RoundWithPrecisionFloat32x8",
+ name: "DiffWithRoundWithPrecisionMaskedFloat32x16",
auxType: auxInt8,
- argLen: 1,
+ argLen: 2,
generic: true,
},
{
- name: "RoundWithPrecisionMaskedFloat32x8",
+ name: "DiffWithRoundWithPrecisionMaskedFloat64x2",
auxType: auxInt8,
argLen: 2,
generic: true,
},
{
- name: "Set128Float32x8",
+ name: "DiffWithRoundWithPrecisionMaskedFloat64x4",
auxType: auxInt8,
argLen: 2,
generic: true,
},
{
- name: "TruncWithPrecisionFloat32x8",
+ name: "DiffWithRoundWithPrecisionMaskedFloat64x8",
auxType: auxInt8,
- argLen: 1,
+ argLen: 2,
generic: true,
},
{
- name: "TruncWithPrecisionMaskedFloat32x8",
+ name: "DiffWithTruncWithPrecisionFloat32x4",
auxType: auxInt8,
- argLen: 2,
+ argLen: 1,
generic: true,
},
{
- name: "CeilWithPrecisionFloat64x2",
+ name: "DiffWithTruncWithPrecisionFloat32x8",
auxType: auxInt8,
argLen: 1,
generic: true,
},
{
- name: "CeilWithPrecisionMaskedFloat64x2",
+ name: "DiffWithTruncWithPrecisionFloat32x16",
auxType: auxInt8,
- argLen: 2,
+ argLen: 1,
generic: true,
},
{
- name: "DiffWithCeilWithPrecisionFloat64x2",
+ name: "DiffWithTruncWithPrecisionFloat64x2",
auxType: auxInt8,
argLen: 1,
generic: true,
},
{
- name: "DiffWithCeilWithPrecisionMaskedFloat64x2",
+ name: "DiffWithTruncWithPrecisionFloat64x4",
auxType: auxInt8,
- argLen: 2,
+ argLen: 1,
generic: true,
},
{
- name: "DiffWithFloorWithPrecisionFloat64x2",
+ name: "DiffWithTruncWithPrecisionFloat64x8",
auxType: auxInt8,
argLen: 1,
generic: true,
},
{
- name: "DiffWithFloorWithPrecisionMaskedFloat64x2",
+ name: "DiffWithTruncWithPrecisionMaskedFloat32x4",
auxType: auxInt8,
argLen: 2,
generic: true,
},
{
- name: "DiffWithRoundWithPrecisionFloat64x2",
+ name: "DiffWithTruncWithPrecisionMaskedFloat32x8",
auxType: auxInt8,
- argLen: 1,
+ argLen: 2,
generic: true,
},
{
- name: "DiffWithRoundWithPrecisionMaskedFloat64x2",
+ name: "DiffWithTruncWithPrecisionMaskedFloat32x16",
auxType: auxInt8,
argLen: 2,
generic: true,
},
{
- name: "DiffWithTruncWithPrecisionFloat64x2",
+ name: "DiffWithTruncWithPrecisionMaskedFloat64x2",
auxType: auxInt8,
- argLen: 1,
+ argLen: 2,
generic: true,
},
{
- name: "DiffWithTruncWithPrecisionMaskedFloat64x2",
+ name: "DiffWithTruncWithPrecisionMaskedFloat64x4",
auxType: auxInt8,
argLen: 2,
generic: true,
},
{
- name: "FloorWithPrecisionFloat64x2",
+ name: "DiffWithTruncWithPrecisionMaskedFloat64x8",
auxType: auxInt8,
- argLen: 1,
+ argLen: 2,
generic: true,
},
{
- name: "FloorWithPrecisionMaskedFloat64x2",
+ name: "FloorWithPrecisionFloat32x4",
auxType: auxInt8,
- argLen: 2,
+ argLen: 1,
generic: true,
},
{
- name: "RoundWithPrecisionFloat64x2",
+ name: "FloorWithPrecisionFloat32x8",
auxType: auxInt8,
argLen: 1,
generic: true,
},
{
- name: "RoundWithPrecisionMaskedFloat64x2",
+ name: "FloorWithPrecisionFloat32x16",
auxType: auxInt8,
- argLen: 2,
+ argLen: 1,
generic: true,
},
{
- name: "TruncWithPrecisionFloat64x2",
+ name: "FloorWithPrecisionFloat64x2",
auxType: auxInt8,
argLen: 1,
generic: true,
},
{
- name: "TruncWithPrecisionMaskedFloat64x2",
+ name: "FloorWithPrecisionFloat64x4",
auxType: auxInt8,
- argLen: 2,
+ argLen: 1,
generic: true,
},
{
- name: "CeilWithPrecisionFloat64x4",
+ name: "FloorWithPrecisionFloat64x8",
auxType: auxInt8,
argLen: 1,
generic: true,
},
{
- name: "CeilWithPrecisionMaskedFloat64x4",
+ name: "FloorWithPrecisionMaskedFloat32x4",
auxType: auxInt8,
argLen: 2,
generic: true,
},
{
- name: "DiffWithCeilWithPrecisionFloat64x4",
+ name: "FloorWithPrecisionMaskedFloat32x8",
auxType: auxInt8,
- argLen: 1,
+ argLen: 2,
generic: true,
},
{
- name: "DiffWithCeilWithPrecisionMaskedFloat64x4",
+ name: "FloorWithPrecisionMaskedFloat32x16",
auxType: auxInt8,
argLen: 2,
generic: true,
},
{
- name: "DiffWithFloorWithPrecisionFloat64x4",
+ name: "FloorWithPrecisionMaskedFloat64x2",
auxType: auxInt8,
- argLen: 1,
+ argLen: 2,
generic: true,
},
{
- name: "DiffWithFloorWithPrecisionMaskedFloat64x4",
+ name: "FloorWithPrecisionMaskedFloat64x4",
auxType: auxInt8,
argLen: 2,
generic: true,
},
{
- name: "DiffWithRoundWithPrecisionFloat64x4",
+ name: "FloorWithPrecisionMaskedFloat64x8",
auxType: auxInt8,
- argLen: 1,
+ argLen: 2,
generic: true,
},
{
- name: "DiffWithRoundWithPrecisionMaskedFloat64x4",
+ name: "GaloisFieldAffineTransformInverseMaskedUint8x16",
auxType: auxInt8,
- argLen: 2,
+ argLen: 3,
generic: true,
},
{
- name: "DiffWithTruncWithPrecisionFloat64x4",
+ name: "GaloisFieldAffineTransformInverseMaskedUint8x32",
auxType: auxInt8,
- argLen: 1,
+ argLen: 3,
generic: true,
},
{
- name: "DiffWithTruncWithPrecisionMaskedFloat64x4",
+ name: "GaloisFieldAffineTransformInverseMaskedUint8x64",
+ auxType: auxInt8,
+ argLen: 3,
+ generic: true,
+ },
+ {
+ name: "GaloisFieldAffineTransformInverseUint8x16",
auxType: auxInt8,
argLen: 2,
generic: true,
},
{
- name: "FloorWithPrecisionFloat64x4",
+ name: "GaloisFieldAffineTransformInverseUint8x32",
auxType: auxInt8,
- argLen: 1,
+ argLen: 2,
generic: true,
},
{
- name: "FloorWithPrecisionMaskedFloat64x4",
+ name: "GaloisFieldAffineTransformInverseUint8x64",
auxType: auxInt8,
argLen: 2,
generic: true,
},
{
- name: "Get128Float64x4",
+ name: "GaloisFieldAffineTransformMaskedUint8x16",
auxType: auxInt8,
- argLen: 1,
+ argLen: 3,
generic: true,
},
{
- name: "RoundWithPrecisionFloat64x4",
+ name: "GaloisFieldAffineTransformMaskedUint8x32",
auxType: auxInt8,
- argLen: 1,
+ argLen: 3,
generic: true,
},
{
- name: "RoundWithPrecisionMaskedFloat64x4",
+ name: "GaloisFieldAffineTransformMaskedUint8x64",
auxType: auxInt8,
- argLen: 2,
+ argLen: 3,
generic: true,
},
{
- name: "Set128Float64x4",
+ name: "GaloisFieldAffineTransformUint8x16",
auxType: auxInt8,
argLen: 2,
generic: true,
},
{
- name: "TruncWithPrecisionFloat64x4",
+ name: "GaloisFieldAffineTransformUint8x32",
auxType: auxInt8,
- argLen: 1,
+ argLen: 2,
generic: true,
},
{
- name: "TruncWithPrecisionMaskedFloat64x4",
+ name: "GaloisFieldAffineTransformUint8x64",
auxType: auxInt8,
argLen: 2,
generic: true,
},
{
- name: "CeilWithPrecisionFloat64x8",
+ name: "Get128Float32x8",
auxType: auxInt8,
argLen: 1,
generic: true,
},
{
- name: "CeilWithPrecisionMaskedFloat64x8",
+ name: "Get128Float64x4",
auxType: auxInt8,
- argLen: 2,
+ argLen: 1,
generic: true,
},
{
- name: "DiffWithCeilWithPrecisionFloat64x8",
+ name: "Get128Int8x32",
auxType: auxInt8,
argLen: 1,
generic: true,
},
{
- name: "DiffWithCeilWithPrecisionMaskedFloat64x8",
+ name: "Get128Int16x16",
auxType: auxInt8,
- argLen: 2,
+ argLen: 1,
generic: true,
},
{
- name: "DiffWithFloorWithPrecisionFloat64x8",
+ name: "Get128Int32x8",
auxType: auxInt8,
argLen: 1,
generic: true,
},
{
- name: "DiffWithFloorWithPrecisionMaskedFloat64x8",
+ name: "Get128Int64x4",
auxType: auxInt8,
- argLen: 2,
+ argLen: 1,
generic: true,
},
{
- name: "DiffWithRoundWithPrecisionFloat64x8",
+ name: "Get128Uint8x32",
auxType: auxInt8,
argLen: 1,
generic: true,
},
{
- name: "DiffWithRoundWithPrecisionMaskedFloat64x8",
+ name: "Get128Uint16x16",
auxType: auxInt8,
- argLen: 2,
+ argLen: 1,
generic: true,
},
{
- name: "DiffWithTruncWithPrecisionFloat64x8",
+ name: "Get128Uint32x8",
auxType: auxInt8,
argLen: 1,
generic: true,
},
{
- name: "DiffWithTruncWithPrecisionMaskedFloat64x8",
+ name: "Get128Uint64x4",
auxType: auxInt8,
- argLen: 2,
+ argLen: 1,
generic: true,
},
{
- name: "FloorWithPrecisionFloat64x8",
+ name: "GetElemInt8x16",
auxType: auxInt8,
argLen: 1,
generic: true,
},
{
- name: "FloorWithPrecisionMaskedFloat64x8",
+ name: "GetElemInt16x8",
auxType: auxInt8,
- argLen: 2,
+ argLen: 1,
generic: true,
},
{
- name: "RoundWithPrecisionFloat64x8",
+ name: "GetElemInt32x4",
auxType: auxInt8,
argLen: 1,
generic: true,
},
{
- name: "RoundWithPrecisionMaskedFloat64x8",
+ name: "GetElemInt64x2",
auxType: auxInt8,
- argLen: 2,
+ argLen: 1,
generic: true,
},
{
- name: "TruncWithPrecisionFloat64x8",
+ name: "GetElemUint8x16",
auxType: auxInt8,
argLen: 1,
generic: true,
},
{
- name: "TruncWithPrecisionMaskedFloat64x8",
+ name: "GetElemUint16x8",
auxType: auxInt8,
- argLen: 2,
+ argLen: 1,
generic: true,
},
{
- name: "Get128Int16x16",
+ name: "GetElemUint32x4",
auxType: auxInt8,
argLen: 1,
generic: true,
},
{
- name: "Set128Int16x16",
+ name: "GetElemUint64x2",
auxType: auxInt8,
- argLen: 2,
+ argLen: 1,
generic: true,
},
{
- name: "ShiftAllLeftAndFillUpperFromInt16x16",
+ name: "RotateAllLeftInt32x4",
auxType: auxInt8,
- argLen: 2,
+ argLen: 1,
generic: true,
},
{
- name: "ShiftAllLeftAndFillUpperFromMaskedInt16x16",
+ name: "RotateAllLeftInt32x8",
auxType: auxInt8,
- argLen: 3,
+ argLen: 1,
generic: true,
},
{
- name: "ShiftAllRightAndFillUpperFromInt16x16",
+ name: "RotateAllLeftInt32x16",
auxType: auxInt8,
- argLen: 2,
+ argLen: 1,
generic: true,
},
{
- name: "ShiftAllRightAndFillUpperFromMaskedInt16x16",
+ name: "RotateAllLeftInt64x2",
auxType: auxInt8,
- argLen: 3,
+ argLen: 1,
generic: true,
},
{
- name: "ShiftAllLeftAndFillUpperFromInt16x32",
+ name: "RotateAllLeftInt64x4",
auxType: auxInt8,
- argLen: 2,
+ argLen: 1,
generic: true,
},
{
- name: "ShiftAllLeftAndFillUpperFromMaskedInt16x32",
+ name: "RotateAllLeftInt64x8",
auxType: auxInt8,
- argLen: 3,
+ argLen: 1,
generic: true,
},
{
- name: "ShiftAllRightAndFillUpperFromInt16x32",
+ name: "RotateAllLeftMaskedInt32x4",
auxType: auxInt8,
argLen: 2,
generic: true,
},
{
- name: "ShiftAllRightAndFillUpperFromMaskedInt16x32",
+ name: "RotateAllLeftMaskedInt32x8",
auxType: auxInt8,
- argLen: 3,
+ argLen: 2,
generic: true,
},
{
- name: "GetElemInt16x8",
+ name: "RotateAllLeftMaskedInt32x16",
auxType: auxInt8,
- argLen: 1,
+ argLen: 2,
generic: true,
},
{
- name: "SetElemInt16x8",
+ name: "RotateAllLeftMaskedInt64x2",
auxType: auxInt8,
argLen: 2,
generic: true,
},
{
- name: "ShiftAllLeftAndFillUpperFromInt16x8",
+ name: "RotateAllLeftMaskedInt64x4",
auxType: auxInt8,
argLen: 2,
generic: true,
},
{
- name: "ShiftAllLeftAndFillUpperFromMaskedInt16x8",
+ name: "RotateAllLeftMaskedInt64x8",
auxType: auxInt8,
- argLen: 3,
+ argLen: 2,
generic: true,
},
{
- name: "ShiftAllRightAndFillUpperFromInt16x8",
+ name: "RotateAllLeftMaskedUint32x4",
auxType: auxInt8,
argLen: 2,
generic: true,
},
{
- name: "ShiftAllRightAndFillUpperFromMaskedInt16x8",
+ name: "RotateAllLeftMaskedUint32x8",
auxType: auxInt8,
- argLen: 3,
+ argLen: 2,
generic: true,
},
{
- name: "RotateAllLeftInt32x16",
+ name: "RotateAllLeftMaskedUint32x16",
auxType: auxInt8,
- argLen: 1,
+ argLen: 2,
generic: true,
},
{
- name: "RotateAllLeftMaskedInt32x16",
+ name: "RotateAllLeftMaskedUint64x2",
auxType: auxInt8,
argLen: 2,
generic: true,
},
{
- name: "RotateAllRightInt32x16",
+ name: "RotateAllLeftMaskedUint64x4",
auxType: auxInt8,
- argLen: 1,
+ argLen: 2,
generic: true,
},
{
- name: "RotateAllRightMaskedInt32x16",
+ name: "RotateAllLeftMaskedUint64x8",
auxType: auxInt8,
argLen: 2,
generic: true,
},
{
- name: "ShiftAllLeftAndFillUpperFromInt32x16",
+ name: "RotateAllLeftUint32x4",
auxType: auxInt8,
- argLen: 2,
+ argLen: 1,
generic: true,
},
{
- name: "ShiftAllLeftAndFillUpperFromMaskedInt32x16",
+ name: "RotateAllLeftUint32x8",
auxType: auxInt8,
- argLen: 3,
+ argLen: 1,
generic: true,
},
{
- name: "ShiftAllRightAndFillUpperFromInt32x16",
+ name: "RotateAllLeftUint32x16",
auxType: auxInt8,
- argLen: 2,
+ argLen: 1,
generic: true,
},
{
- name: "ShiftAllRightAndFillUpperFromMaskedInt32x16",
+ name: "RotateAllLeftUint64x2",
auxType: auxInt8,
- argLen: 3,
+ argLen: 1,
generic: true,
},
{
- name: "GetElemInt32x4",
+ name: "RotateAllLeftUint64x4",
auxType: auxInt8,
argLen: 1,
generic: true,
},
{
- name: "RotateAllLeftInt32x4",
+ name: "RotateAllLeftUint64x8",
auxType: auxInt8,
argLen: 1,
generic: true,
},
{
- name: "RotateAllLeftMaskedInt32x4",
+ name: "RotateAllRightInt32x4",
auxType: auxInt8,
- argLen: 2,
+ argLen: 1,
generic: true,
},
{
- name: "RotateAllRightInt32x4",
+ name: "RotateAllRightInt32x8",
auxType: auxInt8,
argLen: 1,
generic: true,
},
{
- name: "RotateAllRightMaskedInt32x4",
+ name: "RotateAllRightInt32x16",
auxType: auxInt8,
- argLen: 2,
+ argLen: 1,
generic: true,
},
{
- name: "SetElemInt32x4",
+ name: "RotateAllRightInt64x2",
auxType: auxInt8,
- argLen: 2,
+ argLen: 1,
generic: true,
},
{
- name: "ShiftAllLeftAndFillUpperFromInt32x4",
+ name: "RotateAllRightInt64x4",
auxType: auxInt8,
- argLen: 2,
+ argLen: 1,
generic: true,
},
{
- name: "ShiftAllLeftAndFillUpperFromMaskedInt32x4",
+ name: "RotateAllRightInt64x8",
auxType: auxInt8,
- argLen: 3,
+ argLen: 1,
generic: true,
},
{
- name: "ShiftAllRightAndFillUpperFromInt32x4",
+ name: "RotateAllRightMaskedInt32x4",
auxType: auxInt8,
argLen: 2,
generic: true,
},
{
- name: "ShiftAllRightAndFillUpperFromMaskedInt32x4",
+ name: "RotateAllRightMaskedInt32x8",
auxType: auxInt8,
- argLen: 3,
+ argLen: 2,
generic: true,
},
{
- name: "Get128Int32x8",
+ name: "RotateAllRightMaskedInt32x16",
auxType: auxInt8,
- argLen: 1,
+ argLen: 2,
generic: true,
},
{
- name: "RotateAllLeftInt32x8",
+ name: "RotateAllRightMaskedInt64x2",
auxType: auxInt8,
- argLen: 1,
+ argLen: 2,
generic: true,
},
{
- name: "RotateAllLeftMaskedInt32x8",
+ name: "RotateAllRightMaskedInt64x4",
auxType: auxInt8,
argLen: 2,
generic: true,
},
{
- name: "RotateAllRightInt32x8",
+ name: "RotateAllRightMaskedInt64x8",
auxType: auxInt8,
- argLen: 1,
+ argLen: 2,
generic: true,
},
{
- name: "RotateAllRightMaskedInt32x8",
+ name: "RotateAllRightMaskedUint32x4",
auxType: auxInt8,
argLen: 2,
generic: true,
},
{
- name: "Set128Int32x8",
+ name: "RotateAllRightMaskedUint32x8",
auxType: auxInt8,
argLen: 2,
generic: true,
},
{
- name: "ShiftAllLeftAndFillUpperFromInt32x8",
+ name: "RotateAllRightMaskedUint32x16",
auxType: auxInt8,
argLen: 2,
generic: true,
},
{
- name: "ShiftAllLeftAndFillUpperFromMaskedInt32x8",
+ name: "RotateAllRightMaskedUint64x2",
auxType: auxInt8,
- argLen: 3,
+ argLen: 2,
generic: true,
},
{
- name: "ShiftAllRightAndFillUpperFromInt32x8",
+ name: "RotateAllRightMaskedUint64x4",
auxType: auxInt8,
argLen: 2,
generic: true,
},
{
- name: "ShiftAllRightAndFillUpperFromMaskedInt32x8",
+ name: "RotateAllRightMaskedUint64x8",
auxType: auxInt8,
- argLen: 3,
+ argLen: 2,
generic: true,
},
{
- name: "GetElemInt64x2",
+ name: "RotateAllRightUint32x4",
auxType: auxInt8,
argLen: 1,
generic: true,
},
{
- name: "RotateAllLeftInt64x2",
+ name: "RotateAllRightUint32x8",
auxType: auxInt8,
argLen: 1,
generic: true,
},
{
- name: "RotateAllLeftMaskedInt64x2",
+ name: "RotateAllRightUint32x16",
auxType: auxInt8,
- argLen: 2,
+ argLen: 1,
generic: true,
},
{
- name: "RotateAllRightInt64x2",
+ name: "RotateAllRightUint64x2",
auxType: auxInt8,
argLen: 1,
generic: true,
},
{
- name: "RotateAllRightMaskedInt64x2",
+ name: "RotateAllRightUint64x4",
auxType: auxInt8,
- argLen: 2,
+ argLen: 1,
generic: true,
},
{
- name: "SetElemInt64x2",
+ name: "RotateAllRightUint64x8",
auxType: auxInt8,
- argLen: 2,
+ argLen: 1,
generic: true,
},
{
- name: "ShiftAllLeftAndFillUpperFromInt64x2",
+ name: "RoundWithPrecisionFloat32x4",
auxType: auxInt8,
- argLen: 2,
+ argLen: 1,
generic: true,
},
{
- name: "ShiftAllLeftAndFillUpperFromMaskedInt64x2",
+ name: "RoundWithPrecisionFloat32x8",
auxType: auxInt8,
- argLen: 3,
+ argLen: 1,
generic: true,
},
{
- name: "ShiftAllRightAndFillUpperFromInt64x2",
+ name: "RoundWithPrecisionFloat32x16",
auxType: auxInt8,
- argLen: 2,
+ argLen: 1,
generic: true,
},
{
- name: "ShiftAllRightAndFillUpperFromMaskedInt64x2",
+ name: "RoundWithPrecisionFloat64x2",
auxType: auxInt8,
- argLen: 3,
+ argLen: 1,
generic: true,
},
{
- name: "Get128Int64x4",
+ name: "RoundWithPrecisionFloat64x4",
auxType: auxInt8,
argLen: 1,
generic: true,
},
{
- name: "RotateAllLeftInt64x4",
+ name: "RoundWithPrecisionFloat64x8",
auxType: auxInt8,
argLen: 1,
generic: true,
},
{
- name: "RotateAllLeftMaskedInt64x4",
+ name: "RoundWithPrecisionMaskedFloat32x4",
auxType: auxInt8,
argLen: 2,
generic: true,
},
{
- name: "RotateAllRightInt64x4",
+ name: "RoundWithPrecisionMaskedFloat32x8",
auxType: auxInt8,
- argLen: 1,
+ argLen: 2,
generic: true,
},
{
- name: "RotateAllRightMaskedInt64x4",
+ name: "RoundWithPrecisionMaskedFloat32x16",
auxType: auxInt8,
argLen: 2,
generic: true,
},
{
- name: "Set128Int64x4",
+ name: "RoundWithPrecisionMaskedFloat64x2",
auxType: auxInt8,
argLen: 2,
generic: true,
},
{
- name: "ShiftAllLeftAndFillUpperFromInt64x4",
+ name: "RoundWithPrecisionMaskedFloat64x4",
auxType: auxInt8,
argLen: 2,
generic: true,
},
{
- name: "ShiftAllLeftAndFillUpperFromMaskedInt64x4",
+ name: "RoundWithPrecisionMaskedFloat64x8",
auxType: auxInt8,
- argLen: 3,
+ argLen: 2,
generic: true,
},
{
- name: "ShiftAllRightAndFillUpperFromInt64x4",
+ name: "Set128Float32x8",
auxType: auxInt8,
argLen: 2,
generic: true,
},
{
- name: "ShiftAllRightAndFillUpperFromMaskedInt64x4",
+ name: "Set128Float64x4",
auxType: auxInt8,
- argLen: 3,
+ argLen: 2,
generic: true,
},
{
- name: "RotateAllLeftInt64x8",
+ name: "Set128Int8x32",
auxType: auxInt8,
- argLen: 1,
+ argLen: 2,
generic: true,
},
{
- name: "RotateAllLeftMaskedInt64x8",
+ name: "Set128Int16x16",
auxType: auxInt8,
argLen: 2,
generic: true,
},
{
- name: "RotateAllRightInt64x8",
+ name: "Set128Int32x8",
auxType: auxInt8,
- argLen: 1,
+ argLen: 2,
generic: true,
},
{
- name: "RotateAllRightMaskedInt64x8",
+ name: "Set128Int64x4",
auxType: auxInt8,
argLen: 2,
generic: true,
},
{
- name: "ShiftAllLeftAndFillUpperFromInt64x8",
+ name: "Set128Uint8x32",
auxType: auxInt8,
argLen: 2,
generic: true,
},
{
- name: "ShiftAllLeftAndFillUpperFromMaskedInt64x8",
+ name: "Set128Uint16x16",
auxType: auxInt8,
- argLen: 3,
+ argLen: 2,
generic: true,
},
{
- name: "ShiftAllRightAndFillUpperFromInt64x8",
+ name: "Set128Uint32x8",
auxType: auxInt8,
argLen: 2,
generic: true,
},
{
- name: "ShiftAllRightAndFillUpperFromMaskedInt64x8",
+ name: "Set128Uint64x4",
auxType: auxInt8,
- argLen: 3,
+ argLen: 2,
generic: true,
},
{
- name: "GetElemInt8x16",
+ name: "SetElemInt8x16",
auxType: auxInt8,
- argLen: 1,
+ argLen: 2,
generic: true,
},
{
- name: "SetElemInt8x16",
+ name: "SetElemInt16x8",
auxType: auxInt8,
argLen: 2,
generic: true,
},
{
- name: "Get128Int8x32",
+ name: "SetElemInt32x4",
auxType: auxInt8,
- argLen: 1,
+ argLen: 2,
generic: true,
},
{
- name: "Set128Int8x32",
+ name: "SetElemInt64x2",
auxType: auxInt8,
argLen: 2,
generic: true,
},
{
- name: "Get128Uint16x16",
+ name: "SetElemUint8x16",
auxType: auxInt8,
- argLen: 1,
+ argLen: 2,
generic: true,
},
{
- name: "Set128Uint16x16",
+ name: "SetElemUint16x8",
auxType: auxInt8,
argLen: 2,
generic: true,
},
{
- name: "ShiftAllLeftAndFillUpperFromUint16x16",
+ name: "SetElemUint32x4",
auxType: auxInt8,
argLen: 2,
generic: true,
},
{
- name: "ShiftAllLeftAndFillUpperFromMaskedUint16x16",
+ name: "SetElemUint64x2",
auxType: auxInt8,
- argLen: 3,
+ argLen: 2,
generic: true,
},
{
- name: "ShiftAllRightAndFillUpperFromUint16x16",
+ name: "ShiftAllLeftAndFillUpperFromInt16x8",
auxType: auxInt8,
argLen: 2,
generic: true,
},
{
- name: "ShiftAllRightAndFillUpperFromMaskedUint16x16",
+ name: "ShiftAllLeftAndFillUpperFromInt16x16",
auxType: auxInt8,
- argLen: 3,
+ argLen: 2,
generic: true,
},
{
- name: "ShiftAllLeftAndFillUpperFromUint16x32",
+ name: "ShiftAllLeftAndFillUpperFromInt16x32",
auxType: auxInt8,
argLen: 2,
generic: true,
},
{
- name: "ShiftAllLeftAndFillUpperFromMaskedUint16x32",
+ name: "ShiftAllLeftAndFillUpperFromInt32x4",
auxType: auxInt8,
- argLen: 3,
+ argLen: 2,
generic: true,
},
{
- name: "ShiftAllRightAndFillUpperFromUint16x32",
+ name: "ShiftAllLeftAndFillUpperFromInt32x8",
auxType: auxInt8,
argLen: 2,
generic: true,
},
{
- name: "ShiftAllRightAndFillUpperFromMaskedUint16x32",
+ name: "ShiftAllLeftAndFillUpperFromInt32x16",
auxType: auxInt8,
- argLen: 3,
+ argLen: 2,
generic: true,
},
{
- name: "GetElemUint16x8",
+ name: "ShiftAllLeftAndFillUpperFromInt64x2",
auxType: auxInt8,
- argLen: 1,
+ argLen: 2,
generic: true,
},
{
- name: "SetElemUint16x8",
+ name: "ShiftAllLeftAndFillUpperFromInt64x4",
auxType: auxInt8,
argLen: 2,
generic: true,
},
{
- name: "ShiftAllLeftAndFillUpperFromUint16x8",
+ name: "ShiftAllLeftAndFillUpperFromInt64x8",
auxType: auxInt8,
argLen: 2,
generic: true,
},
{
- name: "ShiftAllLeftAndFillUpperFromMaskedUint16x8",
+ name: "ShiftAllLeftAndFillUpperFromMaskedInt16x8",
auxType: auxInt8,
argLen: 3,
generic: true,
},
{
- name: "ShiftAllRightAndFillUpperFromUint16x8",
+ name: "ShiftAllLeftAndFillUpperFromMaskedInt16x16",
auxType: auxInt8,
- argLen: 2,
+ argLen: 3,
generic: true,
},
{
- name: "ShiftAllRightAndFillUpperFromMaskedUint16x8",
+ name: "ShiftAllLeftAndFillUpperFromMaskedInt16x32",
auxType: auxInt8,
argLen: 3,
generic: true,
},
{
- name: "RotateAllLeftUint32x16",
+ name: "ShiftAllLeftAndFillUpperFromMaskedInt32x4",
auxType: auxInt8,
- argLen: 1,
+ argLen: 3,
generic: true,
},
{
- name: "RotateAllLeftMaskedUint32x16",
+ name: "ShiftAllLeftAndFillUpperFromMaskedInt32x8",
auxType: auxInt8,
- argLen: 2,
+ argLen: 3,
generic: true,
},
{
- name: "RotateAllRightUint32x16",
+ name: "ShiftAllLeftAndFillUpperFromMaskedInt32x16",
auxType: auxInt8,
- argLen: 1,
+ argLen: 3,
generic: true,
},
{
- name: "RotateAllRightMaskedUint32x16",
+ name: "ShiftAllLeftAndFillUpperFromMaskedInt64x2",
auxType: auxInt8,
- argLen: 2,
+ argLen: 3,
generic: true,
},
{
- name: "ShiftAllLeftAndFillUpperFromUint32x16",
+ name: "ShiftAllLeftAndFillUpperFromMaskedInt64x4",
auxType: auxInt8,
- argLen: 2,
+ argLen: 3,
generic: true,
},
{
- name: "ShiftAllLeftAndFillUpperFromMaskedUint32x16",
+ name: "ShiftAllLeftAndFillUpperFromMaskedInt64x8",
auxType: auxInt8,
argLen: 3,
generic: true,
},
{
- name: "ShiftAllRightAndFillUpperFromUint32x16",
+ name: "ShiftAllLeftAndFillUpperFromMaskedUint16x8",
auxType: auxInt8,
- argLen: 2,
+ argLen: 3,
generic: true,
},
{
- name: "ShiftAllRightAndFillUpperFromMaskedUint32x16",
+ name: "ShiftAllLeftAndFillUpperFromMaskedUint16x16",
auxType: auxInt8,
argLen: 3,
generic: true,
},
{
- name: "GetElemUint32x4",
+ name: "ShiftAllLeftAndFillUpperFromMaskedUint16x32",
auxType: auxInt8,
- argLen: 1,
+ argLen: 3,
generic: true,
},
{
- name: "RotateAllLeftUint32x4",
+ name: "ShiftAllLeftAndFillUpperFromMaskedUint32x4",
auxType: auxInt8,
- argLen: 1,
+ argLen: 3,
generic: true,
},
{
- name: "RotateAllLeftMaskedUint32x4",
+ name: "ShiftAllLeftAndFillUpperFromMaskedUint32x8",
auxType: auxInt8,
- argLen: 2,
+ argLen: 3,
generic: true,
},
{
- name: "RotateAllRightUint32x4",
+ name: "ShiftAllLeftAndFillUpperFromMaskedUint32x16",
auxType: auxInt8,
- argLen: 1,
+ argLen: 3,
generic: true,
},
{
- name: "RotateAllRightMaskedUint32x4",
+ name: "ShiftAllLeftAndFillUpperFromMaskedUint64x2",
auxType: auxInt8,
- argLen: 2,
+ argLen: 3,
generic: true,
},
{
- name: "SetElemUint32x4",
+ name: "ShiftAllLeftAndFillUpperFromMaskedUint64x4",
auxType: auxInt8,
- argLen: 2,
+ argLen: 3,
generic: true,
},
{
- name: "ShiftAllLeftAndFillUpperFromUint32x4",
+ name: "ShiftAllLeftAndFillUpperFromMaskedUint64x8",
auxType: auxInt8,
- argLen: 2,
+ argLen: 3,
generic: true,
},
{
- name: "ShiftAllLeftAndFillUpperFromMaskedUint32x4",
+ name: "ShiftAllLeftAndFillUpperFromUint16x8",
auxType: auxInt8,
- argLen: 3,
+ argLen: 2,
generic: true,
},
{
- name: "ShiftAllRightAndFillUpperFromUint32x4",
+ name: "ShiftAllLeftAndFillUpperFromUint16x16",
auxType: auxInt8,
argLen: 2,
generic: true,
},
{
- name: "ShiftAllRightAndFillUpperFromMaskedUint32x4",
+ name: "ShiftAllLeftAndFillUpperFromUint16x32",
auxType: auxInt8,
- argLen: 3,
+ argLen: 2,
generic: true,
},
{
- name: "Get128Uint32x8",
+ name: "ShiftAllLeftAndFillUpperFromUint32x4",
auxType: auxInt8,
- argLen: 1,
+ argLen: 2,
generic: true,
},
{
- name: "RotateAllLeftUint32x8",
+ name: "ShiftAllLeftAndFillUpperFromUint32x8",
auxType: auxInt8,
- argLen: 1,
+ argLen: 2,
generic: true,
},
{
- name: "RotateAllLeftMaskedUint32x8",
+ name: "ShiftAllLeftAndFillUpperFromUint32x16",
auxType: auxInt8,
argLen: 2,
generic: true,
},
{
- name: "RotateAllRightUint32x8",
+ name: "ShiftAllLeftAndFillUpperFromUint64x2",
auxType: auxInt8,
- argLen: 1,
+ argLen: 2,
generic: true,
},
{
- name: "RotateAllRightMaskedUint32x8",
+ name: "ShiftAllLeftAndFillUpperFromUint64x4",
auxType: auxInt8,
argLen: 2,
generic: true,
},
{
- name: "Set128Uint32x8",
+ name: "ShiftAllLeftAndFillUpperFromUint64x8",
auxType: auxInt8,
argLen: 2,
generic: true,
},
{
- name: "ShiftAllLeftAndFillUpperFromUint32x8",
+ name: "ShiftAllRightAndFillUpperFromInt16x8",
auxType: auxInt8,
argLen: 2,
generic: true,
},
{
- name: "ShiftAllLeftAndFillUpperFromMaskedUint32x8",
+ name: "ShiftAllRightAndFillUpperFromInt16x16",
auxType: auxInt8,
- argLen: 3,
+ argLen: 2,
generic: true,
},
{
- name: "ShiftAllRightAndFillUpperFromUint32x8",
+ name: "ShiftAllRightAndFillUpperFromInt16x32",
auxType: auxInt8,
argLen: 2,
generic: true,
},
{
- name: "ShiftAllRightAndFillUpperFromMaskedUint32x8",
+ name: "ShiftAllRightAndFillUpperFromInt32x4",
auxType: auxInt8,
- argLen: 3,
+ argLen: 2,
generic: true,
},
{
- name: "GetElemUint64x2",
+ name: "ShiftAllRightAndFillUpperFromInt32x8",
auxType: auxInt8,
- argLen: 1,
+ argLen: 2,
generic: true,
},
{
- name: "RotateAllLeftUint64x2",
+ name: "ShiftAllRightAndFillUpperFromInt32x16",
auxType: auxInt8,
- argLen: 1,
+ argLen: 2,
generic: true,
},
{
- name: "RotateAllLeftMaskedUint64x2",
+ name: "ShiftAllRightAndFillUpperFromInt64x2",
auxType: auxInt8,
argLen: 2,
generic: true,
},
{
- name: "RotateAllRightUint64x2",
+ name: "ShiftAllRightAndFillUpperFromInt64x4",
auxType: auxInt8,
- argLen: 1,
+ argLen: 2,
generic: true,
},
{
- name: "RotateAllRightMaskedUint64x2",
+ name: "ShiftAllRightAndFillUpperFromInt64x8",
auxType: auxInt8,
argLen: 2,
generic: true,
},
{
- name: "SetElemUint64x2",
+ name: "ShiftAllRightAndFillUpperFromMaskedInt16x8",
auxType: auxInt8,
- argLen: 2,
+ argLen: 3,
generic: true,
},
{
- name: "ShiftAllLeftAndFillUpperFromUint64x2",
+ name: "ShiftAllRightAndFillUpperFromMaskedInt16x16",
auxType: auxInt8,
- argLen: 2,
+ argLen: 3,
generic: true,
},
{
- name: "ShiftAllLeftAndFillUpperFromMaskedUint64x2",
+ name: "ShiftAllRightAndFillUpperFromMaskedInt16x32",
auxType: auxInt8,
argLen: 3,
generic: true,
},
{
- name: "ShiftAllRightAndFillUpperFromUint64x2",
+ name: "ShiftAllRightAndFillUpperFromMaskedInt32x4",
auxType: auxInt8,
- argLen: 2,
+ argLen: 3,
generic: true,
},
{
- name: "ShiftAllRightAndFillUpperFromMaskedUint64x2",
+ name: "ShiftAllRightAndFillUpperFromMaskedInt32x8",
auxType: auxInt8,
argLen: 3,
generic: true,
},
{
- name: "Get128Uint64x4",
+ name: "ShiftAllRightAndFillUpperFromMaskedInt32x16",
auxType: auxInt8,
- argLen: 1,
+ argLen: 3,
generic: true,
},
{
- name: "RotateAllLeftUint64x4",
+ name: "ShiftAllRightAndFillUpperFromMaskedInt64x2",
auxType: auxInt8,
- argLen: 1,
+ argLen: 3,
generic: true,
},
{
- name: "RotateAllLeftMaskedUint64x4",
+ name: "ShiftAllRightAndFillUpperFromMaskedInt64x4",
auxType: auxInt8,
- argLen: 2,
+ argLen: 3,
generic: true,
},
{
- name: "RotateAllRightUint64x4",
+ name: "ShiftAllRightAndFillUpperFromMaskedInt64x8",
auxType: auxInt8,
- argLen: 1,
+ argLen: 3,
generic: true,
},
{
- name: "RotateAllRightMaskedUint64x4",
+ name: "ShiftAllRightAndFillUpperFromMaskedUint16x8",
auxType: auxInt8,
- argLen: 2,
+ argLen: 3,
generic: true,
},
{
- name: "Set128Uint64x4",
+ name: "ShiftAllRightAndFillUpperFromMaskedUint16x16",
auxType: auxInt8,
- argLen: 2,
+ argLen: 3,
generic: true,
},
{
- name: "ShiftAllLeftAndFillUpperFromUint64x4",
+ name: "ShiftAllRightAndFillUpperFromMaskedUint16x32",
auxType: auxInt8,
- argLen: 2,
+ argLen: 3,
generic: true,
},
{
- name: "ShiftAllLeftAndFillUpperFromMaskedUint64x4",
+ name: "ShiftAllRightAndFillUpperFromMaskedUint32x4",
auxType: auxInt8,
argLen: 3,
generic: true,
},
{
- name: "ShiftAllRightAndFillUpperFromUint64x4",
+ name: "ShiftAllRightAndFillUpperFromMaskedUint32x8",
auxType: auxInt8,
- argLen: 2,
+ argLen: 3,
generic: true,
},
{
- name: "ShiftAllRightAndFillUpperFromMaskedUint64x4",
+ name: "ShiftAllRightAndFillUpperFromMaskedUint32x16",
auxType: auxInt8,
argLen: 3,
generic: true,
},
{
- name: "RotateAllLeftUint64x8",
+ name: "ShiftAllRightAndFillUpperFromMaskedUint64x2",
auxType: auxInt8,
- argLen: 1,
+ argLen: 3,
generic: true,
},
{
- name: "RotateAllLeftMaskedUint64x8",
+ name: "ShiftAllRightAndFillUpperFromMaskedUint64x4",
auxType: auxInt8,
- argLen: 2,
+ argLen: 3,
generic: true,
},
{
- name: "RotateAllRightUint64x8",
+ name: "ShiftAllRightAndFillUpperFromMaskedUint64x8",
auxType: auxInt8,
- argLen: 1,
+ argLen: 3,
generic: true,
},
{
- name: "RotateAllRightMaskedUint64x8",
+ name: "ShiftAllRightAndFillUpperFromUint16x8",
auxType: auxInt8,
argLen: 2,
generic: true,
},
{
- name: "ShiftAllLeftAndFillUpperFromUint64x8",
+ name: "ShiftAllRightAndFillUpperFromUint16x16",
auxType: auxInt8,
argLen: 2,
generic: true,
},
{
- name: "ShiftAllLeftAndFillUpperFromMaskedUint64x8",
+ name: "ShiftAllRightAndFillUpperFromUint16x32",
auxType: auxInt8,
- argLen: 3,
+ argLen: 2,
generic: true,
},
{
- name: "ShiftAllRightAndFillUpperFromUint64x8",
+ name: "ShiftAllRightAndFillUpperFromUint32x4",
auxType: auxInt8,
argLen: 2,
generic: true,
},
{
- name: "ShiftAllRightAndFillUpperFromMaskedUint64x8",
+ name: "ShiftAllRightAndFillUpperFromUint32x8",
auxType: auxInt8,
- argLen: 3,
+ argLen: 2,
generic: true,
},
{
- name: "GaloisFieldAffineTransformUint8x16",
+ name: "ShiftAllRightAndFillUpperFromUint32x16",
auxType: auxInt8,
argLen: 2,
generic: true,
},
{
- name: "GaloisFieldAffineTransformInverseUint8x16",
+ name: "ShiftAllRightAndFillUpperFromUint64x2",
auxType: auxInt8,
argLen: 2,
generic: true,
},
{
- name: "GaloisFieldAffineTransformInverseMaskedUint8x16",
+ name: "ShiftAllRightAndFillUpperFromUint64x4",
auxType: auxInt8,
- argLen: 3,
+ argLen: 2,
generic: true,
},
{
- name: "GaloisFieldAffineTransformMaskedUint8x16",
+ name: "ShiftAllRightAndFillUpperFromUint64x8",
auxType: auxInt8,
- argLen: 3,
+ argLen: 2,
generic: true,
},
{
- name: "GetElemUint8x16",
+ name: "TruncWithPrecisionFloat32x4",
auxType: auxInt8,
argLen: 1,
generic: true,
},
{
- name: "SetElemUint8x16",
+ name: "TruncWithPrecisionFloat32x8",
auxType: auxInt8,
- argLen: 2,
+ argLen: 1,
generic: true,
},
{
- name: "GaloisFieldAffineTransformUint8x32",
+ name: "TruncWithPrecisionFloat32x16",
auxType: auxInt8,
- argLen: 2,
+ argLen: 1,
generic: true,
},
{
- name: "GaloisFieldAffineTransformInverseUint8x32",
+ name: "TruncWithPrecisionFloat64x2",
auxType: auxInt8,
- argLen: 2,
+ argLen: 1,
generic: true,
},
{
- name: "GaloisFieldAffineTransformInverseMaskedUint8x32",
+ name: "TruncWithPrecisionFloat64x4",
auxType: auxInt8,
- argLen: 3,
+ argLen: 1,
generic: true,
},
{
- name: "GaloisFieldAffineTransformMaskedUint8x32",
+ name: "TruncWithPrecisionFloat64x8",
auxType: auxInt8,
- argLen: 3,
+ argLen: 1,
generic: true,
},
{
- name: "Get128Uint8x32",
+ name: "TruncWithPrecisionMaskedFloat32x4",
auxType: auxInt8,
- argLen: 1,
+ argLen: 2,
generic: true,
},
{
- name: "Set128Uint8x32",
+ name: "TruncWithPrecisionMaskedFloat32x8",
auxType: auxInt8,
argLen: 2,
generic: true,
},
{
- name: "GaloisFieldAffineTransformUint8x64",
+ name: "TruncWithPrecisionMaskedFloat32x16",
auxType: auxInt8,
argLen: 2,
generic: true,
},
{
- name: "GaloisFieldAffineTransformInverseUint8x64",
+ name: "TruncWithPrecisionMaskedFloat64x2",
auxType: auxInt8,
argLen: 2,
generic: true,
},
{
- name: "GaloisFieldAffineTransformInverseMaskedUint8x64",
+ name: "TruncWithPrecisionMaskedFloat64x4",
auxType: auxInt8,
- argLen: 3,
+ argLen: 2,
generic: true,
},
{
- name: "GaloisFieldAffineTransformMaskedUint8x64",
+ name: "TruncWithPrecisionMaskedFloat64x8",
auxType: auxInt8,
- argLen: 3,
+ argLen: 2,
generic: true,
},
}