cmd/internal/obj/riscv: add support for Zicond instructions

This patch implement assembler for the Zicond extension: CZEROEQZ and CZERONEZ.

Follow-up to CL 631576
Updates #75350

Change-Id: Icf4be131fe61c3b7a3bde4811cf42dc807660907
GitHub-Last-Rev: 6539cc86cbf3c49c3247ed935bcbbb31bb886dea
GitHub-Pull-Request: golang/go#75408
Reviewed-on: https://go-review.googlesource.com/c/go/+/702677
Reviewed-by: Mark Freeman <markfreeman@google.com>
Reviewed-by: Joel Sing <joel@sing.id.au>
Reviewed-by: Meng Zhuo <mengzhuo1203@gmail.com>
Reviewed-by: Michael Knyszek <mknyszek@google.com>
Reviewed-by: Mark Ryan <markdryan@rivosinc.com>
TryBot-Bypass: Joel Sing <joel@sing.id.au>

diff --git a/src/cmd/asm/internal/asm/testdata/riscv64.s b/src/cmd/asm/internal/asm/testdata/riscv64.s
index 39d2faac257e405f23a517867945194da3228cc5..07a898465fe873e60073f345134e768ee50ac0fa 100644 (file)
--- a/src/cmd/asm/internal/asm/testdata/riscv64.s
+++ b/src/cmd/asm/internal/asm/testdata/riscv64.s
@@ -195,6 +195,12 @@ start:
        RDTIME          X5                              // f32210c0
        RDINSTRET       X5                              // f32220c0
 
+       // 12.3: Integer Conditional Operations (Zicond)
+       CZEROEQZ        X5, X6, X7                      // b353530e
+       CZEROEQZ        X5, X7                          // b3d3530e
+       CZERONEZ        X5, X6, X7                      // b373530e
+       CZERONEZ        X5, X7                          // b3f3530e
+
        // 13.1: Multiplication Operations
        MUL     X5, X6, X7                              // b3035302
        MULH    X5, X6, X7                              // b3135302

diff --git a/src/cmd/internal/obj/riscv/anames.go b/src/cmd/internal/obj/riscv/anames.go
index 88ac746573b0b8e911c1debe63ea04fc19fc6001..a8807fc7a847f255a68296ae4b4857c8fa081e45 100644 (file)
--- a/src/cmd/internal/obj/riscv/anames.go
+++ b/src/cmd/internal/obj/riscv/anames.go
@@ -61,6 +61,8 @@ var Anames = []string{
        "CSRRWI",
        "CSRRSI",
        "CSRRCI",
+       "CZEROEQZ",
+       "CZERONEZ",
        "MUL",
        "MULH",
        "MULHU",

diff --git a/src/cmd/internal/obj/riscv/cpu.go b/src/cmd/internal/obj/riscv/cpu.go
index e265e0448230c759c917756788fa0d33cb95ca1d..305ef061e3d8e9bfa10b0f5fbd6bef8fbda692bd 100644 (file)
--- a/src/cmd/internal/obj/riscv/cpu.go
+++ b/src/cmd/internal/obj/riscv/cpu.go
@@ -409,6 +409,10 @@ const (
        ACSRRSI
        ACSRRCI
 
+       // 12.3: Integer Conditional Operations (Zicond)
+       ACZEROEQZ
+       ACZERONEZ
+
        // 13.1: Multiplication Operations
        AMUL
        AMULH

diff --git a/src/cmd/internal/obj/riscv/inst.go b/src/cmd/internal/obj/riscv/inst.go
index a6a03dc56523c9c4979fcd5f2668048d6114cbcc..a5b3acdb18110c169bcb0095215c61ab457e7d06 100644 (file)
--- a/src/cmd/internal/obj/riscv/inst.go
+++ b/src/cmd/internal/obj/riscv/inst.go
@@ -1,4 +1,4 @@
-// Code generated by ./parse.py -go rv64_a rv64_c rv64_d rv64_f rv64_i rv64_m rv64_q rv64_zba rv64_zbb rv64_zbs rv_a rv_c rv_c_d rv_d rv_f rv_i rv_m rv_q rv_s rv_system rv_v rv_zba rv_zbb rv_zbs rv_zicsr; DO NOT EDIT.
+// Code generated by ./parse.py -go rv64_a rv64_c rv64_d rv64_f rv64_i rv64_m rv64_q rv64_zba rv64_zbb rv64_zbs rv_a rv_c rv_c_d rv_d rv_f rv_i rv_m rv_q rv_s rv_system rv_v rv_zba rv_zbb rv_zbs rv_zicond rv_zicsr; DO NOT EDIT.
 package riscv
 
 import "cmd/internal/obj"
@@ -194,6 +194,10 @@ func encode(a obj.As) *inst {
                return &inst{0x13, 0x1, 0x0, 0x1, 1537, 0x30}
        case ACTZW:
                return &inst{0x1b, 0x1, 0x0, 0x1, 1537, 0x30}
+       case ACZEROEQZ:
+               return &inst{0x33, 0x5, 0x0, 0x0, 224, 0x7}
+       case ACZERONEZ:
+               return &inst{0x33, 0x7, 0x0, 0x0, 224, 0x7}
        case ADIV:
                return &inst{0x33, 0x4, 0x0, 0x0, 32, 0x1}
        case ADIVU:

diff --git a/src/cmd/internal/obj/riscv/obj.go b/src/cmd/internal/obj/riscv/obj.go
index fcdea57460c083d31752d1be4cad66712ba83d94..9d595f301c4bfa2f9838421fbd599c31db0e8c49 100644 (file)
--- a/src/cmd/internal/obj/riscv/obj.go
+++ b/src/cmd/internal/obj/riscv/obj.go
@@ -1948,6 +1948,10 @@ var instructions = [ALAST & obj.AMask]instructionData{
        ACSRRW & obj.AMask:  {enc: iIIEncoding, immForm: ACSRRWI},
        ACSRRWI & obj.AMask: {enc: iIIEncoding},
 
+       // 12.3: "Zicond" Extension for Integer Conditional Operations
+       ACZERONEZ & obj.AMask: {enc: rIIIEncoding, ternary: true},
+       ACZEROEQZ & obj.AMask: {enc: rIIIEncoding, ternary: true},
+
        // 13.1: Multiplication Operations
        AMUL & obj.AMask:    {enc: rIIIEncoding, ternary: true},
        AMULH & obj.AMask:   {enc: rIIIEncoding, ternary: true},