From 003b5ce1bc15cf265e74ba1ec4eb7cf801e49986 Mon Sep 17 00:00:00 2001 From: Junyang Shao Date: Fri, 19 Sep 2025 18:38:25 +0000 Subject: [PATCH] cmd/compile: fix SIMD const rematerialization condition This CL fixes a condition for the previous fix CL 704056. Cherry-picked from the dev.simd branch. This CL is not necessarily SIMD specific. Apply early to reduce risk. Test is SIMD specific so not included for now. Change-Id: I1f1f8c6f72870403cb3dff14755c43385dc0c933 Reviewed-on: https://go-review.googlesource.com/c/go/+/705499 LUCI-TryBot-Result: Go LUCI Reviewed-by: Cherry Mui Reviewed-on: https://go-review.googlesource.com/c/go/+/708864 Reviewed-by: David Chase --- src/cmd/compile/internal/ssa/regalloc.go | 17 ++++++++++------- 1 file changed, 10 insertions(+), 7 deletions(-) diff --git a/src/cmd/compile/internal/ssa/regalloc.go b/src/cmd/compile/internal/ssa/regalloc.go index 88861dfa14..e959b8ed7d 100644 --- a/src/cmd/compile/internal/ssa/regalloc.go +++ b/src/cmd/compile/internal/ssa/regalloc.go @@ -2561,22 +2561,25 @@ func (e *edgeState) processDest(loc Location, vid ID, splice **Value, pos src.XP e.s.f.Fatalf("can't find source for %s->%s: %s\n", e.p, e.b, v.LongString()) } if dstReg { - // Handle incompatible registers. + // We want to rematerialize v into a register that is incompatible with v's op's register mask. + // Instead of setting the wrong register for the rematerialized v, we should find the right register + // for it and emit an additional copy to move to the desired register. // For #70451. - if e.s.regspec(v).outputs[0].regs®Mask(1<