From 86cd9b5c905d29b18ddc3b93dff60e12143cc1c8 Mon Sep 17 00:00:00 2001 From: Junyang Shao Date: Tue, 25 Nov 2025 17:27:23 +0000 Subject: [PATCH] [dev.simd] simd, cmd/compile: add float -> int conversions This CL also fixed some documentation errors in existing APIs. Go defaults MXCSR to mask exceptions, the documentation is based on this fact. Change-Id: I745083b82b4bef93126a4b4e41f8698956963704 Reviewed-on: https://go-review.googlesource.com/c/go/+/724320 LUCI-TryBot-Result: Go LUCI Reviewed-by: David Chase --- src/cmd/compile/internal/amd64/simdssa.go | 152 +- .../compile/internal/ssa/_gen/simdAMD64.rules | 108 +- .../compile/internal/ssa/_gen/simdAMD64ops.go | 108 +- .../internal/ssa/_gen/simdgenericOps.go | 16 + src/cmd/compile/internal/ssa/opGen.go | 1418 +++++++++++++++- src/cmd/compile/internal/ssa/rewriteAMD64.go | 1500 ++++++++++++++++- .../compile/internal/ssagen/simdintrinsics.go | 16 + src/simd/_gen/simdgen/gen_simdrules.go | 4 +- src/simd/_gen/simdgen/gen_utility.go | 12 + src/simd/_gen/simdgen/godefs.go | 4 +- .../_gen/simdgen/ops/Converts/categories.yaml | 41 +- src/simd/_gen/simdgen/ops/Converts/go.yaml | 47 +- src/simd/ops_amd64.go | 134 +- 13 files changed, 3378 insertions(+), 182 deletions(-) diff --git a/src/cmd/compile/internal/amd64/simdssa.go b/src/cmd/compile/internal/amd64/simdssa.go index 3bfd4ab777..c7a22ad7fb 100644 --- a/src/cmd/compile/internal/amd64/simdssa.go +++ b/src/cmd/compile/internal/amd64/simdssa.go @@ -45,9 +45,25 @@ func ssaGenSIMDValue(s *ssagen.State, v *ssa.Value) bool { ssa.OpAMD64VCVTTPS2DQ128, ssa.OpAMD64VCVTTPS2DQ256, ssa.OpAMD64VCVTTPS2DQ512, - ssa.OpAMD64VCVTPS2UDQ128, - ssa.OpAMD64VCVTPS2UDQ256, - ssa.OpAMD64VCVTPS2UDQ512, + ssa.OpAMD64VCVTTPD2DQX128, + ssa.OpAMD64VCVTTPD2DQY128, + ssa.OpAMD64VCVTTPD2DQ256, + ssa.OpAMD64VCVTTPS2QQ256, + ssa.OpAMD64VCVTTPS2QQ512, + ssa.OpAMD64VCVTTPD2QQ128, + ssa.OpAMD64VCVTTPD2QQ256, + ssa.OpAMD64VCVTTPD2QQ512, + ssa.OpAMD64VCVTTPS2UDQ128, + ssa.OpAMD64VCVTTPS2UDQ256, + ssa.OpAMD64VCVTTPS2UDQ512, + ssa.OpAMD64VCVTTPD2UDQX128, + ssa.OpAMD64VCVTTPD2UDQY128, + ssa.OpAMD64VCVTTPD2UDQ256, + ssa.OpAMD64VCVTTPS2UQQ256, + ssa.OpAMD64VCVTTPS2UQQ512, + ssa.OpAMD64VCVTTPD2UQQ128, + ssa.OpAMD64VCVTTPD2UQQ256, + ssa.OpAMD64VCVTTPD2UQQ512, ssa.OpAMD64VPMOVSXBQ128, ssa.OpAMD64VPMOVSXWQ128, ssa.OpAMD64VPMOVSXDQ128, @@ -819,9 +835,25 @@ func ssaGenSIMDValue(s *ssagen.State, v *ssa.Value) bool { ssa.OpAMD64VCVTTPS2DQMasked128, ssa.OpAMD64VCVTTPS2DQMasked256, ssa.OpAMD64VCVTTPS2DQMasked512, - ssa.OpAMD64VCVTPS2UDQMasked128, - ssa.OpAMD64VCVTPS2UDQMasked256, - ssa.OpAMD64VCVTPS2UDQMasked512, + ssa.OpAMD64VCVTTPD2DQXMasked128, + ssa.OpAMD64VCVTTPD2DQYMasked128, + ssa.OpAMD64VCVTTPD2DQMasked256, + ssa.OpAMD64VCVTTPS2QQMasked256, + ssa.OpAMD64VCVTTPS2QQMasked512, + ssa.OpAMD64VCVTTPD2QQMasked128, + ssa.OpAMD64VCVTTPD2QQMasked256, + ssa.OpAMD64VCVTTPD2QQMasked512, + ssa.OpAMD64VCVTTPS2UDQMasked128, + ssa.OpAMD64VCVTTPS2UDQMasked256, + ssa.OpAMD64VCVTTPS2UDQMasked512, + ssa.OpAMD64VCVTTPD2UDQXMasked128, + ssa.OpAMD64VCVTTPD2UDQYMasked128, + ssa.OpAMD64VCVTTPD2UDQMasked256, + ssa.OpAMD64VCVTTPS2UQQMasked256, + ssa.OpAMD64VCVTTPS2UQQMasked512, + ssa.OpAMD64VCVTTPD2UQQMasked128, + ssa.OpAMD64VCVTTPD2UQQMasked256, + ssa.OpAMD64VCVTTPD2UQQMasked512, ssa.OpAMD64VEXPANDPSMasked128, ssa.OpAMD64VEXPANDPSMasked256, ssa.OpAMD64VEXPANDPSMasked512, @@ -1691,9 +1723,25 @@ func ssaGenSIMDValue(s *ssagen.State, v *ssa.Value) bool { ssa.OpAMD64VCVTTPS2DQMasked128load, ssa.OpAMD64VCVTTPS2DQMasked256load, ssa.OpAMD64VCVTTPS2DQMasked512load, - ssa.OpAMD64VCVTPS2UDQMasked128load, - ssa.OpAMD64VCVTPS2UDQMasked256load, - ssa.OpAMD64VCVTPS2UDQMasked512load, + ssa.OpAMD64VCVTTPD2DQXMasked128load, + ssa.OpAMD64VCVTTPD2DQYMasked128load, + ssa.OpAMD64VCVTTPD2DQMasked256load, + ssa.OpAMD64VCVTTPS2QQMasked256load, + ssa.OpAMD64VCVTTPS2QQMasked512load, + ssa.OpAMD64VCVTTPD2QQMasked128load, + ssa.OpAMD64VCVTTPD2QQMasked256load, + ssa.OpAMD64VCVTTPD2QQMasked512load, + ssa.OpAMD64VCVTTPS2UDQMasked128load, + ssa.OpAMD64VCVTTPS2UDQMasked256load, + ssa.OpAMD64VCVTTPS2UDQMasked512load, + ssa.OpAMD64VCVTTPD2UDQXMasked128load, + ssa.OpAMD64VCVTTPD2UDQYMasked128load, + ssa.OpAMD64VCVTTPD2UDQMasked256load, + ssa.OpAMD64VCVTTPS2UQQMasked256load, + ssa.OpAMD64VCVTTPS2UQQMasked512load, + ssa.OpAMD64VCVTTPD2UQQMasked128load, + ssa.OpAMD64VCVTTPD2UQQMasked256load, + ssa.OpAMD64VCVTTPD2UQQMasked512load, ssa.OpAMD64VPLZCNTDMasked128load, ssa.OpAMD64VPLZCNTDMasked256load, ssa.OpAMD64VPLZCNTDMasked512load, @@ -2077,9 +2125,23 @@ func ssaGenSIMDValue(s *ssagen.State, v *ssa.Value) bool { ssa.OpAMD64VPABSQ256load, ssa.OpAMD64VPABSQ512load, ssa.OpAMD64VCVTTPS2DQ512load, - ssa.OpAMD64VCVTPS2UDQ128load, - ssa.OpAMD64VCVTPS2UDQ256load, - ssa.OpAMD64VCVTPS2UDQ512load, + ssa.OpAMD64VCVTTPD2DQ256load, + ssa.OpAMD64VCVTTPS2QQ256load, + ssa.OpAMD64VCVTTPS2QQ512load, + ssa.OpAMD64VCVTTPD2QQ128load, + ssa.OpAMD64VCVTTPD2QQ256load, + ssa.OpAMD64VCVTTPD2QQ512load, + ssa.OpAMD64VCVTTPS2UDQ128load, + ssa.OpAMD64VCVTTPS2UDQ256load, + ssa.OpAMD64VCVTTPS2UDQ512load, + ssa.OpAMD64VCVTTPD2UDQX128load, + ssa.OpAMD64VCVTTPD2UDQY128load, + ssa.OpAMD64VCVTTPD2UDQ256load, + ssa.OpAMD64VCVTTPS2UQQ256load, + ssa.OpAMD64VCVTTPS2UQQ512load, + ssa.OpAMD64VCVTTPD2UQQ128load, + ssa.OpAMD64VCVTTPD2UQQ256load, + ssa.OpAMD64VCVTTPD2UQQ512load, ssa.OpAMD64VPLZCNTD128load, ssa.OpAMD64VPLZCNTD256load, ssa.OpAMD64VPLZCNTD512load, @@ -2329,9 +2391,25 @@ func ssaGenSIMDValue(s *ssagen.State, v *ssa.Value) bool { ssa.OpAMD64VCVTTPS2DQMasked128Merging, ssa.OpAMD64VCVTTPS2DQMasked256Merging, ssa.OpAMD64VCVTTPS2DQMasked512Merging, - ssa.OpAMD64VCVTPS2UDQMasked128Merging, - ssa.OpAMD64VCVTPS2UDQMasked256Merging, - ssa.OpAMD64VCVTPS2UDQMasked512Merging, + ssa.OpAMD64VCVTTPD2DQXMasked128Merging, + ssa.OpAMD64VCVTTPD2DQYMasked128Merging, + ssa.OpAMD64VCVTTPD2DQMasked256Merging, + ssa.OpAMD64VCVTTPS2QQMasked256Merging, + ssa.OpAMD64VCVTTPS2QQMasked512Merging, + ssa.OpAMD64VCVTTPD2QQMasked128Merging, + ssa.OpAMD64VCVTTPD2QQMasked256Merging, + ssa.OpAMD64VCVTTPD2QQMasked512Merging, + ssa.OpAMD64VCVTTPS2UDQMasked128Merging, + ssa.OpAMD64VCVTTPS2UDQMasked256Merging, + ssa.OpAMD64VCVTTPS2UDQMasked512Merging, + ssa.OpAMD64VCVTTPD2UDQXMasked128Merging, + ssa.OpAMD64VCVTTPD2UDQYMasked128Merging, + ssa.OpAMD64VCVTTPD2UDQMasked256Merging, + ssa.OpAMD64VCVTTPS2UQQMasked256Merging, + ssa.OpAMD64VCVTTPS2UQQMasked512Merging, + ssa.OpAMD64VCVTTPD2UQQMasked128Merging, + ssa.OpAMD64VCVTTPD2UQQMasked256Merging, + ssa.OpAMD64VCVTTPD2UQQMasked512Merging, ssa.OpAMD64VPMOVSXBQMasked128Merging, ssa.OpAMD64VPMOVSXWQMasked128Merging, ssa.OpAMD64VPMOVSXDQMasked128Merging, @@ -2701,12 +2779,44 @@ func ssaGenSIMDValue(s *ssagen.State, v *ssa.Value) bool { ssa.OpAMD64VCVTTPS2DQMasked256load, ssa.OpAMD64VCVTTPS2DQMasked512, ssa.OpAMD64VCVTTPS2DQMasked512load, - ssa.OpAMD64VCVTPS2UDQMasked128, - ssa.OpAMD64VCVTPS2UDQMasked128load, - ssa.OpAMD64VCVTPS2UDQMasked256, - ssa.OpAMD64VCVTPS2UDQMasked256load, - ssa.OpAMD64VCVTPS2UDQMasked512, - ssa.OpAMD64VCVTPS2UDQMasked512load, + ssa.OpAMD64VCVTTPD2DQXMasked128, + ssa.OpAMD64VCVTTPD2DQXMasked128load, + ssa.OpAMD64VCVTTPD2DQYMasked128, + ssa.OpAMD64VCVTTPD2DQYMasked128load, + ssa.OpAMD64VCVTTPD2DQMasked256, + ssa.OpAMD64VCVTTPD2DQMasked256load, + ssa.OpAMD64VCVTTPS2QQMasked256, + ssa.OpAMD64VCVTTPS2QQMasked256load, + ssa.OpAMD64VCVTTPS2QQMasked512, + ssa.OpAMD64VCVTTPS2QQMasked512load, + ssa.OpAMD64VCVTTPD2QQMasked128, + ssa.OpAMD64VCVTTPD2QQMasked128load, + ssa.OpAMD64VCVTTPD2QQMasked256, + ssa.OpAMD64VCVTTPD2QQMasked256load, + ssa.OpAMD64VCVTTPD2QQMasked512, + ssa.OpAMD64VCVTTPD2QQMasked512load, + ssa.OpAMD64VCVTTPS2UDQMasked128, + ssa.OpAMD64VCVTTPS2UDQMasked128load, + ssa.OpAMD64VCVTTPS2UDQMasked256, + ssa.OpAMD64VCVTTPS2UDQMasked256load, + ssa.OpAMD64VCVTTPS2UDQMasked512, + ssa.OpAMD64VCVTTPS2UDQMasked512load, + ssa.OpAMD64VCVTTPD2UDQXMasked128, + ssa.OpAMD64VCVTTPD2UDQXMasked128load, + ssa.OpAMD64VCVTTPD2UDQYMasked128, + ssa.OpAMD64VCVTTPD2UDQYMasked128load, + ssa.OpAMD64VCVTTPD2UDQMasked256, + ssa.OpAMD64VCVTTPD2UDQMasked256load, + ssa.OpAMD64VCVTTPS2UQQMasked256, + ssa.OpAMD64VCVTTPS2UQQMasked256load, + ssa.OpAMD64VCVTTPS2UQQMasked512, + ssa.OpAMD64VCVTTPS2UQQMasked512load, + ssa.OpAMD64VCVTTPD2UQQMasked128, + ssa.OpAMD64VCVTTPD2UQQMasked128load, + ssa.OpAMD64VCVTTPD2UQQMasked256, + ssa.OpAMD64VCVTTPD2UQQMasked256load, + ssa.OpAMD64VCVTTPD2UQQMasked512, + ssa.OpAMD64VCVTTPD2UQQMasked512load, ssa.OpAMD64VDIVPSMasked128, ssa.OpAMD64VDIVPSMasked128load, ssa.OpAMD64VDIVPSMasked256, diff --git a/src/cmd/compile/internal/ssa/_gen/simdAMD64.rules b/src/cmd/compile/internal/ssa/_gen/simdAMD64.rules index 464db33d3b..e81bdbcbbb 100644 --- a/src/cmd/compile/internal/ssa/_gen/simdAMD64.rules +++ b/src/cmd/compile/internal/ssa/_gen/simdAMD64.rules @@ -252,9 +252,25 @@ (ConvertToInt32Float32x4 ...) => (VCVTTPS2DQ128 ...) (ConvertToInt32Float32x8 ...) => (VCVTTPS2DQ256 ...) (ConvertToInt32Float32x16 ...) => (VCVTTPS2DQ512 ...) -(ConvertToUint32Float32x4 ...) => (VCVTPS2UDQ128 ...) -(ConvertToUint32Float32x8 ...) => (VCVTPS2UDQ256 ...) -(ConvertToUint32Float32x16 ...) => (VCVTPS2UDQ512 ...) +(ConvertToInt32Float64x2 ...) => (VCVTTPD2DQX128 ...) +(ConvertToInt32Float64x4 ...) => (VCVTTPD2DQY128 ...) +(ConvertToInt32Float64x8 ...) => (VCVTTPD2DQ256 ...) +(ConvertToInt64Float32x4 ...) => (VCVTTPS2QQ256 ...) +(ConvertToInt64Float32x8 ...) => (VCVTTPS2QQ512 ...) +(ConvertToInt64Float64x2 ...) => (VCVTTPD2QQ128 ...) +(ConvertToInt64Float64x4 ...) => (VCVTTPD2QQ256 ...) +(ConvertToInt64Float64x8 ...) => (VCVTTPD2QQ512 ...) +(ConvertToUint32Float32x4 ...) => (VCVTTPS2UDQ128 ...) +(ConvertToUint32Float32x8 ...) => (VCVTTPS2UDQ256 ...) +(ConvertToUint32Float32x16 ...) => (VCVTTPS2UDQ512 ...) +(ConvertToUint32Float64x2 ...) => (VCVTTPD2UDQX128 ...) +(ConvertToUint32Float64x4 ...) => (VCVTTPD2UDQY128 ...) +(ConvertToUint32Float64x8 ...) => (VCVTTPD2UDQ256 ...) +(ConvertToUint64Float32x4 ...) => (VCVTTPS2UQQ256 ...) +(ConvertToUint64Float32x8 ...) => (VCVTTPS2UQQ512 ...) +(ConvertToUint64Float64x2 ...) => (VCVTTPD2UQQ128 ...) +(ConvertToUint64Float64x4 ...) => (VCVTTPD2UQQ256 ...) +(ConvertToUint64Float64x8 ...) => (VCVTTPD2UQQ512 ...) (CopySignInt8x16 ...) => (VPSIGNB128 ...) (CopySignInt8x32 ...) => (VPSIGNB256 ...) (CopySignInt16x8 ...) => (VPSIGNW128 ...) @@ -1443,9 +1459,25 @@ (VMOVDQU32Masked128 (VCVTTPS2DQ128 x) mask) => (VCVTTPS2DQMasked128 x mask) (VMOVDQU32Masked256 (VCVTTPS2DQ256 x) mask) => (VCVTTPS2DQMasked256 x mask) (VMOVDQU32Masked512 (VCVTTPS2DQ512 x) mask) => (VCVTTPS2DQMasked512 x mask) -(VMOVDQU32Masked128 (VCVTPS2UDQ128 x) mask) => (VCVTPS2UDQMasked128 x mask) -(VMOVDQU32Masked256 (VCVTPS2UDQ256 x) mask) => (VCVTPS2UDQMasked256 x mask) -(VMOVDQU32Masked512 (VCVTPS2UDQ512 x) mask) => (VCVTPS2UDQMasked512 x mask) +(VMOVDQU64Masked128 (VCVTTPD2DQX128 x) mask) => (VCVTTPD2DQXMasked128 x mask) +(VMOVDQU64Masked128 (VCVTTPD2DQY128 x) mask) => (VCVTTPD2DQYMasked128 x mask) +(VMOVDQU64Masked256 (VCVTTPD2DQ256 x) mask) => (VCVTTPD2DQMasked256 x mask) +(VMOVDQU32Masked256 (VCVTTPS2QQ256 x) mask) => (VCVTTPS2QQMasked256 x mask) +(VMOVDQU32Masked512 (VCVTTPS2QQ512 x) mask) => (VCVTTPS2QQMasked512 x mask) +(VMOVDQU64Masked128 (VCVTTPD2QQ128 x) mask) => (VCVTTPD2QQMasked128 x mask) +(VMOVDQU64Masked256 (VCVTTPD2QQ256 x) mask) => (VCVTTPD2QQMasked256 x mask) +(VMOVDQU64Masked512 (VCVTTPD2QQ512 x) mask) => (VCVTTPD2QQMasked512 x mask) +(VMOVDQU32Masked128 (VCVTTPS2UDQ128 x) mask) => (VCVTTPS2UDQMasked128 x mask) +(VMOVDQU32Masked256 (VCVTTPS2UDQ256 x) mask) => (VCVTTPS2UDQMasked256 x mask) +(VMOVDQU32Masked512 (VCVTTPS2UDQ512 x) mask) => (VCVTTPS2UDQMasked512 x mask) +(VMOVDQU64Masked128 (VCVTTPD2UDQX128 x) mask) => (VCVTTPD2UDQXMasked128 x mask) +(VMOVDQU64Masked128 (VCVTTPD2UDQY128 x) mask) => (VCVTTPD2UDQYMasked128 x mask) +(VMOVDQU64Masked256 (VCVTTPD2UDQ256 x) mask) => (VCVTTPD2UDQMasked256 x mask) +(VMOVDQU32Masked256 (VCVTTPS2UQQ256 x) mask) => (VCVTTPS2UQQMasked256 x mask) +(VMOVDQU32Masked512 (VCVTTPS2UQQ512 x) mask) => (VCVTTPS2UQQMasked512 x mask) +(VMOVDQU64Masked128 (VCVTTPD2UQQ128 x) mask) => (VCVTTPD2UQQMasked128 x mask) +(VMOVDQU64Masked256 (VCVTTPD2UQQ256 x) mask) => (VCVTTPD2UQQMasked256 x mask) +(VMOVDQU64Masked512 (VCVTTPD2UQQ512 x) mask) => (VCVTTPD2UQQMasked512 x mask) (VMOVDQU32Masked128 (VDIVPS128 x y) mask) => (VDIVPSMasked128 x y mask) (VMOVDQU32Masked256 (VDIVPS256 x y) mask) => (VDIVPSMasked256 x y mask) (VMOVDQU32Masked512 (VDIVPS512 x y) mask) => (VDIVPSMasked512 x y mask) @@ -1907,8 +1939,8 @@ (VPBLENDMBMasked512 dst (VPSUBSB512 x y) mask) => (VPSUBSBMasked512Merging dst x y mask) (VPBLENDMBMasked512 dst (VPSUBUSB512 x y) mask) => (VPSUBUSBMasked512Merging dst x y mask) (VPBLENDMDMasked512 dst (VADDPS512 x y) mask) => (VADDPSMasked512Merging dst x y mask) -(VPBLENDMDMasked512 dst (VCVTPS2UDQ512 x) mask) => (VCVTPS2UDQMasked512Merging dst x mask) (VPBLENDMDMasked512 dst (VCVTTPS2DQ512 x) mask) => (VCVTTPS2DQMasked512Merging dst x mask) +(VPBLENDMDMasked512 dst (VCVTTPS2UDQ512 x) mask) => (VCVTTPS2UDQMasked512Merging dst x mask) (VPBLENDMDMasked512 dst (VDIVPS512 x y) mask) => (VDIVPSMasked512Merging dst x y mask) (VPBLENDMDMasked512 dst (VMAXPS512 x y) mask) => (VMAXPSMasked512Merging dst x y mask) (VPBLENDMDMasked512 dst (VMINPS512 x y) mask) => (VMINPSMasked512Merging dst x y mask) @@ -1953,6 +1985,10 @@ (VPBLENDMDMasked512 dst (VSQRTPS512 x) mask) => (VSQRTPSMasked512Merging dst x mask) (VPBLENDMDMasked512 dst (VSUBPS512 x y) mask) => (VSUBPSMasked512Merging dst x y mask) (VPBLENDMQMasked512 dst (VADDPD512 x y) mask) => (VADDPDMasked512Merging dst x y mask) +(VPBLENDMQMasked512 dst (VCVTTPD2DQ256 x) mask) => (VCVTTPD2DQMasked256Merging dst x mask) +(VPBLENDMQMasked512 dst (VCVTTPD2QQ512 x) mask) => (VCVTTPD2QQMasked512Merging dst x mask) +(VPBLENDMQMasked512 dst (VCVTTPD2UDQ256 x) mask) => (VCVTTPD2UDQMasked256Merging dst x mask) +(VPBLENDMQMasked512 dst (VCVTTPD2UQQ512 x) mask) => (VCVTTPD2UQQMasked512Merging dst x mask) (VPBLENDMQMasked512 dst (VDIVPD512 x y) mask) => (VDIVPDMasked512Merging dst x y mask) (VPBLENDMQMasked512 dst (VMAXPD512 x y) mask) => (VMAXPDMasked512Merging dst x y mask) (VPBLENDMQMasked512 dst (VMINPD512 x y) mask) => (VMINPDMasked512Merging dst x y mask) @@ -2033,8 +2069,14 @@ (VPBLENDVB128 dst (VBROADCASTSS128 x) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VBROADCASTSSMasked128Merging dst x (VPMOVVec32x4ToM mask)) (VPBLENDVB128 dst (VBROADCASTSS256 x) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VBROADCASTSSMasked256Merging dst x (VPMOVVec32x4ToM mask)) (VPBLENDVB128 dst (VBROADCASTSS512 x) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VBROADCASTSSMasked512Merging dst x (VPMOVVec32x4ToM mask)) -(VPBLENDVB128 dst (VCVTPS2UDQ128 x) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VCVTPS2UDQMasked128Merging dst x (VPMOVVec32x4ToM mask)) +(VPBLENDVB128 dst (VCVTTPD2DQX128 x) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VCVTTPD2DQXMasked128Merging dst x (VPMOVVec64x2ToM mask)) +(VPBLENDVB128 dst (VCVTTPD2QQ128 x) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VCVTTPD2QQMasked128Merging dst x (VPMOVVec64x2ToM mask)) +(VPBLENDVB128 dst (VCVTTPD2UDQX128 x) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VCVTTPD2UDQXMasked128Merging dst x (VPMOVVec64x2ToM mask)) +(VPBLENDVB128 dst (VCVTTPD2UQQ128 x) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VCVTTPD2UQQMasked128Merging dst x (VPMOVVec64x2ToM mask)) (VPBLENDVB128 dst (VCVTTPS2DQ128 x) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VCVTTPS2DQMasked128Merging dst x (VPMOVVec32x4ToM mask)) +(VPBLENDVB128 dst (VCVTTPS2QQ256 x) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VCVTTPS2QQMasked256Merging dst x (VPMOVVec32x4ToM mask)) +(VPBLENDVB128 dst (VCVTTPS2UDQ128 x) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VCVTTPS2UDQMasked128Merging dst x (VPMOVVec32x4ToM mask)) +(VPBLENDVB128 dst (VCVTTPS2UQQ256 x) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VCVTTPS2UQQMasked256Merging dst x (VPMOVVec32x4ToM mask)) (VPBLENDVB128 dst (VDIVPD128 x y) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VDIVPDMasked128Merging dst x y (VPMOVVec64x2ToM mask)) (VPBLENDVB128 dst (VDIVPS128 x y) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VDIVPSMasked128Merging dst x y (VPMOVVec32x4ToM mask)) (VPBLENDVB128 dst (VGF2P8MULB128 x y) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VGF2P8MULBMasked128Merging dst x y (VPMOVVec8x16ToM mask)) @@ -2202,8 +2244,14 @@ (VPBLENDVB128 dst (VSUBPS128 x y) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VSUBPSMasked128Merging dst x y (VPMOVVec32x4ToM mask)) (VPBLENDVB256 dst (VADDPD256 x y) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VADDPDMasked256Merging dst x y (VPMOVVec64x4ToM mask)) (VPBLENDVB256 dst (VADDPS256 x y) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VADDPSMasked256Merging dst x y (VPMOVVec32x8ToM mask)) -(VPBLENDVB256 dst (VCVTPS2UDQ256 x) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VCVTPS2UDQMasked256Merging dst x (VPMOVVec32x8ToM mask)) +(VPBLENDVB256 dst (VCVTTPD2DQY128 x) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VCVTTPD2DQYMasked128Merging dst x (VPMOVVec64x4ToM mask)) +(VPBLENDVB256 dst (VCVTTPD2QQ256 x) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VCVTTPD2QQMasked256Merging dst x (VPMOVVec64x4ToM mask)) +(VPBLENDVB256 dst (VCVTTPD2UDQY128 x) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VCVTTPD2UDQYMasked128Merging dst x (VPMOVVec64x4ToM mask)) +(VPBLENDVB256 dst (VCVTTPD2UQQ256 x) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VCVTTPD2UQQMasked256Merging dst x (VPMOVVec64x4ToM mask)) (VPBLENDVB256 dst (VCVTTPS2DQ256 x) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VCVTTPS2DQMasked256Merging dst x (VPMOVVec32x8ToM mask)) +(VPBLENDVB256 dst (VCVTTPS2QQ512 x) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VCVTTPS2QQMasked512Merging dst x (VPMOVVec32x8ToM mask)) +(VPBLENDVB256 dst (VCVTTPS2UDQ256 x) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VCVTTPS2UDQMasked256Merging dst x (VPMOVVec32x8ToM mask)) +(VPBLENDVB256 dst (VCVTTPS2UQQ512 x) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VCVTTPS2UQQMasked512Merging dst x (VPMOVVec32x8ToM mask)) (VPBLENDVB256 dst (VDIVPD256 x y) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VDIVPDMasked256Merging dst x y (VPMOVVec64x4ToM mask)) (VPBLENDVB256 dst (VDIVPS256 x y) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VDIVPSMasked256Merging dst x y (VPMOVVec32x8ToM mask)) (VPBLENDVB256 dst (VGF2P8MULB256 x y) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VGF2P8MULBMasked256Merging dst x y (VPMOVVec8x32ToM mask)) @@ -2428,15 +2476,45 @@ (VPERMI2PDMasked512 x y l:(VMOVDQUload512 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPERMI2PDMasked512load {sym} [off] x y ptr mask mem) (VPERMI2QMasked512 x y l:(VMOVDQUload512 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPERMI2QMasked512load {sym} [off] x y ptr mask mem) (VCVTTPS2DQ512 l:(VMOVDQUload512 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VCVTTPS2DQ512load {sym} [off] ptr mem) +(VCVTTPD2DQ256 l:(VMOVDQUload512 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VCVTTPD2DQ256load {sym} [off] ptr mem) (VCVTTPS2DQMasked128 l:(VMOVDQUload128 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VCVTTPS2DQMasked128load {sym} [off] ptr mask mem) (VCVTTPS2DQMasked256 l:(VMOVDQUload256 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VCVTTPS2DQMasked256load {sym} [off] ptr mask mem) (VCVTTPS2DQMasked512 l:(VMOVDQUload512 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VCVTTPS2DQMasked512load {sym} [off] ptr mask mem) -(VCVTPS2UDQ128 l:(VMOVDQUload128 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VCVTPS2UDQ128load {sym} [off] ptr mem) -(VCVTPS2UDQ256 l:(VMOVDQUload256 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VCVTPS2UDQ256load {sym} [off] ptr mem) -(VCVTPS2UDQ512 l:(VMOVDQUload512 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VCVTPS2UDQ512load {sym} [off] ptr mem) -(VCVTPS2UDQMasked128 l:(VMOVDQUload128 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VCVTPS2UDQMasked128load {sym} [off] ptr mask mem) -(VCVTPS2UDQMasked256 l:(VMOVDQUload256 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VCVTPS2UDQMasked256load {sym} [off] ptr mask mem) -(VCVTPS2UDQMasked512 l:(VMOVDQUload512 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VCVTPS2UDQMasked512load {sym} [off] ptr mask mem) +(VCVTTPD2DQXMasked128 l:(VMOVDQUload128 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VCVTTPD2DQXMasked128load {sym} [off] ptr mask mem) +(VCVTTPD2DQYMasked128 l:(VMOVDQUload256 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VCVTTPD2DQYMasked128load {sym} [off] ptr mask mem) +(VCVTTPD2DQMasked256 l:(VMOVDQUload512 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VCVTTPD2DQMasked256load {sym} [off] ptr mask mem) +(VCVTTPS2QQ256 l:(VMOVDQUload128 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VCVTTPS2QQ256load {sym} [off] ptr mem) +(VCVTTPS2QQ512 l:(VMOVDQUload256 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VCVTTPS2QQ512load {sym} [off] ptr mem) +(VCVTTPD2QQ128 l:(VMOVDQUload128 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VCVTTPD2QQ128load {sym} [off] ptr mem) +(VCVTTPD2QQ256 l:(VMOVDQUload256 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VCVTTPD2QQ256load {sym} [off] ptr mem) +(VCVTTPD2QQ512 l:(VMOVDQUload512 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VCVTTPD2QQ512load {sym} [off] ptr mem) +(VCVTTPS2QQMasked256 l:(VMOVDQUload128 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VCVTTPS2QQMasked256load {sym} [off] ptr mask mem) +(VCVTTPS2QQMasked512 l:(VMOVDQUload256 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VCVTTPS2QQMasked512load {sym} [off] ptr mask mem) +(VCVTTPD2QQMasked128 l:(VMOVDQUload128 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VCVTTPD2QQMasked128load {sym} [off] ptr mask mem) +(VCVTTPD2QQMasked256 l:(VMOVDQUload256 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VCVTTPD2QQMasked256load {sym} [off] ptr mask mem) +(VCVTTPD2QQMasked512 l:(VMOVDQUload512 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VCVTTPD2QQMasked512load {sym} [off] ptr mask mem) +(VCVTTPS2UDQ128 l:(VMOVDQUload128 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VCVTTPS2UDQ128load {sym} [off] ptr mem) +(VCVTTPS2UDQ256 l:(VMOVDQUload256 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VCVTTPS2UDQ256load {sym} [off] ptr mem) +(VCVTTPS2UDQ512 l:(VMOVDQUload512 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VCVTTPS2UDQ512load {sym} [off] ptr mem) +(VCVTTPD2UDQX128 l:(VMOVDQUload128 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VCVTTPD2UDQX128load {sym} [off] ptr mem) +(VCVTTPD2UDQY128 l:(VMOVDQUload256 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VCVTTPD2UDQY128load {sym} [off] ptr mem) +(VCVTTPD2UDQ256 l:(VMOVDQUload512 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VCVTTPD2UDQ256load {sym} [off] ptr mem) +(VCVTTPS2UDQMasked128 l:(VMOVDQUload128 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VCVTTPS2UDQMasked128load {sym} [off] ptr mask mem) +(VCVTTPS2UDQMasked256 l:(VMOVDQUload256 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VCVTTPS2UDQMasked256load {sym} [off] ptr mask mem) +(VCVTTPS2UDQMasked512 l:(VMOVDQUload512 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VCVTTPS2UDQMasked512load {sym} [off] ptr mask mem) +(VCVTTPD2UDQXMasked128 l:(VMOVDQUload128 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VCVTTPD2UDQXMasked128load {sym} [off] ptr mask mem) +(VCVTTPD2UDQYMasked128 l:(VMOVDQUload256 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VCVTTPD2UDQYMasked128load {sym} [off] ptr mask mem) +(VCVTTPD2UDQMasked256 l:(VMOVDQUload512 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VCVTTPD2UDQMasked256load {sym} [off] ptr mask mem) +(VCVTTPS2UQQ256 l:(VMOVDQUload128 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VCVTTPS2UQQ256load {sym} [off] ptr mem) +(VCVTTPS2UQQ512 l:(VMOVDQUload256 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VCVTTPS2UQQ512load {sym} [off] ptr mem) +(VCVTTPD2UQQ128 l:(VMOVDQUload128 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VCVTTPD2UQQ128load {sym} [off] ptr mem) +(VCVTTPD2UQQ256 l:(VMOVDQUload256 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VCVTTPD2UQQ256load {sym} [off] ptr mem) +(VCVTTPD2UQQ512 l:(VMOVDQUload512 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VCVTTPD2UQQ512load {sym} [off] ptr mem) +(VCVTTPS2UQQMasked256 l:(VMOVDQUload128 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VCVTTPS2UQQMasked256load {sym} [off] ptr mask mem) +(VCVTTPS2UQQMasked512 l:(VMOVDQUload256 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VCVTTPS2UQQMasked512load {sym} [off] ptr mask mem) +(VCVTTPD2UQQMasked128 l:(VMOVDQUload128 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VCVTTPD2UQQMasked128load {sym} [off] ptr mask mem) +(VCVTTPD2UQQMasked256 l:(VMOVDQUload256 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VCVTTPD2UQQMasked256load {sym} [off] ptr mask mem) +(VCVTTPD2UQQMasked512 l:(VMOVDQUload512 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VCVTTPD2UQQMasked512load {sym} [off] ptr mask mem) (VDIVPS512 x l:(VMOVDQUload512 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VDIVPS512load {sym} [off] x ptr mem) (VDIVPD512 x l:(VMOVDQUload512 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VDIVPD512load {sym} [off] x ptr mem) (VDIVPSMasked128 x l:(VMOVDQUload128 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VDIVPSMasked128load {sym} [off] x ptr mask mem) diff --git a/src/cmd/compile/internal/ssa/_gen/simdAMD64ops.go b/src/cmd/compile/internal/ssa/_gen/simdAMD64ops.go index 53d18b22d6..fb95610c5e 100644 --- a/src/cmd/compile/internal/ssa/_gen/simdAMD64ops.go +++ b/src/cmd/compile/internal/ssa/_gen/simdAMD64ops.go @@ -56,18 +56,50 @@ func simdAMD64Ops(v11, v21, v2k, vkv, v2kv, v2kk, v31, v3kv, vgpv, vgp, vfpv, vf {name: "VCOMPRESSPSMasked128", argLength: 2, reg: wkw, asm: "VCOMPRESSPS", commutative: false, typ: "Vec128", resultInArg0: false}, {name: "VCOMPRESSPSMasked256", argLength: 2, reg: wkw, asm: "VCOMPRESSPS", commutative: false, typ: "Vec256", resultInArg0: false}, {name: "VCOMPRESSPSMasked512", argLength: 2, reg: wkw, asm: "VCOMPRESSPS", commutative: false, typ: "Vec512", resultInArg0: false}, - {name: "VCVTPS2UDQ128", argLength: 1, reg: w11, asm: "VCVTPS2UDQ", commutative: false, typ: "Vec128", resultInArg0: false}, - {name: "VCVTPS2UDQ256", argLength: 1, reg: w11, asm: "VCVTPS2UDQ", commutative: false, typ: "Vec256", resultInArg0: false}, - {name: "VCVTPS2UDQ512", argLength: 1, reg: w11, asm: "VCVTPS2UDQ", commutative: false, typ: "Vec512", resultInArg0: false}, - {name: "VCVTPS2UDQMasked128", argLength: 2, reg: wkw, asm: "VCVTPS2UDQ", commutative: false, typ: "Vec128", resultInArg0: false}, - {name: "VCVTPS2UDQMasked256", argLength: 2, reg: wkw, asm: "VCVTPS2UDQ", commutative: false, typ: "Vec256", resultInArg0: false}, - {name: "VCVTPS2UDQMasked512", argLength: 2, reg: wkw, asm: "VCVTPS2UDQ", commutative: false, typ: "Vec512", resultInArg0: false}, + {name: "VCVTTPD2DQ256", argLength: 1, reg: w11, asm: "VCVTTPD2DQ", commutative: false, typ: "Vec256", resultInArg0: false}, + {name: "VCVTTPD2DQMasked256", argLength: 2, reg: wkw, asm: "VCVTTPD2DQ", commutative: false, typ: "Vec256", resultInArg0: false}, + {name: "VCVTTPD2DQX128", argLength: 1, reg: v11, asm: "VCVTTPD2DQX", commutative: false, typ: "Vec128", resultInArg0: false}, + {name: "VCVTTPD2DQXMasked128", argLength: 2, reg: wkw, asm: "VCVTTPD2DQX", commutative: false, typ: "Vec128", resultInArg0: false}, + {name: "VCVTTPD2DQY128", argLength: 1, reg: v11, asm: "VCVTTPD2DQY", commutative: false, typ: "Vec128", resultInArg0: false}, + {name: "VCVTTPD2DQYMasked128", argLength: 2, reg: wkw, asm: "VCVTTPD2DQY", commutative: false, typ: "Vec128", resultInArg0: false}, + {name: "VCVTTPD2QQ128", argLength: 1, reg: w11, asm: "VCVTTPD2QQ", commutative: false, typ: "Vec128", resultInArg0: false}, + {name: "VCVTTPD2QQ256", argLength: 1, reg: w11, asm: "VCVTTPD2QQ", commutative: false, typ: "Vec256", resultInArg0: false}, + {name: "VCVTTPD2QQ512", argLength: 1, reg: w11, asm: "VCVTTPD2QQ", commutative: false, typ: "Vec512", resultInArg0: false}, + {name: "VCVTTPD2QQMasked128", argLength: 2, reg: wkw, asm: "VCVTTPD2QQ", commutative: false, typ: "Vec128", resultInArg0: false}, + {name: "VCVTTPD2QQMasked256", argLength: 2, reg: wkw, asm: "VCVTTPD2QQ", commutative: false, typ: "Vec256", resultInArg0: false}, + {name: "VCVTTPD2QQMasked512", argLength: 2, reg: wkw, asm: "VCVTTPD2QQ", commutative: false, typ: "Vec512", resultInArg0: false}, + {name: "VCVTTPD2UDQ256", argLength: 1, reg: w11, asm: "VCVTTPD2UDQ", commutative: false, typ: "Vec256", resultInArg0: false}, + {name: "VCVTTPD2UDQMasked256", argLength: 2, reg: wkw, asm: "VCVTTPD2UDQ", commutative: false, typ: "Vec256", resultInArg0: false}, + {name: "VCVTTPD2UDQX128", argLength: 1, reg: w11, asm: "VCVTTPD2UDQX", commutative: false, typ: "Vec128", resultInArg0: false}, + {name: "VCVTTPD2UDQXMasked128", argLength: 2, reg: wkw, asm: "VCVTTPD2UDQX", commutative: false, typ: "Vec128", resultInArg0: false}, + {name: "VCVTTPD2UDQY128", argLength: 1, reg: w11, asm: "VCVTTPD2UDQY", commutative: false, typ: "Vec128", resultInArg0: false}, + {name: "VCVTTPD2UDQYMasked128", argLength: 2, reg: wkw, asm: "VCVTTPD2UDQY", commutative: false, typ: "Vec128", resultInArg0: false}, + {name: "VCVTTPD2UQQ128", argLength: 1, reg: w11, asm: "VCVTTPD2UQQ", commutative: false, typ: "Vec128", resultInArg0: false}, + {name: "VCVTTPD2UQQ256", argLength: 1, reg: w11, asm: "VCVTTPD2UQQ", commutative: false, typ: "Vec256", resultInArg0: false}, + {name: "VCVTTPD2UQQ512", argLength: 1, reg: w11, asm: "VCVTTPD2UQQ", commutative: false, typ: "Vec512", resultInArg0: false}, + {name: "VCVTTPD2UQQMasked128", argLength: 2, reg: wkw, asm: "VCVTTPD2UQQ", commutative: false, typ: "Vec128", resultInArg0: false}, + {name: "VCVTTPD2UQQMasked256", argLength: 2, reg: wkw, asm: "VCVTTPD2UQQ", commutative: false, typ: "Vec256", resultInArg0: false}, + {name: "VCVTTPD2UQQMasked512", argLength: 2, reg: wkw, asm: "VCVTTPD2UQQ", commutative: false, typ: "Vec512", resultInArg0: false}, {name: "VCVTTPS2DQ128", argLength: 1, reg: v11, asm: "VCVTTPS2DQ", commutative: false, typ: "Vec128", resultInArg0: false}, {name: "VCVTTPS2DQ256", argLength: 1, reg: v11, asm: "VCVTTPS2DQ", commutative: false, typ: "Vec256", resultInArg0: false}, {name: "VCVTTPS2DQ512", argLength: 1, reg: w11, asm: "VCVTTPS2DQ", commutative: false, typ: "Vec512", resultInArg0: false}, {name: "VCVTTPS2DQMasked128", argLength: 2, reg: wkw, asm: "VCVTTPS2DQ", commutative: false, typ: "Vec128", resultInArg0: false}, {name: "VCVTTPS2DQMasked256", argLength: 2, reg: wkw, asm: "VCVTTPS2DQ", commutative: false, typ: "Vec256", resultInArg0: false}, {name: "VCVTTPS2DQMasked512", argLength: 2, reg: wkw, asm: "VCVTTPS2DQ", commutative: false, typ: "Vec512", resultInArg0: false}, + {name: "VCVTTPS2QQ256", argLength: 1, reg: w11, asm: "VCVTTPS2QQ", commutative: false, typ: "Vec256", resultInArg0: false}, + {name: "VCVTTPS2QQ512", argLength: 1, reg: w11, asm: "VCVTTPS2QQ", commutative: false, typ: "Vec512", resultInArg0: false}, + {name: "VCVTTPS2QQMasked256", argLength: 2, reg: wkw, asm: "VCVTTPS2QQ", commutative: false, typ: "Vec256", resultInArg0: false}, + {name: "VCVTTPS2QQMasked512", argLength: 2, reg: wkw, asm: "VCVTTPS2QQ", commutative: false, typ: "Vec512", resultInArg0: false}, + {name: "VCVTTPS2UDQ128", argLength: 1, reg: w11, asm: "VCVTTPS2UDQ", commutative: false, typ: "Vec128", resultInArg0: false}, + {name: "VCVTTPS2UDQ256", argLength: 1, reg: w11, asm: "VCVTTPS2UDQ", commutative: false, typ: "Vec256", resultInArg0: false}, + {name: "VCVTTPS2UDQ512", argLength: 1, reg: w11, asm: "VCVTTPS2UDQ", commutative: false, typ: "Vec512", resultInArg0: false}, + {name: "VCVTTPS2UDQMasked128", argLength: 2, reg: wkw, asm: "VCVTTPS2UDQ", commutative: false, typ: "Vec128", resultInArg0: false}, + {name: "VCVTTPS2UDQMasked256", argLength: 2, reg: wkw, asm: "VCVTTPS2UDQ", commutative: false, typ: "Vec256", resultInArg0: false}, + {name: "VCVTTPS2UDQMasked512", argLength: 2, reg: wkw, asm: "VCVTTPS2UDQ", commutative: false, typ: "Vec512", resultInArg0: false}, + {name: "VCVTTPS2UQQ256", argLength: 1, reg: w11, asm: "VCVTTPS2UQQ", commutative: false, typ: "Vec256", resultInArg0: false}, + {name: "VCVTTPS2UQQ512", argLength: 1, reg: w11, asm: "VCVTTPS2UQQ", commutative: false, typ: "Vec512", resultInArg0: false}, + {name: "VCVTTPS2UQQMasked256", argLength: 2, reg: wkw, asm: "VCVTTPS2UQQ", commutative: false, typ: "Vec256", resultInArg0: false}, + {name: "VCVTTPS2UQQMasked512", argLength: 2, reg: wkw, asm: "VCVTTPS2UQQ", commutative: false, typ: "Vec512", resultInArg0: false}, {name: "VDIVPD128", argLength: 2, reg: v21, asm: "VDIVPD", commutative: false, typ: "Vec128", resultInArg0: false}, {name: "VDIVPD256", argLength: 2, reg: v21, asm: "VDIVPD", commutative: false, typ: "Vec256", resultInArg0: false}, {name: "VDIVPD512", argLength: 2, reg: w21, asm: "VDIVPD", commutative: false, typ: "Vec512", resultInArg0: false}, @@ -1405,16 +1437,46 @@ func simdAMD64Ops(v11, v21, v2k, vkv, v2kv, v2kk, v31, v3kv, vgpv, vgp, vfpv, vf {name: "VADDPSMasked128load", argLength: 4, reg: w2kwload, asm: "VADDPS", commutative: false, typ: "Vec128", aux: "SymOff", symEffect: "Read", resultInArg0: false}, {name: "VADDPSMasked256load", argLength: 4, reg: w2kwload, asm: "VADDPS", commutative: false, typ: "Vec256", aux: "SymOff", symEffect: "Read", resultInArg0: false}, {name: "VADDPSMasked512load", argLength: 4, reg: w2kwload, asm: "VADDPS", commutative: false, typ: "Vec512", aux: "SymOff", symEffect: "Read", resultInArg0: false}, - {name: "VCVTPS2UDQ128load", argLength: 2, reg: w11load, asm: "VCVTPS2UDQ", commutative: false, typ: "Vec128", aux: "SymOff", symEffect: "Read", resultInArg0: false}, - {name: "VCVTPS2UDQ256load", argLength: 2, reg: w11load, asm: "VCVTPS2UDQ", commutative: false, typ: "Vec256", aux: "SymOff", symEffect: "Read", resultInArg0: false}, - {name: "VCVTPS2UDQ512load", argLength: 2, reg: w11load, asm: "VCVTPS2UDQ", commutative: false, typ: "Vec512", aux: "SymOff", symEffect: "Read", resultInArg0: false}, - {name: "VCVTPS2UDQMasked128load", argLength: 3, reg: wkwload, asm: "VCVTPS2UDQ", commutative: false, typ: "Vec128", aux: "SymOff", symEffect: "Read", resultInArg0: false}, - {name: "VCVTPS2UDQMasked256load", argLength: 3, reg: wkwload, asm: "VCVTPS2UDQ", commutative: false, typ: "Vec256", aux: "SymOff", symEffect: "Read", resultInArg0: false}, - {name: "VCVTPS2UDQMasked512load", argLength: 3, reg: wkwload, asm: "VCVTPS2UDQ", commutative: false, typ: "Vec512", aux: "SymOff", symEffect: "Read", resultInArg0: false}, + {name: "VCVTTPD2DQ256load", argLength: 2, reg: w11load, asm: "VCVTTPD2DQ", commutative: false, typ: "Vec256", aux: "SymOff", symEffect: "Read", resultInArg0: false}, + {name: "VCVTTPD2DQMasked256load", argLength: 3, reg: wkwload, asm: "VCVTTPD2DQ", commutative: false, typ: "Vec256", aux: "SymOff", symEffect: "Read", resultInArg0: false}, + {name: "VCVTTPD2DQXMasked128load", argLength: 3, reg: wkwload, asm: "VCVTTPD2DQX", commutative: false, typ: "Vec128", aux: "SymOff", symEffect: "Read", resultInArg0: false}, + {name: "VCVTTPD2DQYMasked128load", argLength: 3, reg: wkwload, asm: "VCVTTPD2DQY", commutative: false, typ: "Vec128", aux: "SymOff", symEffect: "Read", resultInArg0: false}, + {name: "VCVTTPD2QQ128load", argLength: 2, reg: w11load, asm: "VCVTTPD2QQ", commutative: false, typ: "Vec128", aux: "SymOff", symEffect: "Read", resultInArg0: false}, + {name: "VCVTTPD2QQ256load", argLength: 2, reg: w11load, asm: "VCVTTPD2QQ", commutative: false, typ: "Vec256", aux: "SymOff", symEffect: "Read", resultInArg0: false}, + {name: "VCVTTPD2QQ512load", argLength: 2, reg: w11load, asm: "VCVTTPD2QQ", commutative: false, typ: "Vec512", aux: "SymOff", symEffect: "Read", resultInArg0: false}, + {name: "VCVTTPD2QQMasked128load", argLength: 3, reg: wkwload, asm: "VCVTTPD2QQ", commutative: false, typ: "Vec128", aux: "SymOff", symEffect: "Read", resultInArg0: false}, + {name: "VCVTTPD2QQMasked256load", argLength: 3, reg: wkwload, asm: "VCVTTPD2QQ", commutative: false, typ: "Vec256", aux: "SymOff", symEffect: "Read", resultInArg0: false}, + {name: "VCVTTPD2QQMasked512load", argLength: 3, reg: wkwload, asm: "VCVTTPD2QQ", commutative: false, typ: "Vec512", aux: "SymOff", symEffect: "Read", resultInArg0: false}, + {name: "VCVTTPD2UDQ256load", argLength: 2, reg: w11load, asm: "VCVTTPD2UDQ", commutative: false, typ: "Vec256", aux: "SymOff", symEffect: "Read", resultInArg0: false}, + {name: "VCVTTPD2UDQMasked256load", argLength: 3, reg: wkwload, asm: "VCVTTPD2UDQ", commutative: false, typ: "Vec256", aux: "SymOff", symEffect: "Read", resultInArg0: false}, + {name: "VCVTTPD2UDQX128load", argLength: 2, reg: w11load, asm: "VCVTTPD2UDQX", commutative: false, typ: "Vec128", aux: "SymOff", symEffect: "Read", resultInArg0: false}, + {name: "VCVTTPD2UDQXMasked128load", argLength: 3, reg: wkwload, asm: "VCVTTPD2UDQX", commutative: false, typ: "Vec128", aux: "SymOff", symEffect: "Read", resultInArg0: false}, + {name: "VCVTTPD2UDQY128load", argLength: 2, reg: w11load, asm: "VCVTTPD2UDQY", commutative: false, typ: "Vec128", aux: "SymOff", symEffect: "Read", resultInArg0: false}, + {name: "VCVTTPD2UDQYMasked128load", argLength: 3, reg: wkwload, asm: "VCVTTPD2UDQY", commutative: false, typ: "Vec128", aux: "SymOff", symEffect: "Read", resultInArg0: false}, + {name: "VCVTTPD2UQQ128load", argLength: 2, reg: w11load, asm: "VCVTTPD2UQQ", commutative: false, typ: "Vec128", aux: "SymOff", symEffect: "Read", resultInArg0: false}, + {name: "VCVTTPD2UQQ256load", argLength: 2, reg: w11load, asm: "VCVTTPD2UQQ", commutative: false, typ: "Vec256", aux: "SymOff", symEffect: "Read", resultInArg0: false}, + {name: "VCVTTPD2UQQ512load", argLength: 2, reg: w11load, asm: "VCVTTPD2UQQ", commutative: false, typ: "Vec512", aux: "SymOff", symEffect: "Read", resultInArg0: false}, + {name: "VCVTTPD2UQQMasked128load", argLength: 3, reg: wkwload, asm: "VCVTTPD2UQQ", commutative: false, typ: "Vec128", aux: "SymOff", symEffect: "Read", resultInArg0: false}, + {name: "VCVTTPD2UQQMasked256load", argLength: 3, reg: wkwload, asm: "VCVTTPD2UQQ", commutative: false, typ: "Vec256", aux: "SymOff", symEffect: "Read", resultInArg0: false}, + {name: "VCVTTPD2UQQMasked512load", argLength: 3, reg: wkwload, asm: "VCVTTPD2UQQ", commutative: false, typ: "Vec512", aux: "SymOff", symEffect: "Read", resultInArg0: false}, {name: "VCVTTPS2DQ512load", argLength: 2, reg: w11load, asm: "VCVTTPS2DQ", commutative: false, typ: "Vec512", aux: "SymOff", symEffect: "Read", resultInArg0: false}, {name: "VCVTTPS2DQMasked128load", argLength: 3, reg: wkwload, asm: "VCVTTPS2DQ", commutative: false, typ: "Vec128", aux: "SymOff", symEffect: "Read", resultInArg0: false}, {name: "VCVTTPS2DQMasked256load", argLength: 3, reg: wkwload, asm: "VCVTTPS2DQ", commutative: false, typ: "Vec256", aux: "SymOff", symEffect: "Read", resultInArg0: false}, {name: "VCVTTPS2DQMasked512load", argLength: 3, reg: wkwload, asm: "VCVTTPS2DQ", commutative: false, typ: "Vec512", aux: "SymOff", symEffect: "Read", resultInArg0: false}, + {name: "VCVTTPS2QQ256load", argLength: 2, reg: w11load, asm: "VCVTTPS2QQ", commutative: false, typ: "Vec256", aux: "SymOff", symEffect: "Read", resultInArg0: false}, + {name: "VCVTTPS2QQ512load", argLength: 2, reg: w11load, asm: "VCVTTPS2QQ", commutative: false, typ: "Vec512", aux: "SymOff", symEffect: "Read", resultInArg0: false}, + {name: "VCVTTPS2QQMasked256load", argLength: 3, reg: wkwload, asm: "VCVTTPS2QQ", commutative: false, typ: "Vec256", aux: "SymOff", symEffect: "Read", resultInArg0: false}, + {name: "VCVTTPS2QQMasked512load", argLength: 3, reg: wkwload, asm: "VCVTTPS2QQ", commutative: false, typ: "Vec512", aux: "SymOff", symEffect: "Read", resultInArg0: false}, + {name: "VCVTTPS2UDQ128load", argLength: 2, reg: w11load, asm: "VCVTTPS2UDQ", commutative: false, typ: "Vec128", aux: "SymOff", symEffect: "Read", resultInArg0: false}, + {name: "VCVTTPS2UDQ256load", argLength: 2, reg: w11load, asm: "VCVTTPS2UDQ", commutative: false, typ: "Vec256", aux: "SymOff", symEffect: "Read", resultInArg0: false}, + {name: "VCVTTPS2UDQ512load", argLength: 2, reg: w11load, asm: "VCVTTPS2UDQ", commutative: false, typ: "Vec512", aux: "SymOff", symEffect: "Read", resultInArg0: false}, + {name: "VCVTTPS2UDQMasked128load", argLength: 3, reg: wkwload, asm: "VCVTTPS2UDQ", commutative: false, typ: "Vec128", aux: "SymOff", symEffect: "Read", resultInArg0: false}, + {name: "VCVTTPS2UDQMasked256load", argLength: 3, reg: wkwload, asm: "VCVTTPS2UDQ", commutative: false, typ: "Vec256", aux: "SymOff", symEffect: "Read", resultInArg0: false}, + {name: "VCVTTPS2UDQMasked512load", argLength: 3, reg: wkwload, asm: "VCVTTPS2UDQ", commutative: false, typ: "Vec512", aux: "SymOff", symEffect: "Read", resultInArg0: false}, + {name: "VCVTTPS2UQQ256load", argLength: 2, reg: w11load, asm: "VCVTTPS2UQQ", commutative: false, typ: "Vec256", aux: "SymOff", symEffect: "Read", resultInArg0: false}, + {name: "VCVTTPS2UQQ512load", argLength: 2, reg: w11load, asm: "VCVTTPS2UQQ", commutative: false, typ: "Vec512", aux: "SymOff", symEffect: "Read", resultInArg0: false}, + {name: "VCVTTPS2UQQMasked256load", argLength: 3, reg: wkwload, asm: "VCVTTPS2UQQ", commutative: false, typ: "Vec256", aux: "SymOff", symEffect: "Read", resultInArg0: false}, + {name: "VCVTTPS2UQQMasked512load", argLength: 3, reg: wkwload, asm: "VCVTTPS2UQQ", commutative: false, typ: "Vec512", aux: "SymOff", symEffect: "Read", resultInArg0: false}, {name: "VDIVPD512load", argLength: 3, reg: w21load, asm: "VDIVPD", commutative: false, typ: "Vec512", aux: "SymOff", symEffect: "Read", resultInArg0: false}, {name: "VDIVPDMasked128load", argLength: 4, reg: w2kwload, asm: "VDIVPD", commutative: false, typ: "Vec128", aux: "SymOff", symEffect: "Read", resultInArg0: false}, {name: "VDIVPDMasked256load", argLength: 4, reg: w2kwload, asm: "VDIVPD", commutative: false, typ: "Vec256", aux: "SymOff", symEffect: "Read", resultInArg0: false}, @@ -1962,12 +2024,28 @@ func simdAMD64Ops(v11, v21, v2k, vkv, v2kv, v2kk, v31, v3kv, vgpv, vgp, vfpv, vf {name: "VBROADCASTSSMasked128Merging", argLength: 3, reg: w2kw, asm: "VBROADCASTSS", commutative: false, typ: "Vec128", resultInArg0: true}, {name: "VBROADCASTSSMasked256Merging", argLength: 3, reg: w2kw, asm: "VBROADCASTSS", commutative: false, typ: "Vec256", resultInArg0: true}, {name: "VBROADCASTSSMasked512Merging", argLength: 3, reg: w2kw, asm: "VBROADCASTSS", commutative: false, typ: "Vec512", resultInArg0: true}, - {name: "VCVTPS2UDQMasked128Merging", argLength: 3, reg: w2kw, asm: "VCVTPS2UDQ", commutative: false, typ: "Vec128", resultInArg0: true}, - {name: "VCVTPS2UDQMasked256Merging", argLength: 3, reg: w2kw, asm: "VCVTPS2UDQ", commutative: false, typ: "Vec256", resultInArg0: true}, - {name: "VCVTPS2UDQMasked512Merging", argLength: 3, reg: w2kw, asm: "VCVTPS2UDQ", commutative: false, typ: "Vec512", resultInArg0: true}, + {name: "VCVTTPD2DQMasked256Merging", argLength: 3, reg: w2kw, asm: "VCVTTPD2DQ", commutative: false, typ: "Vec256", resultInArg0: true}, + {name: "VCVTTPD2DQXMasked128Merging", argLength: 3, reg: w2kw, asm: "VCVTTPD2DQX", commutative: false, typ: "Vec128", resultInArg0: true}, + {name: "VCVTTPD2DQYMasked128Merging", argLength: 3, reg: w2kw, asm: "VCVTTPD2DQY", commutative: false, typ: "Vec128", resultInArg0: true}, + {name: "VCVTTPD2QQMasked128Merging", argLength: 3, reg: w2kw, asm: "VCVTTPD2QQ", commutative: false, typ: "Vec128", resultInArg0: true}, + {name: "VCVTTPD2QQMasked256Merging", argLength: 3, reg: w2kw, asm: "VCVTTPD2QQ", commutative: false, typ: "Vec256", resultInArg0: true}, + {name: "VCVTTPD2QQMasked512Merging", argLength: 3, reg: w2kw, asm: "VCVTTPD2QQ", commutative: false, typ: "Vec512", resultInArg0: true}, + {name: "VCVTTPD2UDQMasked256Merging", argLength: 3, reg: w2kw, asm: "VCVTTPD2UDQ", commutative: false, typ: "Vec256", resultInArg0: true}, + {name: "VCVTTPD2UDQXMasked128Merging", argLength: 3, reg: w2kw, asm: "VCVTTPD2UDQX", commutative: false, typ: "Vec128", resultInArg0: true}, + {name: "VCVTTPD2UDQYMasked128Merging", argLength: 3, reg: w2kw, asm: "VCVTTPD2UDQY", commutative: false, typ: "Vec128", resultInArg0: true}, + {name: "VCVTTPD2UQQMasked128Merging", argLength: 3, reg: w2kw, asm: "VCVTTPD2UQQ", commutative: false, typ: "Vec128", resultInArg0: true}, + {name: "VCVTTPD2UQQMasked256Merging", argLength: 3, reg: w2kw, asm: "VCVTTPD2UQQ", commutative: false, typ: "Vec256", resultInArg0: true}, + {name: "VCVTTPD2UQQMasked512Merging", argLength: 3, reg: w2kw, asm: "VCVTTPD2UQQ", commutative: false, typ: "Vec512", resultInArg0: true}, {name: "VCVTTPS2DQMasked128Merging", argLength: 3, reg: w2kw, asm: "VCVTTPS2DQ", commutative: false, typ: "Vec128", resultInArg0: true}, {name: "VCVTTPS2DQMasked256Merging", argLength: 3, reg: w2kw, asm: "VCVTTPS2DQ", commutative: false, typ: "Vec256", resultInArg0: true}, {name: "VCVTTPS2DQMasked512Merging", argLength: 3, reg: w2kw, asm: "VCVTTPS2DQ", commutative: false, typ: "Vec512", resultInArg0: true}, + {name: "VCVTTPS2QQMasked256Merging", argLength: 3, reg: w2kw, asm: "VCVTTPS2QQ", commutative: false, typ: "Vec256", resultInArg0: true}, + {name: "VCVTTPS2QQMasked512Merging", argLength: 3, reg: w2kw, asm: "VCVTTPS2QQ", commutative: false, typ: "Vec512", resultInArg0: true}, + {name: "VCVTTPS2UDQMasked128Merging", argLength: 3, reg: w2kw, asm: "VCVTTPS2UDQ", commutative: false, typ: "Vec128", resultInArg0: true}, + {name: "VCVTTPS2UDQMasked256Merging", argLength: 3, reg: w2kw, asm: "VCVTTPS2UDQ", commutative: false, typ: "Vec256", resultInArg0: true}, + {name: "VCVTTPS2UDQMasked512Merging", argLength: 3, reg: w2kw, asm: "VCVTTPS2UDQ", commutative: false, typ: "Vec512", resultInArg0: true}, + {name: "VCVTTPS2UQQMasked256Merging", argLength: 3, reg: w2kw, asm: "VCVTTPS2UQQ", commutative: false, typ: "Vec256", resultInArg0: true}, + {name: "VCVTTPS2UQQMasked512Merging", argLength: 3, reg: w2kw, asm: "VCVTTPS2UQQ", commutative: false, typ: "Vec512", resultInArg0: true}, {name: "VDIVPDMasked128Merging", argLength: 4, reg: w3kw, asm: "VDIVPD", commutative: false, typ: "Vec128", resultInArg0: true}, {name: "VDIVPDMasked256Merging", argLength: 4, reg: w3kw, asm: "VDIVPD", commutative: false, typ: "Vec256", resultInArg0: true}, {name: "VDIVPDMasked512Merging", argLength: 4, reg: w3kw, asm: "VDIVPD", commutative: false, typ: "Vec512", resultInArg0: true}, diff --git a/src/cmd/compile/internal/ssa/_gen/simdgenericOps.go b/src/cmd/compile/internal/ssa/_gen/simdgenericOps.go index 2dda588df4..d41efc81bf 100644 --- a/src/cmd/compile/internal/ssa/_gen/simdgenericOps.go +++ b/src/cmd/compile/internal/ssa/_gen/simdgenericOps.go @@ -240,9 +240,25 @@ func simdGenericOps() []opData { {name: "ConvertToInt32Float32x4", argLength: 1, commutative: false}, {name: "ConvertToInt32Float32x8", argLength: 1, commutative: false}, {name: "ConvertToInt32Float32x16", argLength: 1, commutative: false}, + {name: "ConvertToInt32Float64x2", argLength: 1, commutative: false}, + {name: "ConvertToInt32Float64x4", argLength: 1, commutative: false}, + {name: "ConvertToInt32Float64x8", argLength: 1, commutative: false}, + {name: "ConvertToInt64Float32x4", argLength: 1, commutative: false}, + {name: "ConvertToInt64Float32x8", argLength: 1, commutative: false}, + {name: "ConvertToInt64Float64x2", argLength: 1, commutative: false}, + {name: "ConvertToInt64Float64x4", argLength: 1, commutative: false}, + {name: "ConvertToInt64Float64x8", argLength: 1, commutative: false}, {name: "ConvertToUint32Float32x4", argLength: 1, commutative: false}, {name: "ConvertToUint32Float32x8", argLength: 1, commutative: false}, {name: "ConvertToUint32Float32x16", argLength: 1, commutative: false}, + {name: "ConvertToUint32Float64x2", argLength: 1, commutative: false}, + {name: "ConvertToUint32Float64x4", argLength: 1, commutative: false}, + {name: "ConvertToUint32Float64x8", argLength: 1, commutative: false}, + {name: "ConvertToUint64Float32x4", argLength: 1, commutative: false}, + {name: "ConvertToUint64Float32x8", argLength: 1, commutative: false}, + {name: "ConvertToUint64Float64x2", argLength: 1, commutative: false}, + {name: "ConvertToUint64Float64x4", argLength: 1, commutative: false}, + {name: "ConvertToUint64Float64x8", argLength: 1, commutative: false}, {name: "CopySignInt8x16", argLength: 2, commutative: false}, {name: "CopySignInt8x32", argLength: 2, commutative: false}, {name: "CopySignInt16x8", argLength: 2, commutative: false}, diff --git a/src/cmd/compile/internal/ssa/opGen.go b/src/cmd/compile/internal/ssa/opGen.go index 966d15b83c..63332003dd 100644 --- a/src/cmd/compile/internal/ssa/opGen.go +++ b/src/cmd/compile/internal/ssa/opGen.go @@ -1297,18 +1297,50 @@ const ( OpAMD64VCOMPRESSPSMasked128 OpAMD64VCOMPRESSPSMasked256 OpAMD64VCOMPRESSPSMasked512 - OpAMD64VCVTPS2UDQ128 - OpAMD64VCVTPS2UDQ256 - OpAMD64VCVTPS2UDQ512 - OpAMD64VCVTPS2UDQMasked128 - OpAMD64VCVTPS2UDQMasked256 - OpAMD64VCVTPS2UDQMasked512 + OpAMD64VCVTTPD2DQ256 + OpAMD64VCVTTPD2DQMasked256 + OpAMD64VCVTTPD2DQX128 + OpAMD64VCVTTPD2DQXMasked128 + OpAMD64VCVTTPD2DQY128 + OpAMD64VCVTTPD2DQYMasked128 + OpAMD64VCVTTPD2QQ128 + OpAMD64VCVTTPD2QQ256 + OpAMD64VCVTTPD2QQ512 + OpAMD64VCVTTPD2QQMasked128 + OpAMD64VCVTTPD2QQMasked256 + OpAMD64VCVTTPD2QQMasked512 + OpAMD64VCVTTPD2UDQ256 + OpAMD64VCVTTPD2UDQMasked256 + OpAMD64VCVTTPD2UDQX128 + OpAMD64VCVTTPD2UDQXMasked128 + OpAMD64VCVTTPD2UDQY128 + OpAMD64VCVTTPD2UDQYMasked128 + OpAMD64VCVTTPD2UQQ128 + OpAMD64VCVTTPD2UQQ256 + OpAMD64VCVTTPD2UQQ512 + OpAMD64VCVTTPD2UQQMasked128 + OpAMD64VCVTTPD2UQQMasked256 + OpAMD64VCVTTPD2UQQMasked512 OpAMD64VCVTTPS2DQ128 OpAMD64VCVTTPS2DQ256 OpAMD64VCVTTPS2DQ512 OpAMD64VCVTTPS2DQMasked128 OpAMD64VCVTTPS2DQMasked256 OpAMD64VCVTTPS2DQMasked512 + OpAMD64VCVTTPS2QQ256 + OpAMD64VCVTTPS2QQ512 + OpAMD64VCVTTPS2QQMasked256 + OpAMD64VCVTTPS2QQMasked512 + OpAMD64VCVTTPS2UDQ128 + OpAMD64VCVTTPS2UDQ256 + OpAMD64VCVTTPS2UDQ512 + OpAMD64VCVTTPS2UDQMasked128 + OpAMD64VCVTTPS2UDQMasked256 + OpAMD64VCVTTPS2UDQMasked512 + OpAMD64VCVTTPS2UQQ256 + OpAMD64VCVTTPS2UQQ512 + OpAMD64VCVTTPS2UQQMasked256 + OpAMD64VCVTTPS2UQQMasked512 OpAMD64VDIVPD128 OpAMD64VDIVPD256 OpAMD64VDIVPD512 @@ -2646,16 +2678,46 @@ const ( OpAMD64VADDPSMasked128load OpAMD64VADDPSMasked256load OpAMD64VADDPSMasked512load - OpAMD64VCVTPS2UDQ128load - OpAMD64VCVTPS2UDQ256load - OpAMD64VCVTPS2UDQ512load - OpAMD64VCVTPS2UDQMasked128load - OpAMD64VCVTPS2UDQMasked256load - OpAMD64VCVTPS2UDQMasked512load + OpAMD64VCVTTPD2DQ256load + OpAMD64VCVTTPD2DQMasked256load + OpAMD64VCVTTPD2DQXMasked128load + OpAMD64VCVTTPD2DQYMasked128load + OpAMD64VCVTTPD2QQ128load + OpAMD64VCVTTPD2QQ256load + OpAMD64VCVTTPD2QQ512load + OpAMD64VCVTTPD2QQMasked128load + OpAMD64VCVTTPD2QQMasked256load + OpAMD64VCVTTPD2QQMasked512load + OpAMD64VCVTTPD2UDQ256load + OpAMD64VCVTTPD2UDQMasked256load + OpAMD64VCVTTPD2UDQX128load + OpAMD64VCVTTPD2UDQXMasked128load + OpAMD64VCVTTPD2UDQY128load + OpAMD64VCVTTPD2UDQYMasked128load + OpAMD64VCVTTPD2UQQ128load + OpAMD64VCVTTPD2UQQ256load + OpAMD64VCVTTPD2UQQ512load + OpAMD64VCVTTPD2UQQMasked128load + OpAMD64VCVTTPD2UQQMasked256load + OpAMD64VCVTTPD2UQQMasked512load OpAMD64VCVTTPS2DQ512load OpAMD64VCVTTPS2DQMasked128load OpAMD64VCVTTPS2DQMasked256load OpAMD64VCVTTPS2DQMasked512load + OpAMD64VCVTTPS2QQ256load + OpAMD64VCVTTPS2QQ512load + OpAMD64VCVTTPS2QQMasked256load + OpAMD64VCVTTPS2QQMasked512load + OpAMD64VCVTTPS2UDQ128load + OpAMD64VCVTTPS2UDQ256load + OpAMD64VCVTTPS2UDQ512load + OpAMD64VCVTTPS2UDQMasked128load + OpAMD64VCVTTPS2UDQMasked256load + OpAMD64VCVTTPS2UDQMasked512load + OpAMD64VCVTTPS2UQQ256load + OpAMD64VCVTTPS2UQQ512load + OpAMD64VCVTTPS2UQQMasked256load + OpAMD64VCVTTPS2UQQMasked512load OpAMD64VDIVPD512load OpAMD64VDIVPDMasked128load OpAMD64VDIVPDMasked256load @@ -3203,12 +3265,28 @@ const ( OpAMD64VBROADCASTSSMasked128Merging OpAMD64VBROADCASTSSMasked256Merging OpAMD64VBROADCASTSSMasked512Merging - OpAMD64VCVTPS2UDQMasked128Merging - OpAMD64VCVTPS2UDQMasked256Merging - OpAMD64VCVTPS2UDQMasked512Merging + OpAMD64VCVTTPD2DQMasked256Merging + OpAMD64VCVTTPD2DQXMasked128Merging + OpAMD64VCVTTPD2DQYMasked128Merging + OpAMD64VCVTTPD2QQMasked128Merging + OpAMD64VCVTTPD2QQMasked256Merging + OpAMD64VCVTTPD2QQMasked512Merging + OpAMD64VCVTTPD2UDQMasked256Merging + OpAMD64VCVTTPD2UDQXMasked128Merging + OpAMD64VCVTTPD2UDQYMasked128Merging + OpAMD64VCVTTPD2UQQMasked128Merging + OpAMD64VCVTTPD2UQQMasked256Merging + OpAMD64VCVTTPD2UQQMasked512Merging OpAMD64VCVTTPS2DQMasked128Merging OpAMD64VCVTTPS2DQMasked256Merging OpAMD64VCVTTPS2DQMasked512Merging + OpAMD64VCVTTPS2QQMasked256Merging + OpAMD64VCVTTPS2QQMasked512Merging + OpAMD64VCVTTPS2UDQMasked128Merging + OpAMD64VCVTTPS2UDQMasked256Merging + OpAMD64VCVTTPS2UDQMasked512Merging + OpAMD64VCVTTPS2UQQMasked256Merging + OpAMD64VCVTTPS2UQQMasked512Merging OpAMD64VDIVPDMasked128Merging OpAMD64VDIVPDMasked256Merging OpAMD64VDIVPDMasked512Merging @@ -6178,9 +6256,25 @@ const ( OpConvertToInt32Float32x4 OpConvertToInt32Float32x8 OpConvertToInt32Float32x16 + OpConvertToInt32Float64x2 + OpConvertToInt32Float64x4 + OpConvertToInt32Float64x8 + OpConvertToInt64Float32x4 + OpConvertToInt64Float32x8 + OpConvertToInt64Float64x2 + OpConvertToInt64Float64x4 + OpConvertToInt64Float64x8 OpConvertToUint32Float32x4 OpConvertToUint32Float32x8 OpConvertToUint32Float32x16 + OpConvertToUint32Float64x2 + OpConvertToUint32Float64x4 + OpConvertToUint32Float64x8 + OpConvertToUint64Float32x4 + OpConvertToUint64Float32x8 + OpConvertToUint64Float64x2 + OpConvertToUint64Float64x4 + OpConvertToUint64Float64x8 OpCopySignInt8x16 OpCopySignInt8x32 OpCopySignInt16x8 @@ -21254,9 +21348,9 @@ var opcodeTable = [...]opInfo{ }, }, { - name: "VCVTPS2UDQ128", + name: "VCVTTPD2DQ256", argLen: 1, - asm: x86.AVCVTPS2UDQ, + asm: x86.AVCVTTPD2DQ, reg: regInfo{ inputs: []inputInfo{ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 @@ -21267,9 +21361,252 @@ var opcodeTable = [...]opInfo{ }, }, { - name: "VCVTPS2UDQ256", + name: "VCVTTPD2DQMasked256", + argLen: 2, + asm: x86.AVCVTTPD2DQ, + reg: regInfo{ + inputs: []inputInfo{ + {1, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7 + {0, 281474976645120}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VCVTTPD2DQX128", + argLen: 1, + asm: x86.AVCVTTPD2DQX, + reg: regInfo{ + inputs: []inputInfo{ + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + outputs: []outputInfo{ + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + }, + }, + { + name: "VCVTTPD2DQXMasked128", + argLen: 2, + asm: x86.AVCVTTPD2DQX, + reg: regInfo{ + inputs: []inputInfo{ + {1, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7 + {0, 281474976645120}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VCVTTPD2DQY128", + argLen: 1, + asm: x86.AVCVTTPD2DQY, + reg: regInfo{ + inputs: []inputInfo{ + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + outputs: []outputInfo{ + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + }, + }, + { + name: "VCVTTPD2DQYMasked128", + argLen: 2, + asm: x86.AVCVTTPD2DQY, + reg: regInfo{ + inputs: []inputInfo{ + {1, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7 + {0, 281474976645120}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VCVTTPD2QQ128", + argLen: 1, + asm: x86.AVCVTTPD2QQ, + reg: regInfo{ + inputs: []inputInfo{ + {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VCVTTPD2QQ256", + argLen: 1, + asm: x86.AVCVTTPD2QQ, + reg: regInfo{ + inputs: []inputInfo{ + {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VCVTTPD2QQ512", + argLen: 1, + asm: x86.AVCVTTPD2QQ, + reg: regInfo{ + inputs: []inputInfo{ + {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VCVTTPD2QQMasked128", + argLen: 2, + asm: x86.AVCVTTPD2QQ, + reg: regInfo{ + inputs: []inputInfo{ + {1, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7 + {0, 281474976645120}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VCVTTPD2QQMasked256", + argLen: 2, + asm: x86.AVCVTTPD2QQ, + reg: regInfo{ + inputs: []inputInfo{ + {1, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7 + {0, 281474976645120}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VCVTTPD2QQMasked512", + argLen: 2, + asm: x86.AVCVTTPD2QQ, + reg: regInfo{ + inputs: []inputInfo{ + {1, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7 + {0, 281474976645120}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VCVTTPD2UDQ256", + argLen: 1, + asm: x86.AVCVTTPD2UDQ, + reg: regInfo{ + inputs: []inputInfo{ + {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VCVTTPD2UDQMasked256", + argLen: 2, + asm: x86.AVCVTTPD2UDQ, + reg: regInfo{ + inputs: []inputInfo{ + {1, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7 + {0, 281474976645120}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VCVTTPD2UDQX128", + argLen: 1, + asm: x86.AVCVTTPD2UDQX, + reg: regInfo{ + inputs: []inputInfo{ + {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VCVTTPD2UDQXMasked128", + argLen: 2, + asm: x86.AVCVTTPD2UDQX, + reg: regInfo{ + inputs: []inputInfo{ + {1, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7 + {0, 281474976645120}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VCVTTPD2UDQY128", + argLen: 1, + asm: x86.AVCVTTPD2UDQY, + reg: regInfo{ + inputs: []inputInfo{ + {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VCVTTPD2UDQYMasked128", + argLen: 2, + asm: x86.AVCVTTPD2UDQY, + reg: regInfo{ + inputs: []inputInfo{ + {1, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7 + {0, 281474976645120}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VCVTTPD2UQQ128", + argLen: 1, + asm: x86.AVCVTTPD2UQQ, + reg: regInfo{ + inputs: []inputInfo{ + {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VCVTTPD2UQQ256", argLen: 1, - asm: x86.AVCVTPS2UDQ, + asm: x86.AVCVTTPD2UQQ, reg: regInfo{ inputs: []inputInfo{ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 @@ -21280,9 +21617,9 @@ var opcodeTable = [...]opInfo{ }, }, { - name: "VCVTPS2UDQ512", + name: "VCVTTPD2UQQ512", argLen: 1, - asm: x86.AVCVTPS2UDQ, + asm: x86.AVCVTTPD2UQQ, reg: regInfo{ inputs: []inputInfo{ {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 @@ -21293,9 +21630,9 @@ var opcodeTable = [...]opInfo{ }, }, { - name: "VCVTPS2UDQMasked128", + name: "VCVTTPD2UQQMasked128", argLen: 2, - asm: x86.AVCVTPS2UDQ, + asm: x86.AVCVTTPD2UQQ, reg: regInfo{ inputs: []inputInfo{ {1, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7 @@ -21307,9 +21644,9 @@ var opcodeTable = [...]opInfo{ }, }, { - name: "VCVTPS2UDQMasked256", + name: "VCVTTPD2UQQMasked256", argLen: 2, - asm: x86.AVCVTPS2UDQ, + asm: x86.AVCVTTPD2UQQ, reg: regInfo{ inputs: []inputInfo{ {1, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7 @@ -21321,9 +21658,9 @@ var opcodeTable = [...]opInfo{ }, }, { - name: "VCVTPS2UDQMasked512", + name: "VCVTTPD2UQQMasked512", argLen: 2, - asm: x86.AVCVTPS2UDQ, + asm: x86.AVCVTTPD2UQQ, reg: regInfo{ inputs: []inputInfo{ {1, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7 @@ -21415,6 +21752,195 @@ var opcodeTable = [...]opInfo{ }, }, }, + { + name: "VCVTTPS2QQ256", + argLen: 1, + asm: x86.AVCVTTPS2QQ, + reg: regInfo{ + inputs: []inputInfo{ + {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VCVTTPS2QQ512", + argLen: 1, + asm: x86.AVCVTTPS2QQ, + reg: regInfo{ + inputs: []inputInfo{ + {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VCVTTPS2QQMasked256", + argLen: 2, + asm: x86.AVCVTTPS2QQ, + reg: regInfo{ + inputs: []inputInfo{ + {1, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7 + {0, 281474976645120}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VCVTTPS2QQMasked512", + argLen: 2, + asm: x86.AVCVTTPS2QQ, + reg: regInfo{ + inputs: []inputInfo{ + {1, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7 + {0, 281474976645120}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VCVTTPS2UDQ128", + argLen: 1, + asm: x86.AVCVTTPS2UDQ, + reg: regInfo{ + inputs: []inputInfo{ + {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VCVTTPS2UDQ256", + argLen: 1, + asm: x86.AVCVTTPS2UDQ, + reg: regInfo{ + inputs: []inputInfo{ + {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VCVTTPS2UDQ512", + argLen: 1, + asm: x86.AVCVTTPS2UDQ, + reg: regInfo{ + inputs: []inputInfo{ + {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VCVTTPS2UDQMasked128", + argLen: 2, + asm: x86.AVCVTTPS2UDQ, + reg: regInfo{ + inputs: []inputInfo{ + {1, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7 + {0, 281474976645120}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VCVTTPS2UDQMasked256", + argLen: 2, + asm: x86.AVCVTTPS2UDQ, + reg: regInfo{ + inputs: []inputInfo{ + {1, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7 + {0, 281474976645120}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VCVTTPS2UDQMasked512", + argLen: 2, + asm: x86.AVCVTTPS2UDQ, + reg: regInfo{ + inputs: []inputInfo{ + {1, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7 + {0, 281474976645120}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VCVTTPS2UQQ256", + argLen: 1, + asm: x86.AVCVTTPS2UQQ, + reg: regInfo{ + inputs: []inputInfo{ + {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VCVTTPS2UQQ512", + argLen: 1, + asm: x86.AVCVTTPS2UQQ, + reg: regInfo{ + inputs: []inputInfo{ + {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VCVTTPS2UQQMasked256", + argLen: 2, + asm: x86.AVCVTTPS2UQQ, + reg: regInfo{ + inputs: []inputInfo{ + {1, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7 + {0, 281474976645120}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VCVTTPS2UQQMasked512", + argLen: 2, + asm: x86.AVCVTTPS2UQQ, + reg: regInfo{ + inputs: []inputInfo{ + {1, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7 + {0, 281474976645120}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, { name: "VDIVPD128", argLen: 2, @@ -41165,11 +41691,11 @@ var opcodeTable = [...]opInfo{ }, }, { - name: "VCVTPS2UDQ128load", + name: "VCVTTPD2DQ256load", auxType: auxSymOff, argLen: 2, symEffect: SymRead, - asm: x86.AVCVTPS2UDQ, + asm: x86.AVCVTTPD2DQ, reg: regInfo{ inputs: []inputInfo{ {0, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB @@ -41180,11 +41706,260 @@ var opcodeTable = [...]opInfo{ }, }, { - name: "VCVTPS2UDQ256load", + name: "VCVTTPD2DQMasked256load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVCVTTPD2DQ, + reg: regInfo{ + inputs: []inputInfo{ + {1, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7 + {0, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VCVTTPD2DQXMasked128load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVCVTTPD2DQX, + reg: regInfo{ + inputs: []inputInfo{ + {1, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7 + {0, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VCVTTPD2DQYMasked128load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVCVTTPD2DQY, + reg: regInfo{ + inputs: []inputInfo{ + {1, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7 + {0, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VCVTTPD2QQ128load", + auxType: auxSymOff, + argLen: 2, + symEffect: SymRead, + asm: x86.AVCVTTPD2QQ, + reg: regInfo{ + inputs: []inputInfo{ + {0, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VCVTTPD2QQ256load", + auxType: auxSymOff, + argLen: 2, + symEffect: SymRead, + asm: x86.AVCVTTPD2QQ, + reg: regInfo{ + inputs: []inputInfo{ + {0, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VCVTTPD2QQ512load", + auxType: auxSymOff, + argLen: 2, + symEffect: SymRead, + asm: x86.AVCVTTPD2QQ, + reg: regInfo{ + inputs: []inputInfo{ + {0, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VCVTTPD2QQMasked128load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVCVTTPD2QQ, + reg: regInfo{ + inputs: []inputInfo{ + {1, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7 + {0, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VCVTTPD2QQMasked256load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVCVTTPD2QQ, + reg: regInfo{ + inputs: []inputInfo{ + {1, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7 + {0, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VCVTTPD2QQMasked512load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVCVTTPD2QQ, + reg: regInfo{ + inputs: []inputInfo{ + {1, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7 + {0, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VCVTTPD2UDQ256load", + auxType: auxSymOff, + argLen: 2, + symEffect: SymRead, + asm: x86.AVCVTTPD2UDQ, + reg: regInfo{ + inputs: []inputInfo{ + {0, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VCVTTPD2UDQMasked256load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVCVTTPD2UDQ, + reg: regInfo{ + inputs: []inputInfo{ + {1, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7 + {0, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VCVTTPD2UDQX128load", + auxType: auxSymOff, + argLen: 2, + symEffect: SymRead, + asm: x86.AVCVTTPD2UDQX, + reg: regInfo{ + inputs: []inputInfo{ + {0, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VCVTTPD2UDQXMasked128load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVCVTTPD2UDQX, + reg: regInfo{ + inputs: []inputInfo{ + {1, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7 + {0, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VCVTTPD2UDQY128load", + auxType: auxSymOff, + argLen: 2, + symEffect: SymRead, + asm: x86.AVCVTTPD2UDQY, + reg: regInfo{ + inputs: []inputInfo{ + {0, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VCVTTPD2UDQYMasked128load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVCVTTPD2UDQY, + reg: regInfo{ + inputs: []inputInfo{ + {1, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7 + {0, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VCVTTPD2UQQ128load", + auxType: auxSymOff, + argLen: 2, + symEffect: SymRead, + asm: x86.AVCVTTPD2UQQ, + reg: regInfo{ + inputs: []inputInfo{ + {0, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VCVTTPD2UQQ256load", auxType: auxSymOff, argLen: 2, symEffect: SymRead, - asm: x86.AVCVTPS2UDQ, + asm: x86.AVCVTTPD2UQQ, reg: regInfo{ inputs: []inputInfo{ {0, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB @@ -41195,11 +41970,11 @@ var opcodeTable = [...]opInfo{ }, }, { - name: "VCVTPS2UDQ512load", + name: "VCVTTPD2UQQ512load", auxType: auxSymOff, argLen: 2, symEffect: SymRead, - asm: x86.AVCVTPS2UDQ, + asm: x86.AVCVTTPD2UQQ, reg: regInfo{ inputs: []inputInfo{ {0, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB @@ -41210,11 +41985,11 @@ var opcodeTable = [...]opInfo{ }, }, { - name: "VCVTPS2UDQMasked128load", + name: "VCVTTPD2UQQMasked128load", auxType: auxSymOff, argLen: 3, symEffect: SymRead, - asm: x86.AVCVTPS2UDQ, + asm: x86.AVCVTTPD2UQQ, reg: regInfo{ inputs: []inputInfo{ {1, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7 @@ -41226,11 +42001,11 @@ var opcodeTable = [...]opInfo{ }, }, { - name: "VCVTPS2UDQMasked256load", + name: "VCVTTPD2UQQMasked256load", auxType: auxSymOff, argLen: 3, symEffect: SymRead, - asm: x86.AVCVTPS2UDQ, + asm: x86.AVCVTTPD2UQQ, reg: regInfo{ inputs: []inputInfo{ {1, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7 @@ -41242,11 +42017,11 @@ var opcodeTable = [...]opInfo{ }, }, { - name: "VCVTPS2UDQMasked512load", + name: "VCVTTPD2UQQMasked512load", auxType: auxSymOff, argLen: 3, symEffect: SymRead, - asm: x86.AVCVTPS2UDQ, + asm: x86.AVCVTTPD2UQQ, reg: regInfo{ inputs: []inputInfo{ {1, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7 @@ -41320,6 +42095,223 @@ var opcodeTable = [...]opInfo{ }, }, }, + { + name: "VCVTTPS2QQ256load", + auxType: auxSymOff, + argLen: 2, + symEffect: SymRead, + asm: x86.AVCVTTPS2QQ, + reg: regInfo{ + inputs: []inputInfo{ + {0, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VCVTTPS2QQ512load", + auxType: auxSymOff, + argLen: 2, + symEffect: SymRead, + asm: x86.AVCVTTPS2QQ, + reg: regInfo{ + inputs: []inputInfo{ + {0, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VCVTTPS2QQMasked256load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVCVTTPS2QQ, + reg: regInfo{ + inputs: []inputInfo{ + {1, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7 + {0, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VCVTTPS2QQMasked512load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVCVTTPS2QQ, + reg: regInfo{ + inputs: []inputInfo{ + {1, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7 + {0, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VCVTTPS2UDQ128load", + auxType: auxSymOff, + argLen: 2, + symEffect: SymRead, + asm: x86.AVCVTTPS2UDQ, + reg: regInfo{ + inputs: []inputInfo{ + {0, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VCVTTPS2UDQ256load", + auxType: auxSymOff, + argLen: 2, + symEffect: SymRead, + asm: x86.AVCVTTPS2UDQ, + reg: regInfo{ + inputs: []inputInfo{ + {0, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VCVTTPS2UDQ512load", + auxType: auxSymOff, + argLen: 2, + symEffect: SymRead, + asm: x86.AVCVTTPS2UDQ, + reg: regInfo{ + inputs: []inputInfo{ + {0, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VCVTTPS2UDQMasked128load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVCVTTPS2UDQ, + reg: regInfo{ + inputs: []inputInfo{ + {1, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7 + {0, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VCVTTPS2UDQMasked256load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVCVTTPS2UDQ, + reg: regInfo{ + inputs: []inputInfo{ + {1, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7 + {0, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VCVTTPS2UDQMasked512load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVCVTTPS2UDQ, + reg: regInfo{ + inputs: []inputInfo{ + {1, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7 + {0, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VCVTTPS2UQQ256load", + auxType: auxSymOff, + argLen: 2, + symEffect: SymRead, + asm: x86.AVCVTTPS2UQQ, + reg: regInfo{ + inputs: []inputInfo{ + {0, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VCVTTPS2UQQ512load", + auxType: auxSymOff, + argLen: 2, + symEffect: SymRead, + asm: x86.AVCVTTPS2UQQ, + reg: regInfo{ + inputs: []inputInfo{ + {0, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VCVTTPS2UQQMasked256load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVCVTTPS2UQQ, + reg: regInfo{ + inputs: []inputInfo{ + {1, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7 + {0, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VCVTTPS2UQQMasked512load", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: x86.AVCVTTPS2UQQ, + reg: regInfo{ + inputs: []inputInfo{ + {1, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7 + {0, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + outputs: []outputInfo{ + {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, { name: "VDIVPD512load", auxType: auxSymOff, @@ -50459,10 +51451,10 @@ var opcodeTable = [...]opInfo{ }, }, { - name: "VCVTPS2UDQMasked128Merging", + name: "VCVTTPD2DQMasked256Merging", argLen: 3, resultInArg0: true, - asm: x86.AVCVTPS2UDQ, + asm: x86.AVCVTTPD2DQ, reg: regInfo{ inputs: []inputInfo{ {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7 @@ -50475,10 +51467,10 @@ var opcodeTable = [...]opInfo{ }, }, { - name: "VCVTPS2UDQMasked256Merging", + name: "VCVTTPD2DQXMasked128Merging", argLen: 3, resultInArg0: true, - asm: x86.AVCVTPS2UDQ, + asm: x86.AVCVTTPD2DQX, reg: regInfo{ inputs: []inputInfo{ {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7 @@ -50491,10 +51483,154 @@ var opcodeTable = [...]opInfo{ }, }, { - name: "VCVTPS2UDQMasked512Merging", + name: "VCVTTPD2DQYMasked128Merging", argLen: 3, resultInArg0: true, - asm: x86.AVCVTPS2UDQ, + asm: x86.AVCVTTPD2DQY, + reg: regInfo{ + inputs: []inputInfo{ + {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7 + {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, 281474976645120}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VCVTTPD2QQMasked128Merging", + argLen: 3, + resultInArg0: true, + asm: x86.AVCVTTPD2QQ, + reg: regInfo{ + inputs: []inputInfo{ + {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7 + {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, 281474976645120}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VCVTTPD2QQMasked256Merging", + argLen: 3, + resultInArg0: true, + asm: x86.AVCVTTPD2QQ, + reg: regInfo{ + inputs: []inputInfo{ + {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7 + {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, 281474976645120}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VCVTTPD2QQMasked512Merging", + argLen: 3, + resultInArg0: true, + asm: x86.AVCVTTPD2QQ, + reg: regInfo{ + inputs: []inputInfo{ + {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7 + {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, 281474976645120}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VCVTTPD2UDQMasked256Merging", + argLen: 3, + resultInArg0: true, + asm: x86.AVCVTTPD2UDQ, + reg: regInfo{ + inputs: []inputInfo{ + {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7 + {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, 281474976645120}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VCVTTPD2UDQXMasked128Merging", + argLen: 3, + resultInArg0: true, + asm: x86.AVCVTTPD2UDQX, + reg: regInfo{ + inputs: []inputInfo{ + {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7 + {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, 281474976645120}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VCVTTPD2UDQYMasked128Merging", + argLen: 3, + resultInArg0: true, + asm: x86.AVCVTTPD2UDQY, + reg: regInfo{ + inputs: []inputInfo{ + {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7 + {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, 281474976645120}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VCVTTPD2UQQMasked128Merging", + argLen: 3, + resultInArg0: true, + asm: x86.AVCVTTPD2UQQ, + reg: regInfo{ + inputs: []inputInfo{ + {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7 + {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, 281474976645120}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VCVTTPD2UQQMasked256Merging", + argLen: 3, + resultInArg0: true, + asm: x86.AVCVTTPD2UQQ, + reg: regInfo{ + inputs: []inputInfo{ + {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7 + {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, 281474976645120}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VCVTTPD2UQQMasked512Merging", + argLen: 3, + resultInArg0: true, + asm: x86.AVCVTTPD2UQQ, reg: regInfo{ inputs: []inputInfo{ {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7 @@ -50554,6 +51690,118 @@ var opcodeTable = [...]opInfo{ }, }, }, + { + name: "VCVTTPS2QQMasked256Merging", + argLen: 3, + resultInArg0: true, + asm: x86.AVCVTTPS2QQ, + reg: regInfo{ + inputs: []inputInfo{ + {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7 + {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, 281474976645120}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VCVTTPS2QQMasked512Merging", + argLen: 3, + resultInArg0: true, + asm: x86.AVCVTTPS2QQ, + reg: regInfo{ + inputs: []inputInfo{ + {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7 + {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, 281474976645120}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VCVTTPS2UDQMasked128Merging", + argLen: 3, + resultInArg0: true, + asm: x86.AVCVTTPS2UDQ, + reg: regInfo{ + inputs: []inputInfo{ + {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7 + {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, 281474976645120}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VCVTTPS2UDQMasked256Merging", + argLen: 3, + resultInArg0: true, + asm: x86.AVCVTTPS2UDQ, + reg: regInfo{ + inputs: []inputInfo{ + {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7 + {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, 281474976645120}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VCVTTPS2UDQMasked512Merging", + argLen: 3, + resultInArg0: true, + asm: x86.AVCVTTPS2UDQ, + reg: regInfo{ + inputs: []inputInfo{ + {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7 + {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, 281474976645120}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VCVTTPS2UQQMasked256Merging", + argLen: 3, + resultInArg0: true, + asm: x86.AVCVTTPS2UQQ, + reg: regInfo{ + inputs: []inputInfo{ + {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7 + {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, 281474976645120}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, + { + name: "VCVTTPS2UQQMasked512Merging", + argLen: 3, + resultInArg0: true, + asm: x86.AVCVTTPS2UQQ, + reg: regInfo{ + inputs: []inputInfo{ + {2, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7 + {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + {1, 281474976645120}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + outputs: []outputInfo{ + {0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 + }, + }, + }, { name: "VDIVPDMasked128Merging", argLen: 4, @@ -86899,6 +88147,46 @@ var opcodeTable = [...]opInfo{ argLen: 1, generic: true, }, + { + name: "ConvertToInt32Float64x2", + argLen: 1, + generic: true, + }, + { + name: "ConvertToInt32Float64x4", + argLen: 1, + generic: true, + }, + { + name: "ConvertToInt32Float64x8", + argLen: 1, + generic: true, + }, + { + name: "ConvertToInt64Float32x4", + argLen: 1, + generic: true, + }, + { + name: "ConvertToInt64Float32x8", + argLen: 1, + generic: true, + }, + { + name: "ConvertToInt64Float64x2", + argLen: 1, + generic: true, + }, + { + name: "ConvertToInt64Float64x4", + argLen: 1, + generic: true, + }, + { + name: "ConvertToInt64Float64x8", + argLen: 1, + generic: true, + }, { name: "ConvertToUint32Float32x4", argLen: 1, @@ -86914,6 +88202,46 @@ var opcodeTable = [...]opInfo{ argLen: 1, generic: true, }, + { + name: "ConvertToUint32Float64x2", + argLen: 1, + generic: true, + }, + { + name: "ConvertToUint32Float64x4", + argLen: 1, + generic: true, + }, + { + name: "ConvertToUint32Float64x8", + argLen: 1, + generic: true, + }, + { + name: "ConvertToUint64Float32x4", + argLen: 1, + generic: true, + }, + { + name: "ConvertToUint64Float32x8", + argLen: 1, + generic: true, + }, + { + name: "ConvertToUint64Float64x2", + argLen: 1, + generic: true, + }, + { + name: "ConvertToUint64Float64x4", + argLen: 1, + generic: true, + }, + { + name: "ConvertToUint64Float64x8", + argLen: 1, + generic: true, + }, { name: "CopySignInt8x16", argLen: 2, diff --git a/src/cmd/compile/internal/ssa/rewriteAMD64.go b/src/cmd/compile/internal/ssa/rewriteAMD64.go index d2618decf3..2c6907e8fd 100644 --- a/src/cmd/compile/internal/ssa/rewriteAMD64.go +++ b/src/cmd/compile/internal/ssa/rewriteAMD64.go @@ -590,18 +590,50 @@ func rewriteValueAMD64(v *Value) bool { return rewriteValueAMD64_OpAMD64VCMPPSMasked256(v) case OpAMD64VCMPPSMasked512: return rewriteValueAMD64_OpAMD64VCMPPSMasked512(v) - case OpAMD64VCVTPS2UDQ128: - return rewriteValueAMD64_OpAMD64VCVTPS2UDQ128(v) - case OpAMD64VCVTPS2UDQ256: - return rewriteValueAMD64_OpAMD64VCVTPS2UDQ256(v) - case OpAMD64VCVTPS2UDQ512: - return rewriteValueAMD64_OpAMD64VCVTPS2UDQ512(v) - case OpAMD64VCVTPS2UDQMasked128: - return rewriteValueAMD64_OpAMD64VCVTPS2UDQMasked128(v) - case OpAMD64VCVTPS2UDQMasked256: - return rewriteValueAMD64_OpAMD64VCVTPS2UDQMasked256(v) - case OpAMD64VCVTPS2UDQMasked512: - return rewriteValueAMD64_OpAMD64VCVTPS2UDQMasked512(v) + case OpAMD64VCVTTPD2DQ256: + return rewriteValueAMD64_OpAMD64VCVTTPD2DQ256(v) + case OpAMD64VCVTTPD2DQMasked256: + return rewriteValueAMD64_OpAMD64VCVTTPD2DQMasked256(v) + case OpAMD64VCVTTPD2DQXMasked128: + return rewriteValueAMD64_OpAMD64VCVTTPD2DQXMasked128(v) + case OpAMD64VCVTTPD2DQYMasked128: + return rewriteValueAMD64_OpAMD64VCVTTPD2DQYMasked128(v) + case OpAMD64VCVTTPD2QQ128: + return rewriteValueAMD64_OpAMD64VCVTTPD2QQ128(v) + case OpAMD64VCVTTPD2QQ256: + return rewriteValueAMD64_OpAMD64VCVTTPD2QQ256(v) + case OpAMD64VCVTTPD2QQ512: + return rewriteValueAMD64_OpAMD64VCVTTPD2QQ512(v) + case OpAMD64VCVTTPD2QQMasked128: + return rewriteValueAMD64_OpAMD64VCVTTPD2QQMasked128(v) + case OpAMD64VCVTTPD2QQMasked256: + return rewriteValueAMD64_OpAMD64VCVTTPD2QQMasked256(v) + case OpAMD64VCVTTPD2QQMasked512: + return rewriteValueAMD64_OpAMD64VCVTTPD2QQMasked512(v) + case OpAMD64VCVTTPD2UDQ256: + return rewriteValueAMD64_OpAMD64VCVTTPD2UDQ256(v) + case OpAMD64VCVTTPD2UDQMasked256: + return rewriteValueAMD64_OpAMD64VCVTTPD2UDQMasked256(v) + case OpAMD64VCVTTPD2UDQX128: + return rewriteValueAMD64_OpAMD64VCVTTPD2UDQX128(v) + case OpAMD64VCVTTPD2UDQXMasked128: + return rewriteValueAMD64_OpAMD64VCVTTPD2UDQXMasked128(v) + case OpAMD64VCVTTPD2UDQY128: + return rewriteValueAMD64_OpAMD64VCVTTPD2UDQY128(v) + case OpAMD64VCVTTPD2UDQYMasked128: + return rewriteValueAMD64_OpAMD64VCVTTPD2UDQYMasked128(v) + case OpAMD64VCVTTPD2UQQ128: + return rewriteValueAMD64_OpAMD64VCVTTPD2UQQ128(v) + case OpAMD64VCVTTPD2UQQ256: + return rewriteValueAMD64_OpAMD64VCVTTPD2UQQ256(v) + case OpAMD64VCVTTPD2UQQ512: + return rewriteValueAMD64_OpAMD64VCVTTPD2UQQ512(v) + case OpAMD64VCVTTPD2UQQMasked128: + return rewriteValueAMD64_OpAMD64VCVTTPD2UQQMasked128(v) + case OpAMD64VCVTTPD2UQQMasked256: + return rewriteValueAMD64_OpAMD64VCVTTPD2UQQMasked256(v) + case OpAMD64VCVTTPD2UQQMasked512: + return rewriteValueAMD64_OpAMD64VCVTTPD2UQQMasked512(v) case OpAMD64VCVTTPS2DQ512: return rewriteValueAMD64_OpAMD64VCVTTPS2DQ512(v) case OpAMD64VCVTTPS2DQMasked128: @@ -610,6 +642,34 @@ func rewriteValueAMD64(v *Value) bool { return rewriteValueAMD64_OpAMD64VCVTTPS2DQMasked256(v) case OpAMD64VCVTTPS2DQMasked512: return rewriteValueAMD64_OpAMD64VCVTTPS2DQMasked512(v) + case OpAMD64VCVTTPS2QQ256: + return rewriteValueAMD64_OpAMD64VCVTTPS2QQ256(v) + case OpAMD64VCVTTPS2QQ512: + return rewriteValueAMD64_OpAMD64VCVTTPS2QQ512(v) + case OpAMD64VCVTTPS2QQMasked256: + return rewriteValueAMD64_OpAMD64VCVTTPS2QQMasked256(v) + case OpAMD64VCVTTPS2QQMasked512: + return rewriteValueAMD64_OpAMD64VCVTTPS2QQMasked512(v) + case OpAMD64VCVTTPS2UDQ128: + return rewriteValueAMD64_OpAMD64VCVTTPS2UDQ128(v) + case OpAMD64VCVTTPS2UDQ256: + return rewriteValueAMD64_OpAMD64VCVTTPS2UDQ256(v) + case OpAMD64VCVTTPS2UDQ512: + return rewriteValueAMD64_OpAMD64VCVTTPS2UDQ512(v) + case OpAMD64VCVTTPS2UDQMasked128: + return rewriteValueAMD64_OpAMD64VCVTTPS2UDQMasked128(v) + case OpAMD64VCVTTPS2UDQMasked256: + return rewriteValueAMD64_OpAMD64VCVTTPS2UDQMasked256(v) + case OpAMD64VCVTTPS2UDQMasked512: + return rewriteValueAMD64_OpAMD64VCVTTPS2UDQMasked512(v) + case OpAMD64VCVTTPS2UQQ256: + return rewriteValueAMD64_OpAMD64VCVTTPS2UQQ256(v) + case OpAMD64VCVTTPS2UQQ512: + return rewriteValueAMD64_OpAMD64VCVTTPS2UQQ512(v) + case OpAMD64VCVTTPS2UQQMasked256: + return rewriteValueAMD64_OpAMD64VCVTTPS2UQQMasked256(v) + case OpAMD64VCVTTPS2UQQMasked512: + return rewriteValueAMD64_OpAMD64VCVTTPS2UQQMasked512(v) case OpAMD64VDIVPD512: return rewriteValueAMD64_OpAMD64VDIVPD512(v) case OpAMD64VDIVPDMasked128: @@ -2676,14 +2736,62 @@ func rewriteValueAMD64(v *Value) bool { case OpConvertToInt32Float32x8: v.Op = OpAMD64VCVTTPS2DQ256 return true + case OpConvertToInt32Float64x2: + v.Op = OpAMD64VCVTTPD2DQX128 + return true + case OpConvertToInt32Float64x4: + v.Op = OpAMD64VCVTTPD2DQY128 + return true + case OpConvertToInt32Float64x8: + v.Op = OpAMD64VCVTTPD2DQ256 + return true + case OpConvertToInt64Float32x4: + v.Op = OpAMD64VCVTTPS2QQ256 + return true + case OpConvertToInt64Float32x8: + v.Op = OpAMD64VCVTTPS2QQ512 + return true + case OpConvertToInt64Float64x2: + v.Op = OpAMD64VCVTTPD2QQ128 + return true + case OpConvertToInt64Float64x4: + v.Op = OpAMD64VCVTTPD2QQ256 + return true + case OpConvertToInt64Float64x8: + v.Op = OpAMD64VCVTTPD2QQ512 + return true case OpConvertToUint32Float32x16: - v.Op = OpAMD64VCVTPS2UDQ512 + v.Op = OpAMD64VCVTTPS2UDQ512 return true case OpConvertToUint32Float32x4: - v.Op = OpAMD64VCVTPS2UDQ128 + v.Op = OpAMD64VCVTTPS2UDQ128 return true case OpConvertToUint32Float32x8: - v.Op = OpAMD64VCVTPS2UDQ256 + v.Op = OpAMD64VCVTTPS2UDQ256 + return true + case OpConvertToUint32Float64x2: + v.Op = OpAMD64VCVTTPD2UDQX128 + return true + case OpConvertToUint32Float64x4: + v.Op = OpAMD64VCVTTPD2UDQY128 + return true + case OpConvertToUint32Float64x8: + v.Op = OpAMD64VCVTTPD2UDQ256 + return true + case OpConvertToUint64Float32x4: + v.Op = OpAMD64VCVTTPS2UQQ256 + return true + case OpConvertToUint64Float32x8: + v.Op = OpAMD64VCVTTPS2UQQ512 + return true + case OpConvertToUint64Float64x2: + v.Op = OpAMD64VCVTTPD2UQQ128 + return true + case OpConvertToUint64Float64x4: + v.Op = OpAMD64VCVTTPD2UQQ256 + return true + case OpConvertToUint64Float64x8: + v.Op = OpAMD64VCVTTPD2UQQ512 return true case OpCopySignInt16x16: v.Op = OpAMD64VPSIGNW256 @@ -28724,11 +28832,429 @@ func rewriteValueAMD64_OpAMD64VCMPPSMasked512(v *Value) bool { } return false } -func rewriteValueAMD64_OpAMD64VCVTPS2UDQ128(v *Value) bool { +func rewriteValueAMD64_OpAMD64VCVTTPD2DQ256(v *Value) bool { + v_0 := v.Args[0] + // match: (VCVTTPD2DQ256 l:(VMOVDQUload512 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VCVTTPD2DQ256load {sym} [off] ptr mem) + for { + l := v_0 + if l.Op != OpAMD64VMOVDQUload512 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VCVTTPD2DQ256load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg2(ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VCVTTPD2DQMasked256(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VCVTTPD2DQMasked256 l:(VMOVDQUload512 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VCVTTPD2DQMasked256load {sym} [off] ptr mask mem) + for { + l := v_0 + if l.Op != OpAMD64VMOVDQUload512 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_1 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VCVTTPD2DQMasked256load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VCVTTPD2DQXMasked128(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VCVTTPD2DQXMasked128 l:(VMOVDQUload128 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VCVTTPD2DQXMasked128load {sym} [off] ptr mask mem) + for { + l := v_0 + if l.Op != OpAMD64VMOVDQUload128 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_1 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VCVTTPD2DQXMasked128load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VCVTTPD2DQYMasked128(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VCVTTPD2DQYMasked128 l:(VMOVDQUload256 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VCVTTPD2DQYMasked128load {sym} [off] ptr mask mem) + for { + l := v_0 + if l.Op != OpAMD64VMOVDQUload256 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_1 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VCVTTPD2DQYMasked128load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VCVTTPD2QQ128(v *Value) bool { + v_0 := v.Args[0] + // match: (VCVTTPD2QQ128 l:(VMOVDQUload128 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VCVTTPD2QQ128load {sym} [off] ptr mem) + for { + l := v_0 + if l.Op != OpAMD64VMOVDQUload128 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VCVTTPD2QQ128load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg2(ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VCVTTPD2QQ256(v *Value) bool { + v_0 := v.Args[0] + // match: (VCVTTPD2QQ256 l:(VMOVDQUload256 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VCVTTPD2QQ256load {sym} [off] ptr mem) + for { + l := v_0 + if l.Op != OpAMD64VMOVDQUload256 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VCVTTPD2QQ256load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg2(ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VCVTTPD2QQ512(v *Value) bool { + v_0 := v.Args[0] + // match: (VCVTTPD2QQ512 l:(VMOVDQUload512 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VCVTTPD2QQ512load {sym} [off] ptr mem) + for { + l := v_0 + if l.Op != OpAMD64VMOVDQUload512 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VCVTTPD2QQ512load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg2(ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VCVTTPD2QQMasked128(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VCVTTPD2QQMasked128 l:(VMOVDQUload128 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VCVTTPD2QQMasked128load {sym} [off] ptr mask mem) + for { + l := v_0 + if l.Op != OpAMD64VMOVDQUload128 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_1 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VCVTTPD2QQMasked128load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VCVTTPD2QQMasked256(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VCVTTPD2QQMasked256 l:(VMOVDQUload256 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VCVTTPD2QQMasked256load {sym} [off] ptr mask mem) + for { + l := v_0 + if l.Op != OpAMD64VMOVDQUload256 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_1 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VCVTTPD2QQMasked256load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VCVTTPD2QQMasked512(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VCVTTPD2QQMasked512 l:(VMOVDQUload512 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VCVTTPD2QQMasked512load {sym} [off] ptr mask mem) + for { + l := v_0 + if l.Op != OpAMD64VMOVDQUload512 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_1 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VCVTTPD2QQMasked512load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VCVTTPD2UDQ256(v *Value) bool { + v_0 := v.Args[0] + // match: (VCVTTPD2UDQ256 l:(VMOVDQUload512 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VCVTTPD2UDQ256load {sym} [off] ptr mem) + for { + l := v_0 + if l.Op != OpAMD64VMOVDQUload512 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VCVTTPD2UDQ256load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg2(ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VCVTTPD2UDQMasked256(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VCVTTPD2UDQMasked256 l:(VMOVDQUload512 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VCVTTPD2UDQMasked256load {sym} [off] ptr mask mem) + for { + l := v_0 + if l.Op != OpAMD64VMOVDQUload512 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_1 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VCVTTPD2UDQMasked256load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VCVTTPD2UDQX128(v *Value) bool { + v_0 := v.Args[0] + // match: (VCVTTPD2UDQX128 l:(VMOVDQUload128 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VCVTTPD2UDQX128load {sym} [off] ptr mem) + for { + l := v_0 + if l.Op != OpAMD64VMOVDQUload128 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VCVTTPD2UDQX128load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg2(ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VCVTTPD2UDQXMasked128(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VCVTTPD2UDQXMasked128 l:(VMOVDQUload128 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VCVTTPD2UDQXMasked128load {sym} [off] ptr mask mem) + for { + l := v_0 + if l.Op != OpAMD64VMOVDQUload128 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_1 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VCVTTPD2UDQXMasked128load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VCVTTPD2UDQY128(v *Value) bool { + v_0 := v.Args[0] + // match: (VCVTTPD2UDQY128 l:(VMOVDQUload256 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VCVTTPD2UDQY128load {sym} [off] ptr mem) + for { + l := v_0 + if l.Op != OpAMD64VMOVDQUload256 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VCVTTPD2UDQY128load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg2(ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VCVTTPD2UDQYMasked128(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VCVTTPD2UDQYMasked128 l:(VMOVDQUload256 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VCVTTPD2UDQYMasked128load {sym} [off] ptr mask mem) + for { + l := v_0 + if l.Op != OpAMD64VMOVDQUload256 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_1 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VCVTTPD2UDQYMasked128load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VCVTTPD2UQQ128(v *Value) bool { v_0 := v.Args[0] - // match: (VCVTPS2UDQ128 l:(VMOVDQUload128 {sym} [off] ptr mem)) + // match: (VCVTTPD2UQQ128 l:(VMOVDQUload128 {sym} [off] ptr mem)) // cond: canMergeLoad(v, l) && clobber(l) - // result: (VCVTPS2UDQ128load {sym} [off] ptr mem) + // result: (VCVTTPD2UQQ128load {sym} [off] ptr mem) for { l := v_0 if l.Op != OpAMD64VMOVDQUload128 { @@ -28741,7 +29267,7 @@ func rewriteValueAMD64_OpAMD64VCVTPS2UDQ128(v *Value) bool { if !(canMergeLoad(v, l) && clobber(l)) { break } - v.reset(OpAMD64VCVTPS2UDQ128load) + v.reset(OpAMD64VCVTTPD2UQQ128load) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg2(ptr, mem) @@ -28749,11 +29275,11 @@ func rewriteValueAMD64_OpAMD64VCVTPS2UDQ128(v *Value) bool { } return false } -func rewriteValueAMD64_OpAMD64VCVTPS2UDQ256(v *Value) bool { +func rewriteValueAMD64_OpAMD64VCVTTPD2UQQ256(v *Value) bool { v_0 := v.Args[0] - // match: (VCVTPS2UDQ256 l:(VMOVDQUload256 {sym} [off] ptr mem)) + // match: (VCVTTPD2UQQ256 l:(VMOVDQUload256 {sym} [off] ptr mem)) // cond: canMergeLoad(v, l) && clobber(l) - // result: (VCVTPS2UDQ256load {sym} [off] ptr mem) + // result: (VCVTTPD2UQQ256load {sym} [off] ptr mem) for { l := v_0 if l.Op != OpAMD64VMOVDQUload256 { @@ -28766,7 +29292,7 @@ func rewriteValueAMD64_OpAMD64VCVTPS2UDQ256(v *Value) bool { if !(canMergeLoad(v, l) && clobber(l)) { break } - v.reset(OpAMD64VCVTPS2UDQ256load) + v.reset(OpAMD64VCVTTPD2UQQ256load) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg2(ptr, mem) @@ -28774,11 +29300,11 @@ func rewriteValueAMD64_OpAMD64VCVTPS2UDQ256(v *Value) bool { } return false } -func rewriteValueAMD64_OpAMD64VCVTPS2UDQ512(v *Value) bool { +func rewriteValueAMD64_OpAMD64VCVTTPD2UQQ512(v *Value) bool { v_0 := v.Args[0] - // match: (VCVTPS2UDQ512 l:(VMOVDQUload512 {sym} [off] ptr mem)) + // match: (VCVTTPD2UQQ512 l:(VMOVDQUload512 {sym} [off] ptr mem)) // cond: canMergeLoad(v, l) && clobber(l) - // result: (VCVTPS2UDQ512load {sym} [off] ptr mem) + // result: (VCVTTPD2UQQ512load {sym} [off] ptr mem) for { l := v_0 if l.Op != OpAMD64VMOVDQUload512 { @@ -28791,7 +29317,7 @@ func rewriteValueAMD64_OpAMD64VCVTPS2UDQ512(v *Value) bool { if !(canMergeLoad(v, l) && clobber(l)) { break } - v.reset(OpAMD64VCVTPS2UDQ512load) + v.reset(OpAMD64VCVTTPD2UQQ512load) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg2(ptr, mem) @@ -28799,12 +29325,12 @@ func rewriteValueAMD64_OpAMD64VCVTPS2UDQ512(v *Value) bool { } return false } -func rewriteValueAMD64_OpAMD64VCVTPS2UDQMasked128(v *Value) bool { +func rewriteValueAMD64_OpAMD64VCVTTPD2UQQMasked128(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] - // match: (VCVTPS2UDQMasked128 l:(VMOVDQUload128 {sym} [off] ptr mem) mask) + // match: (VCVTTPD2UQQMasked128 l:(VMOVDQUload128 {sym} [off] ptr mem) mask) // cond: canMergeLoad(v, l) && clobber(l) - // result: (VCVTPS2UDQMasked128load {sym} [off] ptr mask mem) + // result: (VCVTTPD2UQQMasked128load {sym} [off] ptr mask mem) for { l := v_0 if l.Op != OpAMD64VMOVDQUload128 { @@ -28818,7 +29344,7 @@ func rewriteValueAMD64_OpAMD64VCVTPS2UDQMasked128(v *Value) bool { if !(canMergeLoad(v, l) && clobber(l)) { break } - v.reset(OpAMD64VCVTPS2UDQMasked128load) + v.reset(OpAMD64VCVTTPD2UQQMasked128load) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, mask, mem) @@ -28826,12 +29352,12 @@ func rewriteValueAMD64_OpAMD64VCVTPS2UDQMasked128(v *Value) bool { } return false } -func rewriteValueAMD64_OpAMD64VCVTPS2UDQMasked256(v *Value) bool { +func rewriteValueAMD64_OpAMD64VCVTTPD2UQQMasked256(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] - // match: (VCVTPS2UDQMasked256 l:(VMOVDQUload256 {sym} [off] ptr mem) mask) + // match: (VCVTTPD2UQQMasked256 l:(VMOVDQUload256 {sym} [off] ptr mem) mask) // cond: canMergeLoad(v, l) && clobber(l) - // result: (VCVTPS2UDQMasked256load {sym} [off] ptr mask mem) + // result: (VCVTTPD2UQQMasked256load {sym} [off] ptr mask mem) for { l := v_0 if l.Op != OpAMD64VMOVDQUload256 { @@ -28845,7 +29371,7 @@ func rewriteValueAMD64_OpAMD64VCVTPS2UDQMasked256(v *Value) bool { if !(canMergeLoad(v, l) && clobber(l)) { break } - v.reset(OpAMD64VCVTPS2UDQMasked256load) + v.reset(OpAMD64VCVTTPD2UQQMasked256load) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, mask, mem) @@ -28853,12 +29379,12 @@ func rewriteValueAMD64_OpAMD64VCVTPS2UDQMasked256(v *Value) bool { } return false } -func rewriteValueAMD64_OpAMD64VCVTPS2UDQMasked512(v *Value) bool { +func rewriteValueAMD64_OpAMD64VCVTTPD2UQQMasked512(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] - // match: (VCVTPS2UDQMasked512 l:(VMOVDQUload512 {sym} [off] ptr mem) mask) + // match: (VCVTTPD2UQQMasked512 l:(VMOVDQUload512 {sym} [off] ptr mem) mask) // cond: canMergeLoad(v, l) && clobber(l) - // result: (VCVTPS2UDQMasked512load {sym} [off] ptr mask mem) + // result: (VCVTTPD2UQQMasked512load {sym} [off] ptr mask mem) for { l := v_0 if l.Op != OpAMD64VMOVDQUload512 { @@ -28872,7 +29398,7 @@ func rewriteValueAMD64_OpAMD64VCVTPS2UDQMasked512(v *Value) bool { if !(canMergeLoad(v, l) && clobber(l)) { break } - v.reset(OpAMD64VCVTPS2UDQMasked512load) + v.reset(OpAMD64VCVTTPD2UQQMasked512load) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, mask, mem) @@ -28986,6 +29512,370 @@ func rewriteValueAMD64_OpAMD64VCVTTPS2DQMasked512(v *Value) bool { } return false } +func rewriteValueAMD64_OpAMD64VCVTTPS2QQ256(v *Value) bool { + v_0 := v.Args[0] + // match: (VCVTTPS2QQ256 l:(VMOVDQUload128 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VCVTTPS2QQ256load {sym} [off] ptr mem) + for { + l := v_0 + if l.Op != OpAMD64VMOVDQUload128 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VCVTTPS2QQ256load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg2(ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VCVTTPS2QQ512(v *Value) bool { + v_0 := v.Args[0] + // match: (VCVTTPS2QQ512 l:(VMOVDQUload256 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VCVTTPS2QQ512load {sym} [off] ptr mem) + for { + l := v_0 + if l.Op != OpAMD64VMOVDQUload256 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VCVTTPS2QQ512load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg2(ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VCVTTPS2QQMasked256(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VCVTTPS2QQMasked256 l:(VMOVDQUload128 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VCVTTPS2QQMasked256load {sym} [off] ptr mask mem) + for { + l := v_0 + if l.Op != OpAMD64VMOVDQUload128 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_1 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VCVTTPS2QQMasked256load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VCVTTPS2QQMasked512(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VCVTTPS2QQMasked512 l:(VMOVDQUload256 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VCVTTPS2QQMasked512load {sym} [off] ptr mask mem) + for { + l := v_0 + if l.Op != OpAMD64VMOVDQUload256 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_1 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VCVTTPS2QQMasked512load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VCVTTPS2UDQ128(v *Value) bool { + v_0 := v.Args[0] + // match: (VCVTTPS2UDQ128 l:(VMOVDQUload128 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VCVTTPS2UDQ128load {sym} [off] ptr mem) + for { + l := v_0 + if l.Op != OpAMD64VMOVDQUload128 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VCVTTPS2UDQ128load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg2(ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VCVTTPS2UDQ256(v *Value) bool { + v_0 := v.Args[0] + // match: (VCVTTPS2UDQ256 l:(VMOVDQUload256 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VCVTTPS2UDQ256load {sym} [off] ptr mem) + for { + l := v_0 + if l.Op != OpAMD64VMOVDQUload256 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VCVTTPS2UDQ256load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg2(ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VCVTTPS2UDQ512(v *Value) bool { + v_0 := v.Args[0] + // match: (VCVTTPS2UDQ512 l:(VMOVDQUload512 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VCVTTPS2UDQ512load {sym} [off] ptr mem) + for { + l := v_0 + if l.Op != OpAMD64VMOVDQUload512 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VCVTTPS2UDQ512load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg2(ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VCVTTPS2UDQMasked128(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VCVTTPS2UDQMasked128 l:(VMOVDQUload128 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VCVTTPS2UDQMasked128load {sym} [off] ptr mask mem) + for { + l := v_0 + if l.Op != OpAMD64VMOVDQUload128 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_1 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VCVTTPS2UDQMasked128load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VCVTTPS2UDQMasked256(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VCVTTPS2UDQMasked256 l:(VMOVDQUload256 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VCVTTPS2UDQMasked256load {sym} [off] ptr mask mem) + for { + l := v_0 + if l.Op != OpAMD64VMOVDQUload256 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_1 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VCVTTPS2UDQMasked256load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VCVTTPS2UDQMasked512(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VCVTTPS2UDQMasked512 l:(VMOVDQUload512 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VCVTTPS2UDQMasked512load {sym} [off] ptr mask mem) + for { + l := v_0 + if l.Op != OpAMD64VMOVDQUload512 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_1 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VCVTTPS2UDQMasked512load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VCVTTPS2UQQ256(v *Value) bool { + v_0 := v.Args[0] + // match: (VCVTTPS2UQQ256 l:(VMOVDQUload128 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VCVTTPS2UQQ256load {sym} [off] ptr mem) + for { + l := v_0 + if l.Op != OpAMD64VMOVDQUload128 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VCVTTPS2UQQ256load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg2(ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VCVTTPS2UQQ512(v *Value) bool { + v_0 := v.Args[0] + // match: (VCVTTPS2UQQ512 l:(VMOVDQUload256 {sym} [off] ptr mem)) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VCVTTPS2UQQ512load {sym} [off] ptr mem) + for { + l := v_0 + if l.Op != OpAMD64VMOVDQUload256 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VCVTTPS2UQQ512load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg2(ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VCVTTPS2UQQMasked256(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VCVTTPS2UQQMasked256 l:(VMOVDQUload128 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VCVTTPS2UQQMasked256load {sym} [off] ptr mask mem) + for { + l := v_0 + if l.Op != OpAMD64VMOVDQUload128 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_1 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VCVTTPS2UQQMasked256load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(ptr, mask, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VCVTTPS2UQQMasked512(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (VCVTTPS2UQQMasked512 l:(VMOVDQUload256 {sym} [off] ptr mem) mask) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (VCVTTPS2UQQMasked512load {sym} [off] ptr mask mem) + for { + l := v_0 + if l.Op != OpAMD64VMOVDQUload256 { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + mask := v_1 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64VCVTTPS2UQQMasked512load) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(ptr, mask, mem) + return true + } + return false +} func rewriteValueAMD64_OpAMD64VDIVPD512(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] @@ -32939,15 +33829,15 @@ func rewriteValueAMD64_OpAMD64VMOVDQU32Masked128(v *Value) bool { v.AddArg2(x, mask) return true } - // match: (VMOVDQU32Masked128 (VCVTPS2UDQ128 x) mask) - // result: (VCVTPS2UDQMasked128 x mask) + // match: (VMOVDQU32Masked128 (VCVTTPS2UDQ128 x) mask) + // result: (VCVTTPS2UDQMasked128 x mask) for { - if v_0.Op != OpAMD64VCVTPS2UDQ128 { + if v_0.Op != OpAMD64VCVTTPS2UDQ128 { break } x := v_0.Args[0] mask := v_1 - v.reset(OpAMD64VCVTPS2UDQMasked128) + v.reset(OpAMD64VCVTTPS2UDQMasked128) v.AddArg2(x, mask) return true } @@ -33690,15 +34580,39 @@ func rewriteValueAMD64_OpAMD64VMOVDQU32Masked256(v *Value) bool { v.AddArg2(x, mask) return true } - // match: (VMOVDQU32Masked256 (VCVTPS2UDQ256 x) mask) - // result: (VCVTPS2UDQMasked256 x mask) + // match: (VMOVDQU32Masked256 (VCVTTPS2QQ256 x) mask) + // result: (VCVTTPS2QQMasked256 x mask) + for { + if v_0.Op != OpAMD64VCVTTPS2QQ256 { + break + } + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VCVTTPS2QQMasked256) + v.AddArg2(x, mask) + return true + } + // match: (VMOVDQU32Masked256 (VCVTTPS2UDQ256 x) mask) + // result: (VCVTTPS2UDQMasked256 x mask) for { - if v_0.Op != OpAMD64VCVTPS2UDQ256 { + if v_0.Op != OpAMD64VCVTTPS2UDQ256 { break } x := v_0.Args[0] mask := v_1 - v.reset(OpAMD64VCVTPS2UDQMasked256) + v.reset(OpAMD64VCVTTPS2UDQMasked256) + v.AddArg2(x, mask) + return true + } + // match: (VMOVDQU32Masked256 (VCVTTPS2UQQ256 x) mask) + // result: (VCVTTPS2UQQMasked256 x mask) + for { + if v_0.Op != OpAMD64VCVTTPS2UQQ256 { + break + } + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VCVTTPS2UQQMasked256) v.AddArg2(x, mask) return true } @@ -34529,15 +35443,39 @@ func rewriteValueAMD64_OpAMD64VMOVDQU32Masked512(v *Value) bool { v.AddArg2(x, mask) return true } - // match: (VMOVDQU32Masked512 (VCVTPS2UDQ512 x) mask) - // result: (VCVTPS2UDQMasked512 x mask) + // match: (VMOVDQU32Masked512 (VCVTTPS2QQ512 x) mask) + // result: (VCVTTPS2QQMasked512 x mask) + for { + if v_0.Op != OpAMD64VCVTTPS2QQ512 { + break + } + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VCVTTPS2QQMasked512) + v.AddArg2(x, mask) + return true + } + // match: (VMOVDQU32Masked512 (VCVTTPS2UDQ512 x) mask) + // result: (VCVTTPS2UDQMasked512 x mask) + for { + if v_0.Op != OpAMD64VCVTTPS2UDQ512 { + break + } + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VCVTTPS2UDQMasked512) + v.AddArg2(x, mask) + return true + } + // match: (VMOVDQU32Masked512 (VCVTTPS2UQQ512 x) mask) + // result: (VCVTTPS2UQQMasked512 x mask) for { - if v_0.Op != OpAMD64VCVTPS2UDQ512 { + if v_0.Op != OpAMD64VCVTTPS2UQQ512 { break } x := v_0.Args[0] mask := v_1 - v.reset(OpAMD64VCVTPS2UDQMasked512) + v.reset(OpAMD64VCVTTPS2UQQMasked512) v.AddArg2(x, mask) return true } @@ -35296,6 +36234,78 @@ func rewriteValueAMD64_OpAMD64VMOVDQU64Masked128(v *Value) bool { v.AddArg4(x, y, z, mask) return true } + // match: (VMOVDQU64Masked128 (VCVTTPD2DQX128 x) mask) + // result: (VCVTTPD2DQXMasked128 x mask) + for { + if v_0.Op != OpAMD64VCVTTPD2DQX128 { + break + } + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VCVTTPD2DQXMasked128) + v.AddArg2(x, mask) + return true + } + // match: (VMOVDQU64Masked128 (VCVTTPD2DQY128 x) mask) + // result: (VCVTTPD2DQYMasked128 x mask) + for { + if v_0.Op != OpAMD64VCVTTPD2DQY128 { + break + } + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VCVTTPD2DQYMasked128) + v.AddArg2(x, mask) + return true + } + // match: (VMOVDQU64Masked128 (VCVTTPD2QQ128 x) mask) + // result: (VCVTTPD2QQMasked128 x mask) + for { + if v_0.Op != OpAMD64VCVTTPD2QQ128 { + break + } + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VCVTTPD2QQMasked128) + v.AddArg2(x, mask) + return true + } + // match: (VMOVDQU64Masked128 (VCVTTPD2UDQX128 x) mask) + // result: (VCVTTPD2UDQXMasked128 x mask) + for { + if v_0.Op != OpAMD64VCVTTPD2UDQX128 { + break + } + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VCVTTPD2UDQXMasked128) + v.AddArg2(x, mask) + return true + } + // match: (VMOVDQU64Masked128 (VCVTTPD2UDQY128 x) mask) + // result: (VCVTTPD2UDQYMasked128 x mask) + for { + if v_0.Op != OpAMD64VCVTTPD2UDQY128 { + break + } + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VCVTTPD2UDQYMasked128) + v.AddArg2(x, mask) + return true + } + // match: (VMOVDQU64Masked128 (VCVTTPD2UQQ128 x) mask) + // result: (VCVTTPD2UQQMasked128 x mask) + for { + if v_0.Op != OpAMD64VCVTTPD2UQQ128 { + break + } + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VCVTTPD2UQQMasked128) + v.AddArg2(x, mask) + return true + } // match: (VMOVDQU64Masked128 (VDIVPD128 x y) mask) // result: (VDIVPDMasked128 x y mask) for { @@ -35991,6 +37001,54 @@ func rewriteValueAMD64_OpAMD64VMOVDQU64Masked256(v *Value) bool { v.AddArg4(x, y, z, mask) return true } + // match: (VMOVDQU64Masked256 (VCVTTPD2DQ256 x) mask) + // result: (VCVTTPD2DQMasked256 x mask) + for { + if v_0.Op != OpAMD64VCVTTPD2DQ256 { + break + } + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VCVTTPD2DQMasked256) + v.AddArg2(x, mask) + return true + } + // match: (VMOVDQU64Masked256 (VCVTTPD2QQ256 x) mask) + // result: (VCVTTPD2QQMasked256 x mask) + for { + if v_0.Op != OpAMD64VCVTTPD2QQ256 { + break + } + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VCVTTPD2QQMasked256) + v.AddArg2(x, mask) + return true + } + // match: (VMOVDQU64Masked256 (VCVTTPD2UDQ256 x) mask) + // result: (VCVTTPD2UDQMasked256 x mask) + for { + if v_0.Op != OpAMD64VCVTTPD2UDQ256 { + break + } + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VCVTTPD2UDQMasked256) + v.AddArg2(x, mask) + return true + } + // match: (VMOVDQU64Masked256 (VCVTTPD2UQQ256 x) mask) + // result: (VCVTTPD2UQQMasked256 x mask) + for { + if v_0.Op != OpAMD64VCVTTPD2UQQ256 { + break + } + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VCVTTPD2UQQMasked256) + v.AddArg2(x, mask) + return true + } // match: (VMOVDQU64Masked256 (VDIVPD256 x y) mask) // result: (VDIVPDMasked256 x y mask) for { @@ -36774,6 +37832,30 @@ func rewriteValueAMD64_OpAMD64VMOVDQU64Masked512(v *Value) bool { v.AddArg4(x, y, z, mask) return true } + // match: (VMOVDQU64Masked512 (VCVTTPD2QQ512 x) mask) + // result: (VCVTTPD2QQMasked512 x mask) + for { + if v_0.Op != OpAMD64VCVTTPD2QQ512 { + break + } + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VCVTTPD2QQMasked512) + v.AddArg2(x, mask) + return true + } + // match: (VMOVDQU64Masked512 (VCVTTPD2UQQ512 x) mask) + // result: (VCVTTPD2UQQMasked512 x mask) + for { + if v_0.Op != OpAMD64VCVTTPD2UQQ512 { + break + } + x := v_0.Args[0] + mask := v_1 + v.reset(OpAMD64VCVTTPD2UQQMasked512) + v.AddArg2(x, mask) + return true + } // match: (VMOVDQU64Masked512 (VDIVPD512 x y) mask) // result: (VDIVPDMasked512 x y mask) for { @@ -40989,29 +42071,29 @@ func rewriteValueAMD64_OpAMD64VPBLENDMDMasked512(v *Value) bool { v.AddArg4(dst, x, y, mask) return true } - // match: (VPBLENDMDMasked512 dst (VCVTPS2UDQ512 x) mask) - // result: (VCVTPS2UDQMasked512Merging dst x mask) + // match: (VPBLENDMDMasked512 dst (VCVTTPS2DQ512 x) mask) + // result: (VCVTTPS2DQMasked512Merging dst x mask) for { dst := v_0 - if v_1.Op != OpAMD64VCVTPS2UDQ512 { + if v_1.Op != OpAMD64VCVTTPS2DQ512 { break } x := v_1.Args[0] mask := v_2 - v.reset(OpAMD64VCVTPS2UDQMasked512Merging) + v.reset(OpAMD64VCVTTPS2DQMasked512Merging) v.AddArg3(dst, x, mask) return true } - // match: (VPBLENDMDMasked512 dst (VCVTTPS2DQ512 x) mask) - // result: (VCVTTPS2DQMasked512Merging dst x mask) + // match: (VPBLENDMDMasked512 dst (VCVTTPS2UDQ512 x) mask) + // result: (VCVTTPS2UDQMasked512Merging dst x mask) for { dst := v_0 - if v_1.Op != OpAMD64VCVTTPS2DQ512 { + if v_1.Op != OpAMD64VCVTTPS2UDQ512 { break } x := v_1.Args[0] mask := v_2 - v.reset(OpAMD64VCVTTPS2DQMasked512Merging) + v.reset(OpAMD64VCVTTPS2UDQMasked512Merging) v.AddArg3(dst, x, mask) return true } @@ -41660,6 +42742,58 @@ func rewriteValueAMD64_OpAMD64VPBLENDMQMasked512(v *Value) bool { v.AddArg4(dst, x, y, mask) return true } + // match: (VPBLENDMQMasked512 dst (VCVTTPD2DQ256 x) mask) + // result: (VCVTTPD2DQMasked256Merging dst x mask) + for { + dst := v_0 + if v_1.Op != OpAMD64VCVTTPD2DQ256 { + break + } + x := v_1.Args[0] + mask := v_2 + v.reset(OpAMD64VCVTTPD2DQMasked256Merging) + v.AddArg3(dst, x, mask) + return true + } + // match: (VPBLENDMQMasked512 dst (VCVTTPD2QQ512 x) mask) + // result: (VCVTTPD2QQMasked512Merging dst x mask) + for { + dst := v_0 + if v_1.Op != OpAMD64VCVTTPD2QQ512 { + break + } + x := v_1.Args[0] + mask := v_2 + v.reset(OpAMD64VCVTTPD2QQMasked512Merging) + v.AddArg3(dst, x, mask) + return true + } + // match: (VPBLENDMQMasked512 dst (VCVTTPD2UDQ256 x) mask) + // result: (VCVTTPD2UDQMasked256Merging dst x mask) + for { + dst := v_0 + if v_1.Op != OpAMD64VCVTTPD2UDQ256 { + break + } + x := v_1.Args[0] + mask := v_2 + v.reset(OpAMD64VCVTTPD2UDQMasked256Merging) + v.AddArg3(dst, x, mask) + return true + } + // match: (VPBLENDMQMasked512 dst (VCVTTPD2UQQ512 x) mask) + // result: (VCVTTPD2UQQMasked512Merging dst x mask) + for { + dst := v_0 + if v_1.Op != OpAMD64VCVTTPD2UQQ512 { + break + } + x := v_1.Args[0] + mask := v_2 + v.reset(OpAMD64VCVTTPD2UQQMasked512Merging) + v.AddArg3(dst, x, mask) + return true + } // match: (VPBLENDMQMasked512 dst (VDIVPD512 x y) mask) // result: (VDIVPDMasked512Merging dst x y mask) for { @@ -42852,12 +43986,12 @@ func rewriteValueAMD64_OpAMD64VPBLENDVB128(v *Value) bool { v.AddArg3(dst, x, v0) return true } - // match: (VPBLENDVB128 dst (VCVTPS2UDQ128 x) mask) + // match: (VPBLENDVB128 dst (VCVTTPD2DQX128 x) mask) // cond: v.Block.CPUfeatures.hasFeature(CPUavx512) - // result: (VCVTPS2UDQMasked128Merging dst x (VPMOVVec32x4ToM mask)) + // result: (VCVTTPD2DQXMasked128Merging dst x (VPMOVVec64x2ToM mask)) for { dst := v_0 - if v_1.Op != OpAMD64VCVTPS2UDQ128 { + if v_1.Op != OpAMD64VCVTTPD2DQX128 { break } x := v_1.Args[0] @@ -42865,8 +43999,65 @@ func rewriteValueAMD64_OpAMD64VPBLENDVB128(v *Value) bool { if !(v.Block.CPUfeatures.hasFeature(CPUavx512)) { break } - v.reset(OpAMD64VCVTPS2UDQMasked128Merging) - v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x4ToM, types.TypeMask) + v.reset(OpAMD64VCVTTPD2DQXMasked128Merging) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x2ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(dst, x, v0) + return true + } + // match: (VPBLENDVB128 dst (VCVTTPD2QQ128 x) mask) + // cond: v.Block.CPUfeatures.hasFeature(CPUavx512) + // result: (VCVTTPD2QQMasked128Merging dst x (VPMOVVec64x2ToM mask)) + for { + dst := v_0 + if v_1.Op != OpAMD64VCVTTPD2QQ128 { + break + } + x := v_1.Args[0] + mask := v_2 + if !(v.Block.CPUfeatures.hasFeature(CPUavx512)) { + break + } + v.reset(OpAMD64VCVTTPD2QQMasked128Merging) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x2ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(dst, x, v0) + return true + } + // match: (VPBLENDVB128 dst (VCVTTPD2UDQX128 x) mask) + // cond: v.Block.CPUfeatures.hasFeature(CPUavx512) + // result: (VCVTTPD2UDQXMasked128Merging dst x (VPMOVVec64x2ToM mask)) + for { + dst := v_0 + if v_1.Op != OpAMD64VCVTTPD2UDQX128 { + break + } + x := v_1.Args[0] + mask := v_2 + if !(v.Block.CPUfeatures.hasFeature(CPUavx512)) { + break + } + v.reset(OpAMD64VCVTTPD2UDQXMasked128Merging) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x2ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(dst, x, v0) + return true + } + // match: (VPBLENDVB128 dst (VCVTTPD2UQQ128 x) mask) + // cond: v.Block.CPUfeatures.hasFeature(CPUavx512) + // result: (VCVTTPD2UQQMasked128Merging dst x (VPMOVVec64x2ToM mask)) + for { + dst := v_0 + if v_1.Op != OpAMD64VCVTTPD2UQQ128 { + break + } + x := v_1.Args[0] + mask := v_2 + if !(v.Block.CPUfeatures.hasFeature(CPUavx512)) { + break + } + v.reset(OpAMD64VCVTTPD2UQQMasked128Merging) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x2ToM, types.TypeMask) v0.AddArg(mask) v.AddArg3(dst, x, v0) return true @@ -42890,6 +44081,63 @@ func rewriteValueAMD64_OpAMD64VPBLENDVB128(v *Value) bool { v.AddArg3(dst, x, v0) return true } + // match: (VPBLENDVB128 dst (VCVTTPS2QQ256 x) mask) + // cond: v.Block.CPUfeatures.hasFeature(CPUavx512) + // result: (VCVTTPS2QQMasked256Merging dst x (VPMOVVec32x4ToM mask)) + for { + dst := v_0 + if v_1.Op != OpAMD64VCVTTPS2QQ256 { + break + } + x := v_1.Args[0] + mask := v_2 + if !(v.Block.CPUfeatures.hasFeature(CPUavx512)) { + break + } + v.reset(OpAMD64VCVTTPS2QQMasked256Merging) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x4ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(dst, x, v0) + return true + } + // match: (VPBLENDVB128 dst (VCVTTPS2UDQ128 x) mask) + // cond: v.Block.CPUfeatures.hasFeature(CPUavx512) + // result: (VCVTTPS2UDQMasked128Merging dst x (VPMOVVec32x4ToM mask)) + for { + dst := v_0 + if v_1.Op != OpAMD64VCVTTPS2UDQ128 { + break + } + x := v_1.Args[0] + mask := v_2 + if !(v.Block.CPUfeatures.hasFeature(CPUavx512)) { + break + } + v.reset(OpAMD64VCVTTPS2UDQMasked128Merging) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x4ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(dst, x, v0) + return true + } + // match: (VPBLENDVB128 dst (VCVTTPS2UQQ256 x) mask) + // cond: v.Block.CPUfeatures.hasFeature(CPUavx512) + // result: (VCVTTPS2UQQMasked256Merging dst x (VPMOVVec32x4ToM mask)) + for { + dst := v_0 + if v_1.Op != OpAMD64VCVTTPS2UQQ256 { + break + } + x := v_1.Args[0] + mask := v_2 + if !(v.Block.CPUfeatures.hasFeature(CPUavx512)) { + break + } + v.reset(OpAMD64VCVTTPS2UQQMasked256Merging) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x4ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(dst, x, v0) + return true + } // match: (VPBLENDVB128 dst (VDIVPD128 x y) mask) // cond: v.Block.CPUfeatures.hasFeature(CPUavx512) // result: (VDIVPDMasked128Merging dst x y (VPMOVVec64x2ToM mask)) @@ -46197,12 +47445,12 @@ func rewriteValueAMD64_OpAMD64VPBLENDVB256(v *Value) bool { v.AddArg4(dst, x, y, v0) return true } - // match: (VPBLENDVB256 dst (VCVTPS2UDQ256 x) mask) + // match: (VPBLENDVB256 dst (VCVTTPD2DQY128 x) mask) // cond: v.Block.CPUfeatures.hasFeature(CPUavx512) - // result: (VCVTPS2UDQMasked256Merging dst x (VPMOVVec32x8ToM mask)) + // result: (VCVTTPD2DQYMasked128Merging dst x (VPMOVVec64x4ToM mask)) for { dst := v_0 - if v_1.Op != OpAMD64VCVTPS2UDQ256 { + if v_1.Op != OpAMD64VCVTTPD2DQY128 { break } x := v_1.Args[0] @@ -46210,8 +47458,65 @@ func rewriteValueAMD64_OpAMD64VPBLENDVB256(v *Value) bool { if !(v.Block.CPUfeatures.hasFeature(CPUavx512)) { break } - v.reset(OpAMD64VCVTPS2UDQMasked256Merging) - v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x8ToM, types.TypeMask) + v.reset(OpAMD64VCVTTPD2DQYMasked128Merging) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x4ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(dst, x, v0) + return true + } + // match: (VPBLENDVB256 dst (VCVTTPD2QQ256 x) mask) + // cond: v.Block.CPUfeatures.hasFeature(CPUavx512) + // result: (VCVTTPD2QQMasked256Merging dst x (VPMOVVec64x4ToM mask)) + for { + dst := v_0 + if v_1.Op != OpAMD64VCVTTPD2QQ256 { + break + } + x := v_1.Args[0] + mask := v_2 + if !(v.Block.CPUfeatures.hasFeature(CPUavx512)) { + break + } + v.reset(OpAMD64VCVTTPD2QQMasked256Merging) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x4ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(dst, x, v0) + return true + } + // match: (VPBLENDVB256 dst (VCVTTPD2UDQY128 x) mask) + // cond: v.Block.CPUfeatures.hasFeature(CPUavx512) + // result: (VCVTTPD2UDQYMasked128Merging dst x (VPMOVVec64x4ToM mask)) + for { + dst := v_0 + if v_1.Op != OpAMD64VCVTTPD2UDQY128 { + break + } + x := v_1.Args[0] + mask := v_2 + if !(v.Block.CPUfeatures.hasFeature(CPUavx512)) { + break + } + v.reset(OpAMD64VCVTTPD2UDQYMasked128Merging) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x4ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(dst, x, v0) + return true + } + // match: (VPBLENDVB256 dst (VCVTTPD2UQQ256 x) mask) + // cond: v.Block.CPUfeatures.hasFeature(CPUavx512) + // result: (VCVTTPD2UQQMasked256Merging dst x (VPMOVVec64x4ToM mask)) + for { + dst := v_0 + if v_1.Op != OpAMD64VCVTTPD2UQQ256 { + break + } + x := v_1.Args[0] + mask := v_2 + if !(v.Block.CPUfeatures.hasFeature(CPUavx512)) { + break + } + v.reset(OpAMD64VCVTTPD2UQQMasked256Merging) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x4ToM, types.TypeMask) v0.AddArg(mask) v.AddArg3(dst, x, v0) return true @@ -46235,6 +47540,63 @@ func rewriteValueAMD64_OpAMD64VPBLENDVB256(v *Value) bool { v.AddArg3(dst, x, v0) return true } + // match: (VPBLENDVB256 dst (VCVTTPS2QQ512 x) mask) + // cond: v.Block.CPUfeatures.hasFeature(CPUavx512) + // result: (VCVTTPS2QQMasked512Merging dst x (VPMOVVec32x8ToM mask)) + for { + dst := v_0 + if v_1.Op != OpAMD64VCVTTPS2QQ512 { + break + } + x := v_1.Args[0] + mask := v_2 + if !(v.Block.CPUfeatures.hasFeature(CPUavx512)) { + break + } + v.reset(OpAMD64VCVTTPS2QQMasked512Merging) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x8ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(dst, x, v0) + return true + } + // match: (VPBLENDVB256 dst (VCVTTPS2UDQ256 x) mask) + // cond: v.Block.CPUfeatures.hasFeature(CPUavx512) + // result: (VCVTTPS2UDQMasked256Merging dst x (VPMOVVec32x8ToM mask)) + for { + dst := v_0 + if v_1.Op != OpAMD64VCVTTPS2UDQ256 { + break + } + x := v_1.Args[0] + mask := v_2 + if !(v.Block.CPUfeatures.hasFeature(CPUavx512)) { + break + } + v.reset(OpAMD64VCVTTPS2UDQMasked256Merging) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x8ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(dst, x, v0) + return true + } + // match: (VPBLENDVB256 dst (VCVTTPS2UQQ512 x) mask) + // cond: v.Block.CPUfeatures.hasFeature(CPUavx512) + // result: (VCVTTPS2UQQMasked512Merging dst x (VPMOVVec32x8ToM mask)) + for { + dst := v_0 + if v_1.Op != OpAMD64VCVTTPS2UQQ512 { + break + } + x := v_1.Args[0] + mask := v_2 + if !(v.Block.CPUfeatures.hasFeature(CPUavx512)) { + break + } + v.reset(OpAMD64VCVTTPS2UQQMasked512Merging) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x8ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(dst, x, v0) + return true + } // match: (VPBLENDVB256 dst (VDIVPD256 x y) mask) // cond: v.Block.CPUfeatures.hasFeature(CPUavx512) // result: (VDIVPDMasked256Merging dst x y (VPMOVVec64x4ToM mask)) diff --git a/src/cmd/compile/internal/ssagen/simdintrinsics.go b/src/cmd/compile/internal/ssagen/simdintrinsics.go index 987be73210..eb16f2db32 100644 --- a/src/cmd/compile/internal/ssagen/simdintrinsics.go +++ b/src/cmd/compile/internal/ssagen/simdintrinsics.go @@ -264,9 +264,25 @@ func simdIntrinsics(addF func(pkg, fn string, b intrinsicBuilder, archFamilies . addF(simdPackage, "Float32x4.ConvertToInt32", opLen1(ssa.OpConvertToInt32Float32x4, types.TypeVec128), sys.AMD64) addF(simdPackage, "Float32x8.ConvertToInt32", opLen1(ssa.OpConvertToInt32Float32x8, types.TypeVec256), sys.AMD64) addF(simdPackage, "Float32x16.ConvertToInt32", opLen1(ssa.OpConvertToInt32Float32x16, types.TypeVec512), sys.AMD64) + addF(simdPackage, "Float64x2.ConvertToInt32", opLen1(ssa.OpConvertToInt32Float64x2, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Float64x4.ConvertToInt32", opLen1(ssa.OpConvertToInt32Float64x4, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Float64x8.ConvertToInt32", opLen1(ssa.OpConvertToInt32Float64x8, types.TypeVec256), sys.AMD64) + addF(simdPackage, "Float32x4.ConvertToInt64", opLen1(ssa.OpConvertToInt64Float32x4, types.TypeVec256), sys.AMD64) + addF(simdPackage, "Float32x8.ConvertToInt64", opLen1(ssa.OpConvertToInt64Float32x8, types.TypeVec512), sys.AMD64) + addF(simdPackage, "Float64x2.ConvertToInt64", opLen1(ssa.OpConvertToInt64Float64x2, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Float64x4.ConvertToInt64", opLen1(ssa.OpConvertToInt64Float64x4, types.TypeVec256), sys.AMD64) + addF(simdPackage, "Float64x8.ConvertToInt64", opLen1(ssa.OpConvertToInt64Float64x8, types.TypeVec512), sys.AMD64) addF(simdPackage, "Float32x4.ConvertToUint32", opLen1(ssa.OpConvertToUint32Float32x4, types.TypeVec128), sys.AMD64) addF(simdPackage, "Float32x8.ConvertToUint32", opLen1(ssa.OpConvertToUint32Float32x8, types.TypeVec256), sys.AMD64) addF(simdPackage, "Float32x16.ConvertToUint32", opLen1(ssa.OpConvertToUint32Float32x16, types.TypeVec512), sys.AMD64) + addF(simdPackage, "Float64x2.ConvertToUint32", opLen1(ssa.OpConvertToUint32Float64x2, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Float64x4.ConvertToUint32", opLen1(ssa.OpConvertToUint32Float64x4, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Float64x8.ConvertToUint32", opLen1(ssa.OpConvertToUint32Float64x8, types.TypeVec256), sys.AMD64) + addF(simdPackage, "Float32x4.ConvertToUint64", opLen1(ssa.OpConvertToUint64Float32x4, types.TypeVec256), sys.AMD64) + addF(simdPackage, "Float32x8.ConvertToUint64", opLen1(ssa.OpConvertToUint64Float32x8, types.TypeVec512), sys.AMD64) + addF(simdPackage, "Float64x2.ConvertToUint64", opLen1(ssa.OpConvertToUint64Float64x2, types.TypeVec128), sys.AMD64) + addF(simdPackage, "Float64x4.ConvertToUint64", opLen1(ssa.OpConvertToUint64Float64x4, types.TypeVec256), sys.AMD64) + addF(simdPackage, "Float64x8.ConvertToUint64", opLen1(ssa.OpConvertToUint64Float64x8, types.TypeVec512), sys.AMD64) addF(simdPackage, "Int8x16.CopySign", opLen2(ssa.OpCopySignInt8x16, types.TypeVec128), sys.AMD64) addF(simdPackage, "Int8x32.CopySign", opLen2(ssa.OpCopySignInt8x32, types.TypeVec256), sys.AMD64) addF(simdPackage, "Int16x8.CopySign", opLen2(ssa.OpCopySignInt16x8, types.TypeVec128), sys.AMD64) diff --git a/src/simd/_gen/simdgen/gen_simdrules.go b/src/simd/_gen/simdgen/gen_simdrules.go index 5693496c92..90c3fb620e 100644 --- a/src/simd/_gen/simdgen/gen_simdrules.go +++ b/src/simd/_gen/simdgen/gen_simdrules.go @@ -322,7 +322,7 @@ func writeSIMDRules(ops []Operation) *bytes.Buffer { rule := fmt.Sprintf("(VPBLENDVB%d dst (%s %s) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (%sMerging dst %s (VPMOVVec%dx%dToM mask))\n", *maskElem.Bits, noMaskName, data.Args, data.Asm, data.Args, *maskElem.ElemBits, *maskElem.Lanes) if ok && ruleExisting != rule { - panic("multiple masked merge rules for one op") + panic(fmt.Sprintf("multiple masked merge rules for one op:\n%s\n%s\n", ruleExisting, rule)) } else { maskedMergeOpts[noMaskName] = rule } @@ -333,7 +333,7 @@ func writeSIMDRules(ops []Operation) *bytes.Buffer { rule := fmt.Sprintf("(VPBLENDM%sMasked%d dst (%s %s) mask) => (%sMerging dst %s mask)\n", s2n[*maskElem.ElemBits], *maskElem.Bits, noMaskName, data.Args, data.Asm, data.Args) if ok && ruleExisting != rule { - panic("multiple masked merge rules for one op") + panic(fmt.Sprintf("multiple masked merge rules for one op:\n%s\n%s\n", ruleExisting, rule)) } else { maskedMergeOpts[noMaskName] = rule } diff --git a/src/simd/_gen/simdgen/gen_utility.go b/src/simd/_gen/simdgen/gen_utility.go index c0bc73d5dc..c1d8fc9417 100644 --- a/src/simd/_gen/simdgen/gen_utility.go +++ b/src/simd/_gen/simdgen/gen_utility.go @@ -335,6 +335,18 @@ func (op *Operation) sortOperand() { }) } +// adjustAsm adjusts the asm to make it align with Go's assembler. +func (op *Operation) adjustAsm() { + if op.Asm == "VCVTTPD2DQ" || op.Asm == "VCVTTPD2UDQ" { + switch *op.In[0].Bits { + case 128: + op.Asm += "X" + case 256: + op.Asm += "Y" + } + } +} + // goNormalType returns the Go type name for the result of an Op that // does not return a vector, i.e., that returns a result in a general // register. Currently there's only one family of Ops in Go's simd library diff --git a/src/simd/_gen/simdgen/godefs.go b/src/simd/_gen/simdgen/godefs.go index c127eb1b6d..fb43116576 100644 --- a/src/simd/_gen/simdgen/godefs.go +++ b/src/simd/_gen/simdgen/godefs.go @@ -381,6 +381,7 @@ func writeGoDefs(path string, cl unify.Closure) error { } // TODO: verify that this is safe. op.sortOperand() + op.adjustAsm() ops = append(ops, op) } slices.SortFunc(ops, compareOperations) @@ -399,9 +400,6 @@ func writeGoDefs(path string, cl unify.Closure) error { if *Verbose { log.Printf("dedup len: %d\n", len(deduped)) } - if *Verbose { - log.Printf("dedup len: %d\n", len(deduped)) - } if !*FlagNoDedup { // TODO: This can hide mistakes in the API definitions, especially when // multiple patterns result in the same API unintentionally. Make it stricter. diff --git a/src/simd/_gen/simdgen/ops/Converts/categories.yaml b/src/simd/_gen/simdgen/ops/Converts/categories.yaml index 9abdf454d6..572a710f16 100644 --- a/src/simd/_gen/simdgen/ops/Converts/categories.yaml +++ b/src/simd/_gen/simdgen/ops/Converts/categories.yaml @@ -1,6 +1,35 @@ !sum -# Non-truncating conversions -# int<->int or uint<->uint widening, float<->int|uint conversions or trucating conversions. +# Float <-> Int conversions +- go: "ConvertToInt32" + commutative: false + regexpTag: "convert" + documentation: !string |- + // NAME converts element values to int32. + // When a conversion is inexact, a truncated (round toward zero) value is returned. + // If a converted result is larger than the maximum int32, the indefinite value is returned. +- go: "ConvertToUint32" + commutative: false + regexpTag: "convert" + documentation: !string |- + // NAME converts element values to uint32. + // When a conversion is inexact, a truncated (round toward zero) value is returned. + // If a converted result is larger than the maximum uint32, the maximum uint32 value is returned. +- go: "ConvertToInt64" + commutative: false + regexpTag: "convert" + documentation: !string |- + // NAME converts element values to int64. + // When a conversion is inexact, a truncated (round toward zero) value is returned. + // If a converted result is larger than the maximum int64, the indefinite value is returned. +- go: "ConvertToUint64" + commutative: false + regexpTag: "convert" + documentation: !string |- + // NAME converts element values to uint64. + // When a conversion is inexact, a truncated (round toward zero) value is returned. + // If a converted result is larger than the maximum uint64, the maximum uint64 value is returned. + +# Int <-> Int conversions - go: "(Extend|Saturate|Truncate)?ToInt8" commutative: false regexpTag: "convert" @@ -11,7 +40,7 @@ regexpTag: "convert" documentation: !string |- // NAME converts element values to int16. -- go: "(Extend|Saturate|Truncate)?(Convert)?ToInt32" +- go: "(Extend|Saturate|Truncate)?ToInt32" commutative: false regexpTag: "convert" documentation: !string |- @@ -31,7 +60,7 @@ regexpTag: "convert" documentation: !string |- // NAME converts element values to uint16. -- go: "(Extend|Saturate|Truncate)?(Convert)?ToUint32" +- go: "(Extend|Saturate|Truncate)?ToUint32" regexpTag: "convert" commutative: false documentation: !string |- @@ -41,9 +70,7 @@ commutative: false documentation: !string |- // NAME converts element values to uint64. - -# low-part only conversions -# int<->int or uint<->uint widening conversions. +# low-part only Int <-> Int conversions - go: ExtendLo8ToUint16x8 commutative: false documentation: !string |- diff --git a/src/simd/_gen/simdgen/ops/Converts/go.yaml b/src/simd/_gen/simdgen/ops/Converts/go.yaml index 88e43b8dbf..3968a184e4 100644 --- a/src/simd/_gen/simdgen/ops/Converts/go.yaml +++ b/src/simd/_gen/simdgen/ops/Converts/go.yaml @@ -3,7 +3,7 @@ # float32 -> int32 - go: ConvertToInt32 regexpTag: "convert" - asm: "VCVTTPS2DQ" + asm: "VCVTTP[SD]2DQ" in: - &fp go: $t @@ -16,7 +16,7 @@ # float32 -> uint32 - go: ConvertToUint32 regexpTag: "convert" - asm: "VCVTPS2UDQ" + asm: "VCVTTP[SD]2UDQ" in: - *fp out: @@ -24,6 +24,49 @@ go: $u base: uint elemBits: 32 +# float32|float64 -> int64 +- go: ConvertToInt64 + regexpTag: "convert" + asm: "VCVTTPD2QQ" + in: + - *fp + out: + - &i64 + go: $u + base: int + elemBits: 64 +- go: ConvertToInt64 + regexpTag: "convert" + asm: "VCVTTPS2QQ" + in: + - *fp + out: + - go: $u + base: int + elemBits: 64 + bits: 256|512 +# float32|float64 -> uint64 +- go: ConvertToUint64 + regexpTag: "convert" + asm: "VCVTTPD2UQQ" + in: + - *fp + out: + - &u64 + go: $u + base: uint + elemBits: 64 +- go: ConvertToUint64 + regexpTag: "convert" + asm: "VCVTTPS2UQQ" + in: + - *fp + out: + - go: $u + base: uint + elemBits: 64 + bits: 256|512 + # Widening integer conversions. # uint8 -> uint16 - go: ExtendToUint16 diff --git a/src/simd/ops_amd64.go b/src/simd/ops_amd64.go index 38d984622d..22416e270a 100644 --- a/src/simd/ops_amd64.go +++ b/src/simd/ops_amd64.go @@ -1547,37 +1547,165 @@ func (x Uint8x64) ConcatShiftBytesRightGrouped(constant uint8, y Uint8x64) Uint8 /* ConvertToInt32 */ // ConvertToInt32 converts element values to int32. +// When a conversion is inexact, a truncated (round toward zero) value is returned. +// If a converted result is larger than the maximum int32, the indefinite value is returned. // // Asm: VCVTTPS2DQ, CPU Feature: AVX func (x Float32x4) ConvertToInt32() Int32x4 // ConvertToInt32 converts element values to int32. +// When a conversion is inexact, a truncated (round toward zero) value is returned. +// If a converted result is larger than the maximum int32, the indefinite value is returned. // // Asm: VCVTTPS2DQ, CPU Feature: AVX func (x Float32x8) ConvertToInt32() Int32x8 // ConvertToInt32 converts element values to int32. +// When a conversion is inexact, a truncated (round toward zero) value is returned. +// If a converted result is larger than the maximum int32, the indefinite value is returned. // // Asm: VCVTTPS2DQ, CPU Feature: AVX512 func (x Float32x16) ConvertToInt32() Int32x16 +// ConvertToInt32 converts element values to int32. +// When a conversion is inexact, a truncated (round toward zero) value is returned. +// If a converted result is larger than the maximum int32, the indefinite value is returned. +// +// Asm: VCVTTPD2DQX, CPU Feature: AVX +func (x Float64x2) ConvertToInt32() Int32x4 + +// ConvertToInt32 converts element values to int32. +// When a conversion is inexact, a truncated (round toward zero) value is returned. +// If a converted result is larger than the maximum int32, the indefinite value is returned. +// +// Asm: VCVTTPD2DQY, CPU Feature: AVX +func (x Float64x4) ConvertToInt32() Int32x4 + +// ConvertToInt32 converts element values to int32. +// When a conversion is inexact, a truncated (round toward zero) value is returned. +// If a converted result is larger than the maximum int32, the indefinite value is returned. +// +// Asm: VCVTTPD2DQ, CPU Feature: AVX512 +func (x Float64x8) ConvertToInt32() Int32x8 + +/* ConvertToInt64 */ + +// ConvertToInt64 converts element values to int64. +// When a conversion is inexact, a truncated (round toward zero) value is returned. +// If a converted result is larger than the maximum int64, the indefinite value is returned. +// +// Asm: VCVTTPS2QQ, CPU Feature: AVX512 +func (x Float32x4) ConvertToInt64() Int64x4 + +// ConvertToInt64 converts element values to int64. +// When a conversion is inexact, a truncated (round toward zero) value is returned. +// If a converted result is larger than the maximum int64, the indefinite value is returned. +// +// Asm: VCVTTPS2QQ, CPU Feature: AVX512 +func (x Float32x8) ConvertToInt64() Int64x8 + +// ConvertToInt64 converts element values to int64. +// When a conversion is inexact, a truncated (round toward zero) value is returned. +// If a converted result is larger than the maximum int64, the indefinite value is returned. +// +// Asm: VCVTTPD2QQ, CPU Feature: AVX512 +func (x Float64x2) ConvertToInt64() Int64x2 + +// ConvertToInt64 converts element values to int64. +// When a conversion is inexact, a truncated (round toward zero) value is returned. +// If a converted result is larger than the maximum int64, the indefinite value is returned. +// +// Asm: VCVTTPD2QQ, CPU Feature: AVX512 +func (x Float64x4) ConvertToInt64() Int64x4 + +// ConvertToInt64 converts element values to int64. +// When a conversion is inexact, a truncated (round toward zero) value is returned. +// If a converted result is larger than the maximum int64, the indefinite value is returned. +// +// Asm: VCVTTPD2QQ, CPU Feature: AVX512 +func (x Float64x8) ConvertToInt64() Int64x8 + /* ConvertToUint32 */ // ConvertToUint32 converts element values to uint32. +// When a conversion is inexact, a truncated (round toward zero) value is returned. +// If a converted result is larger than the maximum uint32, the maximum uint32 value is returned. // -// Asm: VCVTPS2UDQ, CPU Feature: AVX512 +// Asm: VCVTTPS2UDQ, CPU Feature: AVX512 func (x Float32x4) ConvertToUint32() Uint32x4 // ConvertToUint32 converts element values to uint32. +// When a conversion is inexact, a truncated (round toward zero) value is returned. +// If a converted result is larger than the maximum uint32, the maximum uint32 value is returned. // -// Asm: VCVTPS2UDQ, CPU Feature: AVX512 +// Asm: VCVTTPS2UDQ, CPU Feature: AVX512 func (x Float32x8) ConvertToUint32() Uint32x8 // ConvertToUint32 converts element values to uint32. +// When a conversion is inexact, a truncated (round toward zero) value is returned. +// If a converted result is larger than the maximum uint32, the maximum uint32 value is returned. // -// Asm: VCVTPS2UDQ, CPU Feature: AVX512 +// Asm: VCVTTPS2UDQ, CPU Feature: AVX512 func (x Float32x16) ConvertToUint32() Uint32x16 +// ConvertToUint32 converts element values to uint32. +// When a conversion is inexact, a truncated (round toward zero) value is returned. +// If a converted result is larger than the maximum uint32, the maximum uint32 value is returned. +// +// Asm: VCVTTPD2UDQX, CPU Feature: AVX512 +func (x Float64x2) ConvertToUint32() Uint32x4 + +// ConvertToUint32 converts element values to uint32. +// When a conversion is inexact, a truncated (round toward zero) value is returned. +// If a converted result is larger than the maximum uint32, the maximum uint32 value is returned. +// +// Asm: VCVTTPD2UDQY, CPU Feature: AVX512 +func (x Float64x4) ConvertToUint32() Uint32x4 + +// ConvertToUint32 converts element values to uint32. +// When a conversion is inexact, a truncated (round toward zero) value is returned. +// If a converted result is larger than the maximum uint32, the maximum uint32 value is returned. +// +// Asm: VCVTTPD2UDQ, CPU Feature: AVX512 +func (x Float64x8) ConvertToUint32() Uint32x8 + +/* ConvertToUint64 */ + +// ConvertToUint64 converts element values to uint64. +// When a conversion is inexact, a truncated (round toward zero) value is returned. +// If a converted result is larger than the maximum uint64, the maximum uint64 value is returned. +// +// Asm: VCVTTPS2UQQ, CPU Feature: AVX512 +func (x Float32x4) ConvertToUint64() Uint64x4 + +// ConvertToUint64 converts element values to uint64. +// When a conversion is inexact, a truncated (round toward zero) value is returned. +// If a converted result is larger than the maximum uint64, the maximum uint64 value is returned. +// +// Asm: VCVTTPS2UQQ, CPU Feature: AVX512 +func (x Float32x8) ConvertToUint64() Uint64x8 + +// ConvertToUint64 converts element values to uint64. +// When a conversion is inexact, a truncated (round toward zero) value is returned. +// If a converted result is larger than the maximum uint64, the maximum uint64 value is returned. +// +// Asm: VCVTTPD2UQQ, CPU Feature: AVX512 +func (x Float64x2) ConvertToUint64() Uint64x2 + +// ConvertToUint64 converts element values to uint64. +// When a conversion is inexact, a truncated (round toward zero) value is returned. +// If a converted result is larger than the maximum uint64, the maximum uint64 value is returned. +// +// Asm: VCVTTPD2UQQ, CPU Feature: AVX512 +func (x Float64x4) ConvertToUint64() Uint64x4 + +// ConvertToUint64 converts element values to uint64. +// When a conversion is inexact, a truncated (round toward zero) value is returned. +// If a converted result is larger than the maximum uint64, the maximum uint64 value is returned. +// +// Asm: VCVTTPD2UQQ, CPU Feature: AVX512 +func (x Float64x8) ConvertToUint64() Uint64x8 + /* CopySign */ // CopySign returns the product of the first operand with -1, 0, or 1, -- 2.52.0