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(parent: 8e0be05) | patch
reflect: correct riscv64 assembly
authorJoel Sing <joel@sing.id.au>
Sun, 19 Jan 2020 15:00:44 +0000 (02:00 +1100)
committerJoel Sing <joel@sing.id.au>
Sun, 19 Jan 2020 15:28:32 +0000 (15:28 +0000)
commit02816a2cad23a9399a6ad18033db0586c110de70
treeb0283cf9ffbc23000ca74fa9314c4545c419addbtree
parent8e0be05ec7c369387c0ed3c9cf37968c6d3afbbdcommit | diff
reflect: correct riscv64 assembly

R0 is not a thing in riscv64 assembly - use ZERO (rather than X0) since
the rest of this currently uses ABI names.

Updates #27532

Change-Id: I28fb68e9f80d05231a07c5921e7062777234e2c5
Reviewed-on: https://go-review.googlesource.com/c/go/+/215437
Reviewed-by: Brad Fitzpatrick <bradfitz@golang.org>
src/reflect/asm_riscv64.s diff | blob | history
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