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cmd/internal/obj/riscv: add NEG/NEGW pseudo-instructions
authorJoel Sing <joel@sing.id.au>
Mon, 2 Mar 2020 16:41:43 +0000 (03:41 +1100)
committerJoel Sing <joel@sing.id.au>
Sun, 15 Mar 2020 08:15:09 +0000 (08:15 +0000)
commit25da2ea72c18a63f5efdb7c506669aa733693bea
treedf3bf3e98f2350bd057bcb74af29e00cf355e3batree
parentdc3255391a59474eda08e71eaf8090753b0a84dbcommit | diff
cmd/internal/obj/riscv: add NEG/NEGW pseudo-instructions

Provide NEG/NEGW pseudo-instructions, which translate to SUB/SUBW with the
zero register as a source.

Change-Id: I2c1ec1e75611c234c5ee8e39390dd188f8e42bae
Reviewed-on: https://go-review.googlesource.com/c/go/+/221689
Reviewed-by: Cherry Zhang <cherryyz@google.com>
src/cmd/asm/internal/asm/testdata/riscvenc.s diff | blob | history
src/cmd/internal/obj/riscv/anames.go diff | blob | history
src/cmd/internal/obj/riscv/cpu.go diff | blob | history
src/cmd/internal/obj/riscv/obj.go diff | blob | history
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