]> Cypherpunks repositories - gostls13.git/commit
cmd/internal/obj/riscv: implement vector load/store instructions
authorJoel Sing <joel@sing.id.au>
Mon, 17 Jun 2024 17:00:47 +0000 (03:00 +1000)
committerJoel Sing <joel@sing.id.au>
Thu, 27 Feb 2025 11:47:20 +0000 (03:47 -0800)
commit37e9c5eaba30db61823643e761b31cdae8cc1854
treebc626bcf20f51fcc37c0f05586468c5cb04d9b70
parent927fdb7843ce96b42791912b42d0d3e6735e8dde
cmd/internal/obj/riscv: implement vector load/store instructions

Implement vector unit stride, vector strided, vector indexed and
vector whole register load and store instructions.

The vector unit stride instructions take an optional vector mask
register, which if specified must be register V0. If only two
operands are given, the instruction is encoded as unmasked.

The vector strided and vector indexed instructions also take an
optional vector mask register, which if specified must be register
V0. If only three operands are given, the instruction is encoded as
unmasked.

Cq-Include-Trybots: luci.golang.try:gotip-linux-riscv64
Change-Id: I35e43bb8f1cf6ae8826fbeec384b95ac945da50f
Reviewed-on: https://go-review.googlesource.com/c/go/+/631937
LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com>
Reviewed-by: Mark Ryan <markdryan@rivosinc.com>
Reviewed-by: Michael Knyszek <mknyszek@google.com>
Reviewed-by: Meng Zhuo <mengzhuo1203@gmail.com>
Reviewed-by: Dmitri Shuralyov <dmitshur@google.com>
Reviewed-by: Pengcheng Wang <wangpengcheng.pp@bytedance.com>
src/cmd/asm/internal/asm/testdata/riscv64.s
src/cmd/asm/internal/asm/testdata/riscv64error.s
src/cmd/internal/obj/riscv/anames.go
src/cmd/internal/obj/riscv/cpu.go
src/cmd/internal/obj/riscv/obj.go