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cmd/asm,cmd/internal/obj/riscv: add LR/SC instructions
authorJoel Sing <joel@sing.id.au>
Thu, 20 Feb 2020 15:30:09 +0000 (02:30 +1100)
committerJoel Sing <joel@sing.id.au>
Sun, 15 Mar 2020 07:51:41 +0000 (07:51 +0000)
commit85a8526a7e8d12a31f2f1d9ebcec2841a27dc493
treed593e38d6bd5ff2d71ace71965323bac033a8474tree
parent2a08f3c18127f91b22ef4f3f96c52850959b25accommit | diff
cmd/asm,cmd/internal/obj/riscv: add LR/SC instructions

Add support for Load-Reserved (LR) and Store-Conditional (SC) instructions.

Use instructions in place of currently used defines.

Updates #36765

Change-Id: I77e660639802293ece40cfde4865ac237e3308d6
Reviewed-on: https://go-review.googlesource.com/c/go/+/220540
Reviewed-by: Cherry Zhang <cherryyz@google.com>
src/cmd/asm/internal/arch/riscv64.go [new file with mode: 0644] blob
src/cmd/asm/internal/asm/asm.go diff | blob | history
src/cmd/asm/internal/asm/testdata/riscvenc.s diff | blob | history
src/cmd/internal/obj/riscv/obj.go diff | blob | history
src/runtime/internal/atomic/atomic_riscv64.s diff | blob | history
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