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(parent: 15131ca) | patch
runtime: optimise gcWriteBarrier for riscv64
authorJoel Sing <joel@sing.id.au>
Tue, 27 Oct 2020 12:30:14 +0000 (23:30 +1100)
committerJoel Sing <joel@sing.id.au>
Thu, 29 Oct 2020 08:00:23 +0000 (08:00 +0000)
commitae82ee4016c44e558b002f0c7ffbb40d698d411e
tree3b29df058948547e92799165bf01a67147038b09tree
parent15131caeaa83e57fd8bdf87dde2801443f5602dbcommit | diff
runtime: optimise gcWriteBarrier for riscv64

Avoid saving unnecessary registers in gcWriteBarrier on riscv64, which also
removes references to X4 and X27 (TP and g registers).

Change-Id: I2854161dcdf0c6047a45347165371827dcf8c1cf
Reviewed-on: https://go-review.googlesource.com/c/go/+/265518
Trust: Joel Sing <joel@sing.id.au>
Reviewed-by: Cherry Zhang <cherryyz@google.com>
Run-TryBot: Cherry Zhang <cherryyz@google.com>
TryBot-Result: Go Bot <gobot@golang.org>
src/runtime/asm_riscv64.s diff | blob | history
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