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(parent: 32dbccd) | patch
cmd/internal/obj/riscv: add NOT pseudo-instruction
authorJoel Sing <joel@sing.id.au>
Mon, 2 Mar 2020 16:40:37 +0000 (03:40 +1100)
committerJoel Sing <joel@sing.id.au>
Sun, 15 Mar 2020 08:14:24 +0000 (08:14 +0000)
commitdc3255391a59474eda08e71eaf8090753b0a84db
treea67d47a6e086df2f58cfc3412eb690d22e9bda3ftree
parent32dbccde78562763b6d5cc847d32c5f94fa6cab4commit | diff
cmd/internal/obj/riscv: add NOT pseudo-instruction

Add a NOT pseudo-instruction that translates to XORI $-1.

Change-Id: I2be4cfe2939e988cd7f8d30260b704701d78475f
Reviewed-on: https://go-review.googlesource.com/c/go/+/221688
Reviewed-by: Cherry Zhang <cherryyz@google.com>
src/cmd/asm/internal/asm/testdata/riscvenc.s diff | blob | history
src/cmd/internal/obj/riscv/anames.go diff | blob | history
src/cmd/internal/obj/riscv/cpu.go diff | blob | history
src/cmd/internal/obj/riscv/obj.go diff | blob | history
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