(MOVWstore [off] {sym} ptr (MOVWreg x) mem) => (MOVWstore [off] {sym} ptr x mem)
(MOVWstore [off] {sym} ptr (MOVWUreg x) mem) => (MOVWstore [off] {sym} ptr x mem)
+(MOVBstore [off] {sym} ptr (MOVVconst [0]) mem) => (MOVBstorezero [off] {sym} ptr mem)
+(MOVHstore [off] {sym} ptr (MOVVconst [0]) mem) => (MOVHstorezero [off] {sym} ptr mem)
+(MOVWstore [off] {sym} ptr (MOVVconst [0]) mem) => (MOVWstorezero [off] {sym} ptr mem)
+(MOVVstore [off] {sym} ptr (MOVVconst [0]) mem) => (MOVVstorezero [off] {sym} ptr mem)
+
// register indexed load
(MOVVload [off] {sym} (ADDV ptr idx) mem) && off == 0 && sym == nil => (MOVVloadidx ptr idx mem)
(MOVWUload [off] {sym} (ADDV ptr idx) mem) && off == 0 && sym == nil => (MOVWUloadidx ptr idx mem)
v.AddArg3(ptr, x, mem)
return true
}
+ // match: (MOVBstore [off] {sym} ptr (MOVVconst [0]) mem)
+ // result: (MOVBstorezero [off] {sym} ptr mem)
+ for {
+ off := auxIntToInt32(v.AuxInt)
+ sym := auxToSym(v.Aux)
+ ptr := v_0
+ if v_1.Op != OpLOONG64MOVVconst || auxIntToInt64(v_1.AuxInt) != 0 {
+ break
+ }
+ mem := v_2
+ v.reset(OpLOONG64MOVBstorezero)
+ v.AuxInt = int32ToAuxInt(off)
+ v.Aux = symToAux(sym)
+ v.AddArg2(ptr, mem)
+ return true
+ }
// match: (MOVBstore [off] {sym} (ADDV ptr idx) val mem)
// cond: off == 0 && sym == nil
// result: (MOVBstoreidx ptr idx val mem)
v.AddArg3(ptr, x, mem)
return true
}
+ // match: (MOVHstore [off] {sym} ptr (MOVVconst [0]) mem)
+ // result: (MOVHstorezero [off] {sym} ptr mem)
+ for {
+ off := auxIntToInt32(v.AuxInt)
+ sym := auxToSym(v.Aux)
+ ptr := v_0
+ if v_1.Op != OpLOONG64MOVVconst || auxIntToInt64(v_1.AuxInt) != 0 {
+ break
+ }
+ mem := v_2
+ v.reset(OpLOONG64MOVHstorezero)
+ v.AuxInt = int32ToAuxInt(off)
+ v.Aux = symToAux(sym)
+ v.AddArg2(ptr, mem)
+ return true
+ }
// match: (MOVHstore [off] {sym} (ADDV ptr idx) val mem)
// cond: off == 0 && sym == nil
// result: (MOVHstoreidx ptr idx val mem)
v.AddArg3(ptr, val, mem)
return true
}
+ // match: (MOVVstore [off] {sym} ptr (MOVVconst [0]) mem)
+ // result: (MOVVstorezero [off] {sym} ptr mem)
+ for {
+ off := auxIntToInt32(v.AuxInt)
+ sym := auxToSym(v.Aux)
+ ptr := v_0
+ if v_1.Op != OpLOONG64MOVVconst || auxIntToInt64(v_1.AuxInt) != 0 {
+ break
+ }
+ mem := v_2
+ v.reset(OpLOONG64MOVVstorezero)
+ v.AuxInt = int32ToAuxInt(off)
+ v.Aux = symToAux(sym)
+ v.AddArg2(ptr, mem)
+ return true
+ }
// match: (MOVVstore [off] {sym} (ADDV ptr idx) val mem)
// cond: off == 0 && sym == nil
// result: (MOVVstoreidx ptr idx val mem)
v.AddArg3(ptr, x, mem)
return true
}
+ // match: (MOVWstore [off] {sym} ptr (MOVVconst [0]) mem)
+ // result: (MOVWstorezero [off] {sym} ptr mem)
+ for {
+ off := auxIntToInt32(v.AuxInt)
+ sym := auxToSym(v.Aux)
+ ptr := v_0
+ if v_1.Op != OpLOONG64MOVVconst || auxIntToInt64(v_1.AuxInt) != 0 {
+ break
+ }
+ mem := v_2
+ v.reset(OpLOONG64MOVWstorezero)
+ v.AuxInt = int32ToAuxInt(off)
+ v.Aux = symToAux(sym)
+ v.AddArg2(ptr, mem)
+ return true
+ }
// match: (MOVWstore [off] {sym} (ADDV ptr idx) val mem)
// cond: off == 0 && sym == nil
// result: (MOVWstoreidx ptr idx val mem)