cmd/compile: add scale field to SSA Ops

Refactoring only.

This makes it easier to add ops
that do indexed memory loads/stores.

Passes toolstash-check.

Change-Id: I82df0d4154718577ec42106fa1bc76571bf65096
Reviewed-on: https://go-review.googlesource.com/c/go/+/166425
Run-TryBot: Josh Bleecher Snyder <josharian@gmail.com>
TryBot-Result: Gobot Gobot <gobot@golang.org>
Reviewed-by: Keith Randall <khr@golang.org>

diff --git a/src/cmd/compile/internal/amd64/ssa.go b/src/cmd/compile/internal/amd64/ssa.go
index a2c7d5d8d8561ed07d1a6f12145b461151f25854..b9fca18d4f242242a4901ffc7db9b042b64135f5 100644 (file)
--- a/src/cmd/compile/internal/amd64/ssa.go
+++ b/src/cmd/compile/internal/amd64/ssa.go
@@ -117,6 +117,21 @@ func opregreg(s *gc.SSAGenState, op obj.As, dest, src int16) *obj.Prog {
        return p
 }
 
+// memIdx fills out a as an indexed memory reference for v.
+// It assumes that the base register and the index register
+// are v.Args[0].Reg() and v.Args[1].Reg(), respectively.
+// The caller must still use gc.AddAux/gc.AddAux2 to handle v.Aux as necessary.
+func memIdx(a *obj.Addr, v *ssa.Value) {
+       r, i := v.Args[0].Reg(), v.Args[1].Reg()
+       a.Type = obj.TYPE_MEM
+       a.Scale = v.Op.Scale()
+       if a.Scale == 1 && i == x86.REG_SP {
+               r, i = i, r
+       }
+       a.Reg = r
+       a.Index = i
+}
+
 // DUFFZERO consists of repeated blocks of 4 MOVUPSs + LEAQ,
 // See runtime/mkduff.go.
 func duffStart(size int64) int64 {
@@ -571,26 +586,9 @@ func ssaGenValue(s *gc.SSAGenState, v *ssa.Value) {
        case ssa.OpAMD64LEAQ1, ssa.OpAMD64LEAQ2, ssa.OpAMD64LEAQ4, ssa.OpAMD64LEAQ8,
                ssa.OpAMD64LEAL1, ssa.OpAMD64LEAL2, ssa.OpAMD64LEAL4, ssa.OpAMD64LEAL8,
                ssa.OpAMD64LEAW1, ssa.OpAMD64LEAW2, ssa.OpAMD64LEAW4, ssa.OpAMD64LEAW8:
-               o := v.Reg()
-               r := v.Args[0].Reg()
-               i := v.Args[1].Reg()
                p := s.Prog(v.Op.Asm())
-               switch v.Op {
-               case ssa.OpAMD64LEAQ1, ssa.OpAMD64LEAL1, ssa.OpAMD64LEAW1:
-                       p.From.Scale = 1
-                       if i == x86.REG_SP {
-                               r, i = i, r
-                       }
-               case ssa.OpAMD64LEAQ2, ssa.OpAMD64LEAL2, ssa.OpAMD64LEAW2:
-                       p.From.Scale = 2
-               case ssa.OpAMD64LEAQ4, ssa.OpAMD64LEAL4, ssa.OpAMD64LEAW4:
-                       p.From.Scale = 4
-               case ssa.OpAMD64LEAQ8, ssa.OpAMD64LEAL8, ssa.OpAMD64LEAW8:
-                       p.From.Scale = 8
-               }
-               p.From.Type = obj.TYPE_MEM
-               p.From.Reg = r
-               p.From.Index = i
+               memIdx(&p.From, v)
+               o := v.Reg()
                p.To.Type = obj.TYPE_REG
                p.To.Reg = o
                if v.AuxInt != 0 && v.Aux == nil {
@@ -702,25 +700,8 @@ func ssaGenValue(s *gc.SSAGenState, v *ssa.Value) {
                p.To.Reg = v.Reg()
        case ssa.OpAMD64MOVBloadidx1, ssa.OpAMD64MOVWloadidx1, ssa.OpAMD64MOVLloadidx1, ssa.OpAMD64MOVQloadidx1, ssa.OpAMD64MOVSSloadidx1, ssa.OpAMD64MOVSDloadidx1,
                ssa.OpAMD64MOVQloadidx8, ssa.OpAMD64MOVSDloadidx8, ssa.OpAMD64MOVLloadidx8, ssa.OpAMD64MOVLloadidx4, ssa.OpAMD64MOVSSloadidx4, ssa.OpAMD64MOVWloadidx2:
-               r := v.Args[0].Reg()
-               i := v.Args[1].Reg()
                p := s.Prog(v.Op.Asm())
-               p.From.Type = obj.TYPE_MEM
-               switch v.Op {
-               case ssa.OpAMD64MOVBloadidx1, ssa.OpAMD64MOVWloadidx1, ssa.OpAMD64MOVLloadidx1, ssa.OpAMD64MOVQloadidx1, ssa.OpAMD64MOVSSloadidx1, ssa.OpAMD64MOVSDloadidx1:
-                       if i == x86.REG_SP {
-                               r, i = i, r
-                       }
-                       p.From.Scale = 1
-               case ssa.OpAMD64MOVQloadidx8, ssa.OpAMD64MOVSDloadidx8, ssa.OpAMD64MOVLloadidx8:
-                       p.From.Scale = 8
-               case ssa.OpAMD64MOVLloadidx4, ssa.OpAMD64MOVSSloadidx4:
-                       p.From.Scale = 4
-               case ssa.OpAMD64MOVWloadidx2:
-                       p.From.Scale = 2
-               }
-               p.From.Reg = r
-               p.From.Index = i
+               memIdx(&p.From, v)
                gc.AddAux(&p.From, v)
                p.To.Type = obj.TYPE_REG
                p.To.Reg = v.Reg()
@@ -736,27 +717,10 @@ func ssaGenValue(s *gc.SSAGenState, v *ssa.Value) {
                gc.AddAux(&p.To, v)
        case ssa.OpAMD64MOVBstoreidx1, ssa.OpAMD64MOVWstoreidx1, ssa.OpAMD64MOVLstoreidx1, ssa.OpAMD64MOVQstoreidx1, ssa.OpAMD64MOVSSstoreidx1, ssa.OpAMD64MOVSDstoreidx1,
                ssa.OpAMD64MOVQstoreidx8, ssa.OpAMD64MOVSDstoreidx8, ssa.OpAMD64MOVLstoreidx8, ssa.OpAMD64MOVSSstoreidx4, ssa.OpAMD64MOVLstoreidx4, ssa.OpAMD64MOVWstoreidx2:
-               r := v.Args[0].Reg()
-               i := v.Args[1].Reg()
                p := s.Prog(v.Op.Asm())
                p.From.Type = obj.TYPE_REG
                p.From.Reg = v.Args[2].Reg()
-               p.To.Type = obj.TYPE_MEM
-               switch v.Op {
-               case ssa.OpAMD64MOVBstoreidx1, ssa.OpAMD64MOVWstoreidx1, ssa.OpAMD64MOVLstoreidx1, ssa.OpAMD64MOVQstoreidx1, ssa.OpAMD64MOVSSstoreidx1, ssa.OpAMD64MOVSDstoreidx1:
-                       if i == x86.REG_SP {
-                               r, i = i, r
-                       }
-                       p.To.Scale = 1
-               case ssa.OpAMD64MOVQstoreidx8, ssa.OpAMD64MOVSDstoreidx8, ssa.OpAMD64MOVLstoreidx8:
-                       p.To.Scale = 8
-               case ssa.OpAMD64MOVSSstoreidx4, ssa.OpAMD64MOVLstoreidx4:
-                       p.To.Scale = 4
-               case ssa.OpAMD64MOVWstoreidx2:
-                       p.To.Scale = 2
-               }
-               p.To.Reg = r
-               p.To.Index = i
+               memIdx(&p.To, v)
                gc.AddAux(&p.To, v)
        case ssa.OpAMD64ADDQconstmodify, ssa.OpAMD64ADDLconstmodify:
                sc := v.AuxValAndOff()
@@ -809,24 +773,7 @@ func ssaGenValue(s *gc.SSAGenState, v *ssa.Value) {
                p.From.Type = obj.TYPE_CONST
                sc := v.AuxValAndOff()
                p.From.Offset = sc.Val()
-               r := v.Args[0].Reg()
-               i := v.Args[1].Reg()
-               switch v.Op {
-               case ssa.OpAMD64MOVBstoreconstidx1, ssa.OpAMD64MOVWstoreconstidx1, ssa.OpAMD64MOVLstoreconstidx1, ssa.OpAMD64MOVQstoreconstidx1:
-                       p.To.Scale = 1
-                       if i == x86.REG_SP {
-                               r, i = i, r
-                       }
-               case ssa.OpAMD64MOVWstoreconstidx2:
-                       p.To.Scale = 2
-               case ssa.OpAMD64MOVLstoreconstidx4:
-                       p.To.Scale = 4
-               case ssa.OpAMD64MOVQstoreconstidx8:
-                       p.To.Scale = 8
-               }
-               p.To.Type = obj.TYPE_MEM
-               p.To.Reg = r
-               p.To.Index = i
+               memIdx(&p.To, v)
                gc.AddAux2(&p.To, v, sc.Off())
        case ssa.OpAMD64MOVLQSX, ssa.OpAMD64MOVWQSX, ssa.OpAMD64MOVBQSX, ssa.OpAMD64MOVLQZX, ssa.OpAMD64MOVWQZX, ssa.OpAMD64MOVBQZX,
                ssa.OpAMD64CVTTSS2SL, ssa.OpAMD64CVTTSD2SL, ssa.OpAMD64CVTTSS2SQ, ssa.OpAMD64CVTTSD2SQ,

diff --git a/src/cmd/compile/internal/ssa/gen/AMD64Ops.go b/src/cmd/compile/internal/ssa/gen/AMD64Ops.go
index c2ed0ea1d95117560e69d33ebdf8566cba1ddc46..a7880430ae61e78f3071ceba050d96ec8e524398 100644 (file)
--- a/src/cmd/compile/internal/ssa/gen/AMD64Ops.go
+++ b/src/cmd/compile/internal/ssa/gen/AMD64Ops.go
@@ -174,17 +174,17 @@ func init() {
                {name: "MOVSDload", argLength: 2, reg: fpload, asm: "MOVSD", aux: "SymOff", faultOnNilArg0: true, symEffect: "Read"}, // fp64 load
                {name: "MOVSSconst", reg: fp01, asm: "MOVSS", aux: "Float32", rematerializeable: true},                               // fp32 constant
                {name: "MOVSDconst", reg: fp01, asm: "MOVSD", aux: "Float64", rematerializeable: true},                               // fp64 constant
-               {name: "MOVSSloadidx1", argLength: 3, reg: fploadidx, asm: "MOVSS", aux: "SymOff", symEffect: "Read"},                // fp32 load indexed by i
-               {name: "MOVSSloadidx4", argLength: 3, reg: fploadidx, asm: "MOVSS", aux: "SymOff", symEffect: "Read"},                // fp32 load indexed by 4*i
-               {name: "MOVSDloadidx1", argLength: 3, reg: fploadidx, asm: "MOVSD", aux: "SymOff", symEffect: "Read"},                // fp64 load indexed by i
-               {name: "MOVSDloadidx8", argLength: 3, reg: fploadidx, asm: "MOVSD", aux: "SymOff", symEffect: "Read"},                // fp64 load indexed by 8*i
+               {name: "MOVSSloadidx1", argLength: 3, reg: fploadidx, asm: "MOVSS", scale: 1, aux: "SymOff", symEffect: "Read"},      // fp32 load indexed by i
+               {name: "MOVSSloadidx4", argLength: 3, reg: fploadidx, asm: "MOVSS", scale: 4, aux: "SymOff", symEffect: "Read"},      // fp32 load indexed by 4*i
+               {name: "MOVSDloadidx1", argLength: 3, reg: fploadidx, asm: "MOVSD", scale: 1, aux: "SymOff", symEffect: "Read"},      // fp64 load indexed by i
+               {name: "MOVSDloadidx8", argLength: 3, reg: fploadidx, asm: "MOVSD", scale: 8, aux: "SymOff", symEffect: "Read"},      // fp64 load indexed by 8*i
 
                {name: "MOVSSstore", argLength: 3, reg: fpstore, asm: "MOVSS", aux: "SymOff", faultOnNilArg0: true, symEffect: "Write"}, // fp32 store
                {name: "MOVSDstore", argLength: 3, reg: fpstore, asm: "MOVSD", aux: "SymOff", faultOnNilArg0: true, symEffect: "Write"}, // fp64 store
-               {name: "MOVSSstoreidx1", argLength: 4, reg: fpstoreidx, asm: "MOVSS", aux: "SymOff", symEffect: "Write"},                // fp32 indexed by i store
-               {name: "MOVSSstoreidx4", argLength: 4, reg: fpstoreidx, asm: "MOVSS", aux: "SymOff", symEffect: "Write"},                // fp32 indexed by 4i store
-               {name: "MOVSDstoreidx1", argLength: 4, reg: fpstoreidx, asm: "MOVSD", aux: "SymOff", symEffect: "Write"},                // fp64 indexed by i store
-               {name: "MOVSDstoreidx8", argLength: 4, reg: fpstoreidx, asm: "MOVSD", aux: "SymOff", symEffect: "Write"},                // fp64 indexed by 8i store
+               {name: "MOVSSstoreidx1", argLength: 4, reg: fpstoreidx, asm: "MOVSS", scale: 1, aux: "SymOff", symEffect: "Write"},      // fp32 indexed by i store
+               {name: "MOVSSstoreidx4", argLength: 4, reg: fpstoreidx, asm: "MOVSS", scale: 4, aux: "SymOff", symEffect: "Write"},      // fp32 indexed by 4i store
+               {name: "MOVSDstoreidx1", argLength: 4, reg: fpstoreidx, asm: "MOVSD", scale: 1, aux: "SymOff", symEffect: "Write"},      // fp64 indexed by i store
+               {name: "MOVSDstoreidx8", argLength: 4, reg: fpstoreidx, asm: "MOVSD", scale: 8, aux: "SymOff", symEffect: "Write"},      // fp64 indexed by 8i store
 
                {name: "ADDSSload", argLength: 3, reg: fp21load, asm: "ADDSS", aux: "SymOff", resultInArg0: true, faultOnNilArg1: true, symEffect: "Read"}, // fp32 arg0 + tmp, tmp loaded from arg1+auxint+aux, arg2 = mem
                {name: "ADDSDload", argLength: 3, reg: fp21load, asm: "ADDSD", aux: "SymOff", resultInArg0: true, faultOnNilArg1: true, symEffect: "Read"}, // fp64 arg0 + tmp, tmp loaded from arg1+auxint+aux, arg2 = mem
@@ -544,21 +544,21 @@ func init() {
 
                {name: "PXOR", argLength: 2, reg: fp21, asm: "PXOR", commutative: true, resultInArg0: true}, // exclusive or, applied to X regs for float negation.
 
-               {name: "LEAQ", argLength: 1, reg: gp11sb, asm: "LEAQ", aux: "SymOff", rematerializeable: true, symEffect: "Addr"}, // arg0 + auxint + offset encoded in aux
-               {name: "LEAL", argLength: 1, reg: gp11sb, asm: "LEAL", aux: "SymOff", rematerializeable: true, symEffect: "Addr"}, // arg0 + auxint + offset encoded in aux
-               {name: "LEAW", argLength: 1, reg: gp11sb, asm: "LEAW", aux: "SymOff", rematerializeable: true, symEffect: "Addr"}, // arg0 + auxint + offset encoded in aux
-               {name: "LEAQ1", argLength: 2, reg: gp21sb, asm: "LEAQ", commutative: true, aux: "SymOff", symEffect: "Addr"},      // arg0 + arg1 + auxint + aux
-               {name: "LEAL1", argLength: 2, reg: gp21sb, asm: "LEAL", commutative: true, aux: "SymOff", symEffect: "Addr"},      // arg0 + arg1 + auxint + aux
-               {name: "LEAW1", argLength: 2, reg: gp21sb, asm: "LEAW", commutative: true, aux: "SymOff", symEffect: "Addr"},      // arg0 + arg1 + auxint + aux
-               {name: "LEAQ2", argLength: 2, reg: gp21sb, asm: "LEAQ", aux: "SymOff", symEffect: "Addr"},                         // arg0 + 2*arg1 + auxint + aux
-               {name: "LEAL2", argLength: 2, reg: gp21sb, asm: "LEAL", aux: "SymOff", symEffect: "Addr"},                         // arg0 + 2*arg1 + auxint + aux
-               {name: "LEAW2", argLength: 2, reg: gp21sb, asm: "LEAW", aux: "SymOff", symEffect: "Addr"},                         // arg0 + 2*arg1 + auxint + aux
-               {name: "LEAQ4", argLength: 2, reg: gp21sb, asm: "LEAQ", aux: "SymOff", symEffect: "Addr"},                         // arg0 + 4*arg1 + auxint + aux
-               {name: "LEAL4", argLength: 2, reg: gp21sb, asm: "LEAL", aux: "SymOff", symEffect: "Addr"},                         // arg0 + 4*arg1 + auxint + aux
-               {name: "LEAW4", argLength: 2, reg: gp21sb, asm: "LEAW", aux: "SymOff", symEffect: "Addr"},                         // arg0 + 4*arg1 + auxint + aux
-               {name: "LEAQ8", argLength: 2, reg: gp21sb, asm: "LEAQ", aux: "SymOff", symEffect: "Addr"},                         // arg0 + 8*arg1 + auxint + aux
-               {name: "LEAL8", argLength: 2, reg: gp21sb, asm: "LEAL", aux: "SymOff", symEffect: "Addr"},                         // arg0 + 8*arg1 + auxint + aux
-               {name: "LEAW8", argLength: 2, reg: gp21sb, asm: "LEAW", aux: "SymOff", symEffect: "Addr"},                         // arg0 + 8*arg1 + auxint + aux
+               {name: "LEAQ", argLength: 1, reg: gp11sb, asm: "LEAQ", aux: "SymOff", rematerializeable: true, symEffect: "Addr"},      // arg0 + auxint + offset encoded in aux
+               {name: "LEAL", argLength: 1, reg: gp11sb, asm: "LEAL", aux: "SymOff", rematerializeable: true, symEffect: "Addr"},      // arg0 + auxint + offset encoded in aux
+               {name: "LEAW", argLength: 1, reg: gp11sb, asm: "LEAW", aux: "SymOff", rematerializeable: true, symEffect: "Addr"},      // arg0 + auxint + offset encoded in aux
+               {name: "LEAQ1", argLength: 2, reg: gp21sb, asm: "LEAQ", scale: 1, commutative: true, aux: "SymOff", symEffect: "Addr"}, // arg0 + arg1 + auxint + aux
+               {name: "LEAL1", argLength: 2, reg: gp21sb, asm: "LEAL", scale: 1, commutative: true, aux: "SymOff", symEffect: "Addr"}, // arg0 + arg1 + auxint + aux
+               {name: "LEAW1", argLength: 2, reg: gp21sb, asm: "LEAW", scale: 1, commutative: true, aux: "SymOff", symEffect: "Addr"}, // arg0 + arg1 + auxint + aux
+               {name: "LEAQ2", argLength: 2, reg: gp21sb, asm: "LEAQ", scale: 2, aux: "SymOff", symEffect: "Addr"},                    // arg0 + 2*arg1 + auxint + aux
+               {name: "LEAL2", argLength: 2, reg: gp21sb, asm: "LEAL", scale: 2, aux: "SymOff", symEffect: "Addr"},                    // arg0 + 2*arg1 + auxint + aux
+               {name: "LEAW2", argLength: 2, reg: gp21sb, asm: "LEAW", scale: 2, aux: "SymOff", symEffect: "Addr"},                    // arg0 + 2*arg1 + auxint + aux
+               {name: "LEAQ4", argLength: 2, reg: gp21sb, asm: "LEAQ", scale: 4, aux: "SymOff", symEffect: "Addr"},                    // arg0 + 4*arg1 + auxint + aux
+               {name: "LEAL4", argLength: 2, reg: gp21sb, asm: "LEAL", scale: 4, aux: "SymOff", symEffect: "Addr"},                    // arg0 + 4*arg1 + auxint + aux
+               {name: "LEAW4", argLength: 2, reg: gp21sb, asm: "LEAW", scale: 4, aux: "SymOff", symEffect: "Addr"},                    // arg0 + 4*arg1 + auxint + aux
+               {name: "LEAQ8", argLength: 2, reg: gp21sb, asm: "LEAQ", scale: 8, aux: "SymOff", symEffect: "Addr"},                    // arg0 + 8*arg1 + auxint + aux
+               {name: "LEAL8", argLength: 2, reg: gp21sb, asm: "LEAL", scale: 8, aux: "SymOff", symEffect: "Addr"},                    // arg0 + 8*arg1 + auxint + aux
+               {name: "LEAW8", argLength: 2, reg: gp21sb, asm: "LEAW", scale: 8, aux: "SymOff", symEffect: "Addr"},                    // arg0 + 8*arg1 + auxint + aux
                // Note: LEAx{1,2,4,8} must not have OpSB as either argument.
 
                // auxint+aux == add auxint and the offset of the symbol in aux (if any) to the effective address
@@ -577,24 +577,24 @@ func init() {
                {name: "MOVOstore", argLength: 3, reg: fpstore, asm: "MOVUPS", aux: "SymOff", typ: "Mem", faultOnNilArg0: true, symEffect: "Write"},  // store 16 bytes in arg1 to arg0+auxint+aux. arg2=mem
 
                // indexed loads/stores
-               {name: "MOVBloadidx1", argLength: 3, reg: gploadidx, commutative: true, asm: "MOVBLZX", aux: "SymOff", typ: "UInt8", symEffect: "Read"},  // load a byte from arg0+arg1+auxint+aux. arg2=mem
-               {name: "MOVWloadidx1", argLength: 3, reg: gploadidx, commutative: true, asm: "MOVWLZX", aux: "SymOff", typ: "UInt16", symEffect: "Read"}, // load 2 bytes from arg0+arg1+auxint+aux. arg2=mem
-               {name: "MOVWloadidx2", argLength: 3, reg: gploadidx, asm: "MOVWLZX", aux: "SymOff", typ: "UInt16", symEffect: "Read"},                    // load 2 bytes from arg0+2*arg1+auxint+aux. arg2=mem
-               {name: "MOVLloadidx1", argLength: 3, reg: gploadidx, commutative: true, asm: "MOVL", aux: "SymOff", typ: "UInt32", symEffect: "Read"},    // load 4 bytes from arg0+arg1+auxint+aux. arg2=mem
-               {name: "MOVLloadidx4", argLength: 3, reg: gploadidx, asm: "MOVL", aux: "SymOff", typ: "UInt32", symEffect: "Read"},                       // load 4 bytes from arg0+4*arg1+auxint+aux. arg2=mem
-               {name: "MOVLloadidx8", argLength: 3, reg: gploadidx, asm: "MOVL", aux: "SymOff", typ: "UInt32", symEffect: "Read"},                       // load 4 bytes from arg0+8*arg1+auxint+aux. arg2=mem
-               {name: "MOVQloadidx1", argLength: 3, reg: gploadidx, commutative: true, asm: "MOVQ", aux: "SymOff", typ: "UInt64", symEffect: "Read"},    // load 8 bytes from arg0+arg1+auxint+aux. arg2=mem
-               {name: "MOVQloadidx8", argLength: 3, reg: gploadidx, asm: "MOVQ", aux: "SymOff", typ: "UInt64", symEffect: "Read"},                       // load 8 bytes from arg0+8*arg1+auxint+aux. arg2=mem
+               {name: "MOVBloadidx1", argLength: 3, reg: gploadidx, commutative: true, asm: "MOVBLZX", scale: 1, aux: "SymOff", typ: "UInt8", symEffect: "Read"},  // load a byte from arg0+arg1+auxint+aux. arg2=mem
+               {name: "MOVWloadidx1", argLength: 3, reg: gploadidx, commutative: true, asm: "MOVWLZX", scale: 1, aux: "SymOff", typ: "UInt16", symEffect: "Read"}, // load 2 bytes from arg0+arg1+auxint+aux. arg2=mem
+               {name: "MOVWloadidx2", argLength: 3, reg: gploadidx, asm: "MOVWLZX", scale: 2, aux: "SymOff", typ: "UInt16", symEffect: "Read"},                    // load 2 bytes from arg0+2*arg1+auxint+aux. arg2=mem
+               {name: "MOVLloadidx1", argLength: 3, reg: gploadidx, commutative: true, asm: "MOVL", scale: 1, aux: "SymOff", typ: "UInt32", symEffect: "Read"},    // load 4 bytes from arg0+arg1+auxint+aux. arg2=mem
+               {name: "MOVLloadidx4", argLength: 3, reg: gploadidx, asm: "MOVL", scale: 4, aux: "SymOff", typ: "UInt32", symEffect: "Read"},                       // load 4 bytes from arg0+4*arg1+auxint+aux. arg2=mem
+               {name: "MOVLloadidx8", argLength: 3, reg: gploadidx, asm: "MOVL", scale: 8, aux: "SymOff", typ: "UInt32", symEffect: "Read"},                       // load 4 bytes from arg0+8*arg1+auxint+aux. arg2=mem
+               {name: "MOVQloadidx1", argLength: 3, reg: gploadidx, commutative: true, asm: "MOVQ", scale: 1, aux: "SymOff", typ: "UInt64", symEffect: "Read"},    // load 8 bytes from arg0+arg1+auxint+aux. arg2=mem
+               {name: "MOVQloadidx8", argLength: 3, reg: gploadidx, asm: "MOVQ", scale: 8, aux: "SymOff", typ: "UInt64", symEffect: "Read"},                       // load 8 bytes from arg0+8*arg1+auxint+aux. arg2=mem
                // TODO: sign-extending indexed loads
                // TODO: mark the MOVXstoreidx1 ops as commutative.  Generates too many rewrite rules at the moment.
-               {name: "MOVBstoreidx1", argLength: 4, reg: gpstoreidx, asm: "MOVB", aux: "SymOff", symEffect: "Write"}, // store byte in arg2 to arg0+arg1+auxint+aux. arg3=mem
-               {name: "MOVWstoreidx1", argLength: 4, reg: gpstoreidx, asm: "MOVW", aux: "SymOff", symEffect: "Write"}, // store 2 bytes in arg2 to arg0+arg1+auxint+aux. arg3=mem
-               {name: "MOVWstoreidx2", argLength: 4, reg: gpstoreidx, asm: "MOVW", aux: "SymOff", symEffect: "Write"}, // store 2 bytes in arg2 to arg0+2*arg1+auxint+aux. arg3=mem
-               {name: "MOVLstoreidx1", argLength: 4, reg: gpstoreidx, asm: "MOVL", aux: "SymOff", symEffect: "Write"}, // store 4 bytes in arg2 to arg0+arg1+auxint+aux. arg3=mem
-               {name: "MOVLstoreidx4", argLength: 4, reg: gpstoreidx, asm: "MOVL", aux: "SymOff", symEffect: "Write"}, // store 4 bytes in arg2 to arg0+4*arg1+auxint+aux. arg3=mem
-               {name: "MOVLstoreidx8", argLength: 4, reg: gpstoreidx, asm: "MOVL", aux: "SymOff", symEffect: "Write"}, // store 4 bytes in arg2 to arg0+8*arg1+auxint+aux. arg3=mem
-               {name: "MOVQstoreidx1", argLength: 4, reg: gpstoreidx, asm: "MOVQ", aux: "SymOff", symEffect: "Write"}, // store 8 bytes in arg2 to arg0+arg1+auxint+aux. arg3=mem
-               {name: "MOVQstoreidx8", argLength: 4, reg: gpstoreidx, asm: "MOVQ", aux: "SymOff", symEffect: "Write"}, // store 8 bytes in arg2 to arg0+8*arg1+auxint+aux. arg3=mem
+               {name: "MOVBstoreidx1", argLength: 4, reg: gpstoreidx, asm: "MOVB", scale: 1, aux: "SymOff", symEffect: "Write"}, // store byte in arg2 to arg0+arg1+auxint+aux. arg3=mem
+               {name: "MOVWstoreidx1", argLength: 4, reg: gpstoreidx, asm: "MOVW", scale: 1, aux: "SymOff", symEffect: "Write"}, // store 2 bytes in arg2 to arg0+arg1+auxint+aux. arg3=mem
+               {name: "MOVWstoreidx2", argLength: 4, reg: gpstoreidx, asm: "MOVW", scale: 2, aux: "SymOff", symEffect: "Write"}, // store 2 bytes in arg2 to arg0+2*arg1+auxint+aux. arg3=mem
+               {name: "MOVLstoreidx1", argLength: 4, reg: gpstoreidx, asm: "MOVL", scale: 1, aux: "SymOff", symEffect: "Write"}, // store 4 bytes in arg2 to arg0+arg1+auxint+aux. arg3=mem
+               {name: "MOVLstoreidx4", argLength: 4, reg: gpstoreidx, asm: "MOVL", scale: 4, aux: "SymOff", symEffect: "Write"}, // store 4 bytes in arg2 to arg0+4*arg1+auxint+aux. arg3=mem
+               {name: "MOVLstoreidx8", argLength: 4, reg: gpstoreidx, asm: "MOVL", scale: 8, aux: "SymOff", symEffect: "Write"}, // store 4 bytes in arg2 to arg0+8*arg1+auxint+aux. arg3=mem
+               {name: "MOVQstoreidx1", argLength: 4, reg: gpstoreidx, asm: "MOVQ", scale: 1, aux: "SymOff", symEffect: "Write"}, // store 8 bytes in arg2 to arg0+arg1+auxint+aux. arg3=mem
+               {name: "MOVQstoreidx8", argLength: 4, reg: gpstoreidx, asm: "MOVQ", scale: 8, aux: "SymOff", symEffect: "Write"}, // store 8 bytes in arg2 to arg0+8*arg1+auxint+aux. arg3=mem
                // TODO: add size-mismatched indexed loads, like MOVBstoreidx4.
 
                // For storeconst ops, the AuxInt field encodes both
@@ -605,13 +605,13 @@ func init() {
                {name: "MOVLstoreconst", argLength: 2, reg: gpstoreconst, asm: "MOVL", aux: "SymValAndOff", typ: "Mem", faultOnNilArg0: true, symEffect: "Write"}, // store low 4 bytes of ...
                {name: "MOVQstoreconst", argLength: 2, reg: gpstoreconst, asm: "MOVQ", aux: "SymValAndOff", typ: "Mem", faultOnNilArg0: true, symEffect: "Write"}, // store 8 bytes of ...
 
-               {name: "MOVBstoreconstidx1", argLength: 3, reg: gpstoreconstidx, asm: "MOVB", aux: "SymValAndOff", typ: "Mem", symEffect: "Write"}, // store low byte of ValAndOff(AuxInt).Val() to arg0+1*arg1+ValAndOff(AuxInt).Off()+aux.  arg2=mem
-               {name: "MOVWstoreconstidx1", argLength: 3, reg: gpstoreconstidx, asm: "MOVW", aux: "SymValAndOff", typ: "Mem", symEffect: "Write"}, // store low 2 bytes of ... arg1 ...
-               {name: "MOVWstoreconstidx2", argLength: 3, reg: gpstoreconstidx, asm: "MOVW", aux: "SymValAndOff", typ: "Mem", symEffect: "Write"}, // store low 2 bytes of ... 2*arg1 ...
-               {name: "MOVLstoreconstidx1", argLength: 3, reg: gpstoreconstidx, asm: "MOVL", aux: "SymValAndOff", typ: "Mem", symEffect: "Write"}, // store low 4 bytes of ... arg1 ...
-               {name: "MOVLstoreconstidx4", argLength: 3, reg: gpstoreconstidx, asm: "MOVL", aux: "SymValAndOff", typ: "Mem", symEffect: "Write"}, // store low 4 bytes of ... 4*arg1 ...
-               {name: "MOVQstoreconstidx1", argLength: 3, reg: gpstoreconstidx, asm: "MOVQ", aux: "SymValAndOff", typ: "Mem", symEffect: "Write"}, // store 8 bytes of ... arg1 ...
-               {name: "MOVQstoreconstidx8", argLength: 3, reg: gpstoreconstidx, asm: "MOVQ", aux: "SymValAndOff", typ: "Mem", symEffect: "Write"}, // store 8 bytes of ... 8*arg1 ...
+               {name: "MOVBstoreconstidx1", argLength: 3, reg: gpstoreconstidx, asm: "MOVB", scale: 1, aux: "SymValAndOff", typ: "Mem", symEffect: "Write"}, // store low byte of ValAndOff(AuxInt).Val() to arg0+1*arg1+ValAndOff(AuxInt).Off()+aux.  arg2=mem
+               {name: "MOVWstoreconstidx1", argLength: 3, reg: gpstoreconstidx, asm: "MOVW", scale: 1, aux: "SymValAndOff", typ: "Mem", symEffect: "Write"}, // store low 2 bytes of ... arg1 ...
+               {name: "MOVWstoreconstidx2", argLength: 3, reg: gpstoreconstidx, asm: "MOVW", scale: 2, aux: "SymValAndOff", typ: "Mem", symEffect: "Write"}, // store low 2 bytes of ... 2*arg1 ...
+               {name: "MOVLstoreconstidx1", argLength: 3, reg: gpstoreconstidx, asm: "MOVL", scale: 1, aux: "SymValAndOff", typ: "Mem", symEffect: "Write"}, // store low 4 bytes of ... arg1 ...
+               {name: "MOVLstoreconstidx4", argLength: 3, reg: gpstoreconstidx, asm: "MOVL", scale: 4, aux: "SymValAndOff", typ: "Mem", symEffect: "Write"}, // store low 4 bytes of ... 4*arg1 ...
+               {name: "MOVQstoreconstidx1", argLength: 3, reg: gpstoreconstidx, asm: "MOVQ", scale: 1, aux: "SymValAndOff", typ: "Mem", symEffect: "Write"}, // store 8 bytes of ... arg1 ...
+               {name: "MOVQstoreconstidx8", argLength: 3, reg: gpstoreconstidx, asm: "MOVQ", scale: 8, aux: "SymValAndOff", typ: "Mem", symEffect: "Write"}, // store 8 bytes of ... 8*arg1 ...
 
                // arg0 = pointer to start of memory to zero
                // arg1 = value to store (will always be zero)

diff --git a/src/cmd/compile/internal/ssa/gen/main.go b/src/cmd/compile/internal/ssa/gen/main.go
index f7195bf536305b47056499358796d221e18f296c..0903f77dbbadff25fd914dd43fb12ab3a0fdfe07 100644 (file)
--- a/src/cmd/compile/internal/ssa/gen/main.go
+++ b/src/cmd/compile/internal/ssa/gen/main.go
@@ -56,6 +56,7 @@ type opData struct {
        hasSideEffects    bool   // for "reasons", not to be eliminated.  E.g., atomic store, #19182.
        zeroWidth         bool   // op never translates into any machine code. example: copy, which may sometimes translate to machine code, is not zero-width.
        symEffect         string // effect this op has on symbol in aux
+       scale             uint8  // amd64/386 indexed load scale
 }
 
 type blockData struct {
@@ -245,6 +246,9 @@ func genOp() {
                        if v.asm != "" {
                                fmt.Fprintf(w, "asm: %s.A%s,\n", pkg, v.asm)
                        }
+                       if v.scale != 0 {
+                               fmt.Fprintf(w, "scale: %d,\n", v.scale)
+                       }
                        fmt.Fprintln(w, "reg:regInfo{")
 
                        // Compute input allocation order. We allocate from the
@@ -291,6 +295,7 @@ func genOp() {
        fmt.Fprintln(w, "}")
 
        fmt.Fprintln(w, "func (o Op) Asm() obj.As {return opcodeTable[o].asm}")
+       fmt.Fprintln(w, "func (o Op) Scale() int16 {return int16(opcodeTable[o].scale)}")
 
        // generate op string method
        fmt.Fprintln(w, "func (o Op) String() string {return opcodeTable[o].name }")

diff --git a/src/cmd/compile/internal/ssa/op.go b/src/cmd/compile/internal/ssa/op.go
index 43f5c59591a0000042651fa0ec50157fcda6236d..a3cebce43bf21262324bca657e14f80e5b4063e2 100644 (file)
--- a/src/cmd/compile/internal/ssa/op.go
+++ b/src/cmd/compile/internal/ssa/op.go
@@ -37,6 +37,7 @@ type opInfo struct {
        hasSideEffects    bool      // for "reasons", not to be eliminated.  E.g., atomic store, #19182.
        zeroWidth         bool      // op never translates into any machine code. example: copy, which may sometimes translate to machine code, is not zero-width.
        symEffect         SymEffect // effect this op has on symbol in aux
+       scale             uint8     // amd64/386 indexed load scale
 }
 
 type inputInfo struct {

diff --git a/src/cmd/compile/internal/ssa/opGen.go b/src/cmd/compile/internal/ssa/opGen.go
index 9222f52b58bca43e2c9c29b83f3d4fd98a57e8ff..ae1a2b47e6b8c27b06f75265f63709c1a2f6537f 100644 (file)
--- a/src/cmd/compile/internal/ssa/opGen.go
+++ b/src/cmd/compile/internal/ssa/opGen.go
@@ -5847,6 +5847,7 @@ var opcodeTable = [...]opInfo{
                argLen:    3,
                symEffect: SymRead,
                asm:       x86.AMOVSS,
+               scale:     1,
                reg: regInfo{
                        inputs: []inputInfo{
                                {1, 65535},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
@@ -5863,6 +5864,7 @@ var opcodeTable = [...]opInfo{
                argLen:    3,
                symEffect: SymRead,
                asm:       x86.AMOVSS,
+               scale:     4,
                reg: regInfo{
                        inputs: []inputInfo{
                                {1, 65535},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
@@ -5879,6 +5881,7 @@ var opcodeTable = [...]opInfo{
                argLen:    3,
                symEffect: SymRead,
                asm:       x86.AMOVSD,
+               scale:     1,
                reg: regInfo{
                        inputs: []inputInfo{
                                {1, 65535},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
@@ -5895,6 +5898,7 @@ var opcodeTable = [...]opInfo{
                argLen:    3,
                symEffect: SymRead,
                asm:       x86.AMOVSD,
+               scale:     8,
                reg: regInfo{
                        inputs: []inputInfo{
                                {1, 65535},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
@@ -5939,6 +5943,7 @@ var opcodeTable = [...]opInfo{
                argLen:    4,
                symEffect: SymWrite,
                asm:       x86.AMOVSS,
+               scale:     1,
                reg: regInfo{
                        inputs: []inputInfo{
                                {1, 65535},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
@@ -5953,6 +5958,7 @@ var opcodeTable = [...]opInfo{
                argLen:    4,
                symEffect: SymWrite,
                asm:       x86.AMOVSS,
+               scale:     4,
                reg: regInfo{
                        inputs: []inputInfo{
                                {1, 65535},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
@@ -5967,6 +5973,7 @@ var opcodeTable = [...]opInfo{
                argLen:    4,
                symEffect: SymWrite,
                asm:       x86.AMOVSD,
+               scale:     1,
                reg: regInfo{
                        inputs: []inputInfo{
                                {1, 65535},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
@@ -5981,6 +5988,7 @@ var opcodeTable = [...]opInfo{
                argLen:    4,
                symEffect: SymWrite,
                asm:       x86.AMOVSD,
+               scale:     8,
                reg: regInfo{
                        inputs: []inputInfo{
                                {1, 65535},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
@@ -10112,6 +10120,7 @@ var opcodeTable = [...]opInfo{
                commutative: true,
                symEffect:   SymAddr,
                asm:         x86.ALEAQ,
+               scale:       1,
                reg: regInfo{
                        inputs: []inputInfo{
                                {1, 65535},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
@@ -10129,6 +10138,7 @@ var opcodeTable = [...]opInfo{
                commutative: true,
                symEffect:   SymAddr,
                asm:         x86.ALEAL,
+               scale:       1,
                reg: regInfo{
                        inputs: []inputInfo{
                                {1, 65535},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
@@ -10146,6 +10156,7 @@ var opcodeTable = [...]opInfo{
                commutative: true,
                symEffect:   SymAddr,
                asm:         x86.ALEAW,
+               scale:       1,
                reg: regInfo{
                        inputs: []inputInfo{
                                {1, 65535},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
@@ -10162,6 +10173,7 @@ var opcodeTable = [...]opInfo{
                argLen:    2,
                symEffect: SymAddr,
                asm:       x86.ALEAQ,
+               scale:     2,
                reg: regInfo{
                        inputs: []inputInfo{
                                {1, 65535},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
@@ -10178,6 +10190,7 @@ var opcodeTable = [...]opInfo{
                argLen:    2,
                symEffect: SymAddr,
                asm:       x86.ALEAL,
+               scale:     2,
                reg: regInfo{
                        inputs: []inputInfo{
                                {1, 65535},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
@@ -10194,6 +10207,7 @@ var opcodeTable = [...]opInfo{
                argLen:    2,
                symEffect: SymAddr,
                asm:       x86.ALEAW,
+               scale:     2,
                reg: regInfo{
                        inputs: []inputInfo{
                                {1, 65535},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
@@ -10210,6 +10224,7 @@ var opcodeTable = [...]opInfo{
                argLen:    2,
                symEffect: SymAddr,
                asm:       x86.ALEAQ,
+               scale:     4,
                reg: regInfo{
                        inputs: []inputInfo{
                                {1, 65535},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
@@ -10226,6 +10241,7 @@ var opcodeTable = [...]opInfo{
                argLen:    2,
                symEffect: SymAddr,
                asm:       x86.ALEAL,
+               scale:     4,
                reg: regInfo{
                        inputs: []inputInfo{
                                {1, 65535},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
@@ -10242,6 +10258,7 @@ var opcodeTable = [...]opInfo{
                argLen:    2,
                symEffect: SymAddr,
                asm:       x86.ALEAW,
+               scale:     4,
                reg: regInfo{
                        inputs: []inputInfo{
                                {1, 65535},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
@@ -10258,6 +10275,7 @@ var opcodeTable = [...]opInfo{
                argLen:    2,
                symEffect: SymAddr,
                asm:       x86.ALEAQ,
+               scale:     8,
                reg: regInfo{
                        inputs: []inputInfo{
                                {1, 65535},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
@@ -10274,6 +10292,7 @@ var opcodeTable = [...]opInfo{
                argLen:    2,
                symEffect: SymAddr,
                asm:       x86.ALEAL,
+               scale:     8,
                reg: regInfo{
                        inputs: []inputInfo{
                                {1, 65535},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
@@ -10290,6 +10309,7 @@ var opcodeTable = [...]opInfo{
                argLen:    2,
                symEffect: SymAddr,
                asm:       x86.ALEAW,
+               scale:     8,
                reg: regInfo{
                        inputs: []inputInfo{
                                {1, 65535},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
@@ -10505,6 +10525,7 @@ var opcodeTable = [...]opInfo{
                commutative: true,
                symEffect:   SymRead,
                asm:         x86.AMOVBLZX,
+               scale:       1,
                reg: regInfo{
                        inputs: []inputInfo{
                                {1, 65535},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
@@ -10522,6 +10543,7 @@ var opcodeTable = [...]opInfo{
                commutative: true,
                symEffect:   SymRead,
                asm:         x86.AMOVWLZX,
+               scale:       1,
                reg: regInfo{
                        inputs: []inputInfo{
                                {1, 65535},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
@@ -10538,6 +10560,7 @@ var opcodeTable = [...]opInfo{
                argLen:    3,
                symEffect: SymRead,
                asm:       x86.AMOVWLZX,
+               scale:     2,
                reg: regInfo{
                        inputs: []inputInfo{
                                {1, 65535},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
@@ -10555,6 +10578,7 @@ var opcodeTable = [...]opInfo{
                commutative: true,
                symEffect:   SymRead,
                asm:         x86.AMOVL,
+               scale:       1,
                reg: regInfo{
                        inputs: []inputInfo{
                                {1, 65535},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
@@ -10571,6 +10595,7 @@ var opcodeTable = [...]opInfo{
                argLen:    3,
                symEffect: SymRead,
                asm:       x86.AMOVL,
+               scale:     4,
                reg: regInfo{
                        inputs: []inputInfo{
                                {1, 65535},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
@@ -10587,6 +10612,7 @@ var opcodeTable = [...]opInfo{
                argLen:    3,
                symEffect: SymRead,
                asm:       x86.AMOVL,
+               scale:     8,
                reg: regInfo{
                        inputs: []inputInfo{
                                {1, 65535},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
@@ -10604,6 +10630,7 @@ var opcodeTable = [...]opInfo{
                commutative: true,
                symEffect:   SymRead,
                asm:         x86.AMOVQ,
+               scale:       1,
                reg: regInfo{
                        inputs: []inputInfo{
                                {1, 65535},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
@@ -10620,6 +10647,7 @@ var opcodeTable = [...]opInfo{
                argLen:    3,
                symEffect: SymRead,
                asm:       x86.AMOVQ,
+               scale:     8,
                reg: regInfo{
                        inputs: []inputInfo{
                                {1, 65535},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
@@ -10636,6 +10664,7 @@ var opcodeTable = [...]opInfo{
                argLen:    4,
                symEffect: SymWrite,
                asm:       x86.AMOVB,
+               scale:     1,
                reg: regInfo{
                        inputs: []inputInfo{
                                {1, 65535},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
@@ -10650,6 +10679,7 @@ var opcodeTable = [...]opInfo{
                argLen:    4,
                symEffect: SymWrite,
                asm:       x86.AMOVW,
+               scale:     1,
                reg: regInfo{
                        inputs: []inputInfo{
                                {1, 65535},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
@@ -10664,6 +10694,7 @@ var opcodeTable = [...]opInfo{
                argLen:    4,
                symEffect: SymWrite,
                asm:       x86.AMOVW,
+               scale:     2,
                reg: regInfo{
                        inputs: []inputInfo{
                                {1, 65535},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
@@ -10678,6 +10709,7 @@ var opcodeTable = [...]opInfo{
                argLen:    4,
                symEffect: SymWrite,
                asm:       x86.AMOVL,
+               scale:     1,
                reg: regInfo{
                        inputs: []inputInfo{
                                {1, 65535},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
@@ -10692,6 +10724,7 @@ var opcodeTable = [...]opInfo{
                argLen:    4,
                symEffect: SymWrite,
                asm:       x86.AMOVL,
+               scale:     4,
                reg: regInfo{
                        inputs: []inputInfo{
                                {1, 65535},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
@@ -10706,6 +10739,7 @@ var opcodeTable = [...]opInfo{
                argLen:    4,
                symEffect: SymWrite,
                asm:       x86.AMOVL,
+               scale:     8,
                reg: regInfo{
                        inputs: []inputInfo{
                                {1, 65535},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
@@ -10720,6 +10754,7 @@ var opcodeTable = [...]opInfo{
                argLen:    4,
                symEffect: SymWrite,
                asm:       x86.AMOVQ,
+               scale:     1,
                reg: regInfo{
                        inputs: []inputInfo{
                                {1, 65535},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
@@ -10734,6 +10769,7 @@ var opcodeTable = [...]opInfo{
                argLen:    4,
                symEffect: SymWrite,
                asm:       x86.AMOVQ,
+               scale:     8,
                reg: regInfo{
                        inputs: []inputInfo{
                                {1, 65535},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
@@ -10800,6 +10836,7 @@ var opcodeTable = [...]opInfo{
                argLen:    3,
                symEffect: SymWrite,
                asm:       x86.AMOVB,
+               scale:     1,
                reg: regInfo{
                        inputs: []inputInfo{
                                {1, 65535},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
@@ -10813,6 +10850,7 @@ var opcodeTable = [...]opInfo{
                argLen:    3,
                symEffect: SymWrite,
                asm:       x86.AMOVW,
+               scale:     1,
                reg: regInfo{
                        inputs: []inputInfo{
                                {1, 65535},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
@@ -10826,6 +10864,7 @@ var opcodeTable = [...]opInfo{
                argLen:    3,
                symEffect: SymWrite,
                asm:       x86.AMOVW,
+               scale:     2,
                reg: regInfo{
                        inputs: []inputInfo{
                                {1, 65535},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
@@ -10839,6 +10878,7 @@ var opcodeTable = [...]opInfo{
                argLen:    3,
                symEffect: SymWrite,
                asm:       x86.AMOVL,
+               scale:     1,
                reg: regInfo{
                        inputs: []inputInfo{
                                {1, 65535},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
@@ -10852,6 +10892,7 @@ var opcodeTable = [...]opInfo{
                argLen:    3,
                symEffect: SymWrite,
                asm:       x86.AMOVL,
+               scale:     4,
                reg: regInfo{
                        inputs: []inputInfo{
                                {1, 65535},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
@@ -10865,6 +10906,7 @@ var opcodeTable = [...]opInfo{
                argLen:    3,
                symEffect: SymWrite,
                asm:       x86.AMOVQ,
+               scale:     1,
                reg: regInfo{
                        inputs: []inputInfo{
                                {1, 65535},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
@@ -10878,6 +10920,7 @@ var opcodeTable = [...]opInfo{
                argLen:    3,
                symEffect: SymWrite,
                asm:       x86.AMOVQ,
+               scale:     8,
                reg: regInfo{
                        inputs: []inputInfo{
                                {1, 65535},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
@@ -30122,6 +30165,7 @@ var opcodeTable = [...]opInfo{
 }
 
 func (o Op) Asm() obj.As          { return opcodeTable[o].asm }
+func (o Op) Scale() int16         { return int16(opcodeTable[o].scale) }
 func (o Op) String() string       { return opcodeTable[o].name }
 func (o Op) UsesScratch() bool    { return opcodeTable[o].usesScratch }
 func (o Op) SymEffect() SymEffect { return opcodeTable[o].symEffect }