cmd/internal/obj/riscv: require memory targets for load and store instructions

This allows for `LD 4(X5), X6' rather than `LD $4, X5, X6'. Similar for other
load and store instructions. It is worth noting that none of these are likely
to be used directly once the MOV pseudo-instructions are implemented.

Updates #27532

Change-Id: Ie043c2dedd2cdaceb258b27976cfb3f74aa1cc1d
Reviewed-on: https://go-review.googlesource.com/c/go/+/196842
Reviewed-by: Cherry Zhang <cherryyz@google.com>
Run-TryBot: Cherry Zhang <cherryyz@google.com>
TryBot-Result: Gobot Gobot <gobot@golang.org>

diff --git a/src/cmd/asm/internal/asm/testdata/riscvenc.s b/src/cmd/asm/internal/asm/testdata/riscvenc.s
index 11fe827ec6f60766a6e7ac9f29b3afce4dcabcf4..f5cb10724c083f0129e8df61142936f4ea9b00c8 100644 (file)
--- a/src/cmd/asm/internal/asm/testdata/riscvenc.s
+++ b/src/cmd/asm/internal/asm/testdata/riscvenc.s
@@ -100,25 +100,25 @@ start:
        BGEU    X5, X6, start   // BGEU X5, X6, 2       // e3f662ee
 
        // 2.6: Load and Store Instructions
-       LW      $0, X5, X6                              // 03a30200
-       LW      $4, X5, X6                              // 03a34200
-       LWU     $0, X5, X6                              // 03e30200
-       LWU     $4, X5, X6                              // 03e34200
-       LH      $0, X5, X6                              // 03930200
-       LH      $4, X5, X6                              // 03934200
-       LHU     $0, X5, X6                              // 03d30200
-       LHU     $4, X5, X6                              // 03d34200
-       LB      $0, X5, X6                              // 03830200
-       LB      $4, X5, X6                              // 03834200
-       LBU     $0, X5, X6                              // 03c30200
-       LBU     $4, X5, X6                              // 03c34200
-
-       SW      $0, X5, X6                              // 23205300
-       SW      $4, X5, X6                              // 23225300
-       SH      $0, X5, X6                              // 23105300
-       SH      $4, X5, X6                              // 23125300
-       SB      $0, X5, X6                              // 23005300
-       SB      $4, X5, X6                              // 23025300
+       LW      (X5), X6                                // 03a30200
+       LW      4(X5), X6                               // 03a34200
+       LWU     (X5), X6                                // 03e30200
+       LWU     4(X5), X6                               // 03e34200
+       LH      (X5), X6                                // 03930200
+       LH      4(X5), X6                               // 03934200
+       LHU     (X5), X6                                // 03d30200
+       LHU     4(X5), X6                               // 03d34200
+       LB      (X5), X6                                // 03830200
+       LB      4(X5), X6                               // 03834200
+       LBU     (X5), X6                                // 03c30200
+       LBU     4(X5), X6                               // 03c34200
+
+       SW      X5, (X6)                                // 23205300
+       SW      X5, 4(X6)                               // 23225300
+       SH      X5, (X6)                                // 23105300
+       SH      X5, 4(X6)                               // 23125300
+       SB      X5, (X6)                                // 23005300
+       SB      X5, 4(X6)                               // 23025300
 
        // 5.2: Integer Computational Instructions (RV64I)
        ADDIW   $1, X5, X6                              // 1b831200
@@ -132,10 +132,10 @@ start:
        SRAW    X5, X6, X7                              // bb535340
 
        // 5.3: Load and Store Instructions (RV64I)
-       LD      $0, X5, X6                              // 03b30200
-       LD      $4, X5, X6                              // 03b34200
-       SD      $0, X5, X6                              // 23305300
-       SD      $4, X5, X6                              // 23325300
+       LD      (X5), X6                                // 03b30200
+       LD      4(X5), X6                               // 03b34200
+       SD      X5, (X6)                                // 23305300
+       SD      X5, 4(X6)                               // 23325300
 
        // 7.1: Multiplication Operations
        MUL     X5, X6, X7                              // b3035302
@@ -158,10 +158,10 @@ start:
        RDINSTRET       X5                              // f32220c0
 
        // 11.5: Single-Precision Load and Store Instructions
-       FLW     $0, X5, F0                              // 07a00200
-       FLW     $4, X5, F0                              // 07a04200
-       FSW     $0, F0, X5                              // 27a00200
-       FSW     $4, F0, X5                              // 27a20200
+       FLW     (X5), F0                                // 07a00200
+       FLW     4(X5), F0                               // 07a04200
+       FSW     F0, (X5)                                // 27a00200
+       FSW     F0, 4(X5)                               // 27a20200
 
        // 11.6: Single-Precision Floating-Point Computational Instructions
        FADDS   F1, F0, F2                              // 53011000
@@ -195,10 +195,10 @@ start:
        FLES    F0, F1, X7                              // d38300a0
 
        // 12.3: Double-Precision Load and Store Instructions
-       FLD     $0, X5, F0                              // 07b00200
-       FLD     $4, X5, F0                              // 07b04200
-       FSD     $0, F0, X5                              // 27b00200
-       FSD     $4, F0, X5                              // 27b20200
+       FLD     (X5), F0                                // 07b00200
+       FLD     4(X5), F0                               // 07b04200
+       FSD     F0, (X5)                                // 27b00200
+       FSD     F0, 4(X5)                               // 27b20200
 
        // 12.4: Double-Precision Floating-Point Computational Instructions
        FADDD   F1, F0, F2                              // 53011002

diff --git a/src/cmd/internal/obj/riscv/obj.go b/src/cmd/internal/obj/riscv/obj.go
index 1930bf9313275ee1160b166a67143aaffce03da2..31852a3a50dc33fcd14947db5494f12171a4affe 100644 (file)
--- a/src/cmd/internal/obj/riscv/obj.go
+++ b/src/cmd/internal/obj/riscv/obj.go
@@ -43,10 +43,7 @@ func lowerJALR(p *obj.Prog) {
        // target register in Reg, and the offset in From.
        p.Reg = p.To.Reg
        p.From, p.To = p.To, p.From
-
-       // Reset Reg so the string looks correct.
-       p.From.Type = obj.TYPE_CONST
-       p.From.Reg = obj.REG_NONE
+       p.From.Type, p.From.Reg = obj.TYPE_CONST, obj.REG_NONE
 }
 
 // progedit is called individually for each *obj.Prog. It normalizes instruction
@@ -88,6 +85,27 @@ func progedit(ctxt *obj.Link, p *obj.Prog, newprog obj.ProgAlloc) {
        }
 
        switch p.As {
+       case ALW, ALWU, ALH, ALHU, ALB, ALBU, ALD, AFLW, AFLD:
+               switch p.From.Type {
+               case obj.TYPE_MEM:
+                       // Convert loads from memory/addresses to ternary form.
+                       p.Reg = p.From.Reg
+                       p.From.Type, p.From.Reg = obj.TYPE_CONST, obj.REG_NONE
+               default:
+                       p.Ctxt.Diag("%v\tmemory required for source", p)
+               }
+
+       case ASW, ASH, ASB, ASD, AFSW, AFSD:
+               switch p.To.Type {
+               case obj.TYPE_MEM:
+                       // Convert stores to memory/addresses to ternary form.
+                       p.Reg = p.From.Reg
+                       p.From.Type, p.From.Offset, p.From.Reg = obj.TYPE_CONST, p.To.Offset, obj.REG_NONE
+                       p.To.Type, p.To.Offset = obj.TYPE_REG, 0
+               default:
+                       p.Ctxt.Diag("%v\tmemory required for destination", p)
+               }
+
        case AJALR:
                lowerJALR(p)