if ctxt.Arch.PtrSize != 4 {
panic("unexpected pointer size")
}
- return ID(word >> 16), ID(word)
+ return ID(word >> 16), ID(int16(word))
}
// Append a pointer-sized uint to buf.
FREGTMP = REG_F15
)
+// http://infocenter.arm.com/help/topic/com.arm.doc.ihi0040b/IHI0040B_aadwarf.pdf
+var ARMDWARFRegisters = map[int16]int16{}
+
+func init() {
+ // f assigns dwarfregisters[from:to] = (base):(step*(to-from)+base)
+ f := func(from, to, base, step int16) {
+ for r := int16(from); r <= to; r++ {
+ ARMDWARFRegisters[r] = step*(r-from) + base
+ }
+ }
+ f(REG_R0, REG_R15, 0, 1)
+ f(REG_F0, REG_F15, 64, 2) // Use d0 through D15, aka S0, S2, ..., S30
+}
+
const (
C_NONE = iota
C_REG
}
var Linkarm = obj.LinkArch{
- Arch: sys.ArchARM,
- Init: buildop,
- Preprocess: preprocess,
- Assemble: span5,
- Progedit: progedit,
- UnaryDst: unaryDst,
+ Arch: sys.ArchARM,
+ Init: buildop,
+ Preprocess: preprocess,
+ Assemble: span5,
+ Progedit: progedit,
+ UnaryDst: unaryDst,
+ DWARFRegisters: ARMDWARFRegisters,
}
FREGRET = REG_F0
)
+// https://llvm.org/svn/llvm-project/llvm/trunk/lib/Target/Mips/MipsRegisterInfo.td search for DwarfRegNum
+// https://gcc.gnu.org/viewcvs/gcc/trunk/gcc/config/mips/mips.c?view=co&revision=258099&content-type=text%2Fplain search for mips_dwarf_regno
+// For now, this is adequate for both 32 and 64 bit.
+var MIPSDWARFRegisters = map[int16]int16{}
+
+func init() {
+ // f assigns dwarfregisters[from:to] = (base):(to-from+base)
+ f := func(from, to, base int16) {
+ for r := int16(from); r <= to; r++ {
+ MIPSDWARFRegisters[r] = (r - from) + base
+ }
+ }
+ f(REG_R0, REG_R31, 0)
+ f(REG_F0, REG_F31, 32) // For 32-bit MIPS, compiler only uses even numbered registers -- see cmd/compile/internal/ssa/gen/MIPSOps.go
+ MIPSDWARFRegisters[REG_HI] = 64
+ MIPSDWARFRegisters[REG_LO] = 65
+}
+
const (
BIG = 32766
)
}
var Linkmips64 = obj.LinkArch{
- Arch: sys.ArchMIPS64,
- Init: buildop,
- Preprocess: preprocess,
- Assemble: span0,
- Progedit: progedit,
+ Arch: sys.ArchMIPS64,
+ Init: buildop,
+ Preprocess: preprocess,
+ Assemble: span0,
+ Progedit: progedit,
+ DWARFRegisters: MIPSDWARFRegisters,
}
var Linkmips64le = obj.LinkArch{
- Arch: sys.ArchMIPS64LE,
- Init: buildop,
- Preprocess: preprocess,
- Assemble: span0,
- Progedit: progedit,
+ Arch: sys.ArchMIPS64LE,
+ Init: buildop,
+ Preprocess: preprocess,
+ Assemble: span0,
+ Progedit: progedit,
+ DWARFRegisters: MIPSDWARFRegisters,
}
var Linkmips = obj.LinkArch{
- Arch: sys.ArchMIPS,
- Init: buildop,
- Preprocess: preprocess,
- Assemble: span0,
- Progedit: progedit,
+ Arch: sys.ArchMIPS,
+ Init: buildop,
+ Preprocess: preprocess,
+ Assemble: span0,
+ Progedit: progedit,
+ DWARFRegisters: MIPSDWARFRegisters,
}
var Linkmipsle = obj.LinkArch{
- Arch: sys.ArchMIPSLE,
- Init: buildop,
- Preprocess: preprocess,
- Assemble: span0,
- Progedit: progedit,
+ Arch: sys.ArchMIPSLE,
+ Init: buildop,
+ Preprocess: preprocess,
+ Assemble: span0,
+ Progedit: progedit,
+ DWARFRegisters: MIPSDWARFRegisters,
}
FREGEXT = REG_F26 /* first external register */
)
+// OpenPOWER ABI for Linux Supplement Power Architecture 64-Bit ELF V2 ABI
+// https://openpowerfoundation.org/?resource_lib=64-bit-elf-v2-abi-specification-power-architecture
+var PPC64DWARFRegisters = map[int16]int16{}
+
+func init() {
+ // f assigns dwarfregister[from:to] = (base):(to-from+base)
+ f := func(from, to, base int16) {
+ for r := int16(from); r <= to; r++ {
+ PPC64DWARFRegisters[r] = r - from + base
+ }
+ }
+ f(REG_R0, REG_R31, 0)
+ f(REG_F0, REG_F31, 32)
+ f(REG_V0, REG_V31, 77)
+ f(REG_CR0, REG_CR7, 68)
+
+ f(REG_VS0, REG_VS31, 32) // overlaps F0-F31
+ f(REG_VS32, REG_VS63, 77) // overlaps V0-V31
+ PPC64DWARFRegisters[REG_LR] = 65
+ PPC64DWARFRegisters[REG_CTR] = 66
+ PPC64DWARFRegisters[REG_XER] = 76
+}
+
/*
* GENERAL:
*
}
var Linkppc64 = obj.LinkArch{
- Arch: sys.ArchPPC64,
- Init: buildop,
- Preprocess: preprocess,
- Assemble: span9,
- Progedit: progedit,
+ Arch: sys.ArchPPC64,
+ Init: buildop,
+ Preprocess: preprocess,
+ Assemble: span9,
+ Progedit: progedit,
+ DWARFRegisters: PPC64DWARFRegisters,
}
var Linkppc64le = obj.LinkArch{
- Arch: sys.ArchPPC64LE,
- Init: buildop,
- Preprocess: preprocess,
- Assemble: span9,
- Progedit: progedit,
+ Arch: sys.ArchPPC64LE,
+ Init: buildop,
+ Preprocess: preprocess,
+ Assemble: span9,
+ Progedit: progedit,
+ DWARFRegisters: PPC64DWARFRegisters,
}
REGSP = REG_R15 // stack pointer
)
+// LINUX for zSeries ELF Application Binary Interface Supplement
+// http://refspecs.linuxfoundation.org/ELF/zSeries/lzsabi0_zSeries/x1472.html
+var S390XDWARFRegisters = map[int16]int16{}
+
+func init() {
+ // f assigns dwarfregisters[from:to by step] = (base):((to-from)/step+base)
+ f := func(from, step, to, base int16) {
+ for r := int16(from); r <= to; r += step {
+ S390XDWARFRegisters[r] = (r-from)/step + base
+ }
+ }
+ f(REG_R0, 1, REG_R15, 0)
+
+ f(REG_F0, 2, REG_F6, 16)
+ f(REG_F1, 2, REG_F7, 20)
+ f(REG_F8, 2, REG_F14, 24)
+ f(REG_F9, 2, REG_F15, 28)
+
+ f(REG_V0, 2, REG_V6, 16) // V0:15 aliased to F0:15
+ f(REG_V1, 2, REG_V7, 20) // TODO what about V16:31?
+ f(REG_V8, 2, REG_V14, 24)
+ f(REG_V9, 2, REG_V15, 28)
+
+ f(REG_AR0, 1, REG_AR15, 48)
+}
+
const (
BIG = 32768 - 8
DISP12 = 4096
}
var Links390x = obj.LinkArch{
- Arch: sys.ArchS390X,
- Init: buildop,
- Preprocess: preprocess,
- Assemble: spanz,
- Progedit: progedit,
- UnaryDst: unaryDst,
+ Arch: sys.ArchS390X,
+ Init: buildop,
+ Preprocess: preprocess,
+ Assemble: spanz,
+ Progedit: progedit,
+ UnaryDst: unaryDst,
+ DWARFRegisters: S390XDWARFRegisters,
}