internal/cpu, runtime: make linux/loong64 HWCAP data available

This can be used to toggle runtime usages of ISA extensions as such
usages appear.

Only the CRC32 bit is exposed for now, as the others are not going to be
utilized in the standard library for a while.

Change-Id: I774032ca84dc8bcf1c9f17558917315af07c7314
Reviewed-on: https://go-review.googlesource.com/c/go/+/482416
Reviewed-by: Ian Lance Taylor <iant@google.com>
Reviewed-by: xiaodong liu <teaofmoli@gmail.com>
LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com>
Reviewed-by: Dmitri Shuralyov <dmitshur@google.com>
Reviewed-by: abner chenc <chenguoqi@loongson.cn>

diff --git a/src/internal/cpu/cpu.go b/src/internal/cpu/cpu.go
index 7174076c5e43c4bd4a6a211e2b35ccab765fe3a3..d6437a566ba23e52928b19c41951919db8da6d58 100644 (file)
--- a/src/internal/cpu/cpu.go
+++ b/src/internal/cpu/cpu.go
@@ -78,6 +78,14 @@ var ARM64 struct {
        _          CacheLinePad
 }
 
+// The booleans in Loong64 contain the correspondingly named cpu feature bit.
+// The struct is padded to avoid false sharing.
+var Loong64 struct {
+       _        CacheLinePad
+       HasCRC32 bool
+       _        CacheLinePad
+}
+
 var MIPS64X struct {
        _      CacheLinePad
        HasMSA bool // MIPS SIMD architecture

diff --git a/src/internal/cpu/cpu_loong64.go b/src/internal/cpu/cpu_loong64.go
index 1c90c24fe318d9e1b902038500468751773930c5..c4709cc158974afde185914746d4c3eca2c21693 100644 (file)
--- a/src/internal/cpu/cpu_loong64.go
+++ b/src/internal/cpu/cpu_loong64.go
@@ -10,4 +10,10 @@ package cpu
 // We choose 64 because Loongson 3A5000 the L1 Dcache is 4-way 256-line 64-byte-per-line.
 const CacheLinePadSize = 64
 
-func doinit() {}
+func doinit() {
+       options = []option{
+               {Name: "crc32", Feature: &Loong64.HasCRC32},
+       }
+
+       osInit()
+}

diff --git a/src/internal/cpu/cpu_loong64_hwcap.go b/src/internal/cpu/cpu_loong64_hwcap.go
new file mode 100644 (file)
index 0000000..b55fde6
--- /dev/null
+++ b/src/internal/cpu/cpu_loong64_hwcap.go
@@ -0,0 +1,30 @@
+// Copyright 2023 The Go Authors. All rights reserved.
+// Use of this source code is governed by a BSD-style
+// license that can be found in the LICENSE file.
+
+//go:build loong64 && linux
+
+package cpu
+
+// This is initialized by archauxv and should not be changed after it is
+// initialized.
+var HWCap uint
+
+// HWCAP bits. These are exposed by the Linux kernel.
+const (
+       hwcap_LOONGARCH_CRC32 = 1 << 6
+)
+
+func hwcapInit() {
+       // It is not taken from CPUCFG data regardless of availability of
+       // CPUCFG, because the CPUCFG data only reflects capabilities of the
+       // hardware, but not kernel support.
+       //
+       // As of 2023, we do not know for sure if the CPUCFG data can be
+       // patched in software, nor does any known LoongArch kernel do that.
+       Loong64.HasCRC32 = isSet(HWCap, hwcap_LOONGARCH_CRC32)
+}
+
+func isSet(hwc uint, value uint) bool {
+       return hwc&value != 0
+}

diff --git a/src/internal/cpu/cpu_loong64_linux.go b/src/internal/cpu/cpu_loong64_linux.go
new file mode 100644 (file)
index 0000000..73bc384
--- /dev/null
+++ b/src/internal/cpu/cpu_loong64_linux.go
@@ -0,0 +1,11 @@
+// Copyright 2023 The Go Authors. All rights reserved.
+// Use of this source code is governed by a BSD-style
+// license that can be found in the LICENSE file.
+
+//go:build loong64 && linux
+
+package cpu
+
+func osInit() {
+       hwcapInit()
+}

diff --git a/src/runtime/os_linux_loong64.go b/src/runtime/os_linux_loong64.go
index 61213dadf85f88eb68c09e51930242a569e8cfae..03926feb8c5fc2c5fed211861ffeaddd12adc463 100644 (file)
--- a/src/runtime/os_linux_loong64.go
+++ b/src/runtime/os_linux_loong64.go
@@ -6,6 +6,13 @@
 
 package runtime
 
-func archauxv(tag, val uintptr) {}
+import "internal/cpu"
+
+func archauxv(tag, val uintptr) {
+       switch tag {
+       case _AT_HWCAP:
+               cpu.HWCap = uint(val)
+       }
+}
 
 func osArchInit() {}