// Merge load and op
// TODO: add indexed variants?
-(ADDQ x l:(MOVQload [off] {sym} ptr mem)) && l.Uses == 1 && canMergeLoad(v, l) && clobber(l) -> @l.Block (ADDQmem <l.Type> x [off] {sym} ptr mem)
-(ADDQ l:(MOVQload [off] {sym} ptr mem) x) && l.Uses == 1 && canMergeLoad(v, l) && clobber(l) -> @l.Block (ADDQmem <l.Type> x [off] {sym} ptr mem)
-(ADDL x l:(MOVLload [off] {sym} ptr mem)) && l.Uses == 1 && canMergeLoad(v, l) && clobber(l) -> @l.Block (ADDLmem <l.Type> x [off] {sym} ptr mem)
-(ADDL l:(MOVLload [off] {sym} ptr mem) x) && l.Uses == 1 && canMergeLoad(v, l) && clobber(l) -> @l.Block (ADDLmem <l.Type> x [off] {sym} ptr mem)
-(SUBQ x l:(MOVQload [off] {sym} ptr mem)) && l.Uses == 1 && canMergeLoad(v, l) && clobber(l) -> @l.Block (SUBQmem <l.Type> x [off] {sym} ptr mem)
-(SUBL x l:(MOVLload [off] {sym} ptr mem)) && l.Uses == 1 && canMergeLoad(v, l) && clobber(l) -> @l.Block (SUBLmem <l.Type> x [off] {sym} ptr mem)
-(ANDQ x l:(MOVQload [off] {sym} ptr mem)) && l.Uses == 1 && canMergeLoad(v, l) && clobber(l) -> @l.Block (ANDQmem <l.Type> x [off] {sym} ptr mem)
-(ANDQ l:(MOVQload [off] {sym} ptr mem) x) && l.Uses == 1 && canMergeLoad(v, l) && clobber(l) -> @l.Block (ANDQmem <l.Type> x [off] {sym} ptr mem)
-(ANDL x l:(MOVLload [off] {sym} ptr mem)) && l.Uses == 1 && canMergeLoad(v, l) && clobber(l) -> @l.Block (ANDLmem <l.Type> x [off] {sym} ptr mem)
-(ANDL l:(MOVLload [off] {sym} ptr mem) x) && l.Uses == 1 && canMergeLoad(v, l) && clobber(l) -> @l.Block (ANDLmem <l.Type> x [off] {sym} ptr mem)
-(ORQ x l:(MOVQload [off] {sym} ptr mem)) && l.Uses == 1 && canMergeLoad(v, l) && clobber(l) -> @l.Block (ORQmem <l.Type> x [off] {sym} ptr mem)
-(ORQ l:(MOVQload [off] {sym} ptr mem) x) && l.Uses == 1 && canMergeLoad(v, l) && clobber(l) -> @l.Block (ORQmem <l.Type> x [off] {sym} ptr mem)
-(ORL x l:(MOVLload [off] {sym} ptr mem)) && l.Uses == 1 && canMergeLoad(v, l) && clobber(l) -> @l.Block (ORLmem <l.Type> x [off] {sym} ptr mem)
-(ORL l:(MOVLload [off] {sym} ptr mem) x) && l.Uses == 1 && canMergeLoad(v, l) && clobber(l) -> @l.Block (ORLmem <l.Type> x [off] {sym} ptr mem)
-(XORQ x l:(MOVQload [off] {sym} ptr mem)) && l.Uses == 1 && canMergeLoad(v, l) && clobber(l) -> @l.Block (XORQmem <l.Type> x [off] {sym} ptr mem)
-(XORQ l:(MOVQload [off] {sym} ptr mem) x) && l.Uses == 1 && canMergeLoad(v, l) && clobber(l) -> @l.Block (XORQmem <l.Type> x [off] {sym} ptr mem)
-(XORL x l:(MOVLload [off] {sym} ptr mem)) && l.Uses == 1 && canMergeLoad(v, l) && clobber(l) -> @l.Block (XORLmem <l.Type> x [off] {sym} ptr mem)
-(XORL l:(MOVLload [off] {sym} ptr mem) x) && l.Uses == 1 && canMergeLoad(v, l) && clobber(l) -> @l.Block (XORLmem <l.Type> x [off] {sym} ptr mem)
-(ADDSD x l:(MOVSDload [off] {sym} ptr mem)) && l.Uses == 1 && canMergeLoad(v, l) && clobber(l) -> @l.Block (ADDSDmem <l.Type> x [off] {sym} ptr mem)
-(ADDSD l:(MOVSDload [off] {sym} ptr mem) x) && l.Uses == 1 && canMergeLoad(v, l) && clobber(l) -> @l.Block (ADDSDmem <l.Type> x [off] {sym} ptr mem)
-(ADDSS x l:(MOVSSload [off] {sym} ptr mem)) && l.Uses == 1 && canMergeLoad(v, l) && clobber(l) -> @l.Block (ADDSSmem <l.Type> x [off] {sym} ptr mem)
-(ADDSS l:(MOVSSload [off] {sym} ptr mem) x) && l.Uses == 1 && canMergeLoad(v, l) && clobber(l) -> @l.Block (ADDSSmem <l.Type> x [off] {sym} ptr mem)
-(SUBSD x l:(MOVSDload [off] {sym} ptr mem)) && l.Uses == 1 && canMergeLoad(v, l) && clobber(l) -> @l.Block (SUBSDmem <l.Type> x [off] {sym} ptr mem)
-(SUBSS x l:(MOVSSload [off] {sym} ptr mem)) && l.Uses == 1 && canMergeLoad(v, l) && clobber(l) -> @l.Block (SUBSSmem <l.Type> x [off] {sym} ptr mem)
-(MULSD x l:(MOVSDload [off] {sym} ptr mem)) && l.Uses == 1 && canMergeLoad(v, l) && clobber(l) -> @l.Block (MULSDmem <l.Type> x [off] {sym} ptr mem)
-(MULSD l:(MOVSDload [off] {sym} ptr mem) x) && l.Uses == 1 && canMergeLoad(v, l) && clobber(l) -> @l.Block (MULSDmem <l.Type> x [off] {sym} ptr mem)
-(MULSS x l:(MOVSSload [off] {sym} ptr mem)) && l.Uses == 1 && canMergeLoad(v, l) && clobber(l) -> @l.Block (MULSSmem <l.Type> x [off] {sym} ptr mem)
-(MULSS l:(MOVSSload [off] {sym} ptr mem) x) && l.Uses == 1 && canMergeLoad(v, l) && clobber(l) -> @l.Block (MULSSmem <l.Type> x [off] {sym} ptr mem)
+(ADDQ x l:(MOVQload [off] {sym} ptr mem)) && l.Uses == 1 && canMergeLoad(v, l) && clobber(l) -> (ADDQmem x [off] {sym} ptr mem)
+(ADDQ l:(MOVQload [off] {sym} ptr mem) x) && l.Uses == 1 && canMergeLoad(v, l) && clobber(l) -> (ADDQmem x [off] {sym} ptr mem)
+(ADDL x l:(MOVLload [off] {sym} ptr mem)) && l.Uses == 1 && canMergeLoad(v, l) && clobber(l) -> (ADDLmem x [off] {sym} ptr mem)
+(ADDL l:(MOVLload [off] {sym} ptr mem) x) && l.Uses == 1 && canMergeLoad(v, l) && clobber(l) -> (ADDLmem x [off] {sym} ptr mem)
+(SUBQ x l:(MOVQload [off] {sym} ptr mem)) && l.Uses == 1 && canMergeLoad(v, l) && clobber(l) -> (SUBQmem x [off] {sym} ptr mem)
+(SUBL x l:(MOVLload [off] {sym} ptr mem)) && l.Uses == 1 && canMergeLoad(v, l) && clobber(l) -> (SUBLmem x [off] {sym} ptr mem)
+(ANDQ x l:(MOVQload [off] {sym} ptr mem)) && l.Uses == 1 && canMergeLoad(v, l) && clobber(l) -> (ANDQmem x [off] {sym} ptr mem)
+(ANDQ l:(MOVQload [off] {sym} ptr mem) x) && l.Uses == 1 && canMergeLoad(v, l) && clobber(l) -> (ANDQmem x [off] {sym} ptr mem)
+(ANDL x l:(MOVLload [off] {sym} ptr mem)) && l.Uses == 1 && canMergeLoad(v, l) && clobber(l) -> (ANDLmem x [off] {sym} ptr mem)
+(ANDL l:(MOVLload [off] {sym} ptr mem) x) && l.Uses == 1 && canMergeLoad(v, l) && clobber(l) -> (ANDLmem x [off] {sym} ptr mem)
+(ORQ x l:(MOVQload [off] {sym} ptr mem)) && l.Uses == 1 && canMergeLoad(v, l) && clobber(l) -> (ORQmem x [off] {sym} ptr mem)
+(ORQ l:(MOVQload [off] {sym} ptr mem) x) && l.Uses == 1 && canMergeLoad(v, l) && clobber(l) -> (ORQmem x [off] {sym} ptr mem)
+(ORL x l:(MOVLload [off] {sym} ptr mem)) && l.Uses == 1 && canMergeLoad(v, l) && clobber(l) -> (ORLmem x [off] {sym} ptr mem)
+(ORL l:(MOVLload [off] {sym} ptr mem) x) && l.Uses == 1 && canMergeLoad(v, l) && clobber(l) -> (ORLmem x [off] {sym} ptr mem)
+(XORQ x l:(MOVQload [off] {sym} ptr mem)) && l.Uses == 1 && canMergeLoad(v, l) && clobber(l) -> (XORQmem x [off] {sym} ptr mem)
+(XORQ l:(MOVQload [off] {sym} ptr mem) x) && l.Uses == 1 && canMergeLoad(v, l) && clobber(l) -> (XORQmem x [off] {sym} ptr mem)
+(XORL x l:(MOVLload [off] {sym} ptr mem)) && l.Uses == 1 && canMergeLoad(v, l) && clobber(l) -> (XORLmem x [off] {sym} ptr mem)
+(XORL l:(MOVLload [off] {sym} ptr mem) x) && l.Uses == 1 && canMergeLoad(v, l) && clobber(l) -> (XORLmem x [off] {sym} ptr mem)
+(ADDSD x l:(MOVSDload [off] {sym} ptr mem)) && l.Uses == 1 && canMergeLoad(v, l) && clobber(l) -> (ADDSDmem x [off] {sym} ptr mem)
+(ADDSD l:(MOVSDload [off] {sym} ptr mem) x) && l.Uses == 1 && canMergeLoad(v, l) && clobber(l) -> (ADDSDmem x [off] {sym} ptr mem)
+(ADDSS x l:(MOVSSload [off] {sym} ptr mem)) && l.Uses == 1 && canMergeLoad(v, l) && clobber(l) -> (ADDSSmem x [off] {sym} ptr mem)
+(ADDSS l:(MOVSSload [off] {sym} ptr mem) x) && l.Uses == 1 && canMergeLoad(v, l) && clobber(l) -> (ADDSSmem x [off] {sym} ptr mem)
+(SUBSD x l:(MOVSDload [off] {sym} ptr mem)) && l.Uses == 1 && canMergeLoad(v, l) && clobber(l) -> (SUBSDmem x [off] {sym} ptr mem)
+(SUBSS x l:(MOVSSload [off] {sym} ptr mem)) && l.Uses == 1 && canMergeLoad(v, l) && clobber(l) -> (SUBSSmem x [off] {sym} ptr mem)
+(MULSD x l:(MOVSDload [off] {sym} ptr mem)) && l.Uses == 1 && canMergeLoad(v, l) && clobber(l) -> (MULSDmem x [off] {sym} ptr mem)
+(MULSD l:(MOVSDload [off] {sym} ptr mem) x) && l.Uses == 1 && canMergeLoad(v, l) && clobber(l) -> (MULSDmem x [off] {sym} ptr mem)
+(MULSS x l:(MOVSSload [off] {sym} ptr mem)) && l.Uses == 1 && canMergeLoad(v, l) && clobber(l) -> (MULSSmem x [off] {sym} ptr mem)
+(MULSS l:(MOVSSload [off] {sym} ptr mem) x) && l.Uses == 1 && canMergeLoad(v, l) && clobber(l) -> (MULSSmem x [off] {sym} ptr mem)
// Merge ADDQconst and LEAQ into atomic loads.
(MOVQatomicload [off1] {sym} (ADDQconst [off2] ptr) mem) && is32Bit(off1+off2) ->
{name: "ROLWconst", argLength: 1, reg: gp11, asm: "ROLW", aux: "Int16", resultInArg0: true, clobberFlags: true}, // arg0 rotate left auxint, rotate amount 0-15
{name: "ROLBconst", argLength: 1, reg: gp11, asm: "ROLB", aux: "Int8", resultInArg0: true, clobberFlags: true}, // arg0 rotate left auxint, rotate amount 0-7
- {name: "ADDLmem", argLength: 3, reg: gp21load, asm: "ADDL", typ: "UInt32", aux: "SymOff", resultInArg0: true, clobberFlags: true, faultOnNilArg1: true}, // arg0 + tmp, tmp loaded from arg1+auxint+aux, arg2 = mem
- {name: "ADDQmem", argLength: 3, reg: gp21load, asm: "ADDQ", typ: "UInt64", aux: "SymOff", resultInArg0: true, clobberFlags: true, faultOnNilArg1: true}, // arg0 + tmp, tmp loaded from arg1+auxint+aux, arg2 = mem
- {name: "SUBQmem", argLength: 3, reg: gp21load, asm: "SUBQ", typ: "UInt64", aux: "SymOff", resultInArg0: true, clobberFlags: true, faultOnNilArg1: true}, // arg0 - tmp, tmp loaded from arg1+auxint+aux, arg2 = mem
- {name: "SUBLmem", argLength: 3, reg: gp21load, asm: "SUBL", typ: "UInt32", aux: "SymOff", resultInArg0: true, clobberFlags: true, faultOnNilArg1: true}, // arg0 - tmp, tmp loaded from arg1+auxint+aux, arg2 = mem
- {name: "ANDLmem", argLength: 3, reg: gp21load, asm: "ANDL", typ: "UInt32", aux: "SymOff", resultInArg0: true, clobberFlags: true, faultOnNilArg1: true}, // arg0 & tmp, tmp loaded from arg1+auxint+aux, arg2 = mem
- {name: "ANDQmem", argLength: 3, reg: gp21load, asm: "ANDQ", typ: "UInt64", aux: "SymOff", resultInArg0: true, clobberFlags: true, faultOnNilArg1: true}, // arg0 & tmp, tmp loaded from arg1+auxint+aux, arg2 = mem
- {name: "ORQmem", argLength: 3, reg: gp21load, asm: "ORQ", typ: "UInt64", aux: "SymOff", resultInArg0: true, clobberFlags: true, faultOnNilArg1: true}, // arg0 | tmp, tmp loaded from arg1+auxint+aux, arg2 = mem
- {name: "ORLmem", argLength: 3, reg: gp21load, asm: "ORL", typ: "UInt32", aux: "SymOff", resultInArg0: true, clobberFlags: true, faultOnNilArg1: true}, // arg0 | tmp, tmp loaded from arg1+auxint+aux, arg2 = mem
- {name: "XORQmem", argLength: 3, reg: gp21load, asm: "XORQ", typ: "UInt64", aux: "SymOff", resultInArg0: true, clobberFlags: true, faultOnNilArg1: true}, // arg0 ^ tmp, tmp loaded from arg1+auxint+aux, arg2 = mem
- {name: "XORLmem", argLength: 3, reg: gp21load, asm: "XORL", typ: "UInt32", aux: "SymOff", resultInArg0: true, clobberFlags: true, faultOnNilArg1: true}, // arg0 ^ tmp, tmp loaded from arg1+auxint+aux, arg2 = mem
+ {name: "ADDLmem", argLength: 3, reg: gp21load, asm: "ADDL", aux: "SymOff", resultInArg0: true, clobberFlags: true, faultOnNilArg1: true}, // arg0 + tmp, tmp loaded from arg1+auxint+aux, arg2 = mem
+ {name: "ADDQmem", argLength: 3, reg: gp21load, asm: "ADDQ", aux: "SymOff", resultInArg0: true, clobberFlags: true, faultOnNilArg1: true}, // arg0 + tmp, tmp loaded from arg1+auxint+aux, arg2 = mem
+ {name: "SUBQmem", argLength: 3, reg: gp21load, asm: "SUBQ", aux: "SymOff", resultInArg0: true, clobberFlags: true, faultOnNilArg1: true}, // arg0 - tmp, tmp loaded from arg1+auxint+aux, arg2 = mem
+ {name: "SUBLmem", argLength: 3, reg: gp21load, asm: "SUBL", aux: "SymOff", resultInArg0: true, clobberFlags: true, faultOnNilArg1: true}, // arg0 - tmp, tmp loaded from arg1+auxint+aux, arg2 = mem
+ {name: "ANDLmem", argLength: 3, reg: gp21load, asm: "ANDL", aux: "SymOff", resultInArg0: true, clobberFlags: true, faultOnNilArg1: true}, // arg0 & tmp, tmp loaded from arg1+auxint+aux, arg2 = mem
+ {name: "ANDQmem", argLength: 3, reg: gp21load, asm: "ANDQ", aux: "SymOff", resultInArg0: true, clobberFlags: true, faultOnNilArg1: true}, // arg0 & tmp, tmp loaded from arg1+auxint+aux, arg2 = mem
+ {name: "ORQmem", argLength: 3, reg: gp21load, asm: "ORQ", aux: "SymOff", resultInArg0: true, clobberFlags: true, faultOnNilArg1: true}, // arg0 | tmp, tmp loaded from arg1+auxint+aux, arg2 = mem
+ {name: "ORLmem", argLength: 3, reg: gp21load, asm: "ORL", aux: "SymOff", resultInArg0: true, clobberFlags: true, faultOnNilArg1: true}, // arg0 | tmp, tmp loaded from arg1+auxint+aux, arg2 = mem
+ {name: "XORQmem", argLength: 3, reg: gp21load, asm: "XORQ", aux: "SymOff", resultInArg0: true, clobberFlags: true, faultOnNilArg1: true}, // arg0 ^ tmp, tmp loaded from arg1+auxint+aux, arg2 = mem
+ {name: "XORLmem", argLength: 3, reg: gp21load, asm: "XORL", aux: "SymOff", resultInArg0: true, clobberFlags: true, faultOnNilArg1: true}, // arg0 ^ tmp, tmp loaded from arg1+auxint+aux, arg2 = mem
// unary ops
{name: "NEGQ", argLength: 1, reg: gp11, asm: "NEGQ", resultInArg0: true, clobberFlags: true}, // -arg0
}
// match: (ADDL x l:(MOVLload [off] {sym} ptr mem))
// cond: l.Uses == 1 && canMergeLoad(v, l) && clobber(l)
- // result: @l.Block (ADDLmem <l.Type> x [off] {sym} ptr mem)
+ // result: (ADDLmem x [off] {sym} ptr mem)
for {
x := v.Args[0]
l := v.Args[1]
if !(l.Uses == 1 && canMergeLoad(v, l) && clobber(l)) {
break
}
- b = l.Block
- v0 := b.NewValue0(v.Pos, OpAMD64ADDLmem, l.Type)
- v.reset(OpCopy)
- v.AddArg(v0)
- v0.AuxInt = off
- v0.Aux = sym
- v0.AddArg(x)
- v0.AddArg(ptr)
- v0.AddArg(mem)
+ v.reset(OpAMD64ADDLmem)
+ v.AuxInt = off
+ v.Aux = sym
+ v.AddArg(x)
+ v.AddArg(ptr)
+ v.AddArg(mem)
return true
}
// match: (ADDL l:(MOVLload [off] {sym} ptr mem) x)
// cond: l.Uses == 1 && canMergeLoad(v, l) && clobber(l)
- // result: @l.Block (ADDLmem <l.Type> x [off] {sym} ptr mem)
+ // result: (ADDLmem x [off] {sym} ptr mem)
for {
l := v.Args[0]
if l.Op != OpAMD64MOVLload {
if !(l.Uses == 1 && canMergeLoad(v, l) && clobber(l)) {
break
}
- b = l.Block
- v0 := b.NewValue0(v.Pos, OpAMD64ADDLmem, l.Type)
- v.reset(OpCopy)
- v.AddArg(v0)
- v0.AuxInt = off
- v0.Aux = sym
- v0.AddArg(x)
- v0.AddArg(ptr)
- v0.AddArg(mem)
+ v.reset(OpAMD64ADDLmem)
+ v.AuxInt = off
+ v.Aux = sym
+ v.AddArg(x)
+ v.AddArg(ptr)
+ v.AddArg(mem)
return true
}
return false
}
// match: (ADDQ x l:(MOVQload [off] {sym} ptr mem))
// cond: l.Uses == 1 && canMergeLoad(v, l) && clobber(l)
- // result: @l.Block (ADDQmem <l.Type> x [off] {sym} ptr mem)
+ // result: (ADDQmem x [off] {sym} ptr mem)
for {
x := v.Args[0]
l := v.Args[1]
if !(l.Uses == 1 && canMergeLoad(v, l) && clobber(l)) {
break
}
- b = l.Block
- v0 := b.NewValue0(v.Pos, OpAMD64ADDQmem, l.Type)
- v.reset(OpCopy)
- v.AddArg(v0)
- v0.AuxInt = off
- v0.Aux = sym
- v0.AddArg(x)
- v0.AddArg(ptr)
- v0.AddArg(mem)
+ v.reset(OpAMD64ADDQmem)
+ v.AuxInt = off
+ v.Aux = sym
+ v.AddArg(x)
+ v.AddArg(ptr)
+ v.AddArg(mem)
return true
}
// match: (ADDQ l:(MOVQload [off] {sym} ptr mem) x)
// cond: l.Uses == 1 && canMergeLoad(v, l) && clobber(l)
- // result: @l.Block (ADDQmem <l.Type> x [off] {sym} ptr mem)
+ // result: (ADDQmem x [off] {sym} ptr mem)
for {
l := v.Args[0]
if l.Op != OpAMD64MOVQload {
if !(l.Uses == 1 && canMergeLoad(v, l) && clobber(l)) {
break
}
- b = l.Block
- v0 := b.NewValue0(v.Pos, OpAMD64ADDQmem, l.Type)
- v.reset(OpCopy)
- v.AddArg(v0)
- v0.AuxInt = off
- v0.Aux = sym
- v0.AddArg(x)
- v0.AddArg(ptr)
- v0.AddArg(mem)
+ v.reset(OpAMD64ADDQmem)
+ v.AuxInt = off
+ v.Aux = sym
+ v.AddArg(x)
+ v.AddArg(ptr)
+ v.AddArg(mem)
return true
}
return false
_ = b
// match: (ADDSD x l:(MOVSDload [off] {sym} ptr mem))
// cond: l.Uses == 1 && canMergeLoad(v, l) && clobber(l)
- // result: @l.Block (ADDSDmem <l.Type> x [off] {sym} ptr mem)
+ // result: (ADDSDmem x [off] {sym} ptr mem)
for {
x := v.Args[0]
l := v.Args[1]
if !(l.Uses == 1 && canMergeLoad(v, l) && clobber(l)) {
break
}
- b = l.Block
- v0 := b.NewValue0(v.Pos, OpAMD64ADDSDmem, l.Type)
- v.reset(OpCopy)
- v.AddArg(v0)
- v0.AuxInt = off
- v0.Aux = sym
- v0.AddArg(x)
- v0.AddArg(ptr)
- v0.AddArg(mem)
+ v.reset(OpAMD64ADDSDmem)
+ v.AuxInt = off
+ v.Aux = sym
+ v.AddArg(x)
+ v.AddArg(ptr)
+ v.AddArg(mem)
return true
}
// match: (ADDSD l:(MOVSDload [off] {sym} ptr mem) x)
// cond: l.Uses == 1 && canMergeLoad(v, l) && clobber(l)
- // result: @l.Block (ADDSDmem <l.Type> x [off] {sym} ptr mem)
+ // result: (ADDSDmem x [off] {sym} ptr mem)
for {
l := v.Args[0]
if l.Op != OpAMD64MOVSDload {
if !(l.Uses == 1 && canMergeLoad(v, l) && clobber(l)) {
break
}
- b = l.Block
- v0 := b.NewValue0(v.Pos, OpAMD64ADDSDmem, l.Type)
- v.reset(OpCopy)
- v.AddArg(v0)
- v0.AuxInt = off
- v0.Aux = sym
- v0.AddArg(x)
- v0.AddArg(ptr)
- v0.AddArg(mem)
+ v.reset(OpAMD64ADDSDmem)
+ v.AuxInt = off
+ v.Aux = sym
+ v.AddArg(x)
+ v.AddArg(ptr)
+ v.AddArg(mem)
return true
}
return false
_ = b
// match: (ADDSS x l:(MOVSSload [off] {sym} ptr mem))
// cond: l.Uses == 1 && canMergeLoad(v, l) && clobber(l)
- // result: @l.Block (ADDSSmem <l.Type> x [off] {sym} ptr mem)
+ // result: (ADDSSmem x [off] {sym} ptr mem)
for {
x := v.Args[0]
l := v.Args[1]
if !(l.Uses == 1 && canMergeLoad(v, l) && clobber(l)) {
break
}
- b = l.Block
- v0 := b.NewValue0(v.Pos, OpAMD64ADDSSmem, l.Type)
- v.reset(OpCopy)
- v.AddArg(v0)
- v0.AuxInt = off
- v0.Aux = sym
- v0.AddArg(x)
- v0.AddArg(ptr)
- v0.AddArg(mem)
+ v.reset(OpAMD64ADDSSmem)
+ v.AuxInt = off
+ v.Aux = sym
+ v.AddArg(x)
+ v.AddArg(ptr)
+ v.AddArg(mem)
return true
}
// match: (ADDSS l:(MOVSSload [off] {sym} ptr mem) x)
// cond: l.Uses == 1 && canMergeLoad(v, l) && clobber(l)
- // result: @l.Block (ADDSSmem <l.Type> x [off] {sym} ptr mem)
+ // result: (ADDSSmem x [off] {sym} ptr mem)
for {
l := v.Args[0]
if l.Op != OpAMD64MOVSSload {
if !(l.Uses == 1 && canMergeLoad(v, l) && clobber(l)) {
break
}
- b = l.Block
- v0 := b.NewValue0(v.Pos, OpAMD64ADDSSmem, l.Type)
- v.reset(OpCopy)
- v.AddArg(v0)
- v0.AuxInt = off
- v0.Aux = sym
- v0.AddArg(x)
- v0.AddArg(ptr)
- v0.AddArg(mem)
+ v.reset(OpAMD64ADDSSmem)
+ v.AuxInt = off
+ v.Aux = sym
+ v.AddArg(x)
+ v.AddArg(ptr)
+ v.AddArg(mem)
return true
}
return false
}
// match: (ANDL x l:(MOVLload [off] {sym} ptr mem))
// cond: l.Uses == 1 && canMergeLoad(v, l) && clobber(l)
- // result: @l.Block (ANDLmem <l.Type> x [off] {sym} ptr mem)
+ // result: (ANDLmem x [off] {sym} ptr mem)
for {
x := v.Args[0]
l := v.Args[1]
if !(l.Uses == 1 && canMergeLoad(v, l) && clobber(l)) {
break
}
- b = l.Block
- v0 := b.NewValue0(v.Pos, OpAMD64ANDLmem, l.Type)
- v.reset(OpCopy)
- v.AddArg(v0)
- v0.AuxInt = off
- v0.Aux = sym
- v0.AddArg(x)
- v0.AddArg(ptr)
- v0.AddArg(mem)
+ v.reset(OpAMD64ANDLmem)
+ v.AuxInt = off
+ v.Aux = sym
+ v.AddArg(x)
+ v.AddArg(ptr)
+ v.AddArg(mem)
return true
}
// match: (ANDL l:(MOVLload [off] {sym} ptr mem) x)
// cond: l.Uses == 1 && canMergeLoad(v, l) && clobber(l)
- // result: @l.Block (ANDLmem <l.Type> x [off] {sym} ptr mem)
+ // result: (ANDLmem x [off] {sym} ptr mem)
for {
l := v.Args[0]
if l.Op != OpAMD64MOVLload {
if !(l.Uses == 1 && canMergeLoad(v, l) && clobber(l)) {
break
}
- b = l.Block
- v0 := b.NewValue0(v.Pos, OpAMD64ANDLmem, l.Type)
- v.reset(OpCopy)
- v.AddArg(v0)
- v0.AuxInt = off
- v0.Aux = sym
- v0.AddArg(x)
- v0.AddArg(ptr)
- v0.AddArg(mem)
+ v.reset(OpAMD64ANDLmem)
+ v.AuxInt = off
+ v.Aux = sym
+ v.AddArg(x)
+ v.AddArg(ptr)
+ v.AddArg(mem)
return true
}
return false
}
// match: (ANDQ x l:(MOVQload [off] {sym} ptr mem))
// cond: l.Uses == 1 && canMergeLoad(v, l) && clobber(l)
- // result: @l.Block (ANDQmem <l.Type> x [off] {sym} ptr mem)
+ // result: (ANDQmem x [off] {sym} ptr mem)
for {
x := v.Args[0]
l := v.Args[1]
if !(l.Uses == 1 && canMergeLoad(v, l) && clobber(l)) {
break
}
- b = l.Block
- v0 := b.NewValue0(v.Pos, OpAMD64ANDQmem, l.Type)
- v.reset(OpCopy)
- v.AddArg(v0)
- v0.AuxInt = off
- v0.Aux = sym
- v0.AddArg(x)
- v0.AddArg(ptr)
- v0.AddArg(mem)
+ v.reset(OpAMD64ANDQmem)
+ v.AuxInt = off
+ v.Aux = sym
+ v.AddArg(x)
+ v.AddArg(ptr)
+ v.AddArg(mem)
return true
}
// match: (ANDQ l:(MOVQload [off] {sym} ptr mem) x)
// cond: l.Uses == 1 && canMergeLoad(v, l) && clobber(l)
- // result: @l.Block (ANDQmem <l.Type> x [off] {sym} ptr mem)
+ // result: (ANDQmem x [off] {sym} ptr mem)
for {
l := v.Args[0]
if l.Op != OpAMD64MOVQload {
if !(l.Uses == 1 && canMergeLoad(v, l) && clobber(l)) {
break
}
- b = l.Block
- v0 := b.NewValue0(v.Pos, OpAMD64ANDQmem, l.Type)
- v.reset(OpCopy)
- v.AddArg(v0)
- v0.AuxInt = off
- v0.Aux = sym
- v0.AddArg(x)
- v0.AddArg(ptr)
- v0.AddArg(mem)
+ v.reset(OpAMD64ANDQmem)
+ v.AuxInt = off
+ v.Aux = sym
+ v.AddArg(x)
+ v.AddArg(ptr)
+ v.AddArg(mem)
return true
}
return false
_ = b
// match: (MULSD x l:(MOVSDload [off] {sym} ptr mem))
// cond: l.Uses == 1 && canMergeLoad(v, l) && clobber(l)
- // result: @l.Block (MULSDmem <l.Type> x [off] {sym} ptr mem)
+ // result: (MULSDmem x [off] {sym} ptr mem)
for {
x := v.Args[0]
l := v.Args[1]
if !(l.Uses == 1 && canMergeLoad(v, l) && clobber(l)) {
break
}
- b = l.Block
- v0 := b.NewValue0(v.Pos, OpAMD64MULSDmem, l.Type)
- v.reset(OpCopy)
- v.AddArg(v0)
- v0.AuxInt = off
- v0.Aux = sym
- v0.AddArg(x)
- v0.AddArg(ptr)
- v0.AddArg(mem)
+ v.reset(OpAMD64MULSDmem)
+ v.AuxInt = off
+ v.Aux = sym
+ v.AddArg(x)
+ v.AddArg(ptr)
+ v.AddArg(mem)
return true
}
// match: (MULSD l:(MOVSDload [off] {sym} ptr mem) x)
// cond: l.Uses == 1 && canMergeLoad(v, l) && clobber(l)
- // result: @l.Block (MULSDmem <l.Type> x [off] {sym} ptr mem)
+ // result: (MULSDmem x [off] {sym} ptr mem)
for {
l := v.Args[0]
if l.Op != OpAMD64MOVSDload {
if !(l.Uses == 1 && canMergeLoad(v, l) && clobber(l)) {
break
}
- b = l.Block
- v0 := b.NewValue0(v.Pos, OpAMD64MULSDmem, l.Type)
- v.reset(OpCopy)
- v.AddArg(v0)
- v0.AuxInt = off
- v0.Aux = sym
- v0.AddArg(x)
- v0.AddArg(ptr)
- v0.AddArg(mem)
+ v.reset(OpAMD64MULSDmem)
+ v.AuxInt = off
+ v.Aux = sym
+ v.AddArg(x)
+ v.AddArg(ptr)
+ v.AddArg(mem)
return true
}
return false
_ = b
// match: (MULSS x l:(MOVSSload [off] {sym} ptr mem))
// cond: l.Uses == 1 && canMergeLoad(v, l) && clobber(l)
- // result: @l.Block (MULSSmem <l.Type> x [off] {sym} ptr mem)
+ // result: (MULSSmem x [off] {sym} ptr mem)
for {
x := v.Args[0]
l := v.Args[1]
if !(l.Uses == 1 && canMergeLoad(v, l) && clobber(l)) {
break
}
- b = l.Block
- v0 := b.NewValue0(v.Pos, OpAMD64MULSSmem, l.Type)
- v.reset(OpCopy)
- v.AddArg(v0)
- v0.AuxInt = off
- v0.Aux = sym
- v0.AddArg(x)
- v0.AddArg(ptr)
- v0.AddArg(mem)
+ v.reset(OpAMD64MULSSmem)
+ v.AuxInt = off
+ v.Aux = sym
+ v.AddArg(x)
+ v.AddArg(ptr)
+ v.AddArg(mem)
return true
}
// match: (MULSS l:(MOVSSload [off] {sym} ptr mem) x)
// cond: l.Uses == 1 && canMergeLoad(v, l) && clobber(l)
- // result: @l.Block (MULSSmem <l.Type> x [off] {sym} ptr mem)
+ // result: (MULSSmem x [off] {sym} ptr mem)
for {
l := v.Args[0]
if l.Op != OpAMD64MOVSSload {
if !(l.Uses == 1 && canMergeLoad(v, l) && clobber(l)) {
break
}
- b = l.Block
- v0 := b.NewValue0(v.Pos, OpAMD64MULSSmem, l.Type)
- v.reset(OpCopy)
- v.AddArg(v0)
- v0.AuxInt = off
- v0.Aux = sym
- v0.AddArg(x)
- v0.AddArg(ptr)
- v0.AddArg(mem)
+ v.reset(OpAMD64MULSSmem)
+ v.AuxInt = off
+ v.Aux = sym
+ v.AddArg(x)
+ v.AddArg(ptr)
+ v.AddArg(mem)
return true
}
return false
}
// match: (ORL x l:(MOVLload [off] {sym} ptr mem))
// cond: l.Uses == 1 && canMergeLoad(v, l) && clobber(l)
- // result: @l.Block (ORLmem <l.Type> x [off] {sym} ptr mem)
+ // result: (ORLmem x [off] {sym} ptr mem)
for {
x := v.Args[0]
l := v.Args[1]
if !(l.Uses == 1 && canMergeLoad(v, l) && clobber(l)) {
break
}
- b = l.Block
- v0 := b.NewValue0(v.Pos, OpAMD64ORLmem, l.Type)
- v.reset(OpCopy)
- v.AddArg(v0)
- v0.AuxInt = off
- v0.Aux = sym
- v0.AddArg(x)
- v0.AddArg(ptr)
- v0.AddArg(mem)
+ v.reset(OpAMD64ORLmem)
+ v.AuxInt = off
+ v.Aux = sym
+ v.AddArg(x)
+ v.AddArg(ptr)
+ v.AddArg(mem)
return true
}
// match: (ORL l:(MOVLload [off] {sym} ptr mem) x)
// cond: l.Uses == 1 && canMergeLoad(v, l) && clobber(l)
- // result: @l.Block (ORLmem <l.Type> x [off] {sym} ptr mem)
+ // result: (ORLmem x [off] {sym} ptr mem)
for {
l := v.Args[0]
if l.Op != OpAMD64MOVLload {
if !(l.Uses == 1 && canMergeLoad(v, l) && clobber(l)) {
break
}
- b = l.Block
- v0 := b.NewValue0(v.Pos, OpAMD64ORLmem, l.Type)
- v.reset(OpCopy)
- v.AddArg(v0)
- v0.AuxInt = off
- v0.Aux = sym
- v0.AddArg(x)
- v0.AddArg(ptr)
- v0.AddArg(mem)
+ v.reset(OpAMD64ORLmem)
+ v.AuxInt = off
+ v.Aux = sym
+ v.AddArg(x)
+ v.AddArg(ptr)
+ v.AddArg(mem)
return true
}
return false
}
// match: (ORQ x l:(MOVQload [off] {sym} ptr mem))
// cond: l.Uses == 1 && canMergeLoad(v, l) && clobber(l)
- // result: @l.Block (ORQmem <l.Type> x [off] {sym} ptr mem)
+ // result: (ORQmem x [off] {sym} ptr mem)
for {
x := v.Args[0]
l := v.Args[1]
if !(l.Uses == 1 && canMergeLoad(v, l) && clobber(l)) {
break
}
- b = l.Block
- v0 := b.NewValue0(v.Pos, OpAMD64ORQmem, l.Type)
- v.reset(OpCopy)
- v.AddArg(v0)
- v0.AuxInt = off
- v0.Aux = sym
- v0.AddArg(x)
- v0.AddArg(ptr)
- v0.AddArg(mem)
+ v.reset(OpAMD64ORQmem)
+ v.AuxInt = off
+ v.Aux = sym
+ v.AddArg(x)
+ v.AddArg(ptr)
+ v.AddArg(mem)
return true
}
// match: (ORQ l:(MOVQload [off] {sym} ptr mem) x)
// cond: l.Uses == 1 && canMergeLoad(v, l) && clobber(l)
- // result: @l.Block (ORQmem <l.Type> x [off] {sym} ptr mem)
+ // result: (ORQmem x [off] {sym} ptr mem)
for {
l := v.Args[0]
if l.Op != OpAMD64MOVQload {
if !(l.Uses == 1 && canMergeLoad(v, l) && clobber(l)) {
break
}
- b = l.Block
- v0 := b.NewValue0(v.Pos, OpAMD64ORQmem, l.Type)
- v.reset(OpCopy)
- v.AddArg(v0)
- v0.AuxInt = off
- v0.Aux = sym
- v0.AddArg(x)
- v0.AddArg(ptr)
- v0.AddArg(mem)
+ v.reset(OpAMD64ORQmem)
+ v.AuxInt = off
+ v.Aux = sym
+ v.AddArg(x)
+ v.AddArg(ptr)
+ v.AddArg(mem)
return true
}
return false
}
// match: (SUBL x l:(MOVLload [off] {sym} ptr mem))
// cond: l.Uses == 1 && canMergeLoad(v, l) && clobber(l)
- // result: @l.Block (SUBLmem <l.Type> x [off] {sym} ptr mem)
+ // result: (SUBLmem x [off] {sym} ptr mem)
for {
x := v.Args[0]
l := v.Args[1]
if !(l.Uses == 1 && canMergeLoad(v, l) && clobber(l)) {
break
}
- b = l.Block
- v0 := b.NewValue0(v.Pos, OpAMD64SUBLmem, l.Type)
- v.reset(OpCopy)
- v.AddArg(v0)
- v0.AuxInt = off
- v0.Aux = sym
- v0.AddArg(x)
- v0.AddArg(ptr)
- v0.AddArg(mem)
+ v.reset(OpAMD64SUBLmem)
+ v.AuxInt = off
+ v.Aux = sym
+ v.AddArg(x)
+ v.AddArg(ptr)
+ v.AddArg(mem)
return true
}
return false
}
// match: (SUBQ x l:(MOVQload [off] {sym} ptr mem))
// cond: l.Uses == 1 && canMergeLoad(v, l) && clobber(l)
- // result: @l.Block (SUBQmem <l.Type> x [off] {sym} ptr mem)
+ // result: (SUBQmem x [off] {sym} ptr mem)
for {
x := v.Args[0]
l := v.Args[1]
if !(l.Uses == 1 && canMergeLoad(v, l) && clobber(l)) {
break
}
- b = l.Block
- v0 := b.NewValue0(v.Pos, OpAMD64SUBQmem, l.Type)
- v.reset(OpCopy)
- v.AddArg(v0)
- v0.AuxInt = off
- v0.Aux = sym
- v0.AddArg(x)
- v0.AddArg(ptr)
- v0.AddArg(mem)
+ v.reset(OpAMD64SUBQmem)
+ v.AuxInt = off
+ v.Aux = sym
+ v.AddArg(x)
+ v.AddArg(ptr)
+ v.AddArg(mem)
return true
}
return false
_ = b
// match: (SUBSD x l:(MOVSDload [off] {sym} ptr mem))
// cond: l.Uses == 1 && canMergeLoad(v, l) && clobber(l)
- // result: @l.Block (SUBSDmem <l.Type> x [off] {sym} ptr mem)
+ // result: (SUBSDmem x [off] {sym} ptr mem)
for {
x := v.Args[0]
l := v.Args[1]
if !(l.Uses == 1 && canMergeLoad(v, l) && clobber(l)) {
break
}
- b = l.Block
- v0 := b.NewValue0(v.Pos, OpAMD64SUBSDmem, l.Type)
- v.reset(OpCopy)
- v.AddArg(v0)
- v0.AuxInt = off
- v0.Aux = sym
- v0.AddArg(x)
- v0.AddArg(ptr)
- v0.AddArg(mem)
+ v.reset(OpAMD64SUBSDmem)
+ v.AuxInt = off
+ v.Aux = sym
+ v.AddArg(x)
+ v.AddArg(ptr)
+ v.AddArg(mem)
return true
}
return false
_ = b
// match: (SUBSS x l:(MOVSSload [off] {sym} ptr mem))
// cond: l.Uses == 1 && canMergeLoad(v, l) && clobber(l)
- // result: @l.Block (SUBSSmem <l.Type> x [off] {sym} ptr mem)
+ // result: (SUBSSmem x [off] {sym} ptr mem)
for {
x := v.Args[0]
l := v.Args[1]
if !(l.Uses == 1 && canMergeLoad(v, l) && clobber(l)) {
break
}
- b = l.Block
- v0 := b.NewValue0(v.Pos, OpAMD64SUBSSmem, l.Type)
- v.reset(OpCopy)
- v.AddArg(v0)
- v0.AuxInt = off
- v0.Aux = sym
- v0.AddArg(x)
- v0.AddArg(ptr)
- v0.AddArg(mem)
+ v.reset(OpAMD64SUBSSmem)
+ v.AuxInt = off
+ v.Aux = sym
+ v.AddArg(x)
+ v.AddArg(ptr)
+ v.AddArg(mem)
return true
}
return false
}
// match: (XORL x l:(MOVLload [off] {sym} ptr mem))
// cond: l.Uses == 1 && canMergeLoad(v, l) && clobber(l)
- // result: @l.Block (XORLmem <l.Type> x [off] {sym} ptr mem)
+ // result: (XORLmem x [off] {sym} ptr mem)
for {
x := v.Args[0]
l := v.Args[1]
if !(l.Uses == 1 && canMergeLoad(v, l) && clobber(l)) {
break
}
- b = l.Block
- v0 := b.NewValue0(v.Pos, OpAMD64XORLmem, l.Type)
- v.reset(OpCopy)
- v.AddArg(v0)
- v0.AuxInt = off
- v0.Aux = sym
- v0.AddArg(x)
- v0.AddArg(ptr)
- v0.AddArg(mem)
+ v.reset(OpAMD64XORLmem)
+ v.AuxInt = off
+ v.Aux = sym
+ v.AddArg(x)
+ v.AddArg(ptr)
+ v.AddArg(mem)
return true
}
// match: (XORL l:(MOVLload [off] {sym} ptr mem) x)
// cond: l.Uses == 1 && canMergeLoad(v, l) && clobber(l)
- // result: @l.Block (XORLmem <l.Type> x [off] {sym} ptr mem)
+ // result: (XORLmem x [off] {sym} ptr mem)
for {
l := v.Args[0]
if l.Op != OpAMD64MOVLload {
if !(l.Uses == 1 && canMergeLoad(v, l) && clobber(l)) {
break
}
- b = l.Block
- v0 := b.NewValue0(v.Pos, OpAMD64XORLmem, l.Type)
- v.reset(OpCopy)
- v.AddArg(v0)
- v0.AuxInt = off
- v0.Aux = sym
- v0.AddArg(x)
- v0.AddArg(ptr)
- v0.AddArg(mem)
+ v.reset(OpAMD64XORLmem)
+ v.AuxInt = off
+ v.Aux = sym
+ v.AddArg(x)
+ v.AddArg(ptr)
+ v.AddArg(mem)
return true
}
return false
}
// match: (XORQ x l:(MOVQload [off] {sym} ptr mem))
// cond: l.Uses == 1 && canMergeLoad(v, l) && clobber(l)
- // result: @l.Block (XORQmem <l.Type> x [off] {sym} ptr mem)
+ // result: (XORQmem x [off] {sym} ptr mem)
for {
x := v.Args[0]
l := v.Args[1]
if !(l.Uses == 1 && canMergeLoad(v, l) && clobber(l)) {
break
}
- b = l.Block
- v0 := b.NewValue0(v.Pos, OpAMD64XORQmem, l.Type)
- v.reset(OpCopy)
- v.AddArg(v0)
- v0.AuxInt = off
- v0.Aux = sym
- v0.AddArg(x)
- v0.AddArg(ptr)
- v0.AddArg(mem)
+ v.reset(OpAMD64XORQmem)
+ v.AuxInt = off
+ v.Aux = sym
+ v.AddArg(x)
+ v.AddArg(ptr)
+ v.AddArg(mem)
return true
}
// match: (XORQ l:(MOVQload [off] {sym} ptr mem) x)
// cond: l.Uses == 1 && canMergeLoad(v, l) && clobber(l)
- // result: @l.Block (XORQmem <l.Type> x [off] {sym} ptr mem)
+ // result: (XORQmem x [off] {sym} ptr mem)
for {
l := v.Args[0]
if l.Op != OpAMD64MOVQload {
if !(l.Uses == 1 && canMergeLoad(v, l) && clobber(l)) {
break
}
- b = l.Block
- v0 := b.NewValue0(v.Pos, OpAMD64XORQmem, l.Type)
- v.reset(OpCopy)
- v.AddArg(v0)
- v0.AuxInt = off
- v0.Aux = sym
- v0.AddArg(x)
- v0.AddArg(ptr)
- v0.AddArg(mem)
+ v.reset(OpAMD64XORQmem)
+ v.AuxInt = off
+ v.Aux = sym
+ v.AddArg(x)
+ v.AddArg(ptr)
+ v.AddArg(mem)
return true
}
return false