// if a register move has only 1 use, just use the same register without emitting instruction
// MOVWnop doesn't emit instruction, only for ensuring the type.
-(MOVWreg x) && x.Uses == 1 -> (MOVWnop x)
+(MOVWreg x) && x.Uses == 1 => (MOVWnop x)
// mul by constant
-(MUL x (MOVWconst [c])) && int32(c) == -1 -> (RSBconst [0] x)
-(MUL _ (MOVWconst [0])) -> (MOVWconst [0])
-(MUL x (MOVWconst [1])) -> x
-(MUL x (MOVWconst [c])) && isPowerOfTwo(c) -> (SLLconst [log2(c)] x)
-(MUL x (MOVWconst [c])) && isPowerOfTwo(c-1) && int32(c) >= 3 -> (ADDshiftLL x x [log2(c-1)])
-(MUL x (MOVWconst [c])) && isPowerOfTwo(c+1) && int32(c) >= 7 -> (RSBshiftLL x x [log2(c+1)])
-(MUL x (MOVWconst [c])) && c%3 == 0 && isPowerOfTwo(c/3) && is32Bit(c) -> (SLLconst [log2(c/3)] (ADDshiftLL <x.Type> x x [1]))
-(MUL x (MOVWconst [c])) && c%5 == 0 && isPowerOfTwo(c/5) && is32Bit(c) -> (SLLconst [log2(c/5)] (ADDshiftLL <x.Type> x x [2]))
-(MUL x (MOVWconst [c])) && c%7 == 0 && isPowerOfTwo(c/7) && is32Bit(c) -> (SLLconst [log2(c/7)] (RSBshiftLL <x.Type> x x [3]))
-(MUL x (MOVWconst [c])) && c%9 == 0 && isPowerOfTwo(c/9) && is32Bit(c) -> (SLLconst [log2(c/9)] (ADDshiftLL <x.Type> x x [3]))
-
-(MULA x (MOVWconst [c]) a) && int32(c) == -1 -> (SUB a x)
-(MULA _ (MOVWconst [0]) a) -> a
-(MULA x (MOVWconst [1]) a) -> (ADD x a)
-(MULA x (MOVWconst [c]) a) && isPowerOfTwo(c) -> (ADD (SLLconst <x.Type> [log2(c)] x) a)
-(MULA x (MOVWconst [c]) a) && isPowerOfTwo(c-1) && int32(c) >= 3 -> (ADD (ADDshiftLL <x.Type> x x [log2(c-1)]) a)
-(MULA x (MOVWconst [c]) a) && isPowerOfTwo(c+1) && int32(c) >= 7 -> (ADD (RSBshiftLL <x.Type> x x [log2(c+1)]) a)
-(MULA x (MOVWconst [c]) a) && c%3 == 0 && isPowerOfTwo(c/3) && is32Bit(c) -> (ADD (SLLconst <x.Type> [log2(c/3)] (ADDshiftLL <x.Type> x x [1])) a)
-(MULA x (MOVWconst [c]) a) && c%5 == 0 && isPowerOfTwo(c/5) && is32Bit(c) -> (ADD (SLLconst <x.Type> [log2(c/5)] (ADDshiftLL <x.Type> x x [2])) a)
-(MULA x (MOVWconst [c]) a) && c%7 == 0 && isPowerOfTwo(c/7) && is32Bit(c) -> (ADD (SLLconst <x.Type> [log2(c/7)] (RSBshiftLL <x.Type> x x [3])) a)
-(MULA x (MOVWconst [c]) a) && c%9 == 0 && isPowerOfTwo(c/9) && is32Bit(c) -> (ADD (SLLconst <x.Type> [log2(c/9)] (ADDshiftLL <x.Type> x x [3])) a)
-
-(MULA (MOVWconst [c]) x a) && int32(c) == -1 -> (SUB a x)
-(MULA (MOVWconst [0]) _ a) -> a
-(MULA (MOVWconst [1]) x a) -> (ADD x a)
-(MULA (MOVWconst [c]) x a) && isPowerOfTwo(c) -> (ADD (SLLconst <x.Type> [log2(c)] x) a)
-(MULA (MOVWconst [c]) x a) && isPowerOfTwo(c-1) && int32(c) >= 3 -> (ADD (ADDshiftLL <x.Type> x x [log2(c-1)]) a)
-(MULA (MOVWconst [c]) x a) && isPowerOfTwo(c+1) && int32(c) >= 7 -> (ADD (RSBshiftLL <x.Type> x x [log2(c+1)]) a)
-(MULA (MOVWconst [c]) x a) && c%3 == 0 && isPowerOfTwo(c/3) && is32Bit(c) -> (ADD (SLLconst <x.Type> [log2(c/3)] (ADDshiftLL <x.Type> x x [1])) a)
-(MULA (MOVWconst [c]) x a) && c%5 == 0 && isPowerOfTwo(c/5) && is32Bit(c) -> (ADD (SLLconst <x.Type> [log2(c/5)] (ADDshiftLL <x.Type> x x [2])) a)
-(MULA (MOVWconst [c]) x a) && c%7 == 0 && isPowerOfTwo(c/7) && is32Bit(c) -> (ADD (SLLconst <x.Type> [log2(c/7)] (RSBshiftLL <x.Type> x x [3])) a)
-(MULA (MOVWconst [c]) x a) && c%9 == 0 && isPowerOfTwo(c/9) && is32Bit(c) -> (ADD (SLLconst <x.Type> [log2(c/9)] (ADDshiftLL <x.Type> x x [3])) a)
-
-(MULS x (MOVWconst [c]) a) && int32(c) == -1 -> (ADD a x)
-(MULS _ (MOVWconst [0]) a) -> a
-(MULS x (MOVWconst [1]) a) -> (RSB x a)
-(MULS x (MOVWconst [c]) a) && isPowerOfTwo(c) -> (RSB (SLLconst <x.Type> [log2(c)] x) a)
-(MULS x (MOVWconst [c]) a) && isPowerOfTwo(c-1) && int32(c) >= 3 -> (RSB (ADDshiftLL <x.Type> x x [log2(c-1)]) a)
-(MULS x (MOVWconst [c]) a) && isPowerOfTwo(c+1) && int32(c) >= 7 -> (RSB (RSBshiftLL <x.Type> x x [log2(c+1)]) a)
-(MULS x (MOVWconst [c]) a) && c%3 == 0 && isPowerOfTwo(c/3) && is32Bit(c) -> (RSB (SLLconst <x.Type> [log2(c/3)] (ADDshiftLL <x.Type> x x [1])) a)
-(MULS x (MOVWconst [c]) a) && c%5 == 0 && isPowerOfTwo(c/5) && is32Bit(c) -> (RSB (SLLconst <x.Type> [log2(c/5)] (ADDshiftLL <x.Type> x x [2])) a)
-(MULS x (MOVWconst [c]) a) && c%7 == 0 && isPowerOfTwo(c/7) && is32Bit(c) -> (RSB (SLLconst <x.Type> [log2(c/7)] (RSBshiftLL <x.Type> x x [3])) a)
-(MULS x (MOVWconst [c]) a) && c%9 == 0 && isPowerOfTwo(c/9) && is32Bit(c) -> (RSB (SLLconst <x.Type> [log2(c/9)] (ADDshiftLL <x.Type> x x [3])) a)
-
-(MULS (MOVWconst [c]) x a) && int32(c) == -1 -> (ADD a x)
-(MULS (MOVWconst [0]) _ a) -> a
-(MULS (MOVWconst [1]) x a) -> (RSB x a)
-(MULS (MOVWconst [c]) x a) && isPowerOfTwo(c) -> (RSB (SLLconst <x.Type> [log2(c)] x) a)
-(MULS (MOVWconst [c]) x a) && isPowerOfTwo(c-1) && int32(c) >= 3 -> (RSB (ADDshiftLL <x.Type> x x [log2(c-1)]) a)
-(MULS (MOVWconst [c]) x a) && isPowerOfTwo(c+1) && int32(c) >= 7 -> (RSB (RSBshiftLL <x.Type> x x [log2(c+1)]) a)
-(MULS (MOVWconst [c]) x a) && c%3 == 0 && isPowerOfTwo(c/3) && is32Bit(c) -> (RSB (SLLconst <x.Type> [log2(c/3)] (ADDshiftLL <x.Type> x x [1])) a)
-(MULS (MOVWconst [c]) x a) && c%5 == 0 && isPowerOfTwo(c/5) && is32Bit(c) -> (RSB (SLLconst <x.Type> [log2(c/5)] (ADDshiftLL <x.Type> x x [2])) a)
-(MULS (MOVWconst [c]) x a) && c%7 == 0 && isPowerOfTwo(c/7) && is32Bit(c) -> (RSB (SLLconst <x.Type> [log2(c/7)] (RSBshiftLL <x.Type> x x [3])) a)
-(MULS (MOVWconst [c]) x a) && c%9 == 0 && isPowerOfTwo(c/9) && is32Bit(c) -> (RSB (SLLconst <x.Type> [log2(c/9)] (ADDshiftLL <x.Type> x x [3])) a)
+(MUL x (MOVWconst [c])) && int32(c) == -1 => (RSBconst [0] x)
+(MUL _ (MOVWconst [0])) => (MOVWconst [0])
+(MUL x (MOVWconst [1])) => x
+(MUL x (MOVWconst [c])) && isPowerOfTwo32(c) => (SLLconst [int32(log32(c))] x)
+(MUL x (MOVWconst [c])) && isPowerOfTwo32(c-1) && c >= 3 => (ADDshiftLL x x [int32(log32(c-1))])
+(MUL x (MOVWconst [c])) && isPowerOfTwo32(c+1) && c >= 7 => (RSBshiftLL x x [int32(log32(c+1))])
+(MUL x (MOVWconst [c])) && c%3 == 0 && isPowerOfTwo32(c/3) => (SLLconst [int32(log32(c/3))] (ADDshiftLL <x.Type> x x [1]))
+(MUL x (MOVWconst [c])) && c%5 == 0 && isPowerOfTwo32(c/5) => (SLLconst [int32(log32(c/5))] (ADDshiftLL <x.Type> x x [2]))
+(MUL x (MOVWconst [c])) && c%7 == 0 && isPowerOfTwo32(c/7) => (SLLconst [int32(log32(c/7))] (RSBshiftLL <x.Type> x x [3]))
+(MUL x (MOVWconst [c])) && c%9 == 0 && isPowerOfTwo32(c/9) => (SLLconst [int32(log32(c/9))] (ADDshiftLL <x.Type> x x [3]))
+
+(MULA x (MOVWconst [c]) a) && c == -1 => (SUB a x)
+(MULA _ (MOVWconst [0]) a) => a
+(MULA x (MOVWconst [1]) a) => (ADD x a)
+(MULA x (MOVWconst [c]) a) && isPowerOfTwo32(c) => (ADD (SLLconst <x.Type> [int32(log32(c))] x) a)
+(MULA x (MOVWconst [c]) a) && isPowerOfTwo32(c-1) && c >= 3 => (ADD (ADDshiftLL <x.Type> x x [int32(log32(c-1))]) a)
+(MULA x (MOVWconst [c]) a) && isPowerOfTwo32(c+1) && c >= 7 => (ADD (RSBshiftLL <x.Type> x x [int32(log32(c+1))]) a)
+(MULA x (MOVWconst [c]) a) && c%3 == 0 && isPowerOfTwo32(c/3) => (ADD (SLLconst <x.Type> [int32(log32(c/3))] (ADDshiftLL <x.Type> x x [1])) a)
+(MULA x (MOVWconst [c]) a) && c%5 == 0 && isPowerOfTwo32(c/5) => (ADD (SLLconst <x.Type> [int32(log32(c/5))] (ADDshiftLL <x.Type> x x [2])) a)
+(MULA x (MOVWconst [c]) a) && c%7 == 0 && isPowerOfTwo32(c/7) => (ADD (SLLconst <x.Type> [int32(log32(c/7))] (RSBshiftLL <x.Type> x x [3])) a)
+(MULA x (MOVWconst [c]) a) && c%9 == 0 && isPowerOfTwo32(c/9) => (ADD (SLLconst <x.Type> [int32(log32(c/9))] (ADDshiftLL <x.Type> x x [3])) a)
+
+(MULA (MOVWconst [c]) x a) && c == -1 => (SUB a x)
+(MULA (MOVWconst [0]) _ a) => a
+(MULA (MOVWconst [1]) x a) => (ADD x a)
+(MULA (MOVWconst [c]) x a) && isPowerOfTwo32(c) => (ADD (SLLconst <x.Type> [int32(log32(c))] x) a)
+(MULA (MOVWconst [c]) x a) && isPowerOfTwo32(c-1) && c >= 3 => (ADD (ADDshiftLL <x.Type> x x [int32(log32(c-1))]) a)
+(MULA (MOVWconst [c]) x a) && isPowerOfTwo32(c+1) && c >= 7 => (ADD (RSBshiftLL <x.Type> x x [int32(log32(c+1))]) a)
+(MULA (MOVWconst [c]) x a) && c%3 == 0 && isPowerOfTwo32(c/3) => (ADD (SLLconst <x.Type> [int32(log32(c/3))] (ADDshiftLL <x.Type> x x [1])) a)
+(MULA (MOVWconst [c]) x a) && c%5 == 0 && isPowerOfTwo32(c/5) => (ADD (SLLconst <x.Type> [int32(log32(c/5))] (ADDshiftLL <x.Type> x x [2])) a)
+(MULA (MOVWconst [c]) x a) && c%7 == 0 && isPowerOfTwo32(c/7) => (ADD (SLLconst <x.Type> [int32(log32(c/7))] (RSBshiftLL <x.Type> x x [3])) a)
+(MULA (MOVWconst [c]) x a) && c%9 == 0 && isPowerOfTwo32(c/9) => (ADD (SLLconst <x.Type> [int32(log32(c/9))] (ADDshiftLL <x.Type> x x [3])) a)
+
+(MULS x (MOVWconst [c]) a) && c == -1 => (ADD a x)
+(MULS _ (MOVWconst [0]) a) => a
+(MULS x (MOVWconst [1]) a) => (RSB x a)
+(MULS x (MOVWconst [c]) a) && isPowerOfTwo32(c) => (RSB (SLLconst <x.Type> [int32(log32(c))] x) a)
+(MULS x (MOVWconst [c]) a) && isPowerOfTwo32(c-1) && c >= 3 => (RSB (ADDshiftLL <x.Type> x x [int32(log32(c-1))]) a)
+(MULS x (MOVWconst [c]) a) && isPowerOfTwo32(c+1) && c >= 7 => (RSB (RSBshiftLL <x.Type> x x [int32(log32(c+1))]) a)
+(MULS x (MOVWconst [c]) a) && c%3 == 0 && isPowerOfTwo32(c/3) => (RSB (SLLconst <x.Type> [int32(log32(c/3))] (ADDshiftLL <x.Type> x x [1])) a)
+(MULS x (MOVWconst [c]) a) && c%5 == 0 && isPowerOfTwo32(c/5) => (RSB (SLLconst <x.Type> [int32(log32(c/5))] (ADDshiftLL <x.Type> x x [2])) a)
+(MULS x (MOVWconst [c]) a) && c%7 == 0 && isPowerOfTwo32(c/7) => (RSB (SLLconst <x.Type> [int32(log32(c/7))] (RSBshiftLL <x.Type> x x [3])) a)
+(MULS x (MOVWconst [c]) a) && c%9 == 0 && isPowerOfTwo32(c/9) => (RSB (SLLconst <x.Type> [int32(log32(c/9))] (ADDshiftLL <x.Type> x x [3])) a)
+
+(MULS (MOVWconst [c]) x a) && c == -1 => (ADD a x)
+(MULS (MOVWconst [0]) _ a) => a
+(MULS (MOVWconst [1]) x a) => (RSB x a)
+(MULS (MOVWconst [c]) x a) && isPowerOfTwo32(c) => (RSB (SLLconst <x.Type> [int32(log32(c))] x) a)
+(MULS (MOVWconst [c]) x a) && isPowerOfTwo32(c-1) && c >= 3 => (RSB (ADDshiftLL <x.Type> x x [int32(log32(c-1))]) a)
+(MULS (MOVWconst [c]) x a) && isPowerOfTwo32(c+1) && c >= 7 => (RSB (RSBshiftLL <x.Type> x x [int32(log32(c+1))]) a)
+(MULS (MOVWconst [c]) x a) && c%3 == 0 && isPowerOfTwo32(c/3) => (RSB (SLLconst <x.Type> [int32(log32(c/3))] (ADDshiftLL <x.Type> x x [1])) a)
+(MULS (MOVWconst [c]) x a) && c%5 == 0 && isPowerOfTwo32(c/5) => (RSB (SLLconst <x.Type> [int32(log32(c/5))] (ADDshiftLL <x.Type> x x [2])) a)
+(MULS (MOVWconst [c]) x a) && c%7 == 0 && isPowerOfTwo32(c/7) => (RSB (SLLconst <x.Type> [int32(log32(c/7))] (RSBshiftLL <x.Type> x x [3])) a)
+(MULS (MOVWconst [c]) x a) && c%9 == 0 && isPowerOfTwo32(c/9) => (RSB (SLLconst <x.Type> [int32(log32(c/9))] (ADDshiftLL <x.Type> x x [3])) a)
// div by constant
-(Select0 (CALLudiv x (MOVWconst [1]))) -> x
-(Select1 (CALLudiv _ (MOVWconst [1]))) -> (MOVWconst [0])
-(Select0 (CALLudiv x (MOVWconst [c]))) && isPowerOfTwo(c) -> (SRLconst [log2(c)] x)
-(Select1 (CALLudiv x (MOVWconst [c]))) && isPowerOfTwo(c) -> (ANDconst [c-1] x)
+(Select0 (CALLudiv x (MOVWconst [1]))) => x
+(Select1 (CALLudiv _ (MOVWconst [1]))) => (MOVWconst [0])
+(Select0 (CALLudiv x (MOVWconst [c]))) && isPowerOfTwo32(c) => (SRLconst [int32(log32(c))] x)
+(Select1 (CALLudiv x (MOVWconst [c]))) && isPowerOfTwo32(c) => (ANDconst [c-1] x)
// constant comparisons
(CMPconst (MOVWconst [x]) [y]) => (FlagConstant [subFlags32(x,y)])
if v_1.Op != OpARMMOVWconst {
continue
}
- c := v_1.AuxInt
+ c := auxIntToInt32(v_1.AuxInt)
if !(int32(c) == -1) {
continue
}
v.reset(OpARMRSBconst)
- v.AuxInt = 0
+ v.AuxInt = int32ToAuxInt(0)
v.AddArg(x)
return true
}
// result: (MOVWconst [0])
for {
for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
- if v_1.Op != OpARMMOVWconst || v_1.AuxInt != 0 {
+ if v_1.Op != OpARMMOVWconst || auxIntToInt32(v_1.AuxInt) != 0 {
continue
}
v.reset(OpARMMOVWconst)
- v.AuxInt = 0
+ v.AuxInt = int32ToAuxInt(0)
return true
}
break
for {
for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
x := v_0
- if v_1.Op != OpARMMOVWconst || v_1.AuxInt != 1 {
+ if v_1.Op != OpARMMOVWconst || auxIntToInt32(v_1.AuxInt) != 1 {
continue
}
v.copyOf(x)
break
}
// match: (MUL x (MOVWconst [c]))
- // cond: isPowerOfTwo(c)
- // result: (SLLconst [log2(c)] x)
+ // cond: isPowerOfTwo32(c)
+ // result: (SLLconst [int32(log32(c))] x)
for {
for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
x := v_0
if v_1.Op != OpARMMOVWconst {
continue
}
- c := v_1.AuxInt
- if !(isPowerOfTwo(c)) {
+ c := auxIntToInt32(v_1.AuxInt)
+ if !(isPowerOfTwo32(c)) {
continue
}
v.reset(OpARMSLLconst)
- v.AuxInt = log2(c)
+ v.AuxInt = int32ToAuxInt(int32(log32(c)))
v.AddArg(x)
return true
}
break
}
// match: (MUL x (MOVWconst [c]))
- // cond: isPowerOfTwo(c-1) && int32(c) >= 3
- // result: (ADDshiftLL x x [log2(c-1)])
+ // cond: isPowerOfTwo32(c-1) && c >= 3
+ // result: (ADDshiftLL x x [int32(log32(c-1))])
for {
for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
x := v_0
if v_1.Op != OpARMMOVWconst {
continue
}
- c := v_1.AuxInt
- if !(isPowerOfTwo(c-1) && int32(c) >= 3) {
+ c := auxIntToInt32(v_1.AuxInt)
+ if !(isPowerOfTwo32(c-1) && c >= 3) {
continue
}
v.reset(OpARMADDshiftLL)
- v.AuxInt = log2(c - 1)
+ v.AuxInt = int32ToAuxInt(int32(log32(c - 1)))
v.AddArg2(x, x)
return true
}
break
}
// match: (MUL x (MOVWconst [c]))
- // cond: isPowerOfTwo(c+1) && int32(c) >= 7
- // result: (RSBshiftLL x x [log2(c+1)])
+ // cond: isPowerOfTwo32(c+1) && c >= 7
+ // result: (RSBshiftLL x x [int32(log32(c+1))])
for {
for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
x := v_0
if v_1.Op != OpARMMOVWconst {
continue
}
- c := v_1.AuxInt
- if !(isPowerOfTwo(c+1) && int32(c) >= 7) {
+ c := auxIntToInt32(v_1.AuxInt)
+ if !(isPowerOfTwo32(c+1) && c >= 7) {
continue
}
v.reset(OpARMRSBshiftLL)
- v.AuxInt = log2(c + 1)
+ v.AuxInt = int32ToAuxInt(int32(log32(c + 1)))
v.AddArg2(x, x)
return true
}
break
}
// match: (MUL x (MOVWconst [c]))
- // cond: c%3 == 0 && isPowerOfTwo(c/3) && is32Bit(c)
- // result: (SLLconst [log2(c/3)] (ADDshiftLL <x.Type> x x [1]))
+ // cond: c%3 == 0 && isPowerOfTwo32(c/3)
+ // result: (SLLconst [int32(log32(c/3))] (ADDshiftLL <x.Type> x x [1]))
for {
for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
x := v_0
if v_1.Op != OpARMMOVWconst {
continue
}
- c := v_1.AuxInt
- if !(c%3 == 0 && isPowerOfTwo(c/3) && is32Bit(c)) {
+ c := auxIntToInt32(v_1.AuxInt)
+ if !(c%3 == 0 && isPowerOfTwo32(c/3)) {
continue
}
v.reset(OpARMSLLconst)
- v.AuxInt = log2(c / 3)
+ v.AuxInt = int32ToAuxInt(int32(log32(c / 3)))
v0 := b.NewValue0(v.Pos, OpARMADDshiftLL, x.Type)
- v0.AuxInt = 1
+ v0.AuxInt = int32ToAuxInt(1)
v0.AddArg2(x, x)
v.AddArg(v0)
return true
break
}
// match: (MUL x (MOVWconst [c]))
- // cond: c%5 == 0 && isPowerOfTwo(c/5) && is32Bit(c)
- // result: (SLLconst [log2(c/5)] (ADDshiftLL <x.Type> x x [2]))
+ // cond: c%5 == 0 && isPowerOfTwo32(c/5)
+ // result: (SLLconst [int32(log32(c/5))] (ADDshiftLL <x.Type> x x [2]))
for {
for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
x := v_0
if v_1.Op != OpARMMOVWconst {
continue
}
- c := v_1.AuxInt
- if !(c%5 == 0 && isPowerOfTwo(c/5) && is32Bit(c)) {
+ c := auxIntToInt32(v_1.AuxInt)
+ if !(c%5 == 0 && isPowerOfTwo32(c/5)) {
continue
}
v.reset(OpARMSLLconst)
- v.AuxInt = log2(c / 5)
+ v.AuxInt = int32ToAuxInt(int32(log32(c / 5)))
v0 := b.NewValue0(v.Pos, OpARMADDshiftLL, x.Type)
- v0.AuxInt = 2
+ v0.AuxInt = int32ToAuxInt(2)
v0.AddArg2(x, x)
v.AddArg(v0)
return true
break
}
// match: (MUL x (MOVWconst [c]))
- // cond: c%7 == 0 && isPowerOfTwo(c/7) && is32Bit(c)
- // result: (SLLconst [log2(c/7)] (RSBshiftLL <x.Type> x x [3]))
+ // cond: c%7 == 0 && isPowerOfTwo32(c/7)
+ // result: (SLLconst [int32(log32(c/7))] (RSBshiftLL <x.Type> x x [3]))
for {
for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
x := v_0
if v_1.Op != OpARMMOVWconst {
continue
}
- c := v_1.AuxInt
- if !(c%7 == 0 && isPowerOfTwo(c/7) && is32Bit(c)) {
+ c := auxIntToInt32(v_1.AuxInt)
+ if !(c%7 == 0 && isPowerOfTwo32(c/7)) {
continue
}
v.reset(OpARMSLLconst)
- v.AuxInt = log2(c / 7)
+ v.AuxInt = int32ToAuxInt(int32(log32(c / 7)))
v0 := b.NewValue0(v.Pos, OpARMRSBshiftLL, x.Type)
- v0.AuxInt = 3
+ v0.AuxInt = int32ToAuxInt(3)
v0.AddArg2(x, x)
v.AddArg(v0)
return true
break
}
// match: (MUL x (MOVWconst [c]))
- // cond: c%9 == 0 && isPowerOfTwo(c/9) && is32Bit(c)
- // result: (SLLconst [log2(c/9)] (ADDshiftLL <x.Type> x x [3]))
+ // cond: c%9 == 0 && isPowerOfTwo32(c/9)
+ // result: (SLLconst [int32(log32(c/9))] (ADDshiftLL <x.Type> x x [3]))
for {
for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
x := v_0
if v_1.Op != OpARMMOVWconst {
continue
}
- c := v_1.AuxInt
- if !(c%9 == 0 && isPowerOfTwo(c/9) && is32Bit(c)) {
+ c := auxIntToInt32(v_1.AuxInt)
+ if !(c%9 == 0 && isPowerOfTwo32(c/9)) {
continue
}
v.reset(OpARMSLLconst)
- v.AuxInt = log2(c / 9)
+ v.AuxInt = int32ToAuxInt(int32(log32(c / 9)))
v0 := b.NewValue0(v.Pos, OpARMADDshiftLL, x.Type)
- v0.AuxInt = 3
+ v0.AuxInt = int32ToAuxInt(3)
v0.AddArg2(x, x)
v.AddArg(v0)
return true
v_0 := v.Args[0]
b := v.Block
// match: (MULA x (MOVWconst [c]) a)
- // cond: int32(c) == -1
+ // cond: c == -1
// result: (SUB a x)
for {
x := v_0
if v_1.Op != OpARMMOVWconst {
break
}
- c := v_1.AuxInt
+ c := auxIntToInt32(v_1.AuxInt)
a := v_2
- if !(int32(c) == -1) {
+ if !(c == -1) {
break
}
v.reset(OpARMSUB)
// match: (MULA _ (MOVWconst [0]) a)
// result: a
for {
- if v_1.Op != OpARMMOVWconst || v_1.AuxInt != 0 {
+ if v_1.Op != OpARMMOVWconst || auxIntToInt32(v_1.AuxInt) != 0 {
break
}
a := v_2
// result: (ADD x a)
for {
x := v_0
- if v_1.Op != OpARMMOVWconst || v_1.AuxInt != 1 {
+ if v_1.Op != OpARMMOVWconst || auxIntToInt32(v_1.AuxInt) != 1 {
break
}
a := v_2
return true
}
// match: (MULA x (MOVWconst [c]) a)
- // cond: isPowerOfTwo(c)
- // result: (ADD (SLLconst <x.Type> [log2(c)] x) a)
+ // cond: isPowerOfTwo32(c)
+ // result: (ADD (SLLconst <x.Type> [int32(log32(c))] x) a)
for {
x := v_0
if v_1.Op != OpARMMOVWconst {
break
}
- c := v_1.AuxInt
+ c := auxIntToInt32(v_1.AuxInt)
a := v_2
- if !(isPowerOfTwo(c)) {
+ if !(isPowerOfTwo32(c)) {
break
}
v.reset(OpARMADD)
v0 := b.NewValue0(v.Pos, OpARMSLLconst, x.Type)
- v0.AuxInt = log2(c)
+ v0.AuxInt = int32ToAuxInt(int32(log32(c)))
v0.AddArg(x)
v.AddArg2(v0, a)
return true
}
// match: (MULA x (MOVWconst [c]) a)
- // cond: isPowerOfTwo(c-1) && int32(c) >= 3
- // result: (ADD (ADDshiftLL <x.Type> x x [log2(c-1)]) a)
+ // cond: isPowerOfTwo32(c-1) && c >= 3
+ // result: (ADD (ADDshiftLL <x.Type> x x [int32(log32(c-1))]) a)
for {
x := v_0
if v_1.Op != OpARMMOVWconst {
break
}
- c := v_1.AuxInt
+ c := auxIntToInt32(v_1.AuxInt)
a := v_2
- if !(isPowerOfTwo(c-1) && int32(c) >= 3) {
+ if !(isPowerOfTwo32(c-1) && c >= 3) {
break
}
v.reset(OpARMADD)
v0 := b.NewValue0(v.Pos, OpARMADDshiftLL, x.Type)
- v0.AuxInt = log2(c - 1)
+ v0.AuxInt = int32ToAuxInt(int32(log32(c - 1)))
v0.AddArg2(x, x)
v.AddArg2(v0, a)
return true
}
// match: (MULA x (MOVWconst [c]) a)
- // cond: isPowerOfTwo(c+1) && int32(c) >= 7
- // result: (ADD (RSBshiftLL <x.Type> x x [log2(c+1)]) a)
+ // cond: isPowerOfTwo32(c+1) && c >= 7
+ // result: (ADD (RSBshiftLL <x.Type> x x [int32(log32(c+1))]) a)
for {
x := v_0
if v_1.Op != OpARMMOVWconst {
break
}
- c := v_1.AuxInt
+ c := auxIntToInt32(v_1.AuxInt)
a := v_2
- if !(isPowerOfTwo(c+1) && int32(c) >= 7) {
+ if !(isPowerOfTwo32(c+1) && c >= 7) {
break
}
v.reset(OpARMADD)
v0 := b.NewValue0(v.Pos, OpARMRSBshiftLL, x.Type)
- v0.AuxInt = log2(c + 1)
+ v0.AuxInt = int32ToAuxInt(int32(log32(c + 1)))
v0.AddArg2(x, x)
v.AddArg2(v0, a)
return true
}
// match: (MULA x (MOVWconst [c]) a)
- // cond: c%3 == 0 && isPowerOfTwo(c/3) && is32Bit(c)
- // result: (ADD (SLLconst <x.Type> [log2(c/3)] (ADDshiftLL <x.Type> x x [1])) a)
+ // cond: c%3 == 0 && isPowerOfTwo32(c/3)
+ // result: (ADD (SLLconst <x.Type> [int32(log32(c/3))] (ADDshiftLL <x.Type> x x [1])) a)
for {
x := v_0
if v_1.Op != OpARMMOVWconst {
break
}
- c := v_1.AuxInt
+ c := auxIntToInt32(v_1.AuxInt)
a := v_2
- if !(c%3 == 0 && isPowerOfTwo(c/3) && is32Bit(c)) {
+ if !(c%3 == 0 && isPowerOfTwo32(c/3)) {
break
}
v.reset(OpARMADD)
v0 := b.NewValue0(v.Pos, OpARMSLLconst, x.Type)
- v0.AuxInt = log2(c / 3)
+ v0.AuxInt = int32ToAuxInt(int32(log32(c / 3)))
v1 := b.NewValue0(v.Pos, OpARMADDshiftLL, x.Type)
- v1.AuxInt = 1
+ v1.AuxInt = int32ToAuxInt(1)
v1.AddArg2(x, x)
v0.AddArg(v1)
v.AddArg2(v0, a)
return true
}
// match: (MULA x (MOVWconst [c]) a)
- // cond: c%5 == 0 && isPowerOfTwo(c/5) && is32Bit(c)
- // result: (ADD (SLLconst <x.Type> [log2(c/5)] (ADDshiftLL <x.Type> x x [2])) a)
+ // cond: c%5 == 0 && isPowerOfTwo32(c/5)
+ // result: (ADD (SLLconst <x.Type> [int32(log32(c/5))] (ADDshiftLL <x.Type> x x [2])) a)
for {
x := v_0
if v_1.Op != OpARMMOVWconst {
break
}
- c := v_1.AuxInt
+ c := auxIntToInt32(v_1.AuxInt)
a := v_2
- if !(c%5 == 0 && isPowerOfTwo(c/5) && is32Bit(c)) {
+ if !(c%5 == 0 && isPowerOfTwo32(c/5)) {
break
}
v.reset(OpARMADD)
v0 := b.NewValue0(v.Pos, OpARMSLLconst, x.Type)
- v0.AuxInt = log2(c / 5)
+ v0.AuxInt = int32ToAuxInt(int32(log32(c / 5)))
v1 := b.NewValue0(v.Pos, OpARMADDshiftLL, x.Type)
- v1.AuxInt = 2
+ v1.AuxInt = int32ToAuxInt(2)
v1.AddArg2(x, x)
v0.AddArg(v1)
v.AddArg2(v0, a)
return true
}
// match: (MULA x (MOVWconst [c]) a)
- // cond: c%7 == 0 && isPowerOfTwo(c/7) && is32Bit(c)
- // result: (ADD (SLLconst <x.Type> [log2(c/7)] (RSBshiftLL <x.Type> x x [3])) a)
+ // cond: c%7 == 0 && isPowerOfTwo32(c/7)
+ // result: (ADD (SLLconst <x.Type> [int32(log32(c/7))] (RSBshiftLL <x.Type> x x [3])) a)
for {
x := v_0
if v_1.Op != OpARMMOVWconst {
break
}
- c := v_1.AuxInt
+ c := auxIntToInt32(v_1.AuxInt)
a := v_2
- if !(c%7 == 0 && isPowerOfTwo(c/7) && is32Bit(c)) {
+ if !(c%7 == 0 && isPowerOfTwo32(c/7)) {
break
}
v.reset(OpARMADD)
v0 := b.NewValue0(v.Pos, OpARMSLLconst, x.Type)
- v0.AuxInt = log2(c / 7)
+ v0.AuxInt = int32ToAuxInt(int32(log32(c / 7)))
v1 := b.NewValue0(v.Pos, OpARMRSBshiftLL, x.Type)
- v1.AuxInt = 3
+ v1.AuxInt = int32ToAuxInt(3)
v1.AddArg2(x, x)
v0.AddArg(v1)
v.AddArg2(v0, a)
return true
}
// match: (MULA x (MOVWconst [c]) a)
- // cond: c%9 == 0 && isPowerOfTwo(c/9) && is32Bit(c)
- // result: (ADD (SLLconst <x.Type> [log2(c/9)] (ADDshiftLL <x.Type> x x [3])) a)
+ // cond: c%9 == 0 && isPowerOfTwo32(c/9)
+ // result: (ADD (SLLconst <x.Type> [int32(log32(c/9))] (ADDshiftLL <x.Type> x x [3])) a)
for {
x := v_0
if v_1.Op != OpARMMOVWconst {
break
}
- c := v_1.AuxInt
+ c := auxIntToInt32(v_1.AuxInt)
a := v_2
- if !(c%9 == 0 && isPowerOfTwo(c/9) && is32Bit(c)) {
+ if !(c%9 == 0 && isPowerOfTwo32(c/9)) {
break
}
v.reset(OpARMADD)
v0 := b.NewValue0(v.Pos, OpARMSLLconst, x.Type)
- v0.AuxInt = log2(c / 9)
+ v0.AuxInt = int32ToAuxInt(int32(log32(c / 9)))
v1 := b.NewValue0(v.Pos, OpARMADDshiftLL, x.Type)
- v1.AuxInt = 3
+ v1.AuxInt = int32ToAuxInt(3)
v1.AddArg2(x, x)
v0.AddArg(v1)
v.AddArg2(v0, a)
return true
}
// match: (MULA (MOVWconst [c]) x a)
- // cond: int32(c) == -1
+ // cond: c == -1
// result: (SUB a x)
for {
if v_0.Op != OpARMMOVWconst {
break
}
- c := v_0.AuxInt
+ c := auxIntToInt32(v_0.AuxInt)
x := v_1
a := v_2
- if !(int32(c) == -1) {
+ if !(c == -1) {
break
}
v.reset(OpARMSUB)
// match: (MULA (MOVWconst [0]) _ a)
// result: a
for {
- if v_0.Op != OpARMMOVWconst || v_0.AuxInt != 0 {
+ if v_0.Op != OpARMMOVWconst || auxIntToInt32(v_0.AuxInt) != 0 {
break
}
a := v_2
// match: (MULA (MOVWconst [1]) x a)
// result: (ADD x a)
for {
- if v_0.Op != OpARMMOVWconst || v_0.AuxInt != 1 {
+ if v_0.Op != OpARMMOVWconst || auxIntToInt32(v_0.AuxInt) != 1 {
break
}
x := v_1
return true
}
// match: (MULA (MOVWconst [c]) x a)
- // cond: isPowerOfTwo(c)
- // result: (ADD (SLLconst <x.Type> [log2(c)] x) a)
+ // cond: isPowerOfTwo32(c)
+ // result: (ADD (SLLconst <x.Type> [int32(log32(c))] x) a)
for {
if v_0.Op != OpARMMOVWconst {
break
}
- c := v_0.AuxInt
+ c := auxIntToInt32(v_0.AuxInt)
x := v_1
a := v_2
- if !(isPowerOfTwo(c)) {
+ if !(isPowerOfTwo32(c)) {
break
}
v.reset(OpARMADD)
v0 := b.NewValue0(v.Pos, OpARMSLLconst, x.Type)
- v0.AuxInt = log2(c)
+ v0.AuxInt = int32ToAuxInt(int32(log32(c)))
v0.AddArg(x)
v.AddArg2(v0, a)
return true
}
// match: (MULA (MOVWconst [c]) x a)
- // cond: isPowerOfTwo(c-1) && int32(c) >= 3
- // result: (ADD (ADDshiftLL <x.Type> x x [log2(c-1)]) a)
+ // cond: isPowerOfTwo32(c-1) && c >= 3
+ // result: (ADD (ADDshiftLL <x.Type> x x [int32(log32(c-1))]) a)
for {
if v_0.Op != OpARMMOVWconst {
break
}
- c := v_0.AuxInt
+ c := auxIntToInt32(v_0.AuxInt)
x := v_1
a := v_2
- if !(isPowerOfTwo(c-1) && int32(c) >= 3) {
+ if !(isPowerOfTwo32(c-1) && c >= 3) {
break
}
v.reset(OpARMADD)
v0 := b.NewValue0(v.Pos, OpARMADDshiftLL, x.Type)
- v0.AuxInt = log2(c - 1)
+ v0.AuxInt = int32ToAuxInt(int32(log32(c - 1)))
v0.AddArg2(x, x)
v.AddArg2(v0, a)
return true
}
// match: (MULA (MOVWconst [c]) x a)
- // cond: isPowerOfTwo(c+1) && int32(c) >= 7
- // result: (ADD (RSBshiftLL <x.Type> x x [log2(c+1)]) a)
+ // cond: isPowerOfTwo32(c+1) && c >= 7
+ // result: (ADD (RSBshiftLL <x.Type> x x [int32(log32(c+1))]) a)
for {
if v_0.Op != OpARMMOVWconst {
break
}
- c := v_0.AuxInt
+ c := auxIntToInt32(v_0.AuxInt)
x := v_1
a := v_2
- if !(isPowerOfTwo(c+1) && int32(c) >= 7) {
+ if !(isPowerOfTwo32(c+1) && c >= 7) {
break
}
v.reset(OpARMADD)
v0 := b.NewValue0(v.Pos, OpARMRSBshiftLL, x.Type)
- v0.AuxInt = log2(c + 1)
+ v0.AuxInt = int32ToAuxInt(int32(log32(c + 1)))
v0.AddArg2(x, x)
v.AddArg2(v0, a)
return true
}
// match: (MULA (MOVWconst [c]) x a)
- // cond: c%3 == 0 && isPowerOfTwo(c/3) && is32Bit(c)
- // result: (ADD (SLLconst <x.Type> [log2(c/3)] (ADDshiftLL <x.Type> x x [1])) a)
+ // cond: c%3 == 0 && isPowerOfTwo32(c/3)
+ // result: (ADD (SLLconst <x.Type> [int32(log32(c/3))] (ADDshiftLL <x.Type> x x [1])) a)
for {
if v_0.Op != OpARMMOVWconst {
break
}
- c := v_0.AuxInt
+ c := auxIntToInt32(v_0.AuxInt)
x := v_1
a := v_2
- if !(c%3 == 0 && isPowerOfTwo(c/3) && is32Bit(c)) {
+ if !(c%3 == 0 && isPowerOfTwo32(c/3)) {
break
}
v.reset(OpARMADD)
v0 := b.NewValue0(v.Pos, OpARMSLLconst, x.Type)
- v0.AuxInt = log2(c / 3)
+ v0.AuxInt = int32ToAuxInt(int32(log32(c / 3)))
v1 := b.NewValue0(v.Pos, OpARMADDshiftLL, x.Type)
- v1.AuxInt = 1
+ v1.AuxInt = int32ToAuxInt(1)
v1.AddArg2(x, x)
v0.AddArg(v1)
v.AddArg2(v0, a)
return true
}
// match: (MULA (MOVWconst [c]) x a)
- // cond: c%5 == 0 && isPowerOfTwo(c/5) && is32Bit(c)
- // result: (ADD (SLLconst <x.Type> [log2(c/5)] (ADDshiftLL <x.Type> x x [2])) a)
+ // cond: c%5 == 0 && isPowerOfTwo32(c/5)
+ // result: (ADD (SLLconst <x.Type> [int32(log32(c/5))] (ADDshiftLL <x.Type> x x [2])) a)
for {
if v_0.Op != OpARMMOVWconst {
break
}
- c := v_0.AuxInt
+ c := auxIntToInt32(v_0.AuxInt)
x := v_1
a := v_2
- if !(c%5 == 0 && isPowerOfTwo(c/5) && is32Bit(c)) {
+ if !(c%5 == 0 && isPowerOfTwo32(c/5)) {
break
}
v.reset(OpARMADD)
v0 := b.NewValue0(v.Pos, OpARMSLLconst, x.Type)
- v0.AuxInt = log2(c / 5)
+ v0.AuxInt = int32ToAuxInt(int32(log32(c / 5)))
v1 := b.NewValue0(v.Pos, OpARMADDshiftLL, x.Type)
- v1.AuxInt = 2
+ v1.AuxInt = int32ToAuxInt(2)
v1.AddArg2(x, x)
v0.AddArg(v1)
v.AddArg2(v0, a)
return true
}
// match: (MULA (MOVWconst [c]) x a)
- // cond: c%7 == 0 && isPowerOfTwo(c/7) && is32Bit(c)
- // result: (ADD (SLLconst <x.Type> [log2(c/7)] (RSBshiftLL <x.Type> x x [3])) a)
+ // cond: c%7 == 0 && isPowerOfTwo32(c/7)
+ // result: (ADD (SLLconst <x.Type> [int32(log32(c/7))] (RSBshiftLL <x.Type> x x [3])) a)
for {
if v_0.Op != OpARMMOVWconst {
break
}
- c := v_0.AuxInt
+ c := auxIntToInt32(v_0.AuxInt)
x := v_1
a := v_2
- if !(c%7 == 0 && isPowerOfTwo(c/7) && is32Bit(c)) {
+ if !(c%7 == 0 && isPowerOfTwo32(c/7)) {
break
}
v.reset(OpARMADD)
v0 := b.NewValue0(v.Pos, OpARMSLLconst, x.Type)
- v0.AuxInt = log2(c / 7)
+ v0.AuxInt = int32ToAuxInt(int32(log32(c / 7)))
v1 := b.NewValue0(v.Pos, OpARMRSBshiftLL, x.Type)
- v1.AuxInt = 3
+ v1.AuxInt = int32ToAuxInt(3)
v1.AddArg2(x, x)
v0.AddArg(v1)
v.AddArg2(v0, a)
return true
}
// match: (MULA (MOVWconst [c]) x a)
- // cond: c%9 == 0 && isPowerOfTwo(c/9) && is32Bit(c)
- // result: (ADD (SLLconst <x.Type> [log2(c/9)] (ADDshiftLL <x.Type> x x [3])) a)
+ // cond: c%9 == 0 && isPowerOfTwo32(c/9)
+ // result: (ADD (SLLconst <x.Type> [int32(log32(c/9))] (ADDshiftLL <x.Type> x x [3])) a)
for {
if v_0.Op != OpARMMOVWconst {
break
}
- c := v_0.AuxInt
+ c := auxIntToInt32(v_0.AuxInt)
x := v_1
a := v_2
- if !(c%9 == 0 && isPowerOfTwo(c/9) && is32Bit(c)) {
+ if !(c%9 == 0 && isPowerOfTwo32(c/9)) {
break
}
v.reset(OpARMADD)
v0 := b.NewValue0(v.Pos, OpARMSLLconst, x.Type)
- v0.AuxInt = log2(c / 9)
+ v0.AuxInt = int32ToAuxInt(int32(log32(c / 9)))
v1 := b.NewValue0(v.Pos, OpARMADDshiftLL, x.Type)
- v1.AuxInt = 3
+ v1.AuxInt = int32ToAuxInt(3)
v1.AddArg2(x, x)
v0.AddArg(v1)
v.AddArg2(v0, a)
v_0 := v.Args[0]
b := v.Block
// match: (MULS x (MOVWconst [c]) a)
- // cond: int32(c) == -1
+ // cond: c == -1
// result: (ADD a x)
for {
x := v_0
if v_1.Op != OpARMMOVWconst {
break
}
- c := v_1.AuxInt
+ c := auxIntToInt32(v_1.AuxInt)
a := v_2
- if !(int32(c) == -1) {
+ if !(c == -1) {
break
}
v.reset(OpARMADD)
// match: (MULS _ (MOVWconst [0]) a)
// result: a
for {
- if v_1.Op != OpARMMOVWconst || v_1.AuxInt != 0 {
+ if v_1.Op != OpARMMOVWconst || auxIntToInt32(v_1.AuxInt) != 0 {
break
}
a := v_2
// result: (RSB x a)
for {
x := v_0
- if v_1.Op != OpARMMOVWconst || v_1.AuxInt != 1 {
+ if v_1.Op != OpARMMOVWconst || auxIntToInt32(v_1.AuxInt) != 1 {
break
}
a := v_2
return true
}
// match: (MULS x (MOVWconst [c]) a)
- // cond: isPowerOfTwo(c)
- // result: (RSB (SLLconst <x.Type> [log2(c)] x) a)
+ // cond: isPowerOfTwo32(c)
+ // result: (RSB (SLLconst <x.Type> [int32(log32(c))] x) a)
for {
x := v_0
if v_1.Op != OpARMMOVWconst {
break
}
- c := v_1.AuxInt
+ c := auxIntToInt32(v_1.AuxInt)
a := v_2
- if !(isPowerOfTwo(c)) {
+ if !(isPowerOfTwo32(c)) {
break
}
v.reset(OpARMRSB)
v0 := b.NewValue0(v.Pos, OpARMSLLconst, x.Type)
- v0.AuxInt = log2(c)
+ v0.AuxInt = int32ToAuxInt(int32(log32(c)))
v0.AddArg(x)
v.AddArg2(v0, a)
return true
}
// match: (MULS x (MOVWconst [c]) a)
- // cond: isPowerOfTwo(c-1) && int32(c) >= 3
- // result: (RSB (ADDshiftLL <x.Type> x x [log2(c-1)]) a)
+ // cond: isPowerOfTwo32(c-1) && c >= 3
+ // result: (RSB (ADDshiftLL <x.Type> x x [int32(log32(c-1))]) a)
for {
x := v_0
if v_1.Op != OpARMMOVWconst {
break
}
- c := v_1.AuxInt
+ c := auxIntToInt32(v_1.AuxInt)
a := v_2
- if !(isPowerOfTwo(c-1) && int32(c) >= 3) {
+ if !(isPowerOfTwo32(c-1) && c >= 3) {
break
}
v.reset(OpARMRSB)
v0 := b.NewValue0(v.Pos, OpARMADDshiftLL, x.Type)
- v0.AuxInt = log2(c - 1)
+ v0.AuxInt = int32ToAuxInt(int32(log32(c - 1)))
v0.AddArg2(x, x)
v.AddArg2(v0, a)
return true
}
// match: (MULS x (MOVWconst [c]) a)
- // cond: isPowerOfTwo(c+1) && int32(c) >= 7
- // result: (RSB (RSBshiftLL <x.Type> x x [log2(c+1)]) a)
+ // cond: isPowerOfTwo32(c+1) && c >= 7
+ // result: (RSB (RSBshiftLL <x.Type> x x [int32(log32(c+1))]) a)
for {
x := v_0
if v_1.Op != OpARMMOVWconst {
break
}
- c := v_1.AuxInt
+ c := auxIntToInt32(v_1.AuxInt)
a := v_2
- if !(isPowerOfTwo(c+1) && int32(c) >= 7) {
+ if !(isPowerOfTwo32(c+1) && c >= 7) {
break
}
v.reset(OpARMRSB)
v0 := b.NewValue0(v.Pos, OpARMRSBshiftLL, x.Type)
- v0.AuxInt = log2(c + 1)
+ v0.AuxInt = int32ToAuxInt(int32(log32(c + 1)))
v0.AddArg2(x, x)
v.AddArg2(v0, a)
return true
}
// match: (MULS x (MOVWconst [c]) a)
- // cond: c%3 == 0 && isPowerOfTwo(c/3) && is32Bit(c)
- // result: (RSB (SLLconst <x.Type> [log2(c/3)] (ADDshiftLL <x.Type> x x [1])) a)
+ // cond: c%3 == 0 && isPowerOfTwo32(c/3)
+ // result: (RSB (SLLconst <x.Type> [int32(log32(c/3))] (ADDshiftLL <x.Type> x x [1])) a)
for {
x := v_0
if v_1.Op != OpARMMOVWconst {
break
}
- c := v_1.AuxInt
+ c := auxIntToInt32(v_1.AuxInt)
a := v_2
- if !(c%3 == 0 && isPowerOfTwo(c/3) && is32Bit(c)) {
+ if !(c%3 == 0 && isPowerOfTwo32(c/3)) {
break
}
v.reset(OpARMRSB)
v0 := b.NewValue0(v.Pos, OpARMSLLconst, x.Type)
- v0.AuxInt = log2(c / 3)
+ v0.AuxInt = int32ToAuxInt(int32(log32(c / 3)))
v1 := b.NewValue0(v.Pos, OpARMADDshiftLL, x.Type)
- v1.AuxInt = 1
+ v1.AuxInt = int32ToAuxInt(1)
v1.AddArg2(x, x)
v0.AddArg(v1)
v.AddArg2(v0, a)
return true
}
// match: (MULS x (MOVWconst [c]) a)
- // cond: c%5 == 0 && isPowerOfTwo(c/5) && is32Bit(c)
- // result: (RSB (SLLconst <x.Type> [log2(c/5)] (ADDshiftLL <x.Type> x x [2])) a)
+ // cond: c%5 == 0 && isPowerOfTwo32(c/5)
+ // result: (RSB (SLLconst <x.Type> [int32(log32(c/5))] (ADDshiftLL <x.Type> x x [2])) a)
for {
x := v_0
if v_1.Op != OpARMMOVWconst {
break
}
- c := v_1.AuxInt
+ c := auxIntToInt32(v_1.AuxInt)
a := v_2
- if !(c%5 == 0 && isPowerOfTwo(c/5) && is32Bit(c)) {
+ if !(c%5 == 0 && isPowerOfTwo32(c/5)) {
break
}
v.reset(OpARMRSB)
v0 := b.NewValue0(v.Pos, OpARMSLLconst, x.Type)
- v0.AuxInt = log2(c / 5)
+ v0.AuxInt = int32ToAuxInt(int32(log32(c / 5)))
v1 := b.NewValue0(v.Pos, OpARMADDshiftLL, x.Type)
- v1.AuxInt = 2
+ v1.AuxInt = int32ToAuxInt(2)
v1.AddArg2(x, x)
v0.AddArg(v1)
v.AddArg2(v0, a)
return true
}
// match: (MULS x (MOVWconst [c]) a)
- // cond: c%7 == 0 && isPowerOfTwo(c/7) && is32Bit(c)
- // result: (RSB (SLLconst <x.Type> [log2(c/7)] (RSBshiftLL <x.Type> x x [3])) a)
+ // cond: c%7 == 0 && isPowerOfTwo32(c/7)
+ // result: (RSB (SLLconst <x.Type> [int32(log32(c/7))] (RSBshiftLL <x.Type> x x [3])) a)
for {
x := v_0
if v_1.Op != OpARMMOVWconst {
break
}
- c := v_1.AuxInt
+ c := auxIntToInt32(v_1.AuxInt)
a := v_2
- if !(c%7 == 0 && isPowerOfTwo(c/7) && is32Bit(c)) {
+ if !(c%7 == 0 && isPowerOfTwo32(c/7)) {
break
}
v.reset(OpARMRSB)
v0 := b.NewValue0(v.Pos, OpARMSLLconst, x.Type)
- v0.AuxInt = log2(c / 7)
+ v0.AuxInt = int32ToAuxInt(int32(log32(c / 7)))
v1 := b.NewValue0(v.Pos, OpARMRSBshiftLL, x.Type)
- v1.AuxInt = 3
+ v1.AuxInt = int32ToAuxInt(3)
v1.AddArg2(x, x)
v0.AddArg(v1)
v.AddArg2(v0, a)
return true
}
// match: (MULS x (MOVWconst [c]) a)
- // cond: c%9 == 0 && isPowerOfTwo(c/9) && is32Bit(c)
- // result: (RSB (SLLconst <x.Type> [log2(c/9)] (ADDshiftLL <x.Type> x x [3])) a)
+ // cond: c%9 == 0 && isPowerOfTwo32(c/9)
+ // result: (RSB (SLLconst <x.Type> [int32(log32(c/9))] (ADDshiftLL <x.Type> x x [3])) a)
for {
x := v_0
if v_1.Op != OpARMMOVWconst {
break
}
- c := v_1.AuxInt
+ c := auxIntToInt32(v_1.AuxInt)
a := v_2
- if !(c%9 == 0 && isPowerOfTwo(c/9) && is32Bit(c)) {
+ if !(c%9 == 0 && isPowerOfTwo32(c/9)) {
break
}
v.reset(OpARMRSB)
v0 := b.NewValue0(v.Pos, OpARMSLLconst, x.Type)
- v0.AuxInt = log2(c / 9)
+ v0.AuxInt = int32ToAuxInt(int32(log32(c / 9)))
v1 := b.NewValue0(v.Pos, OpARMADDshiftLL, x.Type)
- v1.AuxInt = 3
+ v1.AuxInt = int32ToAuxInt(3)
v1.AddArg2(x, x)
v0.AddArg(v1)
v.AddArg2(v0, a)
return true
}
// match: (MULS (MOVWconst [c]) x a)
- // cond: int32(c) == -1
+ // cond: c == -1
// result: (ADD a x)
for {
if v_0.Op != OpARMMOVWconst {
break
}
- c := v_0.AuxInt
+ c := auxIntToInt32(v_0.AuxInt)
x := v_1
a := v_2
- if !(int32(c) == -1) {
+ if !(c == -1) {
break
}
v.reset(OpARMADD)
// match: (MULS (MOVWconst [0]) _ a)
// result: a
for {
- if v_0.Op != OpARMMOVWconst || v_0.AuxInt != 0 {
+ if v_0.Op != OpARMMOVWconst || auxIntToInt32(v_0.AuxInt) != 0 {
break
}
a := v_2
// match: (MULS (MOVWconst [1]) x a)
// result: (RSB x a)
for {
- if v_0.Op != OpARMMOVWconst || v_0.AuxInt != 1 {
+ if v_0.Op != OpARMMOVWconst || auxIntToInt32(v_0.AuxInt) != 1 {
break
}
x := v_1
return true
}
// match: (MULS (MOVWconst [c]) x a)
- // cond: isPowerOfTwo(c)
- // result: (RSB (SLLconst <x.Type> [log2(c)] x) a)
+ // cond: isPowerOfTwo32(c)
+ // result: (RSB (SLLconst <x.Type> [int32(log32(c))] x) a)
for {
if v_0.Op != OpARMMOVWconst {
break
}
- c := v_0.AuxInt
+ c := auxIntToInt32(v_0.AuxInt)
x := v_1
a := v_2
- if !(isPowerOfTwo(c)) {
+ if !(isPowerOfTwo32(c)) {
break
}
v.reset(OpARMRSB)
v0 := b.NewValue0(v.Pos, OpARMSLLconst, x.Type)
- v0.AuxInt = log2(c)
+ v0.AuxInt = int32ToAuxInt(int32(log32(c)))
v0.AddArg(x)
v.AddArg2(v0, a)
return true
}
// match: (MULS (MOVWconst [c]) x a)
- // cond: isPowerOfTwo(c-1) && int32(c) >= 3
- // result: (RSB (ADDshiftLL <x.Type> x x [log2(c-1)]) a)
+ // cond: isPowerOfTwo32(c-1) && c >= 3
+ // result: (RSB (ADDshiftLL <x.Type> x x [int32(log32(c-1))]) a)
for {
if v_0.Op != OpARMMOVWconst {
break
}
- c := v_0.AuxInt
+ c := auxIntToInt32(v_0.AuxInt)
x := v_1
a := v_2
- if !(isPowerOfTwo(c-1) && int32(c) >= 3) {
+ if !(isPowerOfTwo32(c-1) && c >= 3) {
break
}
v.reset(OpARMRSB)
v0 := b.NewValue0(v.Pos, OpARMADDshiftLL, x.Type)
- v0.AuxInt = log2(c - 1)
+ v0.AuxInt = int32ToAuxInt(int32(log32(c - 1)))
v0.AddArg2(x, x)
v.AddArg2(v0, a)
return true
}
// match: (MULS (MOVWconst [c]) x a)
- // cond: isPowerOfTwo(c+1) && int32(c) >= 7
- // result: (RSB (RSBshiftLL <x.Type> x x [log2(c+1)]) a)
+ // cond: isPowerOfTwo32(c+1) && c >= 7
+ // result: (RSB (RSBshiftLL <x.Type> x x [int32(log32(c+1))]) a)
for {
if v_0.Op != OpARMMOVWconst {
break
}
- c := v_0.AuxInt
+ c := auxIntToInt32(v_0.AuxInt)
x := v_1
a := v_2
- if !(isPowerOfTwo(c+1) && int32(c) >= 7) {
+ if !(isPowerOfTwo32(c+1) && c >= 7) {
break
}
v.reset(OpARMRSB)
v0 := b.NewValue0(v.Pos, OpARMRSBshiftLL, x.Type)
- v0.AuxInt = log2(c + 1)
+ v0.AuxInt = int32ToAuxInt(int32(log32(c + 1)))
v0.AddArg2(x, x)
v.AddArg2(v0, a)
return true
}
// match: (MULS (MOVWconst [c]) x a)
- // cond: c%3 == 0 && isPowerOfTwo(c/3) && is32Bit(c)
- // result: (RSB (SLLconst <x.Type> [log2(c/3)] (ADDshiftLL <x.Type> x x [1])) a)
+ // cond: c%3 == 0 && isPowerOfTwo32(c/3)
+ // result: (RSB (SLLconst <x.Type> [int32(log32(c/3))] (ADDshiftLL <x.Type> x x [1])) a)
for {
if v_0.Op != OpARMMOVWconst {
break
}
- c := v_0.AuxInt
+ c := auxIntToInt32(v_0.AuxInt)
x := v_1
a := v_2
- if !(c%3 == 0 && isPowerOfTwo(c/3) && is32Bit(c)) {
+ if !(c%3 == 0 && isPowerOfTwo32(c/3)) {
break
}
v.reset(OpARMRSB)
v0 := b.NewValue0(v.Pos, OpARMSLLconst, x.Type)
- v0.AuxInt = log2(c / 3)
+ v0.AuxInt = int32ToAuxInt(int32(log32(c / 3)))
v1 := b.NewValue0(v.Pos, OpARMADDshiftLL, x.Type)
- v1.AuxInt = 1
+ v1.AuxInt = int32ToAuxInt(1)
v1.AddArg2(x, x)
v0.AddArg(v1)
v.AddArg2(v0, a)
return true
}
// match: (MULS (MOVWconst [c]) x a)
- // cond: c%5 == 0 && isPowerOfTwo(c/5) && is32Bit(c)
- // result: (RSB (SLLconst <x.Type> [log2(c/5)] (ADDshiftLL <x.Type> x x [2])) a)
+ // cond: c%5 == 0 && isPowerOfTwo32(c/5)
+ // result: (RSB (SLLconst <x.Type> [int32(log32(c/5))] (ADDshiftLL <x.Type> x x [2])) a)
for {
if v_0.Op != OpARMMOVWconst {
break
}
- c := v_0.AuxInt
+ c := auxIntToInt32(v_0.AuxInt)
x := v_1
a := v_2
- if !(c%5 == 0 && isPowerOfTwo(c/5) && is32Bit(c)) {
+ if !(c%5 == 0 && isPowerOfTwo32(c/5)) {
break
}
v.reset(OpARMRSB)
v0 := b.NewValue0(v.Pos, OpARMSLLconst, x.Type)
- v0.AuxInt = log2(c / 5)
+ v0.AuxInt = int32ToAuxInt(int32(log32(c / 5)))
v1 := b.NewValue0(v.Pos, OpARMADDshiftLL, x.Type)
- v1.AuxInt = 2
+ v1.AuxInt = int32ToAuxInt(2)
v1.AddArg2(x, x)
v0.AddArg(v1)
v.AddArg2(v0, a)
return true
}
// match: (MULS (MOVWconst [c]) x a)
- // cond: c%7 == 0 && isPowerOfTwo(c/7) && is32Bit(c)
- // result: (RSB (SLLconst <x.Type> [log2(c/7)] (RSBshiftLL <x.Type> x x [3])) a)
+ // cond: c%7 == 0 && isPowerOfTwo32(c/7)
+ // result: (RSB (SLLconst <x.Type> [int32(log32(c/7))] (RSBshiftLL <x.Type> x x [3])) a)
for {
if v_0.Op != OpARMMOVWconst {
break
}
- c := v_0.AuxInt
+ c := auxIntToInt32(v_0.AuxInt)
x := v_1
a := v_2
- if !(c%7 == 0 && isPowerOfTwo(c/7) && is32Bit(c)) {
+ if !(c%7 == 0 && isPowerOfTwo32(c/7)) {
break
}
v.reset(OpARMRSB)
v0 := b.NewValue0(v.Pos, OpARMSLLconst, x.Type)
- v0.AuxInt = log2(c / 7)
+ v0.AuxInt = int32ToAuxInt(int32(log32(c / 7)))
v1 := b.NewValue0(v.Pos, OpARMRSBshiftLL, x.Type)
- v1.AuxInt = 3
+ v1.AuxInt = int32ToAuxInt(3)
v1.AddArg2(x, x)
v0.AddArg(v1)
v.AddArg2(v0, a)
return true
}
// match: (MULS (MOVWconst [c]) x a)
- // cond: c%9 == 0 && isPowerOfTwo(c/9) && is32Bit(c)
- // result: (RSB (SLLconst <x.Type> [log2(c/9)] (ADDshiftLL <x.Type> x x [3])) a)
+ // cond: c%9 == 0 && isPowerOfTwo32(c/9)
+ // result: (RSB (SLLconst <x.Type> [int32(log32(c/9))] (ADDshiftLL <x.Type> x x [3])) a)
for {
if v_0.Op != OpARMMOVWconst {
break
}
- c := v_0.AuxInt
+ c := auxIntToInt32(v_0.AuxInt)
x := v_1
a := v_2
- if !(c%9 == 0 && isPowerOfTwo(c/9) && is32Bit(c)) {
+ if !(c%9 == 0 && isPowerOfTwo32(c/9)) {
break
}
v.reset(OpARMRSB)
v0 := b.NewValue0(v.Pos, OpARMSLLconst, x.Type)
- v0.AuxInt = log2(c / 9)
+ v0.AuxInt = int32ToAuxInt(int32(log32(c / 9)))
v1 := b.NewValue0(v.Pos, OpARMADDshiftLL, x.Type)
- v1.AuxInt = 3
+ v1.AuxInt = int32ToAuxInt(3)
v1.AddArg2(x, x)
v0.AddArg(v1)
v.AddArg2(v0, a)
_ = v_0.Args[1]
x := v_0.Args[0]
v_0_1 := v_0.Args[1]
- if v_0_1.Op != OpARMMOVWconst || v_0_1.AuxInt != 1 {
+ if v_0_1.Op != OpARMMOVWconst || auxIntToInt32(v_0_1.AuxInt) != 1 {
break
}
v.copyOf(x)
return true
}
// match: (Select0 (CALLudiv x (MOVWconst [c])))
- // cond: isPowerOfTwo(c)
- // result: (SRLconst [log2(c)] x)
+ // cond: isPowerOfTwo32(c)
+ // result: (SRLconst [int32(log32(c))] x)
for {
if v_0.Op != OpARMCALLudiv {
break
if v_0_1.Op != OpARMMOVWconst {
break
}
- c := v_0_1.AuxInt
- if !(isPowerOfTwo(c)) {
+ c := auxIntToInt32(v_0_1.AuxInt)
+ if !(isPowerOfTwo32(c)) {
break
}
v.reset(OpARMSRLconst)
- v.AuxInt = log2(c)
+ v.AuxInt = int32ToAuxInt(int32(log32(c)))
v.AddArg(x)
return true
}
}
_ = v_0.Args[1]
v_0_1 := v_0.Args[1]
- if v_0_1.Op != OpARMMOVWconst || v_0_1.AuxInt != 1 {
+ if v_0_1.Op != OpARMMOVWconst || auxIntToInt32(v_0_1.AuxInt) != 1 {
break
}
v.reset(OpARMMOVWconst)
- v.AuxInt = 0
+ v.AuxInt = int32ToAuxInt(0)
return true
}
// match: (Select1 (CALLudiv x (MOVWconst [c])))
- // cond: isPowerOfTwo(c)
+ // cond: isPowerOfTwo32(c)
// result: (ANDconst [c-1] x)
for {
if v_0.Op != OpARMCALLudiv {
if v_0_1.Op != OpARMMOVWconst {
break
}
- c := v_0_1.AuxInt
- if !(isPowerOfTwo(c)) {
+ c := auxIntToInt32(v_0_1.AuxInt)
+ if !(isPowerOfTwo32(c)) {
break
}
v.reset(OpARMANDconst)
- v.AuxInt = c - 1
+ v.AuxInt = int32ToAuxInt(c - 1)
v.AddArg(x)
return true
}