cmd/vendor: update to golang.org/x/arch@5a4828b

This updates master to fix the ppc64 objdump. There were many cases where
the Go objdump was generating opcodes that didn't exist in the Go assembler,
or generated operands in the wrong order. The goal is to generate a Go
objdump that is acceptable to the Go assembler, or as close as possible.

An additional change will be needed for the Go objdump tool to make
use of this.

Change-Id: Ie8d2d534e13b9a64852c99b4b864a9c08ed7e036
Reviewed-on: https://go-review.googlesource.com/c/152517
Reviewed-by: Carlos Eduardo Seo <cseo@linux.vnet.ibm.com>
Reviewed-by: Cherry Zhang <cherryyz@google.com>
Run-TryBot: Cherry Zhang <cherryyz@google.com>
TryBot-Result: Gobot Gobot <gobot@golang.org>

diff --git a/src/cmd/vendor/golang.org/x/arch/ppc64/ppc64asm/decode.go b/src/cmd/vendor/golang.org/x/arch/ppc64/ppc64asm/decode.go
index e1518d52e5c112440f99ee6fe2b90a8247d2db23..5f04ff40e450a5b9d4e58cd9f344086b4e1e7cd1 100644 (file)
--- a/src/cmd/vendor/golang.org/x/arch/ppc64/ppc64asm/decode.go
+++ b/src/cmd/vendor/golang.org/x/arch/ppc64/ppc64asm/decode.go
@@ -172,7 +172,7 @@ func Decode(src []byte, ord binary.ByteOrder) (inst Inst, err error) {
                }
                break
        }
-       if inst.Op == 0 {
+       if inst.Op == 0 && inst.Enc != 0 {
                return inst, errUnknown
        }
        return inst, nil

diff --git a/src/cmd/vendor/golang.org/x/arch/ppc64/ppc64asm/decode_test.go b/src/cmd/vendor/golang.org/x/arch/ppc64/ppc64asm/decode_test.go
index 71f64d64dcc63fb6caa8dc8b1c043580665a0118..039b3edfa0ad075aa173a1ea550bf3dee7b4434f 100644 (file)
--- a/src/cmd/vendor/golang.org/x/arch/ppc64/ppc64asm/decode_test.go
+++ b/src/cmd/vendor/golang.org/x/arch/ppc64/ppc64asm/decode_test.go
@@ -50,8 +50,8 @@ func TestDecode(t *testing.T) {
                        switch syntax {
                        case "gnu":
                                out = GNUSyntax(inst)
-                       //case "plan9":
-                       //      out = GoSyntax(inst, 0, nil, nil)
+                       case "plan9":
+                               out = GoSyntax(inst, 0, nil)
                        default:
                                t.Errorf("unknown syntax %q", syntax)
                                continue

diff --git a/src/cmd/vendor/golang.org/x/arch/ppc64/ppc64asm/gnu.go b/src/cmd/vendor/golang.org/x/arch/ppc64/ppc64asm/gnu.go
index 63be379a0454bc6dd114078b48647458c6b7af79..70872bbd743359d9f322b43807213d4abd92983e 100644 (file)
--- a/src/cmd/vendor/golang.org/x/arch/ppc64/ppc64asm/gnu.go
+++ b/src/cmd/vendor/golang.org/x/arch/ppc64/ppc64asm/gnu.go
@@ -14,8 +14,12 @@ import (
 // This form typically matches the syntax defined in the Power ISA Reference Manual.
 func GNUSyntax(inst Inst) string {
        var buf bytes.Buffer
-       if inst.Op == 0 {
-               return "error: unkown instruction"
+       // When there are all 0s, identify them as the disassembler
+       // in binutils would.
+       if inst.Enc == 0 {
+               return ".long 0x0"
+       } else if inst.Op == 0 {
+               return "error: unknown instruction"
        }
        buf.WriteString(inst.Op.String())
        sep := " "

diff --git a/src/cmd/vendor/golang.org/x/arch/ppc64/ppc64asm/objdump_test.go b/src/cmd/vendor/golang.org/x/arch/ppc64/ppc64asm/objdump_test.go
index ae825fd23c961f4f6e672d1cf21a4ad13a6575fc..b886f7bad1a5014c993c90f2c7f73d84943eb259 100644 (file)
--- a/src/cmd/vendor/golang.org/x/arch/ppc64/ppc64asm/objdump_test.go
+++ b/src/cmd/vendor/golang.org/x/arch/ppc64/ppc64asm/objdump_test.go
@@ -49,11 +49,11 @@ func allowedMismatchObjdump(text string, size int, inst *Inst, dec ExtInst) bool
        switch inst.Op {
        case BC, BCA, BL, BLA, BCL, BCLA, TDI, TWI, TW, TD:
                return true // TODO(minux): we lack the support for extended opcodes here
-       case RLWNM, RLWNM_, RLDICL, RLDICL_, RLWINM, RLWINM_, RLDCL, RLDCL_:
+       case RLWNM, RLWNMCC, RLDICL, RLDICLCC, RLWINM, RLWINMCC, RLDCL, RLDCLCC:
                return true // TODO(minux): we lack the support for extended opcodes here
        case DCBTST, DCBT:
                return true // objdump uses the embedded argument order, we use the server argument order
-       case MTFSF, MTFSF_: // objdump doesn't show the last two arguments
+       case MTFSF, MTFSFCC: // objdump doesn't show the last two arguments
                return true
        case VSPLTB, VSPLTH, VSPLTW: // objdump generates unreasonable result "vspltw v6,v19,4" for 10c49a8c, the last 4 should be 0.
                return true

diff --git a/src/cmd/vendor/golang.org/x/arch/ppc64/ppc64asm/plan9.go b/src/cmd/vendor/golang.org/x/arch/ppc64/ppc64asm/plan9.go
index 57a761e36faa0ef9c01e76f64e7565fbdcf0d488..d039d9d500f787f5307fda7471075b1456f1bda3 100644 (file)
--- a/src/cmd/vendor/golang.org/x/arch/ppc64/ppc64asm/plan9.go
+++ b/src/cmd/vendor/golang.org/x/arch/ppc64/ppc64asm/plan9.go
@@ -19,7 +19,9 @@ func GoSyntax(inst Inst, pc uint64, symname func(uint64) (string, uint64)) strin
        if symname == nil {
                symname = func(uint64) (string, uint64) { return "", 0 }
        }
-       if inst.Op == 0 {
+       if inst.Op == 0 && inst.Enc == 0 {
+               return "WORD $0"
+       } else if inst.Op == 0 {
                return "?"
        }
        var args []string
@@ -28,13 +30,27 @@ func GoSyntax(inst Inst, pc uint64, symname func(uint64) (string, uint64)) strin
                        break
                }
                if s := plan9Arg(&inst, i, pc, a, symname); s != "" {
-                       args = append(args, s)
+                       // In the case for some BC instructions, a CondReg arg has
+                       // both the CR and the branch condition encoded in its value.
+                       // plan9Arg will return a string with the string representation
+                       // of these values separated by a blank that will be treated
+                       // as 2 args from this point on.
+                       if strings.IndexByte(s, ' ') > 0 {
+                               t := strings.Split(s, " ")
+                               args = append(args, t[0])
+                               args = append(args, t[1])
+                       } else {
+                               args = append(args, s)
+                       }
                }
        }
        var op string
        op = plan9OpMap[inst.Op]
        if op == "" {
                op = strings.ToUpper(inst.Op.String())
+               if op[len(op)-1] == '.' {
+                       op = op[:len(op)-1] + "CC"
+               }
        }
        // laid out the instruction
        switch inst.Op {
@@ -45,15 +61,60 @@ func GoSyntax(inst Inst, pc uint64, symname func(uint64) (string, uint64)) strin
                        return fmt.Sprintf("%s %s", op, args[0])
                }
                args = append(args, args[0])
-               return op + " " + strings.Join(args[1:], ", ")
+               return op + " " + strings.Join(args[1:], ",")
+       case SYNC:
+               if args[0] == "$1" {
+                       return "LWSYNC"
+               }
+               return "HWSYNC"
+
+       case ISEL:
+               return "ISEL " + args[3] + "," + args[1] + "," + args[2] + "," + args[0]
+
        // store instructions always have the memory operand at the end, no need to reorder
-       case STB, STBU, STBX, STBUX,
-               STH, STHU, STHX, STHUX,
-               STW, STWU, STWX, STWUX,
-               STD, STDU, STDX, STDUX,
-               STQ,
-               STHBRX, STWBRX:
-               return op + " " + strings.Join(args, ", ")
+       // indexed stores handled separately
+       case STB, STBU,
+               STH, STHU,
+               STW, STWU,
+               STD, STDU,
+               STQ:
+               return op + " " + strings.Join(args, ",")
+
+       case CMPD, CMPDI, CMPLD, CMPLDI, CMPW, CMPWI, CMPLW, CMPLWI:
+               if len(args) == 2 {
+                       return op + " " + args[0] + "," + args[1]
+               } else if len(args) == 3 {
+                       return op + " " + args[0] + "," + args[1] + "," + args[2]
+               }
+               return op + " " + args[0] + " ??"
+
+       case LIS:
+               return "ADDIS $0," + args[1] + "," + args[0]
+       // store instructions with index registers
+       case STBX, STBUX, STHX, STHUX, STWX, STWUX, STDX, STDUX,
+               STHBRX, STWBRX, STDBRX, STSWX, STFSX, STFSUX, STFDX, STFDUX, STFIWX, STFDPX:
+               return "MOV" + op[2:len(op)-1] + " " + args[0] + ",(" + args[2] + ")(" + args[1] + ")"
+
+       case STDCXCC, STWCXCC, STHCXCC, STBCXCC:
+               return op + " " + args[0] + ",(" + args[2] + ")(" + args[1] + ")"
+
+       case STXVD2X, STXVW4X:
+               return op + " " + args[0] + ",(" + args[2] + ")(" + args[1] + ")"
+
+       // load instructions with index registers
+       case LBZX, LBZUX, LHZX, LHZUX, LWZX, LWZUX, LDX, LDUX,
+               LHBRX, LWBRX, LDBRX, LSWX, LFSX, LFSUX, LFDX, LFDUX, LFIWAX, LFIWZX:
+               return "MOV" + op[1:len(op)-1] + " (" + args[2] + ")(" + args[1] + ")," + args[0]
+
+       case LDARX, LWARX, LHARX, LBARX:
+               return op + " (" + args[2] + ")(" + args[1] + ")," + args[0]
+
+       case LXVD2X, LXVW4X:
+               return op + " (" + args[2] + ")(" + args[1] + ")," + args[0]
+
+       case DCBT, DCBTST, DCBZ, DCBST:
+               return op + " (" + args[1] + ")"
+
        // branch instructions needs additional handling
        case BCLR:
                if int(inst.Args[0].(Imm))&20 == 20 { // unconditional
@@ -62,11 +123,17 @@ func GoSyntax(inst Inst, pc uint64, symname func(uint64) (string, uint64)) strin
                return op + " " + strings.Join(args, ", ")
        case BC:
                if int(inst.Args[0].(Imm))&0x1c == 12 { // jump on cond bit set
+                       if len(args) == 4 {
+                               return fmt.Sprintf("B%s %s,%s", args[1], args[2], args[3])
+                       }
                        return fmt.Sprintf("B%s %s", args[1], args[2])
                } else if int(inst.Args[0].(Imm))&0x1c == 4 && revCondMap[args[1]] != "" { // jump on cond bit not set
+                       if len(args) == 4 {
+                               return fmt.Sprintf("B%s %s,%s", revCondMap[args[1]], args[2], args[3])
+                       }
                        return fmt.Sprintf("B%s %s", revCondMap[args[1]], args[2])
                }
-               return op + " " + strings.Join(args, ", ")
+               return op + " " + strings.Join(args, ",")
        case BCCTR:
                if int(inst.Args[0].(Imm))&20 == 20 { // unconditional
                        return "BR (CTR)"
@@ -76,9 +143,9 @@ func GoSyntax(inst Inst, pc uint64, symname func(uint64) (string, uint64)) strin
                if int(inst.Args[0].(Imm))&20 == 20 { // unconditional
                        return "BL (CTR)"
                }
-               return op + " " + strings.Join(args, ", ")
+               return op + " " + strings.Join(args, ",")
        case BCA, BCL, BCLA, BCLRL, BCTAR, BCTARL:
-               return op + " " + strings.Join(args, ", ")
+               return op + " " + strings.Join(args, ",")
        }
 }
 
@@ -102,6 +169,10 @@ func plan9Arg(inst *Inst, argIndex int, pc uint64, arg Arg, symname func(uint64)
                }
                return strings.ToUpper(arg.String())
        case CondReg:
+               // This op is left as its numerical value, not mapped onto CR + condition
+               if inst.Op == ISEL {
+                       return fmt.Sprintf("$%d", (arg - Cond0LT))
+               }
                if arg == CR0 && strings.HasPrefix(inst.Op.String(), "cmp") {
                        return "" // don't show cr0 for cmp instructions
                } else if arg >= CR0 {
@@ -111,7 +182,7 @@ func plan9Arg(inst *Inst, argIndex int, pc uint64, arg Arg, symname func(uint64)
                if arg <= Cond0SO {
                        return bit
                }
-               return fmt.Sprintf("4*CR%d+%s", int(arg-Cond0LT)/4, bit)
+               return fmt.Sprintf("%s CR%d", bit, int(arg-Cond0LT)/4)
        case Imm:
                return fmt.Sprintf("$%d", arg)
        case SpReg:
@@ -148,25 +219,27 @@ var revCondMap = map[string]string{
 
 // plan9OpMap maps an Op to its Plan 9 mnemonics, if different than its GNU mnemonics.
 var plan9OpMap = map[Op]string{
-       LWARX: "LWAR", STWCX_: "STWCCC",
-       LDARX: "LDAR", STDCX_: "STDCCC",
-       LHARX: "LHAR", STHCX_: "STHCCC",
-       LBARX: "LBAR", STBCX_: "STBCCC",
-       ADDI: "ADD",
-       ADD_: "ADDCC",
-       LBZ:  "MOVBZ", STB: "MOVB",
-       LBZU: "MOVBZU", STBU: "MOVBU", // TODO(minux): indexed forms are not handled
+       LWARX: "LWAR",
+       LDARX: "LDAR",
+       LHARX: "LHAR",
+       LBARX: "LBAR",
+       ADDI:  "ADD",
+       SRADI: "SRAD",
+       SUBF:  "SUB",
+       LI:    "MOVD",
+       LBZ:   "MOVBZ", STB: "MOVB",
+       LBZU: "MOVBZU", STBU: "MOVBU",
        LHZ: "MOVHZ", LHA: "MOVH", STH: "MOVH",
        LHZU: "MOVHZU", STHU: "MOVHU",
-       LI:  "MOVD",
-       LIS: "ADDIS",
        LWZ: "MOVWZ", LWA: "MOVW", STW: "MOVW",
        LWZU: "MOVWZU", STWU: "MOVWU",
        LD: "MOVD", STD: "MOVD",
        LDU: "MOVDU", STDU: "MOVDU",
+       CMPD: "CMP", CMPDI: "CMP",
+       CMPW: "CMPW", CMPWI: "CMPW",
+       CMPLD: "CMPU", CMPLDI: "CMPU",
+       CMPLW: "CMPWU", CMPLWI: "CMPWU",
        MTSPR: "MOVD", MFSPR: "MOVD", // the width is ambiguous for SPRs
-       B:     "BR",
-       BL:    "CALL",
-       CMPLD: "CMPU", CMPLW: "CMPWU",
-       CMPD: "CMP", CMPW: "CMPW",
+       B:  "BR",
+       BL: "CALL",
 }

diff --git a/src/cmd/vendor/golang.org/x/arch/ppc64/ppc64asm/tables.go b/src/cmd/vendor/golang.org/x/arch/ppc64/ppc64asm/tables.go
index 24c745c8485693bf288ba90470f9f2789ac7d4c9..f536926dbc11aa8b8b72d991e6028cb896901caf 100644 (file)
--- a/src/cmd/vendor/golang.org/x/arch/ppc64/ppc64asm/tables.go
+++ b/src/cmd/vendor/golang.org/x/arch/ppc64/ppc64asm/tables.go
@@ -6,7 +6,7 @@ package ppc64asm
 const (
        _ Op = iota
        CNTLZW
-       CNTLZW_
+       CNTLZWCC
        B
        BA
        BL
@@ -91,101 +91,101 @@ const (
        LIS
        ADDIS
        ADD
-       ADD_
+       ADDCC
        ADDO
-       ADDO_
+       ADDOCC
        ADDIC
        SUBF
-       SUBF_
+       SUBFCC
        SUBFO
-       SUBFO_
-       ADDIC_
+       SUBFOCC
+       ADDICCC
        SUBFIC
        ADDC
-       ADDC_
+       ADDCCC
        ADDCO
-       ADDCO_
+       ADDCOCC
        SUBFC
-       SUBFC_
+       SUBFCCC
        SUBFCO
-       SUBFCO_
+       SUBFCOCC
        ADDE
-       ADDE_
+       ADDECC
        ADDEO
-       ADDEO_
+       ADDEOCC
        ADDME
-       ADDME_
+       ADDMECC
        ADDMEO
-       ADDMEO_
+       ADDMEOCC
        SUBFE
-       SUBFE_
+       SUBFECC
        SUBFEO
-       SUBFEO_
+       SUBFEOCC
        SUBFME
-       SUBFME_
+       SUBFMECC
        SUBFMEO
-       SUBFMEO_
+       SUBFMEOCC
        ADDZE
-       ADDZE_
+       ADDZECC
        ADDZEO
-       ADDZEO_
+       ADDZEOCC
        SUBFZE
-       SUBFZE_
+       SUBFZECC
        SUBFZEO
-       SUBFZEO_
+       SUBFZEOCC
        NEG
-       NEG_
+       NEGCC
        NEGO
-       NEGO_
+       NEGOCC
        MULLI
        MULLW
-       MULLW_
+       MULLWCC
        MULLWO
-       MULLWO_
+       MULLWOCC
        MULHW
-       MULHW_
+       MULHWCC
        MULHWU
-       MULHWU_
+       MULHWUCC
        DIVW
-       DIVW_
+       DIVWCC
        DIVWO
-       DIVWO_
+       DIVWOCC
        DIVWU
-       DIVWU_
+       DIVWUCC
        DIVWUO
-       DIVWUO_
+       DIVWUOCC
        DIVWE
-       DIVWE_
+       DIVWECC
        DIVWEO
-       DIVWEO_
+       DIVWEOCC
        DIVWEU
-       DIVWEU_
+       DIVWEUCC
        DIVWEUO
-       DIVWEUO_
+       DIVWEUOCC
        MULLD
-       MULLD_
+       MULLDCC
        MULLDO
-       MULLDO_
+       MULLDOCC
        MULHDU
-       MULHDU_
+       MULHDUCC
        MULHD
-       MULHD_
+       MULHDCC
        DIVD
-       DIVD_
+       DIVDCC
        DIVDO
-       DIVDO_
+       DIVDOCC
        DIVDU
-       DIVDU_
+       DIVDUCC
        DIVDUO
-       DIVDUO_
+       DIVDUOCC
        DIVDE
-       DIVDE_
+       DIVDECC
        DIVDEO
-       DIVDEO_
+       DIVDEOCC
        DIVDEU
-       DIVDEU_
+       DIVDEUCC
        DIVDEUO
-       DIVDEUO_
+       DIVDEUOCC
        CMPWI
        CMPDI
        CMPW
@@ -199,77 +199,77 @@ const (
        TDI
        ISEL
        TD
-       ANDI_
-       ANDIS_
+       ANDICC
+       ANDISCC
        ORI
        ORIS
        XORI
        XORIS
        AND
-       AND_
+       ANDCC
        XOR
-       XOR_
+       XORCC
        NAND
-       NAND_
+       NANDCC
        OR
-       OR_
+       ORCC
        NOR
-       NOR_
+       NORCC
        ANDC
-       ANDC_
+       ANDCCC
        EXTSB
-       EXTSB_
+       EXTSBCC
        EQV
-       EQV_
+       EQVCC
        ORC
-       ORC_
+       ORCCC
        EXTSH
-       EXTSH_
+       EXTSHCC
        CMPB
        POPCNTB
        POPCNTW
        PRTYD
        PRTYW
        EXTSW
-       EXTSW_
+       EXTSWCC
        CNTLZD
-       CNTLZD_
+       CNTLZDCC
        POPCNTD
        BPERMD
        RLWINM
-       RLWINM_
+       RLWINMCC
        RLWNM
-       RLWNM_
+       RLWNMCC
        RLWIMI
-       RLWIMI_
+       RLWIMICC
        RLDICL
-       RLDICL_
+       RLDICLCC
        RLDICR
-       RLDICR_
+       RLDICRCC
        RLDIC
-       RLDIC_
+       RLDICCC
        RLDCL
-       RLDCL_
+       RLDCLCC
        RLDCR
-       RLDCR_
+       RLDCRCC
        RLDIMI
-       RLDIMI_
+       RLDIMICC
        SLW
-       SLW_
+       SLWCC
        SRW
-       SRW_
+       SRWCC
        SRAWI
-       SRAWI_
+       SRAWICC
        SRAW
-       SRAW_
+       SRAWCC
        SLD
-       SLD_
+       SLDCC
        SRD
-       SRD_
+       SRDCC
        SRADI
-       SRADI_
+       SRADICC
        SRAD
-       SRAD_
+       SRADCC
        CDTBCD
        CBCDTD
        ADDG6S
@@ -312,112 +312,112 @@ const (
        STFDP
        STFDPX
        FMR
-       FMR_
+       FMRCC
        FABS
-       FABS_
+       FABSCC
        FNABS
-       FNABS_
+       FNABSCC
        FNEG
-       FNEG_
+       FNEGCC
        FCPSGN
-       FCPSGN_
+       FCPSGNCC
        FMRGEW
        FMRGOW
        FADD
-       FADD_
+       FADDCC
        FADDS
-       FADDS_
+       FADDSCC
        FSUB
-       FSUB_
+       FSUBCC
        FSUBS
-       FSUBS_
+       FSUBSCC
        FMUL
-       FMUL_
+       FMULCC
        FMULS
-       FMULS_
+       FMULSCC
        FDIV
-       FDIV_
+       FDIVCC
        FDIVS
-       FDIVS_
+       FDIVSCC
        FSQRT
-       FSQRT_
+       FSQRTCC
        FSQRTS
-       FSQRTS_
+       FSQRTSCC
        FRE
-       FRE_
+       FRECC
        FRES
-       FRES_
+       FRESCC
        FRSQRTE
-       FRSQRTE_
+       FRSQRTECC
        FRSQRTES
-       FRSQRTES_
+       FRSQRTESCC
        FTDIV
        FTSQRT
        FMADD
-       FMADD_
+       FMADDCC
        FMADDS
-       FMADDS_
+       FMADDSCC
        FMSUB
-       FMSUB_
+       FMSUBCC
        FMSUBS
-       FMSUBS_
+       FMSUBSCC
        FNMADD
-       FNMADD_
+       FNMADDCC
        FNMADDS
-       FNMADDS_
+       FNMADDSCC
        FNMSUB
-       FNMSUB_
+       FNMSUBCC
        FNMSUBS
-       FNMSUBS_
+       FNMSUBSCC
        FRSP
-       FRSP_
+       FRSPCC
        FCTID
-       FCTID_
+       FCTIDCC
        FCTIDZ
-       FCTIDZ_
+       FCTIDZCC
        FCTIDU
-       FCTIDU_
+       FCTIDUCC
        FCTIDUZ
-       FCTIDUZ_
+       FCTIDUZCC
        FCTIW
-       FCTIW_
+       FCTIWCC
        FCTIWZ
-       FCTIWZ_
+       FCTIWZCC
        FCTIWU
-       FCTIWU_
+       FCTIWUCC
        FCTIWUZ
-       FCTIWUZ_
+       FCTIWUZCC
        FCFID
-       FCFID_
+       FCFIDCC
        FCFIDU
-       FCFIDU_
+       FCFIDUCC
        FCFIDS
-       FCFIDS_
+       FCFIDSCC
        FCFIDUS
-       FCFIDUS_
+       FCFIDUSCC
        FRIN
-       FRIN_
+       FRINCC
        FRIZ
-       FRIZ_
+       FRIZCC
        FRIP
-       FRIP_
+       FRIPCC
        FRIM
-       FRIM_
+       FRIMCC
        FCMPU
        FCMPO
        FSEL
-       FSEL_
+       FSELCC
        MFFS
-       MFFS_
+       MFFSCC
        MCRFS
        MTFSFI
-       MTFSFI_
+       MTFSFICC
        MTFSF
-       MTFSF_
+       MTFSFCC
        MTFSB0
-       MTFSB0_
+       MTFSB0CC
        MTFSB1
-       MTFSB1_
+       MTFSB1CC
        LVEBX
        LVEHX
        LVEWX
@@ -552,29 +552,29 @@ const (
        VMINUH
        VMINUW
        VCMPEQUB
-       VCMPEQUB_
+       VCMPEQUBCC
        VCMPEQUH
-       VCMPEQUH_
+       VCMPEQUHCC
        VCMPEQUW
-       VCMPEQUW_
+       VCMPEQUWCC
        VCMPEQUD
-       VCMPEQUD_
+       VCMPEQUDCC
        VCMPGTSB
-       VCMPGTSB_
+       VCMPGTSBCC
        VCMPGTSD
-       VCMPGTSD_
+       VCMPGTSDCC
        VCMPGTSH
-       VCMPGTSH_
+       VCMPGTSHCC
        VCMPGTSW
-       VCMPGTSW_
+       VCMPGTSWCC
        VCMPGTUB
-       VCMPGTUB_
+       VCMPGTUBCC
        VCMPGTUD
-       VCMPGTUD_
+       VCMPGTUDCC
        VCMPGTUH
-       VCMPGTUH_
+       VCMPGTUHCC
        VCMPGTUW
-       VCMPGTUW_
+       VCMPGTUWCC
        VAND
        VANDC
        VEQV
@@ -614,13 +614,13 @@ const (
        VRFIP
        VRFIZ
        VCMPBFP
-       VCMPBFP_
+       VCMPBFPCC
        VCMPEQFP
-       VCMPEQFP_
+       VCMPEQFPCC
        VCMPGEFP
-       VCMPGEFP_
+       VCMPGEFPCC
        VCMPGTFP
-       VCMPGTFP_
+       VCMPGTFPCC
        VEXPTEFP
        VLOGEFP
        VREFP
@@ -647,18 +647,18 @@ const (
        VPOPCNTH
        VPOPCNTW
        VBPERMQ
-       BCDADD_
-       BCDSUB_
+       BCDADDCC
+       BCDSUBCC
        MTVSCR
        MFVSCR
        DADD
-       DADD_
+       DADDCC
        DSUB
-       DSUB_
+       DSUBCC
        DMUL
-       DMUL_
+       DMULCC
        DDIV
-       DDIV_
+       DDIVCC
        DCMPU
        DCMPO
        DTSTDC
@@ -666,41 +666,41 @@ const (
        DTSTEX
        DTSTSF
        DQUAI
-       DQUAI_
+       DQUAICC
        DQUA
-       DQUA_
+       DQUACC
        DRRND
-       DRRND_
+       DRRNDCC
        DRINTX
-       DRINTX_
+       DRINTXCC
        DRINTN
-       DRINTN_
+       DRINTNCC
        DCTDP
-       DCTDP_
+       DCTDPCC
        DCTQPQ
-       DCTQPQ_
+       DCTQPQCC
        DRSP
-       DRSP_
+       DRSPCC
        DRDPQ
-       DRDPQ_
+       DRDPQCC
        DCFFIX
-       DCFFIX_
+       DCFFIXCC
        DCFFIXQ
-       DCFFIXQ_
+       DCFFIXQCC
        DCTFIX
-       DCTFIX_
+       DCTFIXCC
        DDEDPD
-       DDEDPD_
+       DDEDPDCC
        DENBCD
-       DENBCD_
+       DENBCDCC
        DXEX
-       DXEX_
+       DXEXCC
        DIEX
-       DIEX_
+       DIEXCC
        DSCLI
-       DSCLI_
+       DSCLICC
        DSCRI
-       DSCRI_
+       DSCRICC
        LXSDX
        LXSIWAX
        LXSIWZX
@@ -768,17 +768,17 @@ const (
        XVADDDP
        XVADDSP
        XVCMPEQDP
-       XVCMPEQDP_
+       XVCMPEQDPCC
        XVCMPEQSP
-       XVCMPEQSP_
+       XVCMPEQSPCC
        XVCMPGEDP
-       XVCMPGEDP_
+       XVCMPGEDPCC
        XVCMPGESP
-       XVCMPGESP_
+       XVCMPGESPCC
        XVCMPGTDP
-       XVCMPGTDP_
+       XVCMPGTDPCC
        XVCMPGTSP
-       XVCMPGTSP_
+       XVCMPGTSPCC
        XVCPSGNDP
        XVCPSGNSP
        XVCVDPSP
@@ -1104,91 +1104,91 @@ const (
        EFDCFS
        EFSCFD
        DLMZB
-       DLMZB_
+       DLMZBCC
        MACCHW
-       MACCHW_
+       MACCHWCC
        MACCHWO
-       MACCHWO_
+       MACCHWOCC
        MACCHWS
-       MACCHWS_
+       MACCHWSCC
        MACCHWSO
-       MACCHWSO_
+       MACCHWSOCC
        MACCHWU
-       MACCHWU_
+       MACCHWUCC
        MACCHWUO
-       MACCHWUO_
+       MACCHWUOCC
        MACCHWSU
-       MACCHWSU_
+       MACCHWSUCC
        MACCHWSUO
-       MACCHWSUO_
+       MACCHWSUOCC
        MACHHW
-       MACHHW_
+       MACHHWCC
        MACHHWO
-       MACHHWO_
+       MACHHWOCC
        MACHHWS
-       MACHHWS_
+       MACHHWSCC
        MACHHWSO
-       MACHHWSO_
+       MACHHWSOCC
        MACHHWU
-       MACHHWU_
+       MACHHWUCC
        MACHHWUO
-       MACHHWUO_
+       MACHHWUOCC
        MACHHWSU
-       MACHHWSU_
+       MACHHWSUCC
        MACHHWSUO
-       MACHHWSUO_
+       MACHHWSUOCC
        MACLHW
-       MACLHW_
+       MACLHWCC
        MACLHWO
-       MACLHWO_
+       MACLHWOCC
        MACLHWS
-       MACLHWS_
+       MACLHWSCC
        MACLHWSO
-       MACLHWSO_
+       MACLHWSOCC
        MACLHWU
-       MACLHWU_
+       MACLHWUCC
        MACLHWUO
-       MACLHWUO_
+       MACLHWUOCC
        MULCHW
-       MULCHW_
+       MULCHWCC
        MACLHWSU
-       MACLHWSU_
+       MACLHWSUCC
        MACLHWSUO
-       MACLHWSUO_
+       MACLHWSUOCC
        MULCHWU
-       MULCHWU_
+       MULCHWUCC
        MULHHW
-       MULHHW_
+       MULHHWCC
        MULLHW
-       MULLHW_
+       MULLHWCC
        MULHHWU
-       MULHHWU_
+       MULHHWUCC
        MULLHWU
-       MULLHWU_
+       MULLHWUCC
        NMACCHW
-       NMACCHW_
+       NMACCHWCC
        NMACCHWO
-       NMACCHWO_
+       NMACCHWOCC
        NMACCHWS
-       NMACCHWS_
+       NMACCHWSCC
        NMACCHWSO
-       NMACCHWSO_
+       NMACCHWSOCC
        NMACHHW
-       NMACHHW_
+       NMACHHWCC
        NMACHHWO
-       NMACHHWO_
+       NMACHHWOCC
        NMACHHWS
-       NMACHHWS_
+       NMACHHWSCC
        NMACHHWSO
-       NMACHHWSO_
+       NMACHHWSOCC
        NMACLHW
-       NMACLHW_
+       NMACLHWCC
        NMACLHWO
-       NMACLHWO_
+       NMACLHWOCC
        NMACLHWS
-       NMACLHWS_
+       NMACLHWSCC
        NMACLHWSO
-       NMACLHWSO_
+       NMACLHWSOCC
        ICBI
        ICBT
        DCBA
@@ -1201,25 +1201,25 @@ const (
        LBARX
        LHARX
        LWARX
-       STBCX_
-       STHCX_
-       STWCX_
+       STBCXCC
+       STHCXCC
+       STWCXCC
        LDARX
-       STDCX_
+       STDCXCC
        LQARX
-       STQCX_
+       STQCXCC
        SYNC
        EIEIO
        MBAR
        WAIT
-       TBEGIN_
-       TEND_
-       TABORT_
-       TABORTWC_
-       TABORTWCI_
-       TABORTDC_
-       TABORTDCI_
-       TSR_
+       TBEGINCC
+       TENDCC
+       TABORTCC
+       TABORTWCCC
+       TABORTWCICC
+       TABORTDCCC
+       TABORTDCICC
+       TSRCC
        TCHECK
        MFTB
        RFEBB
@@ -1250,8 +1250,8 @@ const (
        STWCIX
        STHCIX
        STDCIX
-       TRECLAIM_
-       TRECHKPT_
+       TRECLAIMCC
+       TRECHKPTCC
        MTMSR
        MTMSRD
        MFMSR
@@ -1260,7 +1260,7 @@ const (
        SLBMTE
        SLBMFEV
        SLBMFEE
-       SLBFEE_
+       SLBFEECC
        MTSR
        MTSRIN
        MFSR
@@ -1309,8 +1309,8 @@ const (
        STVEPX
        STVEPXL
        DCBI
-       DCBLQ_
-       ICBLQ_
+       DCBLQCC
+       ICBLQCC
        DCBTLS
        DCBTSTLS
        ICBTLS
@@ -1319,7 +1319,7 @@ const (
        TLBIVAX
        TLBILX
        TLBSX
-       TLBSRX_
+       TLBSRXCC
        TLBRE
        TLBWE
        DNH
@@ -1329,11 +1329,26 @@ const (
        ICREAD
        MFPMR
        MTPMR
+       ADDEX
+       DARN
+       MADDHD
+       MADDHDU
+       MADDLD
+       CMPRB
+       CMPEQB
+       EXTSWSLI
+       EXTSWSLICC
+       MFVSRLD
+       MTVSRDD
+       MTVSRWS
+       MCRXRX
+       COPY
+       PASTECC
 )
 
 var opstr = [...]string{
        CNTLZW:        "cntlzw",
-       CNTLZW_:       "cntlzw.",
+       CNTLZWCC:      "cntlzw.",
        B:             "b",
        BA:            "ba",
        BL:            "bl",
@@ -1418,101 +1433,101 @@ var opstr = [...]string{
        LIS:           "lis",
        ADDIS:         "addis",
        ADD:           "add",
-       ADD_:          "add.",
+       ADDCC:         "add.",
        ADDO:          "addo",
-       ADDO_:         "addo.",
+       ADDOCC:        "addo.",
        ADDIC:         "addic",
        SUBF:          "subf",
-       SUBF_:         "subf.",
+       SUBFCC:        "subf.",
        SUBFO:         "subfo",
-       SUBFO_:        "subfo.",
-       ADDIC_:        "addic.",
+       SUBFOCC:       "subfo.",
+       ADDICCC:       "addic.",
        SUBFIC:        "subfic",
        ADDC:          "addc",
-       ADDC_:         "addc.",
+       ADDCCC:        "addc.",
        ADDCO:         "addco",
-       ADDCO_:        "addco.",
+       ADDCOCC:       "addco.",
        SUBFC:         "subfc",
-       SUBFC_:        "subfc.",
+       SUBFCCC:       "subfc.",
        SUBFCO:        "subfco",
-       SUBFCO_:       "subfco.",
+       SUBFCOCC:      "subfco.",
        ADDE:          "adde",
-       ADDE_:         "adde.",
+       ADDECC:        "adde.",
        ADDEO:         "addeo",
-       ADDEO_:        "addeo.",
+       ADDEOCC:       "addeo.",
        ADDME:         "addme",
-       ADDME_:        "addme.",
+       ADDMECC:       "addme.",
        ADDMEO:        "addmeo",
-       ADDMEO_:       "addmeo.",
+       ADDMEOCC:      "addmeo.",
        SUBFE:         "subfe",
-       SUBFE_:        "subfe.",
+       SUBFECC:       "subfe.",
        SUBFEO:        "subfeo",
-       SUBFEO_:       "subfeo.",
+       SUBFEOCC:      "subfeo.",
        SUBFME:        "subfme",
-       SUBFME_:       "subfme.",
+       SUBFMECC:      "subfme.",
        SUBFMEO:       "subfmeo",
-       SUBFMEO_:      "subfmeo.",
+       SUBFMEOCC:     "subfmeo.",
        ADDZE:         "addze",
-       ADDZE_:        "addze.",
+       ADDZECC:       "addze.",
        ADDZEO:        "addzeo",
-       ADDZEO_:       "addzeo.",
+       ADDZEOCC:      "addzeo.",
        SUBFZE:        "subfze",
-       SUBFZE_:       "subfze.",
+       SUBFZECC:      "subfze.",
        SUBFZEO:       "subfzeo",
-       SUBFZEO_:      "subfzeo.",
+       SUBFZEOCC:     "subfzeo.",
        NEG:           "neg",
-       NEG_:          "neg.",
+       NEGCC:         "neg.",
        NEGO:          "nego",
-       NEGO_:         "nego.",
+       NEGOCC:        "nego.",
        MULLI:         "mulli",
        MULLW:         "mullw",
-       MULLW_:        "mullw.",
+       MULLWCC:       "mullw.",
        MULLWO:        "mullwo",
-       MULLWO_:       "mullwo.",
+       MULLWOCC:      "mullwo.",
        MULHW:         "mulhw",
-       MULHW_:        "mulhw.",
+       MULHWCC:       "mulhw.",
        MULHWU:        "mulhwu",
-       MULHWU_:       "mulhwu.",
+       MULHWUCC:      "mulhwu.",
        DIVW:          "divw",
-       DIVW_:         "divw.",
+       DIVWCC:        "divw.",
        DIVWO:         "divwo",
-       DIVWO_:        "divwo.",
+       DIVWOCC:       "divwo.",
        DIVWU:         "divwu",
-       DIVWU_:        "divwu.",
+       DIVWUCC:       "divwu.",
        DIVWUO:        "divwuo",
-       DIVWUO_:       "divwuo.",
+       DIVWUOCC:      "divwuo.",
        DIVWE:         "divwe",
-       DIVWE_:        "divwe.",
+       DIVWECC:       "divwe.",
        DIVWEO:        "divweo",
-       DIVWEO_:       "divweo.",
+       DIVWEOCC:      "divweo.",
        DIVWEU:        "divweu",
-       DIVWEU_:       "divweu.",
+       DIVWEUCC:      "divweu.",
        DIVWEUO:       "divweuo",
-       DIVWEUO_:      "divweuo.",
+       DIVWEUOCC:     "divweuo.",
        MULLD:         "mulld",
-       MULLD_:        "mulld.",
+       MULLDCC:       "mulld.",
        MULLDO:        "mulldo",
-       MULLDO_:       "mulldo.",
+       MULLDOCC:      "mulldo.",
        MULHDU:        "mulhdu",
-       MULHDU_:       "mulhdu.",
+       MULHDUCC:      "mulhdu.",
        MULHD:         "mulhd",
-       MULHD_:        "mulhd.",
+       MULHDCC:       "mulhd.",
        DIVD:          "divd",
-       DIVD_:         "divd.",
+       DIVDCC:        "divd.",
        DIVDO:         "divdo",
-       DIVDO_:        "divdo.",
+       DIVDOCC:       "divdo.",
        DIVDU:         "divdu",
-       DIVDU_:        "divdu.",
+       DIVDUCC:       "divdu.",
        DIVDUO:        "divduo",
-       DIVDUO_:       "divduo.",
+       DIVDUOCC:      "divduo.",
        DIVDE:         "divde",
-       DIVDE_:        "divde.",
+       DIVDECC:       "divde.",
        DIVDEO:        "divdeo",
-       DIVDEO_:       "divdeo.",
+       DIVDEOCC:      "divdeo.",
        DIVDEU:        "divdeu",
-       DIVDEU_:       "divdeu.",
+       DIVDEUCC:      "divdeu.",
        DIVDEUO:       "divdeuo",
-       DIVDEUO_:      "divdeuo.",
+       DIVDEUOCC:     "divdeuo.",
        CMPWI:         "cmpwi",
        CMPDI:         "cmpdi",
        CMPW:          "cmpw",
@@ -1526,77 +1541,77 @@ var opstr = [...]string{
        TDI:           "tdi",
        ISEL:          "isel",
        TD:            "td",
-       ANDI_:         "andi.",
-       ANDIS_:        "andis.",
+       ANDICC:        "andi.",
+       ANDISCC:       "andis.",
        ORI:           "ori",
        ORIS:          "oris",
        XORI:          "xori",
        XORIS:         "xoris",
        AND:           "and",
-       AND_:          "and.",
+       ANDCC:         "and.",
        XOR:           "xor",
-       XOR_:          "xor.",
+       XORCC:         "xor.",
        NAND:          "nand",
-       NAND_:         "nand.",
+       NANDCC:        "nand.",
        OR:            "or",
-       OR_:           "or.",
+       ORCC:          "or.",
        NOR:           "nor",
-       NOR_:          "nor.",
+       NORCC:         "nor.",
        ANDC:          "andc",
-       ANDC_:         "andc.",
+       ANDCCC:        "andc.",
        EXTSB:         "extsb",
-       EXTSB_:        "extsb.",
+       EXTSBCC:       "extsb.",
        EQV:           "eqv",
-       EQV_:          "eqv.",
+       EQVCC:         "eqv.",
        ORC:           "orc",
-       ORC_:          "orc.",
+       ORCCC:         "orc.",
        EXTSH:         "extsh",
-       EXTSH_:        "extsh.",
+       EXTSHCC:       "extsh.",
        CMPB:          "cmpb",
        POPCNTB:       "popcntb",
        POPCNTW:       "popcntw",
        PRTYD:         "prtyd",
        PRTYW:         "prtyw",
        EXTSW:         "extsw",
-       EXTSW_:        "extsw.",
+       EXTSWCC:       "extsw.",
        CNTLZD:        "cntlzd",
-       CNTLZD_:       "cntlzd.",
+       CNTLZDCC:      "cntlzd.",
        POPCNTD:       "popcntd",
        BPERMD:        "bpermd",
        RLWINM:        "rlwinm",
-       RLWINM_:       "rlwinm.",
+       RLWINMCC:      "rlwinm.",
        RLWNM:         "rlwnm",
-       RLWNM_:        "rlwnm.",
+       RLWNMCC:       "rlwnm.",
        RLWIMI:        "rlwimi",
-       RLWIMI_:       "rlwimi.",
+       RLWIMICC:      "rlwimi.",
        RLDICL:        "rldicl",
-       RLDICL_:       "rldicl.",
+       RLDICLCC:      "rldicl.",
        RLDICR:        "rldicr",
-       RLDICR_:       "rldicr.",
+       RLDICRCC:      "rldicr.",
        RLDIC:         "rldic",
-       RLDIC_:        "rldic.",
+       RLDICCC:       "rldic.",
        RLDCL:         "rldcl",
-       RLDCL_:        "rldcl.",
+       RLDCLCC:       "rldcl.",
        RLDCR:         "rldcr",
-       RLDCR_:        "rldcr.",
+       RLDCRCC:       "rldcr.",
        RLDIMI:        "rldimi",
-       RLDIMI_:       "rldimi.",
+       RLDIMICC:      "rldimi.",
        SLW:           "slw",
-       SLW_:          "slw.",
+       SLWCC:         "slw.",
        SRW:           "srw",
-       SRW_:          "srw.",
+       SRWCC:         "srw.",
        SRAWI:         "srawi",
-       SRAWI_:        "srawi.",
+       SRAWICC:       "srawi.",
        SRAW:          "sraw",
-       SRAW_:         "sraw.",
+       SRAWCC:        "sraw.",
        SLD:           "sld",
-       SLD_:          "sld.",
+       SLDCC:         "sld.",
        SRD:           "srd",
-       SRD_:          "srd.",
+       SRDCC:         "srd.",
        SRADI:         "sradi",
-       SRADI_:        "sradi.",
+       SRADICC:       "sradi.",
        SRAD:          "srad",
-       SRAD_:         "srad.",
+       SRADCC:        "srad.",
        CDTBCD:        "cdtbcd",
        CBCDTD:        "cbcdtd",
        ADDG6S:        "addg6s",
@@ -1639,112 +1654,112 @@ var opstr = [...]string{
        STFDP:         "stfdp",
        STFDPX:        "stfdpx",
        FMR:           "fmr",
-       FMR_:          "fmr.",
+       FMRCC:         "fmr.",
        FABS:          "fabs",
-       FABS_:         "fabs.",
+       FABSCC:        "fabs.",
        FNABS:         "fnabs",
-       FNABS_:        "fnabs.",
+       FNABSCC:       "fnabs.",
        FNEG:          "fneg",
-       FNEG_:         "fneg.",
+       FNEGCC:        "fneg.",
        FCPSGN:        "fcpsgn",
-       FCPSGN_:       "fcpsgn.",
+       FCPSGNCC:      "fcpsgn.",
        FMRGEW:        "fmrgew",
        FMRGOW:        "fmrgow",
        FADD:          "fadd",
-       FADD_:         "fadd.",
+       FADDCC:        "fadd.",
        FADDS:         "fadds",
-       FADDS_:        "fadds.",
+       FADDSCC:       "fadds.",
        FSUB:          "fsub",
-       FSUB_:         "fsub.",
+       FSUBCC:        "fsub.",
        FSUBS:         "fsubs",
-       FSUBS_:        "fsubs.",
+       FSUBSCC:       "fsubs.",
        FMUL:          "fmul",
-       FMUL_:         "fmul.",
+       FMULCC:        "fmul.",
        FMULS:         "fmuls",
-       FMULS_:        "fmuls.",
+       FMULSCC:       "fmuls.",
        FDIV:          "fdiv",
-       FDIV_:         "fdiv.",
+       FDIVCC:        "fdiv.",
        FDIVS:         "fdivs",
-       FDIVS_:        "fdivs.",
+       FDIVSCC:       "fdivs.",
        FSQRT:         "fsqrt",
-       FSQRT_:        "fsqrt.",
+       FSQRTCC:       "fsqrt.",
        FSQRTS:        "fsqrts",
-       FSQRTS_:       "fsqrts.",
+       FSQRTSCC:      "fsqrts.",
        FRE:           "fre",
-       FRE_:          "fre.",
+       FRECC:         "fre.",
        FRES:          "fres",
-       FRES_:         "fres.",
+       FRESCC:        "fres.",
        FRSQRTE:       "frsqrte",
-       FRSQRTE_:      "frsqrte.",
+       FRSQRTECC:     "frsqrte.",
        FRSQRTES:      "frsqrtes",
-       FRSQRTES_:     "frsqrtes.",
+       FRSQRTESCC:    "frsqrtes.",
        FTDIV:         "ftdiv",
        FTSQRT:        "ftsqrt",
        FMADD:         "fmadd",
-       FMADD_:        "fmadd.",
+       FMADDCC:       "fmadd.",
        FMADDS:        "fmadds",
-       FMADDS_:       "fmadds.",
+       FMADDSCC:      "fmadds.",
        FMSUB:         "fmsub",
-       FMSUB_:        "fmsub.",
+       FMSUBCC:       "fmsub.",
        FMSUBS:        "fmsubs",
-       FMSUBS_:       "fmsubs.",
+       FMSUBSCC:      "fmsubs.",
        FNMADD:        "fnmadd",
-       FNMADD_:       "fnmadd.",
+       FNMADDCC:      "fnmadd.",
        FNMADDS:       "fnmadds",
-       FNMADDS_:      "fnmadds.",
+       FNMADDSCC:     "fnmadds.",
        FNMSUB:        "fnmsub",
-       FNMSUB_:       "fnmsub.",
+       FNMSUBCC:      "fnmsub.",
        FNMSUBS:       "fnmsubs",
-       FNMSUBS_:      "fnmsubs.",
+       FNMSUBSCC:     "fnmsubs.",
        FRSP:          "frsp",
-       FRSP_:         "frsp.",
+       FRSPCC:        "frsp.",
        FCTID:         "fctid",
-       FCTID_:        "fctid.",
+       FCTIDCC:       "fctid.",
        FCTIDZ:        "fctidz",
-       FCTIDZ_:       "fctidz.",
+       FCTIDZCC:      "fctidz.",
        FCTIDU:        "fctidu",
-       FCTIDU_:       "fctidu.",
+       FCTIDUCC:      "fctidu.",
        FCTIDUZ:       "fctiduz",
-       FCTIDUZ_:      "fctiduz.",
+       FCTIDUZCC:     "fctiduz.",
        FCTIW:         "fctiw",
-       FCTIW_:        "fctiw.",
+       FCTIWCC:       "fctiw.",
        FCTIWZ:        "fctiwz",
-       FCTIWZ_:       "fctiwz.",
+       FCTIWZCC:      "fctiwz.",
        FCTIWU:        "fctiwu",
-       FCTIWU_:       "fctiwu.",
+       FCTIWUCC:      "fctiwu.",
        FCTIWUZ:       "fctiwuz",
-       FCTIWUZ_:      "fctiwuz.",
+       FCTIWUZCC:     "fctiwuz.",
        FCFID:         "fcfid",
-       FCFID_:        "fcfid.",
+       FCFIDCC:       "fcfid.",
        FCFIDU:        "fcfidu",
-       FCFIDU_:       "fcfidu.",
+       FCFIDUCC:      "fcfidu.",
        FCFIDS:        "fcfids",
-       FCFIDS_:       "fcfids.",
+       FCFIDSCC:      "fcfids.",
        FCFIDUS:       "fcfidus",
-       FCFIDUS_:      "fcfidus.",
+       FCFIDUSCC:     "fcfidus.",
        FRIN:          "frin",
-       FRIN_:         "frin.",
+       FRINCC:        "frin.",
        FRIZ:          "friz",
-       FRIZ_:         "friz.",
+       FRIZCC:        "friz.",
        FRIP:          "frip",
-       FRIP_:         "frip.",
+       FRIPCC:        "frip.",
        FRIM:          "frim",
-       FRIM_:         "frim.",
+       FRIMCC:        "frim.",
        FCMPU:         "fcmpu",
        FCMPO:         "fcmpo",
        FSEL:          "fsel",
-       FSEL_:         "fsel.",
+       FSELCC:        "fsel.",
        MFFS:          "mffs",
-       MFFS_:         "mffs.",
+       MFFSCC:        "mffs.",
        MCRFS:         "mcrfs",
        MTFSFI:        "mtfsfi",
-       MTFSFI_:       "mtfsfi.",
+       MTFSFICC:      "mtfsfi.",
        MTFSF:         "mtfsf",
-       MTFSF_:        "mtfsf.",
+       MTFSFCC:       "mtfsf.",
        MTFSB0:        "mtfsb0",
-       MTFSB0_:       "mtfsb0.",
+       MTFSB0CC:      "mtfsb0.",
        MTFSB1:        "mtfsb1",
-       MTFSB1_:       "mtfsb1.",
+       MTFSB1CC:      "mtfsb1.",
        LVEBX:         "lvebx",
        LVEHX:         "lvehx",
        LVEWX:         "lvewx",
@@ -1879,29 +1894,29 @@ var opstr = [...]string{
        VMINUH:        "vminuh",
        VMINUW:        "vminuw",
        VCMPEQUB:      "vcmpequb",
-       VCMPEQUB_:     "vcmpequb.",
+       VCMPEQUBCC:    "vcmpequb.",
        VCMPEQUH:      "vcmpequh",
-       VCMPEQUH_:     "vcmpequh.",
+       VCMPEQUHCC:    "vcmpequh.",
        VCMPEQUW:      "vcmpequw",
-       VCMPEQUW_:     "vcmpequw.",
+       VCMPEQUWCC:    "vcmpequw.",
        VCMPEQUD:      "vcmpequd",
-       VCMPEQUD_:     "vcmpequd.",
+       VCMPEQUDCC:    "vcmpequd.",
        VCMPGTSB:      "vcmpgtsb",
-       VCMPGTSB_:     "vcmpgtsb.",
+       VCMPGTSBCC:    "vcmpgtsb.",
        VCMPGTSD:      "vcmpgtsd",
-       VCMPGTSD_:     "vcmpgtsd.",
+       VCMPGTSDCC:    "vcmpgtsd.",
        VCMPGTSH:      "vcmpgtsh",
-       VCMPGTSH_:     "vcmpgtsh.",
+       VCMPGTSHCC:    "vcmpgtsh.",
        VCMPGTSW:      "vcmpgtsw",
-       VCMPGTSW_:     "vcmpgtsw.",
+       VCMPGTSWCC:    "vcmpgtsw.",
        VCMPGTUB:      "vcmpgtub",
-       VCMPGTUB_:     "vcmpgtub.",
+       VCMPGTUBCC:    "vcmpgtub.",
        VCMPGTUD:      "vcmpgtud",
-       VCMPGTUD_:     "vcmpgtud.",
+       VCMPGTUDCC:    "vcmpgtud.",
        VCMPGTUH:      "vcmpgtuh",
-       VCMPGTUH_:     "vcmpgtuh.",
+       VCMPGTUHCC:    "vcmpgtuh.",
        VCMPGTUW:      "vcmpgtuw",
-       VCMPGTUW_:     "vcmpgtuw.",
+       VCMPGTUWCC:    "vcmpgtuw.",
        VAND:          "vand",
        VANDC:         "vandc",
        VEQV:          "veqv",
@@ -1941,13 +1956,13 @@ var opstr = [...]string{
        VRFIP:         "vrfip",
        VRFIZ:         "vrfiz",
        VCMPBFP:       "vcmpbfp",
-       VCMPBFP_:      "vcmpbfp.",
+       VCMPBFPCC:     "vcmpbfp.",
        VCMPEQFP:      "vcmpeqfp",
-       VCMPEQFP_:     "vcmpeqfp.",
+       VCMPEQFPCC:    "vcmpeqfp.",
        VCMPGEFP:      "vcmpgefp",
-       VCMPGEFP_:     "vcmpgefp.",
+       VCMPGEFPCC:    "vcmpgefp.",
        VCMPGTFP:      "vcmpgtfp",
-       VCMPGTFP_:     "vcmpgtfp.",
+       VCMPGTFPCC:    "vcmpgtfp.",
        VEXPTEFP:      "vexptefp",
        VLOGEFP:       "vlogefp",
        VREFP:         "vrefp",
@@ -1974,18 +1989,18 @@ var opstr = [...]string{
        VPOPCNTH:      "vpopcnth",
        VPOPCNTW:      "vpopcntw",
        VBPERMQ:       "vbpermq",
-       BCDADD_:       "bcdadd.",
-       BCDSUB_:       "bcdsub.",
+       BCDADDCC:      "bcdadd.",
+       BCDSUBCC:      "bcdsub.",
        MTVSCR:        "mtvscr",
        MFVSCR:        "mfvscr",
        DADD:          "dadd",
-       DADD_:         "dadd.",
+       DADDCC:        "dadd.",
        DSUB:          "dsub",
-       DSUB_:         "dsub.",
+       DSUBCC:        "dsub.",
        DMUL:          "dmul",
-       DMUL_:         "dmul.",
+       DMULCC:        "dmul.",
        DDIV:          "ddiv",
-       DDIV_:         "ddiv.",
+       DDIVCC:        "ddiv.",
        DCMPU:         "dcmpu",
        DCMPO:         "dcmpo",
        DTSTDC:        "dtstdc",
@@ -1993,41 +2008,41 @@ var opstr = [...]string{
        DTSTEX:        "dtstex",
        DTSTSF:        "dtstsf",
        DQUAI:         "dquai",
-       DQUAI_:        "dquai.",
+       DQUAICC:       "dquai.",
        DQUA:          "dqua",
-       DQUA_:         "dqua.",
+       DQUACC:        "dqua.",
        DRRND:         "drrnd",
-       DRRND_:        "drrnd.",
+       DRRNDCC:       "drrnd.",
        DRINTX:        "drintx",
-       DRINTX_:       "drintx.",
+       DRINTXCC:      "drintx.",
        DRINTN:        "drintn",
-       DRINTN_:       "drintn.",
+       DRINTNCC:      "drintn.",
        DCTDP:         "dctdp",
-       DCTDP_:        "dctdp.",
+       DCTDPCC:       "dctdp.",
        DCTQPQ:        "dctqpq",
-       DCTQPQ_:       "dctqpq.",
+       DCTQPQCC:      "dctqpq.",
        DRSP:          "drsp",
-       DRSP_:         "drsp.",
+       DRSPCC:        "drsp.",
        DRDPQ:         "drdpq",
-       DRDPQ_:        "drdpq.",
+       DRDPQCC:       "drdpq.",
        DCFFIX:        "dcffix",
-       DCFFIX_:       "dcffix.",
+       DCFFIXCC:      "dcffix.",
        DCFFIXQ:       "dcffixq",
-       DCFFIXQ_:      "dcffixq.",
+       DCFFIXQCC:     "dcffixq.",
        DCTFIX:        "dctfix",
-       DCTFIX_:       "dctfix.",
+       DCTFIXCC:      "dctfix.",
        DDEDPD:        "ddedpd",
-       DDEDPD_:       "ddedpd.",
+       DDEDPDCC:      "ddedpd.",
        DENBCD:        "denbcd",
-       DENBCD_:       "denbcd.",
+       DENBCDCC:      "denbcd.",
        DXEX:          "dxex",
-       DXEX_:         "dxex.",
+       DXEXCC:        "dxex.",
        DIEX:          "diex",
-       DIEX_:         "diex.",
+       DIEXCC:        "diex.",
        DSCLI:         "dscli",
-       DSCLI_:        "dscli.",
+       DSCLICC:       "dscli.",
        DSCRI:         "dscri",
-       DSCRI_:        "dscri.",
+       DSCRICC:       "dscri.",
        LXSDX:         "lxsdx",
        LXSIWAX:       "lxsiwax",
        LXSIWZX:       "lxsiwzx",
@@ -2095,17 +2110,17 @@ var opstr = [...]string{
        XVADDDP:       "xvadddp",
        XVADDSP:       "xvaddsp",
        XVCMPEQDP:     "xvcmpeqdp",
-       XVCMPEQDP_:    "xvcmpeqdp.",
+       XVCMPEQDPCC:   "xvcmpeqdp.",
        XVCMPEQSP:     "xvcmpeqsp",
-       XVCMPEQSP_:    "xvcmpeqsp.",
+       XVCMPEQSPCC:   "xvcmpeqsp.",
        XVCMPGEDP:     "xvcmpgedp",
-       XVCMPGEDP_:    "xvcmpgedp.",
+       XVCMPGEDPCC:   "xvcmpgedp.",
        XVCMPGESP:     "xvcmpgesp",
-       XVCMPGESP_:    "xvcmpgesp.",
+       XVCMPGESPCC:   "xvcmpgesp.",
        XVCMPGTDP:     "xvcmpgtdp",
-       XVCMPGTDP_:    "xvcmpgtdp.",
+       XVCMPGTDPCC:   "xvcmpgtdp.",
        XVCMPGTSP:     "xvcmpgtsp",
-       XVCMPGTSP_:    "xvcmpgtsp.",
+       XVCMPGTSPCC:   "xvcmpgtsp.",
        XVCPSGNDP:     "xvcpsgndp",
        XVCPSGNSP:     "xvcpsgnsp",
        XVCVDPSP:      "xvcvdpsp",
@@ -2431,91 +2446,91 @@ var opstr = [...]string{
        EFDCFS:        "efdcfs",
        EFSCFD:        "efscfd",
        DLMZB:         "dlmzb",
-       DLMZB_:        "dlmzb.",
+       DLMZBCC:       "dlmzb.",
        MACCHW:        "macchw",
-       MACCHW_:       "macchw.",
+       MACCHWCC:      "macchw.",
        MACCHWO:       "macchwo",
-       MACCHWO_:      "macchwo.",
+       MACCHWOCC:     "macchwo.",
        MACCHWS:       "macchws",
-       MACCHWS_:      "macchws.",
+       MACCHWSCC:     "macchws.",
        MACCHWSO:      "macchwso",
-       MACCHWSO_:     "macchwso.",
+       MACCHWSOCC:    "macchwso.",
        MACCHWU:       "macchwu",
-       MACCHWU_:      "macchwu.",
+       MACCHWUCC:     "macchwu.",
        MACCHWUO:      "macchwuo",
-       MACCHWUO_:     "macchwuo.",
+       MACCHWUOCC:    "macchwuo.",
        MACCHWSU:      "macchwsu",
-       MACCHWSU_:     "macchwsu.",
+       MACCHWSUCC:    "macchwsu.",
        MACCHWSUO:     "macchwsuo",
-       MACCHWSUO_:    "macchwsuo.",
+       MACCHWSUOCC:   "macchwsuo.",
        MACHHW:        "machhw",
-       MACHHW_:       "machhw.",
+       MACHHWCC:      "machhw.",
        MACHHWO:       "machhwo",
-       MACHHWO_:      "machhwo.",
+       MACHHWOCC:     "machhwo.",
        MACHHWS:       "machhws",
-       MACHHWS_:      "machhws.",
+       MACHHWSCC:     "machhws.",
        MACHHWSO:      "machhwso",
-       MACHHWSO_:     "machhwso.",
+       MACHHWSOCC:    "machhwso.",
        MACHHWU:       "machhwu",
-       MACHHWU_:      "machhwu.",
+       MACHHWUCC:     "machhwu.",
        MACHHWUO:      "machhwuo",
-       MACHHWUO_:     "machhwuo.",
+       MACHHWUOCC:    "machhwuo.",
        MACHHWSU:      "machhwsu",
-       MACHHWSU_:     "machhwsu.",
+       MACHHWSUCC:    "machhwsu.",
        MACHHWSUO:     "machhwsuo",
-       MACHHWSUO_:    "machhwsuo.",
+       MACHHWSUOCC:   "machhwsuo.",
        MACLHW:        "maclhw",
-       MACLHW_:       "maclhw.",
+       MACLHWCC:      "maclhw.",
        MACLHWO:       "maclhwo",
-       MACLHWO_:      "maclhwo.",
+       MACLHWOCC:     "maclhwo.",
        MACLHWS:       "maclhws",
-       MACLHWS_:      "maclhws.",
+       MACLHWSCC:     "maclhws.",
        MACLHWSO:      "maclhwso",
-       MACLHWSO_:     "maclhwso.",
+       MACLHWSOCC:    "maclhwso.",
        MACLHWU:       "maclhwu",
-       MACLHWU_:      "maclhwu.",
+       MACLHWUCC:     "maclhwu.",
        MACLHWUO:      "maclhwuo",
-       MACLHWUO_:     "maclhwuo.",
+       MACLHWUOCC:    "maclhwuo.",
        MULCHW:        "mulchw",
-       MULCHW_:       "mulchw.",
+       MULCHWCC:      "mulchw.",
        MACLHWSU:      "maclhwsu",
-       MACLHWSU_:     "maclhwsu.",
+       MACLHWSUCC:    "maclhwsu.",
        MACLHWSUO:     "maclhwsuo",
-       MACLHWSUO_:    "maclhwsuo.",
+       MACLHWSUOCC:   "maclhwsuo.",
        MULCHWU:       "mulchwu",
-       MULCHWU_:      "mulchwu.",
+       MULCHWUCC:     "mulchwu.",
        MULHHW:        "mulhhw",
-       MULHHW_:       "mulhhw.",
+       MULHHWCC:      "mulhhw.",
        MULLHW:        "mullhw",
-       MULLHW_:       "mullhw.",
+       MULLHWCC:      "mullhw.",
        MULHHWU:       "mulhhwu",
-       MULHHWU_:      "mulhhwu.",
+       MULHHWUCC:     "mulhhwu.",
        MULLHWU:       "mullhwu",
-       MULLHWU_:      "mullhwu.",
+       MULLHWUCC:     "mullhwu.",
        NMACCHW:       "nmacchw",
-       NMACCHW_:      "nmacchw.",
+       NMACCHWCC:     "nmacchw.",
        NMACCHWO:      "nmacchwo",
-       NMACCHWO_:     "nmacchwo.",
+       NMACCHWOCC:    "nmacchwo.",
        NMACCHWS:      "nmacchws",
-       NMACCHWS_:     "nmacchws.",
+       NMACCHWSCC:    "nmacchws.",
        NMACCHWSO:     "nmacchwso",
-       NMACCHWSO_:    "nmacchwso.",
+       NMACCHWSOCC:   "nmacchwso.",
        NMACHHW:       "nmachhw",
-       NMACHHW_:      "nmachhw.",
+       NMACHHWCC:     "nmachhw.",
        NMACHHWO:      "nmachhwo",
-       NMACHHWO_:     "nmachhwo.",
+       NMACHHWOCC:    "nmachhwo.",
        NMACHHWS:      "nmachhws",
-       NMACHHWS_:     "nmachhws.",
+       NMACHHWSCC:    "nmachhws.",
        NMACHHWSO:     "nmachhwso",
-       NMACHHWSO_:    "nmachhwso.",
+       NMACHHWSOCC:   "nmachhwso.",
        NMACLHW:       "nmaclhw",
-       NMACLHW_:      "nmaclhw.",
+       NMACLHWCC:     "nmaclhw.",
        NMACLHWO:      "nmaclhwo",
-       NMACLHWO_:     "nmaclhwo.",
+       NMACLHWOCC:    "nmaclhwo.",
        NMACLHWS:      "nmaclhws",
-       NMACLHWS_:     "nmaclhws.",
+       NMACLHWSCC:    "nmaclhws.",
        NMACLHWSO:     "nmaclhwso",
-       NMACLHWSO_:    "nmaclhwso.",
+       NMACLHWSOCC:   "nmaclhwso.",
        ICBI:          "icbi",
        ICBT:          "icbt",
        DCBA:          "dcba",
@@ -2528,25 +2543,25 @@ var opstr = [...]string{
        LBARX:         "lbarx",
        LHARX:         "lharx",
        LWARX:         "lwarx",
-       STBCX_:        "stbcx.",
-       STHCX_:        "sthcx.",
-       STWCX_:        "stwcx.",
+       STBCXCC:       "stbcx.",
+       STHCXCC:       "sthcx.",
+       STWCXCC:       "stwcx.",
        LDARX:         "ldarx",
-       STDCX_:        "stdcx.",
+       STDCXCC:       "stdcx.",
        LQARX:         "lqarx",
-       STQCX_:        "stqcx.",
+       STQCXCC:       "stqcx.",
        SYNC:          "sync",
        EIEIO:         "eieio",
        MBAR:          "mbar",
        WAIT:          "wait",
-       TBEGIN_:       "tbegin.",
-       TEND_:         "tend.",
-       TABORT_:       "tabort.",
-       TABORTWC_:     "tabortwc.",
-       TABORTWCI_:    "tabortwci.",
-       TABORTDC_:     "tabortdc.",
-       TABORTDCI_:    "tabortdci.",
-       TSR_:          "tsr.",
+       TBEGINCC:      "tbegin.",
+       TENDCC:        "tend.",
+       TABORTCC:      "tabort.",
+       TABORTWCCC:    "tabortwc.",
+       TABORTWCICC:   "tabortwci.",
+       TABORTDCCC:    "tabortdc.",
+       TABORTDCICC:   "tabortdci.",
+       TSRCC:         "tsr.",
        TCHECK:        "tcheck",
        MFTB:          "mftb",
        RFEBB:         "rfebb",
@@ -2577,8 +2592,8 @@ var opstr = [...]string{
        STWCIX:        "stwcix",
        STHCIX:        "sthcix",
        STDCIX:        "stdcix",
-       TRECLAIM_:     "treclaim.",
-       TRECHKPT_:     "trechkpt.",
+       TRECLAIMCC:    "treclaim.",
+       TRECHKPTCC:    "trechkpt.",
        MTMSR:         "mtmsr",
        MTMSRD:        "mtmsrd",
        MFMSR:         "mfmsr",
@@ -2587,7 +2602,7 @@ var opstr = [...]string{
        SLBMTE:        "slbmte",
        SLBMFEV:       "slbmfev",
        SLBMFEE:       "slbmfee",
-       SLBFEE_:       "slbfee.",
+       SLBFEECC:      "slbfee.",
        MTSR:          "mtsr",
        MTSRIN:        "mtsrin",
        MFSR:          "mfsr",
@@ -2636,8 +2651,8 @@ var opstr = [...]string{
        STVEPX:        "stvepx",
        STVEPXL:       "stvepxl",
        DCBI:          "dcbi",
-       DCBLQ_:        "dcblq.",
-       ICBLQ_:        "icblq.",
+       DCBLQCC:       "dcblq.",
+       ICBLQCC:       "icblq.",
        DCBTLS:        "dcbtls",
        DCBTSTLS:      "dcbtstls",
        ICBTLS:        "icbtls",
@@ -2646,7 +2661,7 @@ var opstr = [...]string{
        TLBIVAX:       "tlbivax",
        TLBILX:        "tlbilx",
        TLBSX:         "tlbsx",
-       TLBSRX_:       "tlbsrx.",
+       TLBSRXCC:      "tlbsrx.",
        TLBRE:         "tlbre",
        TLBWE:         "tlbwe",
        DNH:           "dnh",
@@ -2656,6 +2671,21 @@ var opstr = [...]string{
        ICREAD:        "icread",
        MFPMR:         "mfpmr",
        MTPMR:         "mtpmr",
+       ADDEX:         "addex",
+       DARN:          "darn",
+       MADDHD:        "maddhd",
+       MADDHDU:       "maddhdu",
+       MADDLD:        "maddld",
+       CMPRB:         "cmprb",
+       CMPEQB:        "cmpeqb",
+       EXTSWSLI:      "extswsli",
+       EXTSWSLICC:    "extswsli.",
+       MFVSRLD:       "mfvsrld",
+       MTVSRDD:       "mtvsrdd",
+       MTVSRWS:       "mtvsrws",
+       MCRXRX:        "mcrxrx",
+       COPY:          "copy",
+       PASTECC:       "paste.",
 }
 
 var (
@@ -2729,12 +2759,13 @@ var (
        ap_SpReg_12_15             = &argField{Type: TypeSpReg, Shift: 0, BitFields: BitFields{{12, 4}}}
        ap_ImmUnsigned_6_20        = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{6, 15}}}
        ap_ImmUnsigned_11_20       = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{11, 10}}}
+       ap_Reg_21_25               = &argField{Type: TypeReg, Shift: 0, BitFields: BitFields{{21, 5}}}
 )
 
 var instFormats = [...]instFormat{
        {CNTLZW, 0xfc0007ff, 0x7c000034, 0xf800, // Count Leading Zeros Word X-form (cntlzw RA, RS)
                [5]*argField{ap_Reg_11_15, ap_Reg_6_10}},
-       {CNTLZW_, 0xfc0007ff, 0x7c000035, 0xf800, // Count Leading Zeros Word X-form (cntlzw. RA, RS)
+       {CNTLZWCC, 0xfc0007ff, 0x7c000035, 0xf800, // Count Leading Zeros Word X-form (cntlzw. RA, RS)
                [5]*argField{ap_Reg_11_15, ap_Reg_6_10}},
        {B, 0xfc000003, 0x48000000, 0x0, // Branch I-form (b target_addr)
                [5]*argField{ap_PCRel_6_29_shift2}},
@@ -2904,195 +2935,195 @@ var instFormats = [...]instFormat{
                [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_ImmSigned_16_31}},
        {ADD, 0xfc0007ff, 0x7c000214, 0x0, // Add XO-form (add RT,RA,RB)
                [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {ADD_, 0xfc0007ff, 0x7c000215, 0x0, // Add XO-form (add. RT,RA,RB)
+       {ADDCC, 0xfc0007ff, 0x7c000215, 0x0, // Add XO-form (add. RT,RA,RB)
                [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
        {ADDO, 0xfc0007ff, 0x7c000614, 0x0, // Add XO-form (addo RT,RA,RB)
                [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {ADDO_, 0xfc0007ff, 0x7c000615, 0x0, // Add XO-form (addo. RT,RA,RB)
+       {ADDOCC, 0xfc0007ff, 0x7c000615, 0x0, // Add XO-form (addo. RT,RA,RB)
                [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
        {ADDIC, 0xfc000000, 0x30000000, 0x0, // Add Immediate Carrying D-form (addic RT,RA,SI)
                [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_ImmSigned_16_31}},
        {SUBF, 0xfc0007ff, 0x7c000050, 0x0, // Subtract From XO-form (subf RT,RA,RB)
                [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {SUBF_, 0xfc0007ff, 0x7c000051, 0x0, // Subtract From XO-form (subf. RT,RA,RB)
+       {SUBFCC, 0xfc0007ff, 0x7c000051, 0x0, // Subtract From XO-form (subf. RT,RA,RB)
                [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
        {SUBFO, 0xfc0007ff, 0x7c000450, 0x0, // Subtract From XO-form (subfo RT,RA,RB)
                [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {SUBFO_, 0xfc0007ff, 0x7c000451, 0x0, // Subtract From XO-form (subfo. RT,RA,RB)
+       {SUBFOCC, 0xfc0007ff, 0x7c000451, 0x0, // Subtract From XO-form (subfo. RT,RA,RB)
                [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {ADDIC_, 0xfc000000, 0x34000000, 0x0, // Add Immediate Carrying and Record D-form (addic. RT,RA,SI)
+       {ADDICCC, 0xfc000000, 0x34000000, 0x0, // Add Immediate Carrying and Record D-form (addic. RT,RA,SI)
                [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_ImmSigned_16_31}},
        {SUBFIC, 0xfc000000, 0x20000000, 0x0, // Subtract From Immediate Carrying D-form (subfic RT,RA,SI)
                [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_ImmSigned_16_31}},
        {ADDC, 0xfc0007ff, 0x7c000014, 0x0, // Add Carrying XO-form (addc RT,RA,RB)
                [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {ADDC_, 0xfc0007ff, 0x7c000015, 0x0, // Add Carrying XO-form (addc. RT,RA,RB)
+       {ADDCCC, 0xfc0007ff, 0x7c000015, 0x0, // Add Carrying XO-form (addc. RT,RA,RB)
                [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
        {ADDCO, 0xfc0007ff, 0x7c000414, 0x0, // Add Carrying XO-form (addco RT,RA,RB)
                [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {ADDCO_, 0xfc0007ff, 0x7c000415, 0x0, // Add Carrying XO-form (addco. RT,RA,RB)
+       {ADDCOCC, 0xfc0007ff, 0x7c000415, 0x0, // Add Carrying XO-form (addco. RT,RA,RB)
                [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
        {SUBFC, 0xfc0007ff, 0x7c000010, 0x0, // Subtract From Carrying XO-form (subfc RT,RA,RB)
                [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {SUBFC_, 0xfc0007ff, 0x7c000011, 0x0, // Subtract From Carrying XO-form (subfc. RT,RA,RB)
+       {SUBFCCC, 0xfc0007ff, 0x7c000011, 0x0, // Subtract From Carrying XO-form (subfc. RT,RA,RB)
                [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
        {SUBFCO, 0xfc0007ff, 0x7c000410, 0x0, // Subtract From Carrying XO-form (subfco RT,RA,RB)
                [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {SUBFCO_, 0xfc0007ff, 0x7c000411, 0x0, // Subtract From Carrying XO-form (subfco. RT,RA,RB)
+       {SUBFCOCC, 0xfc0007ff, 0x7c000411, 0x0, // Subtract From Carrying XO-form (subfco. RT,RA,RB)
                [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
        {ADDE, 0xfc0007ff, 0x7c000114, 0x0, // Add Extended XO-form (adde RT,RA,RB)
                [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {ADDE_, 0xfc0007ff, 0x7c000115, 0x0, // Add Extended XO-form (adde. RT,RA,RB)
+       {ADDECC, 0xfc0007ff, 0x7c000115, 0x0, // Add Extended XO-form (adde. RT,RA,RB)
                [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
        {ADDEO, 0xfc0007ff, 0x7c000514, 0x0, // Add Extended XO-form (addeo RT,RA,RB)
                [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {ADDEO_, 0xfc0007ff, 0x7c000515, 0x0, // Add Extended XO-form (addeo. RT,RA,RB)
+       {ADDEOCC, 0xfc0007ff, 0x7c000515, 0x0, // Add Extended XO-form (addeo. RT,RA,RB)
                [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
        {ADDME, 0xfc0007ff, 0x7c0001d4, 0xf800, // Add to Minus One Extended XO-form (addme RT,RA)
                [5]*argField{ap_Reg_6_10, ap_Reg_11_15}},
-       {ADDME_, 0xfc0007ff, 0x7c0001d5, 0xf800, // Add to Minus One Extended XO-form (addme. RT,RA)
+       {ADDMECC, 0xfc0007ff, 0x7c0001d5, 0xf800, // Add to Minus One Extended XO-form (addme. RT,RA)
                [5]*argField{ap_Reg_6_10, ap_Reg_11_15}},
        {ADDMEO, 0xfc0007ff, 0x7c0005d4, 0xf800, // Add to Minus One Extended XO-form (addmeo RT,RA)
                [5]*argField{ap_Reg_6_10, ap_Reg_11_15}},
-       {ADDMEO_, 0xfc0007ff, 0x7c0005d5, 0xf800, // Add to Minus One Extended XO-form (addmeo. RT,RA)
+       {ADDMEOCC, 0xfc0007ff, 0x7c0005d5, 0xf800, // Add to Minus One Extended XO-form (addmeo. RT,RA)
                [5]*argField{ap_Reg_6_10, ap_Reg_11_15}},
        {SUBFE, 0xfc0007ff, 0x7c000110, 0x0, // Subtract From Extended XO-form (subfe RT,RA,RB)
                [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {SUBFE_, 0xfc0007ff, 0x7c000111, 0x0, // Subtract From Extended XO-form (subfe. RT,RA,RB)
+       {SUBFECC, 0xfc0007ff, 0x7c000111, 0x0, // Subtract From Extended XO-form (subfe. RT,RA,RB)
                [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
        {SUBFEO, 0xfc0007ff, 0x7c000510, 0x0, // Subtract From Extended XO-form (subfeo RT,RA,RB)
                [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {SUBFEO_, 0xfc0007ff, 0x7c000511, 0x0, // Subtract From Extended XO-form (subfeo. RT,RA,RB)
+       {SUBFEOCC, 0xfc0007ff, 0x7c000511, 0x0, // Subtract From Extended XO-form (subfeo. RT,RA,RB)
                [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
        {SUBFME, 0xfc0007ff, 0x7c0001d0, 0xf800, // Subtract From Minus One Extended XO-form (subfme RT,RA)
                [5]*argField{ap_Reg_6_10, ap_Reg_11_15}},
-       {SUBFME_, 0xfc0007ff, 0x7c0001d1, 0xf800, // Subtract From Minus One Extended XO-form (subfme. RT,RA)
+       {SUBFMECC, 0xfc0007ff, 0x7c0001d1, 0xf800, // Subtract From Minus One Extended XO-form (subfme. RT,RA)
                [5]*argField{ap_Reg_6_10, ap_Reg_11_15}},
        {SUBFMEO, 0xfc0007ff, 0x7c0005d0, 0xf800, // Subtract From Minus One Extended XO-form (subfmeo RT,RA)
                [5]*argField{ap_Reg_6_10, ap_Reg_11_15}},
-       {SUBFMEO_, 0xfc0007ff, 0x7c0005d1, 0xf800, // Subtract From Minus One Extended XO-form (subfmeo. RT,RA)
+       {SUBFMEOCC, 0xfc0007ff, 0x7c0005d1, 0xf800, // Subtract From Minus One Extended XO-form (subfmeo. RT,RA)
                [5]*argField{ap_Reg_6_10, ap_Reg_11_15}},
        {ADDZE, 0xfc0007ff, 0x7c000194, 0xf800, // Add to Zero Extended XO-form (addze RT,RA)
                [5]*argField{ap_Reg_6_10, ap_Reg_11_15}},
-       {ADDZE_, 0xfc0007ff, 0x7c000195, 0xf800, // Add to Zero Extended XO-form (addze. RT,RA)
+       {ADDZECC, 0xfc0007ff, 0x7c000195, 0xf800, // Add to Zero Extended XO-form (addze. RT,RA)
                [5]*argField{ap_Reg_6_10, ap_Reg_11_15}},
        {ADDZEO, 0xfc0007ff, 0x7c000594, 0xf800, // Add to Zero Extended XO-form (addzeo RT,RA)
                [5]*argField{ap_Reg_6_10, ap_Reg_11_15}},
-       {ADDZEO_, 0xfc0007ff, 0x7c000595, 0xf800, // Add to Zero Extended XO-form (addzeo. RT,RA)
+       {ADDZEOCC, 0xfc0007ff, 0x7c000595, 0xf800, // Add to Zero Extended XO-form (addzeo. RT,RA)
                [5]*argField{ap_Reg_6_10, ap_Reg_11_15}},
        {SUBFZE, 0xfc0007ff, 0x7c000190, 0xf800, // Subtract From Zero Extended XO-form (subfze RT,RA)
                [5]*argField{ap_Reg_6_10, ap_Reg_11_15}},
-       {SUBFZE_, 0xfc0007ff, 0x7c000191, 0xf800, // Subtract From Zero Extended XO-form (subfze. RT,RA)
+       {SUBFZECC, 0xfc0007ff, 0x7c000191, 0xf800, // Subtract From Zero Extended XO-form (subfze. RT,RA)
                [5]*argField{ap_Reg_6_10, ap_Reg_11_15}},
        {SUBFZEO, 0xfc0007ff, 0x7c000590, 0xf800, // Subtract From Zero Extended XO-form (subfzeo RT,RA)
                [5]*argField{ap_Reg_6_10, ap_Reg_11_15}},
-       {SUBFZEO_, 0xfc0007ff, 0x7c000591, 0xf800, // Subtract From Zero Extended XO-form (subfzeo. RT,RA)
+       {SUBFZEOCC, 0xfc0007ff, 0x7c000591, 0xf800, // Subtract From Zero Extended XO-form (subfzeo. RT,RA)
                [5]*argField{ap_Reg_6_10, ap_Reg_11_15}},
        {NEG, 0xfc0007ff, 0x7c0000d0, 0xf800, // Negate XO-form (neg RT,RA)
                [5]*argField{ap_Reg_6_10, ap_Reg_11_15}},
-       {NEG_, 0xfc0007ff, 0x7c0000d1, 0xf800, // Negate XO-form (neg. RT,RA)
+       {NEGCC, 0xfc0007ff, 0x7c0000d1, 0xf800, // Negate XO-form (neg. RT,RA)
                [5]*argField{ap_Reg_6_10, ap_Reg_11_15}},
        {NEGO, 0xfc0007ff, 0x7c0004d0, 0xf800, // Negate XO-form (nego RT,RA)
                [5]*argField{ap_Reg_6_10, ap_Reg_11_15}},
-       {NEGO_, 0xfc0007ff, 0x7c0004d1, 0xf800, // Negate XO-form (nego. RT,RA)
+       {NEGOCC, 0xfc0007ff, 0x7c0004d1, 0xf800, // Negate XO-form (nego. RT,RA)
                [5]*argField{ap_Reg_6_10, ap_Reg_11_15}},
        {MULLI, 0xfc000000, 0x1c000000, 0x0, // Multiply Low Immediate D-form (mulli RT,RA,SI)
                [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_ImmSigned_16_31}},
        {MULLW, 0xfc0007ff, 0x7c0001d6, 0x0, // Multiply Low Word XO-form (mullw RT,RA,RB)
                [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {MULLW_, 0xfc0007ff, 0x7c0001d7, 0x0, // Multiply Low Word XO-form (mullw. RT,RA,RB)
+       {MULLWCC, 0xfc0007ff, 0x7c0001d7, 0x0, // Multiply Low Word XO-form (mullw. RT,RA,RB)
                [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
        {MULLWO, 0xfc0007ff, 0x7c0005d6, 0x0, // Multiply Low Word XO-form (mullwo RT,RA,RB)
                [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {MULLWO_, 0xfc0007ff, 0x7c0005d7, 0x0, // Multiply Low Word XO-form (mullwo. RT,RA,RB)
+       {MULLWOCC, 0xfc0007ff, 0x7c0005d7, 0x0, // Multiply Low Word XO-form (mullwo. RT,RA,RB)
                [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
        {MULHW, 0xfc0003ff, 0x7c000096, 0x400, // Multiply High Word XO-form (mulhw RT,RA,RB)
                [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {MULHW_, 0xfc0003ff, 0x7c000097, 0x400, // Multiply High Word XO-form (mulhw. RT,RA,RB)
+       {MULHWCC, 0xfc0003ff, 0x7c000097, 0x400, // Multiply High Word XO-form (mulhw. RT,RA,RB)
                [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
        {MULHWU, 0xfc0003ff, 0x7c000016, 0x400, // Multiply High Word Unsigned XO-form (mulhwu RT,RA,RB)
                [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {MULHWU_, 0xfc0003ff, 0x7c000017, 0x400, // Multiply High Word Unsigned XO-form (mulhwu. RT,RA,RB)
+       {MULHWUCC, 0xfc0003ff, 0x7c000017, 0x400, // Multiply High Word Unsigned XO-form (mulhwu. RT,RA,RB)
                [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
        {DIVW, 0xfc0007ff, 0x7c0003d6, 0x0, // Divide Word XO-form (divw RT,RA,RB)
                [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {DIVW_, 0xfc0007ff, 0x7c0003d7, 0x0, // Divide Word XO-form (divw. RT,RA,RB)
+       {DIVWCC, 0xfc0007ff, 0x7c0003d7, 0x0, // Divide Word XO-form (divw. RT,RA,RB)
                [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
        {DIVWO, 0xfc0007ff, 0x7c0007d6, 0x0, // Divide Word XO-form (divwo RT,RA,RB)
                [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {DIVWO_, 0xfc0007ff, 0x7c0007d7, 0x0, // Divide Word XO-form (divwo. RT,RA,RB)
+       {DIVWOCC, 0xfc0007ff, 0x7c0007d7, 0x0, // Divide Word XO-form (divwo. RT,RA,RB)
                [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
        {DIVWU, 0xfc0007ff, 0x7c000396, 0x0, // Divide Word Unsigned XO-form (divwu RT,RA,RB)
                [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {DIVWU_, 0xfc0007ff, 0x7c000397, 0x0, // Divide Word Unsigned XO-form (divwu. RT,RA,RB)
+       {DIVWUCC, 0xfc0007ff, 0x7c000397, 0x0, // Divide Word Unsigned XO-form (divwu. RT,RA,RB)
                [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
        {DIVWUO, 0xfc0007ff, 0x7c000796, 0x0, // Divide Word Unsigned XO-form (divwuo RT,RA,RB)
                [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {DIVWUO_, 0xfc0007ff, 0x7c000797, 0x0, // Divide Word Unsigned XO-form (divwuo. RT,RA,RB)
+       {DIVWUOCC, 0xfc0007ff, 0x7c000797, 0x0, // Divide Word Unsigned XO-form (divwuo. RT,RA,RB)
                [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
        {DIVWE, 0xfc0007ff, 0x7c000356, 0x0, // Divide Word Extended XO-form (divwe RT,RA,RB)
                [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {DIVWE_, 0xfc0007ff, 0x7c000357, 0x0, // Divide Word Extended XO-form (divwe. RT,RA,RB)
+       {DIVWECC, 0xfc0007ff, 0x7c000357, 0x0, // Divide Word Extended XO-form (divwe. RT,RA,RB)
                [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
        {DIVWEO, 0xfc0007ff, 0x7c000756, 0x0, // Divide Word Extended XO-form (divweo RT,RA,RB)
                [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {DIVWEO_, 0xfc0007ff, 0x7c000757, 0x0, // Divide Word Extended XO-form (divweo. RT,RA,RB)
+       {DIVWEOCC, 0xfc0007ff, 0x7c000757, 0x0, // Divide Word Extended XO-form (divweo. RT,RA,RB)
                [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
        {DIVWEU, 0xfc0007ff, 0x7c000316, 0x0, // Divide Word Extended Unsigned XO-form (divweu RT,RA,RB)
                [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {DIVWEU_, 0xfc0007ff, 0x7c000317, 0x0, // Divide Word Extended Unsigned XO-form (divweu. RT,RA,RB)
+       {DIVWEUCC, 0xfc0007ff, 0x7c000317, 0x0, // Divide Word Extended Unsigned XO-form (divweu. RT,RA,RB)
                [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
        {DIVWEUO, 0xfc0007ff, 0x7c000716, 0x0, // Divide Word Extended Unsigned XO-form (divweuo RT,RA,RB)
                [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {DIVWEUO_, 0xfc0007ff, 0x7c000717, 0x0, // Divide Word Extended Unsigned XO-form (divweuo. RT,RA,RB)
+       {DIVWEUOCC, 0xfc0007ff, 0x7c000717, 0x0, // Divide Word Extended Unsigned XO-form (divweuo. RT,RA,RB)
                [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
        {MULLD, 0xfc0007ff, 0x7c0001d2, 0x0, // Multiply Low Doubleword XO-form (mulld RT,RA,RB)
                [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {MULLD_, 0xfc0007ff, 0x7c0001d3, 0x0, // Multiply Low Doubleword XO-form (mulld. RT,RA,RB)
+       {MULLDCC, 0xfc0007ff, 0x7c0001d3, 0x0, // Multiply Low Doubleword XO-form (mulld. RT,RA,RB)
                [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
        {MULLDO, 0xfc0007ff, 0x7c0005d2, 0x0, // Multiply Low Doubleword XO-form (mulldo RT,RA,RB)
                [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {MULLDO_, 0xfc0007ff, 0x7c0005d3, 0x0, // Multiply Low Doubleword XO-form (mulldo. RT,RA,RB)
+       {MULLDOCC, 0xfc0007ff, 0x7c0005d3, 0x0, // Multiply Low Doubleword XO-form (mulldo. RT,RA,RB)
                [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
        {MULHDU, 0xfc0003ff, 0x7c000012, 0x400, // Multiply High Doubleword Unsigned XO-form (mulhdu RT,RA,RB)
                [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {MULHDU_, 0xfc0003ff, 0x7c000013, 0x400, // Multiply High Doubleword Unsigned XO-form (mulhdu. RT,RA,RB)
+       {MULHDUCC, 0xfc0003ff, 0x7c000013, 0x400, // Multiply High Doubleword Unsigned XO-form (mulhdu. RT,RA,RB)
                [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
        {MULHD, 0xfc0003ff, 0x7c000092, 0x400, // Multiply High Doubleword XO-form (mulhd RT,RA,RB)
                [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {MULHD_, 0xfc0003ff, 0x7c000093, 0x400, // Multiply High Doubleword XO-form (mulhd. RT,RA,RB)
+       {MULHDCC, 0xfc0003ff, 0x7c000093, 0x400, // Multiply High Doubleword XO-form (mulhd. RT,RA,RB)
                [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
        {DIVD, 0xfc0007ff, 0x7c0003d2, 0x0, // Divide Doubleword XO-form (divd RT,RA,RB)
                [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {DIVD_, 0xfc0007ff, 0x7c0003d3, 0x0, // Divide Doubleword XO-form (divd. RT,RA,RB)
+       {DIVDCC, 0xfc0007ff, 0x7c0003d3, 0x0, // Divide Doubleword XO-form (divd. RT,RA,RB)
                [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
        {DIVDO, 0xfc0007ff, 0x7c0007d2, 0x0, // Divide Doubleword XO-form (divdo RT,RA,RB)
                [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {DIVDO_, 0xfc0007ff, 0x7c0007d3, 0x0, // Divide Doubleword XO-form (divdo. RT,RA,RB)
+       {DIVDOCC, 0xfc0007ff, 0x7c0007d3, 0x0, // Divide Doubleword XO-form (divdo. RT,RA,RB)
                [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
        {DIVDU, 0xfc0007ff, 0x7c000392, 0x0, // Divide Doubleword Unsigned XO-form (divdu RT,RA,RB)
                [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {DIVDU_, 0xfc0007ff, 0x7c000393, 0x0, // Divide Doubleword Unsigned XO-form (divdu. RT,RA,RB)
+       {DIVDUCC, 0xfc0007ff, 0x7c000393, 0x0, // Divide Doubleword Unsigned XO-form (divdu. RT,RA,RB)
                [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
        {DIVDUO, 0xfc0007ff, 0x7c000792, 0x0, // Divide Doubleword Unsigned XO-form (divduo RT,RA,RB)
                [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {DIVDUO_, 0xfc0007ff, 0x7c000793, 0x0, // Divide Doubleword Unsigned XO-form (divduo. RT,RA,RB)
+       {DIVDUOCC, 0xfc0007ff, 0x7c000793, 0x0, // Divide Doubleword Unsigned XO-form (divduo. RT,RA,RB)
                [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
        {DIVDE, 0xfc0007ff, 0x7c000352, 0x0, // Divide Doubleword Extended XO-form (divde RT,RA,RB)
                [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {DIVDE_, 0xfc0007ff, 0x7c000353, 0x0, // Divide Doubleword Extended XO-form (divde. RT,RA,RB)
+       {DIVDECC, 0xfc0007ff, 0x7c000353, 0x0, // Divide Doubleword Extended XO-form (divde. RT,RA,RB)
                [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
        {DIVDEO, 0xfc0007ff, 0x7c000752, 0x0, // Divide Doubleword Extended XO-form (divdeo RT,RA,RB)
                [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {DIVDEO_, 0xfc0007ff, 0x7c000753, 0x0, // Divide Doubleword Extended XO-form (divdeo. RT,RA,RB)
+       {DIVDEOCC, 0xfc0007ff, 0x7c000753, 0x0, // Divide Doubleword Extended XO-form (divdeo. RT,RA,RB)
                [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
        {DIVDEU, 0xfc0007ff, 0x7c000312, 0x0, // Divide Doubleword Extended Unsigned XO-form (divdeu RT,RA,RB)
                [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {DIVDEU_, 0xfc0007ff, 0x7c000313, 0x0, // Divide Doubleword Extended Unsigned XO-form (divdeu. RT,RA,RB)
+       {DIVDEUCC, 0xfc0007ff, 0x7c000313, 0x0, // Divide Doubleword Extended Unsigned XO-form (divdeu. RT,RA,RB)
                [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
        {DIVDEUO, 0xfc0007ff, 0x7c000712, 0x0, // Divide Doubleword Extended Unsigned XO-form (divdeuo RT,RA,RB)
                [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {DIVDEUO_, 0xfc0007ff, 0x7c000713, 0x0, // Divide Doubleword Extended Unsigned XO-form (divdeuo. RT,RA,RB)
+       {DIVDEUOCC, 0xfc0007ff, 0x7c000713, 0x0, // Divide Doubleword Extended Unsigned XO-form (divdeuo. RT,RA,RB)
                [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
        {CMPWI, 0xfc200000, 0x2c000000, 0x400000, // Compare Immediate D-form (cmpwi BF,RA,SI)
                [5]*argField{ap_CondRegField_6_8, ap_Reg_11_15, ap_ImmSigned_16_31}},
@@ -3120,9 +3151,9 @@ var instFormats = [...]instFormat{
                [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20, ap_CondRegBit_21_25}},
        {TD, 0xfc0007fe, 0x7c000088, 0x1, // Trap Doubleword X-form (td TO,RA,RB)
                [5]*argField{ap_ImmUnsigned_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {ANDI_, 0xfc000000, 0x70000000, 0x0, // AND Immediate D-form (andi. RA,RS,UI)
+       {ANDICC, 0xfc000000, 0x70000000, 0x0, // AND Immediate D-form (andi. RA,RS,UI)
                [5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_ImmUnsigned_16_31}},
-       {ANDIS_, 0xfc000000, 0x74000000, 0x0, // AND Immediate Shifted D-form (andis. RA,RS,UI)
+       {ANDISCC, 0xfc000000, 0x74000000, 0x0, // AND Immediate Shifted D-form (andis. RA,RS,UI)
                [5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_ImmUnsigned_16_31}},
        {ORI, 0xfc000000, 0x60000000, 0x0, // OR Immediate D-form (ori RA,RS,UI)
                [5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_ImmUnsigned_16_31}},
@@ -3134,43 +3165,43 @@ var instFormats = [...]instFormat{
                [5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_ImmUnsigned_16_31}},
        {AND, 0xfc0007ff, 0x7c000038, 0x0, // AND X-form (and RA,RS,RB)
                [5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20}},
-       {AND_, 0xfc0007ff, 0x7c000039, 0x0, // AND X-form (and. RA,RS,RB)
+       {ANDCC, 0xfc0007ff, 0x7c000039, 0x0, // AND X-form (and. RA,RS,RB)
                [5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20}},
        {XOR, 0xfc0007ff, 0x7c000278, 0x0, // XOR X-form (xor RA,RS,RB)
                [5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20}},
-       {XOR_, 0xfc0007ff, 0x7c000279, 0x0, // XOR X-form (xor. RA,RS,RB)
+       {XORCC, 0xfc0007ff, 0x7c000279, 0x0, // XOR X-form (xor. RA,RS,RB)
                [5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20}},
        {NAND, 0xfc0007ff, 0x7c0003b8, 0x0, // NAND X-form (nand RA,RS,RB)
                [5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20}},
-       {NAND_, 0xfc0007ff, 0x7c0003b9, 0x0, // NAND X-form (nand. RA,RS,RB)
+       {NANDCC, 0xfc0007ff, 0x7c0003b9, 0x0, // NAND X-form (nand. RA,RS,RB)
                [5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20}},
        {OR, 0xfc0007ff, 0x7c000378, 0x0, // OR X-form (or RA,RS,RB)
                [5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20}},
-       {OR_, 0xfc0007ff, 0x7c000379, 0x0, // OR X-form (or. RA,RS,RB)
+       {ORCC, 0xfc0007ff, 0x7c000379, 0x0, // OR X-form (or. RA,RS,RB)
                [5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20}},
        {NOR, 0xfc0007ff, 0x7c0000f8, 0x0, // NOR X-form (nor RA,RS,RB)
                [5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20}},
-       {NOR_, 0xfc0007ff, 0x7c0000f9, 0x0, // NOR X-form (nor. RA,RS,RB)
+       {NORCC, 0xfc0007ff, 0x7c0000f9, 0x0, // NOR X-form (nor. RA,RS,RB)
                [5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20}},
        {ANDC, 0xfc0007ff, 0x7c000078, 0x0, // AND with Complement X-form (andc RA,RS,RB)
                [5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20}},
-       {ANDC_, 0xfc0007ff, 0x7c000079, 0x0, // AND with Complement X-form (andc. RA,RS,RB)
+       {ANDCCC, 0xfc0007ff, 0x7c000079, 0x0, // AND with Complement X-form (andc. RA,RS,RB)
                [5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20}},
        {EXTSB, 0xfc0007ff, 0x7c000774, 0xf800, // Extend Sign Byte X-form (extsb RA,RS)
                [5]*argField{ap_Reg_11_15, ap_Reg_6_10}},
-       {EXTSB_, 0xfc0007ff, 0x7c000775, 0xf800, // Extend Sign Byte X-form (extsb. RA,RS)
+       {EXTSBCC, 0xfc0007ff, 0x7c000775, 0xf800, // Extend Sign Byte X-form (extsb. RA,RS)
                [5]*argField{ap_Reg_11_15, ap_Reg_6_10}},
        {EQV, 0xfc0007ff, 0x7c000238, 0x0, // Equivalent X-form (eqv RA,RS,RB)
                [5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20}},
-       {EQV_, 0xfc0007ff, 0x7c000239, 0x0, // Equivalent X-form (eqv. RA,RS,RB)
+       {EQVCC, 0xfc0007ff, 0x7c000239, 0x0, // Equivalent X-form (eqv. RA,RS,RB)
                [5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20}},
        {ORC, 0xfc0007ff, 0x7c000338, 0x0, // OR with Complement X-form (orc RA,RS,RB)
                [5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20}},
-       {ORC_, 0xfc0007ff, 0x7c000339, 0x0, // OR with Complement X-form (orc. RA,RS,RB)
+       {ORCCC, 0xfc0007ff, 0x7c000339, 0x0, // OR with Complement X-form (orc. RA,RS,RB)
                [5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20}},
        {EXTSH, 0xfc0007ff, 0x7c000734, 0xf800, // Extend Sign Halfword X-form (extsh RA,RS)
                [5]*argField{ap_Reg_11_15, ap_Reg_6_10}},
-       {EXTSH_, 0xfc0007ff, 0x7c000735, 0xf800, // Extend Sign Halfword X-form (extsh. RA,RS)
+       {EXTSHCC, 0xfc0007ff, 0x7c000735, 0xf800, // Extend Sign Halfword X-form (extsh. RA,RS)
                [5]*argField{ap_Reg_11_15, ap_Reg_6_10}},
        {CMPB, 0xfc0007fe, 0x7c0003f8, 0x1, // Compare Bytes X-form (cmpb RA,RS,RB)
                [5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20}},
@@ -3184,11 +3215,11 @@ var instFormats = [...]instFormat{
                [5]*argField{ap_Reg_11_15, ap_Reg_6_10}},
        {EXTSW, 0xfc0007ff, 0x7c0007b4, 0xf800, // Extend Sign Word X-form (extsw RA,RS)
                [5]*argField{ap_Reg_11_15, ap_Reg_6_10}},
-       {EXTSW_, 0xfc0007ff, 0x7c0007b5, 0xf800, // Extend Sign Word X-form (extsw. RA,RS)
+       {EXTSWCC, 0xfc0007ff, 0x7c0007b5, 0xf800, // Extend Sign Word X-form (extsw. RA,RS)
                [5]*argField{ap_Reg_11_15, ap_Reg_6_10}},
        {CNTLZD, 0xfc0007ff, 0x7c000074, 0xf800, // Count Leading Zeros Doubleword X-form (cntlzd RA,RS)
                [5]*argField{ap_Reg_11_15, ap_Reg_6_10}},
-       {CNTLZD_, 0xfc0007ff, 0x7c000075, 0xf800, // Count Leading Zeros Doubleword X-form (cntlzd. RA,RS)
+       {CNTLZDCC, 0xfc0007ff, 0x7c000075, 0xf800, // Count Leading Zeros Doubleword X-form (cntlzd. RA,RS)
                [5]*argField{ap_Reg_11_15, ap_Reg_6_10}},
        {POPCNTD, 0xfc0007fe, 0x7c0003f4, 0xf801, // Population Count Doubleword X-form (popcntd RA, RS)
                [5]*argField{ap_Reg_11_15, ap_Reg_6_10}},
@@ -3196,71 +3227,71 @@ var instFormats = [...]instFormat{
                [5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20}},
        {RLWINM, 0xfc000001, 0x54000000, 0x0, // Rotate Left Word Immediate then AND with Mask M-form (rlwinm RA,RS,SH,MB,ME)
                [5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_ImmUnsigned_16_20, ap_ImmUnsigned_21_25, ap_ImmUnsigned_26_30}},
-       {RLWINM_, 0xfc000001, 0x54000001, 0x0, // Rotate Left Word Immediate then AND with Mask M-form (rlwinm. RA,RS,SH,MB,ME)
+       {RLWINMCC, 0xfc000001, 0x54000001, 0x0, // Rotate Left Word Immediate then AND with Mask M-form (rlwinm. RA,RS,SH,MB,ME)
                [5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_ImmUnsigned_16_20, ap_ImmUnsigned_21_25, ap_ImmUnsigned_26_30}},
        {RLWNM, 0xfc000001, 0x5c000000, 0x0, // Rotate Left Word then AND with Mask M-form (rlwnm RA,RS,RB,MB,ME)
                [5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20, ap_ImmUnsigned_21_25, ap_ImmUnsigned_26_30}},
-       {RLWNM_, 0xfc000001, 0x5c000001, 0x0, // Rotate Left Word then AND with Mask M-form (rlwnm. RA,RS,RB,MB,ME)
+       {RLWNMCC, 0xfc000001, 0x5c000001, 0x0, // Rotate Left Word then AND with Mask M-form (rlwnm. RA,RS,RB,MB,ME)
                [5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20, ap_ImmUnsigned_21_25, ap_ImmUnsigned_26_30}},
        {RLWIMI, 0xfc000001, 0x50000000, 0x0, // Rotate Left Word Immediate then Mask Insert M-form (rlwimi RA,RS,SH,MB,ME)
                [5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_ImmUnsigned_16_20, ap_ImmUnsigned_21_25, ap_ImmUnsigned_26_30}},
-       {RLWIMI_, 0xfc000001, 0x50000001, 0x0, // Rotate Left Word Immediate then Mask Insert M-form (rlwimi. RA,RS,SH,MB,ME)
+       {RLWIMICC, 0xfc000001, 0x50000001, 0x0, // Rotate Left Word Immediate then Mask Insert M-form (rlwimi. RA,RS,SH,MB,ME)
                [5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_ImmUnsigned_16_20, ap_ImmUnsigned_21_25, ap_ImmUnsigned_26_30}},
        {RLDICL, 0xfc00001d, 0x78000000, 0x0, // Rotate Left Doubleword Immediate then Clear Left MD-form (rldicl RA,RS,SH,MB)
                [5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_ImmUnsigned_30_30_16_20, ap_ImmUnsigned_26_26_21_25}},
-       {RLDICL_, 0xfc00001d, 0x78000001, 0x0, // Rotate Left Doubleword Immediate then Clear Left MD-form (rldicl. RA,RS,SH,MB)
+       {RLDICLCC, 0xfc00001d, 0x78000001, 0x0, // Rotate Left Doubleword Immediate then Clear Left MD-form (rldicl. RA,RS,SH,MB)
                [5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_ImmUnsigned_30_30_16_20, ap_ImmUnsigned_26_26_21_25}},
        {RLDICR, 0xfc00001d, 0x78000004, 0x0, // Rotate Left Doubleword Immediate then Clear Right MD-form (rldicr RA,RS,SH,ME)
                [5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_ImmUnsigned_30_30_16_20, ap_ImmUnsigned_26_26_21_25}},
-       {RLDICR_, 0xfc00001d, 0x78000005, 0x0, // Rotate Left Doubleword Immediate then Clear Right MD-form (rldicr. RA,RS,SH,ME)
+       {RLDICRCC, 0xfc00001d, 0x78000005, 0x0, // Rotate Left Doubleword Immediate then Clear Right MD-form (rldicr. RA,RS,SH,ME)
                [5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_ImmUnsigned_30_30_16_20, ap_ImmUnsigned_26_26_21_25}},
        {RLDIC, 0xfc00001d, 0x78000008, 0x0, // Rotate Left Doubleword Immediate then Clear MD-form (rldic RA,RS,SH,MB)
                [5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_ImmUnsigned_30_30_16_20, ap_ImmUnsigned_26_26_21_25}},
-       {RLDIC_, 0xfc00001d, 0x78000009, 0x0, // Rotate Left Doubleword Immediate then Clear MD-form (rldic. RA,RS,SH,MB)
+       {RLDICCC, 0xfc00001d, 0x78000009, 0x0, // Rotate Left Doubleword Immediate then Clear MD-form (rldic. RA,RS,SH,MB)
                [5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_ImmUnsigned_30_30_16_20, ap_ImmUnsigned_26_26_21_25}},
        {RLDCL, 0xfc00001f, 0x78000010, 0x0, // Rotate Left Doubleword then Clear Left MDS-form (rldcl RA,RS,RB,MB)
                [5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20, ap_ImmUnsigned_26_26_21_25}},
-       {RLDCL_, 0xfc00001f, 0x78000011, 0x0, // Rotate Left Doubleword then Clear Left MDS-form (rldcl. RA,RS,RB,MB)
+       {RLDCLCC, 0xfc00001f, 0x78000011, 0x0, // Rotate Left Doubleword then Clear Left MDS-form (rldcl. RA,RS,RB,MB)
                [5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20, ap_ImmUnsigned_26_26_21_25}},
        {RLDCR, 0xfc00001f, 0x78000012, 0x0, // Rotate Left Doubleword then Clear Right MDS-form (rldcr RA,RS,RB,ME)
                [5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20, ap_ImmUnsigned_26_26_21_25}},
-       {RLDCR_, 0xfc00001f, 0x78000013, 0x0, // Rotate Left Doubleword then Clear Right MDS-form (rldcr. RA,RS,RB,ME)
+       {RLDCRCC, 0xfc00001f, 0x78000013, 0x0, // Rotate Left Doubleword then Clear Right MDS-form (rldcr. RA,RS,RB,ME)
                [5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20, ap_ImmUnsigned_26_26_21_25}},
        {RLDIMI, 0xfc00001d, 0x7800000c, 0x0, // Rotate Left Doubleword Immediate then Mask Insert MD-form (rldimi RA,RS,SH,MB)
                [5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_ImmUnsigned_30_30_16_20, ap_ImmUnsigned_26_26_21_25}},
-       {RLDIMI_, 0xfc00001d, 0x7800000d, 0x0, // Rotate Left Doubleword Immediate then Mask Insert MD-form (rldimi. RA,RS,SH,MB)
+       {RLDIMICC, 0xfc00001d, 0x7800000d, 0x0, // Rotate Left Doubleword Immediate then Mask Insert MD-form (rldimi. RA,RS,SH,MB)
                [5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_ImmUnsigned_30_30_16_20, ap_ImmUnsigned_26_26_21_25}},
        {SLW, 0xfc0007ff, 0x7c000030, 0x0, // Shift Left Word X-form (slw RA,RS,RB)
                [5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20}},
-       {SLW_, 0xfc0007ff, 0x7c000031, 0x0, // Shift Left Word X-form (slw. RA,RS,RB)
+       {SLWCC, 0xfc0007ff, 0x7c000031, 0x0, // Shift Left Word X-form (slw. RA,RS,RB)
                [5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20}},
        {SRW, 0xfc0007ff, 0x7c000430, 0x0, // Shift Right Word X-form (srw RA,RS,RB)
                [5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20}},
-       {SRW_, 0xfc0007ff, 0x7c000431, 0x0, // Shift Right Word X-form (srw. RA,RS,RB)
+       {SRWCC, 0xfc0007ff, 0x7c000431, 0x0, // Shift Right Word X-form (srw. RA,RS,RB)
                [5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20}},
        {SRAWI, 0xfc0007ff, 0x7c000670, 0x0, // Shift Right Algebraic Word Immediate X-form (srawi RA,RS,SH)
                [5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_ImmUnsigned_16_20}},
-       {SRAWI_, 0xfc0007ff, 0x7c000671, 0x0, // Shift Right Algebraic Word Immediate X-form (srawi. RA,RS,SH)
+       {SRAWICC, 0xfc0007ff, 0x7c000671, 0x0, // Shift Right Algebraic Word Immediate X-form (srawi. RA,RS,SH)
                [5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_ImmUnsigned_16_20}},
        {SRAW, 0xfc0007ff, 0x7c000630, 0x0, // Shift Right Algebraic Word X-form (sraw RA,RS,RB)
                [5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20}},
-       {SRAW_, 0xfc0007ff, 0x7c000631, 0x0, // Shift Right Algebraic Word X-form (sraw. RA,RS,RB)
+       {SRAWCC, 0xfc0007ff, 0x7c000631, 0x0, // Shift Right Algebraic Word X-form (sraw. RA,RS,RB)
                [5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20}},
        {SLD, 0xfc0007ff, 0x7c000036, 0x0, // Shift Left Doubleword X-form (sld RA,RS,RB)
                [5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20}},
-       {SLD_, 0xfc0007ff, 0x7c000037, 0x0, // Shift Left Doubleword X-form (sld. RA,RS,RB)
+       {SLDCC, 0xfc0007ff, 0x7c000037, 0x0, // Shift Left Doubleword X-form (sld. RA,RS,RB)
                [5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20}},
        {SRD, 0xfc0007ff, 0x7c000436, 0x0, // Shift Right Doubleword X-form (srd RA,RS,RB)
                [5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20}},
-       {SRD_, 0xfc0007ff, 0x7c000437, 0x0, // Shift Right Doubleword X-form (srd. RA,RS,RB)
+       {SRDCC, 0xfc0007ff, 0x7c000437, 0x0, // Shift Right Doubleword X-form (srd. RA,RS,RB)
                [5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20}},
        {SRADI, 0xfc0007fd, 0x7c000674, 0x0, // Shift Right Algebraic Doubleword Immediate XS-form (sradi RA,RS,SH)
                [5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_ImmUnsigned_30_30_16_20}},
-       {SRADI_, 0xfc0007fd, 0x7c000675, 0x0, // Shift Right Algebraic Doubleword Immediate XS-form (sradi. RA,RS,SH)
+       {SRADICC, 0xfc0007fd, 0x7c000675, 0x0, // Shift Right Algebraic Doubleword Immediate XS-form (sradi. RA,RS,SH)
                [5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_ImmUnsigned_30_30_16_20}},
        {SRAD, 0xfc0007ff, 0x7c000634, 0x0, // Shift Right Algebraic Doubleword X-form (srad RA,RS,RB)
                [5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20}},
-       {SRAD_, 0xfc0007ff, 0x7c000635, 0x0, // Shift Right Algebraic Doubleword X-form (srad. RA,RS,RB)
+       {SRADCC, 0xfc0007ff, 0x7c000635, 0x0, // Shift Right Algebraic Doubleword X-form (srad. RA,RS,RB)
                [5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20}},
        {CDTBCD, 0xfc0007fe, 0x7c000234, 0xf801, // Convert Declets To Binary Coded Decimal X-form (cdtbcd RA, RS)
                [5]*argField{ap_Reg_11_15, ap_Reg_6_10}},
@@ -3346,23 +3377,23 @@ var instFormats = [...]instFormat{
                [5]*argField{ap_FPReg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
        {FMR, 0xfc0007ff, 0xfc000090, 0x1f0000, // Floating Move Register X-form (fmr FRT,FRB)
                [5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
-       {FMR_, 0xfc0007ff, 0xfc000091, 0x1f0000, // Floating Move Register X-form (fmr. FRT,FRB)
+       {FMRCC, 0xfc0007ff, 0xfc000091, 0x1f0000, // Floating Move Register X-form (fmr. FRT,FRB)
                [5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
        {FABS, 0xfc0007ff, 0xfc000210, 0x1f0000, // Floating Absolute Value X-form (fabs FRT,FRB)
                [5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
-       {FABS_, 0xfc0007ff, 0xfc000211, 0x1f0000, // Floating Absolute Value X-form (fabs. FRT,FRB)
+       {FABSCC, 0xfc0007ff, 0xfc000211, 0x1f0000, // Floating Absolute Value X-form (fabs. FRT,FRB)
                [5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
        {FNABS, 0xfc0007ff, 0xfc000110, 0x1f0000, // Floating Negative Absolute Value X-form (fnabs FRT,FRB)
                [5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
-       {FNABS_, 0xfc0007ff, 0xfc000111, 0x1f0000, // Floating Negative Absolute Value X-form (fnabs. FRT,FRB)
+       {FNABSCC, 0xfc0007ff, 0xfc000111, 0x1f0000, // Floating Negative Absolute Value X-form (fnabs. FRT,FRB)
                [5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
        {FNEG, 0xfc0007ff, 0xfc000050, 0x1f0000, // Floating Negate X-form (fneg FRT,FRB)
                [5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
-       {FNEG_, 0xfc0007ff, 0xfc000051, 0x1f0000, // Floating Negate X-form (fneg. FRT,FRB)
+       {FNEGCC, 0xfc0007ff, 0xfc000051, 0x1f0000, // Floating Negate X-form (fneg. FRT,FRB)
                [5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
        {FCPSGN, 0xfc0007ff, 0xfc000010, 0x0, // Floating Copy Sign X-form (fcpsgn FRT, FRA, FRB)
                [5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_16_20}},
-       {FCPSGN_, 0xfc0007ff, 0xfc000011, 0x0, // Floating Copy Sign X-form (fcpsgn. FRT, FRA, FRB)
+       {FCPSGNCC, 0xfc0007ff, 0xfc000011, 0x0, // Floating Copy Sign X-form (fcpsgn. FRT, FRA, FRB)
                [5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_16_20}},
        {FMRGEW, 0xfc0007fe, 0xfc00078c, 0x1, // Floating Merge Even Word X-form (fmrgew FRT,FRA,FRB)
                [5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_16_20}},
@@ -3370,59 +3401,59 @@ var instFormats = [...]instFormat{
                [5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_16_20}},
        {FADD, 0xfc00003f, 0xfc00002a, 0x7c0, // Floating Add [Single] A-form (fadd FRT,FRA,FRB)
                [5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_16_20}},
-       {FADD_, 0xfc00003f, 0xfc00002b, 0x7c0, // Floating Add [Single] A-form (fadd. FRT,FRA,FRB)
+       {FADDCC, 0xfc00003f, 0xfc00002b, 0x7c0, // Floating Add [Single] A-form (fadd. FRT,FRA,FRB)
                [5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_16_20}},
        {FADDS, 0xfc00003f, 0xec00002a, 0x7c0, // Floating Add [Single] A-form (fadds FRT,FRA,FRB)
                [5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_16_20}},
-       {FADDS_, 0xfc00003f, 0xec00002b, 0x7c0, // Floating Add [Single] A-form (fadds. FRT,FRA,FRB)
+       {FADDSCC, 0xfc00003f, 0xec00002b, 0x7c0, // Floating Add [Single] A-form (fadds. FRT,FRA,FRB)
                [5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_16_20}},
        {FSUB, 0xfc00003f, 0xfc000028, 0x7c0, // Floating Subtract [Single] A-form (fsub FRT,FRA,FRB)
                [5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_16_20}},
-       {FSUB_, 0xfc00003f, 0xfc000029, 0x7c0, // Floating Subtract [Single] A-form (fsub. FRT,FRA,FRB)
+       {FSUBCC, 0xfc00003f, 0xfc000029, 0x7c0, // Floating Subtract [Single] A-form (fsub. FRT,FRA,FRB)
                [5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_16_20}},
        {FSUBS, 0xfc00003f, 0xec000028, 0x7c0, // Floating Subtract [Single] A-form (fsubs FRT,FRA,FRB)
                [5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_16_20}},
-       {FSUBS_, 0xfc00003f, 0xec000029, 0x7c0, // Floating Subtract [Single] A-form (fsubs. FRT,FRA,FRB)
+       {FSUBSCC, 0xfc00003f, 0xec000029, 0x7c0, // Floating Subtract [Single] A-form (fsubs. FRT,FRA,FRB)
                [5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_16_20}},
        {FMUL, 0xfc00003f, 0xfc000032, 0xf800, // Floating Multiply [Single] A-form (fmul FRT,FRA,FRC)
                [5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_21_25}},
-       {FMUL_, 0xfc00003f, 0xfc000033, 0xf800, // Floating Multiply [Single] A-form (fmul. FRT,FRA,FRC)
+       {FMULCC, 0xfc00003f, 0xfc000033, 0xf800, // Floating Multiply [Single] A-form (fmul. FRT,FRA,FRC)
                [5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_21_25}},
        {FMULS, 0xfc00003f, 0xec000032, 0xf800, // Floating Multiply [Single] A-form (fmuls FRT,FRA,FRC)
                [5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_21_25}},
-       {FMULS_, 0xfc00003f, 0xec000033, 0xf800, // Floating Multiply [Single] A-form (fmuls. FRT,FRA,FRC)
+       {FMULSCC, 0xfc00003f, 0xec000033, 0xf800, // Floating Multiply [Single] A-form (fmuls. FRT,FRA,FRC)
                [5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_21_25}},
        {FDIV, 0xfc00003f, 0xfc000024, 0x7c0, // Floating Divide [Single] A-form (fdiv FRT,FRA,FRB)
                [5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_16_20}},
-       {FDIV_, 0xfc00003f, 0xfc000025, 0x7c0, // Floating Divide [Single] A-form (fdiv. FRT,FRA,FRB)
+       {FDIVCC, 0xfc00003f, 0xfc000025, 0x7c0, // Floating Divide [Single] A-form (fdiv. FRT,FRA,FRB)
                [5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_16_20}},
        {FDIVS, 0xfc00003f, 0xec000024, 0x7c0, // Floating Divide [Single] A-form (fdivs FRT,FRA,FRB)
                [5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_16_20}},
-       {FDIVS_, 0xfc00003f, 0xec000025, 0x7c0, // Floating Divide [Single] A-form (fdivs. FRT,FRA,FRB)
+       {FDIVSCC, 0xfc00003f, 0xec000025, 0x7c0, // Floating Divide [Single] A-form (fdivs. FRT,FRA,FRB)
                [5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_16_20}},
        {FSQRT, 0xfc00003f, 0xfc00002c, 0x1f07c0, // Floating Square Root [Single] A-form (fsqrt FRT,FRB)
                [5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
-       {FSQRT_, 0xfc00003f, 0xfc00002d, 0x1f07c0, // Floating Square Root [Single] A-form (fsqrt. FRT,FRB)
+       {FSQRTCC, 0xfc00003f, 0xfc00002d, 0x1f07c0, // Floating Square Root [Single] A-form (fsqrt. FRT,FRB)
                [5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
        {FSQRTS, 0xfc00003f, 0xec00002c, 0x1f07c0, // Floating Square Root [Single] A-form (fsqrts FRT,FRB)
                [5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
-       {FSQRTS_, 0xfc00003f, 0xec00002d, 0x1f07c0, // Floating Square Root [Single] A-form (fsqrts. FRT,FRB)
+       {FSQRTSCC, 0xfc00003f, 0xec00002d, 0x1f07c0, // Floating Square Root [Single] A-form (fsqrts. FRT,FRB)
                [5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
        {FRE, 0xfc00003f, 0xfc000030, 0x1f07c0, // Floating Reciprocal Estimate [Single] A-form (fre FRT,FRB)
                [5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
-       {FRE_, 0xfc00003f, 0xfc000031, 0x1f07c0, // Floating Reciprocal Estimate [Single] A-form (fre. FRT,FRB)
+       {FRECC, 0xfc00003f, 0xfc000031, 0x1f07c0, // Floating Reciprocal Estimate [Single] A-form (fre. FRT,FRB)
                [5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
        {FRES, 0xfc00003f, 0xec000030, 0x1f07c0, // Floating Reciprocal Estimate [Single] A-form (fres FRT,FRB)
                [5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
-       {FRES_, 0xfc00003f, 0xec000031, 0x1f07c0, // Floating Reciprocal Estimate [Single] A-form (fres. FRT,FRB)
+       {FRESCC, 0xfc00003f, 0xec000031, 0x1f07c0, // Floating Reciprocal Estimate [Single] A-form (fres. FRT,FRB)
                [5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
        {FRSQRTE, 0xfc00003f, 0xfc000034, 0x1f07c0, // Floating Reciprocal Square Root Estimate [Single] A-form (frsqrte FRT,FRB)
                [5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
-       {FRSQRTE_, 0xfc00003f, 0xfc000035, 0x1f07c0, // Floating Reciprocal Square Root Estimate [Single] A-form (frsqrte. FRT,FRB)
+       {FRSQRTECC, 0xfc00003f, 0xfc000035, 0x1f07c0, // Floating Reciprocal Square Root Estimate [Single] A-form (frsqrte. FRT,FRB)
                [5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
        {FRSQRTES, 0xfc00003f, 0xec000034, 0x1f07c0, // Floating Reciprocal Square Root Estimate [Single] A-form (frsqrtes FRT,FRB)
                [5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
-       {FRSQRTES_, 0xfc00003f, 0xec000035, 0x1f07c0, // Floating Reciprocal Square Root Estimate [Single] A-form (frsqrtes. FRT,FRB)
+       {FRSQRTESCC, 0xfc00003f, 0xec000035, 0x1f07c0, // Floating Reciprocal Square Root Estimate [Single] A-form (frsqrtes. FRT,FRB)
                [5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
        {FTDIV, 0xfc0007fe, 0xfc000100, 0x600001, // Floating Test for software Divide X-form (ftdiv BF,FRA,FRB)
                [5]*argField{ap_CondRegField_6_8, ap_FPReg_11_15, ap_FPReg_16_20}},
@@ -3430,103 +3461,103 @@ var instFormats = [...]instFormat{
                [5]*argField{ap_CondRegField_6_8, ap_FPReg_16_20}},
        {FMADD, 0xfc00003f, 0xfc00003a, 0x0, // Floating Multiply-Add [Single] A-form (fmadd FRT,FRA,FRC,FRB)
                [5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_21_25, ap_FPReg_16_20}},
-       {FMADD_, 0xfc00003f, 0xfc00003b, 0x0, // Floating Multiply-Add [Single] A-form (fmadd. FRT,FRA,FRC,FRB)
+       {FMADDCC, 0xfc00003f, 0xfc00003b, 0x0, // Floating Multiply-Add [Single] A-form (fmadd. FRT,FRA,FRC,FRB)
                [5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_21_25, ap_FPReg_16_20}},
        {FMADDS, 0xfc00003f, 0xec00003a, 0x0, // Floating Multiply-Add [Single] A-form (fmadds FRT,FRA,FRC,FRB)
                [5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_21_25, ap_FPReg_16_20}},
-       {FMADDS_, 0xfc00003f, 0xec00003b, 0x0, // Floating Multiply-Add [Single] A-form (fmadds. FRT,FRA,FRC,FRB)
+       {FMADDSCC, 0xfc00003f, 0xec00003b, 0x0, // Floating Multiply-Add [Single] A-form (fmadds. FRT,FRA,FRC,FRB)
                [5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_21_25, ap_FPReg_16_20}},
        {FMSUB, 0xfc00003f, 0xfc000038, 0x0, // Floating Multiply-Subtract [Single] A-form (fmsub FRT,FRA,FRC,FRB)
                [5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_21_25, ap_FPReg_16_20}},
-       {FMSUB_, 0xfc00003f, 0xfc000039, 0x0, // Floating Multiply-Subtract [Single] A-form (fmsub. FRT,FRA,FRC,FRB)
+       {FMSUBCC, 0xfc00003f, 0xfc000039, 0x0, // Floating Multiply-Subtract [Single] A-form (fmsub. FRT,FRA,FRC,FRB)
                [5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_21_25, ap_FPReg_16_20}},
        {FMSUBS, 0xfc00003f, 0xec000038, 0x0, // Floating Multiply-Subtract [Single] A-form (fmsubs FRT,FRA,FRC,FRB)
                [5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_21_25, ap_FPReg_16_20}},
-       {FMSUBS_, 0xfc00003f, 0xec000039, 0x0, // Floating Multiply-Subtract [Single] A-form (fmsubs. FRT,FRA,FRC,FRB)
+       {FMSUBSCC, 0xfc00003f, 0xec000039, 0x0, // Floating Multiply-Subtract [Single] A-form (fmsubs. FRT,FRA,FRC,FRB)
                [5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_21_25, ap_FPReg_16_20}},
        {FNMADD, 0xfc00003f, 0xfc00003e, 0x0, // Floating Negative Multiply-Add [Single] A-form (fnmadd FRT,FRA,FRC,FRB)
                [5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_21_25, ap_FPReg_16_20}},
-       {FNMADD_, 0xfc00003f, 0xfc00003f, 0x0, // Floating Negative Multiply-Add [Single] A-form (fnmadd. FRT,FRA,FRC,FRB)
+       {FNMADDCC, 0xfc00003f, 0xfc00003f, 0x0, // Floating Negative Multiply-Add [Single] A-form (fnmadd. FRT,FRA,FRC,FRB)
                [5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_21_25, ap_FPReg_16_20}},
        {FNMADDS, 0xfc00003f, 0xec00003e, 0x0, // Floating Negative Multiply-Add [Single] A-form (fnmadds FRT,FRA,FRC,FRB)
                [5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_21_25, ap_FPReg_16_20}},
-       {FNMADDS_, 0xfc00003f, 0xec00003f, 0x0, // Floating Negative Multiply-Add [Single] A-form (fnmadds. FRT,FRA,FRC,FRB)
+       {FNMADDSCC, 0xfc00003f, 0xec00003f, 0x0, // Floating Negative Multiply-Add [Single] A-form (fnmadds. FRT,FRA,FRC,FRB)
                [5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_21_25, ap_FPReg_16_20}},
        {FNMSUB, 0xfc00003f, 0xfc00003c, 0x0, // Floating Negative Multiply-Subtract [Single] A-form (fnmsub FRT,FRA,FRC,FRB)
                [5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_21_25, ap_FPReg_16_20}},
-       {FNMSUB_, 0xfc00003f, 0xfc00003d, 0x0, // Floating Negative Multiply-Subtract [Single] A-form (fnmsub. FRT,FRA,FRC,FRB)
+       {FNMSUBCC, 0xfc00003f, 0xfc00003d, 0x0, // Floating Negative Multiply-Subtract [Single] A-form (fnmsub. FRT,FRA,FRC,FRB)
                [5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_21_25, ap_FPReg_16_20}},
        {FNMSUBS, 0xfc00003f, 0xec00003c, 0x0, // Floating Negative Multiply-Subtract [Single] A-form (fnmsubs FRT,FRA,FRC,FRB)
                [5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_21_25, ap_FPReg_16_20}},
-       {FNMSUBS_, 0xfc00003f, 0xec00003d, 0x0, // Floating Negative Multiply-Subtract [Single] A-form (fnmsubs. FRT,FRA,FRC,FRB)
+       {FNMSUBSCC, 0xfc00003f, 0xec00003d, 0x0, // Floating Negative Multiply-Subtract [Single] A-form (fnmsubs. FRT,FRA,FRC,FRB)
                [5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_21_25, ap_FPReg_16_20}},
        {FRSP, 0xfc0007ff, 0xfc000018, 0x1f0000, // Floating Round to Single-Precision X-form (frsp FRT,FRB)
                [5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
-       {FRSP_, 0xfc0007ff, 0xfc000019, 0x1f0000, // Floating Round to Single-Precision X-form (frsp. FRT,FRB)
+       {FRSPCC, 0xfc0007ff, 0xfc000019, 0x1f0000, // Floating Round to Single-Precision X-form (frsp. FRT,FRB)
                [5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
        {FCTID, 0xfc0007ff, 0xfc00065c, 0x1f0000, // Floating Convert To Integer Doubleword X-form (fctid FRT,FRB)
                [5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
-       {FCTID_, 0xfc0007ff, 0xfc00065d, 0x1f0000, // Floating Convert To Integer Doubleword X-form (fctid. FRT,FRB)
+       {FCTIDCC, 0xfc0007ff, 0xfc00065d, 0x1f0000, // Floating Convert To Integer Doubleword X-form (fctid. FRT,FRB)
                [5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
        {FCTIDZ, 0xfc0007ff, 0xfc00065e, 0x1f0000, // Floating Convert To Integer Doubleword with round toward Zero X-form (fctidz FRT,FRB)
                [5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
-       {FCTIDZ_, 0xfc0007ff, 0xfc00065f, 0x1f0000, // Floating Convert To Integer Doubleword with round toward Zero X-form (fctidz. FRT,FRB)
+       {FCTIDZCC, 0xfc0007ff, 0xfc00065f, 0x1f0000, // Floating Convert To Integer Doubleword with round toward Zero X-form (fctidz. FRT,FRB)
                [5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
        {FCTIDU, 0xfc0007ff, 0xfc00075c, 0x1f0000, // Floating Convert To Integer Doubleword Unsigned X-form (fctidu FRT,FRB)
                [5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
-       {FCTIDU_, 0xfc0007ff, 0xfc00075d, 0x1f0000, // Floating Convert To Integer Doubleword Unsigned X-form (fctidu. FRT,FRB)
+       {FCTIDUCC, 0xfc0007ff, 0xfc00075d, 0x1f0000, // Floating Convert To Integer Doubleword Unsigned X-form (fctidu. FRT,FRB)
                [5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
        {FCTIDUZ, 0xfc0007ff, 0xfc00075e, 0x1f0000, // Floating Convert To Integer Doubleword Unsigned with round toward Zero X-form (fctiduz FRT,FRB)
                [5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
-       {FCTIDUZ_, 0xfc0007ff, 0xfc00075f, 0x1f0000, // Floating Convert To Integer Doubleword Unsigned with round toward Zero X-form (fctiduz. FRT,FRB)
+       {FCTIDUZCC, 0xfc0007ff, 0xfc00075f, 0x1f0000, // Floating Convert To Integer Doubleword Unsigned with round toward Zero X-form (fctiduz. FRT,FRB)
                [5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
        {FCTIW, 0xfc0007ff, 0xfc00001c, 0x1f0000, // Floating Convert To Integer Word X-form (fctiw FRT,FRB)
                [5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
-       {FCTIW_, 0xfc0007ff, 0xfc00001d, 0x1f0000, // Floating Convert To Integer Word X-form (fctiw. FRT,FRB)
+       {FCTIWCC, 0xfc0007ff, 0xfc00001d, 0x1f0000, // Floating Convert To Integer Word X-form (fctiw. FRT,FRB)
                [5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
        {FCTIWZ, 0xfc0007ff, 0xfc00001e, 0x1f0000, // Floating Convert To Integer Word with round toward Zero X-form (fctiwz FRT,FRB)
                [5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
-       {FCTIWZ_, 0xfc0007ff, 0xfc00001f, 0x1f0000, // Floating Convert To Integer Word with round toward Zero X-form (fctiwz. FRT,FRB)
+       {FCTIWZCC, 0xfc0007ff, 0xfc00001f, 0x1f0000, // Floating Convert To Integer Word with round toward Zero X-form (fctiwz. FRT,FRB)
                [5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
        {FCTIWU, 0xfc0007ff, 0xfc00011c, 0x1f0000, // Floating Convert To Integer Word Unsigned X-form (fctiwu FRT,FRB)
                [5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
-       {FCTIWU_, 0xfc0007ff, 0xfc00011d, 0x1f0000, // Floating Convert To Integer Word Unsigned X-form (fctiwu. FRT,FRB)
+       {FCTIWUCC, 0xfc0007ff, 0xfc00011d, 0x1f0000, // Floating Convert To Integer Word Unsigned X-form (fctiwu. FRT,FRB)
                [5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
        {FCTIWUZ, 0xfc0007ff, 0xfc00011e, 0x1f0000, // Floating Convert To Integer Word Unsigned with round toward Zero X-form (fctiwuz FRT,FRB)
                [5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
-       {FCTIWUZ_, 0xfc0007ff, 0xfc00011f, 0x1f0000, // Floating Convert To Integer Word Unsigned with round toward Zero X-form (fctiwuz. FRT,FRB)
+       {FCTIWUZCC, 0xfc0007ff, 0xfc00011f, 0x1f0000, // Floating Convert To Integer Word Unsigned with round toward Zero X-form (fctiwuz. FRT,FRB)
                [5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
        {FCFID, 0xfc0007ff, 0xfc00069c, 0x1f0000, // Floating Convert From Integer Doubleword X-form (fcfid FRT,FRB)
                [5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
-       {FCFID_, 0xfc0007ff, 0xfc00069d, 0x1f0000, // Floating Convert From Integer Doubleword X-form (fcfid. FRT,FRB)
+       {FCFIDCC, 0xfc0007ff, 0xfc00069d, 0x1f0000, // Floating Convert From Integer Doubleword X-form (fcfid. FRT,FRB)
                [5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
        {FCFIDU, 0xfc0007ff, 0xfc00079c, 0x1f0000, // Floating Convert From Integer Doubleword Unsigned X-form (fcfidu FRT,FRB)
                [5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
-       {FCFIDU_, 0xfc0007ff, 0xfc00079d, 0x1f0000, // Floating Convert From Integer Doubleword Unsigned X-form (fcfidu. FRT,FRB)
+       {FCFIDUCC, 0xfc0007ff, 0xfc00079d, 0x1f0000, // Floating Convert From Integer Doubleword Unsigned X-form (fcfidu. FRT,FRB)
                [5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
        {FCFIDS, 0xfc0007ff, 0xec00069c, 0x1f0000, // Floating Convert From Integer Doubleword Single X-form (fcfids FRT,FRB)
                [5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
-       {FCFIDS_, 0xfc0007ff, 0xec00069d, 0x1f0000, // Floating Convert From Integer Doubleword Single X-form (fcfids. FRT,FRB)
+       {FCFIDSCC, 0xfc0007ff, 0xec00069d, 0x1f0000, // Floating Convert From Integer Doubleword Single X-form (fcfids. FRT,FRB)
                [5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
        {FCFIDUS, 0xfc0007ff, 0xec00079c, 0x1f0000, // Floating Convert From Integer Doubleword Unsigned Single X-form (fcfidus FRT,FRB)
                [5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
-       {FCFIDUS_, 0xfc0007ff, 0xec00079d, 0x1f0000, // Floating Convert From Integer Doubleword Unsigned Single X-form (fcfidus. FRT,FRB)
+       {FCFIDUSCC, 0xfc0007ff, 0xec00079d, 0x1f0000, // Floating Convert From Integer Doubleword Unsigned Single X-form (fcfidus. FRT,FRB)
                [5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
        {FRIN, 0xfc0007ff, 0xfc000310, 0x1f0000, // Floating Round to Integer Nearest X-form (frin FRT,FRB)
                [5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
-       {FRIN_, 0xfc0007ff, 0xfc000311, 0x1f0000, // Floating Round to Integer Nearest X-form (frin. FRT,FRB)
+       {FRINCC, 0xfc0007ff, 0xfc000311, 0x1f0000, // Floating Round to Integer Nearest X-form (frin. FRT,FRB)
                [5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
        {FRIZ, 0xfc0007ff, 0xfc000350, 0x1f0000, // Floating Round to Integer Toward Zero X-form (friz FRT,FRB)
                [5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
-       {FRIZ_, 0xfc0007ff, 0xfc000351, 0x1f0000, // Floating Round to Integer Toward Zero X-form (friz. FRT,FRB)
+       {FRIZCC, 0xfc0007ff, 0xfc000351, 0x1f0000, // Floating Round to Integer Toward Zero X-form (friz. FRT,FRB)
                [5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
        {FRIP, 0xfc0007ff, 0xfc000390, 0x1f0000, // Floating Round to Integer Plus X-form (frip FRT,FRB)
                [5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
-       {FRIP_, 0xfc0007ff, 0xfc000391, 0x1f0000, // Floating Round to Integer Plus X-form (frip. FRT,FRB)
+       {FRIPCC, 0xfc0007ff, 0xfc000391, 0x1f0000, // Floating Round to Integer Plus X-form (frip. FRT,FRB)
                [5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
        {FRIM, 0xfc0007ff, 0xfc0003d0, 0x1f0000, // Floating Round to Integer Minus X-form (frim FRT,FRB)
                [5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
-       {FRIM_, 0xfc0007ff, 0xfc0003d1, 0x1f0000, // Floating Round to Integer Minus X-form (frim. FRT,FRB)
+       {FRIMCC, 0xfc0007ff, 0xfc0003d1, 0x1f0000, // Floating Round to Integer Minus X-form (frim. FRT,FRB)
                [5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
        {FCMPU, 0xfc0007fe, 0xfc000000, 0x600001, // Floating Compare Unordered X-form (fcmpu BF,FRA,FRB)
                [5]*argField{ap_CondRegField_6_8, ap_FPReg_11_15, ap_FPReg_16_20}},
@@ -3534,29 +3565,29 @@ var instFormats = [...]instFormat{
                [5]*argField{ap_CondRegField_6_8, ap_FPReg_11_15, ap_FPReg_16_20}},
        {FSEL, 0xfc00003f, 0xfc00002e, 0x0, // Floating Select A-form (fsel FRT,FRA,FRC,FRB)
                [5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_21_25, ap_FPReg_16_20}},
-       {FSEL_, 0xfc00003f, 0xfc00002f, 0x0, // Floating Select A-form (fsel. FRT,FRA,FRC,FRB)
+       {FSELCC, 0xfc00003f, 0xfc00002f, 0x0, // Floating Select A-form (fsel. FRT,FRA,FRC,FRB)
                [5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_21_25, ap_FPReg_16_20}},
        {MFFS, 0xfc0007ff, 0xfc00048e, 0x1ff800, // Move From FPSCR X-form (mffs FRT)
                [5]*argField{ap_FPReg_6_10}},
-       {MFFS_, 0xfc0007ff, 0xfc00048f, 0x1ff800, // Move From FPSCR X-form (mffs. FRT)
+       {MFFSCC, 0xfc0007ff, 0xfc00048f, 0x1ff800, // Move From FPSCR X-form (mffs. FRT)
                [5]*argField{ap_FPReg_6_10}},
        {MCRFS, 0xfc0007fe, 0xfc000080, 0x63f801, // Move to Condition Register from FPSCR X-form (mcrfs BF,BFA)
                [5]*argField{ap_CondRegField_6_8, ap_CondRegField_11_13}},
        {MTFSFI, 0xfc0007ff, 0xfc00010c, 0x7e0800, // Move To FPSCR Field Immediate X-form (mtfsfi BF,U,W)
                [5]*argField{ap_CondRegField_6_8, ap_ImmUnsigned_16_19, ap_ImmUnsigned_15_15}},
-       {MTFSFI_, 0xfc0007ff, 0xfc00010d, 0x7e0800, // Move To FPSCR Field Immediate X-form (mtfsfi. BF,U,W)
+       {MTFSFICC, 0xfc0007ff, 0xfc00010d, 0x7e0800, // Move To FPSCR Field Immediate X-form (mtfsfi. BF,U,W)
                [5]*argField{ap_CondRegField_6_8, ap_ImmUnsigned_16_19, ap_ImmUnsigned_15_15}},
        {MTFSF, 0xfc0007ff, 0xfc00058e, 0x0, // Move To FPSCR Fields XFL-form (mtfsf FLM,FRB,L,W)
                [5]*argField{ap_ImmUnsigned_7_14, ap_FPReg_16_20, ap_ImmUnsigned_6_6, ap_ImmUnsigned_15_15}},
-       {MTFSF_, 0xfc0007ff, 0xfc00058f, 0x0, // Move To FPSCR Fields XFL-form (mtfsf. FLM,FRB,L,W)
+       {MTFSFCC, 0xfc0007ff, 0xfc00058f, 0x0, // Move To FPSCR Fields XFL-form (mtfsf. FLM,FRB,L,W)
                [5]*argField{ap_ImmUnsigned_7_14, ap_FPReg_16_20, ap_ImmUnsigned_6_6, ap_ImmUnsigned_15_15}},
        {MTFSB0, 0xfc0007ff, 0xfc00008c, 0x1ff800, // Move To FPSCR Bit 0 X-form (mtfsb0 BT)
                [5]*argField{ap_CondRegBit_6_10}},
-       {MTFSB0_, 0xfc0007ff, 0xfc00008d, 0x1ff800, // Move To FPSCR Bit 0 X-form (mtfsb0. BT)
+       {MTFSB0CC, 0xfc0007ff, 0xfc00008d, 0x1ff800, // Move To FPSCR Bit 0 X-form (mtfsb0. BT)
                [5]*argField{ap_CondRegBit_6_10}},
        {MTFSB1, 0xfc0007ff, 0xfc00004c, 0x1ff800, // Move To FPSCR Bit 1 X-form (mtfsb1 BT)
                [5]*argField{ap_CondRegBit_6_10}},
-       {MTFSB1_, 0xfc0007ff, 0xfc00004d, 0x1ff800, // Move To FPSCR Bit 1 X-form (mtfsb1. BT)
+       {MTFSB1CC, 0xfc0007ff, 0xfc00004d, 0x1ff800, // Move To FPSCR Bit 1 X-form (mtfsb1. BT)
                [5]*argField{ap_CondRegBit_6_10}},
        {LVEBX, 0xfc0007fe, 0x7c00000e, 0x1, // Load Vector Element Byte Indexed X-form (lvebx VRT,RA,RB)
                [5]*argField{ap_VecReg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
@@ -3826,51 +3857,51 @@ var instFormats = [...]instFormat{
                [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
        {VCMPEQUB, 0xfc0007ff, 0x10000006, 0x0, // Vector Compare Equal To Unsigned Byte VC-form (vcmpequb VRT,VRA,VRB)
                [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
-       {VCMPEQUB_, 0xfc0007ff, 0x10000406, 0x0, // Vector Compare Equal To Unsigned Byte VC-form (vcmpequb. VRT,VRA,VRB)
+       {VCMPEQUBCC, 0xfc0007ff, 0x10000406, 0x0, // Vector Compare Equal To Unsigned Byte VC-form (vcmpequb. VRT,VRA,VRB)
                [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
        {VCMPEQUH, 0xfc0007ff, 0x10000046, 0x0, // Vector Compare Equal To Unsigned Halfword VC-form (vcmpequh VRT,VRA,VRB)
                [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
-       {VCMPEQUH_, 0xfc0007ff, 0x10000446, 0x0, // Vector Compare Equal To Unsigned Halfword VC-form (vcmpequh. VRT,VRA,VRB)
+       {VCMPEQUHCC, 0xfc0007ff, 0x10000446, 0x0, // Vector Compare Equal To Unsigned Halfword VC-form (vcmpequh. VRT,VRA,VRB)
                [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
        {VCMPEQUW, 0xfc0007ff, 0x10000086, 0x0, // Vector Compare Equal To Unsigned Word VC-form (vcmpequw VRT,VRA,VRB)
                [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
-       {VCMPEQUW_, 0xfc0007ff, 0x10000486, 0x0, // Vector Compare Equal To Unsigned Word VC-form (vcmpequw. VRT,VRA,VRB)
+       {VCMPEQUWCC, 0xfc0007ff, 0x10000486, 0x0, // Vector Compare Equal To Unsigned Word VC-form (vcmpequw. VRT,VRA,VRB)
                [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
        {VCMPEQUD, 0xfc0007ff, 0x100000c7, 0x0, // Vector Compare Equal To Unsigned Doubleword VX-form (vcmpequd VRT,VRA,VRB)
                [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
-       {VCMPEQUD_, 0xfc0007ff, 0x100004c7, 0x0, // Vector Compare Equal To Unsigned Doubleword VX-form (vcmpequd. VRT,VRA,VRB)
+       {VCMPEQUDCC, 0xfc0007ff, 0x100004c7, 0x0, // Vector Compare Equal To Unsigned Doubleword VX-form (vcmpequd. VRT,VRA,VRB)
                [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
        {VCMPGTSB, 0xfc0007ff, 0x10000306, 0x0, // Vector Compare Greater Than Signed Byte VC-form (vcmpgtsb VRT,VRA,VRB)
                [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
-       {VCMPGTSB_, 0xfc0007ff, 0x10000706, 0x0, // Vector Compare Greater Than Signed Byte VC-form (vcmpgtsb. VRT,VRA,VRB)
+       {VCMPGTSBCC, 0xfc0007ff, 0x10000706, 0x0, // Vector Compare Greater Than Signed Byte VC-form (vcmpgtsb. VRT,VRA,VRB)
                [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
        {VCMPGTSD, 0xfc0007ff, 0x100003c7, 0x0, // Vector Compare Greater Than Signed Doubleword VX-form (vcmpgtsd VRT,VRA,VRB)
                [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
-       {VCMPGTSD_, 0xfc0007ff, 0x100007c7, 0x0, // Vector Compare Greater Than Signed Doubleword VX-form (vcmpgtsd. VRT,VRA,VRB)
+       {VCMPGTSDCC, 0xfc0007ff, 0x100007c7, 0x0, // Vector Compare Greater Than Signed Doubleword VX-form (vcmpgtsd. VRT,VRA,VRB)
                [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
        {VCMPGTSH, 0xfc0007ff, 0x10000346, 0x0, // Vector Compare Greater Than Signed Halfword VC-form (vcmpgtsh VRT,VRA,VRB)
                [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
-       {VCMPGTSH_, 0xfc0007ff, 0x10000746, 0x0, // Vector Compare Greater Than Signed Halfword VC-form (vcmpgtsh. VRT,VRA,VRB)
+       {VCMPGTSHCC, 0xfc0007ff, 0x10000746, 0x0, // Vector Compare Greater Than Signed Halfword VC-form (vcmpgtsh. VRT,VRA,VRB)
                [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
        {VCMPGTSW, 0xfc0007ff, 0x10000386, 0x0, // Vector Compare Greater Than Signed Word VC-form (vcmpgtsw VRT,VRA,VRB)
                [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
-       {VCMPGTSW_, 0xfc0007ff, 0x10000786, 0x0, // Vector Compare Greater Than Signed Word VC-form (vcmpgtsw. VRT,VRA,VRB)
+       {VCMPGTSWCC, 0xfc0007ff, 0x10000786, 0x0, // Vector Compare Greater Than Signed Word VC-form (vcmpgtsw. VRT,VRA,VRB)
                [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
        {VCMPGTUB, 0xfc0007ff, 0x10000206, 0x0, // Vector Compare Greater Than Unsigned Byte VC-form (vcmpgtub VRT,VRA,VRB)
                [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
-       {VCMPGTUB_, 0xfc0007ff, 0x10000606, 0x0, // Vector Compare Greater Than Unsigned Byte VC-form (vcmpgtub. VRT,VRA,VRB)
+       {VCMPGTUBCC, 0xfc0007ff, 0x10000606, 0x0, // Vector Compare Greater Than Unsigned Byte VC-form (vcmpgtub. VRT,VRA,VRB)
                [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
        {VCMPGTUD, 0xfc0007ff, 0x100002c7, 0x0, // Vector Compare Greater Than Unsigned Doubleword VX-form (vcmpgtud VRT,VRA,VRB)
                [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
-       {VCMPGTUD_, 0xfc0007ff, 0x100006c7, 0x0, // Vector Compare Greater Than Unsigned Doubleword VX-form (vcmpgtud. VRT,VRA,VRB)
+       {VCMPGTUDCC, 0xfc0007ff, 0x100006c7, 0x0, // Vector Compare Greater Than Unsigned Doubleword VX-form (vcmpgtud. VRT,VRA,VRB)
                [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
        {VCMPGTUH, 0xfc0007ff, 0x10000246, 0x0, // Vector Compare Greater Than Unsigned Halfword VC-form (vcmpgtuh VRT,VRA,VRB)
                [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
-       {VCMPGTUH_, 0xfc0007ff, 0x10000646, 0x0, // Vector Compare Greater Than Unsigned Halfword VC-form (vcmpgtuh. VRT,VRA,VRB)
+       {VCMPGTUHCC, 0xfc0007ff, 0x10000646, 0x0, // Vector Compare Greater Than Unsigned Halfword VC-form (vcmpgtuh. VRT,VRA,VRB)
                [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
        {VCMPGTUW, 0xfc0007ff, 0x10000286, 0x0, // Vector Compare Greater Than Unsigned Word VC-form (vcmpgtuw VRT,VRA,VRB)
                [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
-       {VCMPGTUW_, 0xfc0007ff, 0x10000686, 0x0, // Vector Compare Greater Than Unsigned Word VC-form (vcmpgtuw. VRT,VRA,VRB)
+       {VCMPGTUWCC, 0xfc0007ff, 0x10000686, 0x0, // Vector Compare Greater Than Unsigned Word VC-form (vcmpgtuw. VRT,VRA,VRB)
                [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
        {VAND, 0xfc0007ff, 0x10000404, 0x0, // Vector Logical AND VX-form (vand VRT,VRA,VRB)
                [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
@@ -3950,19 +3981,19 @@ var instFormats = [...]instFormat{
                [5]*argField{ap_VecReg_6_10, ap_VecReg_16_20}},
        {VCMPBFP, 0xfc0007ff, 0x100003c6, 0x0, // Vector Compare Bounds Single-Precision VC-form (vcmpbfp VRT,VRA,VRB)
                [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
-       {VCMPBFP_, 0xfc0007ff, 0x100007c6, 0x0, // Vector Compare Bounds Single-Precision VC-form (vcmpbfp. VRT,VRA,VRB)
+       {VCMPBFPCC, 0xfc0007ff, 0x100007c6, 0x0, // Vector Compare Bounds Single-Precision VC-form (vcmpbfp. VRT,VRA,VRB)
                [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
        {VCMPEQFP, 0xfc0007ff, 0x100000c6, 0x0, // Vector Compare Equal To Single-Precision VC-form (vcmpeqfp VRT,VRA,VRB)
                [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
-       {VCMPEQFP_, 0xfc0007ff, 0x100004c6, 0x0, // Vector Compare Equal To Single-Precision VC-form (vcmpeqfp. VRT,VRA,VRB)
+       {VCMPEQFPCC, 0xfc0007ff, 0x100004c6, 0x0, // Vector Compare Equal To Single-Precision VC-form (vcmpeqfp. VRT,VRA,VRB)
                [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
        {VCMPGEFP, 0xfc0007ff, 0x100001c6, 0x0, // Vector Compare Greater Than or Equal To Single-Precision VC-form (vcmpgefp VRT,VRA,VRB)
                [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
-       {VCMPGEFP_, 0xfc0007ff, 0x100005c6, 0x0, // Vector Compare Greater Than or Equal To Single-Precision VC-form (vcmpgefp. VRT,VRA,VRB)
+       {VCMPGEFPCC, 0xfc0007ff, 0x100005c6, 0x0, // Vector Compare Greater Than or Equal To Single-Precision VC-form (vcmpgefp. VRT,VRA,VRB)
                [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
        {VCMPGTFP, 0xfc0007ff, 0x100002c6, 0x0, // Vector Compare Greater Than Single-Precision VC-form (vcmpgtfp VRT,VRA,VRB)
                [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
-       {VCMPGTFP_, 0xfc0007ff, 0x100006c6, 0x0, // Vector Compare Greater Than Single-Precision VC-form (vcmpgtfp. VRT,VRA,VRB)
+       {VCMPGTFPCC, 0xfc0007ff, 0x100006c6, 0x0, // Vector Compare Greater Than Single-Precision VC-form (vcmpgtfp. VRT,VRA,VRB)
                [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
        {VEXPTEFP, 0xfc0007ff, 0x1000018a, 0x1f0000, // Vector 2 Raised to the Exponent Estimate Floating-Point VX-form (vexptefp VRT,VRB)
                [5]*argField{ap_VecReg_6_10, ap_VecReg_16_20}},
@@ -4016,9 +4047,9 @@ var instFormats = [...]instFormat{
                [5]*argField{ap_VecReg_6_10, ap_VecReg_16_20}},
        {VBPERMQ, 0xfc0007ff, 0x1000054c, 0x0, // Vector Bit Permute Quadword VX-form (vbpermq VRT,VRA,VRB)
                [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
-       {BCDADD_, 0xfc0005ff, 0x10000401, 0x0, // Decimal Add Modulo VX-form (bcdadd. VRT,VRA,VRB,PS)
+       {BCDADDCC, 0xfc0005ff, 0x10000401, 0x0, // Decimal Add Modulo VX-form (bcdadd. VRT,VRA,VRB,PS)
                [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20, ap_ImmUnsigned_22_22}},
-       {BCDSUB_, 0xfc0005ff, 0x10000441, 0x0, // Decimal Subtract Modulo VX-form (bcdsub. VRT,VRA,VRB,PS)
+       {BCDSUBCC, 0xfc0005ff, 0x10000441, 0x0, // Decimal Subtract Modulo VX-form (bcdsub. VRT,VRA,VRB,PS)
                [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20, ap_ImmUnsigned_22_22}},
        {MTVSCR, 0xfc0007ff, 0x10000644, 0x3ff0000, // Move To Vector Status and Control Register VX-form (mtvscr VRB)
                [5]*argField{ap_VecReg_16_20}},
@@ -4026,19 +4057,19 @@ var instFormats = [...]instFormat{
                [5]*argField{ap_VecReg_6_10}},
        {DADD, 0xfc0007ff, 0xec000004, 0x0, // DFP Add [Quad] X-form (dadd FRT,FRA,FRB)
                [5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_16_20}},
-       {DADD_, 0xfc0007ff, 0xec000005, 0x0, // DFP Add [Quad] X-form (dadd. FRT,FRA,FRB)
+       {DADDCC, 0xfc0007ff, 0xec000005, 0x0, // DFP Add [Quad] X-form (dadd. FRT,FRA,FRB)
                [5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_16_20}},
        {DSUB, 0xfc0007ff, 0xec000404, 0x0, // DFP Subtract [Quad] X-form (dsub FRT,FRA,FRB)
                [5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_16_20}},
-       {DSUB_, 0xfc0007ff, 0xec000405, 0x0, // DFP Subtract [Quad] X-form (dsub. FRT,FRA,FRB)
+       {DSUBCC, 0xfc0007ff, 0xec000405, 0x0, // DFP Subtract [Quad] X-form (dsub. FRT,FRA,FRB)
                [5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_16_20}},
        {DMUL, 0xfc0007ff, 0xec000044, 0x0, // DFP Multiply [Quad] X-form (dmul FRT,FRA,FRB)
                [5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_16_20}},
-       {DMUL_, 0xfc0007ff, 0xec000045, 0x0, // DFP Multiply [Quad] X-form (dmul. FRT,FRA,FRB)
+       {DMULCC, 0xfc0007ff, 0xec000045, 0x0, // DFP Multiply [Quad] X-form (dmul. FRT,FRA,FRB)
                [5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_16_20}},
        {DDIV, 0xfc0007ff, 0xec000444, 0x0, // DFP Divide [Quad] X-form (ddiv FRT,FRA,FRB)
                [5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_16_20}},
-       {DDIV_, 0xfc0007ff, 0xec000445, 0x0, // DFP Divide [Quad] X-form (ddiv. FRT,FRA,FRB)
+       {DDIVCC, 0xfc0007ff, 0xec000445, 0x0, // DFP Divide [Quad] X-form (ddiv. FRT,FRA,FRB)
                [5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_16_20}},
        {DCMPU, 0xfc0007fe, 0xec000504, 0x600001, // DFP Compare Unordered [Quad] X-form (dcmpu BF,FRA,FRB)
                [5]*argField{ap_CondRegField_6_8, ap_FPReg_11_15, ap_FPReg_16_20}},
@@ -4054,75 +4085,75 @@ var instFormats = [...]instFormat{
                [5]*argField{ap_CondRegField_6_8, ap_FPReg_11_15, ap_FPReg_16_20}},
        {DQUAI, 0xfc0001ff, 0xec000086, 0x0, // DFP Quantize Immediate [Quad] Z23-form (dquai TE,FRT,FRB,RMC)
                [5]*argField{ap_ImmSigned_11_15, ap_FPReg_6_10, ap_FPReg_16_20, ap_ImmUnsigned_21_22}},
-       {DQUAI_, 0xfc0001ff, 0xec000087, 0x0, // DFP Quantize Immediate [Quad] Z23-form (dquai. TE,FRT,FRB,RMC)
+       {DQUAICC, 0xfc0001ff, 0xec000087, 0x0, // DFP Quantize Immediate [Quad] Z23-form (dquai. TE,FRT,FRB,RMC)
                [5]*argField{ap_ImmSigned_11_15, ap_FPReg_6_10, ap_FPReg_16_20, ap_ImmUnsigned_21_22}},
        {DQUA, 0xfc0001ff, 0xec000006, 0x0, // DFP Quantize [Quad] Z23-form (dqua FRT,FRA,FRB,RMC)
                [5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_16_20, ap_ImmUnsigned_21_22}},
-       {DQUA_, 0xfc0001ff, 0xec000007, 0x0, // DFP Quantize [Quad] Z23-form (dqua. FRT,FRA,FRB,RMC)
+       {DQUACC, 0xfc0001ff, 0xec000007, 0x0, // DFP Quantize [Quad] Z23-form (dqua. FRT,FRA,FRB,RMC)
                [5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_16_20, ap_ImmUnsigned_21_22}},
        {DRRND, 0xfc0001ff, 0xec000046, 0x0, // DFP Reround [Quad] Z23-form (drrnd FRT,FRA,FRB,RMC)
                [5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_16_20, ap_ImmUnsigned_21_22}},
-       {DRRND_, 0xfc0001ff, 0xec000047, 0x0, // DFP Reround [Quad] Z23-form (drrnd. FRT,FRA,FRB,RMC)
+       {DRRNDCC, 0xfc0001ff, 0xec000047, 0x0, // DFP Reround [Quad] Z23-form (drrnd. FRT,FRA,FRB,RMC)
                [5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_16_20, ap_ImmUnsigned_21_22}},
        {DRINTX, 0xfc0001ff, 0xec0000c6, 0x1e0000, // DFP Round To FP Integer With Inexact [Quad] Z23-form (drintx R,FRT,FRB,RMC)
                [5]*argField{ap_ImmUnsigned_15_15, ap_FPReg_6_10, ap_FPReg_16_20, ap_ImmUnsigned_21_22}},
-       {DRINTX_, 0xfc0001ff, 0xec0000c7, 0x1e0000, // DFP Round To FP Integer With Inexact [Quad] Z23-form (drintx. R,FRT,FRB,RMC)
+       {DRINTXCC, 0xfc0001ff, 0xec0000c7, 0x1e0000, // DFP Round To FP Integer With Inexact [Quad] Z23-form (drintx. R,FRT,FRB,RMC)
                [5]*argField{ap_ImmUnsigned_15_15, ap_FPReg_6_10, ap_FPReg_16_20, ap_ImmUnsigned_21_22}},
        {DRINTN, 0xfc0001ff, 0xec0001c6, 0x1e0000, // DFP Round To FP Integer Without Inexact [Quad] Z23-form (drintn R,FRT,FRB,RMC)
                [5]*argField{ap_ImmUnsigned_15_15, ap_FPReg_6_10, ap_FPReg_16_20, ap_ImmUnsigned_21_22}},
-       {DRINTN_, 0xfc0001ff, 0xec0001c7, 0x1e0000, // DFP Round To FP Integer Without Inexact [Quad] Z23-form (drintn. R,FRT,FRB,RMC)
+       {DRINTNCC, 0xfc0001ff, 0xec0001c7, 0x1e0000, // DFP Round To FP Integer Without Inexact [Quad] Z23-form (drintn. R,FRT,FRB,RMC)
                [5]*argField{ap_ImmUnsigned_15_15, ap_FPReg_6_10, ap_FPReg_16_20, ap_ImmUnsigned_21_22}},
        {DCTDP, 0xfc0007ff, 0xec000204, 0x1f0000, // DFP Convert To DFP Long X-form (dctdp FRT,FRB)
                [5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
-       {DCTDP_, 0xfc0007ff, 0xec000205, 0x1f0000, // DFP Convert To DFP Long X-form (dctdp. FRT,FRB)
+       {DCTDPCC, 0xfc0007ff, 0xec000205, 0x1f0000, // DFP Convert To DFP Long X-form (dctdp. FRT,FRB)
                [5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
        {DCTQPQ, 0xfc0007ff, 0xfc000204, 0x1f0000, // DFP Convert To DFP Extended X-form (dctqpq FRTp,FRB)
                [5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
-       {DCTQPQ_, 0xfc0007ff, 0xfc000205, 0x1f0000, // DFP Convert To DFP Extended X-form (dctqpq. FRTp,FRB)
+       {DCTQPQCC, 0xfc0007ff, 0xfc000205, 0x1f0000, // DFP Convert To DFP Extended X-form (dctqpq. FRTp,FRB)
                [5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
        {DRSP, 0xfc0007ff, 0xec000604, 0x1f0000, // DFP Round To DFP Short X-form (drsp FRT,FRB)
                [5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
-       {DRSP_, 0xfc0007ff, 0xec000605, 0x1f0000, // DFP Round To DFP Short X-form (drsp. FRT,FRB)
+       {DRSPCC, 0xfc0007ff, 0xec000605, 0x1f0000, // DFP Round To DFP Short X-form (drsp. FRT,FRB)
                [5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
        {DRDPQ, 0xfc0007ff, 0xfc000604, 0x1f0000, // DFP Round To DFP Long X-form (drdpq FRTp,FRBp)
                [5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
-       {DRDPQ_, 0xfc0007ff, 0xfc000605, 0x1f0000, // DFP Round To DFP Long X-form (drdpq. FRTp,FRBp)
+       {DRDPQCC, 0xfc0007ff, 0xfc000605, 0x1f0000, // DFP Round To DFP Long X-form (drdpq. FRTp,FRBp)
                [5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
        {DCFFIX, 0xfc0007ff, 0xec000644, 0x1f0000, // DFP Convert From Fixed X-form (dcffix FRT,FRB)
                [5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
-       {DCFFIX_, 0xfc0007ff, 0xec000645, 0x1f0000, // DFP Convert From Fixed X-form (dcffix. FRT,FRB)
+       {DCFFIXCC, 0xfc0007ff, 0xec000645, 0x1f0000, // DFP Convert From Fixed X-form (dcffix. FRT,FRB)
                [5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
        {DCFFIXQ, 0xfc0007ff, 0xfc000644, 0x1f0000, // DFP Convert From Fixed Quad X-form (dcffixq FRTp,FRB)
                [5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
-       {DCFFIXQ_, 0xfc0007ff, 0xfc000645, 0x1f0000, // DFP Convert From Fixed Quad X-form (dcffixq. FRTp,FRB)
+       {DCFFIXQCC, 0xfc0007ff, 0xfc000645, 0x1f0000, // DFP Convert From Fixed Quad X-form (dcffixq. FRTp,FRB)
                [5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
        {DCTFIX, 0xfc0007ff, 0xec000244, 0x1f0000, // DFP Convert To Fixed [Quad] X-form (dctfix FRT,FRB)
                [5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
-       {DCTFIX_, 0xfc0007ff, 0xec000245, 0x1f0000, // DFP Convert To Fixed [Quad] X-form (dctfix. FRT,FRB)
+       {DCTFIXCC, 0xfc0007ff, 0xec000245, 0x1f0000, // DFP Convert To Fixed [Quad] X-form (dctfix. FRT,FRB)
                [5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
        {DDEDPD, 0xfc0007ff, 0xec000284, 0x70000, // DFP Decode DPD To BCD [Quad] X-form (ddedpd SP,FRT,FRB)
                [5]*argField{ap_ImmUnsigned_11_12, ap_FPReg_6_10, ap_FPReg_16_20}},
-       {DDEDPD_, 0xfc0007ff, 0xec000285, 0x70000, // DFP Decode DPD To BCD [Quad] X-form (ddedpd. SP,FRT,FRB)
+       {DDEDPDCC, 0xfc0007ff, 0xec000285, 0x70000, // DFP Decode DPD To BCD [Quad] X-form (ddedpd. SP,FRT,FRB)
                [5]*argField{ap_ImmUnsigned_11_12, ap_FPReg_6_10, ap_FPReg_16_20}},
        {DENBCD, 0xfc0007ff, 0xec000684, 0xf0000, // DFP Encode BCD To DPD [Quad] X-form (denbcd S,FRT,FRB)
                [5]*argField{ap_ImmUnsigned_11_11, ap_FPReg_6_10, ap_FPReg_16_20}},
-       {DENBCD_, 0xfc0007ff, 0xec000685, 0xf0000, // DFP Encode BCD To DPD [Quad] X-form (denbcd. S,FRT,FRB)
+       {DENBCDCC, 0xfc0007ff, 0xec000685, 0xf0000, // DFP Encode BCD To DPD [Quad] X-form (denbcd. S,FRT,FRB)
                [5]*argField{ap_ImmUnsigned_11_11, ap_FPReg_6_10, ap_FPReg_16_20}},
        {DXEX, 0xfc0007ff, 0xec0002c4, 0x1f0000, // DFP Extract Biased Exponent [Quad] X-form (dxex FRT,FRB)
                [5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
-       {DXEX_, 0xfc0007ff, 0xec0002c5, 0x1f0000, // DFP Extract Biased Exponent [Quad] X-form (dxex. FRT,FRB)
+       {DXEXCC, 0xfc0007ff, 0xec0002c5, 0x1f0000, // DFP Extract Biased Exponent [Quad] X-form (dxex. FRT,FRB)
                [5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
        {DIEX, 0xfc0007ff, 0xec0006c4, 0x0, // DFP Insert Biased Exponent [Quad] X-form (diex FRT,FRA,FRB)
                [5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_16_20}},
-       {DIEX_, 0xfc0007ff, 0xec0006c5, 0x0, // DFP Insert Biased Exponent [Quad] X-form (diex. FRT,FRA,FRB)
+       {DIEXCC, 0xfc0007ff, 0xec0006c5, 0x0, // DFP Insert Biased Exponent [Quad] X-form (diex. FRT,FRA,FRB)
                [5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_16_20}},
        {DSCLI, 0xfc0003ff, 0xec000084, 0x0, // DFP Shift Significand Left Immediate [Quad] Z22-form (dscli FRT,FRA,SH)
                [5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_ImmUnsigned_16_21}},
-       {DSCLI_, 0xfc0003ff, 0xec000085, 0x0, // DFP Shift Significand Left Immediate [Quad] Z22-form (dscli. FRT,FRA,SH)
+       {DSCLICC, 0xfc0003ff, 0xec000085, 0x0, // DFP Shift Significand Left Immediate [Quad] Z22-form (dscli. FRT,FRA,SH)
                [5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_ImmUnsigned_16_21}},
        {DSCRI, 0xfc0003ff, 0xec0000c4, 0x0, // DFP Shift Significand Right Immediate [Quad] Z22-form (dscri FRT,FRA,SH)
                [5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_ImmUnsigned_16_21}},
-       {DSCRI_, 0xfc0003ff, 0xec0000c5, 0x0, // DFP Shift Significand Right Immediate [Quad] Z22-form (dscri. FRT,FRA,SH)
+       {DSCRICC, 0xfc0003ff, 0xec0000c5, 0x0, // DFP Shift Significand Right Immediate [Quad] Z22-form (dscri. FRT,FRA,SH)
                [5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_ImmUnsigned_16_21}},
        {LXSDX, 0xfc0007fe, 0x7c000498, 0x0, // Load VSX Scalar Doubleword Indexed XX1-form (lxsdx XT,RA,RB)
                [5]*argField{ap_VecSReg_31_31_6_10, ap_Reg_11_15, ap_Reg_16_20}},
@@ -4258,27 +4289,27 @@ var instFormats = [...]instFormat{
                [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}},
        {XVCMPEQDP, 0xfc0007f8, 0xf0000318, 0x0, // VSX Vector Compare Equal To Double-Precision [ & Record ] XX3-form (xvcmpeqdp XT,XA,XB)
                [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}},
-       {XVCMPEQDP_, 0xfc0007f8, 0xf0000718, 0x0, // VSX Vector Compare Equal To Double-Precision [ & Record ] XX3-form (xvcmpeqdp. XT,XA,XB)
+       {XVCMPEQDPCC, 0xfc0007f8, 0xf0000718, 0x0, // VSX Vector Compare Equal To Double-Precision [ & Record ] XX3-form (xvcmpeqdp. XT,XA,XB)
                [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}},
        {XVCMPEQSP, 0xfc0007f8, 0xf0000218, 0x0, // VSX Vector Compare Equal To Single-Precision [ & Record ] XX3-form (xvcmpeqsp XT,XA,XB)
                [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}},
-       {XVCMPEQSP_, 0xfc0007f8, 0xf0000618, 0x0, // VSX Vector Compare Equal To Single-Precision [ & Record ] XX3-form (xvcmpeqsp. XT,XA,XB)
+       {XVCMPEQSPCC, 0xfc0007f8, 0xf0000618, 0x0, // VSX Vector Compare Equal To Single-Precision [ & Record ] XX3-form (xvcmpeqsp. XT,XA,XB)
                [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}},
        {XVCMPGEDP, 0xfc0007f8, 0xf0000398, 0x0, // VSX Vector Compare Greater Than or Equal To Double-Precision [ & Record ] XX3-form (xvcmpgedp XT,XA,XB)
                [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}},
-       {XVCMPGEDP_, 0xfc0007f8, 0xf0000798, 0x0, // VSX Vector Compare Greater Than or Equal To Double-Precision [ & Record ] XX3-form (xvcmpgedp. XT,XA,XB)
+       {XVCMPGEDPCC, 0xfc0007f8, 0xf0000798, 0x0, // VSX Vector Compare Greater Than or Equal To Double-Precision [ & Record ] XX3-form (xvcmpgedp. XT,XA,XB)
                [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}},
        {XVCMPGESP, 0xfc0007f8, 0xf0000298, 0x0, // VSX Vector Compare Greater Than or Equal To Single-Precision [ & record CR6 ] XX3-form (xvcmpgesp XT,XA,XB)
                [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}},
-       {XVCMPGESP_, 0xfc0007f8, 0xf0000698, 0x0, // VSX Vector Compare Greater Than or Equal To Single-Precision [ & record CR6 ] XX3-form (xvcmpgesp. XT,XA,XB)
+       {XVCMPGESPCC, 0xfc0007f8, 0xf0000698, 0x0, // VSX Vector Compare Greater Than or Equal To Single-Precision [ & record CR6 ] XX3-form (xvcmpgesp. XT,XA,XB)
                [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}},
        {XVCMPGTDP, 0xfc0007f8, 0xf0000358, 0x0, // VSX Vector Compare Greater Than Double-Precision [ & record CR6 ] XX3-form (xvcmpgtdp XT,XA,XB)
                [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}},
-       {XVCMPGTDP_, 0xfc0007f8, 0xf0000758, 0x0, // VSX Vector Compare Greater Than Double-Precision [ & record CR6 ] XX3-form (xvcmpgtdp. XT,XA,XB)
+       {XVCMPGTDPCC, 0xfc0007f8, 0xf0000758, 0x0, // VSX Vector Compare Greater Than Double-Precision [ & record CR6 ] XX3-form (xvcmpgtdp. XT,XA,XB)
                [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}},
        {XVCMPGTSP, 0xfc0007f8, 0xf0000258, 0x0, // VSX Vector Compare Greater Than Single-Precision [ & record CR6 ] XX3-form (xvcmpgtsp XT,XA,XB)
                [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}},
-       {XVCMPGTSP_, 0xfc0007f8, 0xf0000658, 0x0, // VSX Vector Compare Greater Than Single-Precision [ & record CR6 ] XX3-form (xvcmpgtsp. XT,XA,XB)
+       {XVCMPGTSPCC, 0xfc0007f8, 0xf0000658, 0x0, // VSX Vector Compare Greater Than Single-Precision [ & record CR6 ] XX3-form (xvcmpgtsp. XT,XA,XB)
                [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}},
        {XVCPSGNDP, 0xfc0007f8, 0xf0000780, 0x0, // VSX Vector Copy Sign Double-Precision XX3-form (xvcpsgndp XT,XA,XB)
                [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}},
@@ -4930,175 +4961,175 @@ var instFormats = [...]instFormat{
                [5]*argField{ap_Reg_6_10, ap_Reg_16_20}},
        {DLMZB, 0xfc0007ff, 0x7c00009c, 0x0, // Determine Leftmost Zero Byte X-form (dlmzb RA,RS,RB)
                [5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20}},
-       {DLMZB_, 0xfc0007ff, 0x7c00009d, 0x0, // Determine Leftmost Zero Byte X-form (dlmzb. RA,RS,RB)
+       {DLMZBCC, 0xfc0007ff, 0x7c00009d, 0x0, // Determine Leftmost Zero Byte X-form (dlmzb. RA,RS,RB)
                [5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20}},
        {MACCHW, 0xfc0007ff, 0x10000158, 0x0, // Multiply Accumulate Cross Halfword to Word Modulo Signed XO-form (macchw RT,RA,RB)
                [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {MACCHW_, 0xfc0007ff, 0x10000159, 0x0, // Multiply Accumulate Cross Halfword to Word Modulo Signed XO-form (macchw. RT,RA,RB)
+       {MACCHWCC, 0xfc0007ff, 0x10000159, 0x0, // Multiply Accumulate Cross Halfword to Word Modulo Signed XO-form (macchw. RT,RA,RB)
                [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
        {MACCHWO, 0xfc0007ff, 0x10000558, 0x0, // Multiply Accumulate Cross Halfword to Word Modulo Signed XO-form (macchwo RT,RA,RB)
                [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {MACCHWO_, 0xfc0007ff, 0x10000559, 0x0, // Multiply Accumulate Cross Halfword to Word Modulo Signed XO-form (macchwo. RT,RA,RB)
+       {MACCHWOCC, 0xfc0007ff, 0x10000559, 0x0, // Multiply Accumulate Cross Halfword to Word Modulo Signed XO-form (macchwo. RT,RA,RB)
                [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
        {MACCHWS, 0xfc0007ff, 0x100001d8, 0x0, // Multiply Accumulate Cross Halfword to Word Saturate Signed XO-form (macchws RT,RA,RB)
                [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {MACCHWS_, 0xfc0007ff, 0x100001d9, 0x0, // Multiply Accumulate Cross Halfword to Word Saturate Signed XO-form (macchws. RT,RA,RB)
+       {MACCHWSCC, 0xfc0007ff, 0x100001d9, 0x0, // Multiply Accumulate Cross Halfword to Word Saturate Signed XO-form (macchws. RT,RA,RB)
                [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
        {MACCHWSO, 0xfc0007ff, 0x100005d8, 0x0, // Multiply Accumulate Cross Halfword to Word Saturate Signed XO-form (macchwso RT,RA,RB)
                [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {MACCHWSO_, 0xfc0007ff, 0x100005d9, 0x0, // Multiply Accumulate Cross Halfword to Word Saturate Signed XO-form (macchwso. RT,RA,RB)
+       {MACCHWSOCC, 0xfc0007ff, 0x100005d9, 0x0, // Multiply Accumulate Cross Halfword to Word Saturate Signed XO-form (macchwso. RT,RA,RB)
                [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
        {MACCHWU, 0xfc0007ff, 0x10000118, 0x0, // Multiply Accumulate Cross Halfword to Word Modulo Unsigned XO-form (macchwu RT,RA,RB)
                [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {MACCHWU_, 0xfc0007ff, 0x10000119, 0x0, // Multiply Accumulate Cross Halfword to Word Modulo Unsigned XO-form (macchwu. RT,RA,RB)
+       {MACCHWUCC, 0xfc0007ff, 0x10000119, 0x0, // Multiply Accumulate Cross Halfword to Word Modulo Unsigned XO-form (macchwu. RT,RA,RB)
                [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
        {MACCHWUO, 0xfc0007ff, 0x10000518, 0x0, // Multiply Accumulate Cross Halfword to Word Modulo Unsigned XO-form (macchwuo RT,RA,RB)
                [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {MACCHWUO_, 0xfc0007ff, 0x10000519, 0x0, // Multiply Accumulate Cross Halfword to Word Modulo Unsigned XO-form (macchwuo. RT,RA,RB)
+       {MACCHWUOCC, 0xfc0007ff, 0x10000519, 0x0, // Multiply Accumulate Cross Halfword to Word Modulo Unsigned XO-form (macchwuo. RT,RA,RB)
                [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
        {MACCHWSU, 0xfc0007ff, 0x10000198, 0x0, // Multiply Accumulate Cross Halfword to Word Saturate Unsigned XO-form (macchwsu RT,RA,RB)
                [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {MACCHWSU_, 0xfc0007ff, 0x10000199, 0x0, // Multiply Accumulate Cross Halfword to Word Saturate Unsigned XO-form (macchwsu. RT,RA,RB)
+       {MACCHWSUCC, 0xfc0007ff, 0x10000199, 0x0, // Multiply Accumulate Cross Halfword to Word Saturate Unsigned XO-form (macchwsu. RT,RA,RB)
                [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
        {MACCHWSUO, 0xfc0007ff, 0x10000598, 0x0, // Multiply Accumulate Cross Halfword to Word Saturate Unsigned XO-form (macchwsuo RT,RA,RB)
                [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {MACCHWSUO_, 0xfc0007ff, 0x10000599, 0x0, // Multiply Accumulate Cross Halfword to Word Saturate Unsigned XO-form (macchwsuo. RT,RA,RB)
+       {MACCHWSUOCC, 0xfc0007ff, 0x10000599, 0x0, // Multiply Accumulate Cross Halfword to Word Saturate Unsigned XO-form (macchwsuo. RT,RA,RB)
                [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
        {MACHHW, 0xfc0007ff, 0x10000058, 0x0, // Multiply Accumulate High Halfword to Word Modulo Signed XO-form (machhw RT,RA,RB)
                [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {MACHHW_, 0xfc0007ff, 0x10000059, 0x0, // Multiply Accumulate High Halfword to Word Modulo Signed XO-form (machhw. RT,RA,RB)
+       {MACHHWCC, 0xfc0007ff, 0x10000059, 0x0, // Multiply Accumulate High Halfword to Word Modulo Signed XO-form (machhw. RT,RA,RB)
                [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
        {MACHHWO, 0xfc0007ff, 0x10000458, 0x0, // Multiply Accumulate High Halfword to Word Modulo Signed XO-form (machhwo RT,RA,RB)
                [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {MACHHWO_, 0xfc0007ff, 0x10000459, 0x0, // Multiply Accumulate High Halfword to Word Modulo Signed XO-form (machhwo. RT,RA,RB)
+       {MACHHWOCC, 0xfc0007ff, 0x10000459, 0x0, // Multiply Accumulate High Halfword to Word Modulo Signed XO-form (machhwo. RT,RA,RB)
                [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
        {MACHHWS, 0xfc0007ff, 0x100000d8, 0x0, // Multiply Accumulate High Halfword to Word Saturate Signed XO-form (machhws RT,RA,RB)
                [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {MACHHWS_, 0xfc0007ff, 0x100000d9, 0x0, // Multiply Accumulate High Halfword to Word Saturate Signed XO-form (machhws. RT,RA,RB)
+       {MACHHWSCC, 0xfc0007ff, 0x100000d9, 0x0, // Multiply Accumulate High Halfword to Word Saturate Signed XO-form (machhws. RT,RA,RB)
                [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
        {MACHHWSO, 0xfc0007ff, 0x100004d8, 0x0, // Multiply Accumulate High Halfword to Word Saturate Signed XO-form (machhwso RT,RA,RB)
                [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {MACHHWSO_, 0xfc0007ff, 0x100004d9, 0x0, // Multiply Accumulate High Halfword to Word Saturate Signed XO-form (machhwso. RT,RA,RB)
+       {MACHHWSOCC, 0xfc0007ff, 0x100004d9, 0x0, // Multiply Accumulate High Halfword to Word Saturate Signed XO-form (machhwso. RT,RA,RB)
                [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
        {MACHHWU, 0xfc0007ff, 0x10000018, 0x0, // Multiply Accumulate High Halfword to Word Modulo Unsigned XO-form (machhwu RT,RA,RB)
                [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {MACHHWU_, 0xfc0007ff, 0x10000019, 0x0, // Multiply Accumulate High Halfword to Word Modulo Unsigned XO-form (machhwu. RT,RA,RB)
+       {MACHHWUCC, 0xfc0007ff, 0x10000019, 0x0, // Multiply Accumulate High Halfword to Word Modulo Unsigned XO-form (machhwu. RT,RA,RB)
                [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
        {MACHHWUO, 0xfc0007ff, 0x10000418, 0x0, // Multiply Accumulate High Halfword to Word Modulo Unsigned XO-form (machhwuo RT,RA,RB)
                [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {MACHHWUO_, 0xfc0007ff, 0x10000419, 0x0, // Multiply Accumulate High Halfword to Word Modulo Unsigned XO-form (machhwuo. RT,RA,RB)
+       {MACHHWUOCC, 0xfc0007ff, 0x10000419, 0x0, // Multiply Accumulate High Halfword to Word Modulo Unsigned XO-form (machhwuo. RT,RA,RB)
                [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
        {MACHHWSU, 0xfc0007ff, 0x10000098, 0x0, // Multiply Accumulate High Halfword to Word Saturate Unsigned XO-form (machhwsu RT,RA,RB)
                [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {MACHHWSU_, 0xfc0007ff, 0x10000099, 0x0, // Multiply Accumulate High Halfword to Word Saturate Unsigned XO-form (machhwsu. RT,RA,RB)
+       {MACHHWSUCC, 0xfc0007ff, 0x10000099, 0x0, // Multiply Accumulate High Halfword to Word Saturate Unsigned XO-form (machhwsu. RT,RA,RB)
                [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
        {MACHHWSUO, 0xfc0007ff, 0x10000498, 0x0, // Multiply Accumulate High Halfword to Word Saturate Unsigned XO-form (machhwsuo RT,RA,RB)
                [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {MACHHWSUO_, 0xfc0007ff, 0x10000499, 0x0, // Multiply Accumulate High Halfword to Word Saturate Unsigned XO-form (machhwsuo. RT,RA,RB)
+       {MACHHWSUOCC, 0xfc0007ff, 0x10000499, 0x0, // Multiply Accumulate High Halfword to Word Saturate Unsigned XO-form (machhwsuo. RT,RA,RB)
                [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
        {MACLHW, 0xfc0007ff, 0x10000358, 0x0, // Multiply Accumulate Low Halfword to Word Modulo Signed XO-form (maclhw RT,RA,RB)
                [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {MACLHW_, 0xfc0007ff, 0x10000359, 0x0, // Multiply Accumulate Low Halfword to Word Modulo Signed XO-form (maclhw. RT,RA,RB)
+       {MACLHWCC, 0xfc0007ff, 0x10000359, 0x0, // Multiply Accumulate Low Halfword to Word Modulo Signed XO-form (maclhw. RT,RA,RB)
                [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
        {MACLHWO, 0xfc0007ff, 0x10000758, 0x0, // Multiply Accumulate Low Halfword to Word Modulo Signed XO-form (maclhwo RT,RA,RB)
                [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {MACLHWO_, 0xfc0007ff, 0x10000759, 0x0, // Multiply Accumulate Low Halfword to Word Modulo Signed XO-form (maclhwo. RT,RA,RB)
+       {MACLHWOCC, 0xfc0007ff, 0x10000759, 0x0, // Multiply Accumulate Low Halfword to Word Modulo Signed XO-form (maclhwo. RT,RA,RB)
                [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
        {MACLHWS, 0xfc0007ff, 0x100003d8, 0x0, // Multiply Accumulate Low Halfword to Word Saturate Signed XO-form (maclhws RT,RA,RB)
                [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {MACLHWS_, 0xfc0007ff, 0x100003d9, 0x0, // Multiply Accumulate Low Halfword to Word Saturate Signed XO-form (maclhws. RT,RA,RB)
+       {MACLHWSCC, 0xfc0007ff, 0x100003d9, 0x0, // Multiply Accumulate Low Halfword to Word Saturate Signed XO-form (maclhws. RT,RA,RB)
                [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
        {MACLHWSO, 0xfc0007ff, 0x100007d8, 0x0, // Multiply Accumulate Low Halfword to Word Saturate Signed XO-form (maclhwso RT,RA,RB)
                [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {MACLHWSO_, 0xfc0007ff, 0x100007d9, 0x0, // Multiply Accumulate Low Halfword to Word Saturate Signed XO-form (maclhwso. RT,RA,RB)
+       {MACLHWSOCC, 0xfc0007ff, 0x100007d9, 0x0, // Multiply Accumulate Low Halfword to Word Saturate Signed XO-form (maclhwso. RT,RA,RB)
                [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
        {MACLHWU, 0xfc0007ff, 0x10000318, 0x0, // Multiply Accumulate Low Halfword to Word Modulo Unsigned XO-form (maclhwu RT,RA,RB)
                [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {MACLHWU_, 0xfc0007ff, 0x10000319, 0x0, // Multiply Accumulate Low Halfword to Word Modulo Unsigned XO-form (maclhwu. RT,RA,RB)
+       {MACLHWUCC, 0xfc0007ff, 0x10000319, 0x0, // Multiply Accumulate Low Halfword to Word Modulo Unsigned XO-form (maclhwu. RT,RA,RB)
                [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
        {MACLHWUO, 0xfc0007ff, 0x10000718, 0x0, // Multiply Accumulate Low Halfword to Word Modulo Unsigned XO-form (maclhwuo RT,RA,RB)
                [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {MACLHWUO_, 0xfc0007ff, 0x10000719, 0x0, // Multiply Accumulate Low Halfword to Word Modulo Unsigned XO-form (maclhwuo. RT,RA,RB)
+       {MACLHWUOCC, 0xfc0007ff, 0x10000719, 0x0, // Multiply Accumulate Low Halfword to Word Modulo Unsigned XO-form (maclhwuo. RT,RA,RB)
                [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
        {MULCHW, 0xfc0007ff, 0x10000150, 0x0, // Multiply Cross Halfword to Word Signed X-form (mulchw RT,RA,RB)
                [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {MULCHW_, 0xfc0007ff, 0x10000151, 0x0, // Multiply Cross Halfword to Word Signed X-form (mulchw. RT,RA,RB)
+       {MULCHWCC, 0xfc0007ff, 0x10000151, 0x0, // Multiply Cross Halfword to Word Signed X-form (mulchw. RT,RA,RB)
                [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
        {MACLHWSU, 0xfc0007ff, 0x10000398, 0x0, // Multiply Accumulate Low Halfword to Word Saturate Unsigned XO-form (maclhwsu RT,RA,RB)
                [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {MACLHWSU_, 0xfc0007ff, 0x10000399, 0x0, // Multiply Accumulate Low Halfword to Word Saturate Unsigned XO-form (maclhwsu. RT,RA,RB)
+       {MACLHWSUCC, 0xfc0007ff, 0x10000399, 0x0, // Multiply Accumulate Low Halfword to Word Saturate Unsigned XO-form (maclhwsu. RT,RA,RB)
                [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
        {MACLHWSUO, 0xfc0007ff, 0x10000798, 0x0, // Multiply Accumulate Low Halfword to Word Saturate Unsigned XO-form (maclhwsuo RT,RA,RB)
                [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {MACLHWSUO_, 0xfc0007ff, 0x10000799, 0x0, // Multiply Accumulate Low Halfword to Word Saturate Unsigned XO-form (maclhwsuo. RT,RA,RB)
+       {MACLHWSUOCC, 0xfc0007ff, 0x10000799, 0x0, // Multiply Accumulate Low Halfword to Word Saturate Unsigned XO-form (maclhwsuo. RT,RA,RB)
                [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
        {MULCHWU, 0xfc0007ff, 0x10000110, 0x0, // Multiply Cross Halfword to Word Unsigned X-form (mulchwu RT,RA,RB)
                [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {MULCHWU_, 0xfc0007ff, 0x10000111, 0x0, // Multiply Cross Halfword to Word Unsigned X-form (mulchwu. RT,RA,RB)
+       {MULCHWUCC, 0xfc0007ff, 0x10000111, 0x0, // Multiply Cross Halfword to Word Unsigned X-form (mulchwu. RT,RA,RB)
                [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
        {MULHHW, 0xfc0007ff, 0x10000050, 0x0, // Multiply High Halfword to Word Signed X-form (mulhhw RT,RA,RB)
                [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {MULHHW_, 0xfc0007ff, 0x10000051, 0x0, // Multiply High Halfword to Word Signed X-form (mulhhw. RT,RA,RB)
+       {MULHHWCC, 0xfc0007ff, 0x10000051, 0x0, // Multiply High Halfword to Word Signed X-form (mulhhw. RT,RA,RB)
                [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
        {MULLHW, 0xfc0007ff, 0x10000350, 0x0, // Multiply Low Halfword to Word Signed X-form (mullhw RT,RA,RB)
                [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {MULLHW_, 0xfc0007ff, 0x10000351, 0x0, // Multiply Low Halfword to Word Signed X-form (mullhw. RT,RA,RB)
+       {MULLHWCC, 0xfc0007ff, 0x10000351, 0x0, // Multiply Low Halfword to Word Signed X-form (mullhw. RT,RA,RB)
                [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
        {MULHHWU, 0xfc0007ff, 0x10000010, 0x0, // Multiply High Halfword to Word Unsigned X-form (mulhhwu RT,RA,RB)
                [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {MULHHWU_, 0xfc0007ff, 0x10000011, 0x0, // Multiply High Halfword to Word Unsigned X-form (mulhhwu. RT,RA,RB)
+       {MULHHWUCC, 0xfc0007ff, 0x10000011, 0x0, // Multiply High Halfword to Word Unsigned X-form (mulhhwu. RT,RA,RB)
                [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
        {MULLHWU, 0xfc0007ff, 0x10000310, 0x0, // Multiply Low Halfword to Word Unsigned X-form (mullhwu RT,RA,RB)
                [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {MULLHWU_, 0xfc0007ff, 0x10000311, 0x0, // Multiply Low Halfword to Word Unsigned X-form (mullhwu. RT,RA,RB)
+       {MULLHWUCC, 0xfc0007ff, 0x10000311, 0x0, // Multiply Low Halfword to Word Unsigned X-form (mullhwu. RT,RA,RB)
                [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
        {NMACCHW, 0xfc0007ff, 0x1000015c, 0x0, // Negative Multiply Accumulate Cross Halfword to Word Modulo Signed XO-form (nmacchw RT,RA,RB)
                [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {NMACCHW_, 0xfc0007ff, 0x1000015d, 0x0, // Negative Multiply Accumulate Cross Halfword to Word Modulo Signed XO-form (nmacchw. RT,RA,RB)
+       {NMACCHWCC, 0xfc0007ff, 0x1000015d, 0x0, // Negative Multiply Accumulate Cross Halfword to Word Modulo Signed XO-form (nmacchw. RT,RA,RB)
                [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
        {NMACCHWO, 0xfc0007ff, 0x1000055c, 0x0, // Negative Multiply Accumulate Cross Halfword to Word Modulo Signed XO-form (nmacchwo RT,RA,RB)
                [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {NMACCHWO_, 0xfc0007ff, 0x1000055d, 0x0, // Negative Multiply Accumulate Cross Halfword to Word Modulo Signed XO-form (nmacchwo. RT,RA,RB)
+       {NMACCHWOCC, 0xfc0007ff, 0x1000055d, 0x0, // Negative Multiply Accumulate Cross Halfword to Word Modulo Signed XO-form (nmacchwo. RT,RA,RB)
                [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
        {NMACCHWS, 0xfc0007ff, 0x100001dc, 0x0, // Negative Multiply Accumulate Cross Halfword to Word Saturate Signed XO-form (nmacchws RT,RA,RB)
                [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {NMACCHWS_, 0xfc0007ff, 0x100001dd, 0x0, // Negative Multiply Accumulate Cross Halfword to Word Saturate Signed XO-form (nmacchws. RT,RA,RB)
+       {NMACCHWSCC, 0xfc0007ff, 0x100001dd, 0x0, // Negative Multiply Accumulate Cross Halfword to Word Saturate Signed XO-form (nmacchws. RT,RA,RB)
                [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
        {NMACCHWSO, 0xfc0007ff, 0x100005dc, 0x0, // Negative Multiply Accumulate Cross Halfword to Word Saturate Signed XO-form (nmacchwso RT,RA,RB)
                [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {NMACCHWSO_, 0xfc0007ff, 0x100005dd, 0x0, // Negative Multiply Accumulate Cross Halfword to Word Saturate Signed XO-form (nmacchwso. RT,RA,RB)
+       {NMACCHWSOCC, 0xfc0007ff, 0x100005dd, 0x0, // Negative Multiply Accumulate Cross Halfword to Word Saturate Signed XO-form (nmacchwso. RT,RA,RB)
                [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
        {NMACHHW, 0xfc0007ff, 0x1000005c, 0x0, // Negative Multiply Accumulate High Halfword to Word Modulo Signed XO-form (nmachhw RT,RA,RB)
                [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {NMACHHW_, 0xfc0007ff, 0x1000005d, 0x0, // Negative Multiply Accumulate High Halfword to Word Modulo Signed XO-form (nmachhw. RT,RA,RB)
+       {NMACHHWCC, 0xfc0007ff, 0x1000005d, 0x0, // Negative Multiply Accumulate High Halfword to Word Modulo Signed XO-form (nmachhw. RT,RA,RB)
                [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
        {NMACHHWO, 0xfc0007ff, 0x1000045c, 0x0, // Negative Multiply Accumulate High Halfword to Word Modulo Signed XO-form (nmachhwo RT,RA,RB)
                [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {NMACHHWO_, 0xfc0007ff, 0x1000045d, 0x0, // Negative Multiply Accumulate High Halfword to Word Modulo Signed XO-form (nmachhwo. RT,RA,RB)
+       {NMACHHWOCC, 0xfc0007ff, 0x1000045d, 0x0, // Negative Multiply Accumulate High Halfword to Word Modulo Signed XO-form (nmachhwo. RT,RA,RB)
                [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
        {NMACHHWS, 0xfc0007ff, 0x100000dc, 0x0, // Negative Multiply Accumulate High Halfword to Word Saturate Signed XO-form (nmachhws RT,RA,RB)
                [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {NMACHHWS_, 0xfc0007ff, 0x100000dd, 0x0, // Negative Multiply Accumulate High Halfword to Word Saturate Signed XO-form (nmachhws. RT,RA,RB)
+       {NMACHHWSCC, 0xfc0007ff, 0x100000dd, 0x0, // Negative Multiply Accumulate High Halfword to Word Saturate Signed XO-form (nmachhws. RT,RA,RB)
                [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
        {NMACHHWSO, 0xfc0007ff, 0x100004dc, 0x0, // Negative Multiply Accumulate High Halfword to Word Saturate Signed XO-form (nmachhwso RT,RA,RB)
                [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {NMACHHWSO_, 0xfc0007ff, 0x100004dd, 0x0, // Negative Multiply Accumulate High Halfword to Word Saturate Signed XO-form (nmachhwso. RT,RA,RB)
+       {NMACHHWSOCC, 0xfc0007ff, 0x100004dd, 0x0, // Negative Multiply Accumulate High Halfword to Word Saturate Signed XO-form (nmachhwso. RT,RA,RB)
                [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
        {NMACLHW, 0xfc0007ff, 0x1000035c, 0x0, // Negative Multiply Accumulate Low Halfword to Word Modulo Signed XO-form (nmaclhw RT,RA,RB)
                [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {NMACLHW_, 0xfc0007ff, 0x1000035d, 0x0, // Negative Multiply Accumulate Low Halfword to Word Modulo Signed XO-form (nmaclhw. RT,RA,RB)
+       {NMACLHWCC, 0xfc0007ff, 0x1000035d, 0x0, // Negative Multiply Accumulate Low Halfword to Word Modulo Signed XO-form (nmaclhw. RT,RA,RB)
                [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
        {NMACLHWO, 0xfc0007ff, 0x1000075c, 0x0, // Negative Multiply Accumulate Low Halfword to Word Modulo Signed XO-form (nmaclhwo RT,RA,RB)
                [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {NMACLHWO_, 0xfc0007ff, 0x1000075d, 0x0, // Negative Multiply Accumulate Low Halfword to Word Modulo Signed XO-form (nmaclhwo. RT,RA,RB)
+       {NMACLHWOCC, 0xfc0007ff, 0x1000075d, 0x0, // Negative Multiply Accumulate Low Halfword to Word Modulo Signed XO-form (nmaclhwo. RT,RA,RB)
                [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
        {NMACLHWS, 0xfc0007ff, 0x100003dc, 0x0, // Negative Multiply Accumulate Low Halfword to Word Saturate Signed XO-form (nmaclhws RT,RA,RB)
                [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {NMACLHWS_, 0xfc0007ff, 0x100003dd, 0x0, // Negative Multiply Accumulate Low Halfword to Word Saturate Signed XO-form (nmaclhws. RT,RA,RB)
+       {NMACLHWSCC, 0xfc0007ff, 0x100003dd, 0x0, // Negative Multiply Accumulate Low Halfword to Word Saturate Signed XO-form (nmaclhws. RT,RA,RB)
                [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
        {NMACLHWSO, 0xfc0007ff, 0x100007dc, 0x0, // Negative Multiply Accumulate Low Halfword to Word Saturate Signed XO-form (nmaclhwso RT,RA,RB)
                [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {NMACLHWSO_, 0xfc0007ff, 0x100007dd, 0x0, // Negative Multiply Accumulate Low Halfword to Word Saturate Signed XO-form (nmaclhwso. RT,RA,RB)
+       {NMACLHWSOCC, 0xfc0007ff, 0x100007dd, 0x0, // Negative Multiply Accumulate Low Halfword to Word Saturate Signed XO-form (nmaclhwso. RT,RA,RB)
                [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
        {ICBI, 0xfc0007fe, 0x7c0007ac, 0x3e00001, // Instruction Cache Block Invalidate X-form (icbi RA,RB)
                [5]*argField{ap_Reg_11_15, ap_Reg_16_20}},
@@ -5136,23 +5167,23 @@ var instFormats = [...]instFormat{
                [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
        {LWARX, 0xfc0007fe, 0x7c000028, 0x0, // Load Word And Reserve Indexed X-form (lwarx RT,RA,RB,EH)
                [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20, ap_ImmUnsigned_31_31}},
-       {STBCX_, 0xfc0007ff, 0x7c00056d, 0x0, // Store Byte Conditional Indexed X-form [Category: Phased-In] (stbcx. RS,RA,RB)
+       {STBCXCC, 0xfc0007ff, 0x7c00056d, 0x0, // Store Byte Conditional Indexed X-form [Category: Phased-In] (stbcx. RS,RA,RB)
                [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {STHCX_, 0xfc0007ff, 0x7c0005ad, 0x0, // Store Halfword Conditional Indexed X-form [Category: Phased-In] (sthcx. RS,RA,RB)
+       {STHCXCC, 0xfc0007ff, 0x7c0005ad, 0x0, // Store Halfword Conditional Indexed X-form [Category: Phased-In] (sthcx. RS,RA,RB)
                [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {STWCX_, 0xfc0007ff, 0x7c00012d, 0x0, // Store Word Conditional Indexed X-form (stwcx. RS,RA,RB)
+       {STWCXCC, 0xfc0007ff, 0x7c00012d, 0x0, // Store Word Conditional Indexed X-form (stwcx. RS,RA,RB)
                [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
        {LDARX, 0xfc0007ff, 0x7c0000a8, 0x0, // Load Doubleword And Reserve Indexed X-form (ldarx RT,RA,RB)
                [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
        {LDARX, 0xfc0007fe, 0x7c0000a8, 0x0, // Load Doubleword And Reserve Indexed X-form (ldarx RT,RA,RB,EH)
                [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20, ap_ImmUnsigned_31_31}},
-       {STDCX_, 0xfc0007ff, 0x7c0001ad, 0x0, // Store Doubleword Conditional Indexed X-form (stdcx. RS,RA,RB)
+       {STDCXCC, 0xfc0007ff, 0x7c0001ad, 0x0, // Store Doubleword Conditional Indexed X-form (stdcx. RS,RA,RB)
                [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
        {LQARX, 0xfc0007ff, 0x7c000228, 0x0, // Load Quadword And Reserve Indexed X-form (lqarx RTp,RA,RB)
                [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
        {LQARX, 0xfc0007fe, 0x7c000228, 0x0, // Load Quadword And Reserve Indexed X-form (lqarx RTp,RA,RB,EH)
                [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20, ap_ImmUnsigned_31_31}},
-       {STQCX_, 0xfc0007ff, 0x7c00016d, 0x0, // Store Quadword Conditional Indexed X-form (stqcx. RSp,RA,RB)
+       {STQCXCC, 0xfc0007ff, 0x7c00016d, 0x0, // Store Quadword Conditional Indexed X-form (stqcx. RSp,RA,RB)
                [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
        {SYNC, 0xfc0007fe, 0x7c0004ac, 0x390f801, // Synchronize X-form (sync L, E)
                [5]*argField{ap_ImmUnsigned_9_10, ap_ImmUnsigned_12_15}},
@@ -5162,21 +5193,21 @@ var instFormats = [...]instFormat{
                [5]*argField{ap_ImmUnsigned_6_10}},
        {WAIT, 0xfc0007fe, 0x7c00007c, 0x39ff801, // Wait X-form (wait WC)
                [5]*argField{ap_ImmUnsigned_9_10}},
-       {TBEGIN_, 0xfc0007ff, 0x7c00051d, 0x1dff800, // Transaction Begin X-form (tbegin. R)
+       {TBEGINCC, 0xfc0007ff, 0x7c00051d, 0x1dff800, // Transaction Begin X-form (tbegin. R)
                [5]*argField{ap_ImmUnsigned_10_10}},
-       {TEND_, 0xfc0007ff, 0x7c00055d, 0x1fff800, // Transaction End X-form (tend. A)
+       {TENDCC, 0xfc0007ff, 0x7c00055d, 0x1fff800, // Transaction End X-form (tend. A)
                [5]*argField{ap_ImmUnsigned_6_6}},
-       {TABORT_, 0xfc0007ff, 0x7c00071d, 0x3e0f800, // Transaction Abort X-form (tabort. RA)
+       {TABORTCC, 0xfc0007ff, 0x7c00071d, 0x3e0f800, // Transaction Abort X-form (tabort. RA)
                [5]*argField{ap_Reg_11_15}},
-       {TABORTWC_, 0xfc0007ff, 0x7c00061d, 0x0, // Transaction Abort Word Conditional X-form (tabortwc. TO,RA,RB)
+       {TABORTWCCC, 0xfc0007ff, 0x7c00061d, 0x0, // Transaction Abort Word Conditional X-form (tabortwc. TO,RA,RB)
                [5]*argField{ap_ImmUnsigned_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {TABORTWCI_, 0xfc0007ff, 0x7c00069d, 0x0, // Transaction Abort Word Conditional Immediate X-form (tabortwci. TO,RA,SI)
+       {TABORTWCICC, 0xfc0007ff, 0x7c00069d, 0x0, // Transaction Abort Word Conditional Immediate X-form (tabortwci. TO,RA,SI)
                [5]*argField{ap_ImmUnsigned_6_10, ap_Reg_11_15, ap_ImmSigned_16_20}},
-       {TABORTDC_, 0xfc0007ff, 0x7c00065d, 0x0, // Transaction Abort Doubleword Conditional X-form (tabortdc. TO,RA,RB)
+       {TABORTDCCC, 0xfc0007ff, 0x7c00065d, 0x0, // Transaction Abort Doubleword Conditional X-form (tabortdc. TO,RA,RB)
                [5]*argField{ap_ImmUnsigned_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {TABORTDCI_, 0xfc0007ff, 0x7c0006dd, 0x0, // Transaction Abort Doubleword Conditional Immediate X-form (tabortdci. TO,RA, SI)
+       {TABORTDCICC, 0xfc0007ff, 0x7c0006dd, 0x0, // Transaction Abort Doubleword Conditional Immediate X-form (tabortdci. TO,RA, SI)
                [5]*argField{ap_ImmUnsigned_6_10, ap_Reg_11_15, ap_ImmSigned_16_20}},
-       {TSR_, 0xfc0007ff, 0x7c0005dd, 0x3dff800, // Transaction Suspend or Resume X-form (tsr. L)
+       {TSRCC, 0xfc0007ff, 0x7c0005dd, 0x3dff800, // Transaction Suspend or Resume X-form (tsr. L)
                [5]*argField{ap_ImmUnsigned_10_10}},
        {TCHECK, 0xfc0007fe, 0x7c00059c, 0x7ff801, // Transaction Check X-form (tcheck BF)
                [5]*argField{ap_CondRegField_6_8}},
@@ -5240,9 +5271,9 @@ var instFormats = [...]instFormat{
                [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
        {STDCIX, 0xfc0007fe, 0x7c0007ea, 0x1, // Store Doubleword Caching Inhibited Indexed X-form (stdcix RS,RA,RB)
                [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {TRECLAIM_, 0xfc0007ff, 0x7c00075d, 0x3e0f800, // Transaction Reclaim X-form (treclaim. RA)
+       {TRECLAIMCC, 0xfc0007ff, 0x7c00075d, 0x3e0f800, // Transaction Reclaim X-form (treclaim. RA)
                [5]*argField{ap_Reg_11_15}},
-       {TRECHKPT_, 0xfc0007ff, 0x7c0007dd, 0x3fff800, // Transaction Recheckpoint X-form (trechkpt.)
+       {TRECHKPTCC, 0xfc0007ff, 0x7c0007dd, 0x3fff800, // Transaction Recheckpoint X-form (trechkpt.)
                [5]*argField{}},
        {MTSPR, 0xfc0007fe, 0x7c0003a6, 0x1, // Move To Special Purpose Register XFX-form (mtspr SPR,RS)
                [5]*argField{ap_SpReg_16_20_11_15, ap_Reg_6_10}},
@@ -5264,7 +5295,7 @@ var instFormats = [...]instFormat{
                [5]*argField{ap_Reg_6_10, ap_Reg_16_20}},
        {SLBMFEE, 0xfc0007fe, 0x7c000726, 0x1f0001, // SLB Move From Entry ESID X-form (slbmfee RT,RB)
                [5]*argField{ap_Reg_6_10, ap_Reg_16_20}},
-       {SLBFEE_, 0xfc0007ff, 0x7c0007a7, 0x1f0000, // SLB Find Entry ESID X-form (slbfee. RT,RB)
+       {SLBFEECC, 0xfc0007ff, 0x7c0007a7, 0x1f0000, // SLB Find Entry ESID X-form (slbfee. RT,RB)
                [5]*argField{ap_Reg_6_10, ap_Reg_16_20}},
        {MTSR, 0xfc0007fe, 0x7c0001a4, 0x10f801, // Move To Segment Register X-form (mtsr SR,RS)
                [5]*argField{ap_SpReg_12_15, ap_Reg_6_10}},
@@ -5372,9 +5403,9 @@ var instFormats = [...]instFormat{
                [5]*argField{ap_VecReg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
        {DCBI, 0xfc0007fe, 0x7c0003ac, 0x3e00001, // Data Cache Block Invalidate X-form (dcbi RA,RB)
                [5]*argField{ap_Reg_11_15, ap_Reg_16_20}},
-       {DCBLQ_, 0xfc0007ff, 0x7c00034d, 0x2000000, // Data Cache Block Lock Query X-form (dcblq. CT,RA,RB)
+       {DCBLQCC, 0xfc0007ff, 0x7c00034d, 0x2000000, // Data Cache Block Lock Query X-form (dcblq. CT,RA,RB)
                [5]*argField{ap_ImmUnsigned_7_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {ICBLQ_, 0xfc0007ff, 0x7c00018d, 0x2000000, // Instruction Cache Block Lock Query X-form (icblq. CT,RA,RB)
+       {ICBLQCC, 0xfc0007ff, 0x7c00018d, 0x2000000, // Instruction Cache Block Lock Query X-form (icblq. CT,RA,RB)
                [5]*argField{ap_ImmUnsigned_7_10, ap_Reg_11_15, ap_Reg_16_20}},
        {DCBTLS, 0xfc0007fe, 0x7c00014c, 0x2000001, // Data Cache Block Touch and Lock Set X-form (dcbtls CT,RA,RB)
                [5]*argField{ap_ImmUnsigned_7_10, ap_Reg_11_15, ap_Reg_16_20}},
@@ -5392,7 +5423,7 @@ var instFormats = [...]instFormat{
                [5]*argField{ap_Reg_11_15, ap_Reg_16_20}},
        {TLBSX, 0xfc0007fe, 0x7c000724, 0x3e00001, // TLB Search Indexed X-form (tlbsx RA,RB)
                [5]*argField{ap_Reg_11_15, ap_Reg_16_20}},
-       {TLBSRX_, 0xfc0007ff, 0x7c0006a5, 0x3e00000, // TLB Search and Reserve Indexed X-form (tlbsrx. RA,RB)
+       {TLBSRXCC, 0xfc0007ff, 0x7c0006a5, 0x3e00000, // TLB Search and Reserve Indexed X-form (tlbsrx. RA,RB)
                [5]*argField{ap_Reg_11_15, ap_Reg_16_20}},
        {TLBRE, 0xfc0007fe, 0x7c000764, 0x3fff801, // TLB Read Entry X-form (tlbre)
                [5]*argField{}},
@@ -5418,4 +5449,46 @@ var instFormats = [...]instFormat{
                [5]*argField{ap_Reg_6_10, ap_SpReg_11_20}},
        {MTPMR, 0xfc0007fe, 0x7c00039c, 0x1, // Move To Performance Monitor Register XFX-form (mtpmr PMRN,RS)
                [5]*argField{ap_SpReg_11_20, ap_Reg_6_10}},
+       {ADDEX, 0xfc0001fe, 0x7c000154, 0x1, // Add Extended using alternate carry bit Z23-form (addex RT,RA,RB,CY)
+               [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20, ap_ImmUnsigned_21_22}},
+       {DARN, 0xfc0007fe, 0x7c0005e6, 0x1cf801, // Deliver A Random Number X-form (darn RT,L)
+               [5]*argField{ap_Reg_6_10, ap_ImmUnsigned_14_15}},
+       {MADDHD, 0xfc00003f, 0x10000030, 0x0, // Multiply-Add High Doubleword VA-form (maddhd RT,RA,RB,RC)
+               [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20, ap_Reg_21_25}},
+       {MADDHDU, 0xfc00003f, 0x10000031, 0x0, // Multiply-Add High Doubleword Unsigned VA-form (maddhdu RT,RA,RB,RC)
+               [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20, ap_Reg_21_25}},
+       {MADDLD, 0xfc00003f, 0x10000033, 0x0, // Multiply-Add Low Doubleword VA-form (maddld RT,RA,RB,RC)
+               [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20, ap_Reg_21_25}},
+       {CMPRB, 0xfc0007fe, 0x7c000180, 0x400001, // Compare Ranged Byte X-form (cmprb BF,L,RA,RB)
+               [5]*argField{ap_CondRegField_6_8, ap_ImmUnsigned_10_10, ap_Reg_11_15, ap_Reg_16_20}},
+       {CMPEQB, 0xfc0007fe, 0x7c0001c0, 0x600001, // Compare Equal Byte X-form (cmpeqb BF,RA,RB)
+               [5]*argField{ap_CondRegField_6_8, ap_Reg_11_15, ap_Reg_16_20}},
+       {BPERMD, 0xfc0007fe, 0x7c0001f8, 0x1, // Bit Permute Doubleword X-form (bpermd RA,RS,RB])
+               [5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20}},
+       {EXTSWSLI, 0xfc0007fd, 0x7c0006f4, 0x0, // Extend-Sign Word and Shift Left Immediate XS-form (extswsli RA,RS,SH)
+               [5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_ImmUnsigned_30_30_16_20}},
+       {EXTSWSLICC, 0xfc0007fd, 0x7c0006f5, 0x0, // Extend-Sign Word and Shift Left Immediate XS-form (extswsli. RA,RS,SH)
+               [5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_ImmUnsigned_30_30_16_20}},
+       {MFVSRD, 0xfc0007fe, 0x7c000066, 0xf800, // Move From VSR Doubleword X-form (mfvsrd RA,XS)
+               [5]*argField{ap_Reg_11_15, ap_VecSReg_31_31_6_10}},
+       {MFVSRLD, 0xfc0007fe, 0x7c000266, 0xf800, // Move From VSR Lower Doubleword X-form (mfvsrld RA,XS)
+               [5]*argField{ap_Reg_11_15, ap_VecSReg_31_31_6_10}},
+       {MFVSRWZ, 0xfc0007fe, 0x7c0000e6, 0xf800, // Move From VSR Word and Zero X-form (mfvsrwz RA,XS)
+               [5]*argField{ap_Reg_11_15, ap_VecSReg_31_31_6_10}},
+       {MTVSRD, 0xfc0007fe, 0x7c000166, 0xf800, // Move To VSR Doubleword X-form (mtvsrd XT,RA)
+               [5]*argField{ap_VecSReg_31_31_6_10, ap_Reg_11_15}},
+       {MTVSRWA, 0xfc0007fe, 0x7c0001a6, 0xf800, // Move To VSR Word Algebraic X-form (mtvsrwa XT,RA)
+               [5]*argField{ap_VecSReg_31_31_6_10, ap_Reg_11_15}},
+       {MTVSRWZ, 0xfc0007fe, 0x7c0001e6, 0xf800, // Move To VSR Word and Zero X-form (mtvsrwz XT,RA)
+               [5]*argField{ap_VecSReg_31_31_6_10, ap_Reg_11_15}},
+       {MTVSRDD, 0xfc0007fe, 0x7c000366, 0x0, // Move To VSR Double Doubleword X-form (mtvsrdd XT,RA,RB)
+               [5]*argField{ap_VecSReg_31_31_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+       {MTVSRWS, 0xfc0007fe, 0x7c000326, 0xf800, // Move To VSR Word & Splat X-form (mtvsrws XT,RA)
+               [5]*argField{ap_VecSReg_31_31_6_10, ap_Reg_11_15}},
+       {MCRXRX, 0xfc0007fe, 0x7c000480, 0x7ff801, // Move to CR from XER Extended X-form (mcrxrx BF)
+               [5]*argField{ap_CondRegField_6_8}},
+       {COPY, 0xfc2007fe, 0x7c20060c, 0x3c00001, // Copy X-form (copy RA,RB)
+               [5]*argField{ap_Reg_11_15, ap_Reg_16_20}},
+       {PASTECC, 0xfc2007ff, 0x7c20070d, 0x3c00000, // Paste X-form (paste. RA,RB)
+               [5]*argField{ap_Reg_11_15, ap_Reg_16_20}},
 }

diff --git a/src/cmd/vendor/golang.org/x/arch/ppc64/ppc64asm/testdata/decode.txt b/src/cmd/vendor/golang.org/x/arch/ppc64/ppc64asm/testdata/decode.txt
index b4e5db2cb2c3f3121387876bfacea630c152c94f..2a89de04c913260b515b469e9a8644a2f53f7fcd 100644 (file)
--- a/src/cmd/vendor/golang.org/x/arch/ppc64/ppc64asm/testdata/decode.txt
+++ b/src/cmd/vendor/golang.org/x/arch/ppc64/ppc64asm/testdata/decode.txt
@@ -1,25 +1,56 @@
 6d746162|      gnu     xoris r20,r11,24930
+6d746162|      plan9   XORIS R11,$24930,R20
 4c040000|      gnu     mcrf cr0,cr1
-88000017|      gnu     lbz r0,23(0)
-4abaa88a|      gnu     ba 0xfebaa888
-7d8fc2a6|      gnu     mfspr r12,783
-00000000|      gnu     error: unknown instruction
+88a70002|      gnu     lbz r5,2(r7)
+88a70002|      plan9   MOVBZ 2(R7),R5
+00000000|      plan9   WORD $0
+00010000|      plan9   error: unknown instruction
+00000000|      gnu     .long 0x0
+00002000|      gnu     error: unknown instruction
 a1841e80|      gnu     lhz r12,7808(r4)
+a1841e80|      plan9   MOVHZ 7808(R4),R12
 42093d10|      gnu     bc 16,4*cr2+gt,.+0x3d10
 e38d5b90|      gnu     lq r28,23440(r13)
 84127a20|      gnu     lwzu r0,31264(r18)
-c61bb730|      gnu     lfsu f16,-18640(r27)
-0825f440|      gnu     tdi 1,r5,-3008
-a9a912c1|      gnu     lha r13,4801(r9)
+84127a20|      plan9   MOVWZU 31264(R18),R0
+a8630000|      gnu     lha r3,0(r3)
+a8630000|      plan9   MOVH 0(R3),R3
 ebb24fd1|      gnu     ldu r29,20432(r18)
+ebb24fd1|      plan9   MOVDU 20432(R18),R29
 b1ce0612|      gnu     sth r14,1554(r14)
-f3c04322|      gnu     xvcvdpuxws vs30,vs40
+b1ce0612|      plan9   MOVH R14,1554(R14)
 945c62a2|      gnu     stwu r2,25250(r28)
-9c8156e3|      gnu     stbu r4,22243(r1)
 f91b9c7a|      gnu     stq r8,-25480(r27)
-2c1c81b4|      gnu     cmpwi r28,-32332
-f87b904d|      gnu     stdu r3,-28596(r27)
-eab3c832|      gnu     lwa r21,-14288(r19)
+2c030001|      gnu     cmpwi r3,1
+2c030001|      plan9   CMPW R3,$1
+e8610032|      gnu     lwa r3,48(r1)
+e8610032|      plan9   MOVW 48(R1),R3
 4320336b|      gnu     bcla 25,lt,0x3368
 7e40092e|      gnu     stwx r18,0,r1
+7e40092e|      plan9   MOVW R18,(R1)(0)
 7c103c2c|      gnu     lwbrx r0,r16,r7
+7c103c2c|      plan9   MOVWBR (R7)(R16),R0
+7c441d28|      gnu     stdbrx r2,r4,r3
+7c441d28|      plan9   MOVDBR R2,(R3)(R4)
+3d220001|      gnu     addis r9,r2,1
+3d220001|      plan9   ADDIS R2,$1,R9
+7ce628ae|      gnu     lbzx r7,r6,r5
+7ce628ae|      plan9   MOVBZ (R5)(R6),R7
+7c0e1e99|      gnu     lxvd2x vs32,r14,r3
+7c0e1e99|      plan9   LXVD2X (R3)(R14),VS32
+7c00422c|      gnu     dcbt r0,r8,0
+7c00422c|      plan9   DCBT (R8)
+7fab3040|      gnu     cmpld cr7,r11,r6
+7fab3040|      plan9   CMPU CR7,R11,R6
+2c030001|      gnu     cmpwi r3,1
+2c030001|      plan9   CMPW R3,$1
+7c2b4840|      gnu     cmpld r11,r9
+7c2b4840|      plan9   CMPU R11,R9
+7c6521ad|      gnu     stdcx. r3,r5,r4
+7c6521ad|      plan9   STDCXCC R3,(R4)(R5)
+fbe1ffd1|      gnu     stdu r31,-48(r1)
+fbe1ffd1|      plan9   MOVDU R31,-48(R1)
+7c941f19|      gnu     stxvw4x vs36,r20,r3
+7c941f19|      plan9   STXVW4X VS36,(R3)(R20)
+7c6520a8|      gnu     ldarx r3,r5,r4
+7c6520a8|      plan9   LDAR (R4)(R5),R3

diff --git a/src/cmd/vendor/vendor.json b/src/cmd/vendor/vendor.json
index 23ff3225af9a7b74312090ecabed127e7da44460..89764c8c6fee33a40d420de727ad8bf584881439 100644 (file)
--- a/src/cmd/vendor/vendor.json
+++ b/src/cmd/vendor/vendor.json
@@ -116,8 +116,8 @@
                },
                {
                        "path": "golang.org/x/arch/ppc64/ppc64asm",
-                       "revision": "5099b4b992f2813e39cfe2623c6f638718bd0fc6",
-                       "revisionTime": "2018-04-06T10:28:20Z"
+                       "revision": "5a4828bb704534b8a2fa09c791c67d0fb372f472",
+                       "revisionTime": "2018-12-03T22:54:21Z"
                },
                {
                        "path": "golang.org/x/arch/x86/x86asm",