cmd/compile: mark MOVQconvert as resultInArg0 on x86 architectures

This prevents unnecessary reg-reg moves during pointer arithmetic.

This change reduces the size of the full hello world binary by 0.4%.

Updates #21572

Change-Id: Ia0427021e5c94545a0dbd83a6801815806e5b12d
Reviewed-on: https://go-review.googlesource.com/58371
Run-TryBot: Josh Bleecher Snyder <josharian@gmail.com>
Run-TryBot: Martin Möhrmann <moehrmann@google.com>
Reviewed-by: Keith Randall <khr@golang.org>

diff --git a/src/cmd/compile/internal/ssa/gen/386Ops.go b/src/cmd/compile/internal/ssa/gen/386Ops.go
index 8965d62353d50b8a2474f205da726ad0582b9256..25f3931c20629e9afb55b35c1a4e88b8bb7be790 100644 (file)
--- a/src/cmd/compile/internal/ssa/gen/386Ops.go
+++ b/src/cmd/compile/internal/ssa/gen/386Ops.go
@@ -448,7 +448,7 @@ func init() {
                // (particularly stack maps).  It takes a memory arg so it
                // gets correctly ordered with respect to GC safepoints.
                // arg0=ptr/int arg1=mem, output=int/ptr
-               {name: "MOVLconvert", argLength: 2, reg: gp11, asm: "MOVL"},
+               {name: "MOVLconvert", argLength: 2, reg: gp11, asm: "MOVL", resultInArg0: true},
 
                // Constant flag values. For any comparison, there are 5 possible
                // outcomes: the three from the signed total order (<,==,>) and the

diff --git a/src/cmd/compile/internal/ssa/gen/AMD64Ops.go b/src/cmd/compile/internal/ssa/gen/AMD64Ops.go
index da38eba678cdeed31fd16a3315eb3af0955018ff..89781acd854e47aa6b1166080f29d3dd2ddd2567 100644 (file)
--- a/src/cmd/compile/internal/ssa/gen/AMD64Ops.go
+++ b/src/cmd/compile/internal/ssa/gen/AMD64Ops.go
@@ -538,8 +538,8 @@ func init() {
                // (particularly stack maps).  It takes a memory arg so it
                // gets correctly ordered with respect to GC safepoints.
                // arg0=ptr/int arg1=mem, output=int/ptr
-               {name: "MOVQconvert", argLength: 2, reg: gp11, asm: "MOVQ"},
-               {name: "MOVLconvert", argLength: 2, reg: gp11, asm: "MOVL"}, // amd64p32 equivalent
+               {name: "MOVQconvert", argLength: 2, reg: gp11, asm: "MOVQ", resultInArg0: true},
+               {name: "MOVLconvert", argLength: 2, reg: gp11, asm: "MOVL", resultInArg0: true}, // amd64p32 equivalent
 
                // Constant flag values. For any comparison, there are 5 possible
                // outcomes: the three from the signed total order (<,==,>) and the

diff --git a/src/cmd/compile/internal/ssa/gen/main.go b/src/cmd/compile/internal/ssa/gen/main.go
index ea6fa8781366aa75efa4293cf0b84a9d07760f8c..6562fdcf467df12273fbf3821638d19373790054 100644 (file)
--- a/src/cmd/compile/internal/ssa/gen/main.go
+++ b/src/cmd/compile/internal/ssa/gen/main.go
@@ -177,10 +177,10 @@ func genOp() {
                        if v.resultInArg0 {
                                fmt.Fprintln(w, "resultInArg0: true,")
                                if v.reg.inputs[0] != v.reg.outputs[0] {
-                                       log.Fatalf("input[0] and output[0] must use the same registers for %s", v.name)
+                                       log.Fatalf("%s: input[0] and output[0] must use the same registers for %s", a.name, v.name)
                                }
                                if v.commutative && v.reg.inputs[1] != v.reg.outputs[0] {
-                                       log.Fatalf("input[1] and output[0] must use the same registers for %s", v.name)
+                                       log.Fatalf("%s: input[1] and output[0] must use the same registers for %s", a.name, v.name)
                                }
                        }
                        if v.resultNotInArgs {

diff --git a/src/cmd/compile/internal/ssa/opGen.go b/src/cmd/compile/internal/ssa/opGen.go
index 81fbf7299848a5f93f007fe245275bd5e85284ac..b754a6747ec0e21fb132bd636742d3d42998a357 100644 (file)
--- a/src/cmd/compile/internal/ssa/opGen.go
+++ b/src/cmd/compile/internal/ssa/opGen.go
@@ -4271,9 +4271,10 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:   "MOVLconvert",
-               argLen: 2,
-               asm:    x86.AMOVL,
+               name:         "MOVLconvert",
+               argLen:       2,
+               resultInArg0: true,
+               asm:          x86.AMOVL,
                reg: regInfo{
                        inputs: []inputInfo{
                                {0, 239}, // AX CX DX BX BP SI DI
@@ -7820,9 +7821,10 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:   "MOVQconvert",
-               argLen: 2,
-               asm:    x86.AMOVQ,
+               name:         "MOVQconvert",
+               argLen:       2,
+               resultInArg0: true,
+               asm:          x86.AMOVQ,
                reg: regInfo{
                        inputs: []inputInfo{
                                {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
@@ -7833,9 +7835,10 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:   "MOVLconvert",
-               argLen: 2,
-               asm:    x86.AMOVL,
+               name:         "MOVLconvert",
+               argLen:       2,
+               resultInArg0: true,
+               asm:          x86.AMOVL,
                reg: regInfo{
                        inputs: []inputInfo{
                                {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15