(MOVDnop <t> x:(MOVWload [off] {sym} ptr mem)) && x.Uses == 1 && clobber(x) -> @x.Block (MOVWload <t> [off] {sym} ptr mem)
(MOVDnop <t> x:(MOVDload [off] {sym} ptr mem)) && x.Uses == 1 && clobber(x) -> @x.Block (MOVDload <t> [off] {sym} ptr mem)
-// TODO(mundaym): uncomment rules once signed indexed loads are added.
(MOVDreg <t> x:(MOVBZloadidx [off] {sym} ptr idx mem)) && x.Uses == 1 && clobber(x) -> @x.Block (MOVBZloadidx <t> [off] {sym} ptr idx mem)
-//(MOVDreg <t> x:(MOVBloadidx [off] {sym} ptr idx mem)) && x.Uses == 1 && clobber(x) -> @x.Block (MOVBloadidx <t> [off] {sym} ptr idx mem)
+(MOVDreg <t> x:(MOVBloadidx [off] {sym} ptr idx mem)) && x.Uses == 1 && clobber(x) -> @x.Block (MOVBloadidx <t> [off] {sym} ptr idx mem)
(MOVDreg <t> x:(MOVHZloadidx [off] {sym} ptr idx mem)) && x.Uses == 1 && clobber(x) -> @x.Block (MOVHZloadidx <t> [off] {sym} ptr idx mem)
-//(MOVDreg <t> x:(MOVHloadidx [off] {sym} ptr idx mem)) && x.Uses == 1 && clobber(x) -> @x.Block (MOVHloadidx <t> [off] {sym} ptr idx mem)
+(MOVDreg <t> x:(MOVHloadidx [off] {sym} ptr idx mem)) && x.Uses == 1 && clobber(x) -> @x.Block (MOVHloadidx <t> [off] {sym} ptr idx mem)
(MOVDreg <t> x:(MOVWZloadidx [off] {sym} ptr idx mem)) && x.Uses == 1 && clobber(x) -> @x.Block (MOVWZloadidx <t> [off] {sym} ptr idx mem)
-//(MOVDreg <t> x:(MOVWloadidx [off] {sym} ptr idx mem)) && x.Uses == 1 && clobber(x) -> @x.Block (MOVWloadidx <t> [off] {sym} ptr idx mem)
+(MOVDreg <t> x:(MOVWloadidx [off] {sym} ptr idx mem)) && x.Uses == 1 && clobber(x) -> @x.Block (MOVWloadidx <t> [off] {sym} ptr idx mem)
(MOVDreg <t> x:(MOVDloadidx [off] {sym} ptr idx mem)) && x.Uses == 1 && clobber(x) -> @x.Block (MOVDloadidx <t> [off] {sym} ptr idx mem)
(MOVDnop <t> x:(MOVBZloadidx [off] {sym} ptr idx mem)) && x.Uses == 1 && clobber(x) -> @x.Block (MOVBZloadidx <t> [off] {sym} ptr idx mem)
-//(MOVDnop <t> x:(MOVBloadidx [off] {sym} ptr idx mem)) && x.Uses == 1 && clobber(x) -> @x.Block (MOVBloadidx <t> [off] {sym} ptr idx mem)
+(MOVDnop <t> x:(MOVBloadidx [off] {sym} ptr idx mem)) && x.Uses == 1 && clobber(x) -> @x.Block (MOVBloadidx <t> [off] {sym} ptr idx mem)
(MOVDnop <t> x:(MOVHZloadidx [off] {sym} ptr idx mem)) && x.Uses == 1 && clobber(x) -> @x.Block (MOVHZloadidx <t> [off] {sym} ptr idx mem)
-//(MOVDnop <t> x:(MOVHloadidx [off] {sym} ptr idx mem)) && x.Uses == 1 && clobber(x) -> @x.Block (MOVHloadidx <t> [off] {sym} ptr idx mem)
+(MOVDnop <t> x:(MOVHloadidx [off] {sym} ptr idx mem)) && x.Uses == 1 && clobber(x) -> @x.Block (MOVHloadidx <t> [off] {sym} ptr idx mem)
(MOVDnop <t> x:(MOVWZloadidx [off] {sym} ptr idx mem)) && x.Uses == 1 && clobber(x) -> @x.Block (MOVWZloadidx <t> [off] {sym} ptr idx mem)
-//(MOVDnop <t> x:(MOVWloadidx [off] {sym} ptr idx mem)) && x.Uses == 1 && clobber(x) -> @x.Block (MOVWloadidx <t> [off] {sym} ptr idx mem)
+(MOVDnop <t> x:(MOVWloadidx [off] {sym} ptr idx mem)) && x.Uses == 1 && clobber(x) -> @x.Block (MOVWloadidx <t> [off] {sym} ptr idx mem)
(MOVDnop <t> x:(MOVDloadidx [off] {sym} ptr idx mem)) && x.Uses == 1 && clobber(x) -> @x.Block (MOVDloadidx <t> [off] {sym} ptr idx mem)
// Fold sign extensions into conditional moves of constants.
// Make sure we don't combine these ops if the load has another use.
// This prevents a single load from being split into multiple loads
// which then might return different values. See test/atomicload.go.
-(MOVBreg x:(MOVBZload [off] {sym} ptr mem)) && x.Uses == 1 && clobber(x) -> @x.Block (MOVBload <v.Type> [off] {sym} ptr mem)
+(MOVBreg x:(MOVBZload [off] {sym} ptr mem)) && x.Uses == 1 && clobber(x) -> @x.Block (MOVBload <v.Type> [off] {sym} ptr mem)
+(MOVBreg x:(MOVBload [off] {sym} ptr mem)) && x.Uses == 1 && clobber(x) -> @x.Block (MOVBload <v.Type> [off] {sym} ptr mem)
(MOVBZreg x:(MOVBZload [off] {sym} ptr mem)) && x.Uses == 1 && clobber(x) -> @x.Block (MOVBZload <v.Type> [off] {sym} ptr mem)
-(MOVHreg x:(MOVHZload [off] {sym} ptr mem)) && x.Uses == 1 && clobber(x) -> @x.Block (MOVHload <v.Type> [off] {sym} ptr mem)
+(MOVBZreg x:(MOVBload [off] {sym} ptr mem)) && x.Uses == 1 && clobber(x) -> @x.Block (MOVBZload <v.Type> [off] {sym} ptr mem)
+(MOVHreg x:(MOVHZload [off] {sym} ptr mem)) && x.Uses == 1 && clobber(x) -> @x.Block (MOVHload <v.Type> [off] {sym} ptr mem)
+(MOVHreg x:(MOVHload [off] {sym} ptr mem)) && x.Uses == 1 && clobber(x) -> @x.Block (MOVHload <v.Type> [off] {sym} ptr mem)
(MOVHZreg x:(MOVHZload [off] {sym} ptr mem)) && x.Uses == 1 && clobber(x) -> @x.Block (MOVHZload <v.Type> [off] {sym} ptr mem)
-(MOVWreg x:(MOVWZload [off] {sym} ptr mem)) && x.Uses == 1 && clobber(x) -> @x.Block (MOVWload <v.Type> [off] {sym} ptr mem)
+(MOVHZreg x:(MOVHload [off] {sym} ptr mem)) && x.Uses == 1 && clobber(x) -> @x.Block (MOVHZload <v.Type> [off] {sym} ptr mem)
+(MOVWreg x:(MOVWZload [off] {sym} ptr mem)) && x.Uses == 1 && clobber(x) -> @x.Block (MOVWload <v.Type> [off] {sym} ptr mem)
+(MOVWreg x:(MOVWload [off] {sym} ptr mem)) && x.Uses == 1 && clobber(x) -> @x.Block (MOVWload <v.Type> [off] {sym} ptr mem)
(MOVWZreg x:(MOVWZload [off] {sym} ptr mem)) && x.Uses == 1 && clobber(x) -> @x.Block (MOVWZload <v.Type> [off] {sym} ptr mem)
+(MOVWZreg x:(MOVWload [off] {sym} ptr mem)) && x.Uses == 1 && clobber(x) -> @x.Block (MOVWZload <v.Type> [off] {sym} ptr mem)
+(MOVBreg x:(MOVBZloadidx [off] {sym} ptr idx mem)) && x.Uses == 1 && clobber(x) -> @x.Block (MOVBloadidx <v.Type> [off] {sym} ptr idx mem)
+(MOVBreg x:(MOVBloadidx [off] {sym} ptr idx mem)) && x.Uses == 1 && clobber(x) -> @x.Block (MOVBloadidx <v.Type> [off] {sym} ptr idx mem)
(MOVBZreg x:(MOVBZloadidx [off] {sym} ptr idx mem)) && x.Uses == 1 && clobber(x) -> @x.Block (MOVBZloadidx <v.Type> [off] {sym} ptr idx mem)
+(MOVBZreg x:(MOVBloadidx [off] {sym} ptr idx mem)) && x.Uses == 1 && clobber(x) -> @x.Block (MOVBZloadidx <v.Type> [off] {sym} ptr idx mem)
+(MOVHreg x:(MOVHZloadidx [off] {sym} ptr idx mem)) && x.Uses == 1 && clobber(x) -> @x.Block (MOVHloadidx <v.Type> [off] {sym} ptr idx mem)
+(MOVHreg x:(MOVHloadidx [off] {sym} ptr idx mem)) && x.Uses == 1 && clobber(x) -> @x.Block (MOVHloadidx <v.Type> [off] {sym} ptr idx mem)
(MOVHZreg x:(MOVHZloadidx [off] {sym} ptr idx mem)) && x.Uses == 1 && clobber(x) -> @x.Block (MOVHZloadidx <v.Type> [off] {sym} ptr idx mem)
+(MOVHZreg x:(MOVHloadidx [off] {sym} ptr idx mem)) && x.Uses == 1 && clobber(x) -> @x.Block (MOVHZloadidx <v.Type> [off] {sym} ptr idx mem)
+(MOVWreg x:(MOVWZloadidx [off] {sym} ptr idx mem)) && x.Uses == 1 && clobber(x) -> @x.Block (MOVWloadidx <v.Type> [off] {sym} ptr idx mem)
+(MOVWreg x:(MOVWloadidx [off] {sym} ptr idx mem)) && x.Uses == 1 && clobber(x) -> @x.Block (MOVWloadidx <v.Type> [off] {sym} ptr idx mem)
(MOVWZreg x:(MOVWZloadidx [off] {sym} ptr idx mem)) && x.Uses == 1 && clobber(x) -> @x.Block (MOVWZloadidx <v.Type> [off] {sym} ptr idx mem)
+(MOVWZreg x:(MOVWloadidx [off] {sym} ptr idx mem)) && x.Uses == 1 && clobber(x) -> @x.Block (MOVWZloadidx <v.Type> [off] {sym} ptr idx mem)
// replace load from same location as preceding store with copy
(MOVDload [off] {sym} ptr1 (MOVDstore [off] {sym} ptr2 x _)) && isSamePtr(ptr1, ptr2) -> (MOVDreg x)
// generating indexed loads and stores
(MOVBZload [off1] {sym1} (MOVDaddridx [off2] {sym2} ptr idx) mem) && is32Bit(off1+off2) && canMergeSym(sym1, sym2) ->
(MOVBZloadidx [off1+off2] {mergeSym(sym1,sym2)} ptr idx mem)
+(MOVBload [off1] {sym1} (MOVDaddridx [off2] {sym2} ptr idx) mem) && is32Bit(off1+off2) && canMergeSym(sym1, sym2) ->
+ (MOVBloadidx [off1+off2] {mergeSym(sym1,sym2)} ptr idx mem)
(MOVHZload [off1] {sym1} (MOVDaddridx [off2] {sym2} ptr idx) mem) && is32Bit(off1+off2) && canMergeSym(sym1, sym2) ->
(MOVHZloadidx [off1+off2] {mergeSym(sym1,sym2)} ptr idx mem)
+(MOVHload [off1] {sym1} (MOVDaddridx [off2] {sym2} ptr idx) mem) && is32Bit(off1+off2) && canMergeSym(sym1, sym2) ->
+ (MOVHloadidx [off1+off2] {mergeSym(sym1,sym2)} ptr idx mem)
(MOVWZload [off1] {sym1} (MOVDaddridx [off2] {sym2} ptr idx) mem) && is32Bit(off1+off2) && canMergeSym(sym1, sym2) ->
(MOVWZloadidx [off1+off2] {mergeSym(sym1,sym2)} ptr idx mem)
+(MOVWload [off1] {sym1} (MOVDaddridx [off2] {sym2} ptr idx) mem) && is32Bit(off1+off2) && canMergeSym(sym1, sym2) ->
+ (MOVWloadidx [off1+off2] {mergeSym(sym1,sym2)} ptr idx mem)
(MOVDload [off1] {sym1} (MOVDaddridx [off2] {sym2} ptr idx) mem) && is32Bit(off1+off2) && canMergeSym(sym1, sym2) ->
(MOVDloadidx [off1+off2] {mergeSym(sym1,sym2)} ptr idx mem)
(FMOVSload [off1] {sym1} (MOVDaddridx [off2] {sym2} ptr idx) mem) && is32Bit(off1+off2) && canMergeSym(sym1, sym2) ->
(FMOVDstoreidx [off1+off2] {mergeSym(sym1,sym2)} ptr idx val mem)
(MOVBZload [off] {sym} (ADD ptr idx) mem) && ptr.Op != OpSB -> (MOVBZloadidx [off] {sym} ptr idx mem)
+(MOVBload [off] {sym} (ADD ptr idx) mem) && ptr.Op != OpSB -> (MOVBloadidx [off] {sym} ptr idx mem)
(MOVHZload [off] {sym} (ADD ptr idx) mem) && ptr.Op != OpSB -> (MOVHZloadidx [off] {sym} ptr idx mem)
+(MOVHload [off] {sym} (ADD ptr idx) mem) && ptr.Op != OpSB -> (MOVHloadidx [off] {sym} ptr idx mem)
(MOVWZload [off] {sym} (ADD ptr idx) mem) && ptr.Op != OpSB -> (MOVWZloadidx [off] {sym} ptr idx mem)
-(MOVDload [off] {sym} (ADD ptr idx) mem) && ptr.Op != OpSB -> (MOVDloadidx [off] {sym} ptr idx mem)
+(MOVWload [off] {sym} (ADD ptr idx) mem) && ptr.Op != OpSB -> (MOVWloadidx [off] {sym} ptr idx mem)
+(MOVDload [off] {sym} (ADD ptr idx) mem) && ptr.Op != OpSB -> (MOVDloadidx [off] {sym} ptr idx mem)
(FMOVSload [off] {sym} (ADD ptr idx) mem) && ptr.Op != OpSB -> (FMOVSloadidx [off] {sym} ptr idx mem)
(FMOVDload [off] {sym} (ADD ptr idx) mem) && ptr.Op != OpSB -> (FMOVDloadidx [off] {sym} ptr idx mem)
-(MOVBstore [off] {sym} (ADD ptr idx) val mem) && ptr.Op != OpSB -> (MOVBstoreidx [off] {sym} ptr idx val mem)
-(MOVHstore [off] {sym} (ADD ptr idx) val mem) && ptr.Op != OpSB -> (MOVHstoreidx [off] {sym} ptr idx val mem)
-(MOVWstore [off] {sym} (ADD ptr idx) val mem) && ptr.Op != OpSB -> (MOVWstoreidx [off] {sym} ptr idx val mem)
-(MOVDstore [off] {sym} (ADD ptr idx) val mem) && ptr.Op != OpSB -> (MOVDstoreidx [off] {sym} ptr idx val mem)
+
+(MOVBstore [off] {sym} (ADD ptr idx) val mem) && ptr.Op != OpSB -> (MOVBstoreidx [off] {sym} ptr idx val mem)
+(MOVHstore [off] {sym} (ADD ptr idx) val mem) && ptr.Op != OpSB -> (MOVHstoreidx [off] {sym} ptr idx val mem)
+(MOVWstore [off] {sym} (ADD ptr idx) val mem) && ptr.Op != OpSB -> (MOVWstoreidx [off] {sym} ptr idx val mem)
+(MOVDstore [off] {sym} (ADD ptr idx) val mem) && ptr.Op != OpSB -> (MOVDstoreidx [off] {sym} ptr idx val mem)
(FMOVSstore [off] {sym} (ADD ptr idx) val mem) && ptr.Op != OpSB -> (FMOVSstoreidx [off] {sym} ptr idx val mem)
(FMOVDstore [off] {sym} (ADD ptr idx) val mem) && ptr.Op != OpSB -> (FMOVDstoreidx [off] {sym} ptr idx val mem)
// combine ADD into indexed loads and stores
-(MOVBZloadidx [c] {sym} (ADDconst [d] ptr) idx mem) -> (MOVBZloadidx [c+d] {sym} ptr idx mem)
-(MOVHZloadidx [c] {sym} (ADDconst [d] ptr) idx mem) -> (MOVHZloadidx [c+d] {sym} ptr idx mem)
-(MOVWZloadidx [c] {sym} (ADDconst [d] ptr) idx mem) -> (MOVWZloadidx [c+d] {sym} ptr idx mem)
-(MOVDloadidx [c] {sym} (ADDconst [d] ptr) idx mem) -> (MOVDloadidx [c+d] {sym} ptr idx mem)
-(FMOVSloadidx [c] {sym} (ADDconst [d] ptr) idx mem) -> (FMOVSloadidx [c+d] {sym} ptr idx mem)
-(FMOVDloadidx [c] {sym} (ADDconst [d] ptr) idx mem) -> (FMOVDloadidx [c+d] {sym} ptr idx mem)
-
-(MOVBstoreidx [c] {sym} (ADDconst [d] ptr) idx val mem) -> (MOVBstoreidx [c+d] {sym} ptr idx val mem)
-(MOVHstoreidx [c] {sym} (ADDconst [d] ptr) idx val mem) -> (MOVHstoreidx [c+d] {sym} ptr idx val mem)
-(MOVWstoreidx [c] {sym} (ADDconst [d] ptr) idx val mem) -> (MOVWstoreidx [c+d] {sym} ptr idx val mem)
-(MOVDstoreidx [c] {sym} (ADDconst [d] ptr) idx val mem) -> (MOVDstoreidx [c+d] {sym} ptr idx val mem)
-(FMOVSstoreidx [c] {sym} (ADDconst [d] ptr) idx val mem) -> (FMOVSstoreidx [c+d] {sym} ptr idx val mem)
-(FMOVDstoreidx [c] {sym} (ADDconst [d] ptr) idx val mem) -> (FMOVDstoreidx [c+d] {sym} ptr idx val mem)
-
-(MOVBZloadidx [c] {sym} ptr (ADDconst [d] idx) mem) -> (MOVBZloadidx [c+d] {sym} ptr idx mem)
-(MOVHZloadidx [c] {sym} ptr (ADDconst [d] idx) mem) -> (MOVHZloadidx [c+d] {sym} ptr idx mem)
-(MOVWZloadidx [c] {sym} ptr (ADDconst [d] idx) mem) -> (MOVWZloadidx [c+d] {sym} ptr idx mem)
-(MOVDloadidx [c] {sym} ptr (ADDconst [d] idx) mem) -> (MOVDloadidx [c+d] {sym} ptr idx mem)
-(FMOVSloadidx [c] {sym} ptr (ADDconst [d] idx) mem) -> (FMOVSloadidx [c+d] {sym} ptr idx mem)
-(FMOVDloadidx [c] {sym} ptr (ADDconst [d] idx) mem) -> (FMOVDloadidx [c+d] {sym} ptr idx mem)
-
-(MOVBstoreidx [c] {sym} ptr (ADDconst [d] idx) val mem) -> (MOVBstoreidx [c+d] {sym} ptr idx val mem)
-(MOVHstoreidx [c] {sym} ptr (ADDconst [d] idx) val mem) -> (MOVHstoreidx [c+d] {sym} ptr idx val mem)
-(MOVWstoreidx [c] {sym} ptr (ADDconst [d] idx) val mem) -> (MOVWstoreidx [c+d] {sym} ptr idx val mem)
-(MOVDstoreidx [c] {sym} ptr (ADDconst [d] idx) val mem) -> (MOVDstoreidx [c+d] {sym} ptr idx val mem)
-(FMOVSstoreidx [c] {sym} ptr (ADDconst [d] idx) val mem) -> (FMOVSstoreidx [c+d] {sym} ptr idx val mem)
-(FMOVDstoreidx [c] {sym} ptr (ADDconst [d] idx) val mem) -> (FMOVDstoreidx [c+d] {sym} ptr idx val mem)
+(MOVBZloadidx [c] {sym} (ADDconst [d] ptr) idx mem) && is20Bit(c+d) -> (MOVBZloadidx [c+d] {sym} ptr idx mem)
+(MOVBloadidx [c] {sym} (ADDconst [d] ptr) idx mem) && is20Bit(c+d) -> (MOVBloadidx [c+d] {sym} ptr idx mem)
+(MOVHZloadidx [c] {sym} (ADDconst [d] ptr) idx mem) && is20Bit(c+d) -> (MOVHZloadidx [c+d] {sym} ptr idx mem)
+(MOVHloadidx [c] {sym} (ADDconst [d] ptr) idx mem) && is20Bit(c+d) -> (MOVHloadidx [c+d] {sym} ptr idx mem)
+(MOVWZloadidx [c] {sym} (ADDconst [d] ptr) idx mem) && is20Bit(c+d) -> (MOVWZloadidx [c+d] {sym} ptr idx mem)
+(MOVWloadidx [c] {sym} (ADDconst [d] ptr) idx mem) && is20Bit(c+d) -> (MOVWloadidx [c+d] {sym} ptr idx mem)
+(MOVDloadidx [c] {sym} (ADDconst [d] ptr) idx mem) && is20Bit(c+d) -> (MOVDloadidx [c+d] {sym} ptr idx mem)
+(FMOVSloadidx [c] {sym} (ADDconst [d] ptr) idx mem) && is20Bit(c+d) -> (FMOVSloadidx [c+d] {sym} ptr idx mem)
+(FMOVDloadidx [c] {sym} (ADDconst [d] ptr) idx mem) && is20Bit(c+d) -> (FMOVDloadidx [c+d] {sym} ptr idx mem)
+
+(MOVBstoreidx [c] {sym} (ADDconst [d] ptr) idx val mem) && is20Bit(c+d) -> (MOVBstoreidx [c+d] {sym} ptr idx val mem)
+(MOVHstoreidx [c] {sym} (ADDconst [d] ptr) idx val mem) && is20Bit(c+d) -> (MOVHstoreidx [c+d] {sym} ptr idx val mem)
+(MOVWstoreidx [c] {sym} (ADDconst [d] ptr) idx val mem) && is20Bit(c+d) -> (MOVWstoreidx [c+d] {sym} ptr idx val mem)
+(MOVDstoreidx [c] {sym} (ADDconst [d] ptr) idx val mem) && is20Bit(c+d) -> (MOVDstoreidx [c+d] {sym} ptr idx val mem)
+(FMOVSstoreidx [c] {sym} (ADDconst [d] ptr) idx val mem) && is20Bit(c+d) -> (FMOVSstoreidx [c+d] {sym} ptr idx val mem)
+(FMOVDstoreidx [c] {sym} (ADDconst [d] ptr) idx val mem) && is20Bit(c+d) -> (FMOVDstoreidx [c+d] {sym} ptr idx val mem)
+
+(MOVBZloadidx [c] {sym} ptr (ADDconst [d] idx) mem) && is20Bit(c+d) -> (MOVBZloadidx [c+d] {sym} ptr idx mem)
+(MOVBloadidx [c] {sym} ptr (ADDconst [d] idx) mem) && is20Bit(c+d) -> (MOVBloadidx [c+d] {sym} ptr idx mem)
+(MOVHZloadidx [c] {sym} ptr (ADDconst [d] idx) mem) && is20Bit(c+d) -> (MOVHZloadidx [c+d] {sym} ptr idx mem)
+(MOVHloadidx [c] {sym} ptr (ADDconst [d] idx) mem) && is20Bit(c+d) -> (MOVHloadidx [c+d] {sym} ptr idx mem)
+(MOVWZloadidx [c] {sym} ptr (ADDconst [d] idx) mem) && is20Bit(c+d) -> (MOVWZloadidx [c+d] {sym} ptr idx mem)
+(MOVWloadidx [c] {sym} ptr (ADDconst [d] idx) mem) && is20Bit(c+d) -> (MOVWloadidx [c+d] {sym} ptr idx mem)
+(MOVDloadidx [c] {sym} ptr (ADDconst [d] idx) mem) && is20Bit(c+d) -> (MOVDloadidx [c+d] {sym} ptr idx mem)
+(FMOVSloadidx [c] {sym} ptr (ADDconst [d] idx) mem) && is20Bit(c+d) -> (FMOVSloadidx [c+d] {sym} ptr idx mem)
+(FMOVDloadidx [c] {sym} ptr (ADDconst [d] idx) mem) && is20Bit(c+d) -> (FMOVDloadidx [c+d] {sym} ptr idx mem)
+
+(MOVBstoreidx [c] {sym} ptr (ADDconst [d] idx) val mem) && is20Bit(c+d) -> (MOVBstoreidx [c+d] {sym} ptr idx val mem)
+(MOVHstoreidx [c] {sym} ptr (ADDconst [d] idx) val mem) && is20Bit(c+d) -> (MOVHstoreidx [c+d] {sym} ptr idx val mem)
+(MOVWstoreidx [c] {sym} ptr (ADDconst [d] idx) val mem) && is20Bit(c+d) -> (MOVWstoreidx [c+d] {sym} ptr idx val mem)
+(MOVDstoreidx [c] {sym} ptr (ADDconst [d] idx) val mem) && is20Bit(c+d) -> (MOVDstoreidx [c+d] {sym} ptr idx val mem)
+(FMOVSstoreidx [c] {sym} ptr (ADDconst [d] idx) val mem) && is20Bit(c+d) -> (FMOVSstoreidx [c+d] {sym} ptr idx val mem)
+(FMOVDstoreidx [c] {sym} ptr (ADDconst [d] idx) val mem) && is20Bit(c+d) -> (FMOVDstoreidx [c+d] {sym} ptr idx val mem)
// MOVDaddr into MOVDaddridx
(MOVDaddridx [off1] {sym1} (MOVDaddr [off2] {sym2} x) y) && is32Bit(off1+off2) && canMergeSym(sym1, sym2) && x.Op != OpSB ->
return rewriteValueS390X_OpS390XMOVBZreg_0(v) || rewriteValueS390X_OpS390XMOVBZreg_10(v)
case OpS390XMOVBload:
return rewriteValueS390X_OpS390XMOVBload_0(v)
+ case OpS390XMOVBloadidx:
+ return rewriteValueS390X_OpS390XMOVBloadidx_0(v)
case OpS390XMOVBreg:
return rewriteValueS390X_OpS390XMOVBreg_0(v)
case OpS390XMOVBstore:
return rewriteValueS390X_OpS390XMOVHZreg_0(v)
case OpS390XMOVHload:
return rewriteValueS390X_OpS390XMOVHload_0(v)
+ case OpS390XMOVHloadidx:
+ return rewriteValueS390X_OpS390XMOVHloadidx_0(v)
case OpS390XMOVHreg:
- return rewriteValueS390X_OpS390XMOVHreg_0(v)
+ return rewriteValueS390X_OpS390XMOVHreg_0(v) || rewriteValueS390X_OpS390XMOVHreg_10(v)
case OpS390XMOVHstore:
return rewriteValueS390X_OpS390XMOVHstore_0(v) || rewriteValueS390X_OpS390XMOVHstore_10(v)
case OpS390XMOVHstoreconst:
case OpS390XMOVWZloadidx:
return rewriteValueS390X_OpS390XMOVWZloadidx_0(v)
case OpS390XMOVWZreg:
- return rewriteValueS390X_OpS390XMOVWZreg_0(v)
+ return rewriteValueS390X_OpS390XMOVWZreg_0(v) || rewriteValueS390X_OpS390XMOVWZreg_10(v)
case OpS390XMOVWload:
return rewriteValueS390X_OpS390XMOVWload_0(v)
+ case OpS390XMOVWloadidx:
+ return rewriteValueS390X_OpS390XMOVWloadidx_0(v)
case OpS390XMOVWreg:
return rewriteValueS390X_OpS390XMOVWreg_0(v) || rewriteValueS390X_OpS390XMOVWreg_10(v)
case OpS390XMOVWstore:
}
func rewriteValueS390X_OpS390XFMOVDloadidx_0(v *Value) bool {
// match: (FMOVDloadidx [c] {sym} (ADDconst [d] ptr) idx mem)
- // cond:
+ // cond: is20Bit(c+d)
// result: (FMOVDloadidx [c+d] {sym} ptr idx mem)
for {
c := v.AuxInt
ptr := v_0.Args[0]
idx := v.Args[1]
mem := v.Args[2]
+ if !(is20Bit(c + d)) {
+ break
+ }
v.reset(OpS390XFMOVDloadidx)
v.AuxInt = c + d
v.Aux = sym
return true
}
// match: (FMOVDloadidx [c] {sym} ptr (ADDconst [d] idx) mem)
- // cond:
+ // cond: is20Bit(c+d)
// result: (FMOVDloadidx [c+d] {sym} ptr idx mem)
for {
c := v.AuxInt
d := v_1.AuxInt
idx := v_1.Args[0]
mem := v.Args[2]
+ if !(is20Bit(c + d)) {
+ break
+ }
v.reset(OpS390XFMOVDloadidx)
v.AuxInt = c + d
v.Aux = sym
}
func rewriteValueS390X_OpS390XFMOVDstoreidx_0(v *Value) bool {
// match: (FMOVDstoreidx [c] {sym} (ADDconst [d] ptr) idx val mem)
- // cond:
+ // cond: is20Bit(c+d)
// result: (FMOVDstoreidx [c+d] {sym} ptr idx val mem)
for {
c := v.AuxInt
idx := v.Args[1]
val := v.Args[2]
mem := v.Args[3]
+ if !(is20Bit(c + d)) {
+ break
+ }
v.reset(OpS390XFMOVDstoreidx)
v.AuxInt = c + d
v.Aux = sym
return true
}
// match: (FMOVDstoreidx [c] {sym} ptr (ADDconst [d] idx) val mem)
- // cond:
+ // cond: is20Bit(c+d)
// result: (FMOVDstoreidx [c+d] {sym} ptr idx val mem)
for {
c := v.AuxInt
idx := v_1.Args[0]
val := v.Args[2]
mem := v.Args[3]
+ if !(is20Bit(c + d)) {
+ break
+ }
v.reset(OpS390XFMOVDstoreidx)
v.AuxInt = c + d
v.Aux = sym
}
func rewriteValueS390X_OpS390XFMOVSloadidx_0(v *Value) bool {
// match: (FMOVSloadidx [c] {sym} (ADDconst [d] ptr) idx mem)
- // cond:
+ // cond: is20Bit(c+d)
// result: (FMOVSloadidx [c+d] {sym} ptr idx mem)
for {
c := v.AuxInt
ptr := v_0.Args[0]
idx := v.Args[1]
mem := v.Args[2]
+ if !(is20Bit(c + d)) {
+ break
+ }
v.reset(OpS390XFMOVSloadidx)
v.AuxInt = c + d
v.Aux = sym
return true
}
// match: (FMOVSloadidx [c] {sym} ptr (ADDconst [d] idx) mem)
- // cond:
+ // cond: is20Bit(c+d)
// result: (FMOVSloadidx [c+d] {sym} ptr idx mem)
for {
c := v.AuxInt
d := v_1.AuxInt
idx := v_1.Args[0]
mem := v.Args[2]
+ if !(is20Bit(c + d)) {
+ break
+ }
v.reset(OpS390XFMOVSloadidx)
v.AuxInt = c + d
v.Aux = sym
}
func rewriteValueS390X_OpS390XFMOVSstoreidx_0(v *Value) bool {
// match: (FMOVSstoreidx [c] {sym} (ADDconst [d] ptr) idx val mem)
- // cond:
+ // cond: is20Bit(c+d)
// result: (FMOVSstoreidx [c+d] {sym} ptr idx val mem)
for {
c := v.AuxInt
idx := v.Args[1]
val := v.Args[2]
mem := v.Args[3]
+ if !(is20Bit(c + d)) {
+ break
+ }
v.reset(OpS390XFMOVSstoreidx)
v.AuxInt = c + d
v.Aux = sym
return true
}
// match: (FMOVSstoreidx [c] {sym} ptr (ADDconst [d] idx) val mem)
- // cond:
+ // cond: is20Bit(c+d)
// result: (FMOVSstoreidx [c+d] {sym} ptr idx val mem)
for {
c := v.AuxInt
idx := v_1.Args[0]
val := v.Args[2]
mem := v.Args[3]
+ if !(is20Bit(c + d)) {
+ break
+ }
v.reset(OpS390XFMOVSstoreidx)
v.AuxInt = c + d
v.Aux = sym
}
func rewriteValueS390X_OpS390XMOVBZloadidx_0(v *Value) bool {
// match: (MOVBZloadidx [c] {sym} (ADDconst [d] ptr) idx mem)
- // cond:
+ // cond: is20Bit(c+d)
// result: (MOVBZloadidx [c+d] {sym} ptr idx mem)
for {
c := v.AuxInt
ptr := v_0.Args[0]
idx := v.Args[1]
mem := v.Args[2]
+ if !(is20Bit(c + d)) {
+ break
+ }
v.reset(OpS390XMOVBZloadidx)
v.AuxInt = c + d
v.Aux = sym
return true
}
// match: (MOVBZloadidx [c] {sym} idx (ADDconst [d] ptr) mem)
- // cond:
+ // cond: is20Bit(c+d)
// result: (MOVBZloadidx [c+d] {sym} ptr idx mem)
for {
c := v.AuxInt
d := v_1.AuxInt
ptr := v_1.Args[0]
mem := v.Args[2]
+ if !(is20Bit(c + d)) {
+ break
+ }
v.reset(OpS390XMOVBZloadidx)
v.AuxInt = c + d
v.Aux = sym
return true
}
// match: (MOVBZloadidx [c] {sym} ptr (ADDconst [d] idx) mem)
- // cond:
+ // cond: is20Bit(c+d)
// result: (MOVBZloadidx [c+d] {sym} ptr idx mem)
for {
c := v.AuxInt
d := v_1.AuxInt
idx := v_1.Args[0]
mem := v.Args[2]
+ if !(is20Bit(c + d)) {
+ break
+ }
v.reset(OpS390XMOVBZloadidx)
v.AuxInt = c + d
v.Aux = sym
return true
}
// match: (MOVBZloadidx [c] {sym} (ADDconst [d] idx) ptr mem)
- // cond:
+ // cond: is20Bit(c+d)
// result: (MOVBZloadidx [c+d] {sym} ptr idx mem)
for {
c := v.AuxInt
idx := v_0.Args[0]
ptr := v.Args[1]
mem := v.Args[2]
+ if !(is20Bit(c + d)) {
+ break
+ }
v.reset(OpS390XMOVBZloadidx)
v.AuxInt = c + d
v.Aux = sym
v0.AddArg(mem)
return true
}
+ // match: (MOVBZreg x:(MOVBload [off] {sym} ptr mem))
+ // cond: x.Uses == 1 && clobber(x)
+ // result: @x.Block (MOVBZload <v.Type> [off] {sym} ptr mem)
+ for {
+ x := v.Args[0]
+ if x.Op != OpS390XMOVBload {
+ break
+ }
+ off := x.AuxInt
+ sym := x.Aux
+ _ = x.Args[1]
+ ptr := x.Args[0]
+ mem := x.Args[1]
+ if !(x.Uses == 1 && clobber(x)) {
+ break
+ }
+ b = x.Block
+ v0 := b.NewValue0(v.Pos, OpS390XMOVBZload, v.Type)
+ v.reset(OpCopy)
+ v.AddArg(v0)
+ v0.AuxInt = off
+ v0.Aux = sym
+ v0.AddArg(ptr)
+ v0.AddArg(mem)
+ return true
+ }
// match: (MOVBZreg x:(MOVBZloadidx [off] {sym} ptr idx mem))
// cond: x.Uses == 1 && clobber(x)
// result: @x.Block (MOVBZloadidx <v.Type> [off] {sym} ptr idx mem)
v0.AddArg(mem)
return true
}
+ // match: (MOVBZreg x:(MOVBloadidx [off] {sym} ptr idx mem))
+ // cond: x.Uses == 1 && clobber(x)
+ // result: @x.Block (MOVBZloadidx <v.Type> [off] {sym} ptr idx mem)
+ for {
+ x := v.Args[0]
+ if x.Op != OpS390XMOVBloadidx {
+ break
+ }
+ off := x.AuxInt
+ sym := x.Aux
+ _ = x.Args[2]
+ ptr := x.Args[0]
+ idx := x.Args[1]
+ mem := x.Args[2]
+ if !(x.Uses == 1 && clobber(x)) {
+ break
+ }
+ b = x.Block
+ v0 := b.NewValue0(v.Pos, OpS390XMOVBZloadidx, v.Type)
+ v.reset(OpCopy)
+ v.AddArg(v0)
+ v0.AuxInt = off
+ v0.Aux = sym
+ v0.AddArg(ptr)
+ v0.AddArg(idx)
+ v0.AddArg(mem)
+ return true
+ }
return false
}
func rewriteValueS390X_OpS390XMOVBload_0(v *Value) bool {
v.AddArg(mem)
return true
}
+ // match: (MOVBload [off1] {sym1} (MOVDaddridx [off2] {sym2} ptr idx) mem)
+ // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2)
+ // result: (MOVBloadidx [off1+off2] {mergeSym(sym1,sym2)} ptr idx mem)
+ for {
+ off1 := v.AuxInt
+ sym1 := v.Aux
+ _ = v.Args[1]
+ v_0 := v.Args[0]
+ if v_0.Op != OpS390XMOVDaddridx {
+ break
+ }
+ off2 := v_0.AuxInt
+ sym2 := v_0.Aux
+ _ = v_0.Args[1]
+ ptr := v_0.Args[0]
+ idx := v_0.Args[1]
+ mem := v.Args[1]
+ if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) {
+ break
+ }
+ v.reset(OpS390XMOVBloadidx)
+ v.AuxInt = off1 + off2
+ v.Aux = mergeSym(sym1, sym2)
+ v.AddArg(ptr)
+ v.AddArg(idx)
+ v.AddArg(mem)
+ return true
+ }
+ // match: (MOVBload [off] {sym} (ADD ptr idx) mem)
+ // cond: ptr.Op != OpSB
+ // result: (MOVBloadidx [off] {sym} ptr idx mem)
+ for {
+ off := v.AuxInt
+ sym := v.Aux
+ _ = v.Args[1]
+ v_0 := v.Args[0]
+ if v_0.Op != OpS390XADD {
+ break
+ }
+ _ = v_0.Args[1]
+ ptr := v_0.Args[0]
+ idx := v_0.Args[1]
+ mem := v.Args[1]
+ if !(ptr.Op != OpSB) {
+ break
+ }
+ v.reset(OpS390XMOVBloadidx)
+ v.AuxInt = off
+ v.Aux = sym
+ v.AddArg(ptr)
+ v.AddArg(idx)
+ v.AddArg(mem)
+ return true
+ }
+ return false
+}
+func rewriteValueS390X_OpS390XMOVBloadidx_0(v *Value) bool {
+ // match: (MOVBloadidx [c] {sym} (ADDconst [d] ptr) idx mem)
+ // cond: is20Bit(c+d)
+ // result: (MOVBloadidx [c+d] {sym} ptr idx mem)
+ for {
+ c := v.AuxInt
+ sym := v.Aux
+ _ = v.Args[2]
+ v_0 := v.Args[0]
+ if v_0.Op != OpS390XADDconst {
+ break
+ }
+ d := v_0.AuxInt
+ ptr := v_0.Args[0]
+ idx := v.Args[1]
+ mem := v.Args[2]
+ if !(is20Bit(c + d)) {
+ break
+ }
+ v.reset(OpS390XMOVBloadidx)
+ v.AuxInt = c + d
+ v.Aux = sym
+ v.AddArg(ptr)
+ v.AddArg(idx)
+ v.AddArg(mem)
+ return true
+ }
+ // match: (MOVBloadidx [c] {sym} idx (ADDconst [d] ptr) mem)
+ // cond: is20Bit(c+d)
+ // result: (MOVBloadidx [c+d] {sym} ptr idx mem)
+ for {
+ c := v.AuxInt
+ sym := v.Aux
+ _ = v.Args[2]
+ idx := v.Args[0]
+ v_1 := v.Args[1]
+ if v_1.Op != OpS390XADDconst {
+ break
+ }
+ d := v_1.AuxInt
+ ptr := v_1.Args[0]
+ mem := v.Args[2]
+ if !(is20Bit(c + d)) {
+ break
+ }
+ v.reset(OpS390XMOVBloadidx)
+ v.AuxInt = c + d
+ v.Aux = sym
+ v.AddArg(ptr)
+ v.AddArg(idx)
+ v.AddArg(mem)
+ return true
+ }
+ // match: (MOVBloadidx [c] {sym} ptr (ADDconst [d] idx) mem)
+ // cond: is20Bit(c+d)
+ // result: (MOVBloadidx [c+d] {sym} ptr idx mem)
+ for {
+ c := v.AuxInt
+ sym := v.Aux
+ _ = v.Args[2]
+ ptr := v.Args[0]
+ v_1 := v.Args[1]
+ if v_1.Op != OpS390XADDconst {
+ break
+ }
+ d := v_1.AuxInt
+ idx := v_1.Args[0]
+ mem := v.Args[2]
+ if !(is20Bit(c + d)) {
+ break
+ }
+ v.reset(OpS390XMOVBloadidx)
+ v.AuxInt = c + d
+ v.Aux = sym
+ v.AddArg(ptr)
+ v.AddArg(idx)
+ v.AddArg(mem)
+ return true
+ }
+ // match: (MOVBloadidx [c] {sym} (ADDconst [d] idx) ptr mem)
+ // cond: is20Bit(c+d)
+ // result: (MOVBloadidx [c+d] {sym} ptr idx mem)
+ for {
+ c := v.AuxInt
+ sym := v.Aux
+ _ = v.Args[2]
+ v_0 := v.Args[0]
+ if v_0.Op != OpS390XADDconst {
+ break
+ }
+ d := v_0.AuxInt
+ idx := v_0.Args[0]
+ ptr := v.Args[1]
+ mem := v.Args[2]
+ if !(is20Bit(c + d)) {
+ break
+ }
+ v.reset(OpS390XMOVBloadidx)
+ v.AuxInt = c + d
+ v.Aux = sym
+ v.AddArg(ptr)
+ v.AddArg(idx)
+ v.AddArg(mem)
+ return true
+ }
return false
}
func rewriteValueS390X_OpS390XMOVBreg_0(v *Value) bool {
}
// match: (MOVBreg x:(MOVBZload [off] {sym} ptr mem))
// cond: x.Uses == 1 && clobber(x)
- // result: @x.Block (MOVBload <v.Type> [off] {sym} ptr mem)
+ // result: @x.Block (MOVBload <v.Type> [off] {sym} ptr mem)
for {
x := v.Args[0]
if x.Op != OpS390XMOVBZload {
v0.AddArg(mem)
return true
}
- return false
-}
-func rewriteValueS390X_OpS390XMOVBstore_0(v *Value) bool {
+ // match: (MOVBreg x:(MOVBload [off] {sym} ptr mem))
+ // cond: x.Uses == 1 && clobber(x)
+ // result: @x.Block (MOVBload <v.Type> [off] {sym} ptr mem)
+ for {
+ x := v.Args[0]
+ if x.Op != OpS390XMOVBload {
+ break
+ }
+ off := x.AuxInt
+ sym := x.Aux
+ _ = x.Args[1]
+ ptr := x.Args[0]
+ mem := x.Args[1]
+ if !(x.Uses == 1 && clobber(x)) {
+ break
+ }
+ b = x.Block
+ v0 := b.NewValue0(v.Pos, OpS390XMOVBload, v.Type)
+ v.reset(OpCopy)
+ v.AddArg(v0)
+ v0.AuxInt = off
+ v0.Aux = sym
+ v0.AddArg(ptr)
+ v0.AddArg(mem)
+ return true
+ }
+ // match: (MOVBreg x:(MOVBZloadidx [off] {sym} ptr idx mem))
+ // cond: x.Uses == 1 && clobber(x)
+ // result: @x.Block (MOVBloadidx <v.Type> [off] {sym} ptr idx mem)
+ for {
+ x := v.Args[0]
+ if x.Op != OpS390XMOVBZloadidx {
+ break
+ }
+ off := x.AuxInt
+ sym := x.Aux
+ _ = x.Args[2]
+ ptr := x.Args[0]
+ idx := x.Args[1]
+ mem := x.Args[2]
+ if !(x.Uses == 1 && clobber(x)) {
+ break
+ }
+ b = x.Block
+ v0 := b.NewValue0(v.Pos, OpS390XMOVBloadidx, v.Type)
+ v.reset(OpCopy)
+ v.AddArg(v0)
+ v0.AuxInt = off
+ v0.Aux = sym
+ v0.AddArg(ptr)
+ v0.AddArg(idx)
+ v0.AddArg(mem)
+ return true
+ }
+ // match: (MOVBreg x:(MOVBloadidx [off] {sym} ptr idx mem))
+ // cond: x.Uses == 1 && clobber(x)
+ // result: @x.Block (MOVBloadidx <v.Type> [off] {sym} ptr idx mem)
+ for {
+ x := v.Args[0]
+ if x.Op != OpS390XMOVBloadidx {
+ break
+ }
+ off := x.AuxInt
+ sym := x.Aux
+ _ = x.Args[2]
+ ptr := x.Args[0]
+ idx := x.Args[1]
+ mem := x.Args[2]
+ if !(x.Uses == 1 && clobber(x)) {
+ break
+ }
+ b = x.Block
+ v0 := b.NewValue0(v.Pos, OpS390XMOVBloadidx, v.Type)
+ v.reset(OpCopy)
+ v.AddArg(v0)
+ v0.AuxInt = off
+ v0.Aux = sym
+ v0.AddArg(ptr)
+ v0.AddArg(idx)
+ v0.AddArg(mem)
+ return true
+ }
+ return false
+}
+func rewriteValueS390X_OpS390XMOVBstore_0(v *Value) bool {
// match: (MOVBstore [off] {sym} ptr (MOVBreg x) mem)
// cond:
// result: (MOVBstore [off] {sym} ptr x mem)
}
// match: (MOVBstore [off] {sym} (ADD ptr idx) val mem)
// cond: ptr.Op != OpSB
- // result: (MOVBstoreidx [off] {sym} ptr idx val mem)
+ // result: (MOVBstoreidx [off] {sym} ptr idx val mem)
for {
off := v.AuxInt
sym := v.Aux
}
func rewriteValueS390X_OpS390XMOVBstoreidx_0(v *Value) bool {
// match: (MOVBstoreidx [c] {sym} (ADDconst [d] ptr) idx val mem)
- // cond:
- // result: (MOVBstoreidx [c+d] {sym} ptr idx val mem)
+ // cond: is20Bit(c+d)
+ // result: (MOVBstoreidx [c+d] {sym} ptr idx val mem)
for {
c := v.AuxInt
sym := v.Aux
idx := v.Args[1]
val := v.Args[2]
mem := v.Args[3]
+ if !(is20Bit(c + d)) {
+ break
+ }
v.reset(OpS390XMOVBstoreidx)
v.AuxInt = c + d
v.Aux = sym
return true
}
// match: (MOVBstoreidx [c] {sym} idx (ADDconst [d] ptr) val mem)
- // cond:
- // result: (MOVBstoreidx [c+d] {sym} ptr idx val mem)
+ // cond: is20Bit(c+d)
+ // result: (MOVBstoreidx [c+d] {sym} ptr idx val mem)
for {
c := v.AuxInt
sym := v.Aux
ptr := v_1.Args[0]
val := v.Args[2]
mem := v.Args[3]
+ if !(is20Bit(c + d)) {
+ break
+ }
v.reset(OpS390XMOVBstoreidx)
v.AuxInt = c + d
v.Aux = sym
return true
}
// match: (MOVBstoreidx [c] {sym} ptr (ADDconst [d] idx) val mem)
- // cond:
- // result: (MOVBstoreidx [c+d] {sym} ptr idx val mem)
+ // cond: is20Bit(c+d)
+ // result: (MOVBstoreidx [c+d] {sym} ptr idx val mem)
for {
c := v.AuxInt
sym := v.Aux
idx := v_1.Args[0]
val := v.Args[2]
mem := v.Args[3]
+ if !(is20Bit(c + d)) {
+ break
+ }
v.reset(OpS390XMOVBstoreidx)
v.AuxInt = c + d
v.Aux = sym
return true
}
// match: (MOVBstoreidx [c] {sym} (ADDconst [d] idx) ptr val mem)
- // cond:
- // result: (MOVBstoreidx [c+d] {sym} ptr idx val mem)
+ // cond: is20Bit(c+d)
+ // result: (MOVBstoreidx [c+d] {sym} ptr idx val mem)
for {
c := v.AuxInt
sym := v.Aux
ptr := v.Args[1]
val := v.Args[2]
mem := v.Args[3]
+ if !(is20Bit(c + d)) {
+ break
+ }
v.reset(OpS390XMOVBstoreidx)
v.AuxInt = c + d
v.Aux = sym
}
// match: (MOVDload [off] {sym} (ADD ptr idx) mem)
// cond: ptr.Op != OpSB
- // result: (MOVDloadidx [off] {sym} ptr idx mem)
+ // result: (MOVDloadidx [off] {sym} ptr idx mem)
for {
off := v.AuxInt
sym := v.Aux
}
func rewriteValueS390X_OpS390XMOVDloadidx_0(v *Value) bool {
// match: (MOVDloadidx [c] {sym} (ADDconst [d] ptr) idx mem)
- // cond:
- // result: (MOVDloadidx [c+d] {sym} ptr idx mem)
+ // cond: is20Bit(c+d)
+ // result: (MOVDloadidx [c+d] {sym} ptr idx mem)
for {
c := v.AuxInt
sym := v.Aux
ptr := v_0.Args[0]
idx := v.Args[1]
mem := v.Args[2]
+ if !(is20Bit(c + d)) {
+ break
+ }
v.reset(OpS390XMOVDloadidx)
v.AuxInt = c + d
v.Aux = sym
return true
}
// match: (MOVDloadidx [c] {sym} idx (ADDconst [d] ptr) mem)
- // cond:
- // result: (MOVDloadidx [c+d] {sym} ptr idx mem)
+ // cond: is20Bit(c+d)
+ // result: (MOVDloadidx [c+d] {sym} ptr idx mem)
for {
c := v.AuxInt
sym := v.Aux
d := v_1.AuxInt
ptr := v_1.Args[0]
mem := v.Args[2]
+ if !(is20Bit(c + d)) {
+ break
+ }
v.reset(OpS390XMOVDloadidx)
v.AuxInt = c + d
v.Aux = sym
return true
}
// match: (MOVDloadidx [c] {sym} ptr (ADDconst [d] idx) mem)
- // cond:
- // result: (MOVDloadidx [c+d] {sym} ptr idx mem)
+ // cond: is20Bit(c+d)
+ // result: (MOVDloadidx [c+d] {sym} ptr idx mem)
for {
c := v.AuxInt
sym := v.Aux
d := v_1.AuxInt
idx := v_1.Args[0]
mem := v.Args[2]
+ if !(is20Bit(c + d)) {
+ break
+ }
v.reset(OpS390XMOVDloadidx)
v.AuxInt = c + d
v.Aux = sym
return true
}
// match: (MOVDloadidx [c] {sym} (ADDconst [d] idx) ptr mem)
- // cond:
- // result: (MOVDloadidx [c+d] {sym} ptr idx mem)
+ // cond: is20Bit(c+d)
+ // result: (MOVDloadidx [c+d] {sym} ptr idx mem)
for {
c := v.AuxInt
sym := v.Aux
idx := v_0.Args[0]
ptr := v.Args[1]
mem := v.Args[2]
+ if !(is20Bit(c + d)) {
+ break
+ }
v.reset(OpS390XMOVDloadidx)
v.AuxInt = c + d
v.Aux = sym
func rewriteValueS390X_OpS390XMOVDnop_10(v *Value) bool {
b := v.Block
_ = b
+ // match: (MOVDnop <t> x:(MOVBloadidx [off] {sym} ptr idx mem))
+ // cond: x.Uses == 1 && clobber(x)
+ // result: @x.Block (MOVBloadidx <t> [off] {sym} ptr idx mem)
+ for {
+ t := v.Type
+ x := v.Args[0]
+ if x.Op != OpS390XMOVBloadidx {
+ break
+ }
+ off := x.AuxInt
+ sym := x.Aux
+ _ = x.Args[2]
+ ptr := x.Args[0]
+ idx := x.Args[1]
+ mem := x.Args[2]
+ if !(x.Uses == 1 && clobber(x)) {
+ break
+ }
+ b = x.Block
+ v0 := b.NewValue0(v.Pos, OpS390XMOVBloadidx, t)
+ v.reset(OpCopy)
+ v.AddArg(v0)
+ v0.AuxInt = off
+ v0.Aux = sym
+ v0.AddArg(ptr)
+ v0.AddArg(idx)
+ v0.AddArg(mem)
+ return true
+ }
// match: (MOVDnop <t> x:(MOVHZloadidx [off] {sym} ptr idx mem))
// cond: x.Uses == 1 && clobber(x)
// result: @x.Block (MOVHZloadidx <t> [off] {sym} ptr idx mem)
v0.AddArg(mem)
return true
}
+ // match: (MOVDnop <t> x:(MOVHloadidx [off] {sym} ptr idx mem))
+ // cond: x.Uses == 1 && clobber(x)
+ // result: @x.Block (MOVHloadidx <t> [off] {sym} ptr idx mem)
+ for {
+ t := v.Type
+ x := v.Args[0]
+ if x.Op != OpS390XMOVHloadidx {
+ break
+ }
+ off := x.AuxInt
+ sym := x.Aux
+ _ = x.Args[2]
+ ptr := x.Args[0]
+ idx := x.Args[1]
+ mem := x.Args[2]
+ if !(x.Uses == 1 && clobber(x)) {
+ break
+ }
+ b = x.Block
+ v0 := b.NewValue0(v.Pos, OpS390XMOVHloadidx, t)
+ v.reset(OpCopy)
+ v.AddArg(v0)
+ v0.AuxInt = off
+ v0.Aux = sym
+ v0.AddArg(ptr)
+ v0.AddArg(idx)
+ v0.AddArg(mem)
+ return true
+ }
// match: (MOVDnop <t> x:(MOVWZloadidx [off] {sym} ptr idx mem))
// cond: x.Uses == 1 && clobber(x)
// result: @x.Block (MOVWZloadidx <t> [off] {sym} ptr idx mem)
v0.AddArg(mem)
return true
}
+ // match: (MOVDnop <t> x:(MOVWloadidx [off] {sym} ptr idx mem))
+ // cond: x.Uses == 1 && clobber(x)
+ // result: @x.Block (MOVWloadidx <t> [off] {sym} ptr idx mem)
+ for {
+ t := v.Type
+ x := v.Args[0]
+ if x.Op != OpS390XMOVWloadidx {
+ break
+ }
+ off := x.AuxInt
+ sym := x.Aux
+ _ = x.Args[2]
+ ptr := x.Args[0]
+ idx := x.Args[1]
+ mem := x.Args[2]
+ if !(x.Uses == 1 && clobber(x)) {
+ break
+ }
+ b = x.Block
+ v0 := b.NewValue0(v.Pos, OpS390XMOVWloadidx, t)
+ v.reset(OpCopy)
+ v.AddArg(v0)
+ v0.AuxInt = off
+ v0.Aux = sym
+ v0.AddArg(ptr)
+ v0.AddArg(idx)
+ v0.AddArg(mem)
+ return true
+ }
// match: (MOVDnop <t> x:(MOVDloadidx [off] {sym} ptr idx mem))
// cond: x.Uses == 1 && clobber(x)
// result: @x.Block (MOVDloadidx <t> [off] {sym} ptr idx mem)
v0.AddArg(mem)
return true
}
+ // match: (MOVDreg <t> x:(MOVBloadidx [off] {sym} ptr idx mem))
+ // cond: x.Uses == 1 && clobber(x)
+ // result: @x.Block (MOVBloadidx <t> [off] {sym} ptr idx mem)
+ for {
+ t := v.Type
+ x := v.Args[0]
+ if x.Op != OpS390XMOVBloadidx {
+ break
+ }
+ off := x.AuxInt
+ sym := x.Aux
+ _ = x.Args[2]
+ ptr := x.Args[0]
+ idx := x.Args[1]
+ mem := x.Args[2]
+ if !(x.Uses == 1 && clobber(x)) {
+ break
+ }
+ b = x.Block
+ v0 := b.NewValue0(v.Pos, OpS390XMOVBloadidx, t)
+ v.reset(OpCopy)
+ v.AddArg(v0)
+ v0.AuxInt = off
+ v0.Aux = sym
+ v0.AddArg(ptr)
+ v0.AddArg(idx)
+ v0.AddArg(mem)
+ return true
+ }
// match: (MOVDreg <t> x:(MOVHZloadidx [off] {sym} ptr idx mem))
// cond: x.Uses == 1 && clobber(x)
// result: @x.Block (MOVHZloadidx <t> [off] {sym} ptr idx mem)
v0.AddArg(mem)
return true
}
- // match: (MOVDreg <t> x:(MOVWZloadidx [off] {sym} ptr idx mem))
+ // match: (MOVDreg <t> x:(MOVHloadidx [off] {sym} ptr idx mem))
// cond: x.Uses == 1 && clobber(x)
- // result: @x.Block (MOVWZloadidx <t> [off] {sym} ptr idx mem)
+ // result: @x.Block (MOVHloadidx <t> [off] {sym} ptr idx mem)
for {
t := v.Type
x := v.Args[0]
- if x.Op != OpS390XMOVWZloadidx {
+ if x.Op != OpS390XMOVHloadidx {
break
}
off := x.AuxInt
break
}
b = x.Block
- v0 := b.NewValue0(v.Pos, OpS390XMOVWZloadidx, t)
+ v0 := b.NewValue0(v.Pos, OpS390XMOVHloadidx, t)
v.reset(OpCopy)
v.AddArg(v0)
v0.AuxInt = off
v0.AddArg(mem)
return true
}
- // match: (MOVDreg <t> x:(MOVDloadidx [off] {sym} ptr idx mem))
+ // match: (MOVDreg <t> x:(MOVWZloadidx [off] {sym} ptr idx mem))
// cond: x.Uses == 1 && clobber(x)
- // result: @x.Block (MOVDloadidx <t> [off] {sym} ptr idx mem)
+ // result: @x.Block (MOVWZloadidx <t> [off] {sym} ptr idx mem)
for {
t := v.Type
x := v.Args[0]
- if x.Op != OpS390XMOVDloadidx {
+ if x.Op != OpS390XMOVWZloadidx {
break
}
off := x.AuxInt
break
}
b = x.Block
- v0 := b.NewValue0(v.Pos, OpS390XMOVDloadidx, t)
+ v0 := b.NewValue0(v.Pos, OpS390XMOVWZloadidx, t)
v.reset(OpCopy)
v.AddArg(v0)
v0.AuxInt = off
v0.AddArg(mem)
return true
}
- return false
-}
-func rewriteValueS390X_OpS390XMOVDstore_0(v *Value) bool {
- // match: (MOVDstore [off1] {sym} (ADDconst [off2] ptr) val mem)
- // cond: is20Bit(off1+off2)
- // result: (MOVDstore [off1+off2] {sym} ptr val mem)
+ // match: (MOVDreg <t> x:(MOVWloadidx [off] {sym} ptr idx mem))
+ // cond: x.Uses == 1 && clobber(x)
+ // result: @x.Block (MOVWloadidx <t> [off] {sym} ptr idx mem)
for {
- off1 := v.AuxInt
- sym := v.Aux
- _ = v.Args[2]
- v_0 := v.Args[0]
- if v_0.Op != OpS390XADDconst {
+ t := v.Type
+ x := v.Args[0]
+ if x.Op != OpS390XMOVWloadidx {
break
}
- off2 := v_0.AuxInt
- ptr := v_0.Args[0]
- val := v.Args[1]
- mem := v.Args[2]
- if !(is20Bit(off1 + off2)) {
+ off := x.AuxInt
+ sym := x.Aux
+ _ = x.Args[2]
+ ptr := x.Args[0]
+ idx := x.Args[1]
+ mem := x.Args[2]
+ if !(x.Uses == 1 && clobber(x)) {
break
}
- v.reset(OpS390XMOVDstore)
- v.AuxInt = off1 + off2
+ b = x.Block
+ v0 := b.NewValue0(v.Pos, OpS390XMOVWloadidx, t)
+ v.reset(OpCopy)
+ v.AddArg(v0)
+ v0.AuxInt = off
+ v0.Aux = sym
+ v0.AddArg(ptr)
+ v0.AddArg(idx)
+ v0.AddArg(mem)
+ return true
+ }
+ // match: (MOVDreg <t> x:(MOVDloadidx [off] {sym} ptr idx mem))
+ // cond: x.Uses == 1 && clobber(x)
+ // result: @x.Block (MOVDloadidx <t> [off] {sym} ptr idx mem)
+ for {
+ t := v.Type
+ x := v.Args[0]
+ if x.Op != OpS390XMOVDloadidx {
+ break
+ }
+ off := x.AuxInt
+ sym := x.Aux
+ _ = x.Args[2]
+ ptr := x.Args[0]
+ idx := x.Args[1]
+ mem := x.Args[2]
+ if !(x.Uses == 1 && clobber(x)) {
+ break
+ }
+ b = x.Block
+ v0 := b.NewValue0(v.Pos, OpS390XMOVDloadidx, t)
+ v.reset(OpCopy)
+ v.AddArg(v0)
+ v0.AuxInt = off
+ v0.Aux = sym
+ v0.AddArg(ptr)
+ v0.AddArg(idx)
+ v0.AddArg(mem)
+ return true
+ }
+ return false
+}
+func rewriteValueS390X_OpS390XMOVDstore_0(v *Value) bool {
+ // match: (MOVDstore [off1] {sym} (ADDconst [off2] ptr) val mem)
+ // cond: is20Bit(off1+off2)
+ // result: (MOVDstore [off1+off2] {sym} ptr val mem)
+ for {
+ off1 := v.AuxInt
+ sym := v.Aux
+ _ = v.Args[2]
+ v_0 := v.Args[0]
+ if v_0.Op != OpS390XADDconst {
+ break
+ }
+ off2 := v_0.AuxInt
+ ptr := v_0.Args[0]
+ val := v.Args[1]
+ mem := v.Args[2]
+ if !(is20Bit(off1 + off2)) {
+ break
+ }
+ v.reset(OpS390XMOVDstore)
+ v.AuxInt = off1 + off2
v.Aux = sym
v.AddArg(ptr)
v.AddArg(val)
}
// match: (MOVDstore [off] {sym} (ADD ptr idx) val mem)
// cond: ptr.Op != OpSB
- // result: (MOVDstoreidx [off] {sym} ptr idx val mem)
+ // result: (MOVDstoreidx [off] {sym} ptr idx val mem)
for {
off := v.AuxInt
sym := v.Aux
}
func rewriteValueS390X_OpS390XMOVDstoreidx_0(v *Value) bool {
// match: (MOVDstoreidx [c] {sym} (ADDconst [d] ptr) idx val mem)
- // cond:
- // result: (MOVDstoreidx [c+d] {sym} ptr idx val mem)
+ // cond: is20Bit(c+d)
+ // result: (MOVDstoreidx [c+d] {sym} ptr idx val mem)
for {
c := v.AuxInt
sym := v.Aux
idx := v.Args[1]
val := v.Args[2]
mem := v.Args[3]
+ if !(is20Bit(c + d)) {
+ break
+ }
v.reset(OpS390XMOVDstoreidx)
v.AuxInt = c + d
v.Aux = sym
return true
}
// match: (MOVDstoreidx [c] {sym} idx (ADDconst [d] ptr) val mem)
- // cond:
- // result: (MOVDstoreidx [c+d] {sym} ptr idx val mem)
+ // cond: is20Bit(c+d)
+ // result: (MOVDstoreidx [c+d] {sym} ptr idx val mem)
for {
c := v.AuxInt
sym := v.Aux
ptr := v_1.Args[0]
val := v.Args[2]
mem := v.Args[3]
+ if !(is20Bit(c + d)) {
+ break
+ }
v.reset(OpS390XMOVDstoreidx)
v.AuxInt = c + d
v.Aux = sym
return true
}
// match: (MOVDstoreidx [c] {sym} ptr (ADDconst [d] idx) val mem)
- // cond:
- // result: (MOVDstoreidx [c+d] {sym} ptr idx val mem)
+ // cond: is20Bit(c+d)
+ // result: (MOVDstoreidx [c+d] {sym} ptr idx val mem)
for {
c := v.AuxInt
sym := v.Aux
idx := v_1.Args[0]
val := v.Args[2]
mem := v.Args[3]
+ if !(is20Bit(c + d)) {
+ break
+ }
v.reset(OpS390XMOVDstoreidx)
v.AuxInt = c + d
v.Aux = sym
return true
}
// match: (MOVDstoreidx [c] {sym} (ADDconst [d] idx) ptr val mem)
- // cond:
- // result: (MOVDstoreidx [c+d] {sym} ptr idx val mem)
+ // cond: is20Bit(c+d)
+ // result: (MOVDstoreidx [c+d] {sym} ptr idx val mem)
for {
c := v.AuxInt
sym := v.Aux
ptr := v.Args[1]
val := v.Args[2]
mem := v.Args[3]
+ if !(is20Bit(c + d)) {
+ break
+ }
v.reset(OpS390XMOVDstoreidx)
v.AuxInt = c + d
v.Aux = sym
}
func rewriteValueS390X_OpS390XMOVHZloadidx_0(v *Value) bool {
// match: (MOVHZloadidx [c] {sym} (ADDconst [d] ptr) idx mem)
- // cond:
+ // cond: is20Bit(c+d)
// result: (MOVHZloadidx [c+d] {sym} ptr idx mem)
for {
c := v.AuxInt
ptr := v_0.Args[0]
idx := v.Args[1]
mem := v.Args[2]
+ if !(is20Bit(c + d)) {
+ break
+ }
v.reset(OpS390XMOVHZloadidx)
v.AuxInt = c + d
v.Aux = sym
return true
}
// match: (MOVHZloadidx [c] {sym} idx (ADDconst [d] ptr) mem)
- // cond:
+ // cond: is20Bit(c+d)
// result: (MOVHZloadidx [c+d] {sym} ptr idx mem)
for {
c := v.AuxInt
d := v_1.AuxInt
ptr := v_1.Args[0]
mem := v.Args[2]
+ if !(is20Bit(c + d)) {
+ break
+ }
v.reset(OpS390XMOVHZloadidx)
v.AuxInt = c + d
v.Aux = sym
return true
}
// match: (MOVHZloadidx [c] {sym} ptr (ADDconst [d] idx) mem)
- // cond:
+ // cond: is20Bit(c+d)
// result: (MOVHZloadidx [c+d] {sym} ptr idx mem)
for {
c := v.AuxInt
d := v_1.AuxInt
idx := v_1.Args[0]
mem := v.Args[2]
+ if !(is20Bit(c + d)) {
+ break
+ }
v.reset(OpS390XMOVHZloadidx)
v.AuxInt = c + d
v.Aux = sym
return true
}
// match: (MOVHZloadidx [c] {sym} (ADDconst [d] idx) ptr mem)
- // cond:
+ // cond: is20Bit(c+d)
// result: (MOVHZloadidx [c+d] {sym} ptr idx mem)
for {
c := v.AuxInt
idx := v_0.Args[0]
ptr := v.Args[1]
mem := v.Args[2]
+ if !(is20Bit(c + d)) {
+ break
+ }
v.reset(OpS390XMOVHZloadidx)
v.AuxInt = c + d
v.Aux = sym
v0.AddArg(mem)
return true
}
+ // match: (MOVHZreg x:(MOVHload [off] {sym} ptr mem))
+ // cond: x.Uses == 1 && clobber(x)
+ // result: @x.Block (MOVHZload <v.Type> [off] {sym} ptr mem)
+ for {
+ x := v.Args[0]
+ if x.Op != OpS390XMOVHload {
+ break
+ }
+ off := x.AuxInt
+ sym := x.Aux
+ _ = x.Args[1]
+ ptr := x.Args[0]
+ mem := x.Args[1]
+ if !(x.Uses == 1 && clobber(x)) {
+ break
+ }
+ b = x.Block
+ v0 := b.NewValue0(v.Pos, OpS390XMOVHZload, v.Type)
+ v.reset(OpCopy)
+ v.AddArg(v0)
+ v0.AuxInt = off
+ v0.Aux = sym
+ v0.AddArg(ptr)
+ v0.AddArg(mem)
+ return true
+ }
// match: (MOVHZreg x:(MOVHZloadidx [off] {sym} ptr idx mem))
// cond: x.Uses == 1 && clobber(x)
// result: @x.Block (MOVHZloadidx <v.Type> [off] {sym} ptr idx mem)
v0.AddArg(mem)
return true
}
+ // match: (MOVHZreg x:(MOVHloadidx [off] {sym} ptr idx mem))
+ // cond: x.Uses == 1 && clobber(x)
+ // result: @x.Block (MOVHZloadidx <v.Type> [off] {sym} ptr idx mem)
+ for {
+ x := v.Args[0]
+ if x.Op != OpS390XMOVHloadidx {
+ break
+ }
+ off := x.AuxInt
+ sym := x.Aux
+ _ = x.Args[2]
+ ptr := x.Args[0]
+ idx := x.Args[1]
+ mem := x.Args[2]
+ if !(x.Uses == 1 && clobber(x)) {
+ break
+ }
+ b = x.Block
+ v0 := b.NewValue0(v.Pos, OpS390XMOVHZloadidx, v.Type)
+ v.reset(OpCopy)
+ v.AddArg(v0)
+ v0.AuxInt = off
+ v0.Aux = sym
+ v0.AddArg(ptr)
+ v0.AddArg(idx)
+ v0.AddArg(mem)
+ return true
+ }
return false
}
func rewriteValueS390X_OpS390XMOVHload_0(v *Value) bool {
v.AddArg(mem)
return true
}
- return false
-}
-func rewriteValueS390X_OpS390XMOVHreg_0(v *Value) bool {
- b := v.Block
- _ = b
- // match: (MOVHreg x:(MOVBload _ _))
- // cond:
- // result: (MOVDreg x)
+ // match: (MOVHload [off1] {sym1} (MOVDaddridx [off2] {sym2} ptr idx) mem)
+ // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2)
+ // result: (MOVHloadidx [off1+off2] {mergeSym(sym1,sym2)} ptr idx mem)
for {
- x := v.Args[0]
- if x.Op != OpS390XMOVBload {
+ off1 := v.AuxInt
+ sym1 := v.Aux
+ _ = v.Args[1]
+ v_0 := v.Args[0]
+ if v_0.Op != OpS390XMOVDaddridx {
break
}
- _ = x.Args[1]
- v.reset(OpS390XMOVDreg)
- v.AddArg(x)
- return true
- }
- // match: (MOVHreg x:(MOVBZload _ _))
- // cond:
- // result: (MOVDreg x)
- for {
- x := v.Args[0]
- if x.Op != OpS390XMOVBZload {
+ off2 := v_0.AuxInt
+ sym2 := v_0.Aux
+ _ = v_0.Args[1]
+ ptr := v_0.Args[0]
+ idx := v_0.Args[1]
+ mem := v.Args[1]
+ if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) {
break
}
- _ = x.Args[1]
- v.reset(OpS390XMOVDreg)
- v.AddArg(x)
+ v.reset(OpS390XMOVHloadidx)
+ v.AuxInt = off1 + off2
+ v.Aux = mergeSym(sym1, sym2)
+ v.AddArg(ptr)
+ v.AddArg(idx)
+ v.AddArg(mem)
return true
}
- // match: (MOVHreg x:(MOVHload _ _))
- // cond:
- // result: (MOVDreg x)
+ // match: (MOVHload [off] {sym} (ADD ptr idx) mem)
+ // cond: ptr.Op != OpSB
+ // result: (MOVHloadidx [off] {sym} ptr idx mem)
for {
- x := v.Args[0]
- if x.Op != OpS390XMOVHload {
+ off := v.AuxInt
+ sym := v.Aux
+ _ = v.Args[1]
+ v_0 := v.Args[0]
+ if v_0.Op != OpS390XADD {
break
}
- _ = x.Args[1]
- v.reset(OpS390XMOVDreg)
- v.AddArg(x)
+ _ = v_0.Args[1]
+ ptr := v_0.Args[0]
+ idx := v_0.Args[1]
+ mem := v.Args[1]
+ if !(ptr.Op != OpSB) {
+ break
+ }
+ v.reset(OpS390XMOVHloadidx)
+ v.AuxInt = off
+ v.Aux = sym
+ v.AddArg(ptr)
+ v.AddArg(idx)
+ v.AddArg(mem)
return true
}
- // match: (MOVHreg x:(Arg <t>))
- // cond: (is8BitInt(t) || is16BitInt(t)) && isSigned(t)
- // result: (MOVDreg x)
+ return false
+}
+func rewriteValueS390X_OpS390XMOVHloadidx_0(v *Value) bool {
+ // match: (MOVHloadidx [c] {sym} (ADDconst [d] ptr) idx mem)
+ // cond: is20Bit(c+d)
+ // result: (MOVHloadidx [c+d] {sym} ptr idx mem)
for {
- x := v.Args[0]
- if x.Op != OpArg {
+ c := v.AuxInt
+ sym := v.Aux
+ _ = v.Args[2]
+ v_0 := v.Args[0]
+ if v_0.Op != OpS390XADDconst {
break
}
- t := x.Type
- if !((is8BitInt(t) || is16BitInt(t)) && isSigned(t)) {
+ d := v_0.AuxInt
+ ptr := v_0.Args[0]
+ idx := v.Args[1]
+ mem := v.Args[2]
+ if !(is20Bit(c + d)) {
break
}
- v.reset(OpS390XMOVDreg)
- v.AddArg(x)
+ v.reset(OpS390XMOVHloadidx)
+ v.AuxInt = c + d
+ v.Aux = sym
+ v.AddArg(ptr)
+ v.AddArg(idx)
+ v.AddArg(mem)
return true
}
- // match: (MOVHreg x:(MOVBreg _))
- // cond:
- // result: (MOVDreg x)
+ // match: (MOVHloadidx [c] {sym} idx (ADDconst [d] ptr) mem)
+ // cond: is20Bit(c+d)
+ // result: (MOVHloadidx [c+d] {sym} ptr idx mem)
for {
- x := v.Args[0]
- if x.Op != OpS390XMOVBreg {
- break
- }
+ c := v.AuxInt
+ sym := v.Aux
+ _ = v.Args[2]
+ idx := v.Args[0]
+ v_1 := v.Args[1]
+ if v_1.Op != OpS390XADDconst {
+ break
+ }
+ d := v_1.AuxInt
+ ptr := v_1.Args[0]
+ mem := v.Args[2]
+ if !(is20Bit(c + d)) {
+ break
+ }
+ v.reset(OpS390XMOVHloadidx)
+ v.AuxInt = c + d
+ v.Aux = sym
+ v.AddArg(ptr)
+ v.AddArg(idx)
+ v.AddArg(mem)
+ return true
+ }
+ // match: (MOVHloadidx [c] {sym} ptr (ADDconst [d] idx) mem)
+ // cond: is20Bit(c+d)
+ // result: (MOVHloadidx [c+d] {sym} ptr idx mem)
+ for {
+ c := v.AuxInt
+ sym := v.Aux
+ _ = v.Args[2]
+ ptr := v.Args[0]
+ v_1 := v.Args[1]
+ if v_1.Op != OpS390XADDconst {
+ break
+ }
+ d := v_1.AuxInt
+ idx := v_1.Args[0]
+ mem := v.Args[2]
+ if !(is20Bit(c + d)) {
+ break
+ }
+ v.reset(OpS390XMOVHloadidx)
+ v.AuxInt = c + d
+ v.Aux = sym
+ v.AddArg(ptr)
+ v.AddArg(idx)
+ v.AddArg(mem)
+ return true
+ }
+ // match: (MOVHloadidx [c] {sym} (ADDconst [d] idx) ptr mem)
+ // cond: is20Bit(c+d)
+ // result: (MOVHloadidx [c+d] {sym} ptr idx mem)
+ for {
+ c := v.AuxInt
+ sym := v.Aux
+ _ = v.Args[2]
+ v_0 := v.Args[0]
+ if v_0.Op != OpS390XADDconst {
+ break
+ }
+ d := v_0.AuxInt
+ idx := v_0.Args[0]
+ ptr := v.Args[1]
+ mem := v.Args[2]
+ if !(is20Bit(c + d)) {
+ break
+ }
+ v.reset(OpS390XMOVHloadidx)
+ v.AuxInt = c + d
+ v.Aux = sym
+ v.AddArg(ptr)
+ v.AddArg(idx)
+ v.AddArg(mem)
+ return true
+ }
+ return false
+}
+func rewriteValueS390X_OpS390XMOVHreg_0(v *Value) bool {
+ b := v.Block
+ _ = b
+ // match: (MOVHreg x:(MOVBload _ _))
+ // cond:
+ // result: (MOVDreg x)
+ for {
+ x := v.Args[0]
+ if x.Op != OpS390XMOVBload {
+ break
+ }
+ _ = x.Args[1]
+ v.reset(OpS390XMOVDreg)
+ v.AddArg(x)
+ return true
+ }
+ // match: (MOVHreg x:(MOVBZload _ _))
+ // cond:
+ // result: (MOVDreg x)
+ for {
+ x := v.Args[0]
+ if x.Op != OpS390XMOVBZload {
+ break
+ }
+ _ = x.Args[1]
+ v.reset(OpS390XMOVDreg)
+ v.AddArg(x)
+ return true
+ }
+ // match: (MOVHreg x:(MOVHload _ _))
+ // cond:
+ // result: (MOVDreg x)
+ for {
+ x := v.Args[0]
+ if x.Op != OpS390XMOVHload {
+ break
+ }
+ _ = x.Args[1]
+ v.reset(OpS390XMOVDreg)
+ v.AddArg(x)
+ return true
+ }
+ // match: (MOVHreg x:(Arg <t>))
+ // cond: (is8BitInt(t) || is16BitInt(t)) && isSigned(t)
+ // result: (MOVDreg x)
+ for {
+ x := v.Args[0]
+ if x.Op != OpArg {
+ break
+ }
+ t := x.Type
+ if !((is8BitInt(t) || is16BitInt(t)) && isSigned(t)) {
+ break
+ }
+ v.reset(OpS390XMOVDreg)
+ v.AddArg(x)
+ return true
+ }
+ // match: (MOVHreg x:(MOVBreg _))
+ // cond:
+ // result: (MOVDreg x)
+ for {
+ x := v.Args[0]
+ if x.Op != OpS390XMOVBreg {
+ break
+ }
v.reset(OpS390XMOVDreg)
v.AddArg(x)
return true
}
// match: (MOVHreg x:(MOVHZload [off] {sym} ptr mem))
// cond: x.Uses == 1 && clobber(x)
- // result: @x.Block (MOVHload <v.Type> [off] {sym} ptr mem)
+ // result: @x.Block (MOVHload <v.Type> [off] {sym} ptr mem)
for {
x := v.Args[0]
if x.Op != OpS390XMOVHZload {
v0.AddArg(mem)
return true
}
+ // match: (MOVHreg x:(MOVHload [off] {sym} ptr mem))
+ // cond: x.Uses == 1 && clobber(x)
+ // result: @x.Block (MOVHload <v.Type> [off] {sym} ptr mem)
+ for {
+ x := v.Args[0]
+ if x.Op != OpS390XMOVHload {
+ break
+ }
+ off := x.AuxInt
+ sym := x.Aux
+ _ = x.Args[1]
+ ptr := x.Args[0]
+ mem := x.Args[1]
+ if !(x.Uses == 1 && clobber(x)) {
+ break
+ }
+ b = x.Block
+ v0 := b.NewValue0(v.Pos, OpS390XMOVHload, v.Type)
+ v.reset(OpCopy)
+ v.AddArg(v0)
+ v0.AuxInt = off
+ v0.Aux = sym
+ v0.AddArg(ptr)
+ v0.AddArg(mem)
+ return true
+ }
+ return false
+}
+func rewriteValueS390X_OpS390XMOVHreg_10(v *Value) bool {
+ b := v.Block
+ _ = b
+ // match: (MOVHreg x:(MOVHZloadidx [off] {sym} ptr idx mem))
+ // cond: x.Uses == 1 && clobber(x)
+ // result: @x.Block (MOVHloadidx <v.Type> [off] {sym} ptr idx mem)
+ for {
+ x := v.Args[0]
+ if x.Op != OpS390XMOVHZloadidx {
+ break
+ }
+ off := x.AuxInt
+ sym := x.Aux
+ _ = x.Args[2]
+ ptr := x.Args[0]
+ idx := x.Args[1]
+ mem := x.Args[2]
+ if !(x.Uses == 1 && clobber(x)) {
+ break
+ }
+ b = x.Block
+ v0 := b.NewValue0(v.Pos, OpS390XMOVHloadidx, v.Type)
+ v.reset(OpCopy)
+ v.AddArg(v0)
+ v0.AuxInt = off
+ v0.Aux = sym
+ v0.AddArg(ptr)
+ v0.AddArg(idx)
+ v0.AddArg(mem)
+ return true
+ }
+ // match: (MOVHreg x:(MOVHloadidx [off] {sym} ptr idx mem))
+ // cond: x.Uses == 1 && clobber(x)
+ // result: @x.Block (MOVHloadidx <v.Type> [off] {sym} ptr idx mem)
+ for {
+ x := v.Args[0]
+ if x.Op != OpS390XMOVHloadidx {
+ break
+ }
+ off := x.AuxInt
+ sym := x.Aux
+ _ = x.Args[2]
+ ptr := x.Args[0]
+ idx := x.Args[1]
+ mem := x.Args[2]
+ if !(x.Uses == 1 && clobber(x)) {
+ break
+ }
+ b = x.Block
+ v0 := b.NewValue0(v.Pos, OpS390XMOVHloadidx, v.Type)
+ v.reset(OpCopy)
+ v.AddArg(v0)
+ v0.AuxInt = off
+ v0.Aux = sym
+ v0.AddArg(ptr)
+ v0.AddArg(idx)
+ v0.AddArg(mem)
+ return true
+ }
return false
}
func rewriteValueS390X_OpS390XMOVHstore_0(v *Value) bool {
}
// match: (MOVHstore [off] {sym} (ADD ptr idx) val mem)
// cond: ptr.Op != OpSB
- // result: (MOVHstoreidx [off] {sym} ptr idx val mem)
+ // result: (MOVHstoreidx [off] {sym} ptr idx val mem)
for {
off := v.AuxInt
sym := v.Aux
}
func rewriteValueS390X_OpS390XMOVHstoreidx_0(v *Value) bool {
// match: (MOVHstoreidx [c] {sym} (ADDconst [d] ptr) idx val mem)
- // cond:
- // result: (MOVHstoreidx [c+d] {sym} ptr idx val mem)
+ // cond: is20Bit(c+d)
+ // result: (MOVHstoreidx [c+d] {sym} ptr idx val mem)
for {
c := v.AuxInt
sym := v.Aux
idx := v.Args[1]
val := v.Args[2]
mem := v.Args[3]
+ if !(is20Bit(c + d)) {
+ break
+ }
v.reset(OpS390XMOVHstoreidx)
v.AuxInt = c + d
v.Aux = sym
return true
}
// match: (MOVHstoreidx [c] {sym} idx (ADDconst [d] ptr) val mem)
- // cond:
- // result: (MOVHstoreidx [c+d] {sym} ptr idx val mem)
+ // cond: is20Bit(c+d)
+ // result: (MOVHstoreidx [c+d] {sym} ptr idx val mem)
for {
c := v.AuxInt
sym := v.Aux
ptr := v_1.Args[0]
val := v.Args[2]
mem := v.Args[3]
+ if !(is20Bit(c + d)) {
+ break
+ }
v.reset(OpS390XMOVHstoreidx)
v.AuxInt = c + d
v.Aux = sym
return true
}
// match: (MOVHstoreidx [c] {sym} ptr (ADDconst [d] idx) val mem)
- // cond:
- // result: (MOVHstoreidx [c+d] {sym} ptr idx val mem)
+ // cond: is20Bit(c+d)
+ // result: (MOVHstoreidx [c+d] {sym} ptr idx val mem)
for {
c := v.AuxInt
sym := v.Aux
idx := v_1.Args[0]
val := v.Args[2]
mem := v.Args[3]
+ if !(is20Bit(c + d)) {
+ break
+ }
v.reset(OpS390XMOVHstoreidx)
v.AuxInt = c + d
v.Aux = sym
return true
}
// match: (MOVHstoreidx [c] {sym} (ADDconst [d] idx) ptr val mem)
- // cond:
- // result: (MOVHstoreidx [c+d] {sym} ptr idx val mem)
+ // cond: is20Bit(c+d)
+ // result: (MOVHstoreidx [c+d] {sym} ptr idx val mem)
for {
c := v.AuxInt
sym := v.Aux
ptr := v.Args[1]
val := v.Args[2]
mem := v.Args[3]
+ if !(is20Bit(c + d)) {
+ break
+ }
v.reset(OpS390XMOVHstoreidx)
v.AuxInt = c + d
v.Aux = sym
}
func rewriteValueS390X_OpS390XMOVWZloadidx_0(v *Value) bool {
// match: (MOVWZloadidx [c] {sym} (ADDconst [d] ptr) idx mem)
- // cond:
+ // cond: is20Bit(c+d)
// result: (MOVWZloadidx [c+d] {sym} ptr idx mem)
for {
c := v.AuxInt
ptr := v_0.Args[0]
idx := v.Args[1]
mem := v.Args[2]
+ if !(is20Bit(c + d)) {
+ break
+ }
v.reset(OpS390XMOVWZloadidx)
v.AuxInt = c + d
v.Aux = sym
return true
}
// match: (MOVWZloadidx [c] {sym} idx (ADDconst [d] ptr) mem)
- // cond:
+ // cond: is20Bit(c+d)
// result: (MOVWZloadidx [c+d] {sym} ptr idx mem)
for {
c := v.AuxInt
d := v_1.AuxInt
ptr := v_1.Args[0]
mem := v.Args[2]
+ if !(is20Bit(c + d)) {
+ break
+ }
v.reset(OpS390XMOVWZloadidx)
v.AuxInt = c + d
v.Aux = sym
return true
}
// match: (MOVWZloadidx [c] {sym} ptr (ADDconst [d] idx) mem)
- // cond:
+ // cond: is20Bit(c+d)
// result: (MOVWZloadidx [c+d] {sym} ptr idx mem)
for {
c := v.AuxInt
d := v_1.AuxInt
idx := v_1.Args[0]
mem := v.Args[2]
+ if !(is20Bit(c + d)) {
+ break
+ }
v.reset(OpS390XMOVWZloadidx)
v.AuxInt = c + d
v.Aux = sym
return true
}
// match: (MOVWZloadidx [c] {sym} (ADDconst [d] idx) ptr mem)
- // cond:
+ // cond: is20Bit(c+d)
// result: (MOVWZloadidx [c+d] {sym} ptr idx mem)
for {
c := v.AuxInt
idx := v_0.Args[0]
ptr := v.Args[1]
mem := v.Args[2]
+ if !(is20Bit(c + d)) {
+ break
+ }
v.reset(OpS390XMOVWZloadidx)
v.AuxInt = c + d
v.Aux = sym
v0.AddArg(mem)
return true
}
- // match: (MOVWZreg x:(MOVWZloadidx [off] {sym} ptr idx mem))
+ // match: (MOVWZreg x:(MOVWload [off] {sym} ptr mem))
// cond: x.Uses == 1 && clobber(x)
- // result: @x.Block (MOVWZloadidx <v.Type> [off] {sym} ptr idx mem)
+ // result: @x.Block (MOVWZload <v.Type> [off] {sym} ptr mem)
for {
x := v.Args[0]
- if x.Op != OpS390XMOVWZloadidx {
+ if x.Op != OpS390XMOVWload {
+ break
+ }
+ off := x.AuxInt
+ sym := x.Aux
+ _ = x.Args[1]
+ ptr := x.Args[0]
+ mem := x.Args[1]
+ if !(x.Uses == 1 && clobber(x)) {
+ break
+ }
+ b = x.Block
+ v0 := b.NewValue0(v.Pos, OpS390XMOVWZload, v.Type)
+ v.reset(OpCopy)
+ v.AddArg(v0)
+ v0.AuxInt = off
+ v0.Aux = sym
+ v0.AddArg(ptr)
+ v0.AddArg(mem)
+ return true
+ }
+ return false
+}
+func rewriteValueS390X_OpS390XMOVWZreg_10(v *Value) bool {
+ b := v.Block
+ _ = b
+ // match: (MOVWZreg x:(MOVWZloadidx [off] {sym} ptr idx mem))
+ // cond: x.Uses == 1 && clobber(x)
+ // result: @x.Block (MOVWZloadidx <v.Type> [off] {sym} ptr idx mem)
+ for {
+ x := v.Args[0]
+ if x.Op != OpS390XMOVWZloadidx {
+ break
+ }
+ off := x.AuxInt
+ sym := x.Aux
+ _ = x.Args[2]
+ ptr := x.Args[0]
+ idx := x.Args[1]
+ mem := x.Args[2]
+ if !(x.Uses == 1 && clobber(x)) {
+ break
+ }
+ b = x.Block
+ v0 := b.NewValue0(v.Pos, OpS390XMOVWZloadidx, v.Type)
+ v.reset(OpCopy)
+ v.AddArg(v0)
+ v0.AuxInt = off
+ v0.Aux = sym
+ v0.AddArg(ptr)
+ v0.AddArg(idx)
+ v0.AddArg(mem)
+ return true
+ }
+ // match: (MOVWZreg x:(MOVWloadidx [off] {sym} ptr idx mem))
+ // cond: x.Uses == 1 && clobber(x)
+ // result: @x.Block (MOVWZloadidx <v.Type> [off] {sym} ptr idx mem)
+ for {
+ x := v.Args[0]
+ if x.Op != OpS390XMOVWloadidx {
break
}
off := x.AuxInt
v.AddArg(mem)
return true
}
+ // match: (MOVWload [off1] {sym1} (MOVDaddridx [off2] {sym2} ptr idx) mem)
+ // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2)
+ // result: (MOVWloadidx [off1+off2] {mergeSym(sym1,sym2)} ptr idx mem)
+ for {
+ off1 := v.AuxInt
+ sym1 := v.Aux
+ _ = v.Args[1]
+ v_0 := v.Args[0]
+ if v_0.Op != OpS390XMOVDaddridx {
+ break
+ }
+ off2 := v_0.AuxInt
+ sym2 := v_0.Aux
+ _ = v_0.Args[1]
+ ptr := v_0.Args[0]
+ idx := v_0.Args[1]
+ mem := v.Args[1]
+ if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) {
+ break
+ }
+ v.reset(OpS390XMOVWloadidx)
+ v.AuxInt = off1 + off2
+ v.Aux = mergeSym(sym1, sym2)
+ v.AddArg(ptr)
+ v.AddArg(idx)
+ v.AddArg(mem)
+ return true
+ }
+ // match: (MOVWload [off] {sym} (ADD ptr idx) mem)
+ // cond: ptr.Op != OpSB
+ // result: (MOVWloadidx [off] {sym} ptr idx mem)
+ for {
+ off := v.AuxInt
+ sym := v.Aux
+ _ = v.Args[1]
+ v_0 := v.Args[0]
+ if v_0.Op != OpS390XADD {
+ break
+ }
+ _ = v_0.Args[1]
+ ptr := v_0.Args[0]
+ idx := v_0.Args[1]
+ mem := v.Args[1]
+ if !(ptr.Op != OpSB) {
+ break
+ }
+ v.reset(OpS390XMOVWloadidx)
+ v.AuxInt = off
+ v.Aux = sym
+ v.AddArg(ptr)
+ v.AddArg(idx)
+ v.AddArg(mem)
+ return true
+ }
+ return false
+}
+func rewriteValueS390X_OpS390XMOVWloadidx_0(v *Value) bool {
+ // match: (MOVWloadidx [c] {sym} (ADDconst [d] ptr) idx mem)
+ // cond: is20Bit(c+d)
+ // result: (MOVWloadidx [c+d] {sym} ptr idx mem)
+ for {
+ c := v.AuxInt
+ sym := v.Aux
+ _ = v.Args[2]
+ v_0 := v.Args[0]
+ if v_0.Op != OpS390XADDconst {
+ break
+ }
+ d := v_0.AuxInt
+ ptr := v_0.Args[0]
+ idx := v.Args[1]
+ mem := v.Args[2]
+ if !(is20Bit(c + d)) {
+ break
+ }
+ v.reset(OpS390XMOVWloadidx)
+ v.AuxInt = c + d
+ v.Aux = sym
+ v.AddArg(ptr)
+ v.AddArg(idx)
+ v.AddArg(mem)
+ return true
+ }
+ // match: (MOVWloadidx [c] {sym} idx (ADDconst [d] ptr) mem)
+ // cond: is20Bit(c+d)
+ // result: (MOVWloadidx [c+d] {sym} ptr idx mem)
+ for {
+ c := v.AuxInt
+ sym := v.Aux
+ _ = v.Args[2]
+ idx := v.Args[0]
+ v_1 := v.Args[1]
+ if v_1.Op != OpS390XADDconst {
+ break
+ }
+ d := v_1.AuxInt
+ ptr := v_1.Args[0]
+ mem := v.Args[2]
+ if !(is20Bit(c + d)) {
+ break
+ }
+ v.reset(OpS390XMOVWloadidx)
+ v.AuxInt = c + d
+ v.Aux = sym
+ v.AddArg(ptr)
+ v.AddArg(idx)
+ v.AddArg(mem)
+ return true
+ }
+ // match: (MOVWloadidx [c] {sym} ptr (ADDconst [d] idx) mem)
+ // cond: is20Bit(c+d)
+ // result: (MOVWloadidx [c+d] {sym} ptr idx mem)
+ for {
+ c := v.AuxInt
+ sym := v.Aux
+ _ = v.Args[2]
+ ptr := v.Args[0]
+ v_1 := v.Args[1]
+ if v_1.Op != OpS390XADDconst {
+ break
+ }
+ d := v_1.AuxInt
+ idx := v_1.Args[0]
+ mem := v.Args[2]
+ if !(is20Bit(c + d)) {
+ break
+ }
+ v.reset(OpS390XMOVWloadidx)
+ v.AuxInt = c + d
+ v.Aux = sym
+ v.AddArg(ptr)
+ v.AddArg(idx)
+ v.AddArg(mem)
+ return true
+ }
+ // match: (MOVWloadidx [c] {sym} (ADDconst [d] idx) ptr mem)
+ // cond: is20Bit(c+d)
+ // result: (MOVWloadidx [c+d] {sym} ptr idx mem)
+ for {
+ c := v.AuxInt
+ sym := v.Aux
+ _ = v.Args[2]
+ v_0 := v.Args[0]
+ if v_0.Op != OpS390XADDconst {
+ break
+ }
+ d := v_0.AuxInt
+ idx := v_0.Args[0]
+ ptr := v.Args[1]
+ mem := v.Args[2]
+ if !(is20Bit(c + d)) {
+ break
+ }
+ v.reset(OpS390XMOVWloadidx)
+ v.AuxInt = c + d
+ v.Aux = sym
+ v.AddArg(ptr)
+ v.AddArg(idx)
+ v.AddArg(mem)
+ return true
+ }
return false
}
func rewriteValueS390X_OpS390XMOVWreg_0(v *Value) bool {
}
// match: (MOVWreg x:(MOVWZload [off] {sym} ptr mem))
// cond: x.Uses == 1 && clobber(x)
- // result: @x.Block (MOVWload <v.Type> [off] {sym} ptr mem)
+ // result: @x.Block (MOVWload <v.Type> [off] {sym} ptr mem)
for {
x := v.Args[0]
if x.Op != OpS390XMOVWZload {
v0.AddArg(mem)
return true
}
+ // match: (MOVWreg x:(MOVWload [off] {sym} ptr mem))
+ // cond: x.Uses == 1 && clobber(x)
+ // result: @x.Block (MOVWload <v.Type> [off] {sym} ptr mem)
+ for {
+ x := v.Args[0]
+ if x.Op != OpS390XMOVWload {
+ break
+ }
+ off := x.AuxInt
+ sym := x.Aux
+ _ = x.Args[1]
+ ptr := x.Args[0]
+ mem := x.Args[1]
+ if !(x.Uses == 1 && clobber(x)) {
+ break
+ }
+ b = x.Block
+ v0 := b.NewValue0(v.Pos, OpS390XMOVWload, v.Type)
+ v.reset(OpCopy)
+ v.AddArg(v0)
+ v0.AuxInt = off
+ v0.Aux = sym
+ v0.AddArg(ptr)
+ v0.AddArg(mem)
+ return true
+ }
+ // match: (MOVWreg x:(MOVWZloadidx [off] {sym} ptr idx mem))
+ // cond: x.Uses == 1 && clobber(x)
+ // result: @x.Block (MOVWloadidx <v.Type> [off] {sym} ptr idx mem)
+ for {
+ x := v.Args[0]
+ if x.Op != OpS390XMOVWZloadidx {
+ break
+ }
+ off := x.AuxInt
+ sym := x.Aux
+ _ = x.Args[2]
+ ptr := x.Args[0]
+ idx := x.Args[1]
+ mem := x.Args[2]
+ if !(x.Uses == 1 && clobber(x)) {
+ break
+ }
+ b = x.Block
+ v0 := b.NewValue0(v.Pos, OpS390XMOVWloadidx, v.Type)
+ v.reset(OpCopy)
+ v.AddArg(v0)
+ v0.AuxInt = off
+ v0.Aux = sym
+ v0.AddArg(ptr)
+ v0.AddArg(idx)
+ v0.AddArg(mem)
+ return true
+ }
+ // match: (MOVWreg x:(MOVWloadidx [off] {sym} ptr idx mem))
+ // cond: x.Uses == 1 && clobber(x)
+ // result: @x.Block (MOVWloadidx <v.Type> [off] {sym} ptr idx mem)
+ for {
+ x := v.Args[0]
+ if x.Op != OpS390XMOVWloadidx {
+ break
+ }
+ off := x.AuxInt
+ sym := x.Aux
+ _ = x.Args[2]
+ ptr := x.Args[0]
+ idx := x.Args[1]
+ mem := x.Args[2]
+ if !(x.Uses == 1 && clobber(x)) {
+ break
+ }
+ b = x.Block
+ v0 := b.NewValue0(v.Pos, OpS390XMOVWloadidx, v.Type)
+ v.reset(OpCopy)
+ v.AddArg(v0)
+ v0.AuxInt = off
+ v0.Aux = sym
+ v0.AddArg(ptr)
+ v0.AddArg(idx)
+ v0.AddArg(mem)
+ return true
+ }
return false
}
func rewriteValueS390X_OpS390XMOVWstore_0(v *Value) bool {
}
// match: (MOVWstore [off] {sym} (ADD ptr idx) val mem)
// cond: ptr.Op != OpSB
- // result: (MOVWstoreidx [off] {sym} ptr idx val mem)
+ // result: (MOVWstoreidx [off] {sym} ptr idx val mem)
for {
off := v.AuxInt
sym := v.Aux
}
func rewriteValueS390X_OpS390XMOVWstoreidx_0(v *Value) bool {
// match: (MOVWstoreidx [c] {sym} (ADDconst [d] ptr) idx val mem)
- // cond:
- // result: (MOVWstoreidx [c+d] {sym} ptr idx val mem)
+ // cond: is20Bit(c+d)
+ // result: (MOVWstoreidx [c+d] {sym} ptr idx val mem)
for {
c := v.AuxInt
sym := v.Aux
idx := v.Args[1]
val := v.Args[2]
mem := v.Args[3]
+ if !(is20Bit(c + d)) {
+ break
+ }
v.reset(OpS390XMOVWstoreidx)
v.AuxInt = c + d
v.Aux = sym
return true
}
// match: (MOVWstoreidx [c] {sym} idx (ADDconst [d] ptr) val mem)
- // cond:
- // result: (MOVWstoreidx [c+d] {sym} ptr idx val mem)
+ // cond: is20Bit(c+d)
+ // result: (MOVWstoreidx [c+d] {sym} ptr idx val mem)
for {
c := v.AuxInt
sym := v.Aux
ptr := v_1.Args[0]
val := v.Args[2]
mem := v.Args[3]
+ if !(is20Bit(c + d)) {
+ break
+ }
v.reset(OpS390XMOVWstoreidx)
v.AuxInt = c + d
v.Aux = sym
return true
}
// match: (MOVWstoreidx [c] {sym} ptr (ADDconst [d] idx) val mem)
- // cond:
- // result: (MOVWstoreidx [c+d] {sym} ptr idx val mem)
+ // cond: is20Bit(c+d)
+ // result: (MOVWstoreidx [c+d] {sym} ptr idx val mem)
for {
c := v.AuxInt
sym := v.Aux
idx := v_1.Args[0]
val := v.Args[2]
mem := v.Args[3]
+ if !(is20Bit(c + d)) {
+ break
+ }
v.reset(OpS390XMOVWstoreidx)
v.AuxInt = c + d
v.Aux = sym
return true
}
// match: (MOVWstoreidx [c] {sym} (ADDconst [d] idx) ptr val mem)
- // cond:
- // result: (MOVWstoreidx [c+d] {sym} ptr idx val mem)
+ // cond: is20Bit(c+d)
+ // result: (MOVWstoreidx [c+d] {sym} ptr idx val mem)
for {
c := v.AuxInt
sym := v.Aux
ptr := v.Args[1]
val := v.Args[2]
mem := v.Args[3]
+ if !(is20Bit(c + d)) {
+ break
+ }
v.reset(OpS390XMOVWstoreidx)
v.AuxInt = c + d
v.Aux = sym