(MNEG x (MOVDconst [c])) && isPowerOfTwo(c) -> (NEG (SLLconst <x.Type> [log2(c)] x))
(MNEG x (MOVDconst [c])) && isPowerOfTwo(c-1) && c >= 3 -> (NEG (ADDshiftLL <x.Type> x x [log2(c-1)]))
(MNEG x (MOVDconst [c])) && isPowerOfTwo(c+1) && c >= 7 -> (NEG (ADDshiftLL <x.Type> (NEG <x.Type> x) x [log2(c+1)]))
-(MNEG x (MOVDconst [c])) && c%3 == 0 && isPowerOfTwo(c/3) -> (NEG (SLLconst <x.Type> [log2(c/3)] (ADDshiftLL <x.Type> x x [1])))
+(MNEG x (MOVDconst [c])) && c%3 == 0 && isPowerOfTwo(c/3) -> (SLLconst <x.Type> [log2(c/3)] (SUBshiftLL <x.Type> x x [2]))
(MNEG x (MOVDconst [c])) && c%5 == 0 && isPowerOfTwo(c/5) -> (NEG (SLLconst <x.Type> [log2(c/5)] (ADDshiftLL <x.Type> x x [2])))
-(MNEG x (MOVDconst [c])) && c%7 == 0 && isPowerOfTwo(c/7) -> (NEG (SLLconst <x.Type> [log2(c/7)] (ADDshiftLL <x.Type> (NEG <x.Type> x) x [3])))
+(MNEG x (MOVDconst [c])) && c%7 == 0 && isPowerOfTwo(c/7) -> (SLLconst <x.Type> [log2(c/7)] (SUBshiftLL <x.Type> x x [3]))
(MNEG x (MOVDconst [c])) && c%9 == 0 && isPowerOfTwo(c/9) -> (NEG (SLLconst <x.Type> [log2(c/9)] (ADDshiftLL <x.Type> x x [3])))
(MNEGW x (MOVDconst [c])) && int32(c)==-1 -> x
(MNEGW x (MOVDconst [c])) && isPowerOfTwo(c) -> (NEG (SLLconst <x.Type> [log2(c)] x))
(MNEGW x (MOVDconst [c])) && isPowerOfTwo(c-1) && int32(c) >= 3 -> (NEG (ADDshiftLL <x.Type> x x [log2(c-1)]))
(MNEGW x (MOVDconst [c])) && isPowerOfTwo(c+1) && int32(c) >= 7 -> (NEG (ADDshiftLL <x.Type> (NEG <x.Type> x) x [log2(c+1)]))
-(MNEGW x (MOVDconst [c])) && c%3 == 0 && isPowerOfTwo(c/3) && is32Bit(c) -> (NEG (SLLconst <x.Type> [log2(c/3)] (ADDshiftLL <x.Type> x x [1])))
+(MNEGW x (MOVDconst [c])) && c%3 == 0 && isPowerOfTwo(c/3) && is32Bit(c) -> (SLLconst <x.Type> [log2(c/3)] (SUBshiftLL <x.Type> x x [2]))
(MNEGW x (MOVDconst [c])) && c%5 == 0 && isPowerOfTwo(c/5) && is32Bit(c) -> (NEG (SLLconst <x.Type> [log2(c/5)] (ADDshiftLL <x.Type> x x [2])))
-(MNEGW x (MOVDconst [c])) && c%7 == 0 && isPowerOfTwo(c/7) && is32Bit(c) -> (NEG (SLLconst <x.Type> [log2(c/7)] (ADDshiftLL <x.Type> (NEG <x.Type> x) x [3])))
+(MNEGW x (MOVDconst [c])) && c%7 == 0 && isPowerOfTwo(c/7) && is32Bit(c) -> (SLLconst <x.Type> [log2(c/7)] (SUBshiftLL <x.Type> x x [3]))
(MNEGW x (MOVDconst [c])) && c%9 == 0 && isPowerOfTwo(c/9) && is32Bit(c) -> (NEG (SLLconst <x.Type> [log2(c/9)] (ADDshiftLL <x.Type> x x [3])))
// div by constant
(FSUBS a (FNMULS x y)) -> (FMADDS a x y)
(FSUBD a (FNMULD x y)) -> (FMADDD a x y)
(FSUBS (FNMULS x y) a) -> (FNMADDS a x y)
-(FSUBD (FNMULD x y) a) -> (FNMADDD a x y)
+(FSUBD (FNMULD x y) a) -> (FNMADDD a x y)
\ No newline at end of file
}
// match: (MNEG x (MOVDconst [c]))
// cond: c%3 == 0 && isPowerOfTwo(c/3)
- // result: (NEG (SLLconst <x.Type> [log2(c/3)] (ADDshiftLL <x.Type> x x [1])))
+ // result: (SLLconst <x.Type> [log2(c/3)] (SUBshiftLL <x.Type> x x [2]))
for {
_ = v.Args[1]
x := v.Args[0]
if !(c%3 == 0 && isPowerOfTwo(c/3)) {
break
}
- v.reset(OpARM64NEG)
- v0 := b.NewValue0(v.Pos, OpARM64SLLconst, x.Type)
- v0.AuxInt = log2(c / 3)
- v1 := b.NewValue0(v.Pos, OpARM64ADDshiftLL, x.Type)
- v1.AuxInt = 1
- v1.AddArg(x)
- v1.AddArg(x)
- v0.AddArg(v1)
+ v.reset(OpARM64SLLconst)
+ v.Type = x.Type
+ v.AuxInt = log2(c / 3)
+ v0 := b.NewValue0(v.Pos, OpARM64SUBshiftLL, x.Type)
+ v0.AuxInt = 2
+ v0.AddArg(x)
+ v0.AddArg(x)
v.AddArg(v0)
return true
}
// match: (MNEG (MOVDconst [c]) x)
// cond: c%3 == 0 && isPowerOfTwo(c/3)
- // result: (NEG (SLLconst <x.Type> [log2(c/3)] (ADDshiftLL <x.Type> x x [1])))
+ // result: (SLLconst <x.Type> [log2(c/3)] (SUBshiftLL <x.Type> x x [2]))
for {
_ = v.Args[1]
v_0 := v.Args[0]
if !(c%3 == 0 && isPowerOfTwo(c/3)) {
break
}
- v.reset(OpARM64NEG)
- v0 := b.NewValue0(v.Pos, OpARM64SLLconst, x.Type)
- v0.AuxInt = log2(c / 3)
- v1 := b.NewValue0(v.Pos, OpARM64ADDshiftLL, x.Type)
- v1.AuxInt = 1
- v1.AddArg(x)
- v1.AddArg(x)
- v0.AddArg(v1)
+ v.reset(OpARM64SLLconst)
+ v.Type = x.Type
+ v.AuxInt = log2(c / 3)
+ v0 := b.NewValue0(v.Pos, OpARM64SUBshiftLL, x.Type)
+ v0.AuxInt = 2
+ v0.AddArg(x)
+ v0.AddArg(x)
v.AddArg(v0)
return true
}
}
// match: (MNEG x (MOVDconst [c]))
// cond: c%7 == 0 && isPowerOfTwo(c/7)
- // result: (NEG (SLLconst <x.Type> [log2(c/7)] (ADDshiftLL <x.Type> (NEG <x.Type> x) x [3])))
+ // result: (SLLconst <x.Type> [log2(c/7)] (SUBshiftLL <x.Type> x x [3]))
for {
_ = v.Args[1]
x := v.Args[0]
if !(c%7 == 0 && isPowerOfTwo(c/7)) {
break
}
- v.reset(OpARM64NEG)
- v0 := b.NewValue0(v.Pos, OpARM64SLLconst, x.Type)
- v0.AuxInt = log2(c / 7)
- v1 := b.NewValue0(v.Pos, OpARM64ADDshiftLL, x.Type)
- v1.AuxInt = 3
- v2 := b.NewValue0(v.Pos, OpARM64NEG, x.Type)
- v2.AddArg(x)
- v1.AddArg(v2)
- v1.AddArg(x)
- v0.AddArg(v1)
+ v.reset(OpARM64SLLconst)
+ v.Type = x.Type
+ v.AuxInt = log2(c / 7)
+ v0 := b.NewValue0(v.Pos, OpARM64SUBshiftLL, x.Type)
+ v0.AuxInt = 3
+ v0.AddArg(x)
+ v0.AddArg(x)
v.AddArg(v0)
return true
}
// match: (MNEG (MOVDconst [c]) x)
// cond: c%7 == 0 && isPowerOfTwo(c/7)
- // result: (NEG (SLLconst <x.Type> [log2(c/7)] (ADDshiftLL <x.Type> (NEG <x.Type> x) x [3])))
+ // result: (SLLconst <x.Type> [log2(c/7)] (SUBshiftLL <x.Type> x x [3]))
for {
_ = v.Args[1]
v_0 := v.Args[0]
if !(c%7 == 0 && isPowerOfTwo(c/7)) {
break
}
- v.reset(OpARM64NEG)
- v0 := b.NewValue0(v.Pos, OpARM64SLLconst, x.Type)
- v0.AuxInt = log2(c / 7)
- v1 := b.NewValue0(v.Pos, OpARM64ADDshiftLL, x.Type)
- v1.AuxInt = 3
- v2 := b.NewValue0(v.Pos, OpARM64NEG, x.Type)
- v2.AddArg(x)
- v1.AddArg(v2)
- v1.AddArg(x)
- v0.AddArg(v1)
+ v.reset(OpARM64SLLconst)
+ v.Type = x.Type
+ v.AuxInt = log2(c / 7)
+ v0 := b.NewValue0(v.Pos, OpARM64SUBshiftLL, x.Type)
+ v0.AuxInt = 3
+ v0.AddArg(x)
+ v0.AddArg(x)
v.AddArg(v0)
return true
}
}
// match: (MNEGW x (MOVDconst [c]))
// cond: c%3 == 0 && isPowerOfTwo(c/3) && is32Bit(c)
- // result: (NEG (SLLconst <x.Type> [log2(c/3)] (ADDshiftLL <x.Type> x x [1])))
+ // result: (SLLconst <x.Type> [log2(c/3)] (SUBshiftLL <x.Type> x x [2]))
for {
_ = v.Args[1]
x := v.Args[0]
if !(c%3 == 0 && isPowerOfTwo(c/3) && is32Bit(c)) {
break
}
- v.reset(OpARM64NEG)
- v0 := b.NewValue0(v.Pos, OpARM64SLLconst, x.Type)
- v0.AuxInt = log2(c / 3)
- v1 := b.NewValue0(v.Pos, OpARM64ADDshiftLL, x.Type)
- v1.AuxInt = 1
- v1.AddArg(x)
- v1.AddArg(x)
- v0.AddArg(v1)
+ v.reset(OpARM64SLLconst)
+ v.Type = x.Type
+ v.AuxInt = log2(c / 3)
+ v0 := b.NewValue0(v.Pos, OpARM64SUBshiftLL, x.Type)
+ v0.AuxInt = 2
+ v0.AddArg(x)
+ v0.AddArg(x)
v.AddArg(v0)
return true
}
// match: (MNEGW (MOVDconst [c]) x)
// cond: c%3 == 0 && isPowerOfTwo(c/3) && is32Bit(c)
- // result: (NEG (SLLconst <x.Type> [log2(c/3)] (ADDshiftLL <x.Type> x x [1])))
+ // result: (SLLconst <x.Type> [log2(c/3)] (SUBshiftLL <x.Type> x x [2]))
for {
_ = v.Args[1]
v_0 := v.Args[0]
if !(c%3 == 0 && isPowerOfTwo(c/3) && is32Bit(c)) {
break
}
- v.reset(OpARM64NEG)
- v0 := b.NewValue0(v.Pos, OpARM64SLLconst, x.Type)
- v0.AuxInt = log2(c / 3)
- v1 := b.NewValue0(v.Pos, OpARM64ADDshiftLL, x.Type)
- v1.AuxInt = 1
- v1.AddArg(x)
- v1.AddArg(x)
- v0.AddArg(v1)
+ v.reset(OpARM64SLLconst)
+ v.Type = x.Type
+ v.AuxInt = log2(c / 3)
+ v0 := b.NewValue0(v.Pos, OpARM64SUBshiftLL, x.Type)
+ v0.AuxInt = 2
+ v0.AddArg(x)
+ v0.AddArg(x)
v.AddArg(v0)
return true
}
}
// match: (MNEGW x (MOVDconst [c]))
// cond: c%7 == 0 && isPowerOfTwo(c/7) && is32Bit(c)
- // result: (NEG (SLLconst <x.Type> [log2(c/7)] (ADDshiftLL <x.Type> (NEG <x.Type> x) x [3])))
+ // result: (SLLconst <x.Type> [log2(c/7)] (SUBshiftLL <x.Type> x x [3]))
for {
_ = v.Args[1]
x := v.Args[0]
if !(c%7 == 0 && isPowerOfTwo(c/7) && is32Bit(c)) {
break
}
- v.reset(OpARM64NEG)
- v0 := b.NewValue0(v.Pos, OpARM64SLLconst, x.Type)
- v0.AuxInt = log2(c / 7)
- v1 := b.NewValue0(v.Pos, OpARM64ADDshiftLL, x.Type)
- v1.AuxInt = 3
- v2 := b.NewValue0(v.Pos, OpARM64NEG, x.Type)
- v2.AddArg(x)
- v1.AddArg(v2)
- v1.AddArg(x)
- v0.AddArg(v1)
+ v.reset(OpARM64SLLconst)
+ v.Type = x.Type
+ v.AuxInt = log2(c / 7)
+ v0 := b.NewValue0(v.Pos, OpARM64SUBshiftLL, x.Type)
+ v0.AuxInt = 3
+ v0.AddArg(x)
+ v0.AddArg(x)
v.AddArg(v0)
return true
}
// match: (MNEGW (MOVDconst [c]) x)
// cond: c%7 == 0 && isPowerOfTwo(c/7) && is32Bit(c)
- // result: (NEG (SLLconst <x.Type> [log2(c/7)] (ADDshiftLL <x.Type> (NEG <x.Type> x) x [3])))
+ // result: (SLLconst <x.Type> [log2(c/7)] (SUBshiftLL <x.Type> x x [3]))
for {
_ = v.Args[1]
v_0 := v.Args[0]
if !(c%7 == 0 && isPowerOfTwo(c/7) && is32Bit(c)) {
break
}
- v.reset(OpARM64NEG)
- v0 := b.NewValue0(v.Pos, OpARM64SLLconst, x.Type)
- v0.AuxInt = log2(c / 7)
- v1 := b.NewValue0(v.Pos, OpARM64ADDshiftLL, x.Type)
- v1.AuxInt = 3
- v2 := b.NewValue0(v.Pos, OpARM64NEG, x.Type)
- v2.AddArg(x)
- v1.AddArg(v2)
- v1.AddArg(x)
- v0.AddArg(v1)
+ v.reset(OpARM64SLLconst)
+ v.Type = x.Type
+ v.AuxInt = log2(c / 7)
+ v0 := b.NewValue0(v.Pos, OpARM64SUBshiftLL, x.Type)
+ v0.AuxInt = 3
+ v0.AddArg(x)
+ v0.AddArg(x)
v.AddArg(v0)
return true
}
}
}
return false
-}
+}
\ No newline at end of file