]> Cypherpunks repositories - gostls13.git/commitdiff
cmd/asm: add rev64 instruction on ARM64
authorFangming.Fang <fangming.fang@arm.com>
Wed, 18 Apr 2018 02:55:09 +0000 (02:55 +0000)
committerBrad Fitzpatrick <bradfitz@golang.org>
Thu, 19 Apr 2018 03:00:36 +0000 (03:00 +0000)
This change provides VREV64 instruction for AES-GCM implementation.

Change-Id: Icdf278862b03556388586f459964b025c47b8c19
Reviewed-on: https://go-review.googlesource.com/107696
Reviewed-by: Brad Fitzpatrick <bradfitz@golang.org>
src/cmd/asm/internal/asm/testdata/arm64.s
src/cmd/asm/internal/asm/testdata/arm64error.s
src/cmd/internal/obj/arm64/a.out.go
src/cmd/internal/obj/arm64/anames.go
src/cmd/internal/obj/arm64/asm7.go
src/cmd/internal/obj/arm64/doc.go

index b5d44ebe50f62b356b30f84ea0dbf2211de5be57..1dc437830fa962e169adce4dba00fe33fec71995 100644 (file)
@@ -309,6 +309,8 @@ TEXT        foo(SB), DUPOK|NOSPLIT, $-8
        VMOV    V8.B[0], V12.B[1]     // 0c05036e
        VMOV    V8.B[7], V4.B[8]      // 043d116e
        VREV32  V5.B16, V5.B16        // a508206e
+       VREV64  V2.S2, V3.S2          // 4308a00e
+       VREV64  V2.S4, V3.S4          // 4308a04e
        VDUP    V19.S[0], V17.S4      // 7106044e
 //
 // B/BL
index 6f27af2f8994e41e7d0b8a4e2c84a285aa7bb1e5..7de93849320cd12b4f5955fa1ed0a86bbd331b45 100644 (file)
@@ -81,4 +81,6 @@ TEXT errors(SB),$0
        VLD1.P  (R8)(R9<<2), [V2.B16]                            // ERROR "invalid extended register"
        VST1.P  [V1.B16], (R8)(R9.UXTW)                          // ERROR "invalid extended register"
        VST1.P  [V1.B16], (R8)(R9<<1)                            // ERROR "invalid extended register"
+       VREV64  V1.H4, V2.H8                                     // ERROR "invalid arrangement"
+       VREV64  V1.D1, V2.D1                                     // ERROR "invalid arrangement"
        RET
index 70cc522a463f1b9712e598b3f837ecd5cd4a2e3d..44a912e33f3e8f8a1e7bb2ddff260c43fb7dd065 100644 (file)
@@ -881,6 +881,7 @@ const (
        AVLD1
        AVORR
        AVREV32
+       AVREV64
        AVST1
        AVDUP
        AVMOVS
index cc92d86a4a12a7df3e047920637f7a79cab476c8..88300fc8cd657385220544771bc2e15f22dc194d 100644 (file)
@@ -383,6 +383,7 @@ var Anames = []string{
        "VLD1",
        "VORR",
        "VREV32",
+       "VREV64",
        "VST1",
        "VDUP",
        "VMOVS",
index 66163d789e9a4893f1ba025f258e45fb5444b36f..8e0f6f96f88ab1e982c915a2e5fc68d325f3a35d 100644 (file)
@@ -2387,6 +2387,7 @@ func buildop(ctxt *obj.Link) {
 
                case AVREV32:
                        oprangeset(AVRBIT, t)
+                       oprangeset(AVREV64, t)
 
                case ASHA1H,
                        AVCNT,
@@ -3964,8 +3965,7 @@ func (c *ctxt7) asmout(p *obj.Prog, o *Optab, out []uint32) {
                rf := int((p.From.Reg) & 31)
                rt := int((p.To.Reg) & 31)
 
-               Q := 0
-               size := 0
+               var Q, size uint32
                switch af {
                case ARNG_8B:
                        Q = 0
@@ -3979,6 +3979,12 @@ func (c *ctxt7) asmout(p *obj.Prog, o *Optab, out []uint32) {
                case ARNG_8H:
                        Q = 1
                        size = 1
+               case ARNG_2S:
+                       Q = 0
+                       size = 2
+               case ARNG_4S:
+                       Q = 1
+                       size = 2
                default:
                        c.ctxt.Diag("invalid arrangement: %v\n", p)
                }
@@ -3987,6 +3993,10 @@ func (c *ctxt7) asmout(p *obj.Prog, o *Optab, out []uint32) {
                        c.ctxt.Diag("invalid arrangement: %v", p)
                }
 
+               if p.As == AVREV32 && (af == ARNG_2S || af == ARNG_4S) {
+                       c.ctxt.Diag("invalid arrangement: %v", p)
+               }
+
                if p.As == AVMOV {
                        o1 |= uint32(rf&31) << 16
                }
@@ -3995,7 +4005,7 @@ func (c *ctxt7) asmout(p *obj.Prog, o *Optab, out []uint32) {
                        size = 1
                }
 
-               o1 |= (uint32(Q&1) << 30) | (uint32(size&3) << 22) | (uint32(rf&31) << 5) | uint32(rt&31)
+               o1 |= (Q&1) << 30 | (size&3) << 22 | uint32(rf&31) << 5 | uint32(rt&31)
 
        case 84: /* vst1 [Vt1.<T>, Vt2.<T>, ...], (Rn) */
                r := int(p.To.Reg)
@@ -5073,6 +5083,9 @@ func (c *ctxt7) oprrr(p *obj.Prog, a obj.As) uint32 {
        case AVREV32:
                return 11<<26 | 2<<24 | 1<<21 | 1<<11
 
+       case AVREV64:
+               return 3<<26 | 2<<24 | 1<<21 | 1<<11
+
        case AVMOV:
                return 7<<25 | 5<<21 | 7<<10
 
index 0a7700f8ac469e4631133278f721a67886f7a79e..d06025d21cde6ea166947fb3a049e11de31a9c57 100644 (file)
@@ -258,6 +258,11 @@ Go Assembly for ARM64 Reference Manual
         <T> Is an arrangement specifier and can have the following values:
         B8, B16, H4, H8
 
+    VREV64: Reverse elements in 64-bit words (vector).
+      REV64 <Vn>.<T>, <Vd>.<T>
+        <T> Is an arrangement specifier and can have the following values:
+        B8, B16, H4, H8, S2, S4
+
     VSHL: Shift Left(immediate)
       VSHL     $shift, <Vn>.<T>, <Vd>.<T>
         <T> is an arrangement specifier and can have the following values: